drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <ethdev_driver.h>
  11 #include <ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16 #include <rte_vect.h>
  17
  18 #include "bnxt.h"
  19 #include "bnxt_filter.h"
  20 #include "bnxt_hwrm.h"
  21 #include "bnxt_irq.h"
  22 #include "bnxt_reps.h"
  23 #include "bnxt_ring.h"
  24 #include "bnxt_rxq.h"
  25 #include "bnxt_rxr.h"
  26 #include "bnxt_stats.h"
  27 #include "bnxt_txq.h"
  28 #include "bnxt_txr.h"
  29 #include "bnxt_vnic.h"
  30 #include "hsi_struct_def_dpdk.h"
  31 #include "bnxt_nvm_defs.h"
  32 #include "bnxt_tf_common.h"
  33 #include "ulp_flow_db.h"
  34 #include "rte_pmd_bnxt.h"
  35
  36 #define DRV_MODULE_NAME         "bnxt"
  37 static const char bnxt_version[] =
  38         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  39
  40 /*
  41  * The set of PCI devices this driver supports
  42  */
  43 static const struct rte_pci_id bnxt_pci_id_map[] = {
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  47                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
  87         { .vendor_id = 0, /* sentinel */ },
  88 };
  89
  90 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
  91 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
  92 #define BNXT_DEVARG_REPRESENTOR "representor"
  93 #define BNXT_DEVARG_REP_BASED_PF  "rep-based-pf"
  94 #define BNXT_DEVARG_REP_IS_PF  "rep-is-pf"
  95 #define BNXT_DEVARG_REP_Q_R2F  "rep-q-r2f"
  96 #define BNXT_DEVARG_REP_Q_F2R  "rep-q-f2r"
  97 #define BNXT_DEVARG_REP_FC_R2F  "rep-fc-r2f"
  98 #define BNXT_DEVARG_REP_FC_F2R  "rep-fc-f2r"
  99
 100 static const char *const bnxt_dev_args[] = {
 101         BNXT_DEVARG_REPRESENTOR,
 102         BNXT_DEVARG_FLOW_XSTAT,
 103         BNXT_DEVARG_MAX_NUM_KFLOWS,
 104         BNXT_DEVARG_REP_BASED_PF,
 105         BNXT_DEVARG_REP_IS_PF,
 106         BNXT_DEVARG_REP_Q_R2F,
 107         BNXT_DEVARG_REP_Q_F2R,
 108         BNXT_DEVARG_REP_FC_R2F,
 109         BNXT_DEVARG_REP_FC_F2R,
 110         NULL
 111 };
 112
 113 /*
 114  * flow_xstat == false to disable the feature
 115  * flow_xstat == true to enable the feature
 116  */
 117 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 118
 119 /*
 120  * rep_is_pf == false to indicate VF representor
 121  * rep_is_pf == true to indicate PF representor
 122  */
 123 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)        ((rep_is_pf) > 1)
 124
 125 /*
 126  * rep_based_pf == Physical index of the PF
 127  */
 128 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)  ((rep_based_pf) > 15)
 129 /*
 130  * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
 131  */
 132 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)        ((rep_q_r2f) > 3)
 133
 134 /*
 135  * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
 136  */
 137 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)        ((rep_q_f2r) > 3)
 138
 139 /*
 140  * rep_fc_r2f == Flow control for the representor to endpoint direction
 141  */
 142 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)      ((rep_fc_r2f) > 1)
 143
 144 /*
 145  * rep_fc_f2r == Flow control for the endpoint to representor direction
 146  */
 147 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)      ((rep_fc_f2r) > 1)
 148
 149 int bnxt_cfa_code_dynfield_offset = -1;
 150
 151 /*
 152  * max_num_kflows must be >= 32
 153  * and must be a power-of-2 supported value
 154  * return: 1 -> invalid
 155  *         0 -> valid
 156  */
 157 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 158 {
 159         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 160                 return 1;
 161         return 0;
 162 }
 163
 164 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 165 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 166 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 167 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 168 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 169 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 170 static void bnxt_dev_recover(void *arg);
 171 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 172 static void bnxt_free_rep_info(struct bnxt *bp);
 173
 174 int is_bnxt_in_error(struct bnxt *bp)
 175 {
 176         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 177                 return -EIO;
 178         if (bp->flags & BNXT_FLAG_FW_RESET)
 179                 return -EBUSY;
 180
 181         return 0;
 182 }
 183
 184 /***********************/
 185
 186 /*
 187  * High level utility functions
 188  */
 189
 190 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 191 {
 192         unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
 193                                              BNXT_RSS_TBL_SIZE_P5);
 194
 195         if (!BNXT_CHIP_P5(bp))
 196                 return 1;
 197
 198         return RTE_ALIGN_MUL_CEIL(num_rss_rings,
 199                                   BNXT_RSS_ENTRIES_PER_CTX_P5) /
 200                                   BNXT_RSS_ENTRIES_PER_CTX_P5;
 201 }
 202
 203 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 204 {
 205         if (!BNXT_CHIP_P5(bp))
 206                 return HW_HASH_INDEX_SIZE;
 207
 208         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
 209 }
 210
 211 static void bnxt_free_parent_info(struct bnxt *bp)
 212 {
 213         rte_free(bp->parent);
 214         bp->parent = NULL;
 215 }
 216
 217 static void bnxt_free_pf_info(struct bnxt *bp)
 218 {
 219         rte_free(bp->pf);
 220         bp->pf = NULL;
 221 }
 222
 223 static void bnxt_free_link_info(struct bnxt *bp)
 224 {
 225         rte_free(bp->link_info);
 226         bp->link_info = NULL;
 227 }
 228
 229 static void bnxt_free_leds_info(struct bnxt *bp)
 230 {
 231         if (BNXT_VF(bp))
 232                 return;
 233
 234         rte_free(bp->leds);
 235         bp->leds = NULL;
 236 }
 237
 238 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 239 {
 240         rte_free(bp->flow_stat);
 241         bp->flow_stat = NULL;
 242 }
 243
 244 static void bnxt_free_cos_queues(struct bnxt *bp)
 245 {
 246         rte_free(bp->rx_cos_queue);
 247         bp->rx_cos_queue = NULL;
 248         rte_free(bp->tx_cos_queue);
 249         bp->tx_cos_queue = NULL;
 250 }
 251
 252 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 253 {
 254         bnxt_free_filter_mem(bp);
 255         bnxt_free_vnic_attributes(bp);
 256         bnxt_free_vnic_mem(bp);
 257
 258         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 259          * If the number of rings change across fw update,
 260          * we don't have much choice except to warn the user.
 261          */
 262         if (!reconfig) {
 263                 bnxt_free_stats(bp);
 264                 bnxt_free_tx_rings(bp);
 265                 bnxt_free_rx_rings(bp);
 266         }
 267         bnxt_free_async_cp_ring(bp);
 268         bnxt_free_rxtx_nq_ring(bp);
 269
 270         rte_free(bp->grp_info);
 271         bp->grp_info = NULL;
 272 }
 273
 274 static int bnxt_alloc_parent_info(struct bnxt *bp)
 275 {
 276         bp->parent = rte_zmalloc("bnxt_parent_info",
 277                                  sizeof(struct bnxt_parent_info), 0);
 278         if (bp->parent == NULL)
 279                 return -ENOMEM;
 280
 281         return 0;
 282 }
 283
 284 static int bnxt_alloc_pf_info(struct bnxt *bp)
 285 {
 286         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 287         if (bp->pf == NULL)
 288                 return -ENOMEM;
 289
 290         return 0;
 291 }
 292
 293 static int bnxt_alloc_link_info(struct bnxt *bp)
 294 {
 295         bp->link_info =
 296                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 297         if (bp->link_info == NULL)
 298                 return -ENOMEM;
 299
 300         return 0;
 301 }
 302
 303 static int bnxt_alloc_leds_info(struct bnxt *bp)
 304 {
 305         if (BNXT_VF(bp))
 306                 return 0;
 307
 308         bp->leds = rte_zmalloc("bnxt_leds",
 309                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 310                                0);
 311         if (bp->leds == NULL)
 312                 return -ENOMEM;
 313
 314         return 0;
 315 }
 316
 317 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 318 {
 319         bp->rx_cos_queue =
 320                 rte_zmalloc("bnxt_rx_cosq",
 321                             BNXT_COS_QUEUE_COUNT *
 322                             sizeof(struct bnxt_cos_queue_info),
 323                             0);
 324         if (bp->rx_cos_queue == NULL)
 325                 return -ENOMEM;
 326
 327         bp->tx_cos_queue =
 328                 rte_zmalloc("bnxt_tx_cosq",
 329                             BNXT_COS_QUEUE_COUNT *
 330                             sizeof(struct bnxt_cos_queue_info),
 331                             0);
 332         if (bp->tx_cos_queue == NULL)
 333                 return -ENOMEM;
 334
 335         return 0;
 336 }
 337
 338 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 339 {
 340         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 341                                     sizeof(struct bnxt_flow_stat_info), 0);
 342         if (bp->flow_stat == NULL)
 343                 return -ENOMEM;
 344
 345         return 0;
 346 }
 347
 348 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 349 {
 350         int rc;
 351
 352         rc = bnxt_alloc_ring_grps(bp);
 353         if (rc)
 354                 goto alloc_mem_err;
 355
 356         rc = bnxt_alloc_async_ring_struct(bp);
 357         if (rc)
 358                 goto alloc_mem_err;
 359
 360         rc = bnxt_alloc_vnic_mem(bp);
 361         if (rc)
 362                 goto alloc_mem_err;
 363
 364         rc = bnxt_alloc_vnic_attributes(bp);
 365         if (rc)
 366                 goto alloc_mem_err;
 367
 368         rc = bnxt_alloc_filter_mem(bp);
 369         if (rc)
 370                 goto alloc_mem_err;
 371
 372         rc = bnxt_alloc_async_cp_ring(bp);
 373         if (rc)
 374                 goto alloc_mem_err;
 375
 376         rc = bnxt_alloc_rxtx_nq_ring(bp);
 377         if (rc)
 378                 goto alloc_mem_err;
 379
 380         if (BNXT_FLOW_XSTATS_EN(bp)) {
 381                 rc = bnxt_alloc_flow_stats_info(bp);
 382                 if (rc)
 383                         goto alloc_mem_err;
 384         }
 385
 386         return 0;
 387
 388 alloc_mem_err:
 389         bnxt_free_mem(bp, reconfig);
 390         return rc;
 391 }
 392
 393 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 394 {
 395         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 396         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 397         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 398         struct bnxt_rx_queue *rxq;
 399         unsigned int j;
 400         int rc;
 401
 402         rc = bnxt_vnic_grp_alloc(bp, vnic);
 403         if (rc)
 404                 goto err_out;
 405
 406         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 407                     vnic_id, vnic, vnic->fw_grp_ids);
 408
 409         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 410         if (rc)
 411                 goto err_out;
 412
 413         /* Alloc RSS context only if RSS mode is enabled */
 414         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 415                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 416
 417                 /* RSS table size in Thor is 512.
 418                  * Cap max Rx rings to same value
 419                  */
 420                 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
 421                         PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
 422                                     bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
 423                         goto err_out;
 424                 }
 425
 426                 rc = 0;
 427                 for (j = 0; j < nr_ctxs; j++) {
 428                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 429                         if (rc)
 430                                 break;
 431                 }
 432                 if (rc) {
 433                         PMD_DRV_LOG(ERR,
 434                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 435                                     vnic_id, j, rc);
 436                         goto err_out;
 437                 }
 438                 vnic->num_lb_ctxts = nr_ctxs;
 439         }
 440
 441         /*
 442          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 443          * setting is not available at this time, it will not be
 444          * configured correctly in the CFA.
 445          */
 446         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 447                 vnic->vlan_strip = true;
 448         else
 449                 vnic->vlan_strip = false;
 450
 451         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 452         if (rc)
 453                 goto err_out;
 454
 455         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 456         if (rc)
 457                 goto err_out;
 458
 459         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 460                 rxq = bp->eth_dev->data->rx_queues[j];
 461
 462                 PMD_DRV_LOG(DEBUG,
 463                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 464                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 465
 466                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 467                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 468                 else
 469                         vnic->rx_queue_cnt++;
 470         }
 471
 472         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 473
 474         rc = bnxt_vnic_rss_configure(bp, vnic);
 475         if (rc)
 476                 goto err_out;
 477
 478         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 479
 480         rc = bnxt_hwrm_vnic_tpa_cfg(bp, vnic,
 481                                     (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) ?
 482                                     true : false);
 483         if (rc)
 484                 goto err_out;
 485
 486         return 0;
 487 err_out:
 488         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 489                     vnic_id, rc);
 490         return rc;
 491 }
 492
 493 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 494 {
 495         int rc = 0;
 496
 497         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 498                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 499         if (rc)
 500                 return rc;
 501
 502         PMD_DRV_LOG(DEBUG,
 503                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 504                     " rx_fc_in_tbl.ctx_id = %d\n",
 505                     bp->flow_stat->rx_fc_in_tbl.va,
 506                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 507                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 508
 509         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 510                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 511         if (rc)
 512                 return rc;
 513
 514         PMD_DRV_LOG(DEBUG,
 515                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 516                     " rx_fc_out_tbl.ctx_id = %d\n",
 517                     bp->flow_stat->rx_fc_out_tbl.va,
 518                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 519                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 520
 521         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 522                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 523         if (rc)
 524                 return rc;
 525
 526         PMD_DRV_LOG(DEBUG,
 527                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 528                     " tx_fc_in_tbl.ctx_id = %d\n",
 529                     bp->flow_stat->tx_fc_in_tbl.va,
 530                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 531                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 532
 533         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 534                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 535         if (rc)
 536                 return rc;
 537
 538         PMD_DRV_LOG(DEBUG,
 539                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 540                     " tx_fc_out_tbl.ctx_id = %d\n",
 541                     bp->flow_stat->tx_fc_out_tbl.va,
 542                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 543                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 544
 545         memset(bp->flow_stat->rx_fc_out_tbl.va,
 546                0,
 547                bp->flow_stat->rx_fc_out_tbl.size);
 548         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 549                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 550                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 551                                        bp->flow_stat->max_fc,
 552                                        true);
 553         if (rc)
 554                 return rc;
 555
 556         memset(bp->flow_stat->tx_fc_out_tbl.va,
 557                0,
 558                bp->flow_stat->tx_fc_out_tbl.size);
 559         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 560                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 561                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 562                                        bp->flow_stat->max_fc,
 563                                        true);
 564
 565         return rc;
 566 }
 567
 568 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 569                                   struct bnxt_ctx_mem_buf_info *ctx)
 570 {
 571         if (!ctx)
 572                 return -EINVAL;
 573
 574         ctx->va = rte_zmalloc(type, size, 0);
 575         if (ctx->va == NULL)
 576                 return -ENOMEM;
 577         rte_mem_lock_page(ctx->va);
 578         ctx->size = size;
 579         ctx->dma = rte_mem_virt2iova(ctx->va);
 580         if (ctx->dma == RTE_BAD_IOVA)
 581                 return -ENOMEM;
 582
 583         return 0;
 584 }
 585
 586 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 587 {
 588         struct rte_pci_device *pdev = bp->pdev;
 589         char type[RTE_MEMZONE_NAMESIZE];
 590         uint16_t max_fc;
 591         int rc = 0;
 592
 593         max_fc = bp->flow_stat->max_fc;
 594
 595         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 596                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 597         /* 4 bytes for each counter-id */
 598         rc = bnxt_alloc_ctx_mem_buf(type,
 599                                     max_fc * 4,
 600                                     &bp->flow_stat->rx_fc_in_tbl);
 601         if (rc)
 602                 return rc;
 603
 604         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 605                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 606         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 607         rc = bnxt_alloc_ctx_mem_buf(type,
 608                                     max_fc * 16,
 609                                     &bp->flow_stat->rx_fc_out_tbl);
 610         if (rc)
 611                 return rc;
 612
 613         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 614                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 615         /* 4 bytes for each counter-id */
 616         rc = bnxt_alloc_ctx_mem_buf(type,
 617                                     max_fc * 4,
 618                                     &bp->flow_stat->tx_fc_in_tbl);
 619         if (rc)
 620                 return rc;
 621
 622         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 623                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 624         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 625         rc = bnxt_alloc_ctx_mem_buf(type,
 626                                     max_fc * 16,
 627                                     &bp->flow_stat->tx_fc_out_tbl);
 628         if (rc)
 629                 return rc;
 630
 631         rc = bnxt_register_fc_ctx_mem(bp);
 632
 633         return rc;
 634 }
 635
 636 static int bnxt_init_ctx_mem(struct bnxt *bp)
 637 {
 638         int rc = 0;
 639
 640         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 641             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 642             !BNXT_FLOW_XSTATS_EN(bp))
 643                 return 0;
 644
 645         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 646         if (rc)
 647                 return rc;
 648
 649         rc = bnxt_init_fc_ctx_mem(bp);
 650
 651         return rc;
 652 }
 653
 654 static int bnxt_update_phy_setting(struct bnxt *bp)
 655 {
 656         struct rte_eth_link new;
 657         int rc;
 658
 659         rc = bnxt_get_hwrm_link_config(bp, &new);
 660         if (rc) {
 661                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 662                 return rc;
 663         }
 664
 665         /*
 666          * On BCM957508-N2100 adapters, FW will not allow any user other
 667          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 668          * always returns link up. Force phy update always in that case.
 669          */
 670         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 671                 rc = bnxt_set_hwrm_link_config(bp, true);
 672                 if (rc) {
 673                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 674                         return rc;
 675                 }
 676         }
 677
 678         return rc;
 679 }
 680
 681 static void bnxt_free_prev_ring_stats(struct bnxt *bp)
 682 {
 683         rte_free(bp->prev_rx_ring_stats);
 684         rte_free(bp->prev_tx_ring_stats);
 685
 686         bp->prev_rx_ring_stats = NULL;
 687         bp->prev_tx_ring_stats = NULL;
 688 }
 689
 690 static int bnxt_alloc_prev_ring_stats(struct bnxt *bp)
 691 {
 692         bp->prev_rx_ring_stats =  rte_zmalloc("bnxt_prev_rx_ring_stats",
 693                                               sizeof(struct bnxt_ring_stats) *
 694                                               bp->rx_cp_nr_rings,
 695                                               0);
 696         if (bp->prev_rx_ring_stats == NULL)
 697                 return -ENOMEM;
 698
 699         bp->prev_tx_ring_stats = rte_zmalloc("bnxt_prev_tx_ring_stats",
 700                                              sizeof(struct bnxt_ring_stats) *
 701                                              bp->tx_cp_nr_rings,
 702                                              0);
 703         if (bp->prev_tx_ring_stats == NULL)
 704                 goto error;
 705
 706         return 0;
 707
 708 error:
 709         bnxt_free_prev_ring_stats(bp);
 710         return -ENOMEM;
 711 }
 712
 713 static int bnxt_start_nic(struct bnxt *bp)
 714 {
 715         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 716         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 717         uint32_t intr_vector = 0;
 718         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 719         uint32_t vec = BNXT_MISC_VEC_ID;
 720         unsigned int i, j;
 721         int rc;
 722
 723         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 724                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 725                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 726                 bp->flags |= BNXT_FLAG_JUMBO;
 727         } else {
 728                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 729                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 730                 bp->flags &= ~BNXT_FLAG_JUMBO;
 731         }
 732
 733         /* THOR does not support ring groups.
 734          * But we will use the array to save RSS context IDs.
 735          */
 736         if (BNXT_CHIP_P5(bp))
 737                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
 738
 739         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 740         if (rc) {
 741                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 742                 goto err_out;
 743         }
 744
 745         rc = bnxt_alloc_hwrm_rings(bp);
 746         if (rc) {
 747                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 748                 goto err_out;
 749         }
 750
 751         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 752         if (rc) {
 753                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 754                 goto err_out;
 755         }
 756
 757         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 758                 goto skip_cosq_cfg;
 759
 760         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 761                 if (bp->rx_cos_queue[i].id != 0xff) {
 762                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 763
 764                         if (!vnic) {
 765                                 PMD_DRV_LOG(ERR,
 766                                             "Num pools more than FW profile\n");
 767                                 rc = -EINVAL;
 768                                 goto err_out;
 769                         }
 770                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 771                         bp->rx_cosq_cnt++;
 772                 }
 773         }
 774
 775 skip_cosq_cfg:
 776         rc = bnxt_mq_rx_configure(bp);
 777         if (rc) {
 778                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 779                 goto err_out;
 780         }
 781
 782         /* default vnic 0 */
 783         rc = bnxt_setup_one_vnic(bp, 0);
 784         if (rc)
 785                 goto err_out;
 786         /* VNIC configuration */
 787         if (BNXT_RFS_NEEDS_VNIC(bp)) {
 788                 for (i = 1; i < bp->nr_vnics; i++) {
 789                         rc = bnxt_setup_one_vnic(bp, i);
 790                         if (rc)
 791                                 goto err_out;
 792                 }
 793         }
 794
 795         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 796         if (rc) {
 797                 PMD_DRV_LOG(ERR,
 798                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 799                 goto err_out;
 800         }
 801
 802         /* check and configure queue intr-vector mapping */
 803         if ((rte_intr_cap_multiple(intr_handle) ||
 804              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 805             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 806                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 807                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 808                 if (intr_vector > bp->rx_cp_nr_rings) {
 809                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 810                                         bp->rx_cp_nr_rings);
 811                         return -ENOTSUP;
 812                 }
 813                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 814                 if (rc)
 815                         return rc;
 816         }
 817
 818         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 819                 intr_handle->intr_vec =
 820                         rte_zmalloc("intr_vec",
 821                                     bp->eth_dev->data->nb_rx_queues *
 822                                     sizeof(int), 0);
 823                 if (intr_handle->intr_vec == NULL) {
 824                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 825                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 826                         rc = -ENOMEM;
 827                         goto err_out;
 828                 }
 829                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 830                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 831                          intr_handle->intr_vec, intr_handle->nb_efd,
 832                         intr_handle->max_intr);
 833                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 834                      queue_id++) {
 835                         intr_handle->intr_vec[queue_id] =
 836                                                         vec + BNXT_RX_VEC_START;
 837                         if (vec < base + intr_handle->nb_efd - 1)
 838                                 vec++;
 839                 }
 840         }
 841
 842         /* enable uio/vfio intr/eventfd mapping */
 843         rc = rte_intr_enable(intr_handle);
 844 #ifndef RTE_EXEC_ENV_FREEBSD
 845         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 846         if (rc)
 847                 goto err_out;
 848 #endif
 849
 850         rc = bnxt_update_phy_setting(bp);
 851         if (rc)
 852                 goto err_out;
 853
 854         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 855         if (!bp->mark_table)
 856                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 857
 858         return 0;
 859
 860 err_out:
 861         /* Some of the error status returned by FW may not be from errno.h */
 862         if (rc > 0)
 863                 rc = -EIO;
 864
 865         return rc;
 866 }
 867
 868 static int bnxt_shutdown_nic(struct bnxt *bp)
 869 {
 870         bnxt_free_all_hwrm_resources(bp);
 871         bnxt_free_all_filters(bp);
 872         bnxt_free_all_vnics(bp);
 873         return 0;
 874 }
 875
 876 /*
 877  * Device configuration and status function
 878  */
 879
 880 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 881 {
 882         uint32_t link_speed = 0;
 883         uint32_t speed_capa = 0;
 884
 885         if (bp->link_info == NULL)
 886                 return 0;
 887
 888         link_speed = bp->link_info->support_speeds;
 889
 890         /* If PAM4 is configured, use PAM4 supported speed */
 891         if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
 892                 link_speed = bp->link_info->support_pam4_speeds;
 893
 894         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 895                 speed_capa |= ETH_LINK_SPEED_100M;
 896         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 897                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 898         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 899                 speed_capa |= ETH_LINK_SPEED_1G;
 900         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 901                 speed_capa |= ETH_LINK_SPEED_2_5G;
 902         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 903                 speed_capa |= ETH_LINK_SPEED_10G;
 904         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 905                 speed_capa |= ETH_LINK_SPEED_20G;
 906         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 907                 speed_capa |= ETH_LINK_SPEED_25G;
 908         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 909                 speed_capa |= ETH_LINK_SPEED_40G;
 910         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 911                 speed_capa |= ETH_LINK_SPEED_50G;
 912         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 913                 speed_capa |= ETH_LINK_SPEED_100G;
 914         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
 915                 speed_capa |= ETH_LINK_SPEED_50G;
 916         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
 917                 speed_capa |= ETH_LINK_SPEED_100G;
 918         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
 919                 speed_capa |= ETH_LINK_SPEED_200G;
 920
 921         if (bp->link_info->auto_mode ==
 922             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 923                 speed_capa |= ETH_LINK_SPEED_FIXED;
 924
 925         return speed_capa;
 926 }
 927
 928 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 929                                 struct rte_eth_dev_info *dev_info)
 930 {
 931         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 932         struct bnxt *bp = eth_dev->data->dev_private;
 933         uint16_t max_vnics, i, j, vpool, vrxq;
 934         unsigned int max_rx_rings;
 935         int rc;
 936
 937         rc = is_bnxt_in_error(bp);
 938         if (rc)
 939                 return rc;
 940
 941         /* MAC Specifics */
 942         dev_info->max_mac_addrs = bp->max_l2_ctx;
 943         dev_info->max_hash_mac_addrs = 0;
 944
 945         /* PF/VF specifics */
 946         if (BNXT_PF(bp))
 947                 dev_info->max_vfs = pdev->max_vfs;
 948
 949         max_rx_rings = bnxt_max_rings(bp);
 950         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 951         dev_info->max_rx_queues = max_rx_rings;
 952         dev_info->max_tx_queues = max_rx_rings;
 953         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 954         dev_info->hash_key_size = 40;
 955         max_vnics = bp->max_vnics;
 956
 957         /* MTU specifics */
 958         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 959         dev_info->max_mtu = BNXT_MAX_MTU;
 960
 961         /* Fast path specifics */
 962         dev_info->min_rx_bufsize = 1;
 963         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 964
 965         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 966         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 967                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 968         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 969         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
 970                                     dev_info->tx_queue_offload_capa;
 971         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 972
 973         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 974
 975         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 976                 .rx_thresh = {
 977                         .pthresh = 8,
 978                         .hthresh = 8,
 979                         .wthresh = 0,
 980                 },
 981                 .rx_free_thresh = 32,
 982                 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
 983         };
 984
 985         dev_info->default_txconf = (struct rte_eth_txconf) {
 986                 .tx_thresh = {
 987                         .pthresh = 32,
 988                         .hthresh = 0,
 989                         .wthresh = 0,
 990                 },
 991                 .tx_free_thresh = 32,
 992                 .tx_rs_thresh = 32,
 993         };
 994         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 995
 996         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 997         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 998         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 999         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
1000         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
1001
1002         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
1003                 dev_info->switch_info.name = eth_dev->device->name;
1004                 dev_info->switch_info.domain_id = bp->switch_domain_id;
1005                 dev_info->switch_info.port_id =
1006                                 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
1007                                     BNXT_SWITCH_PORT_ID_TRUSTED_VF;
1008         }
1009
1010         /*
1011          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
1012          *       need further investigation.
1013          */
1014
1015         /* VMDq resources */
1016         vpool = 64; /* ETH_64_POOLS */
1017         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
1018         for (i = 0; i < 4; vpool >>= 1, i++) {
1019                 if (max_vnics > vpool) {
1020                         for (j = 0; j < 5; vrxq >>= 1, j++) {
1021                                 if (dev_info->max_rx_queues > vrxq) {
1022                                         if (vpool > vrxq)
1023                                                 vpool = vrxq;
1024                                         goto found;
1025                                 }
1026                         }
1027                         /* Not enough resources to support VMDq */
1028                         break;
1029                 }
1030         }
1031         /* Not enough resources to support VMDq */
1032         vpool = 0;
1033         vrxq = 0;
1034 found:
1035         dev_info->max_vmdq_pools = vpool;
1036         dev_info->vmdq_queue_num = vrxq;
1037
1038         dev_info->vmdq_pool_base = 0;
1039         dev_info->vmdq_queue_base = 0;
1040
1041         return 0;
1042 }
1043
1044 /* Configure the device based on the configuration provided */
1045 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1046 {
1047         struct bnxt *bp = eth_dev->data->dev_private;
1048         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1049         int rc;
1050
1051         bp->rx_queues = (void *)eth_dev->data->rx_queues;
1052         bp->tx_queues = (void *)eth_dev->data->tx_queues;
1053         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1054         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1055
1056         rc = is_bnxt_in_error(bp);
1057         if (rc)
1058                 return rc;
1059
1060         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1061                 rc = bnxt_hwrm_check_vf_rings(bp);
1062                 if (rc) {
1063                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1064                         return -ENOSPC;
1065                 }
1066
1067                 /* If a resource has already been allocated - in this case
1068                  * it is the async completion ring, free it. Reallocate it after
1069                  * resource reservation. This will ensure the resource counts
1070                  * are calculated correctly.
1071                  */
1072
1073                 pthread_mutex_lock(&bp->def_cp_lock);
1074
1075                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1076                         bnxt_disable_int(bp);
1077                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
1078                 }
1079
1080                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1081                 if (rc) {
1082                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1083                         pthread_mutex_unlock(&bp->def_cp_lock);
1084                         return -ENOSPC;
1085                 }
1086
1087                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1088                         rc = bnxt_alloc_async_cp_ring(bp);
1089                         if (rc) {
1090                                 pthread_mutex_unlock(&bp->def_cp_lock);
1091                                 return rc;
1092                         }
1093                         bnxt_enable_int(bp);
1094                 }
1095
1096                 pthread_mutex_unlock(&bp->def_cp_lock);
1097         }
1098
1099         /* Inherit new configurations */
1100         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1101             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1102             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1103                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1104             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1105             bp->max_stat_ctx)
1106                 goto resource_error;
1107
1108         if (BNXT_HAS_RING_GRPS(bp) &&
1109             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1110                 goto resource_error;
1111
1112         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1113             bp->max_vnics < eth_dev->data->nb_rx_queues)
1114                 goto resource_error;
1115
1116         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1117         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1118
1119         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1120                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1121         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1122
1123         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1124                 eth_dev->data->mtu =
1125                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1126                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1127                         BNXT_NUM_VLANS;
1128                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1129         }
1130         return 0;
1131
1132 resource_error:
1133         PMD_DRV_LOG(ERR,
1134                     "Insufficient resources to support requested config\n");
1135         PMD_DRV_LOG(ERR,
1136                     "Num Queues Requested: Tx %d, Rx %d\n",
1137                     eth_dev->data->nb_tx_queues,
1138                     eth_dev->data->nb_rx_queues);
1139         PMD_DRV_LOG(ERR,
1140                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1141                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1142                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1143         return -ENOSPC;
1144 }
1145
1146 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1147 {
1148         struct rte_eth_link *link = &eth_dev->data->dev_link;
1149
1150         if (link->link_status)
1151                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1152                         eth_dev->data->port_id,
1153                         (uint32_t)link->link_speed,
1154                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1155                         ("full-duplex") : ("half-duplex\n"));
1156         else
1157                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1158                         eth_dev->data->port_id);
1159 }
1160
1161 /*
1162  * Determine whether the current configuration requires support for scattered
1163  * receive; return 1 if scattered receive is required and 0 if not.
1164  */
1165 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1166 {
1167         uint16_t buf_size;
1168         int i;
1169
1170         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1171                 return 1;
1172
1173         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO)
1174                 return 1;
1175
1176         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1177                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1178
1179                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1180                                       RTE_PKTMBUF_HEADROOM);
1181                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1182                         return 1;
1183         }
1184         return 0;
1185 }
1186
1187 static eth_rx_burst_t
1188 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1189 {
1190         struct bnxt *bp = eth_dev->data->dev_private;
1191
1192         /* Disable vector mode RX for Stingray2 for now */
1193         if (BNXT_CHIP_SR2(bp)) {
1194                 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1195                 return bnxt_recv_pkts;
1196         }
1197
1198 #if (defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)) && \
1199         !defined(RTE_LIBRTE_IEEE1588)
1200
1201         /* Vector mode receive cannot be enabled if scattered rx is in use. */
1202         if (eth_dev->data->scattered_rx)
1203                 goto use_scalar_rx;
1204
1205         /*
1206          * Vector mode receive cannot be enabled if Truflow is enabled or if
1207          * asynchronous completions and receive completions can be placed in
1208          * the same completion ring.
1209          */
1210         if (BNXT_TRUFLOW_EN(bp) || !BNXT_NUM_ASYNC_CPR(bp))
1211                 goto use_scalar_rx;
1212
1213         /*
1214          * Vector mode receive cannot be enabled if any receive offloads outside
1215          * a limited subset have been enabled.
1216          */
1217         if (eth_dev->data->dev_conf.rxmode.offloads &
1218                 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1219                   DEV_RX_OFFLOAD_KEEP_CRC |
1220                   DEV_RX_OFFLOAD_JUMBO_FRAME |
1221                   DEV_RX_OFFLOAD_IPV4_CKSUM |
1222                   DEV_RX_OFFLOAD_UDP_CKSUM |
1223                   DEV_RX_OFFLOAD_TCP_CKSUM |
1224                   DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1225                   DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1226                   DEV_RX_OFFLOAD_RSS_HASH |
1227                   DEV_RX_OFFLOAD_VLAN_FILTER))
1228                 goto use_scalar_rx;
1229
1230 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1231         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1232             rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1233                 PMD_DRV_LOG(INFO,
1234                             "Using AVX2 vector mode receive for port %d\n",
1235                             eth_dev->data->port_id);
1236                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1237                 return bnxt_recv_pkts_vec_avx2;
1238         }
1239  #endif
1240         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1241                 PMD_DRV_LOG(INFO,
1242                             "Using SSE vector mode receive for port %d\n",
1243                             eth_dev->data->port_id);
1244                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1245                 return bnxt_recv_pkts_vec;
1246         }
1247
1248 use_scalar_rx:
1249         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1250                     eth_dev->data->port_id);
1251         PMD_DRV_LOG(INFO,
1252                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1253                     eth_dev->data->port_id,
1254                     eth_dev->data->scattered_rx,
1255                     eth_dev->data->dev_conf.rxmode.offloads);
1256 #endif
1257         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1258         return bnxt_recv_pkts;
1259 }
1260
1261 static eth_tx_burst_t
1262 bnxt_transmit_function(struct rte_eth_dev *eth_dev)
1263 {
1264         struct bnxt *bp = eth_dev->data->dev_private;
1265
1266         /* Disable vector mode TX for Stingray2 for now */
1267         if (BNXT_CHIP_SR2(bp))
1268                 return bnxt_xmit_pkts;
1269
1270 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) && \
1271         !defined(RTE_LIBRTE_IEEE1588)
1272         uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1273
1274         /*
1275          * Vector mode transmit can be enabled only if not using scatter rx
1276          * or tx offloads.
1277          */
1278         if (eth_dev->data->scattered_rx ||
1279             (offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) ||
1280             BNXT_TRUFLOW_EN(bp))
1281                 goto use_scalar_tx;
1282
1283 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1284         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1285             rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1286                 PMD_DRV_LOG(INFO,
1287                             "Using AVX2 vector mode transmit for port %d\n",
1288                             eth_dev->data->port_id);
1289                 return bnxt_xmit_pkts_vec_avx2;
1290         }
1291 #endif
1292         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1293                 PMD_DRV_LOG(INFO,
1294                             "Using SSE vector mode transmit for port %d\n",
1295                             eth_dev->data->port_id);
1296                 return bnxt_xmit_pkts_vec;
1297         }
1298
1299 use_scalar_tx:
1300         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1301                     eth_dev->data->port_id);
1302         PMD_DRV_LOG(INFO,
1303                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1304                     eth_dev->data->port_id,
1305                     eth_dev->data->scattered_rx,
1306                     offloads);
1307 #endif
1308         return bnxt_xmit_pkts;
1309 }
1310
1311 static int bnxt_handle_if_change_status(struct bnxt *bp)
1312 {
1313         int rc;
1314
1315         /* Since fw has undergone a reset and lost all contexts,
1316          * set fatal flag to not issue hwrm during cleanup
1317          */
1318         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1319         bnxt_uninit_resources(bp, true);
1320
1321         /* clear fatal flag so that re-init happens */
1322         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1323         rc = bnxt_init_resources(bp, true);
1324
1325         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1326
1327         return rc;
1328 }
1329
1330 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1331 {
1332         struct bnxt *bp = eth_dev->data->dev_private;
1333         int rc = 0;
1334
1335         if (!BNXT_SINGLE_PF(bp))
1336                 return -ENOTSUP;
1337
1338         if (!bp->link_info->link_up)
1339                 rc = bnxt_set_hwrm_link_config(bp, true);
1340         if (!rc)
1341                 eth_dev->data->dev_link.link_status = 1;
1342
1343         bnxt_print_link_info(eth_dev);
1344         return rc;
1345 }
1346
1347 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1348 {
1349         struct bnxt *bp = eth_dev->data->dev_private;
1350
1351         if (!BNXT_SINGLE_PF(bp))
1352                 return -ENOTSUP;
1353
1354         eth_dev->data->dev_link.link_status = 0;
1355         bnxt_set_hwrm_link_config(bp, false);
1356         bp->link_info->link_up = 0;
1357
1358         return 0;
1359 }
1360
1361 static void bnxt_free_switch_domain(struct bnxt *bp)
1362 {
1363         int rc = 0;
1364
1365         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)))
1366                 return;
1367
1368         rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1369         if (rc)
1370                 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1371                             bp->switch_domain_id, rc);
1372 }
1373
1374 static void bnxt_ptp_get_current_time(void *arg)
1375 {
1376         struct bnxt *bp = arg;
1377         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1378         int rc;
1379
1380         rc = is_bnxt_in_error(bp);
1381         if (rc)
1382                 return;
1383
1384         if (!ptp)
1385                 return;
1386
1387         bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1388                                 &ptp->current_time);
1389
1390         rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1391         if (rc != 0) {
1392                 PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n");
1393                 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1394         }
1395 }
1396
1397 static int bnxt_schedule_ptp_alarm(struct bnxt *bp)
1398 {
1399         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1400         int rc;
1401
1402         if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED)
1403                 return 0;
1404
1405         bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1406                                 &ptp->current_time);
1407
1408         rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1409         return rc;
1410 }
1411
1412 static void bnxt_cancel_ptp_alarm(struct bnxt *bp)
1413 {
1414         if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) {
1415                 rte_eal_alarm_cancel(bnxt_ptp_get_current_time, (void *)bp);
1416                 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1417         }
1418 }
1419
1420 static void bnxt_ptp_stop(struct bnxt *bp)
1421 {
1422         bnxt_cancel_ptp_alarm(bp);
1423         bp->flags2 &= ~BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1424 }
1425
1426 static int bnxt_ptp_start(struct bnxt *bp)
1427 {
1428         int rc;
1429
1430         rc = bnxt_schedule_ptp_alarm(bp);
1431         if (rc != 0) {
1432                 PMD_DRV_LOG(ERR, "Failed to schedule PTP alarm\n");
1433         } else {
1434                 bp->flags2 |= BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1435                 bp->flags2 |= BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1436         }
1437
1438         return rc;
1439 }
1440
1441 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev)
1442 {
1443         struct bnxt *bp = eth_dev->data->dev_private;
1444         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1445         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1446         struct rte_eth_link link;
1447         int ret;
1448
1449         eth_dev->data->dev_started = 0;
1450         eth_dev->data->scattered_rx = 0;
1451
1452         /* Prevent crashes when queues are still in use */
1453         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1454         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1455
1456         bnxt_disable_int(bp);
1457
1458         /* disable uio/vfio intr/eventfd mapping */
1459         rte_intr_disable(intr_handle);
1460
1461         /* Stop the child representors for this device */
1462         ret = bnxt_rep_stop_all(bp);
1463         if (ret != 0)
1464                 return ret;
1465
1466         /* delete the bnxt ULP port details */
1467         bnxt_ulp_port_deinit(bp);
1468
1469         bnxt_cancel_fw_health_check(bp);
1470
1471         if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1472                 bnxt_cancel_ptp_alarm(bp);
1473
1474         /* Do not bring link down during reset recovery */
1475         if (!is_bnxt_in_error(bp)) {
1476                 bnxt_dev_set_link_down_op(eth_dev);
1477                 /* Wait for link to be reset */
1478                 if (BNXT_SINGLE_PF(bp))
1479                         rte_delay_ms(500);
1480                 /* clear the recorded link status */
1481                 memset(&link, 0, sizeof(link));
1482                 rte_eth_linkstatus_set(eth_dev, &link);
1483         }
1484
1485         /* Clean queue intr-vector mapping */
1486         rte_intr_efd_disable(intr_handle);
1487         if (intr_handle->intr_vec != NULL) {
1488                 rte_free(intr_handle->intr_vec);
1489                 intr_handle->intr_vec = NULL;
1490         }
1491
1492         bnxt_hwrm_port_clr_stats(bp);
1493         bnxt_free_tx_mbufs(bp);
1494         bnxt_free_rx_mbufs(bp);
1495         /* Process any remaining notifications in default completion queue */
1496         bnxt_int_handler(eth_dev);
1497         bnxt_shutdown_nic(bp);
1498         bnxt_hwrm_if_change(bp, false);
1499
1500         bnxt_free_prev_ring_stats(bp);
1501         rte_free(bp->mark_table);
1502         bp->mark_table = NULL;
1503
1504         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1505         bp->rx_cosq_cnt = 0;
1506         /* All filters are deleted on a port stop. */
1507         if (BNXT_FLOW_XSTATS_EN(bp))
1508                 bp->flow_stat->flow_count = 0;
1509
1510         return 0;
1511 }
1512
1513 /* Unload the driver, release resources */
1514 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1515 {
1516         struct bnxt *bp = eth_dev->data->dev_private;
1517
1518         pthread_mutex_lock(&bp->err_recovery_lock);
1519         if (bp->flags & BNXT_FLAG_FW_RESET) {
1520                 PMD_DRV_LOG(ERR,
1521                             "Adapter recovering from error..Please retry\n");
1522                 pthread_mutex_unlock(&bp->err_recovery_lock);
1523                 return -EAGAIN;
1524         }
1525         pthread_mutex_unlock(&bp->err_recovery_lock);
1526
1527         return bnxt_dev_stop(eth_dev);
1528 }
1529
1530 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1531 {
1532         struct bnxt *bp = eth_dev->data->dev_private;
1533         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1534         int vlan_mask = 0;
1535         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1536
1537         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1538                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1539                 return -EINVAL;
1540         }
1541
1542         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1543                 PMD_DRV_LOG(ERR,
1544                             "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1545                             bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1546
1547         do {
1548                 rc = bnxt_hwrm_if_change(bp, true);
1549                 if (rc == 0 || rc != -EAGAIN)
1550                         break;
1551
1552                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1553         } while (retry_cnt--);
1554
1555         if (rc)
1556                 return rc;
1557
1558         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1559                 rc = bnxt_handle_if_change_status(bp);
1560                 if (rc)
1561                         return rc;
1562         }
1563
1564         bnxt_enable_int(bp);
1565
1566         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1567
1568         rc = bnxt_start_nic(bp);
1569         if (rc)
1570                 goto error;
1571
1572         rc = bnxt_alloc_prev_ring_stats(bp);
1573         if (rc)
1574                 goto error;
1575
1576         eth_dev->data->dev_started = 1;
1577
1578         bnxt_link_update_op(eth_dev, 1);
1579
1580         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1581                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1582         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1583                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1584         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1585         if (rc)
1586                 goto error;
1587
1588         /* Initialize bnxt ULP port details */
1589         rc = bnxt_ulp_port_init(bp);
1590         if (rc)
1591                 goto error;
1592
1593         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1594         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1595
1596         bnxt_schedule_fw_health_check(bp);
1597
1598         if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1599                 bnxt_schedule_ptp_alarm(bp);
1600
1601         return 0;
1602
1603 error:
1604         bnxt_dev_stop(eth_dev);
1605         return rc;
1606 }
1607
1608 static void
1609 bnxt_uninit_locks(struct bnxt *bp)
1610 {
1611         pthread_mutex_destroy(&bp->flow_lock);
1612         pthread_mutex_destroy(&bp->def_cp_lock);
1613         pthread_mutex_destroy(&bp->health_check_lock);
1614         pthread_mutex_destroy(&bp->err_recovery_lock);
1615         if (bp->rep_info) {
1616                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
1617                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
1618         }
1619 }
1620
1621 static void bnxt_drv_uninit(struct bnxt *bp)
1622 {
1623         bnxt_free_leds_info(bp);
1624         bnxt_free_cos_queues(bp);
1625         bnxt_free_link_info(bp);
1626         bnxt_free_parent_info(bp);
1627         bnxt_uninit_locks(bp);
1628
1629         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1630         bp->tx_mem_zone = NULL;
1631         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1632         bp->rx_mem_zone = NULL;
1633
1634         bnxt_free_vf_info(bp);
1635         bnxt_free_pf_info(bp);
1636
1637         rte_free(bp->grp_info);
1638         bp->grp_info = NULL;
1639 }
1640
1641 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1642 {
1643         struct bnxt *bp = eth_dev->data->dev_private;
1644         int ret = 0;
1645
1646         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1647                 return 0;
1648
1649         pthread_mutex_lock(&bp->err_recovery_lock);
1650         if (bp->flags & BNXT_FLAG_FW_RESET) {
1651                 PMD_DRV_LOG(ERR,
1652                             "Adapter recovering from error...Please retry\n");
1653                 pthread_mutex_unlock(&bp->err_recovery_lock);
1654                 return -EAGAIN;
1655         }
1656         pthread_mutex_unlock(&bp->err_recovery_lock);
1657
1658         /* cancel the recovery handler before remove dev */
1659         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1660         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1661         bnxt_cancel_fc_thread(bp);
1662
1663         if (eth_dev->data->dev_started)
1664                 ret = bnxt_dev_stop(eth_dev);
1665
1666         bnxt_uninit_resources(bp, false);
1667
1668         bnxt_drv_uninit(bp);
1669
1670         return ret;
1671 }
1672
1673 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1674                                     uint32_t index)
1675 {
1676         struct bnxt *bp = eth_dev->data->dev_private;
1677         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1678         struct bnxt_vnic_info *vnic;
1679         struct bnxt_filter_info *filter, *temp_filter;
1680         uint32_t i;
1681
1682         if (is_bnxt_in_error(bp))
1683                 return;
1684
1685         /*
1686          * Loop through all VNICs from the specified filter flow pools to
1687          * remove the corresponding MAC addr filter
1688          */
1689         for (i = 0; i < bp->nr_vnics; i++) {
1690                 if (!(pool_mask & (1ULL << i)))
1691                         continue;
1692
1693                 vnic = &bp->vnic_info[i];
1694                 filter = STAILQ_FIRST(&vnic->filter);
1695                 while (filter) {
1696                         temp_filter = STAILQ_NEXT(filter, next);
1697                         if (filter->mac_index == index) {
1698                                 STAILQ_REMOVE(&vnic->filter, filter,
1699                                                 bnxt_filter_info, next);
1700                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1701                                 bnxt_free_filter(bp, filter);
1702                         }
1703                         filter = temp_filter;
1704                 }
1705         }
1706 }
1707
1708 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1709                                struct rte_ether_addr *mac_addr, uint32_t index,
1710                                uint32_t pool)
1711 {
1712         struct bnxt_filter_info *filter;
1713         int rc = 0;
1714
1715         /* Attach requested MAC address to the new l2_filter */
1716         STAILQ_FOREACH(filter, &vnic->filter, next) {
1717                 if (filter->mac_index == index) {
1718                         PMD_DRV_LOG(DEBUG,
1719                                     "MAC addr already existed for pool %d\n",
1720                                     pool);
1721                         return 0;
1722                 }
1723         }
1724
1725         filter = bnxt_alloc_filter(bp);
1726         if (!filter) {
1727                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1728                 return -ENODEV;
1729         }
1730
1731         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1732          * if the MAC that's been programmed now is a different one, then,
1733          * copy that addr to filter->l2_addr
1734          */
1735         if (mac_addr)
1736                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1737         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1738
1739         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1740         if (!rc) {
1741                 filter->mac_index = index;
1742                 if (filter->mac_index == 0)
1743                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1744                 else
1745                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1746         } else {
1747                 bnxt_free_filter(bp, filter);
1748         }
1749
1750         return rc;
1751 }
1752
1753 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1754                                 struct rte_ether_addr *mac_addr,
1755                                 uint32_t index, uint32_t pool)
1756 {
1757         struct bnxt *bp = eth_dev->data->dev_private;
1758         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1759         int rc = 0;
1760
1761         rc = is_bnxt_in_error(bp);
1762         if (rc)
1763                 return rc;
1764
1765         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1766                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1767                 return -ENOTSUP;
1768         }
1769
1770         if (!vnic) {
1771                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1772                 return -EINVAL;
1773         }
1774
1775         /* Filter settings will get applied when port is started */
1776         if (!eth_dev->data->dev_started)
1777                 return 0;
1778
1779         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1780
1781         return rc;
1782 }
1783
1784 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1785 {
1786         int rc = 0;
1787         struct bnxt *bp = eth_dev->data->dev_private;
1788         struct rte_eth_link new;
1789         int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1790                         BNXT_MIN_LINK_WAIT_CNT;
1791
1792         rc = is_bnxt_in_error(bp);
1793         if (rc)
1794                 return rc;
1795
1796         memset(&new, 0, sizeof(new));
1797
1798         if (bp->link_info == NULL)
1799                 goto out;
1800
1801         do {
1802                 /* Retrieve link info from hardware */
1803                 rc = bnxt_get_hwrm_link_config(bp, &new);
1804                 if (rc) {
1805                         new.link_speed = ETH_LINK_SPEED_100M;
1806                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1807                         PMD_DRV_LOG(ERR,
1808                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1809                         goto out;
1810                 }
1811
1812                 if (!wait_to_complete || new.link_status)
1813                         break;
1814
1815                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1816         } while (cnt--);
1817
1818         /* Only single function PF can bring phy down.
1819          * When port is stopped, report link down for VF/MH/NPAR functions.
1820          */
1821         if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1822                 memset(&new, 0, sizeof(new));
1823
1824 out:
1825         /* Timed out or success */
1826         if (new.link_status != eth_dev->data->dev_link.link_status ||
1827             new.link_speed != eth_dev->data->dev_link.link_speed) {
1828                 rte_eth_linkstatus_set(eth_dev, &new);
1829
1830                 rte_eth_dev_callback_process(eth_dev,
1831                                              RTE_ETH_EVENT_INTR_LSC,
1832                                              NULL);
1833
1834                 bnxt_print_link_info(eth_dev);
1835         }
1836
1837         return rc;
1838 }
1839
1840 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1841 {
1842         struct bnxt *bp = eth_dev->data->dev_private;
1843         struct bnxt_vnic_info *vnic;
1844         uint32_t old_flags;
1845         int rc;
1846
1847         rc = is_bnxt_in_error(bp);
1848         if (rc)
1849                 return rc;
1850
1851         /* Filter settings will get applied when port is started */
1852         if (!eth_dev->data->dev_started)
1853                 return 0;
1854
1855         if (bp->vnic_info == NULL)
1856                 return 0;
1857
1858         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1859
1860         old_flags = vnic->flags;
1861         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1862         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1863         if (rc != 0)
1864                 vnic->flags = old_flags;
1865
1866         return rc;
1867 }
1868
1869 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1870 {
1871         struct bnxt *bp = eth_dev->data->dev_private;
1872         struct bnxt_vnic_info *vnic;
1873         uint32_t old_flags;
1874         int rc;
1875
1876         rc = is_bnxt_in_error(bp);
1877         if (rc)
1878                 return rc;
1879
1880         /* Filter settings will get applied when port is started */
1881         if (!eth_dev->data->dev_started)
1882                 return 0;
1883
1884         if (bp->vnic_info == NULL)
1885                 return 0;
1886
1887         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1888
1889         old_flags = vnic->flags;
1890         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1891         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1892         if (rc != 0)
1893                 vnic->flags = old_flags;
1894
1895         return rc;
1896 }
1897
1898 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1899 {
1900         struct bnxt *bp = eth_dev->data->dev_private;
1901         struct bnxt_vnic_info *vnic;
1902         uint32_t old_flags;
1903         int rc;
1904
1905         rc = is_bnxt_in_error(bp);
1906         if (rc)
1907                 return rc;
1908
1909         /* Filter settings will get applied when port is started */
1910         if (!eth_dev->data->dev_started)
1911                 return 0;
1912
1913         if (bp->vnic_info == NULL)
1914                 return 0;
1915
1916         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1917
1918         old_flags = vnic->flags;
1919         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1920         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1921         if (rc != 0)
1922                 vnic->flags = old_flags;
1923
1924         return rc;
1925 }
1926
1927 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1928 {
1929         struct bnxt *bp = eth_dev->data->dev_private;
1930         struct bnxt_vnic_info *vnic;
1931         uint32_t old_flags;
1932         int rc;
1933
1934         rc = is_bnxt_in_error(bp);
1935         if (rc)
1936                 return rc;
1937
1938         /* Filter settings will get applied when port is started */
1939         if (!eth_dev->data->dev_started)
1940                 return 0;
1941
1942         if (bp->vnic_info == NULL)
1943                 return 0;
1944
1945         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1946
1947         old_flags = vnic->flags;
1948         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1949         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1950         if (rc != 0)
1951                 vnic->flags = old_flags;
1952
1953         return rc;
1954 }
1955
1956 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1957 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1958 {
1959         if (qid >= bp->rx_nr_rings)
1960                 return NULL;
1961
1962         return bp->eth_dev->data->rx_queues[qid];
1963 }
1964
1965 /* Return rxq corresponding to a given rss table ring/group ID. */
1966 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1967 {
1968         struct bnxt_rx_queue *rxq;
1969         unsigned int i;
1970
1971         if (!BNXT_HAS_RING_GRPS(bp)) {
1972                 for (i = 0; i < bp->rx_nr_rings; i++) {
1973                         rxq = bp->eth_dev->data->rx_queues[i];
1974                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1975                                 return rxq->index;
1976                 }
1977         } else {
1978                 for (i = 0; i < bp->rx_nr_rings; i++) {
1979                         if (bp->grp_info[i].fw_grp_id == fwr)
1980                                 return i;
1981                 }
1982         }
1983
1984         return INVALID_HW_RING_ID;
1985 }
1986
1987 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1988                             struct rte_eth_rss_reta_entry64 *reta_conf,
1989                             uint16_t reta_size)
1990 {
1991         struct bnxt *bp = eth_dev->data->dev_private;
1992         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1993         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1994         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1995         uint16_t idx, sft;
1996         int i, rc;
1997
1998         rc = is_bnxt_in_error(bp);
1999         if (rc)
2000                 return rc;
2001
2002         if (!vnic->rss_table)
2003                 return -EINVAL;
2004
2005         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
2006                 return -EINVAL;
2007
2008         if (reta_size != tbl_size) {
2009                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2010                         "(%d) must equal the size supported by the hardware "
2011                         "(%d)\n", reta_size, tbl_size);
2012                 return -EINVAL;
2013         }
2014
2015         for (i = 0; i < reta_size; i++) {
2016                 struct bnxt_rx_queue *rxq;
2017
2018                 idx = i / RTE_RETA_GROUP_SIZE;
2019                 sft = i % RTE_RETA_GROUP_SIZE;
2020
2021                 if (!(reta_conf[idx].mask & (1ULL << sft)))
2022                         continue;
2023
2024                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
2025                 if (!rxq) {
2026                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
2027                         return -EINVAL;
2028                 }
2029
2030                 if (BNXT_CHIP_P5(bp)) {
2031                         vnic->rss_table[i * 2] =
2032                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
2033                         vnic->rss_table[i * 2 + 1] =
2034                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
2035                 } else {
2036                         vnic->rss_table[i] =
2037                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
2038                 }
2039         }
2040
2041         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2042         return rc;
2043 }
2044
2045 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
2046                               struct rte_eth_rss_reta_entry64 *reta_conf,
2047                               uint16_t reta_size)
2048 {
2049         struct bnxt *bp = eth_dev->data->dev_private;
2050         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2051         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
2052         uint16_t idx, sft, i;
2053         int rc;
2054
2055         rc = is_bnxt_in_error(bp);
2056         if (rc)
2057                 return rc;
2058
2059         /* Retrieve from the default VNIC */
2060         if (!vnic)
2061                 return -EINVAL;
2062         if (!vnic->rss_table)
2063                 return -EINVAL;
2064
2065         if (reta_size != tbl_size) {
2066                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2067                         "(%d) must equal the size supported by the hardware "
2068                         "(%d)\n", reta_size, tbl_size);
2069                 return -EINVAL;
2070         }
2071
2072         for (idx = 0, i = 0; i < reta_size; i++) {
2073                 idx = i / RTE_RETA_GROUP_SIZE;
2074                 sft = i % RTE_RETA_GROUP_SIZE;
2075
2076                 if (reta_conf[idx].mask & (1ULL << sft)) {
2077                         uint16_t qid;
2078
2079                         if (BNXT_CHIP_P5(bp))
2080                                 qid = bnxt_rss_to_qid(bp,
2081                                                       vnic->rss_table[i * 2]);
2082                         else
2083                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
2084
2085                         if (qid == INVALID_HW_RING_ID) {
2086                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
2087                                 return -EINVAL;
2088                         }
2089                         reta_conf[idx].reta[sft] = qid;
2090                 }
2091         }
2092
2093         return 0;
2094 }
2095
2096 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
2097                                    struct rte_eth_rss_conf *rss_conf)
2098 {
2099         struct bnxt *bp = eth_dev->data->dev_private;
2100         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2101         struct bnxt_vnic_info *vnic;
2102         int rc;
2103
2104         rc = is_bnxt_in_error(bp);
2105         if (rc)
2106                 return rc;
2107
2108         /*
2109          * If RSS enablement were different than dev_configure,
2110          * then return -EINVAL
2111          */
2112         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
2113                 if (!rss_conf->rss_hf)
2114                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
2115         } else {
2116                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
2117                         return -EINVAL;
2118         }
2119
2120         bp->flags |= BNXT_FLAG_UPDATE_HASH;
2121         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
2122                rss_conf,
2123                sizeof(*rss_conf));
2124
2125         /* Update the default RSS VNIC(s) */
2126         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2127         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
2128         vnic->hash_mode =
2129                 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
2130                                             ETH_RSS_LEVEL(rss_conf->rss_hf));
2131
2132         /*
2133          * If hashkey is not specified, use the previously configured
2134          * hashkey
2135          */
2136         if (!rss_conf->rss_key)
2137                 goto rss_config;
2138
2139         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
2140                 PMD_DRV_LOG(ERR,
2141                             "Invalid hashkey length, should be 16 bytes\n");
2142                 return -EINVAL;
2143         }
2144         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
2145
2146 rss_config:
2147         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2148         return rc;
2149 }
2150
2151 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
2152                                      struct rte_eth_rss_conf *rss_conf)
2153 {
2154         struct bnxt *bp = eth_dev->data->dev_private;
2155         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2156         int len, rc;
2157         uint32_t hash_types;
2158
2159         rc = is_bnxt_in_error(bp);
2160         if (rc)
2161                 return rc;
2162
2163         /* RSS configuration is the same for all VNICs */
2164         if (vnic && vnic->rss_hash_key) {
2165                 if (rss_conf->rss_key) {
2166                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
2167                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
2168                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
2169                 }
2170
2171                 hash_types = vnic->hash_type;
2172                 rss_conf->rss_hf = 0;
2173                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
2174                         rss_conf->rss_hf |= ETH_RSS_IPV4;
2175                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
2176                 }
2177                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
2178                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2179                         hash_types &=
2180                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
2181                 }
2182                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
2183                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2184                         hash_types &=
2185                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
2186                 }
2187                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
2188                         rss_conf->rss_hf |= ETH_RSS_IPV6;
2189                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
2190                 }
2191                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
2192                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2193                         hash_types &=
2194                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
2195                 }
2196                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
2197                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2198                         hash_types &=
2199                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2200                 }
2201
2202                 rss_conf->rss_hf |=
2203                         bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2204
2205                 if (hash_types) {
2206                         PMD_DRV_LOG(ERR,
2207                                 "Unknown RSS config from firmware (%08x), RSS disabled",
2208                                 vnic->hash_type);
2209                         return -ENOTSUP;
2210                 }
2211         } else {
2212                 rss_conf->rss_hf = 0;
2213         }
2214         return 0;
2215 }
2216
2217 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2218                                struct rte_eth_fc_conf *fc_conf)
2219 {
2220         struct bnxt *bp = dev->data->dev_private;
2221         struct rte_eth_link link_info;
2222         int rc;
2223
2224         rc = is_bnxt_in_error(bp);
2225         if (rc)
2226                 return rc;
2227
2228         rc = bnxt_get_hwrm_link_config(bp, &link_info);
2229         if (rc)
2230                 return rc;
2231
2232         memset(fc_conf, 0, sizeof(*fc_conf));
2233         if (bp->link_info->auto_pause)
2234                 fc_conf->autoneg = 1;
2235         switch (bp->link_info->pause) {
2236         case 0:
2237                 fc_conf->mode = RTE_FC_NONE;
2238                 break;
2239         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2240                 fc_conf->mode = RTE_FC_TX_PAUSE;
2241                 break;
2242         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2243                 fc_conf->mode = RTE_FC_RX_PAUSE;
2244                 break;
2245         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2246                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2247                 fc_conf->mode = RTE_FC_FULL;
2248                 break;
2249         }
2250         return 0;
2251 }
2252
2253 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2254                                struct rte_eth_fc_conf *fc_conf)
2255 {
2256         struct bnxt *bp = dev->data->dev_private;
2257         int rc;
2258
2259         rc = is_bnxt_in_error(bp);
2260         if (rc)
2261                 return rc;
2262
2263         if (!BNXT_SINGLE_PF(bp)) {
2264                 PMD_DRV_LOG(ERR,
2265                             "Flow Control Settings cannot be modified on VF or on shared PF\n");
2266                 return -ENOTSUP;
2267         }
2268
2269         switch (fc_conf->mode) {
2270         case RTE_FC_NONE:
2271                 bp->link_info->auto_pause = 0;
2272                 bp->link_info->force_pause = 0;
2273                 break;
2274         case RTE_FC_RX_PAUSE:
2275                 if (fc_conf->autoneg) {
2276                         bp->link_info->auto_pause =
2277                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2278                         bp->link_info->force_pause = 0;
2279                 } else {
2280                         bp->link_info->auto_pause = 0;
2281                         bp->link_info->force_pause =
2282                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2283                 }
2284                 break;
2285         case RTE_FC_TX_PAUSE:
2286                 if (fc_conf->autoneg) {
2287                         bp->link_info->auto_pause =
2288                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2289                         bp->link_info->force_pause = 0;
2290                 } else {
2291                         bp->link_info->auto_pause = 0;
2292                         bp->link_info->force_pause =
2293                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2294                 }
2295                 break;
2296         case RTE_FC_FULL:
2297                 if (fc_conf->autoneg) {
2298                         bp->link_info->auto_pause =
2299                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2300                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2301                         bp->link_info->force_pause = 0;
2302                 } else {
2303                         bp->link_info->auto_pause = 0;
2304                         bp->link_info->force_pause =
2305                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2306                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2307                 }
2308                 break;
2309         }
2310         return bnxt_set_hwrm_link_config(bp, true);
2311 }
2312
2313 /* Add UDP tunneling port */
2314 static int
2315 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2316                          struct rte_eth_udp_tunnel *udp_tunnel)
2317 {
2318         struct bnxt *bp = eth_dev->data->dev_private;
2319         uint16_t tunnel_type = 0;
2320         int rc = 0;
2321
2322         rc = is_bnxt_in_error(bp);
2323         if (rc)
2324                 return rc;
2325
2326         switch (udp_tunnel->prot_type) {
2327         case RTE_TUNNEL_TYPE_VXLAN:
2328                 if (bp->vxlan_port_cnt) {
2329                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2330                                 udp_tunnel->udp_port);
2331                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2332                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2333                                 return -ENOSPC;
2334                         }
2335                         bp->vxlan_port_cnt++;
2336                         return 0;
2337                 }
2338                 tunnel_type =
2339                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2340                 bp->vxlan_port_cnt++;
2341                 break;
2342         case RTE_TUNNEL_TYPE_GENEVE:
2343                 if (bp->geneve_port_cnt) {
2344                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2345                                 udp_tunnel->udp_port);
2346                         if (bp->geneve_port != udp_tunnel->udp_port) {
2347                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2348                                 return -ENOSPC;
2349                         }
2350                         bp->geneve_port_cnt++;
2351                         return 0;
2352                 }
2353                 tunnel_type =
2354                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2355                 bp->geneve_port_cnt++;
2356                 break;
2357         default:
2358                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2359                 return -ENOTSUP;
2360         }
2361         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2362                                              tunnel_type);
2363         return rc;
2364 }
2365
2366 static int
2367 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2368                          struct rte_eth_udp_tunnel *udp_tunnel)
2369 {
2370         struct bnxt *bp = eth_dev->data->dev_private;
2371         uint16_t tunnel_type = 0;
2372         uint16_t port = 0;
2373         int rc = 0;
2374
2375         rc = is_bnxt_in_error(bp);
2376         if (rc)
2377                 return rc;
2378
2379         switch (udp_tunnel->prot_type) {
2380         case RTE_TUNNEL_TYPE_VXLAN:
2381                 if (!bp->vxlan_port_cnt) {
2382                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2383                         return -EINVAL;
2384                 }
2385                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2386                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2387                                 udp_tunnel->udp_port, bp->vxlan_port);
2388                         return -EINVAL;
2389                 }
2390                 if (--bp->vxlan_port_cnt)
2391                         return 0;
2392
2393                 tunnel_type =
2394                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2395                 port = bp->vxlan_fw_dst_port_id;
2396                 break;
2397         case RTE_TUNNEL_TYPE_GENEVE:
2398                 if (!bp->geneve_port_cnt) {
2399                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2400                         return -EINVAL;
2401                 }
2402                 if (bp->geneve_port != udp_tunnel->udp_port) {
2403                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2404                                 udp_tunnel->udp_port, bp->geneve_port);
2405                         return -EINVAL;
2406                 }
2407                 if (--bp->geneve_port_cnt)
2408                         return 0;
2409
2410                 tunnel_type =
2411                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2412                 port = bp->geneve_fw_dst_port_id;
2413                 break;
2414         default:
2415                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2416                 return -ENOTSUP;
2417         }
2418
2419         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2420         return rc;
2421 }
2422
2423 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2424 {
2425         struct bnxt_filter_info *filter;
2426         struct bnxt_vnic_info *vnic;
2427         int rc = 0;
2428         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2429
2430         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2431         filter = STAILQ_FIRST(&vnic->filter);
2432         while (filter) {
2433                 /* Search for this matching MAC+VLAN filter */
2434                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2435                         /* Delete the filter */
2436                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2437                         if (rc)
2438                                 return rc;
2439                         STAILQ_REMOVE(&vnic->filter, filter,
2440                                       bnxt_filter_info, next);
2441                         bnxt_free_filter(bp, filter);
2442                         PMD_DRV_LOG(INFO,
2443                                     "Deleted vlan filter for %d\n",
2444                                     vlan_id);
2445                         return 0;
2446                 }
2447                 filter = STAILQ_NEXT(filter, next);
2448         }
2449         return -ENOENT;
2450 }
2451
2452 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2453 {
2454         struct bnxt_filter_info *filter;
2455         struct bnxt_vnic_info *vnic;
2456         int rc = 0;
2457         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2458                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2459         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2460
2461         /* Implementation notes on the use of VNIC in this command:
2462          *
2463          * By default, these filters belong to default vnic for the function.
2464          * Once these filters are set up, only destination VNIC can be modified.
2465          * If the destination VNIC is not specified in this command,
2466          * then the HWRM shall only create an l2 context id.
2467          */
2468
2469         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2470         filter = STAILQ_FIRST(&vnic->filter);
2471         /* Check if the VLAN has already been added */
2472         while (filter) {
2473                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2474                         return -EEXIST;
2475
2476                 filter = STAILQ_NEXT(filter, next);
2477         }
2478
2479         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2480          * command to create MAC+VLAN filter with the right flags, enables set.
2481          */
2482         filter = bnxt_alloc_filter(bp);
2483         if (!filter) {
2484                 PMD_DRV_LOG(ERR,
2485                             "MAC/VLAN filter alloc failed\n");
2486                 return -ENOMEM;
2487         }
2488         /* MAC + VLAN ID filter */
2489         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2490          * untagged packets are received
2491          *
2492          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2493          * packets and only the programmed vlan's packets are received
2494          */
2495         filter->l2_ivlan = vlan_id;
2496         filter->l2_ivlan_mask = 0x0FFF;
2497         filter->enables |= en;
2498         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2499
2500         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2501         if (rc) {
2502                 /* Free the newly allocated filter as we were
2503                  * not able to create the filter in hardware.
2504                  */
2505                 bnxt_free_filter(bp, filter);
2506                 return rc;
2507         }
2508
2509         filter->mac_index = 0;
2510         /* Add this new filter to the list */
2511         if (vlan_id == 0)
2512                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2513         else
2514                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2515
2516         PMD_DRV_LOG(INFO,
2517                     "Added Vlan filter for %d\n", vlan_id);
2518         return rc;
2519 }
2520
2521 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2522                 uint16_t vlan_id, int on)
2523 {
2524         struct bnxt *bp = eth_dev->data->dev_private;
2525         int rc;
2526
2527         rc = is_bnxt_in_error(bp);
2528         if (rc)
2529                 return rc;
2530
2531         if (!eth_dev->data->dev_started) {
2532                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2533                 return -EINVAL;
2534         }
2535
2536         /* These operations apply to ALL existing MAC/VLAN filters */
2537         if (on)
2538                 return bnxt_add_vlan_filter(bp, vlan_id);
2539         else
2540                 return bnxt_del_vlan_filter(bp, vlan_id);
2541 }
2542
2543 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2544                                     struct bnxt_vnic_info *vnic)
2545 {
2546         struct bnxt_filter_info *filter;
2547         int rc;
2548
2549         filter = STAILQ_FIRST(&vnic->filter);
2550         while (filter) {
2551                 if (filter->mac_index == 0 &&
2552                     !memcmp(filter->l2_addr, bp->mac_addr,
2553                             RTE_ETHER_ADDR_LEN)) {
2554                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2555                         if (!rc) {
2556                                 STAILQ_REMOVE(&vnic->filter, filter,
2557                                               bnxt_filter_info, next);
2558                                 bnxt_free_filter(bp, filter);
2559                         }
2560                         return rc;
2561                 }
2562                 filter = STAILQ_NEXT(filter, next);
2563         }
2564         return 0;
2565 }
2566
2567 static int
2568 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2569 {
2570         struct bnxt_vnic_info *vnic;
2571         unsigned int i;
2572         int rc;
2573
2574         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2575         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2576                 /* Remove any VLAN filters programmed */
2577                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2578                         bnxt_del_vlan_filter(bp, i);
2579
2580                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2581                 if (rc)
2582                         return rc;
2583         } else {
2584                 /* Default filter will allow packets that match the
2585                  * dest mac. So, it has to be deleted, otherwise, we
2586                  * will endup receiving vlan packets for which the
2587                  * filter is not programmed, when hw-vlan-filter
2588                  * configuration is ON
2589                  */
2590                 bnxt_del_dflt_mac_filter(bp, vnic);
2591                 /* This filter will allow only untagged packets */
2592                 bnxt_add_vlan_filter(bp, 0);
2593         }
2594         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2595                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2596
2597         return 0;
2598 }
2599
2600 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2601 {
2602         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2603         unsigned int i;
2604         int rc;
2605
2606         /* Destroy vnic filters and vnic */
2607         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2608             DEV_RX_OFFLOAD_VLAN_FILTER) {
2609                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2610                         bnxt_del_vlan_filter(bp, i);
2611         }
2612         bnxt_del_dflt_mac_filter(bp, vnic);
2613
2614         rc = bnxt_hwrm_vnic_ctx_free(bp, vnic);
2615         if (rc)
2616                 return rc;
2617
2618         rc = bnxt_hwrm_vnic_free(bp, vnic);
2619         if (rc)
2620                 return rc;
2621
2622         rte_free(vnic->fw_grp_ids);
2623         vnic->fw_grp_ids = NULL;
2624
2625         vnic->rx_queue_cnt = 0;
2626
2627         return 0;
2628 }
2629
2630 static int
2631 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2632 {
2633         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2634         int rc;
2635
2636         /* Destroy, recreate and reconfigure the default vnic */
2637         rc = bnxt_free_one_vnic(bp, 0);
2638         if (rc)
2639                 return rc;
2640
2641         /* default vnic 0 */
2642         rc = bnxt_setup_one_vnic(bp, 0);
2643         if (rc)
2644                 return rc;
2645
2646         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2647             DEV_RX_OFFLOAD_VLAN_FILTER) {
2648                 rc = bnxt_add_vlan_filter(bp, 0);
2649                 if (rc)
2650                         return rc;
2651                 rc = bnxt_restore_vlan_filters(bp);
2652                 if (rc)
2653                         return rc;
2654         } else {
2655                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2656                 if (rc)
2657                         return rc;
2658         }
2659
2660         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2661         if (rc)
2662                 return rc;
2663
2664         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2665                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2666
2667         return rc;
2668 }
2669
2670 static int
2671 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2672 {
2673         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2674         struct bnxt *bp = dev->data->dev_private;
2675         int rc;
2676
2677         rc = is_bnxt_in_error(bp);
2678         if (rc)
2679                 return rc;
2680
2681         /* Filter settings will get applied when port is started */
2682         if (!dev->data->dev_started)
2683                 return 0;
2684
2685         if (mask & ETH_VLAN_FILTER_MASK) {
2686                 /* Enable or disable VLAN filtering */
2687                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2688                 if (rc)
2689                         return rc;
2690         }
2691
2692         if (mask & ETH_VLAN_STRIP_MASK) {
2693                 /* Enable or disable VLAN stripping */
2694                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2695                 if (rc)
2696                         return rc;
2697         }
2698
2699         if (mask & ETH_VLAN_EXTEND_MASK) {
2700                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2701                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2702                 else
2703                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2704         }
2705
2706         return 0;
2707 }
2708
2709 static int
2710 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2711                       uint16_t tpid)
2712 {
2713         struct bnxt *bp = dev->data->dev_private;
2714         int qinq = dev->data->dev_conf.rxmode.offloads &
2715                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2716
2717         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2718             vlan_type != ETH_VLAN_TYPE_OUTER) {
2719                 PMD_DRV_LOG(ERR,
2720                             "Unsupported vlan type.");
2721                 return -EINVAL;
2722         }
2723         if (!qinq) {
2724                 PMD_DRV_LOG(ERR,
2725                             "QinQ not enabled. Needs to be ON as we can "
2726                             "accelerate only outer vlan\n");
2727                 return -EINVAL;
2728         }
2729
2730         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2731                 switch (tpid) {
2732                 case RTE_ETHER_TYPE_QINQ:
2733                         bp->outer_tpid_bd =
2734                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2735                                 break;
2736                 case RTE_ETHER_TYPE_VLAN:
2737                         bp->outer_tpid_bd =
2738                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2739                                 break;
2740                 case RTE_ETHER_TYPE_QINQ1:
2741                         bp->outer_tpid_bd =
2742                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2743                                 break;
2744                 case RTE_ETHER_TYPE_QINQ2:
2745                         bp->outer_tpid_bd =
2746                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2747                                 break;
2748                 case RTE_ETHER_TYPE_QINQ3:
2749                         bp->outer_tpid_bd =
2750                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2751                                 break;
2752                 default:
2753                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2754                         return -EINVAL;
2755                 }
2756                 bp->outer_tpid_bd |= tpid;
2757                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2758         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2759                 PMD_DRV_LOG(ERR,
2760                             "Can accelerate only outer vlan in QinQ\n");
2761                 return -EINVAL;
2762         }
2763
2764         return 0;
2765 }
2766
2767 static int
2768 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2769                              struct rte_ether_addr *addr)
2770 {
2771         struct bnxt *bp = dev->data->dev_private;
2772         /* Default Filter is tied to VNIC 0 */
2773         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2774         int rc;
2775
2776         rc = is_bnxt_in_error(bp);
2777         if (rc)
2778                 return rc;
2779
2780         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2781                 return -EPERM;
2782
2783         if (rte_is_zero_ether_addr(addr))
2784                 return -EINVAL;
2785
2786         /* Filter settings will get applied when port is started */
2787         if (!dev->data->dev_started)
2788                 return 0;
2789
2790         /* Check if the requested MAC is already added */
2791         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2792                 return 0;
2793
2794         /* Destroy filter and re-create it */
2795         bnxt_del_dflt_mac_filter(bp, vnic);
2796
2797         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2798         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2799                 /* This filter will allow only untagged packets */
2800                 rc = bnxt_add_vlan_filter(bp, 0);
2801         } else {
2802                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2803         }
2804
2805         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2806         return rc;
2807 }
2808
2809 static int
2810 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2811                           struct rte_ether_addr *mc_addr_set,
2812                           uint32_t nb_mc_addr)
2813 {
2814         struct bnxt *bp = eth_dev->data->dev_private;
2815         char *mc_addr_list = (char *)mc_addr_set;
2816         struct bnxt_vnic_info *vnic;
2817         uint32_t off = 0, i = 0;
2818         int rc;
2819
2820         rc = is_bnxt_in_error(bp);
2821         if (rc)
2822                 return rc;
2823
2824         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2825
2826         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2827                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2828                 goto allmulti;
2829         }
2830
2831         /* TODO Check for Duplicate mcast addresses */
2832         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2833         for (i = 0; i < nb_mc_addr; i++) {
2834                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2835                         RTE_ETHER_ADDR_LEN);
2836                 off += RTE_ETHER_ADDR_LEN;
2837         }
2838
2839         vnic->mc_addr_cnt = i;
2840         if (vnic->mc_addr_cnt)
2841                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2842         else
2843                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2844
2845 allmulti:
2846         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2847 }
2848
2849 static int
2850 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2851 {
2852         struct bnxt *bp = dev->data->dev_private;
2853         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2854         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2855         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2856         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2857         int ret;
2858
2859         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2860                         fw_major, fw_minor, fw_updt, fw_rsvd);
2861         if (ret < 0)
2862                 return -EINVAL;
2863
2864         ret += 1; /* add the size of '\0' */
2865         if (fw_size < (size_t)ret)
2866                 return ret;
2867         else
2868                 return 0;
2869 }
2870
2871 static void
2872 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2873         struct rte_eth_rxq_info *qinfo)
2874 {
2875         struct bnxt *bp = dev->data->dev_private;
2876         struct bnxt_rx_queue *rxq;
2877
2878         if (is_bnxt_in_error(bp))
2879                 return;
2880
2881         rxq = dev->data->rx_queues[queue_id];
2882
2883         qinfo->mp = rxq->mb_pool;
2884         qinfo->scattered_rx = dev->data->scattered_rx;
2885         qinfo->nb_desc = rxq->nb_rx_desc;
2886
2887         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2888         qinfo->conf.rx_drop_en = rxq->drop_en;
2889         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2890         qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2891 }
2892
2893 static void
2894 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2895         struct rte_eth_txq_info *qinfo)
2896 {
2897         struct bnxt *bp = dev->data->dev_private;
2898         struct bnxt_tx_queue *txq;
2899
2900         if (is_bnxt_in_error(bp))
2901                 return;
2902
2903         txq = dev->data->tx_queues[queue_id];
2904
2905         qinfo->nb_desc = txq->nb_tx_desc;
2906
2907         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2908         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2909         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2910
2911         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2912         qinfo->conf.tx_rs_thresh = 0;
2913         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2914         qinfo->conf.offloads = txq->offloads;
2915 }
2916
2917 static const struct {
2918         eth_rx_burst_t pkt_burst;
2919         const char *info;
2920 } bnxt_rx_burst_info[] = {
2921         {bnxt_recv_pkts,                "Scalar"},
2922 #if defined(RTE_ARCH_X86)
2923         {bnxt_recv_pkts_vec,            "Vector SSE"},
2924 #endif
2925 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2926         {bnxt_recv_pkts_vec_avx2,       "Vector AVX2"},
2927 #endif
2928 #if defined(RTE_ARCH_ARM64)
2929         {bnxt_recv_pkts_vec,            "Vector Neon"},
2930 #endif
2931 };
2932
2933 static int
2934 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2935                        struct rte_eth_burst_mode *mode)
2936 {
2937         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2938         size_t i;
2939
2940         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2941                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2942                         snprintf(mode->info, sizeof(mode->info), "%s",
2943                                  bnxt_rx_burst_info[i].info);
2944                         return 0;
2945                 }
2946         }
2947
2948         return -EINVAL;
2949 }
2950
2951 static const struct {
2952         eth_tx_burst_t pkt_burst;
2953         const char *info;
2954 } bnxt_tx_burst_info[] = {
2955         {bnxt_xmit_pkts,                "Scalar"},
2956 #if defined(RTE_ARCH_X86)
2957         {bnxt_xmit_pkts_vec,            "Vector SSE"},
2958 #endif
2959 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2960         {bnxt_xmit_pkts_vec_avx2,       "Vector AVX2"},
2961 #endif
2962 #if defined(RTE_ARCH_ARM64)
2963         {bnxt_xmit_pkts_vec,            "Vector Neon"},
2964 #endif
2965 };
2966
2967 static int
2968 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2969                        struct rte_eth_burst_mode *mode)
2970 {
2971         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2972         size_t i;
2973
2974         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2975                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2976                         snprintf(mode->info, sizeof(mode->info), "%s",
2977                                  bnxt_tx_burst_info[i].info);
2978                         return 0;
2979                 }
2980         }
2981
2982         return -EINVAL;
2983 }
2984
2985 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2986 {
2987         struct bnxt *bp = eth_dev->data->dev_private;
2988         uint32_t new_pkt_size;
2989         uint32_t rc = 0;
2990         uint32_t i;
2991
2992         rc = is_bnxt_in_error(bp);
2993         if (rc)
2994                 return rc;
2995
2996         /* Exit if receive queues are not configured yet */
2997         if (!eth_dev->data->nb_rx_queues)
2998                 return rc;
2999
3000         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
3001                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
3002
3003         /*
3004          * Disallow any MTU change that would require scattered receive support
3005          * if it is not already enabled.
3006          */
3007         if (eth_dev->data->dev_started &&
3008             !eth_dev->data->scattered_rx &&
3009             (new_pkt_size >
3010              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
3011                 PMD_DRV_LOG(ERR,
3012                             "MTU change would require scattered rx support. ");
3013                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
3014                 return -EINVAL;
3015         }
3016
3017         if (new_mtu > RTE_ETHER_MTU) {
3018                 bp->flags |= BNXT_FLAG_JUMBO;
3019                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
3020                         DEV_RX_OFFLOAD_JUMBO_FRAME;
3021         } else {
3022                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
3023                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3024                 bp->flags &= ~BNXT_FLAG_JUMBO;
3025         }
3026
3027         /* Is there a change in mtu setting? */
3028         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
3029                 return rc;
3030
3031         for (i = 0; i < bp->nr_vnics; i++) {
3032                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3033                 uint16_t size = 0;
3034
3035                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
3036                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
3037                 if (rc)
3038                         break;
3039
3040                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
3041                 size -= RTE_PKTMBUF_HEADROOM;
3042
3043                 if (size < new_mtu) {
3044                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
3045                         if (rc)
3046                                 return rc;
3047                 }
3048         }
3049
3050         if (!rc)
3051                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
3052
3053         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
3054
3055         return rc;
3056 }
3057
3058 static int
3059 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
3060 {
3061         struct bnxt *bp = dev->data->dev_private;
3062         uint16_t vlan = bp->vlan;
3063         int rc;
3064
3065         rc = is_bnxt_in_error(bp);
3066         if (rc)
3067                 return rc;
3068
3069         if (!BNXT_SINGLE_PF(bp)) {
3070                 PMD_DRV_LOG(ERR, "PVID cannot be modified on VF or on shared PF\n");
3071                 return -ENOTSUP;
3072         }
3073         bp->vlan = on ? pvid : 0;
3074
3075         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
3076         if (rc)
3077                 bp->vlan = vlan;
3078         return rc;
3079 }
3080
3081 static int
3082 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
3083 {
3084         struct bnxt *bp = dev->data->dev_private;
3085         int rc;
3086
3087         rc = is_bnxt_in_error(bp);
3088         if (rc)
3089                 return rc;
3090
3091         return bnxt_hwrm_port_led_cfg(bp, true);
3092 }
3093
3094 static int
3095 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
3096 {
3097         struct bnxt *bp = dev->data->dev_private;
3098         int rc;
3099
3100         rc = is_bnxt_in_error(bp);
3101         if (rc)
3102                 return rc;
3103
3104         return bnxt_hwrm_port_led_cfg(bp, false);
3105 }
3106
3107 static uint32_t
3108 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3109 {
3110         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
3111         struct bnxt_cp_ring_info *cpr;
3112         uint32_t desc = 0, raw_cons;
3113         struct bnxt_rx_queue *rxq;
3114         struct rx_pkt_cmpl *rxcmp;
3115         int rc;
3116
3117         rc = is_bnxt_in_error(bp);
3118         if (rc)
3119                 return rc;
3120
3121         rxq = dev->data->rx_queues[rx_queue_id];
3122         cpr = rxq->cp_ring;
3123         raw_cons = cpr->cp_raw_cons;
3124
3125         while (1) {
3126                 uint32_t agg_cnt, cons, cmpl_type;
3127
3128                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3129                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3130
3131                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3132                         break;
3133
3134                 cmpl_type = CMP_TYPE(rxcmp);
3135
3136                 switch (cmpl_type) {
3137                 case CMPL_BASE_TYPE_RX_L2:
3138                 case CMPL_BASE_TYPE_RX_L2_V2:
3139                         agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3140                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3141                         desc++;
3142                         break;
3143
3144                 case CMPL_BASE_TYPE_RX_TPA_END:
3145                         if (BNXT_CHIP_P5(rxq->bp)) {
3146                                 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3147
3148                                 p5_tpa_end = (void *)rxcmp;
3149                                 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3150                         } else {
3151                                 struct rx_tpa_end_cmpl *tpa_end;
3152
3153                                 tpa_end = (void *)rxcmp;
3154                                 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3155                         }
3156
3157                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3158                         desc++;
3159                         break;
3160
3161                 default:
3162                         raw_cons += CMP_LEN(cmpl_type);
3163                 }
3164         }
3165
3166         return desc;
3167 }
3168
3169 static int
3170 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
3171 {
3172         struct bnxt_rx_queue *rxq = rx_queue;
3173         struct bnxt_cp_ring_info *cpr;
3174         struct bnxt_rx_ring_info *rxr;
3175         uint32_t desc, raw_cons;
3176         struct bnxt *bp = rxq->bp;
3177         struct rx_pkt_cmpl *rxcmp;
3178         int rc;
3179
3180         rc = is_bnxt_in_error(bp);
3181         if (rc)
3182                 return rc;
3183
3184         if (offset >= rxq->nb_rx_desc)
3185                 return -EINVAL;
3186
3187         rxr = rxq->rx_ring;
3188         cpr = rxq->cp_ring;
3189
3190         /*
3191          * For the vector receive case, the completion at the requested
3192          * offset can be indexed directly.
3193          */
3194 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
3195         if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) {
3196                 struct rx_pkt_cmpl *rxcmp;
3197                 uint32_t cons;
3198
3199                 /* Check status of completion descriptor. */
3200                 raw_cons = cpr->cp_raw_cons +
3201                            offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2);
3202                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3203                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3204
3205                 if (CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3206                         return RTE_ETH_RX_DESC_DONE;
3207
3208                 /* Check whether rx desc has an mbuf attached. */
3209                 cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2);
3210                 if (cons >= rxq->rxrearm_start &&
3211                     cons < rxq->rxrearm_start + rxq->rxrearm_nb) {
3212                         return RTE_ETH_RX_DESC_UNAVAIL;
3213                 }
3214
3215                 return RTE_ETH_RX_DESC_AVAIL;
3216         }
3217 #endif
3218
3219         /*
3220          * For the non-vector receive case, scan the completion ring to
3221          * locate the completion descriptor for the requested offset.
3222          */
3223         raw_cons = cpr->cp_raw_cons;
3224         desc = 0;
3225         while (1) {
3226                 uint32_t agg_cnt, cons, cmpl_type;
3227
3228                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3229                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3230
3231                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3232                         break;
3233
3234                 cmpl_type = CMP_TYPE(rxcmp);
3235
3236                 switch (cmpl_type) {
3237                 case CMPL_BASE_TYPE_RX_L2:
3238                 case CMPL_BASE_TYPE_RX_L2_V2:
3239                         if (desc == offset) {
3240                                 cons = rxcmp->opaque;
3241                                 if (rxr->rx_buf_ring[cons])
3242                                         return RTE_ETH_RX_DESC_DONE;
3243                                 else
3244                                         return RTE_ETH_RX_DESC_UNAVAIL;
3245                         }
3246                         agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3247                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3248                         desc++;
3249                         break;
3250
3251                 case CMPL_BASE_TYPE_RX_TPA_END:
3252                         if (desc == offset)
3253                                 return RTE_ETH_RX_DESC_DONE;
3254
3255                         if (BNXT_CHIP_P5(rxq->bp)) {
3256                                 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3257
3258                                 p5_tpa_end = (void *)rxcmp;
3259                                 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3260                         } else {
3261                                 struct rx_tpa_end_cmpl *tpa_end;
3262
3263                                 tpa_end = (void *)rxcmp;
3264                                 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3265                         }
3266
3267                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3268                         desc++;
3269                         break;
3270
3271                 default:
3272                         raw_cons += CMP_LEN(cmpl_type);
3273                 }
3274         }
3275
3276         return RTE_ETH_RX_DESC_AVAIL;
3277 }
3278
3279 static int
3280 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
3281 {
3282         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
3283         struct bnxt_tx_ring_info *txr;
3284         struct bnxt_cp_ring_info *cpr;
3285         struct rte_mbuf **tx_buf;
3286         struct tx_pkt_cmpl *txcmp;
3287         uint32_t cons, cp_cons;
3288         int rc;
3289
3290         if (!txq)
3291                 return -EINVAL;
3292
3293         rc = is_bnxt_in_error(txq->bp);
3294         if (rc)
3295                 return rc;
3296
3297         cpr = txq->cp_ring;
3298         txr = txq->tx_ring;
3299
3300         if (offset >= txq->nb_tx_desc)
3301                 return -EINVAL;
3302
3303         cons = RING_CMP(cpr->cp_ring_struct, offset);
3304         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3305         cp_cons = cpr->cp_raw_cons;
3306
3307         if (cons > cp_cons) {
3308                 if (CMPL_VALID(txcmp, cpr->valid))
3309                         return RTE_ETH_TX_DESC_UNAVAIL;
3310         } else {
3311                 if (CMPL_VALID(txcmp, !cpr->valid))
3312                         return RTE_ETH_TX_DESC_UNAVAIL;
3313         }
3314         tx_buf = &txr->tx_buf_ring[cons];
3315         if (*tx_buf == NULL)
3316                 return RTE_ETH_TX_DESC_DONE;
3317
3318         return RTE_ETH_TX_DESC_FULL;
3319 }
3320
3321 int
3322 bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
3323                      const struct rte_flow_ops **ops)
3324 {
3325         struct bnxt *bp = dev->data->dev_private;
3326         int ret = 0;
3327
3328         if (!bp)
3329                 return -EIO;
3330
3331         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3332                 struct bnxt_representor *vfr = dev->data->dev_private;
3333                 bp = vfr->parent_dev->data->dev_private;
3334                 /* parent is deleted while children are still valid */
3335                 if (!bp) {
3336                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error\n",
3337                                     dev->data->port_id);
3338                         return -EIO;
3339                 }
3340         }
3341
3342         ret = is_bnxt_in_error(bp);
3343         if (ret)
3344                 return ret;
3345
3346         /* PMD supports thread-safe flow operations.  rte_flow API
3347          * functions can avoid mutex for multi-thread safety.
3348          */
3349         dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3350
3351         if (BNXT_TRUFLOW_EN(bp))
3352                 *ops = &bnxt_ulp_rte_flow_ops;
3353         else
3354                 *ops = &bnxt_flow_ops;
3355
3356         return ret;
3357 }
3358
3359 static const uint32_t *
3360 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3361 {
3362         static const uint32_t ptypes[] = {
3363                 RTE_PTYPE_L2_ETHER_VLAN,
3364                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3365                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3366                 RTE_PTYPE_L4_ICMP,
3367                 RTE_PTYPE_L4_TCP,
3368                 RTE_PTYPE_L4_UDP,
3369                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3370                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3371                 RTE_PTYPE_INNER_L4_ICMP,
3372                 RTE_PTYPE_INNER_L4_TCP,
3373                 RTE_PTYPE_INNER_L4_UDP,
3374                 RTE_PTYPE_UNKNOWN
3375         };
3376
3377         if (!dev->rx_pkt_burst)
3378                 return NULL;
3379
3380         return ptypes;
3381 }
3382
3383 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3384                          int reg_win)
3385 {
3386         uint32_t reg_base = *reg_arr & 0xfffff000;
3387         uint32_t win_off;
3388         int i;
3389
3390         for (i = 0; i < count; i++) {
3391                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3392                         return -ERANGE;
3393         }
3394         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3395         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3396         return 0;
3397 }
3398
3399 static int bnxt_map_ptp_regs(struct bnxt *bp)
3400 {
3401         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3402         uint32_t *reg_arr;
3403         int rc, i;
3404
3405         reg_arr = ptp->rx_regs;
3406         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3407         if (rc)
3408                 return rc;
3409
3410         reg_arr = ptp->tx_regs;
3411         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3412         if (rc)
3413                 return rc;
3414
3415         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3416                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3417
3418         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3419                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3420
3421         return 0;
3422 }
3423
3424 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3425 {
3426         rte_write32(0, (uint8_t *)bp->bar0 +
3427                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3428         rte_write32(0, (uint8_t *)bp->bar0 +
3429                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3430 }
3431
3432 static uint64_t bnxt_cc_read(struct bnxt *bp)
3433 {
3434         uint64_t ns;
3435
3436         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3437                               BNXT_GRCPF_REG_SYNC_TIME));
3438         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3439                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3440         return ns;
3441 }
3442
3443 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3444 {
3445         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3446         uint32_t fifo;
3447
3448         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3449                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3450         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3451                 return -EAGAIN;
3452
3453         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3454                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3455         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3456                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3457         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3458                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3459         rte_read32((uint8_t *)bp->bar0 + ptp->tx_mapped_regs[BNXT_PTP_TX_SEQ]);
3460
3461         return 0;
3462 }
3463
3464 static int bnxt_clr_rx_ts(struct bnxt *bp, uint64_t *last_ts)
3465 {
3466         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3467         struct bnxt_pf_info *pf = bp->pf;
3468         uint16_t port_id;
3469         int i = 0;
3470         uint32_t fifo;
3471
3472         if (!ptp || (bp->flags & BNXT_FLAG_CHIP_P5))
3473                 return -EINVAL;
3474
3475         port_id = pf->port_id;
3476         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3477                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3478         while ((fifo & BNXT_PTP_RX_FIFO_PENDING) && (i < BNXT_PTP_RX_PND_CNT)) {
3479                 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3480                             ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3481                 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3482                                         ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3483                 *last_ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3484                                         ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3485                 *last_ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3486                                         ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3487                 i++;
3488         }
3489
3490         if (i >= BNXT_PTP_RX_PND_CNT)
3491                 return -EBUSY;
3492
3493         return 0;
3494 }
3495
3496 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3497 {
3498         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3499         struct bnxt_pf_info *pf = bp->pf;
3500         uint16_t port_id;
3501         uint32_t fifo;
3502
3503         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3504                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3505         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3506                 return -EAGAIN;
3507
3508         port_id = pf->port_id;
3509         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3510                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3511
3512         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3513                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3514         if (fifo & BNXT_PTP_RX_FIFO_PENDING)
3515                 return bnxt_clr_rx_ts(bp, ts);
3516
3517         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3518                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3519         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3520                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3521
3522         return 0;
3523 }
3524
3525 static int
3526 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3527 {
3528         uint64_t ns;
3529         struct bnxt *bp = dev->data->dev_private;
3530         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3531
3532         if (!ptp)
3533                 return -ENOTSUP;
3534
3535         ns = rte_timespec_to_ns(ts);
3536         /* Set the timecounters to a new value. */
3537         ptp->tc.nsec = ns;
3538         ptp->tx_tstamp_tc.nsec = ns;
3539         ptp->rx_tstamp_tc.nsec = ns;
3540
3541         return 0;
3542 }
3543
3544 static int
3545 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3546 {
3547         struct bnxt *bp = dev->data->dev_private;
3548         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3549         uint64_t ns, systime_cycles = 0;
3550         int rc = 0;
3551
3552         if (!ptp)
3553                 return -ENOTSUP;
3554
3555         if (BNXT_CHIP_P5(bp))
3556                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3557                                              &systime_cycles);
3558         else
3559                 systime_cycles = bnxt_cc_read(bp);
3560
3561         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3562         *ts = rte_ns_to_timespec(ns);
3563
3564         return rc;
3565 }
3566 static int
3567 bnxt_timesync_enable(struct rte_eth_dev *dev)
3568 {
3569         struct bnxt *bp = dev->data->dev_private;
3570         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3571         uint32_t shift = 0;
3572         int rc;
3573
3574         if (!ptp)
3575                 return -ENOTSUP;
3576
3577         ptp->rx_filter = 1;
3578         ptp->tx_tstamp_en = 1;
3579         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3580
3581         rc = bnxt_hwrm_ptp_cfg(bp);
3582         if (rc)
3583                 return rc;
3584
3585         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3586         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3587         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3588
3589         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3590         ptp->tc.cc_shift = shift;
3591         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3592
3593         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3594         ptp->rx_tstamp_tc.cc_shift = shift;
3595         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3596
3597         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3598         ptp->tx_tstamp_tc.cc_shift = shift;
3599         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3600
3601         if (!BNXT_CHIP_P5(bp))
3602                 bnxt_map_ptp_regs(bp);
3603         else
3604                 rc = bnxt_ptp_start(bp);
3605
3606         return rc;
3607 }
3608
3609 static int
3610 bnxt_timesync_disable(struct rte_eth_dev *dev)
3611 {
3612         struct bnxt *bp = dev->data->dev_private;
3613         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3614
3615         if (!ptp)
3616                 return -ENOTSUP;
3617
3618         ptp->rx_filter = 0;
3619         ptp->tx_tstamp_en = 0;
3620         ptp->rxctl = 0;
3621
3622         bnxt_hwrm_ptp_cfg(bp);
3623
3624         if (!BNXT_CHIP_P5(bp))
3625                 bnxt_unmap_ptp_regs(bp);
3626         else
3627                 bnxt_ptp_stop(bp);
3628
3629         return 0;
3630 }
3631
3632 static int
3633 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3634                                  struct timespec *timestamp,
3635                                  uint32_t flags __rte_unused)
3636 {
3637         struct bnxt *bp = dev->data->dev_private;
3638         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3639         uint64_t rx_tstamp_cycles = 0;
3640         uint64_t ns;
3641
3642         if (!ptp)
3643                 return -ENOTSUP;
3644
3645         if (BNXT_CHIP_P5(bp))
3646                 rx_tstamp_cycles = ptp->rx_timestamp;
3647         else
3648                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3649
3650         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3651         *timestamp = rte_ns_to_timespec(ns);
3652         return  0;
3653 }
3654
3655 static int
3656 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3657                                  struct timespec *timestamp)
3658 {
3659         struct bnxt *bp = dev->data->dev_private;
3660         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3661         uint64_t tx_tstamp_cycles = 0;
3662         uint64_t ns;
3663         int rc = 0;
3664
3665         if (!ptp)
3666                 return -ENOTSUP;
3667
3668         if (BNXT_CHIP_P5(bp))
3669                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3670                                              &tx_tstamp_cycles);
3671         else
3672                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3673
3674         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3675         *timestamp = rte_ns_to_timespec(ns);
3676
3677         return rc;
3678 }
3679
3680 static int
3681 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3682 {
3683         struct bnxt *bp = dev->data->dev_private;
3684         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3685
3686         if (!ptp)
3687                 return -ENOTSUP;
3688
3689         ptp->tc.nsec += delta;
3690         ptp->tx_tstamp_tc.nsec += delta;
3691         ptp->rx_tstamp_tc.nsec += delta;
3692
3693         return 0;
3694 }
3695
3696 static int
3697 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3698 {
3699         struct bnxt *bp = dev->data->dev_private;
3700         int rc;
3701         uint32_t dir_entries;
3702         uint32_t entry_length;
3703
3704         rc = is_bnxt_in_error(bp);
3705         if (rc)
3706                 return rc;
3707
3708         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3709                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3710                     bp->pdev->addr.devid, bp->pdev->addr.function);
3711
3712         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3713         if (rc != 0)
3714                 return rc;
3715
3716         return dir_entries * entry_length;
3717 }
3718
3719 static int
3720 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3721                 struct rte_dev_eeprom_info *in_eeprom)
3722 {
3723         struct bnxt *bp = dev->data->dev_private;
3724         uint32_t index;
3725         uint32_t offset;
3726         int rc;
3727
3728         rc = is_bnxt_in_error(bp);
3729         if (rc)
3730                 return rc;
3731
3732         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3733                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3734                     bp->pdev->addr.devid, bp->pdev->addr.function,
3735                     in_eeprom->offset, in_eeprom->length);
3736
3737         if (in_eeprom->offset == 0) /* special offset value to get directory */
3738                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3739                                                 in_eeprom->data);
3740
3741         index = in_eeprom->offset >> 24;
3742         offset = in_eeprom->offset & 0xffffff;
3743
3744         if (index != 0)
3745                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3746                                            in_eeprom->length, in_eeprom->data);
3747
3748         return 0;
3749 }
3750
3751 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3752 {
3753         switch (dir_type) {
3754         case BNX_DIR_TYPE_CHIMP_PATCH:
3755         case BNX_DIR_TYPE_BOOTCODE:
3756         case BNX_DIR_TYPE_BOOTCODE_2:
3757         case BNX_DIR_TYPE_APE_FW:
3758         case BNX_DIR_TYPE_APE_PATCH:
3759         case BNX_DIR_TYPE_KONG_FW:
3760         case BNX_DIR_TYPE_KONG_PATCH:
3761         case BNX_DIR_TYPE_BONO_FW:
3762         case BNX_DIR_TYPE_BONO_PATCH:
3763                 /* FALLTHROUGH */
3764                 return true;
3765         }
3766
3767         return false;
3768 }
3769
3770 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3771 {
3772         switch (dir_type) {
3773         case BNX_DIR_TYPE_AVS:
3774         case BNX_DIR_TYPE_EXP_ROM_MBA:
3775         case BNX_DIR_TYPE_PCIE:
3776         case BNX_DIR_TYPE_TSCF_UCODE:
3777         case BNX_DIR_TYPE_EXT_PHY:
3778         case BNX_DIR_TYPE_CCM:
3779         case BNX_DIR_TYPE_ISCSI_BOOT:
3780         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3781         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3782                 /* FALLTHROUGH */
3783                 return true;
3784         }
3785
3786         return false;
3787 }
3788
3789 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3790 {
3791         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3792                 bnxt_dir_type_is_other_exec_format(dir_type);
3793 }
3794
3795 static int
3796 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3797                 struct rte_dev_eeprom_info *in_eeprom)
3798 {
3799         struct bnxt *bp = dev->data->dev_private;
3800         uint8_t index, dir_op;
3801         uint16_t type, ext, ordinal, attr;
3802         int rc;
3803
3804         rc = is_bnxt_in_error(bp);
3805         if (rc)
3806                 return rc;
3807
3808         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3809                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3810                     bp->pdev->addr.devid, bp->pdev->addr.function,
3811                     in_eeprom->offset, in_eeprom->length);
3812
3813         if (!BNXT_PF(bp)) {
3814                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3815                 return -EINVAL;
3816         }
3817
3818         type = in_eeprom->magic >> 16;
3819
3820         if (type == 0xffff) { /* special value for directory operations */
3821                 index = in_eeprom->magic & 0xff;
3822                 dir_op = in_eeprom->magic >> 8;
3823                 if (index == 0)
3824                         return -EINVAL;
3825                 switch (dir_op) {
3826                 case 0x0e: /* erase */
3827                         if (in_eeprom->offset != ~in_eeprom->magic)
3828                                 return -EINVAL;
3829                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3830                 default:
3831                         return -EINVAL;
3832                 }
3833         }
3834
3835         /* Create or re-write an NVM item: */
3836         if (bnxt_dir_type_is_executable(type) == true)
3837                 return -EOPNOTSUPP;
3838         ext = in_eeprom->magic & 0xffff;
3839         ordinal = in_eeprom->offset >> 16;
3840         attr = in_eeprom->offset & 0xffff;
3841
3842         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3843                                      in_eeprom->data, in_eeprom->length);
3844 }
3845
3846 /*
3847  * Initialization
3848  */
3849
3850 static const struct eth_dev_ops bnxt_dev_ops = {
3851         .dev_infos_get = bnxt_dev_info_get_op,
3852         .dev_close = bnxt_dev_close_op,
3853         .dev_configure = bnxt_dev_configure_op,
3854         .dev_start = bnxt_dev_start_op,
3855         .dev_stop = bnxt_dev_stop_op,
3856         .dev_set_link_up = bnxt_dev_set_link_up_op,
3857         .dev_set_link_down = bnxt_dev_set_link_down_op,
3858         .stats_get = bnxt_stats_get_op,
3859         .stats_reset = bnxt_stats_reset_op,
3860         .rx_queue_setup = bnxt_rx_queue_setup_op,
3861         .rx_queue_release = bnxt_rx_queue_release_op,
3862         .tx_queue_setup = bnxt_tx_queue_setup_op,
3863         .tx_queue_release = bnxt_tx_queue_release_op,
3864         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3865         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3866         .reta_update = bnxt_reta_update_op,
3867         .reta_query = bnxt_reta_query_op,
3868         .rss_hash_update = bnxt_rss_hash_update_op,
3869         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3870         .link_update = bnxt_link_update_op,
3871         .promiscuous_enable = bnxt_promiscuous_enable_op,
3872         .promiscuous_disable = bnxt_promiscuous_disable_op,
3873         .allmulticast_enable = bnxt_allmulticast_enable_op,
3874         .allmulticast_disable = bnxt_allmulticast_disable_op,
3875         .mac_addr_add = bnxt_mac_addr_add_op,
3876         .mac_addr_remove = bnxt_mac_addr_remove_op,
3877         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3878         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3879         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3880         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3881         .vlan_filter_set = bnxt_vlan_filter_set_op,
3882         .vlan_offload_set = bnxt_vlan_offload_set_op,
3883         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3884         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3885         .mtu_set = bnxt_mtu_set_op,
3886         .mac_addr_set = bnxt_set_default_mac_addr_op,
3887         .xstats_get = bnxt_dev_xstats_get_op,
3888         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3889         .xstats_reset = bnxt_dev_xstats_reset_op,
3890         .fw_version_get = bnxt_fw_version_get,
3891         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3892         .rxq_info_get = bnxt_rxq_info_get_op,
3893         .txq_info_get = bnxt_txq_info_get_op,
3894         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
3895         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
3896         .dev_led_on = bnxt_dev_led_on_op,
3897         .dev_led_off = bnxt_dev_led_off_op,
3898         .rx_queue_start = bnxt_rx_queue_start,
3899         .rx_queue_stop = bnxt_rx_queue_stop,
3900         .tx_queue_start = bnxt_tx_queue_start,
3901         .tx_queue_stop = bnxt_tx_queue_stop,
3902         .flow_ops_get = bnxt_flow_ops_get_op,
3903         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3904         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3905         .get_eeprom           = bnxt_get_eeprom_op,
3906         .set_eeprom           = bnxt_set_eeprom_op,
3907         .timesync_enable      = bnxt_timesync_enable,
3908         .timesync_disable     = bnxt_timesync_disable,
3909         .timesync_read_time   = bnxt_timesync_read_time,
3910         .timesync_write_time   = bnxt_timesync_write_time,
3911         .timesync_adjust_time = bnxt_timesync_adjust_time,
3912         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3913         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3914 };
3915
3916 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3917 {
3918         uint32_t offset;
3919
3920         /* Only pre-map the reset GRC registers using window 3 */
3921         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3922                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3923
3924         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3925
3926         return offset;
3927 }
3928
3929 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3930 {
3931         struct bnxt_error_recovery_info *info = bp->recovery_info;
3932         uint32_t reg_base = 0xffffffff;
3933         int i;
3934
3935         /* Only pre-map the monitoring GRC registers using window 2 */
3936         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3937                 uint32_t reg = info->status_regs[i];
3938
3939                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3940                         continue;
3941
3942                 if (reg_base == 0xffffffff)
3943                         reg_base = reg & 0xfffff000;
3944                 if ((reg & 0xfffff000) != reg_base)
3945                         return -ERANGE;
3946
3947                 /* Use mask 0xffc as the Lower 2 bits indicates
3948                  * address space location
3949                  */
3950                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3951                                                 (reg & 0xffc);
3952         }
3953
3954         if (reg_base == 0xffffffff)
3955                 return 0;
3956
3957         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3958                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3959
3960         return 0;
3961 }
3962
3963 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3964 {
3965         struct bnxt_error_recovery_info *info = bp->recovery_info;
3966         uint32_t delay = info->delay_after_reset[index];
3967         uint32_t val = info->reset_reg_val[index];
3968         uint32_t reg = info->reset_reg[index];
3969         uint32_t type, offset;
3970         int ret;
3971
3972         type = BNXT_FW_STATUS_REG_TYPE(reg);
3973         offset = BNXT_FW_STATUS_REG_OFF(reg);
3974
3975         switch (type) {
3976         case BNXT_FW_STATUS_REG_TYPE_CFG:
3977                 ret = rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3978                 if (ret < 0) {
3979                         PMD_DRV_LOG(ERR, "Failed to write %#x at PCI offset %#x",
3980                                     val, offset);
3981                         return;
3982                 }
3983                 break;
3984         case BNXT_FW_STATUS_REG_TYPE_GRC:
3985                 offset = bnxt_map_reset_regs(bp, offset);
3986                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3987                 break;
3988         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3989                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3990                 break;
3991         }
3992         /* wait on a specific interval of time until core reset is complete */
3993         if (delay)
3994                 rte_delay_ms(delay);
3995 }
3996
3997 static void bnxt_dev_cleanup(struct bnxt *bp)
3998 {
3999         bp->eth_dev->data->dev_link.link_status = 0;
4000         bp->link_info->link_up = 0;
4001         if (bp->eth_dev->data->dev_started)
4002                 bnxt_dev_stop(bp->eth_dev);
4003
4004         bnxt_uninit_resources(bp, true);
4005 }
4006
4007 static int
4008 bnxt_check_fw_reset_done(struct bnxt *bp)
4009 {
4010         int timeout = bp->fw_reset_max_msecs;
4011         uint16_t val = 0;
4012         int rc;
4013
4014         do {
4015                 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4016                 if (rc < 0) {
4017                         PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4018                         return rc;
4019                 }
4020                 if (val != 0xffff)
4021                         break;
4022                 rte_delay_ms(1);
4023         } while (timeout--);
4024
4025         if (val == 0xffff) {
4026                 PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n");
4027                 return -1;
4028         }
4029
4030         return 0;
4031 }
4032
4033 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4034 {
4035         struct rte_eth_dev *dev = bp->eth_dev;
4036         struct rte_vlan_filter_conf *vfc;
4037         int vidx, vbit, rc;
4038         uint16_t vlan_id;
4039
4040         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4041                 vfc = &dev->data->vlan_filter_conf;
4042                 vidx = vlan_id / 64;
4043                 vbit = vlan_id % 64;
4044
4045                 /* Each bit corresponds to a VLAN id */
4046                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4047                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4048                         if (rc)
4049                                 return rc;
4050                 }
4051         }
4052
4053         return 0;
4054 }
4055
4056 static int bnxt_restore_mac_filters(struct bnxt *bp)
4057 {
4058         struct rte_eth_dev *dev = bp->eth_dev;
4059         struct rte_eth_dev_info dev_info;
4060         struct rte_ether_addr *addr;
4061         uint64_t pool_mask;
4062         uint32_t pool = 0;
4063         uint32_t i;
4064         int rc;
4065
4066         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4067                 return 0;
4068
4069         rc = bnxt_dev_info_get_op(dev, &dev_info);
4070         if (rc)
4071                 return rc;
4072
4073         /* replay MAC address configuration */
4074         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4075                 addr = &dev->data->mac_addrs[i];
4076
4077                 /* skip zero address */
4078                 if (rte_is_zero_ether_addr(addr))
4079                         continue;
4080
4081                 pool = 0;
4082                 pool_mask = dev->data->mac_pool_sel[i];
4083
4084                 do {
4085                         if (pool_mask & 1ULL) {
4086                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4087                                 if (rc)
4088                                         return rc;
4089                         }
4090                         pool_mask >>= 1;
4091                         pool++;
4092                 } while (pool_mask);
4093         }
4094
4095         return 0;
4096 }
4097
4098 static int bnxt_restore_filters(struct bnxt *bp)
4099 {
4100         struct rte_eth_dev *dev = bp->eth_dev;
4101         int ret = 0;
4102
4103         if (dev->data->all_multicast) {
4104                 ret = bnxt_allmulticast_enable_op(dev);
4105                 if (ret)
4106                         return ret;
4107         }
4108         if (dev->data->promiscuous) {
4109                 ret = bnxt_promiscuous_enable_op(dev);
4110                 if (ret)
4111                         return ret;
4112         }
4113
4114         ret = bnxt_restore_mac_filters(bp);
4115         if (ret)
4116                 return ret;
4117
4118         ret = bnxt_restore_vlan_filters(bp);
4119         /* TODO restore other filters as well */
4120         return ret;
4121 }
4122
4123 static int bnxt_check_fw_ready(struct bnxt *bp)
4124 {
4125         int timeout = bp->fw_reset_max_msecs;
4126         int rc = 0;
4127
4128         do {
4129                 rc = bnxt_hwrm_poll_ver_get(bp);
4130                 if (rc == 0)
4131                         break;
4132                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4133                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4134         } while (rc && timeout > 0);
4135
4136         if (rc)
4137                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4138
4139         return rc;
4140 }
4141
4142 static void bnxt_dev_recover(void *arg)
4143 {
4144         struct bnxt *bp = arg;
4145         int rc = 0;
4146
4147         pthread_mutex_lock(&bp->err_recovery_lock);
4148
4149         if (!bp->fw_reset_min_msecs) {
4150                 rc = bnxt_check_fw_reset_done(bp);
4151                 if (rc)
4152                         goto err;
4153         }
4154
4155         /* Clear Error flag so that device re-init should happen */
4156         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4157
4158         rc = bnxt_check_fw_ready(bp);
4159         if (rc)
4160                 goto err;
4161
4162         rc = bnxt_init_resources(bp, true);
4163         if (rc) {
4164                 PMD_DRV_LOG(ERR,
4165                             "Failed to initialize resources after reset\n");
4166                 goto err;
4167         }
4168         /* clear reset flag as the device is initialized now */
4169         bp->flags &= ~BNXT_FLAG_FW_RESET;
4170
4171         rc = bnxt_dev_start_op(bp->eth_dev);
4172         if (rc) {
4173                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4174                 goto err_start;
4175         }
4176
4177         rc = bnxt_restore_filters(bp);
4178         if (rc)
4179                 goto err_start;
4180
4181         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4182         pthread_mutex_unlock(&bp->err_recovery_lock);
4183
4184         return;
4185 err_start:
4186         bnxt_dev_stop(bp->eth_dev);
4187 err:
4188         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4189         bnxt_uninit_resources(bp, false);
4190         pthread_mutex_unlock(&bp->err_recovery_lock);
4191         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4192 }
4193
4194 void bnxt_dev_reset_and_resume(void *arg)
4195 {
4196         struct bnxt *bp = arg;
4197         uint32_t us = US_PER_MS * bp->fw_reset_min_msecs;
4198         uint16_t val = 0;
4199         int rc;
4200
4201         bnxt_dev_cleanup(bp);
4202
4203         bnxt_wait_for_device_shutdown(bp);
4204
4205         /* During some fatal firmware error conditions, the PCI config space
4206          * register 0x2e which normally contains the subsystem ID will become
4207          * 0xffff. This register will revert back to the normal value after
4208          * the chip has completed core reset. If we detect this condition,
4209          * we can poll this config register immediately for the value to revert.
4210          */
4211         if (bp->flags & BNXT_FLAG_FATAL_ERROR) {
4212                 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4213                 if (rc < 0) {
4214                         PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4215                         return;
4216                 }
4217                 if (val == 0xffff) {
4218                         bp->fw_reset_min_msecs = 0;
4219                         us = 1;
4220                 }
4221         }
4222
4223         rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp);
4224         if (rc)
4225                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4226 }
4227
4228 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4229 {
4230         struct bnxt_error_recovery_info *info = bp->recovery_info;
4231         uint32_t reg = info->status_regs[index];
4232         uint32_t type, offset, val = 0;
4233         int ret = 0;
4234
4235         type = BNXT_FW_STATUS_REG_TYPE(reg);
4236         offset = BNXT_FW_STATUS_REG_OFF(reg);
4237
4238         switch (type) {
4239         case BNXT_FW_STATUS_REG_TYPE_CFG:
4240                 ret = rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4241                 if (ret < 0)
4242                         PMD_DRV_LOG(ERR, "Failed to read PCI offset %#x",
4243                                     offset);
4244                 break;
4245         case BNXT_FW_STATUS_REG_TYPE_GRC:
4246                 offset = info->mapped_status_regs[index];
4247                 /* FALLTHROUGH */
4248         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4249                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4250                                        offset));
4251                 break;
4252         }
4253
4254         return val;
4255 }
4256
4257 static int bnxt_fw_reset_all(struct bnxt *bp)
4258 {
4259         struct bnxt_error_recovery_info *info = bp->recovery_info;
4260         uint32_t i;
4261         int rc = 0;
4262
4263         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4264                 /* Reset through master function driver */
4265                 for (i = 0; i < info->reg_array_cnt; i++)
4266                         bnxt_write_fw_reset_reg(bp, i);
4267                 /* Wait for time specified by FW after triggering reset */
4268                 rte_delay_ms(info->master_func_wait_period_after_reset);
4269         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4270                 /* Reset with the help of Kong processor */
4271                 rc = bnxt_hwrm_fw_reset(bp);
4272                 if (rc)
4273                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4274         }
4275
4276         return rc;
4277 }
4278
4279 static void bnxt_fw_reset_cb(void *arg)
4280 {
4281         struct bnxt *bp = arg;
4282         struct bnxt_error_recovery_info *info = bp->recovery_info;
4283         int rc = 0;
4284
4285         /* Only Master function can do FW reset */
4286         if (bnxt_is_master_func(bp) &&
4287             bnxt_is_recovery_enabled(bp)) {
4288                 rc = bnxt_fw_reset_all(bp);
4289                 if (rc) {
4290                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4291                         return;
4292                 }
4293         }
4294
4295         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4296          * EXCEPTION_FATAL_ASYNC event to all the functions
4297          * (including MASTER FUNC). After receiving this Async, all the active
4298          * drivers should treat this case as FW initiated recovery
4299          */
4300         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4301                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4302                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4303
4304                 /* To recover from error */
4305                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4306                                   (void *)bp);
4307         }
4308 }
4309
4310 /* Driver should poll FW heartbeat, reset_counter with the frequency
4311  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4312  * When the driver detects heartbeat stop or change in reset_counter,
4313  * it has to trigger a reset to recover from the error condition.
4314  * A “master PF” is the function who will have the privilege to
4315  * initiate the chimp reset. The master PF will be elected by the
4316  * firmware and will be notified through async message.
4317  */
4318 static void bnxt_check_fw_health(void *arg)
4319 {
4320         struct bnxt *bp = arg;
4321         struct bnxt_error_recovery_info *info = bp->recovery_info;
4322         uint32_t val = 0, wait_msec;
4323
4324         if (!info || !bnxt_is_recovery_enabled(bp) ||
4325             is_bnxt_in_error(bp))
4326                 return;
4327
4328         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4329         if (val == info->last_heart_beat)
4330                 goto reset;
4331
4332         info->last_heart_beat = val;
4333
4334         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4335         if (val != info->last_reset_counter)
4336                 goto reset;
4337
4338         info->last_reset_counter = val;
4339
4340         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4341                           bnxt_check_fw_health, (void *)bp);
4342
4343         return;
4344 reset:
4345         /* Stop DMA to/from device */
4346         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4347         bp->flags |= BNXT_FLAG_FW_RESET;
4348
4349         bnxt_stop_rxtx(bp);
4350
4351         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4352
4353         if (bnxt_is_master_func(bp))
4354                 wait_msec = info->master_func_wait_period;
4355         else
4356                 wait_msec = info->normal_func_wait_period;
4357
4358         rte_eal_alarm_set(US_PER_MS * wait_msec,
4359                           bnxt_fw_reset_cb, (void *)bp);
4360 }
4361
4362 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4363 {
4364         uint32_t polling_freq;
4365
4366         pthread_mutex_lock(&bp->health_check_lock);
4367
4368         if (!bnxt_is_recovery_enabled(bp))
4369                 goto done;
4370
4371         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4372                 goto done;
4373
4374         polling_freq = bp->recovery_info->driver_polling_freq;
4375
4376         rte_eal_alarm_set(US_PER_MS * polling_freq,
4377                           bnxt_check_fw_health, (void *)bp);
4378         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4379
4380 done:
4381         pthread_mutex_unlock(&bp->health_check_lock);
4382 }
4383
4384 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4385 {
4386         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4387         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4388 }
4389
4390 static bool bnxt_vf_pciid(uint16_t device_id)
4391 {
4392         switch (device_id) {
4393         case BROADCOM_DEV_ID_57304_VF:
4394         case BROADCOM_DEV_ID_57406_VF:
4395         case BROADCOM_DEV_ID_5731X_VF:
4396         case BROADCOM_DEV_ID_5741X_VF:
4397         case BROADCOM_DEV_ID_57414_VF:
4398         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4399         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4400         case BROADCOM_DEV_ID_58802_VF:
4401         case BROADCOM_DEV_ID_57500_VF1:
4402         case BROADCOM_DEV_ID_57500_VF2:
4403         case BROADCOM_DEV_ID_58818_VF:
4404                 /* FALLTHROUGH */
4405                 return true;
4406         default:
4407                 return false;
4408         }
4409 }
4410
4411 /* Phase 5 device */
4412 static bool bnxt_p5_device(uint16_t device_id)
4413 {
4414         switch (device_id) {
4415         case BROADCOM_DEV_ID_57508:
4416         case BROADCOM_DEV_ID_57504:
4417         case BROADCOM_DEV_ID_57502:
4418         case BROADCOM_DEV_ID_57508_MF1:
4419         case BROADCOM_DEV_ID_57504_MF1:
4420         case BROADCOM_DEV_ID_57502_MF1:
4421         case BROADCOM_DEV_ID_57508_MF2:
4422         case BROADCOM_DEV_ID_57504_MF2:
4423         case BROADCOM_DEV_ID_57502_MF2:
4424         case BROADCOM_DEV_ID_57500_VF1:
4425         case BROADCOM_DEV_ID_57500_VF2:
4426         case BROADCOM_DEV_ID_58812:
4427         case BROADCOM_DEV_ID_58814:
4428         case BROADCOM_DEV_ID_58818:
4429         case BROADCOM_DEV_ID_58818_VF:
4430                 /* FALLTHROUGH */
4431                 return true;
4432         default:
4433                 return false;
4434         }
4435 }
4436
4437 bool bnxt_stratus_device(struct bnxt *bp)
4438 {
4439         uint16_t device_id = bp->pdev->id.device_id;
4440
4441         switch (device_id) {
4442         case BROADCOM_DEV_ID_STRATUS_NIC:
4443         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4444         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4445                 /* FALLTHROUGH */
4446                 return true;
4447         default:
4448                 return false;
4449         }
4450 }
4451
4452 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev)
4453 {
4454         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4455         struct bnxt *bp = eth_dev->data->dev_private;
4456
4457         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4458         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4459         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4460         if (!bp->bar0 || !bp->doorbell_base) {
4461                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4462                 return -ENODEV;
4463         }
4464
4465         bp->eth_dev = eth_dev;
4466         bp->pdev = pci_dev;
4467
4468         return 0;
4469 }
4470
4471 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4472                                   struct bnxt_ctx_pg_info *ctx_pg,
4473                                   uint32_t mem_size,
4474                                   const char *suffix,
4475                                   uint16_t idx)
4476 {
4477         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4478         const struct rte_memzone *mz = NULL;
4479         char mz_name[RTE_MEMZONE_NAMESIZE];
4480         rte_iova_t mz_phys_addr;
4481         uint64_t valid_bits = 0;
4482         uint32_t sz;
4483         int i;
4484
4485         if (!mem_size)
4486                 return 0;
4487
4488         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4489                          BNXT_PAGE_SIZE;
4490         rmem->page_size = BNXT_PAGE_SIZE;
4491         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4492         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4493         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4494
4495         valid_bits = PTU_PTE_VALID;
4496
4497         if (rmem->nr_pages > 1) {
4498                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4499                          "bnxt_ctx_pg_tbl%s_%x_%d",
4500                          suffix, idx, bp->eth_dev->data->port_id);
4501                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4502                 mz = rte_memzone_lookup(mz_name);
4503                 if (!mz) {
4504                         mz = rte_memzone_reserve_aligned(mz_name,
4505                                                 rmem->nr_pages * 8,
4506                                                 SOCKET_ID_ANY,
4507                                                 RTE_MEMZONE_2MB |
4508                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4509                                                 RTE_MEMZONE_IOVA_CONTIG,
4510                                                 BNXT_PAGE_SIZE);
4511                         if (mz == NULL)
4512                                 return -ENOMEM;
4513                 }
4514
4515                 memset(mz->addr, 0, mz->len);
4516                 mz_phys_addr = mz->iova;
4517
4518                 rmem->pg_tbl = mz->addr;
4519                 rmem->pg_tbl_map = mz_phys_addr;
4520                 rmem->pg_tbl_mz = mz;
4521         }
4522
4523         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4524                  suffix, idx, bp->eth_dev->data->port_id);
4525         mz = rte_memzone_lookup(mz_name);
4526         if (!mz) {
4527                 mz = rte_memzone_reserve_aligned(mz_name,
4528                                                  mem_size,
4529                                                  SOCKET_ID_ANY,
4530                                                  RTE_MEMZONE_1GB |
4531                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4532                                                  RTE_MEMZONE_IOVA_CONTIG,
4533                                                  BNXT_PAGE_SIZE);
4534                 if (mz == NULL)
4535                         return -ENOMEM;
4536         }
4537
4538         memset(mz->addr, 0, mz->len);
4539         mz_phys_addr = mz->iova;
4540
4541         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4542                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4543                 rmem->dma_arr[i] = mz_phys_addr + sz;
4544
4545                 if (rmem->nr_pages > 1) {
4546                         if (i == rmem->nr_pages - 2 &&
4547                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4548                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4549                         else if (i == rmem->nr_pages - 1 &&
4550                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4551                                 valid_bits |= PTU_PTE_LAST;
4552
4553                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4554                                                            valid_bits);
4555                 }
4556         }
4557
4558         rmem->mz = mz;
4559         if (rmem->vmem_size)
4560                 rmem->vmem = (void **)mz->addr;
4561         rmem->dma_arr[0] = mz_phys_addr;
4562         return 0;
4563 }
4564
4565 static void bnxt_free_ctx_mem(struct bnxt *bp)
4566 {
4567         int i;
4568
4569         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4570                 return;
4571
4572         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4573         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4574         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4575         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4576         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4577         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4578         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4579         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4580         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4581         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4582         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4583
4584         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4585                 if (bp->ctx->tqm_mem[i])
4586                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4587         }
4588
4589         rte_free(bp->ctx);
4590         bp->ctx = NULL;
4591 }
4592
4593 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4594
4595 #define min_t(type, x, y) ({                    \
4596         type __min1 = (x);                      \
4597         type __min2 = (y);                      \
4598         __min1 < __min2 ? __min1 : __min2; })
4599
4600 #define max_t(type, x, y) ({                    \
4601         type __max1 = (x);                      \
4602         type __max2 = (y);                      \
4603         __max1 > __max2 ? __max1 : __max2; })
4604
4605 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4606
4607 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4608 {
4609         struct bnxt_ctx_pg_info *ctx_pg;
4610         struct bnxt_ctx_mem_info *ctx;
4611         uint32_t mem_size, ena, entries;
4612         uint32_t entries_sp, min;
4613         int i, rc;
4614
4615         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4616         if (rc) {
4617                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4618                 return rc;
4619         }
4620         ctx = bp->ctx;
4621         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4622                 return 0;
4623
4624         ctx_pg = &ctx->qp_mem;
4625         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4626         if (ctx->qp_entry_size) {
4627                 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4628                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4629                 if (rc)
4630                         return rc;
4631         }
4632
4633         ctx_pg = &ctx->srq_mem;
4634         ctx_pg->entries = ctx->srq_max_l2_entries;
4635         if (ctx->srq_entry_size) {
4636                 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4637                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4638                 if (rc)
4639                         return rc;
4640         }
4641
4642         ctx_pg = &ctx->cq_mem;
4643         ctx_pg->entries = ctx->cq_max_l2_entries;
4644         if (ctx->cq_entry_size) {
4645                 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4646                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4647                 if (rc)
4648                         return rc;
4649         }
4650
4651         ctx_pg = &ctx->vnic_mem;
4652         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4653                 ctx->vnic_max_ring_table_entries;
4654         if (ctx->vnic_entry_size) {
4655                 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4656                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4657                 if (rc)
4658                         return rc;
4659         }
4660
4661         ctx_pg = &ctx->stat_mem;
4662         ctx_pg->entries = ctx->stat_max_entries;
4663         if (ctx->stat_entry_size) {
4664                 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4665                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4666                 if (rc)
4667                         return rc;
4668         }
4669
4670         min = ctx->tqm_min_entries_per_ring;
4671
4672         entries_sp = ctx->qp_max_l2_entries +
4673                      ctx->vnic_max_vnic_entries +
4674                      2 * ctx->qp_min_qp1_entries + min;
4675         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4676
4677         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4678         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4679         entries = clamp_t(uint32_t, entries, min,
4680                           ctx->tqm_max_entries_per_ring);
4681         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4682                 /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7.
4683                  * i > 8 is other ext rings.
4684                  */
4685                 ctx_pg = ctx->tqm_mem[i];
4686                 ctx_pg->entries = i ? entries : entries_sp;
4687                 if (ctx->tqm_entry_size) {
4688                         mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4689                         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size,
4690                                                     "tqm_mem", i);
4691                         if (rc)
4692                                 return rc;
4693                 }
4694                 if (i < BNXT_MAX_TQM_LEGACY_RINGS)
4695                         ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4696                 else
4697                         ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8;
4698         }
4699
4700         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4701         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4702         if (rc)
4703                 PMD_DRV_LOG(ERR,
4704                             "Failed to configure context mem: rc = %d\n", rc);
4705         else
4706                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4707
4708         return rc;
4709 }
4710
4711 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4712 {
4713         struct rte_pci_device *pci_dev = bp->pdev;
4714         char mz_name[RTE_MEMZONE_NAMESIZE];
4715         const struct rte_memzone *mz = NULL;
4716         uint32_t total_alloc_len;
4717         rte_iova_t mz_phys_addr;
4718
4719         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4720                 return 0;
4721
4722         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4723                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4724                  pci_dev->addr.bus, pci_dev->addr.devid,
4725                  pci_dev->addr.function, "rx_port_stats");
4726         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4727         mz = rte_memzone_lookup(mz_name);
4728         total_alloc_len =
4729                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4730                                        sizeof(struct rx_port_stats_ext) + 512);
4731         if (!mz) {
4732                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4733                                          SOCKET_ID_ANY,
4734                                          RTE_MEMZONE_2MB |
4735                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4736                                          RTE_MEMZONE_IOVA_CONTIG);
4737                 if (mz == NULL)
4738                         return -ENOMEM;
4739         }
4740         memset(mz->addr, 0, mz->len);
4741         mz_phys_addr = mz->iova;
4742
4743         bp->rx_mem_zone = (const void *)mz;
4744         bp->hw_rx_port_stats = mz->addr;
4745         bp->hw_rx_port_stats_map = mz_phys_addr;
4746
4747         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4748                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4749                  pci_dev->addr.bus, pci_dev->addr.devid,
4750                  pci_dev->addr.function, "tx_port_stats");
4751         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4752         mz = rte_memzone_lookup(mz_name);
4753         total_alloc_len =
4754                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4755                                        sizeof(struct tx_port_stats_ext) + 512);
4756         if (!mz) {
4757                 mz = rte_memzone_reserve(mz_name,
4758                                          total_alloc_len,
4759                                          SOCKET_ID_ANY,
4760                                          RTE_MEMZONE_2MB |
4761                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4762                                          RTE_MEMZONE_IOVA_CONTIG);
4763                 if (mz == NULL)
4764                         return -ENOMEM;
4765         }
4766         memset(mz->addr, 0, mz->len);
4767         mz_phys_addr = mz->iova;
4768
4769         bp->tx_mem_zone = (const void *)mz;
4770         bp->hw_tx_port_stats = mz->addr;
4771         bp->hw_tx_port_stats_map = mz_phys_addr;
4772         bp->flags |= BNXT_FLAG_PORT_STATS;
4773
4774         /* Display extended statistics if FW supports it */
4775         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4776             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4777             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4778                 return 0;
4779
4780         bp->hw_rx_port_stats_ext = (void *)
4781                 ((uint8_t *)bp->hw_rx_port_stats +
4782                  sizeof(struct rx_port_stats));
4783         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4784                 sizeof(struct rx_port_stats);
4785         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4786
4787         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4788             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4789                 bp->hw_tx_port_stats_ext = (void *)
4790                         ((uint8_t *)bp->hw_tx_port_stats +
4791                          sizeof(struct tx_port_stats));
4792                 bp->hw_tx_port_stats_ext_map =
4793                         bp->hw_tx_port_stats_map +
4794                         sizeof(struct tx_port_stats);
4795                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4796         }
4797
4798         return 0;
4799 }
4800
4801 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4802 {
4803         struct bnxt *bp = eth_dev->data->dev_private;
4804         int rc = 0;
4805
4806         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4807                                                RTE_ETHER_ADDR_LEN *
4808                                                bp->max_l2_ctx,
4809                                                0);
4810         if (eth_dev->data->mac_addrs == NULL) {
4811                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4812                 return -ENOMEM;
4813         }
4814
4815         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4816                 if (BNXT_PF(bp))
4817                         return -EINVAL;
4818
4819                 /* Generate a random MAC address, if none was assigned by PF */
4820                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4821                 bnxt_eth_hw_addr_random(bp->mac_addr);
4822                 PMD_DRV_LOG(INFO,
4823                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4824                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4825                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4826
4827                 rc = bnxt_hwrm_set_mac(bp);
4828                 if (rc)
4829                         return rc;
4830         }
4831
4832         /* Copy the permanent MAC from the FUNC_QCAPS response */
4833         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4834
4835         return rc;
4836 }
4837
4838 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4839 {
4840         int rc = 0;
4841
4842         /* MAC is already configured in FW */
4843         if (BNXT_HAS_DFLT_MAC_SET(bp))
4844                 return 0;
4845
4846         /* Restore the old MAC configured */
4847         rc = bnxt_hwrm_set_mac(bp);
4848         if (rc)
4849                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4850
4851         return rc;
4852 }
4853
4854 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4855 {
4856         if (!BNXT_PF(bp))
4857                 return;
4858
4859         memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
4860
4861         if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
4862                 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
4863         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
4864         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
4865         BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
4866         BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
4867 }
4868
4869 uint16_t
4870 bnxt_get_svif(uint16_t port_id, bool func_svif,
4871               enum bnxt_ulp_intf_type type)
4872 {
4873         struct rte_eth_dev *eth_dev;
4874         struct bnxt *bp;
4875
4876         eth_dev = &rte_eth_devices[port_id];
4877         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4878                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4879                 if (!vfr)
4880                         return 0;
4881
4882                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4883                         return vfr->svif;
4884
4885                 eth_dev = vfr->parent_dev;
4886         }
4887
4888         bp = eth_dev->data->dev_private;
4889
4890         return func_svif ? bp->func_svif : bp->port_svif;
4891 }
4892
4893 uint16_t
4894 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
4895 {
4896         struct rte_eth_dev *eth_dev;
4897         struct bnxt_vnic_info *vnic;
4898         struct bnxt *bp;
4899
4900         eth_dev = &rte_eth_devices[port];
4901         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4902                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4903                 if (!vfr)
4904                         return 0;
4905
4906                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4907                         return vfr->dflt_vnic_id;
4908
4909                 eth_dev = vfr->parent_dev;
4910         }
4911
4912         bp = eth_dev->data->dev_private;
4913
4914         vnic = BNXT_GET_DEFAULT_VNIC(bp);
4915
4916         return vnic->fw_vnic_id;
4917 }
4918
4919 uint16_t
4920 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
4921 {
4922         struct rte_eth_dev *eth_dev;
4923         struct bnxt *bp;
4924
4925         eth_dev = &rte_eth_devices[port];
4926         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4927                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4928                 if (!vfr)
4929                         return 0;
4930
4931                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4932                         return vfr->fw_fid;
4933
4934                 eth_dev = vfr->parent_dev;
4935         }
4936
4937         bp = eth_dev->data->dev_private;
4938
4939         return bp->fw_fid;
4940 }
4941
4942 enum bnxt_ulp_intf_type
4943 bnxt_get_interface_type(uint16_t port)
4944 {
4945         struct rte_eth_dev *eth_dev;
4946         struct bnxt *bp;
4947
4948         eth_dev = &rte_eth_devices[port];
4949         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
4950                 return BNXT_ULP_INTF_TYPE_VF_REP;
4951
4952         bp = eth_dev->data->dev_private;
4953         if (BNXT_PF(bp))
4954                 return BNXT_ULP_INTF_TYPE_PF;
4955         else if (BNXT_VF_IS_TRUSTED(bp))
4956                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
4957         else if (BNXT_VF(bp))
4958                 return BNXT_ULP_INTF_TYPE_VF;
4959
4960         return BNXT_ULP_INTF_TYPE_INVALID;
4961 }
4962
4963 uint16_t
4964 bnxt_get_phy_port_id(uint16_t port_id)
4965 {
4966         struct bnxt_representor *vfr;
4967         struct rte_eth_dev *eth_dev;
4968         struct bnxt *bp;
4969
4970         eth_dev = &rte_eth_devices[port_id];
4971         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4972                 vfr = eth_dev->data->dev_private;
4973                 if (!vfr)
4974                         return 0;
4975
4976                 eth_dev = vfr->parent_dev;
4977         }
4978
4979         bp = eth_dev->data->dev_private;
4980
4981         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
4982 }
4983
4984 uint16_t
4985 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
4986 {
4987         struct rte_eth_dev *eth_dev;
4988         struct bnxt *bp;
4989
4990         eth_dev = &rte_eth_devices[port_id];
4991         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4992                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4993                 if (!vfr)
4994                         return 0;
4995
4996                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4997                         return vfr->fw_fid - 1;
4998
4999                 eth_dev = vfr->parent_dev;
5000         }
5001
5002         bp = eth_dev->data->dev_private;
5003
5004         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5005 }
5006
5007 uint16_t
5008 bnxt_get_vport(uint16_t port_id)
5009 {
5010         return (1 << bnxt_get_phy_port_id(port_id));
5011 }
5012
5013 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5014 {
5015         struct bnxt_error_recovery_info *info = bp->recovery_info;
5016
5017         if (info) {
5018                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5019                         memset(info, 0, sizeof(*info));
5020                 return;
5021         }
5022
5023         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5024                 return;
5025
5026         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5027                            sizeof(*info), 0);
5028         if (!info)
5029                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5030
5031         bp->recovery_info = info;
5032 }
5033
5034 static void bnxt_check_fw_status(struct bnxt *bp)
5035 {
5036         uint32_t fw_status;
5037
5038         if (!(bp->recovery_info &&
5039               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5040                 return;
5041
5042         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5043         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5044                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5045                             fw_status);
5046 }
5047
5048 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5049 {
5050         struct bnxt_error_recovery_info *info = bp->recovery_info;
5051         uint32_t status_loc;
5052         uint32_t sig_ver;
5053
5054         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5055                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5056         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5057                                    BNXT_GRCP_WINDOW_2_BASE +
5058                                    offsetof(struct hcomm_status,
5059                                             sig_ver)));
5060         /* If the signature is absent, then FW does not support this feature */
5061         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5062             HCOMM_STATUS_SIGNATURE_VAL)
5063                 return 0;
5064
5065         if (!info) {
5066                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5067                                    sizeof(*info), 0);
5068                 if (!info)
5069                         return -ENOMEM;
5070                 bp->recovery_info = info;
5071         } else {
5072                 memset(info, 0, sizeof(*info));
5073         }
5074
5075         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5076                                       BNXT_GRCP_WINDOW_2_BASE +
5077                                       offsetof(struct hcomm_status,
5078                                                fw_status_loc)));
5079
5080         /* Only pre-map the FW health status GRC register */
5081         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5082                 return 0;
5083
5084         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5085         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5086                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5087
5088         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5089                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5090
5091         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5092
5093         return 0;
5094 }
5095
5096 /* This function gets the FW version along with the
5097  * capabilities(MAX and current) of the function, vnic,
5098  * error recovery, phy and other chip related info
5099  */
5100 static int bnxt_get_config(struct bnxt *bp)
5101 {
5102         uint16_t mtu;
5103         int rc = 0;
5104
5105         bp->fw_cap = 0;
5106
5107         rc = bnxt_map_hcomm_fw_status_reg(bp);
5108         if (rc)
5109                 return rc;
5110
5111         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5112         if (rc) {
5113                 bnxt_check_fw_status(bp);
5114                 return rc;
5115         }
5116
5117         rc = bnxt_hwrm_func_reset(bp);
5118         if (rc)
5119                 return -EIO;
5120
5121         rc = bnxt_hwrm_vnic_qcaps(bp);
5122         if (rc)
5123                 return rc;
5124
5125         rc = bnxt_hwrm_queue_qportcfg(bp);
5126         if (rc)
5127                 return rc;
5128
5129         /* Get the MAX capabilities for this function.
5130          * This function also allocates context memory for TQM rings and
5131          * informs the firmware about this allocated backing store memory.
5132          */
5133         rc = bnxt_hwrm_func_qcaps(bp);
5134         if (rc)
5135                 return rc;
5136
5137         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5138         if (rc)
5139                 return rc;
5140
5141         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5142         if (rc)
5143                 return rc;
5144
5145         bnxt_hwrm_port_mac_qcfg(bp);
5146
5147         bnxt_hwrm_parent_pf_qcfg(bp);
5148
5149         bnxt_hwrm_port_phy_qcaps(bp);
5150
5151         bnxt_alloc_error_recovery_info(bp);
5152         /* Get the adapter error recovery support info */
5153         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5154         if (rc)
5155                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5156
5157         bnxt_hwrm_port_led_qcaps(bp);
5158
5159         return 0;
5160 }
5161
5162 static int
5163 bnxt_init_locks(struct bnxt *bp)
5164 {
5165         int err;
5166
5167         err = pthread_mutex_init(&bp->flow_lock, NULL);
5168         if (err) {
5169                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5170                 return err;
5171         }
5172
5173         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5174         if (err) {
5175                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5176                 return err;
5177         }
5178
5179         err = pthread_mutex_init(&bp->health_check_lock, NULL);
5180         if (err) {
5181                 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5182                 return err;
5183         }
5184
5185         err = pthread_mutex_init(&bp->err_recovery_lock, NULL);
5186         if (err)
5187                 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n");
5188
5189         return err;
5190 }
5191
5192 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5193 {
5194         int rc = 0;
5195
5196         rc = bnxt_get_config(bp);
5197         if (rc)
5198                 return rc;
5199
5200         if (!reconfig_dev) {
5201                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5202                 if (rc)
5203                         return rc;
5204         } else {
5205                 rc = bnxt_restore_dflt_mac(bp);
5206                 if (rc)
5207                         return rc;
5208         }
5209
5210         bnxt_config_vf_req_fwd(bp);
5211
5212         rc = bnxt_hwrm_func_driver_register(bp);
5213         if (rc) {
5214                 PMD_DRV_LOG(ERR, "Failed to register driver");
5215                 return -EBUSY;
5216         }
5217
5218         if (BNXT_PF(bp)) {
5219                 if (bp->pdev->max_vfs) {
5220                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5221                         if (rc) {
5222                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5223                                 return rc;
5224                         }
5225                 } else {
5226                         rc = bnxt_hwrm_allocate_pf_only(bp);
5227                         if (rc) {
5228                                 PMD_DRV_LOG(ERR,
5229                                             "Failed to allocate PF resources");
5230                                 return rc;
5231                         }
5232                 }
5233         }
5234
5235         rc = bnxt_alloc_mem(bp, reconfig_dev);
5236         if (rc)
5237                 return rc;
5238
5239         rc = bnxt_setup_int(bp);
5240         if (rc)
5241                 return rc;
5242
5243         rc = bnxt_request_int(bp);
5244         if (rc)
5245                 return rc;
5246
5247         rc = bnxt_init_ctx_mem(bp);
5248         if (rc) {
5249                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5250                 return rc;
5251         }
5252
5253         return 0;
5254 }
5255
5256 static int
5257 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5258                              const char *value, void *opaque_arg)
5259 {
5260         struct bnxt *bp = opaque_arg;
5261         unsigned long flow_xstat;
5262         char *end = NULL;
5263
5264         if (!value || !opaque_arg) {
5265                 PMD_DRV_LOG(ERR,
5266                             "Invalid parameter passed to flow_xstat devarg.\n");
5267                 return -EINVAL;
5268         }
5269
5270         flow_xstat = strtoul(value, &end, 10);
5271         if (end == NULL || *end != '\0' ||
5272             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5273                 PMD_DRV_LOG(ERR,
5274                             "Invalid parameter passed to flow_xstat devarg.\n");
5275                 return -EINVAL;
5276         }
5277
5278         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5279                 PMD_DRV_LOG(ERR,
5280                             "Invalid value passed to flow_xstat devarg.\n");
5281                 return -EINVAL;
5282         }
5283
5284         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5285         if (BNXT_FLOW_XSTATS_EN(bp))
5286                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5287
5288         return 0;
5289 }
5290
5291 static int
5292 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5293                                         const char *value, void *opaque_arg)
5294 {
5295         struct bnxt *bp = opaque_arg;
5296         unsigned long max_num_kflows;
5297         char *end = NULL;
5298
5299         if (!value || !opaque_arg) {
5300                 PMD_DRV_LOG(ERR,
5301                         "Invalid parameter passed to max_num_kflows devarg.\n");
5302                 return -EINVAL;
5303         }
5304
5305         max_num_kflows = strtoul(value, &end, 10);
5306         if (end == NULL || *end != '\0' ||
5307                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5308                 PMD_DRV_LOG(ERR,
5309                         "Invalid parameter passed to max_num_kflows devarg.\n");
5310                 return -EINVAL;
5311         }
5312
5313         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5314                 PMD_DRV_LOG(ERR,
5315                         "Invalid value passed to max_num_kflows devarg.\n");
5316                 return -EINVAL;
5317         }
5318
5319         bp->max_num_kflows = max_num_kflows;
5320         if (bp->max_num_kflows)
5321                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5322                                 max_num_kflows);
5323
5324         return 0;
5325 }
5326
5327 static int
5328 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5329                             const char *value, void *opaque_arg)
5330 {
5331         struct bnxt_representor *vfr_bp = opaque_arg;
5332         unsigned long rep_is_pf;
5333         char *end = NULL;
5334
5335         if (!value || !opaque_arg) {
5336                 PMD_DRV_LOG(ERR,
5337                             "Invalid parameter passed to rep_is_pf devargs.\n");
5338                 return -EINVAL;
5339         }
5340
5341         rep_is_pf = strtoul(value, &end, 10);
5342         if (end == NULL || *end != '\0' ||
5343             (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5344                 PMD_DRV_LOG(ERR,
5345                             "Invalid parameter passed to rep_is_pf devargs.\n");
5346                 return -EINVAL;
5347         }
5348
5349         if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5350                 PMD_DRV_LOG(ERR,
5351                             "Invalid value passed to rep_is_pf devargs.\n");
5352                 return -EINVAL;
5353         }
5354
5355         vfr_bp->flags |= rep_is_pf;
5356         if (BNXT_REP_PF(vfr_bp))
5357                 PMD_DRV_LOG(INFO, "PF representor\n");
5358         else
5359                 PMD_DRV_LOG(INFO, "VF representor\n");
5360
5361         return 0;
5362 }
5363
5364 static int
5365 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5366                                const char *value, void *opaque_arg)
5367 {
5368         struct bnxt_representor *vfr_bp = opaque_arg;
5369         unsigned long rep_based_pf;
5370         char *end = NULL;
5371
5372         if (!value || !opaque_arg) {
5373                 PMD_DRV_LOG(ERR,
5374                             "Invalid parameter passed to rep_based_pf "
5375                             "devargs.\n");
5376                 return -EINVAL;
5377         }
5378
5379         rep_based_pf = strtoul(value, &end, 10);
5380         if (end == NULL || *end != '\0' ||
5381             (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5382                 PMD_DRV_LOG(ERR,
5383                             "Invalid parameter passed to rep_based_pf "
5384                             "devargs.\n");
5385                 return -EINVAL;
5386         }
5387
5388         if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5389                 PMD_DRV_LOG(ERR,
5390                             "Invalid value passed to rep_based_pf devargs.\n");
5391                 return -EINVAL;
5392         }
5393
5394         vfr_bp->rep_based_pf = rep_based_pf;
5395         vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
5396
5397         PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5398
5399         return 0;
5400 }
5401
5402 static int
5403 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5404                             const char *value, void *opaque_arg)
5405 {
5406         struct bnxt_representor *vfr_bp = opaque_arg;
5407         unsigned long rep_q_r2f;
5408         char *end = NULL;
5409
5410         if (!value || !opaque_arg) {
5411                 PMD_DRV_LOG(ERR,
5412                             "Invalid parameter passed to rep_q_r2f "
5413                             "devargs.\n");
5414                 return -EINVAL;
5415         }
5416
5417         rep_q_r2f = strtoul(value, &end, 10);
5418         if (end == NULL || *end != '\0' ||
5419             (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5420                 PMD_DRV_LOG(ERR,
5421                             "Invalid parameter passed to rep_q_r2f "
5422                             "devargs.\n");
5423                 return -EINVAL;
5424         }
5425
5426         if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5427                 PMD_DRV_LOG(ERR,
5428                             "Invalid value passed to rep_q_r2f devargs.\n");
5429                 return -EINVAL;
5430         }
5431
5432         vfr_bp->rep_q_r2f = rep_q_r2f;
5433         vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5434         PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5435
5436         return 0;
5437 }
5438
5439 static int
5440 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5441                             const char *value, void *opaque_arg)
5442 {
5443         struct bnxt_representor *vfr_bp = opaque_arg;
5444         unsigned long rep_q_f2r;
5445         char *end = NULL;
5446
5447         if (!value || !opaque_arg) {
5448                 PMD_DRV_LOG(ERR,
5449                             "Invalid parameter passed to rep_q_f2r "
5450                             "devargs.\n");
5451                 return -EINVAL;
5452         }
5453
5454         rep_q_f2r = strtoul(value, &end, 10);
5455         if (end == NULL || *end != '\0' ||
5456             (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5457                 PMD_DRV_LOG(ERR,
5458                             "Invalid parameter passed to rep_q_f2r "
5459                             "devargs.\n");
5460                 return -EINVAL;
5461         }
5462
5463         if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5464                 PMD_DRV_LOG(ERR,
5465                             "Invalid value passed to rep_q_f2r devargs.\n");
5466                 return -EINVAL;
5467         }
5468
5469         vfr_bp->rep_q_f2r = rep_q_f2r;
5470         vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5471         PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5472
5473         return 0;
5474 }
5475
5476 static int
5477 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5478                              const char *value, void *opaque_arg)
5479 {
5480         struct bnxt_representor *vfr_bp = opaque_arg;
5481         unsigned long rep_fc_r2f;
5482         char *end = NULL;
5483
5484         if (!value || !opaque_arg) {
5485                 PMD_DRV_LOG(ERR,
5486                             "Invalid parameter passed to rep_fc_r2f "
5487                             "devargs.\n");
5488                 return -EINVAL;
5489         }
5490
5491         rep_fc_r2f = strtoul(value, &end, 10);
5492         if (end == NULL || *end != '\0' ||
5493             (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5494                 PMD_DRV_LOG(ERR,
5495                             "Invalid parameter passed to rep_fc_r2f "
5496                             "devargs.\n");
5497                 return -EINVAL;
5498         }
5499
5500         if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5501                 PMD_DRV_LOG(ERR,
5502                             "Invalid value passed to rep_fc_r2f devargs.\n");
5503                 return -EINVAL;
5504         }
5505
5506         vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5507         vfr_bp->rep_fc_r2f = rep_fc_r2f;
5508         PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5509
5510         return 0;
5511 }
5512
5513 static int
5514 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5515                              const char *value, void *opaque_arg)
5516 {
5517         struct bnxt_representor *vfr_bp = opaque_arg;
5518         unsigned long rep_fc_f2r;
5519         char *end = NULL;
5520
5521         if (!value || !opaque_arg) {
5522                 PMD_DRV_LOG(ERR,
5523                             "Invalid parameter passed to rep_fc_f2r "
5524                             "devargs.\n");
5525                 return -EINVAL;
5526         }
5527
5528         rep_fc_f2r = strtoul(value, &end, 10);
5529         if (end == NULL || *end != '\0' ||
5530             (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5531                 PMD_DRV_LOG(ERR,
5532                             "Invalid parameter passed to rep_fc_f2r "
5533                             "devargs.\n");
5534                 return -EINVAL;
5535         }
5536
5537         if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5538                 PMD_DRV_LOG(ERR,
5539                             "Invalid value passed to rep_fc_f2r devargs.\n");
5540                 return -EINVAL;
5541         }
5542
5543         vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5544         vfr_bp->rep_fc_f2r = rep_fc_f2r;
5545         PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5546
5547         return 0;
5548 }
5549
5550 static int
5551 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5552 {
5553         struct rte_kvargs *kvlist;
5554         int ret;
5555
5556         if (devargs == NULL)
5557                 return 0;
5558
5559         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5560         if (kvlist == NULL)
5561                 return -EINVAL;
5562
5563         /*
5564          * Handler for "flow_xstat" devarg.
5565          * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5566          */
5567         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5568                                  bnxt_parse_devarg_flow_xstat, bp);
5569         if (ret)
5570                 goto err;
5571
5572         /*
5573          * Handler for "max_num_kflows" devarg.
5574          * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5575          */
5576         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5577                                  bnxt_parse_devarg_max_num_kflows, bp);
5578         if (ret)
5579                 goto err;
5580
5581 err:
5582         rte_kvargs_free(kvlist);
5583         return ret;
5584 }
5585
5586 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5587 {
5588         int rc = 0;
5589
5590         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5591                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5592                 if (rc)
5593                         PMD_DRV_LOG(ERR,
5594                                     "Failed to alloc switch domain: %d\n", rc);
5595                 else
5596                         PMD_DRV_LOG(INFO,
5597                                     "Switch domain allocated %d\n",
5598                                     bp->switch_domain_id);
5599         }
5600
5601         return rc;
5602 }
5603
5604 /* Allocate and initialize various fields in bnxt struct that
5605  * need to be allocated/destroyed only once in the lifetime of the driver
5606  */
5607 static int bnxt_drv_init(struct rte_eth_dev *eth_dev)
5608 {
5609         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5610         struct bnxt *bp = eth_dev->data->dev_private;
5611         int rc = 0;
5612
5613         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5614
5615         if (bnxt_vf_pciid(pci_dev->id.device_id))
5616                 bp->flags |= BNXT_FLAG_VF;
5617
5618         if (bnxt_p5_device(pci_dev->id.device_id))
5619                 bp->flags |= BNXT_FLAG_CHIP_P5;
5620
5621         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5622             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5623             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5624             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5625                 bp->flags |= BNXT_FLAG_STINGRAY;
5626
5627         if (BNXT_TRUFLOW_EN(bp)) {
5628                 /* extra mbuf field is required to store CFA code from mark */
5629                 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5630                         .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5631                         .size = sizeof(bnxt_cfa_code_dynfield_t),
5632                         .align = __alignof__(bnxt_cfa_code_dynfield_t),
5633                 };
5634                 bnxt_cfa_code_dynfield_offset =
5635                         rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5636                 if (bnxt_cfa_code_dynfield_offset < 0) {
5637                         PMD_DRV_LOG(ERR,
5638                             "Failed to register mbuf field for TruFlow mark\n");
5639                         return -rte_errno;
5640                 }
5641         }
5642
5643         rc = bnxt_map_pci_bars(eth_dev);
5644         if (rc) {
5645                 PMD_DRV_LOG(ERR,
5646                             "Failed to initialize board rc: %x\n", rc);
5647                 return rc;
5648         }
5649
5650         rc = bnxt_alloc_pf_info(bp);
5651         if (rc)
5652                 return rc;
5653
5654         rc = bnxt_alloc_link_info(bp);
5655         if (rc)
5656                 return rc;
5657
5658         rc = bnxt_alloc_parent_info(bp);
5659         if (rc)
5660                 return rc;
5661
5662         rc = bnxt_alloc_hwrm_resources(bp);
5663         if (rc) {
5664                 PMD_DRV_LOG(ERR,
5665                             "Failed to allocate response buffer rc: %x\n", rc);
5666                 return rc;
5667         }
5668         rc = bnxt_alloc_leds_info(bp);
5669         if (rc)
5670                 return rc;
5671
5672         rc = bnxt_alloc_cos_queues(bp);
5673         if (rc)
5674                 return rc;
5675
5676         rc = bnxt_init_locks(bp);
5677         if (rc)
5678                 return rc;
5679
5680         rc = bnxt_alloc_switch_domain(bp);
5681         if (rc)
5682                 return rc;
5683
5684         return rc;
5685 }
5686
5687 static int
5688 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5689 {
5690         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5691         static int version_printed;
5692         struct bnxt *bp;
5693         int rc;
5694
5695         if (version_printed++ == 0)
5696                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5697
5698         eth_dev->dev_ops = &bnxt_dev_ops;
5699         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5700         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5701         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5702         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5703         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5704
5705         /*
5706          * For secondary processes, we don't initialise any further
5707          * as primary has already done this work.
5708          */
5709         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5710                 return 0;
5711
5712         rte_eth_copy_pci_info(eth_dev, pci_dev);
5713         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
5714
5715         bp = eth_dev->data->dev_private;
5716
5717         /* Parse dev arguments passed on when starting the DPDK application. */
5718         rc = bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5719         if (rc)
5720                 goto error_free;
5721
5722         rc = bnxt_drv_init(eth_dev);
5723         if (rc)
5724                 goto error_free;
5725
5726         rc = bnxt_init_resources(bp, false);
5727         if (rc)
5728                 goto error_free;
5729
5730         rc = bnxt_alloc_stats_mem(bp);
5731         if (rc)
5732                 goto error_free;
5733
5734         PMD_DRV_LOG(INFO,
5735                     "Found %s device at mem %" PRIX64 ", node addr %pM\n",
5736                     DRV_MODULE_NAME,
5737                     pci_dev->mem_resource[0].phys_addr,
5738                     pci_dev->mem_resource[0].addr);
5739
5740         return 0;
5741
5742 error_free:
5743         bnxt_dev_uninit(eth_dev);
5744         return rc;
5745 }
5746
5747
5748 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5749 {
5750         if (!ctx)
5751                 return;
5752
5753         if (ctx->va)
5754                 rte_free(ctx->va);
5755
5756         ctx->va = NULL;
5757         ctx->dma = RTE_BAD_IOVA;
5758         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5759 }
5760
5761 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5762 {
5763         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5764                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5765                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
5766                                   bp->flow_stat->max_fc,
5767                                   false);
5768
5769         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5770                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5771                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
5772                                   bp->flow_stat->max_fc,
5773                                   false);
5774
5775         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5776                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5777         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5778
5779         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5780                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5781         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5782
5783         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5784                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5785         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5786
5787         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5788                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5789         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5790 }
5791
5792 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5793 {
5794         bnxt_unregister_fc_ctx_mem(bp);
5795
5796         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5797         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5798         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5799         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5800 }
5801
5802 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5803 {
5804         if (BNXT_FLOW_XSTATS_EN(bp))
5805                 bnxt_uninit_fc_ctx_mem(bp);
5806 }
5807
5808 static void
5809 bnxt_free_error_recovery_info(struct bnxt *bp)
5810 {
5811         rte_free(bp->recovery_info);
5812         bp->recovery_info = NULL;
5813         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5814 }
5815
5816 static int
5817 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5818 {
5819         int rc;
5820
5821         bnxt_free_int(bp);
5822         bnxt_free_mem(bp, reconfig_dev);
5823
5824         bnxt_hwrm_func_buf_unrgtr(bp);
5825         if (bp->pf != NULL) {
5826                 rte_free(bp->pf->vf_req_buf);
5827                 bp->pf->vf_req_buf = NULL;
5828         }
5829
5830         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5831         bp->flags &= ~BNXT_FLAG_REGISTERED;
5832         bnxt_free_ctx_mem(bp);
5833         if (!reconfig_dev) {
5834                 bnxt_free_hwrm_resources(bp);
5835                 bnxt_free_error_recovery_info(bp);
5836         }
5837
5838         bnxt_uninit_ctx_mem(bp);
5839
5840         bnxt_free_flow_stats_info(bp);
5841         if (bp->rep_info != NULL)
5842                 bnxt_free_switch_domain(bp);
5843         bnxt_free_rep_info(bp);
5844         rte_free(bp->ptp_cfg);
5845         bp->ptp_cfg = NULL;
5846         return rc;
5847 }
5848
5849 static int
5850 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5851 {
5852         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5853                 return -EPERM;
5854
5855         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5856
5857         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5858                 bnxt_dev_close_op(eth_dev);
5859
5860         return 0;
5861 }
5862
5863 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5864 {
5865         struct bnxt *bp = eth_dev->data->dev_private;
5866         struct rte_eth_dev *vf_rep_eth_dev;
5867         int ret = 0, i;
5868
5869         if (!bp)
5870                 return -EINVAL;
5871
5872         for (i = 0; i < bp->num_reps; i++) {
5873                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5874                 if (!vf_rep_eth_dev)
5875                         continue;
5876                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
5877                             vf_rep_eth_dev->data->port_id);
5878                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
5879         }
5880         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
5881                     eth_dev->data->port_id);
5882         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5883
5884         return ret;
5885 }
5886
5887 static void bnxt_free_rep_info(struct bnxt *bp)
5888 {
5889         rte_free(bp->rep_info);
5890         bp->rep_info = NULL;
5891         rte_free(bp->cfa_code_map);
5892         bp->cfa_code_map = NULL;
5893 }
5894
5895 static int bnxt_init_rep_info(struct bnxt *bp)
5896 {
5897         int i = 0, rc;
5898
5899         if (bp->rep_info)
5900                 return 0;
5901
5902         bp->rep_info = rte_zmalloc("bnxt_rep_info",
5903                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5904                                    0);
5905         if (!bp->rep_info) {
5906                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5907                 return -ENOMEM;
5908         }
5909         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5910                                        sizeof(*bp->cfa_code_map) *
5911                                        BNXT_MAX_CFA_CODE, 0);
5912         if (!bp->cfa_code_map) {
5913                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5914                 bnxt_free_rep_info(bp);
5915                 return -ENOMEM;
5916         }
5917
5918         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5919                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5920
5921         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5922         if (rc) {
5923                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5924                 bnxt_free_rep_info(bp);
5925                 return rc;
5926         }
5927
5928         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
5929         if (rc) {
5930                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
5931                 bnxt_free_rep_info(bp);
5932                 return rc;
5933         }
5934
5935         return rc;
5936 }
5937
5938 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5939                                struct rte_eth_devargs *eth_da,
5940                                struct rte_eth_dev *backing_eth_dev,
5941                                const char *dev_args)
5942 {
5943         struct rte_eth_dev *vf_rep_eth_dev;
5944         char name[RTE_ETH_NAME_MAX_LEN];
5945         struct bnxt *backing_bp;
5946         uint16_t num_rep;
5947         int i, ret = 0;
5948         struct rte_kvargs *kvlist = NULL;
5949
5950         if (eth_da->type == RTE_ETH_REPRESENTOR_NONE)
5951                 return 0;
5952         if (eth_da->type != RTE_ETH_REPRESENTOR_VF) {
5953                 PMD_DRV_LOG(ERR, "unsupported representor type %d\n",
5954                             eth_da->type);
5955                 return -ENOTSUP;
5956         }
5957         num_rep = eth_da->nb_representor_ports;
5958         if (num_rep > BNXT_MAX_VF_REPS) {
5959                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5960                             num_rep, BNXT_MAX_VF_REPS);
5961                 return -EINVAL;
5962         }
5963
5964         if (num_rep >= RTE_MAX_ETHPORTS) {
5965                 PMD_DRV_LOG(ERR,
5966                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
5967                             num_rep, RTE_MAX_ETHPORTS);
5968                 return -EINVAL;
5969         }
5970
5971         backing_bp = backing_eth_dev->data->dev_private;
5972
5973         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
5974                 PMD_DRV_LOG(ERR,
5975                             "Not a PF or trusted VF. No Representor support\n");
5976                 /* Returning an error is not an option.
5977                  * Applications are not handling this correctly
5978                  */
5979                 return 0;
5980         }
5981
5982         if (bnxt_init_rep_info(backing_bp))
5983                 return 0;
5984
5985         for (i = 0; i < num_rep; i++) {
5986                 struct bnxt_representor representor = {
5987                         .vf_id = eth_da->representor_ports[i],
5988                         .switch_domain_id = backing_bp->switch_domain_id,
5989                         .parent_dev = backing_eth_dev
5990                 };
5991
5992                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
5993                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
5994                                     representor.vf_id, BNXT_MAX_VF_REPS);
5995                         continue;
5996                 }
5997
5998                 /* representor port net_bdf_port */
5999                 snprintf(name, sizeof(name), "net_%s_representor_%d",
6000                          pci_dev->device.name, eth_da->representor_ports[i]);
6001
6002                 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
6003                 if (kvlist) {
6004                         /*
6005                          * Handler for "rep_is_pf" devarg.
6006                          * Invoked as for ex: "-a 000:00:0d.0,
6007                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6008                          */
6009                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
6010                                                  bnxt_parse_devarg_rep_is_pf,
6011                                                  (void *)&representor);
6012                         if (ret) {
6013                                 ret = -EINVAL;
6014                                 goto err;
6015                         }
6016                         /*
6017                          * Handler for "rep_based_pf" devarg.
6018                          * Invoked as for ex: "-a 000:00:0d.0,
6019                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6020                          */
6021                         ret = rte_kvargs_process(kvlist,
6022                                                  BNXT_DEVARG_REP_BASED_PF,
6023                                                  bnxt_parse_devarg_rep_based_pf,
6024                                                  (void *)&representor);
6025                         if (ret) {
6026                                 ret = -EINVAL;
6027                                 goto err;
6028                         }
6029                         /*
6030                          * Handler for "rep_based_pf" devarg.
6031                          * Invoked as for ex: "-a 000:00:0d.0,
6032                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6033                          */
6034                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
6035                                                  bnxt_parse_devarg_rep_q_r2f,
6036                                                  (void *)&representor);
6037                         if (ret) {
6038                                 ret = -EINVAL;
6039                                 goto err;
6040                         }
6041                         /*
6042                          * Handler for "rep_based_pf" devarg.
6043                          * Invoked as for ex: "-a 000:00:0d.0,
6044                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6045                          */
6046                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
6047                                                  bnxt_parse_devarg_rep_q_f2r,
6048                                                  (void *)&representor);
6049                         if (ret) {
6050                                 ret = -EINVAL;
6051                                 goto err;
6052                         }
6053                         /*
6054                          * Handler for "rep_based_pf" devarg.
6055                          * Invoked as for ex: "-a 000:00:0d.0,
6056                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6057                          */
6058                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
6059                                                  bnxt_parse_devarg_rep_fc_r2f,
6060                                                  (void *)&representor);
6061                         if (ret) {
6062                                 ret = -EINVAL;
6063                                 goto err;
6064                         }
6065                         /*
6066                          * Handler for "rep_based_pf" devarg.
6067                          * Invoked as for ex: "-a 000:00:0d.0,
6068                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6069                          */
6070                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
6071                                                  bnxt_parse_devarg_rep_fc_f2r,
6072                                                  (void *)&representor);
6073                         if (ret) {
6074                                 ret = -EINVAL;
6075                                 goto err;
6076                         }
6077                 }
6078
6079                 ret = rte_eth_dev_create(&pci_dev->device, name,
6080                                          sizeof(struct bnxt_representor),
6081                                          NULL, NULL,
6082                                          bnxt_representor_init,
6083                                          &representor);
6084                 if (ret) {
6085                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6086                                     "representor %s.", name);
6087                         goto err;
6088                 }
6089
6090                 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6091                 if (!vf_rep_eth_dev) {
6092                         PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6093                                     " for VF-Rep: %s.", name);
6094                         ret = -ENODEV;
6095                         goto err;
6096                 }
6097
6098                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6099                             backing_eth_dev->data->port_id);
6100                 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6101                                                          vf_rep_eth_dev;
6102                 backing_bp->num_reps++;
6103
6104         }
6105
6106         rte_kvargs_free(kvlist);
6107         return 0;
6108
6109 err:
6110         /* If num_rep > 1, then rollback already created
6111          * ports, since we'll be failing the probe anyway
6112          */
6113         if (num_rep > 1)
6114                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6115         rte_errno = -ret;
6116         rte_kvargs_free(kvlist);
6117
6118         return ret;
6119 }
6120
6121 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6122                           struct rte_pci_device *pci_dev)
6123 {
6124         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6125         struct rte_eth_dev *backing_eth_dev;
6126         uint16_t num_rep;
6127         int ret = 0;
6128
6129         if (pci_dev->device.devargs) {
6130                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6131                                             &eth_da);
6132                 if (ret)
6133                         return ret;
6134         }
6135
6136         num_rep = eth_da.nb_representor_ports;
6137         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6138                     num_rep);
6139
6140         /* We could come here after first level of probe is already invoked
6141          * as part of an application bringup(OVS-DPDK vswitchd), so first check
6142          * for already allocated eth_dev for the backing device (PF/Trusted VF)
6143          */
6144         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6145         if (backing_eth_dev == NULL) {
6146                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6147                                          sizeof(struct bnxt),
6148                                          eth_dev_pci_specific_init, pci_dev,
6149                                          bnxt_dev_init, NULL);
6150
6151                 if (ret || !num_rep)
6152                         return ret;
6153
6154                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6155         }
6156         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6157                     backing_eth_dev->data->port_id);
6158
6159         if (!num_rep)
6160                 return ret;
6161
6162         /* probe representor ports now */
6163         ret = bnxt_rep_port_probe(pci_dev, &eth_da, backing_eth_dev,
6164                                   pci_dev->device.devargs->args);
6165
6166         return ret;
6167 }
6168
6169 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6170 {
6171         struct rte_eth_dev *eth_dev;
6172
6173         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6174         if (!eth_dev)
6175                 return 0; /* Invoked typically only by OVS-DPDK, by the
6176                            * time it comes here the eth_dev is already
6177                            * deleted by rte_eth_dev_close(), so returning
6178                            * +ve value will at least help in proper cleanup
6179                            */
6180
6181         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6182         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6183                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6184                         return rte_eth_dev_destroy(eth_dev,
6185                                                    bnxt_representor_uninit);
6186                 else
6187                         return rte_eth_dev_destroy(eth_dev,
6188                                                    bnxt_dev_uninit);
6189         } else {
6190                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6191         }
6192 }
6193
6194 static struct rte_pci_driver bnxt_rte_pmd = {
6195         .id_table = bnxt_pci_id_map,
6196         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6197                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6198                                                   * and OVS-DPDK
6199                                                   */
6200         .probe = bnxt_pci_probe,
6201         .remove = bnxt_pci_remove,
6202 };
6203
6204 static bool
6205 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6206 {
6207         if (strcmp(dev->device->driver->name, drv->driver.name))
6208                 return false;
6209
6210         return true;
6211 }
6212
6213 bool is_bnxt_supported(struct rte_eth_dev *dev)
6214 {
6215         return is_device_supported(dev, &bnxt_rte_pmd);
6216 }
6217
6218 RTE_LOG_REGISTER_SUFFIX(bnxt_logtype_driver, driver, NOTICE);
6219 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6220 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6221 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");