1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
20 #include "bnxt_ring.h"
23 #include "bnxt_stats.h"
26 #include "bnxt_vnic.h"
27 #include "hsi_struct_def_dpdk.h"
28 #include "bnxt_nvm_defs.h"
30 #define DRV_MODULE_NAME "bnxt"
31 static const char bnxt_version[] =
32 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
33 int bnxt_logtype_driver;
36 * The set of PCI devices this driver supports
38 static const struct rte_pci_id bnxt_pci_id_map[] = {
39 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
40 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
41 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
42 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
43 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
45 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
47 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
92 { .vendor_id = 0, /* sentinel */ },
95 #define BNXT_ETH_RSS_SUPPORT ( \
97 ETH_RSS_NONFRAG_IPV4_TCP | \
98 ETH_RSS_NONFRAG_IPV4_UDP | \
100 ETH_RSS_NONFRAG_IPV6_TCP | \
101 ETH_RSS_NONFRAG_IPV6_UDP)
103 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
104 DEV_TX_OFFLOAD_IPV4_CKSUM | \
105 DEV_TX_OFFLOAD_TCP_CKSUM | \
106 DEV_TX_OFFLOAD_UDP_CKSUM | \
107 DEV_TX_OFFLOAD_TCP_TSO | \
108 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
109 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
110 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
111 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
112 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
113 DEV_TX_OFFLOAD_QINQ_INSERT | \
114 DEV_TX_OFFLOAD_MULTI_SEGS)
116 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
117 DEV_RX_OFFLOAD_VLAN_STRIP | \
118 DEV_RX_OFFLOAD_IPV4_CKSUM | \
119 DEV_RX_OFFLOAD_UDP_CKSUM | \
120 DEV_RX_OFFLOAD_TCP_CKSUM | \
121 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
122 DEV_RX_OFFLOAD_JUMBO_FRAME | \
123 DEV_RX_OFFLOAD_KEEP_CRC | \
124 DEV_RX_OFFLOAD_VLAN_EXTEND | \
125 DEV_RX_OFFLOAD_TCP_LRO | \
126 DEV_RX_OFFLOAD_SCATTER | \
127 DEV_RX_OFFLOAD_RSS_HASH)
129 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
130 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
131 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
132 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
133 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
134 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
135 static int bnxt_restore_vlan_filters(struct bnxt *bp);
136 static void bnxt_dev_recover(void *arg);
138 int is_bnxt_in_error(struct bnxt *bp)
140 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
142 if (bp->flags & BNXT_FLAG_FW_RESET)
148 /***********************/
151 * High level utility functions
154 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
156 if (!BNXT_CHIP_THOR(bp))
159 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
160 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
161 BNXT_RSS_ENTRIES_PER_CTX_THOR;
164 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
166 if (!BNXT_CHIP_THOR(bp))
167 return HW_HASH_INDEX_SIZE;
169 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
172 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
174 bnxt_free_filter_mem(bp);
175 bnxt_free_vnic_attributes(bp);
176 bnxt_free_vnic_mem(bp);
178 /* tx/rx rings are configured as part of *_queue_setup callbacks.
179 * If the number of rings change across fw update,
180 * we don't have much choice except to warn the user.
184 bnxt_free_tx_rings(bp);
185 bnxt_free_rx_rings(bp);
187 bnxt_free_async_cp_ring(bp);
188 bnxt_free_rxtx_nq_ring(bp);
190 rte_free(bp->grp_info);
194 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
198 rc = bnxt_alloc_ring_grps(bp);
202 rc = bnxt_alloc_async_ring_struct(bp);
206 rc = bnxt_alloc_vnic_mem(bp);
210 rc = bnxt_alloc_vnic_attributes(bp);
214 rc = bnxt_alloc_filter_mem(bp);
218 rc = bnxt_alloc_async_cp_ring(bp);
222 rc = bnxt_alloc_rxtx_nq_ring(bp);
229 bnxt_free_mem(bp, reconfig);
233 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
235 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
236 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
237 uint64_t rx_offloads = dev_conf->rxmode.offloads;
238 struct bnxt_rx_queue *rxq;
242 rc = bnxt_vnic_grp_alloc(bp, vnic);
246 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
247 vnic_id, vnic, vnic->fw_grp_ids);
249 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
253 /* Alloc RSS context only if RSS mode is enabled */
254 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
255 int j, nr_ctxs = bnxt_rss_ctxts(bp);
258 for (j = 0; j < nr_ctxs; j++) {
259 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
265 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
269 vnic->num_lb_ctxts = nr_ctxs;
273 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
274 * setting is not available at this time, it will not be
275 * configured correctly in the CFA.
277 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
278 vnic->vlan_strip = true;
280 vnic->vlan_strip = false;
282 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
286 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
290 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
291 rxq = bp->eth_dev->data->rx_queues[j];
294 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
295 j, rxq->vnic, rxq->vnic->fw_grp_ids);
297 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
298 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
300 vnic->rx_queue_cnt++;
303 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
305 rc = bnxt_vnic_rss_configure(bp, vnic);
309 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
311 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
312 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
314 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
318 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
323 static int bnxt_init_chip(struct bnxt *bp)
325 struct rte_eth_link new;
326 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
327 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
328 uint32_t intr_vector = 0;
329 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
330 uint32_t vec = BNXT_MISC_VEC_ID;
334 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
335 bp->eth_dev->data->dev_conf.rxmode.offloads |=
336 DEV_RX_OFFLOAD_JUMBO_FRAME;
337 bp->flags |= BNXT_FLAG_JUMBO;
339 bp->eth_dev->data->dev_conf.rxmode.offloads &=
340 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
341 bp->flags &= ~BNXT_FLAG_JUMBO;
344 /* THOR does not support ring groups.
345 * But we will use the array to save RSS context IDs.
347 if (BNXT_CHIP_THOR(bp))
348 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
350 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
352 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
356 rc = bnxt_alloc_hwrm_rings(bp);
358 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
362 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
364 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
368 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
371 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
372 if (bp->rx_cos_queue[i].id != 0xff) {
373 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
377 "Num pools more than FW profile\n");
381 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
387 rc = bnxt_mq_rx_configure(bp);
389 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
393 /* VNIC configuration */
394 for (i = 0; i < bp->nr_vnics; i++) {
395 rc = bnxt_setup_one_vnic(bp, i);
400 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
403 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
407 /* check and configure queue intr-vector mapping */
408 if ((rte_intr_cap_multiple(intr_handle) ||
409 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
410 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
411 intr_vector = bp->eth_dev->data->nb_rx_queues;
412 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
413 if (intr_vector > bp->rx_cp_nr_rings) {
414 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
418 rc = rte_intr_efd_enable(intr_handle, intr_vector);
423 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
424 intr_handle->intr_vec =
425 rte_zmalloc("intr_vec",
426 bp->eth_dev->data->nb_rx_queues *
428 if (intr_handle->intr_vec == NULL) {
429 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
430 " intr_vec", bp->eth_dev->data->nb_rx_queues);
434 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
435 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
436 intr_handle->intr_vec, intr_handle->nb_efd,
437 intr_handle->max_intr);
438 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
440 intr_handle->intr_vec[queue_id] =
441 vec + BNXT_RX_VEC_START;
442 if (vec < base + intr_handle->nb_efd - 1)
447 /* enable uio/vfio intr/eventfd mapping */
448 rc = rte_intr_enable(intr_handle);
449 #ifndef RTE_EXEC_ENV_FREEBSD
450 /* In FreeBSD OS, nic_uio driver does not support interrupts */
455 rc = bnxt_get_hwrm_link_config(bp, &new);
457 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
461 if (!bp->link_info.link_up) {
462 rc = bnxt_set_hwrm_link_config(bp, true);
465 "HWRM link config failure rc: %x\n", rc);
469 bnxt_print_link_info(bp->eth_dev);
471 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
473 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
478 rte_free(intr_handle->intr_vec);
480 rte_intr_efd_disable(intr_handle);
482 /* Some of the error status returned by FW may not be from errno.h */
489 static int bnxt_shutdown_nic(struct bnxt *bp)
491 bnxt_free_all_hwrm_resources(bp);
492 bnxt_free_all_filters(bp);
493 bnxt_free_all_vnics(bp);
498 * Device configuration and status function
501 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
502 struct rte_eth_dev_info *dev_info)
504 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
505 struct bnxt *bp = eth_dev->data->dev_private;
506 uint16_t max_vnics, i, j, vpool, vrxq;
507 unsigned int max_rx_rings;
510 rc = is_bnxt_in_error(bp);
515 dev_info->max_mac_addrs = bp->max_l2_ctx;
516 dev_info->max_hash_mac_addrs = 0;
518 /* PF/VF specifics */
520 dev_info->max_vfs = pdev->max_vfs;
522 max_rx_rings = BNXT_MAX_RINGS(bp);
523 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
524 dev_info->max_rx_queues = max_rx_rings;
525 dev_info->max_tx_queues = max_rx_rings;
526 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
527 dev_info->hash_key_size = 40;
528 max_vnics = bp->max_vnics;
531 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
532 dev_info->max_mtu = BNXT_MAX_MTU;
534 /* Fast path specifics */
535 dev_info->min_rx_bufsize = 1;
536 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
538 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
539 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
540 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
541 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
542 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
545 dev_info->default_rxconf = (struct rte_eth_rxconf) {
551 .rx_free_thresh = 32,
552 /* If no descriptors available, pkts are dropped by default */
556 dev_info->default_txconf = (struct rte_eth_txconf) {
562 .tx_free_thresh = 32,
565 eth_dev->data->dev_conf.intr_conf.lsc = 1;
567 eth_dev->data->dev_conf.intr_conf.rxq = 1;
568 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
569 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
570 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
571 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
576 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
577 * need further investigation.
581 vpool = 64; /* ETH_64_POOLS */
582 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
583 for (i = 0; i < 4; vpool >>= 1, i++) {
584 if (max_vnics > vpool) {
585 for (j = 0; j < 5; vrxq >>= 1, j++) {
586 if (dev_info->max_rx_queues > vrxq) {
592 /* Not enough resources to support VMDq */
596 /* Not enough resources to support VMDq */
600 dev_info->max_vmdq_pools = vpool;
601 dev_info->vmdq_queue_num = vrxq;
603 dev_info->vmdq_pool_base = 0;
604 dev_info->vmdq_queue_base = 0;
609 /* Configure the device based on the configuration provided */
610 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
612 struct bnxt *bp = eth_dev->data->dev_private;
613 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
616 bp->rx_queues = (void *)eth_dev->data->rx_queues;
617 bp->tx_queues = (void *)eth_dev->data->tx_queues;
618 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
619 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
621 rc = is_bnxt_in_error(bp);
625 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
626 rc = bnxt_hwrm_check_vf_rings(bp);
628 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
632 /* If a resource has already been allocated - in this case
633 * it is the async completion ring, free it. Reallocate it after
634 * resource reservation. This will ensure the resource counts
635 * are calculated correctly.
638 pthread_mutex_lock(&bp->def_cp_lock);
640 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
641 bnxt_disable_int(bp);
642 bnxt_free_cp_ring(bp, bp->async_cp_ring);
645 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
647 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
648 pthread_mutex_unlock(&bp->def_cp_lock);
652 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
653 rc = bnxt_alloc_async_cp_ring(bp);
655 pthread_mutex_unlock(&bp->def_cp_lock);
661 pthread_mutex_unlock(&bp->def_cp_lock);
663 /* legacy driver needs to get updated values */
664 rc = bnxt_hwrm_func_qcaps(bp);
666 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
671 /* Inherit new configurations */
672 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
673 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
674 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
675 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
676 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
680 if (BNXT_HAS_RING_GRPS(bp) &&
681 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
684 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
685 bp->max_vnics < eth_dev->data->nb_rx_queues)
688 bp->rx_cp_nr_rings = bp->rx_nr_rings;
689 bp->tx_cp_nr_rings = bp->tx_nr_rings;
691 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
692 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
693 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
695 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
697 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
698 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
700 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
706 "Insufficient resources to support requested config\n");
708 "Num Queues Requested: Tx %d, Rx %d\n",
709 eth_dev->data->nb_tx_queues,
710 eth_dev->data->nb_rx_queues);
712 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
713 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
714 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
718 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
720 struct rte_eth_link *link = ð_dev->data->dev_link;
722 if (link->link_status)
723 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
724 eth_dev->data->port_id,
725 (uint32_t)link->link_speed,
726 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
727 ("full-duplex") : ("half-duplex\n"));
729 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
730 eth_dev->data->port_id);
734 * Determine whether the current configuration requires support for scattered
735 * receive; return 1 if scattered receive is required and 0 if not.
737 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
742 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
745 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
746 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
748 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
749 RTE_PKTMBUF_HEADROOM);
750 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
756 static eth_rx_burst_t
757 bnxt_receive_function(struct rte_eth_dev *eth_dev)
759 struct bnxt *bp = eth_dev->data->dev_private;
762 #ifndef RTE_LIBRTE_IEEE1588
764 * Vector mode receive can be enabled only if scatter rx is not
765 * in use and rx offloads are limited to VLAN stripping and
768 if (!eth_dev->data->scattered_rx &&
769 !(eth_dev->data->dev_conf.rxmode.offloads &
770 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
771 DEV_RX_OFFLOAD_KEEP_CRC |
772 DEV_RX_OFFLOAD_JUMBO_FRAME |
773 DEV_RX_OFFLOAD_IPV4_CKSUM |
774 DEV_RX_OFFLOAD_UDP_CKSUM |
775 DEV_RX_OFFLOAD_TCP_CKSUM |
776 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
777 DEV_RX_OFFLOAD_RSS_HASH |
778 DEV_RX_OFFLOAD_VLAN_FILTER))) {
779 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
780 eth_dev->data->port_id);
781 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
782 return bnxt_recv_pkts_vec;
784 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
785 eth_dev->data->port_id);
787 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
788 eth_dev->data->port_id,
789 eth_dev->data->scattered_rx,
790 eth_dev->data->dev_conf.rxmode.offloads);
793 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
794 return bnxt_recv_pkts;
797 static eth_tx_burst_t
798 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
801 #ifndef RTE_LIBRTE_IEEE1588
803 * Vector mode transmit can be enabled only if not using scatter rx
806 if (!eth_dev->data->scattered_rx &&
807 !eth_dev->data->dev_conf.txmode.offloads) {
808 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
809 eth_dev->data->port_id);
810 return bnxt_xmit_pkts_vec;
812 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
813 eth_dev->data->port_id);
815 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
816 eth_dev->data->port_id,
817 eth_dev->data->scattered_rx,
818 eth_dev->data->dev_conf.txmode.offloads);
821 return bnxt_xmit_pkts;
824 static int bnxt_handle_if_change_status(struct bnxt *bp)
828 /* Since fw has undergone a reset and lost all contexts,
829 * set fatal flag to not issue hwrm during cleanup
831 bp->flags |= BNXT_FLAG_FATAL_ERROR;
832 bnxt_uninit_resources(bp, true);
834 /* clear fatal flag so that re-init happens */
835 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
836 rc = bnxt_init_resources(bp, true);
838 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
843 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
845 struct bnxt *bp = eth_dev->data->dev_private;
846 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
850 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
851 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
855 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
857 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
858 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
861 rc = bnxt_hwrm_if_change(bp, 1);
863 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
864 rc = bnxt_handle_if_change_status(bp);
871 rc = bnxt_init_chip(bp);
875 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
876 eth_dev->data->dev_started = 1;
878 bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
880 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
881 vlan_mask |= ETH_VLAN_FILTER_MASK;
882 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
883 vlan_mask |= ETH_VLAN_STRIP_MASK;
884 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
888 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
889 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
891 pthread_mutex_lock(&bp->def_cp_lock);
892 bnxt_schedule_fw_health_check(bp);
893 pthread_mutex_unlock(&bp->def_cp_lock);
897 bnxt_hwrm_if_change(bp, 0);
898 bnxt_shutdown_nic(bp);
899 bnxt_free_tx_mbufs(bp);
900 bnxt_free_rx_mbufs(bp);
901 eth_dev->data->dev_started = 0;
905 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
907 struct bnxt *bp = eth_dev->data->dev_private;
910 if (!bp->link_info.link_up)
911 rc = bnxt_set_hwrm_link_config(bp, true);
913 eth_dev->data->dev_link.link_status = 1;
915 bnxt_print_link_info(eth_dev);
919 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
921 struct bnxt *bp = eth_dev->data->dev_private;
923 eth_dev->data->dev_link.link_status = 0;
924 bnxt_set_hwrm_link_config(bp, false);
925 bp->link_info.link_up = 0;
930 /* Unload the driver, release resources */
931 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
933 struct bnxt *bp = eth_dev->data->dev_private;
934 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
935 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
937 eth_dev->data->dev_started = 0;
938 /* Prevent crashes when queues are still in use */
939 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
940 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
942 bnxt_disable_int(bp);
944 /* disable uio/vfio intr/eventfd mapping */
945 rte_intr_disable(intr_handle);
947 bnxt_cancel_fw_health_check(bp);
949 bnxt_dev_set_link_down_op(eth_dev);
951 /* Wait for link to be reset and the async notification to process.
952 * During reset recovery, there is no need to wait and
953 * VF/NPAR functions do not have privilege to change PHY config.
955 if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
956 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
958 /* Clean queue intr-vector mapping */
959 rte_intr_efd_disable(intr_handle);
960 if (intr_handle->intr_vec != NULL) {
961 rte_free(intr_handle->intr_vec);
962 intr_handle->intr_vec = NULL;
965 bnxt_hwrm_port_clr_stats(bp);
966 bnxt_free_tx_mbufs(bp);
967 bnxt_free_rx_mbufs(bp);
968 /* Process any remaining notifications in default completion queue */
969 bnxt_int_handler(eth_dev);
970 bnxt_shutdown_nic(bp);
971 bnxt_hwrm_if_change(bp, 0);
973 rte_free(bp->mark_table);
974 bp->mark_table = NULL;
976 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
980 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
982 struct bnxt *bp = eth_dev->data->dev_private;
984 /* cancel the recovery handler before remove dev */
985 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
986 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
988 if (eth_dev->data->dev_started)
989 bnxt_dev_stop_op(eth_dev);
991 bnxt_uninit_resources(bp, false);
993 eth_dev->dev_ops = NULL;
994 eth_dev->rx_pkt_burst = NULL;
995 eth_dev->tx_pkt_burst = NULL;
997 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
998 bp->tx_mem_zone = NULL;
999 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1000 bp->rx_mem_zone = NULL;
1002 rte_free(bp->pf.vf_info);
1003 bp->pf.vf_info = NULL;
1005 rte_free(bp->grp_info);
1006 bp->grp_info = NULL;
1009 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1012 struct bnxt *bp = eth_dev->data->dev_private;
1013 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1014 struct bnxt_vnic_info *vnic;
1015 struct bnxt_filter_info *filter, *temp_filter;
1018 if (is_bnxt_in_error(bp))
1022 * Loop through all VNICs from the specified filter flow pools to
1023 * remove the corresponding MAC addr filter
1025 for (i = 0; i < bp->nr_vnics; i++) {
1026 if (!(pool_mask & (1ULL << i)))
1029 vnic = &bp->vnic_info[i];
1030 filter = STAILQ_FIRST(&vnic->filter);
1032 temp_filter = STAILQ_NEXT(filter, next);
1033 if (filter->mac_index == index) {
1034 STAILQ_REMOVE(&vnic->filter, filter,
1035 bnxt_filter_info, next);
1036 bnxt_hwrm_clear_l2_filter(bp, filter);
1037 bnxt_free_filter(bp, filter);
1039 filter = temp_filter;
1044 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1045 struct rte_ether_addr *mac_addr, uint32_t index,
1048 struct bnxt_filter_info *filter;
1051 /* Attach requested MAC address to the new l2_filter */
1052 STAILQ_FOREACH(filter, &vnic->filter, next) {
1053 if (filter->mac_index == index) {
1055 "MAC addr already existed for pool %d\n",
1061 filter = bnxt_alloc_filter(bp);
1063 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1067 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1068 * if the MAC that's been programmed now is a different one, then,
1069 * copy that addr to filter->l2_addr
1072 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1073 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1075 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1077 filter->mac_index = index;
1078 if (filter->mac_index == 0)
1079 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1081 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1083 bnxt_free_filter(bp, filter);
1089 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1090 struct rte_ether_addr *mac_addr,
1091 uint32_t index, uint32_t pool)
1093 struct bnxt *bp = eth_dev->data->dev_private;
1094 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1097 rc = is_bnxt_in_error(bp);
1101 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1102 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1107 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1111 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1116 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1117 bool exp_link_status)
1120 struct bnxt *bp = eth_dev->data->dev_private;
1121 struct rte_eth_link new;
1122 int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1123 BNXT_LINK_DOWN_WAIT_CNT;
1125 rc = is_bnxt_in_error(bp);
1129 memset(&new, 0, sizeof(new));
1131 /* Retrieve link info from hardware */
1132 rc = bnxt_get_hwrm_link_config(bp, &new);
1134 new.link_speed = ETH_LINK_SPEED_100M;
1135 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1137 "Failed to retrieve link rc = 0x%x!\n", rc);
1141 if (!wait_to_complete || new.link_status == exp_link_status)
1144 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1148 /* Timed out or success */
1149 if (new.link_status != eth_dev->data->dev_link.link_status ||
1150 new.link_speed != eth_dev->data->dev_link.link_speed) {
1151 rte_eth_linkstatus_set(eth_dev, &new);
1153 _rte_eth_dev_callback_process(eth_dev,
1154 RTE_ETH_EVENT_INTR_LSC,
1157 bnxt_print_link_info(eth_dev);
1163 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1164 int wait_to_complete)
1166 return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1169 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1171 struct bnxt *bp = eth_dev->data->dev_private;
1172 struct bnxt_vnic_info *vnic;
1176 rc = is_bnxt_in_error(bp);
1180 /* Filter settings will get applied when port is started */
1181 if (!eth_dev->data->dev_started)
1184 if (bp->vnic_info == NULL)
1187 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1189 old_flags = vnic->flags;
1190 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1191 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1193 vnic->flags = old_flags;
1198 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1200 struct bnxt *bp = eth_dev->data->dev_private;
1201 struct bnxt_vnic_info *vnic;
1205 rc = is_bnxt_in_error(bp);
1209 /* Filter settings will get applied when port is started */
1210 if (!eth_dev->data->dev_started)
1213 if (bp->vnic_info == NULL)
1216 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1218 old_flags = vnic->flags;
1219 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1220 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1222 vnic->flags = old_flags;
1227 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1229 struct bnxt *bp = eth_dev->data->dev_private;
1230 struct bnxt_vnic_info *vnic;
1234 rc = is_bnxt_in_error(bp);
1238 /* Filter settings will get applied when port is started */
1239 if (!eth_dev->data->dev_started)
1242 if (bp->vnic_info == NULL)
1245 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1247 old_flags = vnic->flags;
1248 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1249 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1251 vnic->flags = old_flags;
1256 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1258 struct bnxt *bp = eth_dev->data->dev_private;
1259 struct bnxt_vnic_info *vnic;
1263 rc = is_bnxt_in_error(bp);
1267 /* Filter settings will get applied when port is started */
1268 if (!eth_dev->data->dev_started)
1271 if (bp->vnic_info == NULL)
1274 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1276 old_flags = vnic->flags;
1277 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1278 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1280 vnic->flags = old_flags;
1285 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1286 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1288 if (qid >= bp->rx_nr_rings)
1291 return bp->eth_dev->data->rx_queues[qid];
1294 /* Return rxq corresponding to a given rss table ring/group ID. */
1295 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1297 struct bnxt_rx_queue *rxq;
1300 if (!BNXT_HAS_RING_GRPS(bp)) {
1301 for (i = 0; i < bp->rx_nr_rings; i++) {
1302 rxq = bp->eth_dev->data->rx_queues[i];
1303 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1307 for (i = 0; i < bp->rx_nr_rings; i++) {
1308 if (bp->grp_info[i].fw_grp_id == fwr)
1313 return INVALID_HW_RING_ID;
1316 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1317 struct rte_eth_rss_reta_entry64 *reta_conf,
1320 struct bnxt *bp = eth_dev->data->dev_private;
1321 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1322 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1323 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1327 rc = is_bnxt_in_error(bp);
1331 if (!vnic->rss_table)
1334 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1337 if (reta_size != tbl_size) {
1338 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1339 "(%d) must equal the size supported by the hardware "
1340 "(%d)\n", reta_size, tbl_size);
1344 for (i = 0; i < reta_size; i++) {
1345 struct bnxt_rx_queue *rxq;
1347 idx = i / RTE_RETA_GROUP_SIZE;
1348 sft = i % RTE_RETA_GROUP_SIZE;
1350 if (!(reta_conf[idx].mask & (1ULL << sft)))
1353 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1355 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1359 if (BNXT_CHIP_THOR(bp)) {
1360 vnic->rss_table[i * 2] =
1361 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1362 vnic->rss_table[i * 2 + 1] =
1363 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1365 vnic->rss_table[i] =
1366 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1370 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1374 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1375 struct rte_eth_rss_reta_entry64 *reta_conf,
1378 struct bnxt *bp = eth_dev->data->dev_private;
1379 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1380 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1381 uint16_t idx, sft, i;
1384 rc = is_bnxt_in_error(bp);
1388 /* Retrieve from the default VNIC */
1391 if (!vnic->rss_table)
1394 if (reta_size != tbl_size) {
1395 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1396 "(%d) must equal the size supported by the hardware "
1397 "(%d)\n", reta_size, tbl_size);
1401 for (idx = 0, i = 0; i < reta_size; i++) {
1402 idx = i / RTE_RETA_GROUP_SIZE;
1403 sft = i % RTE_RETA_GROUP_SIZE;
1405 if (reta_conf[idx].mask & (1ULL << sft)) {
1408 if (BNXT_CHIP_THOR(bp))
1409 qid = bnxt_rss_to_qid(bp,
1410 vnic->rss_table[i * 2]);
1412 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1414 if (qid == INVALID_HW_RING_ID) {
1415 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1418 reta_conf[idx].reta[sft] = qid;
1425 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1426 struct rte_eth_rss_conf *rss_conf)
1428 struct bnxt *bp = eth_dev->data->dev_private;
1429 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1430 struct bnxt_vnic_info *vnic;
1433 rc = is_bnxt_in_error(bp);
1438 * If RSS enablement were different than dev_configure,
1439 * then return -EINVAL
1441 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1442 if (!rss_conf->rss_hf)
1443 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1445 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1449 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1450 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1452 /* Update the default RSS VNIC(s) */
1453 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1454 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1457 * If hashkey is not specified, use the previously configured
1460 if (!rss_conf->rss_key)
1463 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1465 "Invalid hashkey length, should be 16 bytes\n");
1468 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1471 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1475 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1476 struct rte_eth_rss_conf *rss_conf)
1478 struct bnxt *bp = eth_dev->data->dev_private;
1479 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1481 uint32_t hash_types;
1483 rc = is_bnxt_in_error(bp);
1487 /* RSS configuration is the same for all VNICs */
1488 if (vnic && vnic->rss_hash_key) {
1489 if (rss_conf->rss_key) {
1490 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1491 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1492 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1495 hash_types = vnic->hash_type;
1496 rss_conf->rss_hf = 0;
1497 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1498 rss_conf->rss_hf |= ETH_RSS_IPV4;
1499 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1501 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1502 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1504 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1506 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1507 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1509 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1511 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1512 rss_conf->rss_hf |= ETH_RSS_IPV6;
1513 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1515 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1516 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1518 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1520 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1521 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1523 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1527 "Unknwon RSS config from firmware (%08x), RSS disabled",
1532 rss_conf->rss_hf = 0;
1537 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1538 struct rte_eth_fc_conf *fc_conf)
1540 struct bnxt *bp = dev->data->dev_private;
1541 struct rte_eth_link link_info;
1544 rc = is_bnxt_in_error(bp);
1548 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1552 memset(fc_conf, 0, sizeof(*fc_conf));
1553 if (bp->link_info.auto_pause)
1554 fc_conf->autoneg = 1;
1555 switch (bp->link_info.pause) {
1557 fc_conf->mode = RTE_FC_NONE;
1559 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1560 fc_conf->mode = RTE_FC_TX_PAUSE;
1562 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1563 fc_conf->mode = RTE_FC_RX_PAUSE;
1565 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1566 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1567 fc_conf->mode = RTE_FC_FULL;
1573 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1574 struct rte_eth_fc_conf *fc_conf)
1576 struct bnxt *bp = dev->data->dev_private;
1579 rc = is_bnxt_in_error(bp);
1583 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1584 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1588 switch (fc_conf->mode) {
1590 bp->link_info.auto_pause = 0;
1591 bp->link_info.force_pause = 0;
1593 case RTE_FC_RX_PAUSE:
1594 if (fc_conf->autoneg) {
1595 bp->link_info.auto_pause =
1596 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1597 bp->link_info.force_pause = 0;
1599 bp->link_info.auto_pause = 0;
1600 bp->link_info.force_pause =
1601 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1604 case RTE_FC_TX_PAUSE:
1605 if (fc_conf->autoneg) {
1606 bp->link_info.auto_pause =
1607 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1608 bp->link_info.force_pause = 0;
1610 bp->link_info.auto_pause = 0;
1611 bp->link_info.force_pause =
1612 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1616 if (fc_conf->autoneg) {
1617 bp->link_info.auto_pause =
1618 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1619 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1620 bp->link_info.force_pause = 0;
1622 bp->link_info.auto_pause = 0;
1623 bp->link_info.force_pause =
1624 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1625 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1629 return bnxt_set_hwrm_link_config(bp, true);
1632 /* Add UDP tunneling port */
1634 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1635 struct rte_eth_udp_tunnel *udp_tunnel)
1637 struct bnxt *bp = eth_dev->data->dev_private;
1638 uint16_t tunnel_type = 0;
1641 rc = is_bnxt_in_error(bp);
1645 switch (udp_tunnel->prot_type) {
1646 case RTE_TUNNEL_TYPE_VXLAN:
1647 if (bp->vxlan_port_cnt) {
1648 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1649 udp_tunnel->udp_port);
1650 if (bp->vxlan_port != udp_tunnel->udp_port) {
1651 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1654 bp->vxlan_port_cnt++;
1658 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1659 bp->vxlan_port_cnt++;
1661 case RTE_TUNNEL_TYPE_GENEVE:
1662 if (bp->geneve_port_cnt) {
1663 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1664 udp_tunnel->udp_port);
1665 if (bp->geneve_port != udp_tunnel->udp_port) {
1666 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1669 bp->geneve_port_cnt++;
1673 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1674 bp->geneve_port_cnt++;
1677 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1680 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1686 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1687 struct rte_eth_udp_tunnel *udp_tunnel)
1689 struct bnxt *bp = eth_dev->data->dev_private;
1690 uint16_t tunnel_type = 0;
1694 rc = is_bnxt_in_error(bp);
1698 switch (udp_tunnel->prot_type) {
1699 case RTE_TUNNEL_TYPE_VXLAN:
1700 if (!bp->vxlan_port_cnt) {
1701 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1704 if (bp->vxlan_port != udp_tunnel->udp_port) {
1705 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1706 udp_tunnel->udp_port, bp->vxlan_port);
1709 if (--bp->vxlan_port_cnt)
1713 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1714 port = bp->vxlan_fw_dst_port_id;
1716 case RTE_TUNNEL_TYPE_GENEVE:
1717 if (!bp->geneve_port_cnt) {
1718 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1721 if (bp->geneve_port != udp_tunnel->udp_port) {
1722 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1723 udp_tunnel->udp_port, bp->geneve_port);
1726 if (--bp->geneve_port_cnt)
1730 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1731 port = bp->geneve_fw_dst_port_id;
1734 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1738 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1741 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1744 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1745 bp->geneve_port = 0;
1750 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1752 struct bnxt_filter_info *filter;
1753 struct bnxt_vnic_info *vnic;
1755 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1757 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1758 filter = STAILQ_FIRST(&vnic->filter);
1760 /* Search for this matching MAC+VLAN filter */
1761 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
1762 /* Delete the filter */
1763 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1766 STAILQ_REMOVE(&vnic->filter, filter,
1767 bnxt_filter_info, next);
1768 bnxt_free_filter(bp, filter);
1770 "Deleted vlan filter for %d\n",
1774 filter = STAILQ_NEXT(filter, next);
1779 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1781 struct bnxt_filter_info *filter;
1782 struct bnxt_vnic_info *vnic;
1784 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1785 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1786 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1788 /* Implementation notes on the use of VNIC in this command:
1790 * By default, these filters belong to default vnic for the function.
1791 * Once these filters are set up, only destination VNIC can be modified.
1792 * If the destination VNIC is not specified in this command,
1793 * then the HWRM shall only create an l2 context id.
1796 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1797 filter = STAILQ_FIRST(&vnic->filter);
1798 /* Check if the VLAN has already been added */
1800 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
1803 filter = STAILQ_NEXT(filter, next);
1806 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1807 * command to create MAC+VLAN filter with the right flags, enables set.
1809 filter = bnxt_alloc_filter(bp);
1812 "MAC/VLAN filter alloc failed\n");
1815 /* MAC + VLAN ID filter */
1816 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1817 * untagged packets are received
1819 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
1820 * packets and only the programmed vlan's packets are received
1822 filter->l2_ivlan = vlan_id;
1823 filter->l2_ivlan_mask = 0x0FFF;
1824 filter->enables |= en;
1825 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1827 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1829 /* Free the newly allocated filter as we were
1830 * not able to create the filter in hardware.
1832 bnxt_free_filter(bp, filter);
1836 filter->mac_index = 0;
1837 /* Add this new filter to the list */
1839 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1841 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1844 "Added Vlan filter for %d\n", vlan_id);
1848 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1849 uint16_t vlan_id, int on)
1851 struct bnxt *bp = eth_dev->data->dev_private;
1854 rc = is_bnxt_in_error(bp);
1858 /* These operations apply to ALL existing MAC/VLAN filters */
1860 return bnxt_add_vlan_filter(bp, vlan_id);
1862 return bnxt_del_vlan_filter(bp, vlan_id);
1865 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
1866 struct bnxt_vnic_info *vnic)
1868 struct bnxt_filter_info *filter;
1871 filter = STAILQ_FIRST(&vnic->filter);
1873 if (filter->mac_index == 0 &&
1874 !memcmp(filter->l2_addr, bp->mac_addr,
1875 RTE_ETHER_ADDR_LEN)) {
1876 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1878 STAILQ_REMOVE(&vnic->filter, filter,
1879 bnxt_filter_info, next);
1880 bnxt_free_filter(bp, filter);
1884 filter = STAILQ_NEXT(filter, next);
1890 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
1892 struct bnxt_vnic_info *vnic;
1896 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1897 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1898 /* Remove any VLAN filters programmed */
1899 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1900 bnxt_del_vlan_filter(bp, i);
1902 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1906 /* Default filter will allow packets that match the
1907 * dest mac. So, it has to be deleted, otherwise, we
1908 * will endup receiving vlan packets for which the
1909 * filter is not programmed, when hw-vlan-filter
1910 * configuration is ON
1912 bnxt_del_dflt_mac_filter(bp, vnic);
1913 /* This filter will allow only untagged packets */
1914 bnxt_add_vlan_filter(bp, 0);
1916 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1917 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1922 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
1924 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
1928 /* Destroy vnic filters and vnic */
1929 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
1930 DEV_RX_OFFLOAD_VLAN_FILTER) {
1931 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1932 bnxt_del_vlan_filter(bp, i);
1934 bnxt_del_dflt_mac_filter(bp, vnic);
1936 rc = bnxt_hwrm_vnic_free(bp, vnic);
1940 rte_free(vnic->fw_grp_ids);
1941 vnic->fw_grp_ids = NULL;
1947 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
1949 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1952 /* Destroy, recreate and reconfigure the default vnic */
1953 rc = bnxt_free_one_vnic(bp, 0);
1957 /* default vnic 0 */
1958 rc = bnxt_setup_one_vnic(bp, 0);
1962 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
1963 DEV_RX_OFFLOAD_VLAN_FILTER) {
1964 rc = bnxt_add_vlan_filter(bp, 0);
1967 rc = bnxt_restore_vlan_filters(bp);
1971 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1976 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1980 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1981 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1987 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1989 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1990 struct bnxt *bp = dev->data->dev_private;
1993 rc = is_bnxt_in_error(bp);
1997 /* Filter settings will get applied when port is started */
1998 if (!dev->data->dev_started)
2001 if (mask & ETH_VLAN_FILTER_MASK) {
2002 /* Enable or disable VLAN filtering */
2003 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2008 if (mask & ETH_VLAN_STRIP_MASK) {
2009 /* Enable or disable VLAN stripping */
2010 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2015 if (mask & ETH_VLAN_EXTEND_MASK) {
2016 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2017 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2019 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2026 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2029 struct bnxt *bp = dev->data->dev_private;
2030 int qinq = dev->data->dev_conf.rxmode.offloads &
2031 DEV_RX_OFFLOAD_VLAN_EXTEND;
2033 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2034 vlan_type != ETH_VLAN_TYPE_OUTER) {
2036 "Unsupported vlan type.");
2041 "QinQ not enabled. Needs to be ON as we can "
2042 "accelerate only outer vlan\n");
2046 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2048 case RTE_ETHER_TYPE_QINQ:
2050 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2052 case RTE_ETHER_TYPE_VLAN:
2054 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2058 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2062 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2066 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2069 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2072 bp->outer_tpid_bd |= tpid;
2073 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2074 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2076 "Can accelerate only outer vlan in QinQ\n");
2084 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2085 struct rte_ether_addr *addr)
2087 struct bnxt *bp = dev->data->dev_private;
2088 /* Default Filter is tied to VNIC 0 */
2089 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2092 rc = is_bnxt_in_error(bp);
2096 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2099 if (rte_is_zero_ether_addr(addr))
2102 /* Check if the requested MAC is already added */
2103 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2106 /* Destroy filter and re-create it */
2107 bnxt_del_dflt_mac_filter(bp, vnic);
2109 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2110 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2111 /* This filter will allow only untagged packets */
2112 rc = bnxt_add_vlan_filter(bp, 0);
2114 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2117 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2122 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2123 struct rte_ether_addr *mc_addr_set,
2124 uint32_t nb_mc_addr)
2126 struct bnxt *bp = eth_dev->data->dev_private;
2127 char *mc_addr_list = (char *)mc_addr_set;
2128 struct bnxt_vnic_info *vnic;
2129 uint32_t off = 0, i = 0;
2132 rc = is_bnxt_in_error(bp);
2136 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2138 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2139 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2143 /* TODO Check for Duplicate mcast addresses */
2144 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2145 for (i = 0; i < nb_mc_addr; i++) {
2146 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2147 RTE_ETHER_ADDR_LEN);
2148 off += RTE_ETHER_ADDR_LEN;
2151 vnic->mc_addr_cnt = i;
2152 if (vnic->mc_addr_cnt)
2153 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2155 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2158 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2162 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2164 struct bnxt *bp = dev->data->dev_private;
2165 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2166 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2167 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2170 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2171 fw_major, fw_minor, fw_updt);
2173 ret += 1; /* add the size of '\0' */
2174 if (fw_size < (uint32_t)ret)
2181 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2182 struct rte_eth_rxq_info *qinfo)
2184 struct bnxt *bp = dev->data->dev_private;
2185 struct bnxt_rx_queue *rxq;
2187 if (is_bnxt_in_error(bp))
2190 rxq = dev->data->rx_queues[queue_id];
2192 qinfo->mp = rxq->mb_pool;
2193 qinfo->scattered_rx = dev->data->scattered_rx;
2194 qinfo->nb_desc = rxq->nb_rx_desc;
2196 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2197 qinfo->conf.rx_drop_en = 0;
2198 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2202 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2203 struct rte_eth_txq_info *qinfo)
2205 struct bnxt *bp = dev->data->dev_private;
2206 struct bnxt_tx_queue *txq;
2208 if (is_bnxt_in_error(bp))
2211 txq = dev->data->tx_queues[queue_id];
2213 qinfo->nb_desc = txq->nb_tx_desc;
2215 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2216 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2217 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2219 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2220 qinfo->conf.tx_rs_thresh = 0;
2221 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2224 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2226 struct bnxt *bp = eth_dev->data->dev_private;
2227 uint32_t new_pkt_size;
2231 rc = is_bnxt_in_error(bp);
2235 /* Exit if receive queues are not configured yet */
2236 if (!eth_dev->data->nb_rx_queues)
2239 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2240 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2244 * If vector-mode tx/rx is active, disallow any MTU change that would
2245 * require scattered receive support.
2247 if (eth_dev->data->dev_started &&
2248 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2249 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2251 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2253 "MTU change would require scattered rx support. ");
2254 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2259 if (new_mtu > RTE_ETHER_MTU) {
2260 bp->flags |= BNXT_FLAG_JUMBO;
2261 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2262 DEV_RX_OFFLOAD_JUMBO_FRAME;
2264 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2265 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2266 bp->flags &= ~BNXT_FLAG_JUMBO;
2269 /* Is there a change in mtu setting? */
2270 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2273 for (i = 0; i < bp->nr_vnics; i++) {
2274 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2277 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2278 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2282 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2283 size -= RTE_PKTMBUF_HEADROOM;
2285 if (size < new_mtu) {
2286 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2293 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2295 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2301 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2303 struct bnxt *bp = dev->data->dev_private;
2304 uint16_t vlan = bp->vlan;
2307 rc = is_bnxt_in_error(bp);
2311 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2313 "PVID cannot be modified for this function\n");
2316 bp->vlan = on ? pvid : 0;
2318 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2325 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2327 struct bnxt *bp = dev->data->dev_private;
2330 rc = is_bnxt_in_error(bp);
2334 return bnxt_hwrm_port_led_cfg(bp, true);
2338 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2340 struct bnxt *bp = dev->data->dev_private;
2343 rc = is_bnxt_in_error(bp);
2347 return bnxt_hwrm_port_led_cfg(bp, false);
2351 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2353 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2354 uint32_t desc = 0, raw_cons = 0, cons;
2355 struct bnxt_cp_ring_info *cpr;
2356 struct bnxt_rx_queue *rxq;
2357 struct rx_pkt_cmpl *rxcmp;
2360 rc = is_bnxt_in_error(bp);
2364 rxq = dev->data->rx_queues[rx_queue_id];
2366 raw_cons = cpr->cp_raw_cons;
2369 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2370 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2371 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2373 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2385 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2387 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2388 struct bnxt_rx_ring_info *rxr;
2389 struct bnxt_cp_ring_info *cpr;
2390 struct bnxt_sw_rx_bd *rx_buf;
2391 struct rx_pkt_cmpl *rxcmp;
2392 uint32_t cons, cp_cons;
2398 rc = is_bnxt_in_error(rxq->bp);
2405 if (offset >= rxq->nb_rx_desc)
2408 cons = RING_CMP(cpr->cp_ring_struct, offset);
2409 cp_cons = cpr->cp_raw_cons;
2410 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2412 if (cons > cp_cons) {
2413 if (CMPL_VALID(rxcmp, cpr->valid))
2414 return RTE_ETH_RX_DESC_DONE;
2416 if (CMPL_VALID(rxcmp, !cpr->valid))
2417 return RTE_ETH_RX_DESC_DONE;
2419 rx_buf = &rxr->rx_buf_ring[cons];
2420 if (rx_buf->mbuf == NULL)
2421 return RTE_ETH_RX_DESC_UNAVAIL;
2424 return RTE_ETH_RX_DESC_AVAIL;
2428 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2430 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2431 struct bnxt_tx_ring_info *txr;
2432 struct bnxt_cp_ring_info *cpr;
2433 struct bnxt_sw_tx_bd *tx_buf;
2434 struct tx_pkt_cmpl *txcmp;
2435 uint32_t cons, cp_cons;
2441 rc = is_bnxt_in_error(txq->bp);
2448 if (offset >= txq->nb_tx_desc)
2451 cons = RING_CMP(cpr->cp_ring_struct, offset);
2452 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2453 cp_cons = cpr->cp_raw_cons;
2455 if (cons > cp_cons) {
2456 if (CMPL_VALID(txcmp, cpr->valid))
2457 return RTE_ETH_TX_DESC_UNAVAIL;
2459 if (CMPL_VALID(txcmp, !cpr->valid))
2460 return RTE_ETH_TX_DESC_UNAVAIL;
2462 tx_buf = &txr->tx_buf_ring[cons];
2463 if (tx_buf->mbuf == NULL)
2464 return RTE_ETH_TX_DESC_DONE;
2466 return RTE_ETH_TX_DESC_FULL;
2469 static struct bnxt_filter_info *
2470 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2471 struct rte_eth_ethertype_filter *efilter,
2472 struct bnxt_vnic_info *vnic0,
2473 struct bnxt_vnic_info *vnic,
2476 struct bnxt_filter_info *mfilter = NULL;
2480 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2481 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2482 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2483 " ethertype filter.", efilter->ether_type);
2487 if (efilter->queue >= bp->rx_nr_rings) {
2488 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2493 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2494 vnic = &bp->vnic_info[efilter->queue];
2496 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2501 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2502 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2503 if ((!memcmp(efilter->mac_addr.addr_bytes,
2504 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2506 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2507 mfilter->ethertype == efilter->ether_type)) {
2513 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2514 if ((!memcmp(efilter->mac_addr.addr_bytes,
2515 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2516 mfilter->ethertype == efilter->ether_type &&
2518 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2532 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2533 enum rte_filter_op filter_op,
2536 struct bnxt *bp = dev->data->dev_private;
2537 struct rte_eth_ethertype_filter *efilter =
2538 (struct rte_eth_ethertype_filter *)arg;
2539 struct bnxt_filter_info *bfilter, *filter1;
2540 struct bnxt_vnic_info *vnic, *vnic0;
2543 if (filter_op == RTE_ETH_FILTER_NOP)
2547 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2552 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2553 vnic = &bp->vnic_info[efilter->queue];
2555 switch (filter_op) {
2556 case RTE_ETH_FILTER_ADD:
2557 bnxt_match_and_validate_ether_filter(bp, efilter,
2562 bfilter = bnxt_get_unused_filter(bp);
2563 if (bfilter == NULL) {
2565 "Not enough resources for a new filter.\n");
2568 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2569 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2570 RTE_ETHER_ADDR_LEN);
2571 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2572 RTE_ETHER_ADDR_LEN);
2573 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2574 bfilter->ethertype = efilter->ether_type;
2575 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2577 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2578 if (filter1 == NULL) {
2583 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2584 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2586 bfilter->dst_id = vnic->fw_vnic_id;
2588 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2590 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2593 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2596 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2598 case RTE_ETH_FILTER_DELETE:
2599 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2601 if (ret == -EEXIST) {
2602 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2604 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2606 bnxt_free_filter(bp, filter1);
2607 } else if (ret == 0) {
2608 PMD_DRV_LOG(ERR, "No matching filter found\n");
2612 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2618 bnxt_free_filter(bp, bfilter);
2624 parse_ntuple_filter(struct bnxt *bp,
2625 struct rte_eth_ntuple_filter *nfilter,
2626 struct bnxt_filter_info *bfilter)
2630 if (nfilter->queue >= bp->rx_nr_rings) {
2631 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2635 switch (nfilter->dst_port_mask) {
2637 bfilter->dst_port_mask = -1;
2638 bfilter->dst_port = nfilter->dst_port;
2639 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2640 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2643 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2647 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2648 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2650 switch (nfilter->proto_mask) {
2652 if (nfilter->proto == 17) /* IPPROTO_UDP */
2653 bfilter->ip_protocol = 17;
2654 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2655 bfilter->ip_protocol = 6;
2658 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2661 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2665 switch (nfilter->dst_ip_mask) {
2667 bfilter->dst_ipaddr_mask[0] = -1;
2668 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2669 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2670 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2673 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2677 switch (nfilter->src_ip_mask) {
2679 bfilter->src_ipaddr_mask[0] = -1;
2680 bfilter->src_ipaddr[0] = nfilter->src_ip;
2681 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2682 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2685 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2689 switch (nfilter->src_port_mask) {
2691 bfilter->src_port_mask = -1;
2692 bfilter->src_port = nfilter->src_port;
2693 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2694 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2697 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2701 bfilter->enables = en;
2705 static struct bnxt_filter_info*
2706 bnxt_match_ntuple_filter(struct bnxt *bp,
2707 struct bnxt_filter_info *bfilter,
2708 struct bnxt_vnic_info **mvnic)
2710 struct bnxt_filter_info *mfilter = NULL;
2713 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2714 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2715 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2716 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2717 bfilter->src_ipaddr_mask[0] ==
2718 mfilter->src_ipaddr_mask[0] &&
2719 bfilter->src_port == mfilter->src_port &&
2720 bfilter->src_port_mask == mfilter->src_port_mask &&
2721 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2722 bfilter->dst_ipaddr_mask[0] ==
2723 mfilter->dst_ipaddr_mask[0] &&
2724 bfilter->dst_port == mfilter->dst_port &&
2725 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2726 bfilter->flags == mfilter->flags &&
2727 bfilter->enables == mfilter->enables) {
2738 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2739 struct rte_eth_ntuple_filter *nfilter,
2740 enum rte_filter_op filter_op)
2742 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2743 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2746 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2747 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2751 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2752 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2756 bfilter = bnxt_get_unused_filter(bp);
2757 if (bfilter == NULL) {
2759 "Not enough resources for a new filter.\n");
2762 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2766 vnic = &bp->vnic_info[nfilter->queue];
2767 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2768 filter1 = STAILQ_FIRST(&vnic0->filter);
2769 if (filter1 == NULL) {
2774 bfilter->dst_id = vnic->fw_vnic_id;
2775 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2777 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2778 bfilter->ethertype = 0x800;
2779 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2781 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2783 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2784 bfilter->dst_id == mfilter->dst_id) {
2785 PMD_DRV_LOG(ERR, "filter exists.\n");
2788 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2789 bfilter->dst_id != mfilter->dst_id) {
2790 mfilter->dst_id = vnic->fw_vnic_id;
2791 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2792 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2793 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2794 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2795 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2798 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2799 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2804 if (filter_op == RTE_ETH_FILTER_ADD) {
2805 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2806 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2809 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2811 if (mfilter == NULL) {
2812 /* This should not happen. But for Coverity! */
2816 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2818 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2819 bnxt_free_filter(bp, mfilter);
2820 bnxt_free_filter(bp, bfilter);
2825 bnxt_free_filter(bp, bfilter);
2830 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2831 enum rte_filter_op filter_op,
2834 struct bnxt *bp = dev->data->dev_private;
2837 if (filter_op == RTE_ETH_FILTER_NOP)
2841 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2846 switch (filter_op) {
2847 case RTE_ETH_FILTER_ADD:
2848 ret = bnxt_cfg_ntuple_filter(bp,
2849 (struct rte_eth_ntuple_filter *)arg,
2852 case RTE_ETH_FILTER_DELETE:
2853 ret = bnxt_cfg_ntuple_filter(bp,
2854 (struct rte_eth_ntuple_filter *)arg,
2858 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2866 bnxt_parse_fdir_filter(struct bnxt *bp,
2867 struct rte_eth_fdir_filter *fdir,
2868 struct bnxt_filter_info *filter)
2870 enum rte_fdir_mode fdir_mode =
2871 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2872 struct bnxt_vnic_info *vnic0, *vnic;
2873 struct bnxt_filter_info *filter1;
2877 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2880 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2881 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2883 switch (fdir->input.flow_type) {
2884 case RTE_ETH_FLOW_IPV4:
2885 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2887 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2888 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2889 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2890 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2891 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2892 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2893 filter->ip_addr_type =
2894 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2895 filter->src_ipaddr_mask[0] = 0xffffffff;
2896 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2897 filter->dst_ipaddr_mask[0] = 0xffffffff;
2898 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2899 filter->ethertype = 0x800;
2900 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2902 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2903 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2904 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2905 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2906 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2907 filter->dst_port_mask = 0xffff;
2908 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2909 filter->src_port_mask = 0xffff;
2910 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2911 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2912 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2913 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2914 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2915 filter->ip_protocol = 6;
2916 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2917 filter->ip_addr_type =
2918 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2919 filter->src_ipaddr_mask[0] = 0xffffffff;
2920 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2921 filter->dst_ipaddr_mask[0] = 0xffffffff;
2922 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2923 filter->ethertype = 0x800;
2924 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2926 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2927 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2928 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2929 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2930 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2931 filter->dst_port_mask = 0xffff;
2932 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2933 filter->src_port_mask = 0xffff;
2934 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2935 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2936 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2937 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2938 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2939 filter->ip_protocol = 17;
2940 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2941 filter->ip_addr_type =
2942 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2943 filter->src_ipaddr_mask[0] = 0xffffffff;
2944 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2945 filter->dst_ipaddr_mask[0] = 0xffffffff;
2946 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2947 filter->ethertype = 0x800;
2948 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2950 case RTE_ETH_FLOW_IPV6:
2951 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2953 filter->ip_addr_type =
2954 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2955 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2956 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2957 rte_memcpy(filter->src_ipaddr,
2958 fdir->input.flow.ipv6_flow.src_ip, 16);
2959 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2960 rte_memcpy(filter->dst_ipaddr,
2961 fdir->input.flow.ipv6_flow.dst_ip, 16);
2962 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2963 memset(filter->dst_ipaddr_mask, 0xff, 16);
2964 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2965 memset(filter->src_ipaddr_mask, 0xff, 16);
2966 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2967 filter->ethertype = 0x86dd;
2968 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2970 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2971 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2972 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2973 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2974 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2975 filter->dst_port_mask = 0xffff;
2976 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2977 filter->src_port_mask = 0xffff;
2978 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2979 filter->ip_addr_type =
2980 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2981 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2982 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2983 rte_memcpy(filter->src_ipaddr,
2984 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2985 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2986 rte_memcpy(filter->dst_ipaddr,
2987 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2988 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2989 memset(filter->dst_ipaddr_mask, 0xff, 16);
2990 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2991 memset(filter->src_ipaddr_mask, 0xff, 16);
2992 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2993 filter->ethertype = 0x86dd;
2994 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2996 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2997 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2998 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2999 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3000 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3001 filter->dst_port_mask = 0xffff;
3002 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3003 filter->src_port_mask = 0xffff;
3004 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3005 filter->ip_addr_type =
3006 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3007 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3008 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3009 rte_memcpy(filter->src_ipaddr,
3010 fdir->input.flow.udp6_flow.ip.src_ip, 16);
3011 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3012 rte_memcpy(filter->dst_ipaddr,
3013 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3014 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3015 memset(filter->dst_ipaddr_mask, 0xff, 16);
3016 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3017 memset(filter->src_ipaddr_mask, 0xff, 16);
3018 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3019 filter->ethertype = 0x86dd;
3020 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3022 case RTE_ETH_FLOW_L2_PAYLOAD:
3023 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3024 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3026 case RTE_ETH_FLOW_VXLAN:
3027 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3029 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3030 filter->tunnel_type =
3031 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3032 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3034 case RTE_ETH_FLOW_NVGRE:
3035 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3037 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3038 filter->tunnel_type =
3039 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3040 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3042 case RTE_ETH_FLOW_UNKNOWN:
3043 case RTE_ETH_FLOW_RAW:
3044 case RTE_ETH_FLOW_FRAG_IPV4:
3045 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3046 case RTE_ETH_FLOW_FRAG_IPV6:
3047 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3048 case RTE_ETH_FLOW_IPV6_EX:
3049 case RTE_ETH_FLOW_IPV6_TCP_EX:
3050 case RTE_ETH_FLOW_IPV6_UDP_EX:
3051 case RTE_ETH_FLOW_GENEVE:
3057 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3058 vnic = &bp->vnic_info[fdir->action.rx_queue];
3060 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3064 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3065 rte_memcpy(filter->dst_macaddr,
3066 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3067 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3070 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3071 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3072 filter1 = STAILQ_FIRST(&vnic0->filter);
3073 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3075 filter->dst_id = vnic->fw_vnic_id;
3076 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3077 if (filter->dst_macaddr[i] == 0x00)
3078 filter1 = STAILQ_FIRST(&vnic0->filter);
3080 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3083 if (filter1 == NULL)
3086 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3087 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3089 filter->enables = en;
3094 static struct bnxt_filter_info *
3095 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3096 struct bnxt_vnic_info **mvnic)
3098 struct bnxt_filter_info *mf = NULL;
3101 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3102 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3104 STAILQ_FOREACH(mf, &vnic->filter, next) {
3105 if (mf->filter_type == nf->filter_type &&
3106 mf->flags == nf->flags &&
3107 mf->src_port == nf->src_port &&
3108 mf->src_port_mask == nf->src_port_mask &&
3109 mf->dst_port == nf->dst_port &&
3110 mf->dst_port_mask == nf->dst_port_mask &&
3111 mf->ip_protocol == nf->ip_protocol &&
3112 mf->ip_addr_type == nf->ip_addr_type &&
3113 mf->ethertype == nf->ethertype &&
3114 mf->vni == nf->vni &&
3115 mf->tunnel_type == nf->tunnel_type &&
3116 mf->l2_ovlan == nf->l2_ovlan &&
3117 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3118 mf->l2_ivlan == nf->l2_ivlan &&
3119 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3120 !memcmp(mf->l2_addr, nf->l2_addr,
3121 RTE_ETHER_ADDR_LEN) &&
3122 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3123 RTE_ETHER_ADDR_LEN) &&
3124 !memcmp(mf->src_macaddr, nf->src_macaddr,
3125 RTE_ETHER_ADDR_LEN) &&
3126 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3127 RTE_ETHER_ADDR_LEN) &&
3128 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3129 sizeof(nf->src_ipaddr)) &&
3130 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3131 sizeof(nf->src_ipaddr_mask)) &&
3132 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3133 sizeof(nf->dst_ipaddr)) &&
3134 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3135 sizeof(nf->dst_ipaddr_mask))) {
3146 bnxt_fdir_filter(struct rte_eth_dev *dev,
3147 enum rte_filter_op filter_op,
3150 struct bnxt *bp = dev->data->dev_private;
3151 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
3152 struct bnxt_filter_info *filter, *match;
3153 struct bnxt_vnic_info *vnic, *mvnic;
3156 if (filter_op == RTE_ETH_FILTER_NOP)
3159 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3162 switch (filter_op) {
3163 case RTE_ETH_FILTER_ADD:
3164 case RTE_ETH_FILTER_DELETE:
3166 filter = bnxt_get_unused_filter(bp);
3167 if (filter == NULL) {
3169 "Not enough resources for a new flow.\n");
3173 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3176 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3178 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3179 vnic = &bp->vnic_info[0];
3181 vnic = &bp->vnic_info[fdir->action.rx_queue];
3183 match = bnxt_match_fdir(bp, filter, &mvnic);
3184 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3185 if (match->dst_id == vnic->fw_vnic_id) {
3186 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3190 match->dst_id = vnic->fw_vnic_id;
3191 ret = bnxt_hwrm_set_ntuple_filter(bp,
3194 STAILQ_REMOVE(&mvnic->filter, match,
3195 bnxt_filter_info, next);
3196 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3198 "Filter with matching pattern exist\n");
3200 "Updated it to new destination q\n");
3204 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3205 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3210 if (filter_op == RTE_ETH_FILTER_ADD) {
3211 ret = bnxt_hwrm_set_ntuple_filter(bp,
3216 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3218 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3219 STAILQ_REMOVE(&vnic->filter, match,
3220 bnxt_filter_info, next);
3221 bnxt_free_filter(bp, match);
3222 bnxt_free_filter(bp, filter);
3225 case RTE_ETH_FILTER_FLUSH:
3226 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3227 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3229 STAILQ_FOREACH(filter, &vnic->filter, next) {
3230 if (filter->filter_type ==
3231 HWRM_CFA_NTUPLE_FILTER) {
3233 bnxt_hwrm_clear_ntuple_filter(bp,
3235 STAILQ_REMOVE(&vnic->filter, filter,
3236 bnxt_filter_info, next);
3241 case RTE_ETH_FILTER_UPDATE:
3242 case RTE_ETH_FILTER_STATS:
3243 case RTE_ETH_FILTER_INFO:
3244 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3247 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3254 bnxt_free_filter(bp, filter);
3259 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3260 enum rte_filter_type filter_type,
3261 enum rte_filter_op filter_op, void *arg)
3265 ret = is_bnxt_in_error(dev->data->dev_private);
3269 switch (filter_type) {
3270 case RTE_ETH_FILTER_TUNNEL:
3272 "filter type: %d: To be implemented\n", filter_type);
3274 case RTE_ETH_FILTER_FDIR:
3275 ret = bnxt_fdir_filter(dev, filter_op, arg);
3277 case RTE_ETH_FILTER_NTUPLE:
3278 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3280 case RTE_ETH_FILTER_ETHERTYPE:
3281 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3283 case RTE_ETH_FILTER_GENERIC:
3284 if (filter_op != RTE_ETH_FILTER_GET)
3286 *(const void **)arg = &bnxt_flow_ops;
3290 "Filter type (%d) not supported", filter_type);
3297 static const uint32_t *
3298 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3300 static const uint32_t ptypes[] = {
3301 RTE_PTYPE_L2_ETHER_VLAN,
3302 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3303 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3307 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3308 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3309 RTE_PTYPE_INNER_L4_ICMP,
3310 RTE_PTYPE_INNER_L4_TCP,
3311 RTE_PTYPE_INNER_L4_UDP,
3315 if (!dev->rx_pkt_burst)
3321 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3324 uint32_t reg_base = *reg_arr & 0xfffff000;
3328 for (i = 0; i < count; i++) {
3329 if ((reg_arr[i] & 0xfffff000) != reg_base)
3332 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3333 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3337 static int bnxt_map_ptp_regs(struct bnxt *bp)
3339 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3343 reg_arr = ptp->rx_regs;
3344 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3348 reg_arr = ptp->tx_regs;
3349 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3353 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3354 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3356 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3357 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3362 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3364 rte_write32(0, (uint8_t *)bp->bar0 +
3365 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3366 rte_write32(0, (uint8_t *)bp->bar0 +
3367 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3370 static uint64_t bnxt_cc_read(struct bnxt *bp)
3374 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3375 BNXT_GRCPF_REG_SYNC_TIME));
3376 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3377 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3381 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3383 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3386 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3387 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3388 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3391 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3392 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3393 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3394 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3395 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3396 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3401 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3403 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3404 struct bnxt_pf_info *pf = &bp->pf;
3411 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3412 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3413 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3416 port_id = pf->port_id;
3417 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3418 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3420 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3421 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3422 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3423 /* bnxt_clr_rx_ts(bp); TBD */
3427 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3428 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3429 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3430 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3436 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3439 struct bnxt *bp = dev->data->dev_private;
3440 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3445 ns = rte_timespec_to_ns(ts);
3446 /* Set the timecounters to a new value. */
3453 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3455 struct bnxt *bp = dev->data->dev_private;
3456 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3457 uint64_t ns, systime_cycles = 0;
3463 if (BNXT_CHIP_THOR(bp))
3464 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3467 systime_cycles = bnxt_cc_read(bp);
3469 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3470 *ts = rte_ns_to_timespec(ns);
3475 bnxt_timesync_enable(struct rte_eth_dev *dev)
3477 struct bnxt *bp = dev->data->dev_private;
3478 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3486 ptp->tx_tstamp_en = 1;
3487 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3489 rc = bnxt_hwrm_ptp_cfg(bp);
3493 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3494 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3495 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3497 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3498 ptp->tc.cc_shift = shift;
3499 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3501 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3502 ptp->rx_tstamp_tc.cc_shift = shift;
3503 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3505 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3506 ptp->tx_tstamp_tc.cc_shift = shift;
3507 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3509 if (!BNXT_CHIP_THOR(bp))
3510 bnxt_map_ptp_regs(bp);
3516 bnxt_timesync_disable(struct rte_eth_dev *dev)
3518 struct bnxt *bp = dev->data->dev_private;
3519 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3525 ptp->tx_tstamp_en = 0;
3528 bnxt_hwrm_ptp_cfg(bp);
3530 if (!BNXT_CHIP_THOR(bp))
3531 bnxt_unmap_ptp_regs(bp);
3537 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3538 struct timespec *timestamp,
3539 uint32_t flags __rte_unused)
3541 struct bnxt *bp = dev->data->dev_private;
3542 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3543 uint64_t rx_tstamp_cycles = 0;
3549 if (BNXT_CHIP_THOR(bp))
3550 rx_tstamp_cycles = ptp->rx_timestamp;
3552 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3554 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3555 *timestamp = rte_ns_to_timespec(ns);
3560 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3561 struct timespec *timestamp)
3563 struct bnxt *bp = dev->data->dev_private;
3564 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3565 uint64_t tx_tstamp_cycles = 0;
3572 if (BNXT_CHIP_THOR(bp))
3573 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3576 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3578 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3579 *timestamp = rte_ns_to_timespec(ns);
3585 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3587 struct bnxt *bp = dev->data->dev_private;
3588 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3593 ptp->tc.nsec += delta;
3599 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3601 struct bnxt *bp = dev->data->dev_private;
3603 uint32_t dir_entries;
3604 uint32_t entry_length;
3606 rc = is_bnxt_in_error(bp);
3610 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3611 bp->pdev->addr.domain, bp->pdev->addr.bus,
3612 bp->pdev->addr.devid, bp->pdev->addr.function);
3614 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3618 return dir_entries * entry_length;
3622 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3623 struct rte_dev_eeprom_info *in_eeprom)
3625 struct bnxt *bp = dev->data->dev_private;
3630 rc = is_bnxt_in_error(bp);
3634 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3635 bp->pdev->addr.domain, bp->pdev->addr.bus,
3636 bp->pdev->addr.devid, bp->pdev->addr.function,
3637 in_eeprom->offset, in_eeprom->length);
3639 if (in_eeprom->offset == 0) /* special offset value to get directory */
3640 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3643 index = in_eeprom->offset >> 24;
3644 offset = in_eeprom->offset & 0xffffff;
3647 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3648 in_eeprom->length, in_eeprom->data);
3653 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3656 case BNX_DIR_TYPE_CHIMP_PATCH:
3657 case BNX_DIR_TYPE_BOOTCODE:
3658 case BNX_DIR_TYPE_BOOTCODE_2:
3659 case BNX_DIR_TYPE_APE_FW:
3660 case BNX_DIR_TYPE_APE_PATCH:
3661 case BNX_DIR_TYPE_KONG_FW:
3662 case BNX_DIR_TYPE_KONG_PATCH:
3663 case BNX_DIR_TYPE_BONO_FW:
3664 case BNX_DIR_TYPE_BONO_PATCH:
3672 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3675 case BNX_DIR_TYPE_AVS:
3676 case BNX_DIR_TYPE_EXP_ROM_MBA:
3677 case BNX_DIR_TYPE_PCIE:
3678 case BNX_DIR_TYPE_TSCF_UCODE:
3679 case BNX_DIR_TYPE_EXT_PHY:
3680 case BNX_DIR_TYPE_CCM:
3681 case BNX_DIR_TYPE_ISCSI_BOOT:
3682 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3683 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3691 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3693 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3694 bnxt_dir_type_is_other_exec_format(dir_type);
3698 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3699 struct rte_dev_eeprom_info *in_eeprom)
3701 struct bnxt *bp = dev->data->dev_private;
3702 uint8_t index, dir_op;
3703 uint16_t type, ext, ordinal, attr;
3706 rc = is_bnxt_in_error(bp);
3710 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3711 bp->pdev->addr.domain, bp->pdev->addr.bus,
3712 bp->pdev->addr.devid, bp->pdev->addr.function,
3713 in_eeprom->offset, in_eeprom->length);
3716 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3720 type = in_eeprom->magic >> 16;
3722 if (type == 0xffff) { /* special value for directory operations */
3723 index = in_eeprom->magic & 0xff;
3724 dir_op = in_eeprom->magic >> 8;
3728 case 0x0e: /* erase */
3729 if (in_eeprom->offset != ~in_eeprom->magic)
3731 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3737 /* Create or re-write an NVM item: */
3738 if (bnxt_dir_type_is_executable(type) == true)
3740 ext = in_eeprom->magic & 0xffff;
3741 ordinal = in_eeprom->offset >> 16;
3742 attr = in_eeprom->offset & 0xffff;
3744 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3745 in_eeprom->data, in_eeprom->length);
3752 static const struct eth_dev_ops bnxt_dev_ops = {
3753 .dev_infos_get = bnxt_dev_info_get_op,
3754 .dev_close = bnxt_dev_close_op,
3755 .dev_configure = bnxt_dev_configure_op,
3756 .dev_start = bnxt_dev_start_op,
3757 .dev_stop = bnxt_dev_stop_op,
3758 .dev_set_link_up = bnxt_dev_set_link_up_op,
3759 .dev_set_link_down = bnxt_dev_set_link_down_op,
3760 .stats_get = bnxt_stats_get_op,
3761 .stats_reset = bnxt_stats_reset_op,
3762 .rx_queue_setup = bnxt_rx_queue_setup_op,
3763 .rx_queue_release = bnxt_rx_queue_release_op,
3764 .tx_queue_setup = bnxt_tx_queue_setup_op,
3765 .tx_queue_release = bnxt_tx_queue_release_op,
3766 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3767 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3768 .reta_update = bnxt_reta_update_op,
3769 .reta_query = bnxt_reta_query_op,
3770 .rss_hash_update = bnxt_rss_hash_update_op,
3771 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3772 .link_update = bnxt_link_update_op,
3773 .promiscuous_enable = bnxt_promiscuous_enable_op,
3774 .promiscuous_disable = bnxt_promiscuous_disable_op,
3775 .allmulticast_enable = bnxt_allmulticast_enable_op,
3776 .allmulticast_disable = bnxt_allmulticast_disable_op,
3777 .mac_addr_add = bnxt_mac_addr_add_op,
3778 .mac_addr_remove = bnxt_mac_addr_remove_op,
3779 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3780 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3781 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3782 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3783 .vlan_filter_set = bnxt_vlan_filter_set_op,
3784 .vlan_offload_set = bnxt_vlan_offload_set_op,
3785 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3786 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3787 .mtu_set = bnxt_mtu_set_op,
3788 .mac_addr_set = bnxt_set_default_mac_addr_op,
3789 .xstats_get = bnxt_dev_xstats_get_op,
3790 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3791 .xstats_reset = bnxt_dev_xstats_reset_op,
3792 .fw_version_get = bnxt_fw_version_get,
3793 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3794 .rxq_info_get = bnxt_rxq_info_get_op,
3795 .txq_info_get = bnxt_txq_info_get_op,
3796 .dev_led_on = bnxt_dev_led_on_op,
3797 .dev_led_off = bnxt_dev_led_off_op,
3798 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3799 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3800 .rx_queue_count = bnxt_rx_queue_count_op,
3801 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3802 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3803 .rx_queue_start = bnxt_rx_queue_start,
3804 .rx_queue_stop = bnxt_rx_queue_stop,
3805 .tx_queue_start = bnxt_tx_queue_start,
3806 .tx_queue_stop = bnxt_tx_queue_stop,
3807 .filter_ctrl = bnxt_filter_ctrl_op,
3808 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3809 .get_eeprom_length = bnxt_get_eeprom_length_op,
3810 .get_eeprom = bnxt_get_eeprom_op,
3811 .set_eeprom = bnxt_set_eeprom_op,
3812 .timesync_enable = bnxt_timesync_enable,
3813 .timesync_disable = bnxt_timesync_disable,
3814 .timesync_read_time = bnxt_timesync_read_time,
3815 .timesync_write_time = bnxt_timesync_write_time,
3816 .timesync_adjust_time = bnxt_timesync_adjust_time,
3817 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3818 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3821 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3825 /* Only pre-map the reset GRC registers using window 3 */
3826 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3827 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3829 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3834 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3836 struct bnxt_error_recovery_info *info = bp->recovery_info;
3837 uint32_t reg_base = 0xffffffff;
3840 /* Only pre-map the monitoring GRC registers using window 2 */
3841 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3842 uint32_t reg = info->status_regs[i];
3844 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3847 if (reg_base == 0xffffffff)
3848 reg_base = reg & 0xfffff000;
3849 if ((reg & 0xfffff000) != reg_base)
3852 /* Use mask 0xffc as the Lower 2 bits indicates
3853 * address space location
3855 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3859 if (reg_base == 0xffffffff)
3862 rte_write32(reg_base, (uint8_t *)bp->bar0 +
3863 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3868 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3870 struct bnxt_error_recovery_info *info = bp->recovery_info;
3871 uint32_t delay = info->delay_after_reset[index];
3872 uint32_t val = info->reset_reg_val[index];
3873 uint32_t reg = info->reset_reg[index];
3874 uint32_t type, offset;
3876 type = BNXT_FW_STATUS_REG_TYPE(reg);
3877 offset = BNXT_FW_STATUS_REG_OFF(reg);
3880 case BNXT_FW_STATUS_REG_TYPE_CFG:
3881 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3883 case BNXT_FW_STATUS_REG_TYPE_GRC:
3884 offset = bnxt_map_reset_regs(bp, offset);
3885 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3887 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3888 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3891 /* wait on a specific interval of time until core reset is complete */
3893 rte_delay_ms(delay);
3896 static void bnxt_dev_cleanup(struct bnxt *bp)
3898 bnxt_set_hwrm_link_config(bp, false);
3899 bp->link_info.link_up = 0;
3900 if (bp->eth_dev->data->dev_started)
3901 bnxt_dev_stop_op(bp->eth_dev);
3903 bnxt_uninit_resources(bp, true);
3906 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3908 struct rte_eth_dev *dev = bp->eth_dev;
3909 struct rte_vlan_filter_conf *vfc;
3913 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3914 vfc = &dev->data->vlan_filter_conf;
3915 vidx = vlan_id / 64;
3916 vbit = vlan_id % 64;
3918 /* Each bit corresponds to a VLAN id */
3919 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3920 rc = bnxt_add_vlan_filter(bp, vlan_id);
3929 static int bnxt_restore_mac_filters(struct bnxt *bp)
3931 struct rte_eth_dev *dev = bp->eth_dev;
3932 struct rte_eth_dev_info dev_info;
3933 struct rte_ether_addr *addr;
3939 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
3942 rc = bnxt_dev_info_get_op(dev, &dev_info);
3946 /* replay MAC address configuration */
3947 for (i = 1; i < dev_info.max_mac_addrs; i++) {
3948 addr = &dev->data->mac_addrs[i];
3950 /* skip zero address */
3951 if (rte_is_zero_ether_addr(addr))
3955 pool_mask = dev->data->mac_pool_sel[i];
3958 if (pool_mask & 1ULL) {
3959 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3965 } while (pool_mask);
3971 static int bnxt_restore_filters(struct bnxt *bp)
3973 struct rte_eth_dev *dev = bp->eth_dev;
3976 if (dev->data->all_multicast) {
3977 ret = bnxt_allmulticast_enable_op(dev);
3981 if (dev->data->promiscuous) {
3982 ret = bnxt_promiscuous_enable_op(dev);
3987 ret = bnxt_restore_mac_filters(bp);
3991 ret = bnxt_restore_vlan_filters(bp);
3992 /* TODO restore other filters as well */
3996 static void bnxt_dev_recover(void *arg)
3998 struct bnxt *bp = arg;
3999 int timeout = bp->fw_reset_max_msecs;
4002 /* Clear Error flag so that device re-init should happen */
4003 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4006 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4009 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4010 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4011 } while (rc && timeout);
4014 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4018 rc = bnxt_init_resources(bp, true);
4021 "Failed to initialize resources after reset\n");
4024 /* clear reset flag as the device is initialized now */
4025 bp->flags &= ~BNXT_FLAG_FW_RESET;
4027 rc = bnxt_dev_start_op(bp->eth_dev);
4029 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4033 rc = bnxt_restore_filters(bp);
4037 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4040 bnxt_dev_stop_op(bp->eth_dev);
4042 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4043 bnxt_uninit_resources(bp, false);
4044 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4047 void bnxt_dev_reset_and_resume(void *arg)
4049 struct bnxt *bp = arg;
4052 bnxt_dev_cleanup(bp);
4054 bnxt_wait_for_device_shutdown(bp);
4056 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4057 bnxt_dev_recover, (void *)bp);
4059 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4062 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4064 struct bnxt_error_recovery_info *info = bp->recovery_info;
4065 uint32_t reg = info->status_regs[index];
4066 uint32_t type, offset, val = 0;
4068 type = BNXT_FW_STATUS_REG_TYPE(reg);
4069 offset = BNXT_FW_STATUS_REG_OFF(reg);
4072 case BNXT_FW_STATUS_REG_TYPE_CFG:
4073 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4075 case BNXT_FW_STATUS_REG_TYPE_GRC:
4076 offset = info->mapped_status_regs[index];
4078 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4079 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4087 static int bnxt_fw_reset_all(struct bnxt *bp)
4089 struct bnxt_error_recovery_info *info = bp->recovery_info;
4093 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4094 /* Reset through master function driver */
4095 for (i = 0; i < info->reg_array_cnt; i++)
4096 bnxt_write_fw_reset_reg(bp, i);
4097 /* Wait for time specified by FW after triggering reset */
4098 rte_delay_ms(info->master_func_wait_period_after_reset);
4099 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4100 /* Reset with the help of Kong processor */
4101 rc = bnxt_hwrm_fw_reset(bp);
4103 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4109 static void bnxt_fw_reset_cb(void *arg)
4111 struct bnxt *bp = arg;
4112 struct bnxt_error_recovery_info *info = bp->recovery_info;
4115 /* Only Master function can do FW reset */
4116 if (bnxt_is_master_func(bp) &&
4117 bnxt_is_recovery_enabled(bp)) {
4118 rc = bnxt_fw_reset_all(bp);
4120 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4125 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4126 * EXCEPTION_FATAL_ASYNC event to all the functions
4127 * (including MASTER FUNC). After receiving this Async, all the active
4128 * drivers should treat this case as FW initiated recovery
4130 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4131 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4132 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4134 /* To recover from error */
4135 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4140 /* Driver should poll FW heartbeat, reset_counter with the frequency
4141 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4142 * When the driver detects heartbeat stop or change in reset_counter,
4143 * it has to trigger a reset to recover from the error condition.
4144 * A “master PF” is the function who will have the privilege to
4145 * initiate the chimp reset. The master PF will be elected by the
4146 * firmware and will be notified through async message.
4148 static void bnxt_check_fw_health(void *arg)
4150 struct bnxt *bp = arg;
4151 struct bnxt_error_recovery_info *info = bp->recovery_info;
4152 uint32_t val = 0, wait_msec;
4154 if (!info || !bnxt_is_recovery_enabled(bp) ||
4155 is_bnxt_in_error(bp))
4158 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4159 if (val == info->last_heart_beat)
4162 info->last_heart_beat = val;
4164 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4165 if (val != info->last_reset_counter)
4168 info->last_reset_counter = val;
4170 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4171 bnxt_check_fw_health, (void *)bp);
4175 /* Stop DMA to/from device */
4176 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4177 bp->flags |= BNXT_FLAG_FW_RESET;
4179 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4181 if (bnxt_is_master_func(bp))
4182 wait_msec = info->master_func_wait_period;
4184 wait_msec = info->normal_func_wait_period;
4186 rte_eal_alarm_set(US_PER_MS * wait_msec,
4187 bnxt_fw_reset_cb, (void *)bp);
4190 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4192 uint32_t polling_freq;
4194 if (!bnxt_is_recovery_enabled(bp))
4197 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4200 polling_freq = bp->recovery_info->driver_polling_freq;
4202 rte_eal_alarm_set(US_PER_MS * polling_freq,
4203 bnxt_check_fw_health, (void *)bp);
4204 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4207 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4209 if (!bnxt_is_recovery_enabled(bp))
4212 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4213 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4216 static bool bnxt_vf_pciid(uint16_t device_id)
4218 switch (device_id) {
4219 case BROADCOM_DEV_ID_57304_VF:
4220 case BROADCOM_DEV_ID_57406_VF:
4221 case BROADCOM_DEV_ID_5731X_VF:
4222 case BROADCOM_DEV_ID_5741X_VF:
4223 case BROADCOM_DEV_ID_57414_VF:
4224 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4225 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4226 case BROADCOM_DEV_ID_58802_VF:
4227 case BROADCOM_DEV_ID_57500_VF1:
4228 case BROADCOM_DEV_ID_57500_VF2:
4236 static bool bnxt_thor_device(uint16_t device_id)
4238 switch (device_id) {
4239 case BROADCOM_DEV_ID_57508:
4240 case BROADCOM_DEV_ID_57504:
4241 case BROADCOM_DEV_ID_57502:
4242 case BROADCOM_DEV_ID_57508_MF1:
4243 case BROADCOM_DEV_ID_57504_MF1:
4244 case BROADCOM_DEV_ID_57502_MF1:
4245 case BROADCOM_DEV_ID_57508_MF2:
4246 case BROADCOM_DEV_ID_57504_MF2:
4247 case BROADCOM_DEV_ID_57502_MF2:
4248 case BROADCOM_DEV_ID_57500_VF1:
4249 case BROADCOM_DEV_ID_57500_VF2:
4257 bool bnxt_stratus_device(struct bnxt *bp)
4259 uint16_t device_id = bp->pdev->id.device_id;
4261 switch (device_id) {
4262 case BROADCOM_DEV_ID_STRATUS_NIC:
4263 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4264 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4272 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4274 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4275 struct bnxt *bp = eth_dev->data->dev_private;
4277 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4278 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4279 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4280 if (!bp->bar0 || !bp->doorbell_base) {
4281 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4285 bp->eth_dev = eth_dev;
4291 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4292 struct bnxt_ctx_pg_info *ctx_pg,
4297 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4298 const struct rte_memzone *mz = NULL;
4299 char mz_name[RTE_MEMZONE_NAMESIZE];
4300 rte_iova_t mz_phys_addr;
4301 uint64_t valid_bits = 0;
4308 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4310 rmem->page_size = BNXT_PAGE_SIZE;
4311 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4312 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4313 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4315 valid_bits = PTU_PTE_VALID;
4317 if (rmem->nr_pages > 1) {
4318 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4319 "bnxt_ctx_pg_tbl%s_%x_%d",
4320 suffix, idx, bp->eth_dev->data->port_id);
4321 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4322 mz = rte_memzone_lookup(mz_name);
4324 mz = rte_memzone_reserve_aligned(mz_name,
4328 RTE_MEMZONE_SIZE_HINT_ONLY |
4329 RTE_MEMZONE_IOVA_CONTIG,
4335 memset(mz->addr, 0, mz->len);
4336 mz_phys_addr = mz->iova;
4338 rmem->pg_tbl = mz->addr;
4339 rmem->pg_tbl_map = mz_phys_addr;
4340 rmem->pg_tbl_mz = mz;
4343 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4344 suffix, idx, bp->eth_dev->data->port_id);
4345 mz = rte_memzone_lookup(mz_name);
4347 mz = rte_memzone_reserve_aligned(mz_name,
4351 RTE_MEMZONE_SIZE_HINT_ONLY |
4352 RTE_MEMZONE_IOVA_CONTIG,
4358 memset(mz->addr, 0, mz->len);
4359 mz_phys_addr = mz->iova;
4361 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4362 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4363 rmem->dma_arr[i] = mz_phys_addr + sz;
4365 if (rmem->nr_pages > 1) {
4366 if (i == rmem->nr_pages - 2 &&
4367 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4368 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4369 else if (i == rmem->nr_pages - 1 &&
4370 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4371 valid_bits |= PTU_PTE_LAST;
4373 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4379 if (rmem->vmem_size)
4380 rmem->vmem = (void **)mz->addr;
4381 rmem->dma_arr[0] = mz_phys_addr;
4385 static void bnxt_free_ctx_mem(struct bnxt *bp)
4389 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4392 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4393 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4394 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4395 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4396 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4397 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4398 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4399 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4400 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4401 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4402 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4404 for (i = 0; i < BNXT_MAX_Q; i++) {
4405 if (bp->ctx->tqm_mem[i])
4406 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4413 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4415 #define min_t(type, x, y) ({ \
4416 type __min1 = (x); \
4417 type __min2 = (y); \
4418 __min1 < __min2 ? __min1 : __min2; })
4420 #define max_t(type, x, y) ({ \
4421 type __max1 = (x); \
4422 type __max2 = (y); \
4423 __max1 > __max2 ? __max1 : __max2; })
4425 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4427 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4429 struct bnxt_ctx_pg_info *ctx_pg;
4430 struct bnxt_ctx_mem_info *ctx;
4431 uint32_t mem_size, ena, entries;
4434 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4436 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4440 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4443 ctx_pg = &ctx->qp_mem;
4444 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4445 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4446 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4450 ctx_pg = &ctx->srq_mem;
4451 ctx_pg->entries = ctx->srq_max_l2_entries;
4452 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4453 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4457 ctx_pg = &ctx->cq_mem;
4458 ctx_pg->entries = ctx->cq_max_l2_entries;
4459 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4460 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4464 ctx_pg = &ctx->vnic_mem;
4465 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4466 ctx->vnic_max_ring_table_entries;
4467 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4468 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4472 ctx_pg = &ctx->stat_mem;
4473 ctx_pg->entries = ctx->stat_max_entries;
4474 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4475 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4479 entries = ctx->qp_max_l2_entries +
4480 ctx->vnic_max_vnic_entries +
4481 ctx->tqm_min_entries_per_ring;
4482 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4483 entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4484 ctx->tqm_max_entries_per_ring);
4485 for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4486 ctx_pg = ctx->tqm_mem[i];
4487 /* use min tqm entries for now. */
4488 ctx_pg->entries = entries;
4489 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4490 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4493 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4496 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4497 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4500 "Failed to configure context mem: rc = %d\n", rc);
4502 ctx->flags |= BNXT_CTX_FLAG_INITED;
4507 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4509 struct rte_pci_device *pci_dev = bp->pdev;
4510 char mz_name[RTE_MEMZONE_NAMESIZE];
4511 const struct rte_memzone *mz = NULL;
4512 uint32_t total_alloc_len;
4513 rte_iova_t mz_phys_addr;
4515 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4518 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4519 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4520 pci_dev->addr.bus, pci_dev->addr.devid,
4521 pci_dev->addr.function, "rx_port_stats");
4522 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4523 mz = rte_memzone_lookup(mz_name);
4525 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4526 sizeof(struct rx_port_stats_ext) + 512);
4528 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4531 RTE_MEMZONE_SIZE_HINT_ONLY |
4532 RTE_MEMZONE_IOVA_CONTIG);
4536 memset(mz->addr, 0, mz->len);
4537 mz_phys_addr = mz->iova;
4539 bp->rx_mem_zone = (const void *)mz;
4540 bp->hw_rx_port_stats = mz->addr;
4541 bp->hw_rx_port_stats_map = mz_phys_addr;
4543 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4544 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4545 pci_dev->addr.bus, pci_dev->addr.devid,
4546 pci_dev->addr.function, "tx_port_stats");
4547 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4548 mz = rte_memzone_lookup(mz_name);
4550 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4551 sizeof(struct tx_port_stats_ext) + 512);
4553 mz = rte_memzone_reserve(mz_name,
4557 RTE_MEMZONE_SIZE_HINT_ONLY |
4558 RTE_MEMZONE_IOVA_CONTIG);
4562 memset(mz->addr, 0, mz->len);
4563 mz_phys_addr = mz->iova;
4565 bp->tx_mem_zone = (const void *)mz;
4566 bp->hw_tx_port_stats = mz->addr;
4567 bp->hw_tx_port_stats_map = mz_phys_addr;
4568 bp->flags |= BNXT_FLAG_PORT_STATS;
4570 /* Display extended statistics if FW supports it */
4571 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4572 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4573 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4576 bp->hw_rx_port_stats_ext = (void *)
4577 ((uint8_t *)bp->hw_rx_port_stats +
4578 sizeof(struct rx_port_stats));
4579 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4580 sizeof(struct rx_port_stats);
4581 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4583 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4584 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4585 bp->hw_tx_port_stats_ext = (void *)
4586 ((uint8_t *)bp->hw_tx_port_stats +
4587 sizeof(struct tx_port_stats));
4588 bp->hw_tx_port_stats_ext_map =
4589 bp->hw_tx_port_stats_map +
4590 sizeof(struct tx_port_stats);
4591 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4597 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4599 struct bnxt *bp = eth_dev->data->dev_private;
4602 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4603 RTE_ETHER_ADDR_LEN *
4606 if (eth_dev->data->mac_addrs == NULL) {
4607 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4611 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4615 /* Generate a random MAC address, if none was assigned by PF */
4616 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4617 bnxt_eth_hw_addr_random(bp->mac_addr);
4619 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4620 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4621 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4623 rc = bnxt_hwrm_set_mac(bp);
4625 memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4626 RTE_ETHER_ADDR_LEN);
4630 /* Copy the permanent MAC from the FUNC_QCAPS response */
4631 memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4632 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4637 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4641 /* MAC is already configured in FW */
4642 if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4645 /* Restore the old MAC configured */
4646 rc = bnxt_hwrm_set_mac(bp);
4648 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4653 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4658 #define ALLOW_FUNC(x) \
4660 uint32_t arg = (x); \
4661 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4662 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4665 /* Forward all requests if firmware is new enough */
4666 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4667 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4668 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4669 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4671 PMD_DRV_LOG(WARNING,
4672 "Firmware too old for VF mailbox functionality\n");
4673 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4677 * The following are used for driver cleanup. If we disallow these,
4678 * VF drivers can't clean up cleanly.
4680 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4681 ALLOW_FUNC(HWRM_VNIC_FREE);
4682 ALLOW_FUNC(HWRM_RING_FREE);
4683 ALLOW_FUNC(HWRM_RING_GRP_FREE);
4684 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4685 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4686 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4687 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4688 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4691 static int bnxt_init_fw(struct bnxt *bp)
4698 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
4702 rc = bnxt_hwrm_func_reset(bp);
4706 rc = bnxt_hwrm_vnic_qcaps(bp);
4710 rc = bnxt_hwrm_queue_qportcfg(bp);
4714 /* Get the MAX capabilities for this function.
4715 * This function also allocates context memory for TQM rings and
4716 * informs the firmware about this allocated backing store memory.
4718 rc = bnxt_hwrm_func_qcaps(bp);
4722 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4726 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4730 /* Get the adapter error recovery support info */
4731 rc = bnxt_hwrm_error_recovery_qcfg(bp);
4733 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4735 bnxt_hwrm_port_led_qcaps(bp);
4741 bnxt_init_locks(struct bnxt *bp)
4745 err = pthread_mutex_init(&bp->flow_lock, NULL);
4747 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4751 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4753 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4757 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4761 rc = bnxt_init_fw(bp);
4765 if (!reconfig_dev) {
4766 rc = bnxt_setup_mac_addr(bp->eth_dev);
4770 rc = bnxt_restore_dflt_mac(bp);
4775 bnxt_config_vf_req_fwd(bp);
4777 rc = bnxt_hwrm_func_driver_register(bp);
4779 PMD_DRV_LOG(ERR, "Failed to register driver");
4784 if (bp->pdev->max_vfs) {
4785 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4787 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4791 rc = bnxt_hwrm_allocate_pf_only(bp);
4794 "Failed to allocate PF resources");
4800 rc = bnxt_alloc_mem(bp, reconfig_dev);
4804 rc = bnxt_setup_int(bp);
4808 rc = bnxt_request_int(bp);
4812 rc = bnxt_init_locks(bp);
4820 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4822 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4823 static int version_printed;
4827 if (version_printed++ == 0)
4828 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4830 eth_dev->dev_ops = &bnxt_dev_ops;
4831 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4832 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4835 * For secondary processes, we don't initialise any further
4836 * as primary has already done this work.
4838 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4841 rte_eth_copy_pci_info(eth_dev, pci_dev);
4843 bp = eth_dev->data->dev_private;
4845 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
4847 if (bnxt_vf_pciid(pci_dev->id.device_id))
4848 bp->flags |= BNXT_FLAG_VF;
4850 if (bnxt_thor_device(pci_dev->id.device_id))
4851 bp->flags |= BNXT_FLAG_THOR_CHIP;
4853 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4854 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4855 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4856 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4857 bp->flags |= BNXT_FLAG_STINGRAY;
4859 rc = bnxt_init_board(eth_dev);
4862 "Failed to initialize board rc: %x\n", rc);
4866 rc = bnxt_alloc_hwrm_resources(bp);
4869 "Failed to allocate hwrm resource rc: %x\n", rc);
4872 rc = bnxt_init_resources(bp, false);
4876 rc = bnxt_alloc_stats_mem(bp);
4880 /* Pass the information to the rte_eth_dev_close() that it should also
4881 * release the private port resources.
4883 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
4886 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4887 pci_dev->mem_resource[0].phys_addr,
4888 pci_dev->mem_resource[0].addr);
4893 bnxt_dev_uninit(eth_dev);
4898 bnxt_uninit_locks(struct bnxt *bp)
4900 pthread_mutex_destroy(&bp->flow_lock);
4901 pthread_mutex_destroy(&bp->def_cp_lock);
4905 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4910 bnxt_free_mem(bp, reconfig_dev);
4911 bnxt_hwrm_func_buf_unrgtr(bp);
4912 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4913 bp->flags &= ~BNXT_FLAG_REGISTERED;
4914 bnxt_free_ctx_mem(bp);
4915 if (!reconfig_dev) {
4916 bnxt_free_hwrm_resources(bp);
4918 if (bp->recovery_info != NULL) {
4919 rte_free(bp->recovery_info);
4920 bp->recovery_info = NULL;
4924 bnxt_uninit_locks(bp);
4925 rte_free(bp->ptp_cfg);
4931 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4933 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4936 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4938 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
4939 bnxt_dev_close_op(eth_dev);
4944 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4945 struct rte_pci_device *pci_dev)
4947 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4951 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4953 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4954 return rte_eth_dev_pci_generic_remove(pci_dev,
4957 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4960 static struct rte_pci_driver bnxt_rte_pmd = {
4961 .id_table = bnxt_pci_id_map,
4962 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4963 .probe = bnxt_pci_probe,
4964 .remove = bnxt_pci_remove,
4968 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4970 if (strcmp(dev->device->driver->name, drv->driver.name))
4976 bool is_bnxt_supported(struct rte_eth_dev *dev)
4978 return is_device_supported(dev, &bnxt_rte_pmd);
4981 RTE_INIT(bnxt_init_log)
4983 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4984 if (bnxt_logtype_driver >= 0)
4985 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4988 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4989 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4990 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");