drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16
  17 #include "bnxt.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_reps.h"
  22 #include "bnxt_ring.h"
  23 #include "bnxt_rxq.h"
  24 #include "bnxt_rxr.h"
  25 #include "bnxt_stats.h"
  26 #include "bnxt_txq.h"
  27 #include "bnxt_txr.h"
  28 #include "bnxt_vnic.h"
  29 #include "hsi_struct_def_dpdk.h"
  30 #include "bnxt_nvm_defs.h"
  31 #include "bnxt_tf_common.h"
  32 #include "ulp_flow_db.h"
  33
  34 #define DRV_MODULE_NAME         "bnxt"
  35 static const char bnxt_version[] =
  36         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  37
  38 /*
  39  * The set of PCI devices this driver supports
  40  */
  41 static const struct rte_pci_id bnxt_pci_id_map[] = {
  42         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  43                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  95         { .vendor_id = 0, /* sentinel */ },
  96 };
  97
  98 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
  99 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
 100 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
 101 #define BNXT_DEVARG_REPRESENTOR "representor"
 102 #define BNXT_DEVARG_REP_BASED_PF  "rep-based-pf"
 103 #define BNXT_DEVARG_REP_IS_PF  "rep-is-pf"
 104 #define BNXT_DEVARG_REP_Q_R2F  "rep-q-r2f"
 105 #define BNXT_DEVARG_REP_Q_F2R  "rep-q-f2r"
 106 #define BNXT_DEVARG_REP_FC_R2F  "rep-fc-r2f"
 107 #define BNXT_DEVARG_REP_FC_F2R  "rep-fc-f2r"
 108
 109 static const char *const bnxt_dev_args[] = {
 110         BNXT_DEVARG_REPRESENTOR,
 111         BNXT_DEVARG_TRUFLOW,
 112         BNXT_DEVARG_FLOW_XSTAT,
 113         BNXT_DEVARG_MAX_NUM_KFLOWS,
 114         BNXT_DEVARG_REP_BASED_PF,
 115         BNXT_DEVARG_REP_IS_PF,
 116         BNXT_DEVARG_REP_Q_R2F,
 117         BNXT_DEVARG_REP_Q_F2R,
 118         BNXT_DEVARG_REP_FC_R2F,
 119         BNXT_DEVARG_REP_FC_F2R,
 120         NULL
 121 };
 122
 123 /*
 124  * truflow == false to disable the feature
 125  * truflow == true to enable the feature
 126  */
 127 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 128
 129 /*
 130  * flow_xstat == false to disable the feature
 131  * flow_xstat == true to enable the feature
 132  */
 133 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 134
 135 /*
 136  * rep_is_pf == false to indicate VF representor
 137  * rep_is_pf == true to indicate PF representor
 138  */
 139 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)        ((rep_is_pf) > 1)
 140
 141 /*
 142  * rep_based_pf == Physical index of the PF
 143  */
 144 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)  ((rep_based_pf) > 15)
 145 /*
 146  * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
 147  */
 148 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)        ((rep_q_r2f) > 3)
 149
 150 /*
 151  * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
 152  */
 153 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)        ((rep_q_f2r) > 3)
 154
 155 /*
 156  * rep_fc_r2f == Flow control for the representor to endpoint direction
 157  */
 158 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)      ((rep_fc_r2f) > 1)
 159
 160 /*
 161  * rep_fc_f2r == Flow control for the endpoint to representor direction
 162  */
 163 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)      ((rep_fc_f2r) > 1)
 164
 165 /*
 166  * max_num_kflows must be >= 32
 167  * and must be a power-of-2 supported value
 168  * return: 1 -> invalid
 169  *         0 -> valid
 170  */
 171 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 172 {
 173         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 174                 return 1;
 175         return 0;
 176 }
 177
 178 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 179 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 180 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 181 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 182 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 183 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 184 static void bnxt_dev_recover(void *arg);
 185 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 186 static void bnxt_free_rep_info(struct bnxt *bp);
 187
 188 int is_bnxt_in_error(struct bnxt *bp)
 189 {
 190         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 191                 return -EIO;
 192         if (bp->flags & BNXT_FLAG_FW_RESET)
 193                 return -EBUSY;
 194
 195         return 0;
 196 }
 197
 198 /***********************/
 199
 200 /*
 201  * High level utility functions
 202  */
 203
 204 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 205 {
 206         if (!BNXT_CHIP_THOR(bp))
 207                 return 1;
 208
 209         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 210                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 211                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 212 }
 213
 214 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 215 {
 216         if (!BNXT_CHIP_THOR(bp))
 217                 return HW_HASH_INDEX_SIZE;
 218
 219         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 220 }
 221
 222 static void bnxt_free_parent_info(struct bnxt *bp)
 223 {
 224         rte_free(bp->parent);
 225 }
 226
 227 static void bnxt_free_pf_info(struct bnxt *bp)
 228 {
 229         rte_free(bp->pf);
 230 }
 231
 232 static void bnxt_free_link_info(struct bnxt *bp)
 233 {
 234         rte_free(bp->link_info);
 235 }
 236
 237 static void bnxt_free_leds_info(struct bnxt *bp)
 238 {
 239         if (BNXT_VF(bp))
 240                 return;
 241
 242         rte_free(bp->leds);
 243         bp->leds = NULL;
 244 }
 245
 246 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 247 {
 248         rte_free(bp->flow_stat);
 249         bp->flow_stat = NULL;
 250 }
 251
 252 static void bnxt_free_cos_queues(struct bnxt *bp)
 253 {
 254         rte_free(bp->rx_cos_queue);
 255         rte_free(bp->tx_cos_queue);
 256 }
 257
 258 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 259 {
 260         bnxt_free_filter_mem(bp);
 261         bnxt_free_vnic_attributes(bp);
 262         bnxt_free_vnic_mem(bp);
 263
 264         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 265          * If the number of rings change across fw update,
 266          * we don't have much choice except to warn the user.
 267          */
 268         if (!reconfig) {
 269                 bnxt_free_stats(bp);
 270                 bnxt_free_tx_rings(bp);
 271                 bnxt_free_rx_rings(bp);
 272         }
 273         bnxt_free_async_cp_ring(bp);
 274         bnxt_free_rxtx_nq_ring(bp);
 275
 276         rte_free(bp->grp_info);
 277         bp->grp_info = NULL;
 278 }
 279
 280 static int bnxt_alloc_parent_info(struct bnxt *bp)
 281 {
 282         bp->parent = rte_zmalloc("bnxt_parent_info",
 283                                  sizeof(struct bnxt_parent_info), 0);
 284         if (bp->parent == NULL)
 285                 return -ENOMEM;
 286
 287         return 0;
 288 }
 289
 290 static int bnxt_alloc_pf_info(struct bnxt *bp)
 291 {
 292         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 293         if (bp->pf == NULL)
 294                 return -ENOMEM;
 295
 296         return 0;
 297 }
 298
 299 static int bnxt_alloc_link_info(struct bnxt *bp)
 300 {
 301         bp->link_info =
 302                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 303         if (bp->link_info == NULL)
 304                 return -ENOMEM;
 305
 306         return 0;
 307 }
 308
 309 static int bnxt_alloc_leds_info(struct bnxt *bp)
 310 {
 311         if (BNXT_VF(bp))
 312                 return 0;
 313
 314         bp->leds = rte_zmalloc("bnxt_leds",
 315                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 316                                0);
 317         if (bp->leds == NULL)
 318                 return -ENOMEM;
 319
 320         return 0;
 321 }
 322
 323 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 324 {
 325         bp->rx_cos_queue =
 326                 rte_zmalloc("bnxt_rx_cosq",
 327                             BNXT_COS_QUEUE_COUNT *
 328                             sizeof(struct bnxt_cos_queue_info),
 329                             0);
 330         if (bp->rx_cos_queue == NULL)
 331                 return -ENOMEM;
 332
 333         bp->tx_cos_queue =
 334                 rte_zmalloc("bnxt_tx_cosq",
 335                             BNXT_COS_QUEUE_COUNT *
 336                             sizeof(struct bnxt_cos_queue_info),
 337                             0);
 338         if (bp->tx_cos_queue == NULL)
 339                 return -ENOMEM;
 340
 341         return 0;
 342 }
 343
 344 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 345 {
 346         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 347                                     sizeof(struct bnxt_flow_stat_info), 0);
 348         if (bp->flow_stat == NULL)
 349                 return -ENOMEM;
 350
 351         return 0;
 352 }
 353
 354 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 355 {
 356         int rc;
 357
 358         rc = bnxt_alloc_ring_grps(bp);
 359         if (rc)
 360                 goto alloc_mem_err;
 361
 362         rc = bnxt_alloc_async_ring_struct(bp);
 363         if (rc)
 364                 goto alloc_mem_err;
 365
 366         rc = bnxt_alloc_vnic_mem(bp);
 367         if (rc)
 368                 goto alloc_mem_err;
 369
 370         rc = bnxt_alloc_vnic_attributes(bp);
 371         if (rc)
 372                 goto alloc_mem_err;
 373
 374         rc = bnxt_alloc_filter_mem(bp);
 375         if (rc)
 376                 goto alloc_mem_err;
 377
 378         rc = bnxt_alloc_async_cp_ring(bp);
 379         if (rc)
 380                 goto alloc_mem_err;
 381
 382         rc = bnxt_alloc_rxtx_nq_ring(bp);
 383         if (rc)
 384                 goto alloc_mem_err;
 385
 386         if (BNXT_FLOW_XSTATS_EN(bp)) {
 387                 rc = bnxt_alloc_flow_stats_info(bp);
 388                 if (rc)
 389                         goto alloc_mem_err;
 390         }
 391
 392         return 0;
 393
 394 alloc_mem_err:
 395         bnxt_free_mem(bp, reconfig);
 396         return rc;
 397 }
 398
 399 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 400 {
 401         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 402         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 403         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 404         struct bnxt_rx_queue *rxq;
 405         unsigned int j;
 406         int rc;
 407
 408         rc = bnxt_vnic_grp_alloc(bp, vnic);
 409         if (rc)
 410                 goto err_out;
 411
 412         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 413                     vnic_id, vnic, vnic->fw_grp_ids);
 414
 415         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 416         if (rc)
 417                 goto err_out;
 418
 419         /* Alloc RSS context only if RSS mode is enabled */
 420         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 421                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 422
 423                 rc = 0;
 424                 for (j = 0; j < nr_ctxs; j++) {
 425                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 426                         if (rc)
 427                                 break;
 428                 }
 429                 if (rc) {
 430                         PMD_DRV_LOG(ERR,
 431                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 432                                     vnic_id, j, rc);
 433                         goto err_out;
 434                 }
 435                 vnic->num_lb_ctxts = nr_ctxs;
 436         }
 437
 438         /*
 439          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 440          * setting is not available at this time, it will not be
 441          * configured correctly in the CFA.
 442          */
 443         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 444                 vnic->vlan_strip = true;
 445         else
 446                 vnic->vlan_strip = false;
 447
 448         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 449         if (rc)
 450                 goto err_out;
 451
 452         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 453         if (rc)
 454                 goto err_out;
 455
 456         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 457                 rxq = bp->eth_dev->data->rx_queues[j];
 458
 459                 PMD_DRV_LOG(DEBUG,
 460                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 461                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 462
 463                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 464                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 465                 else
 466                         vnic->rx_queue_cnt++;
 467         }
 468
 469         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 470
 471         rc = bnxt_vnic_rss_configure(bp, vnic);
 472         if (rc)
 473                 goto err_out;
 474
 475         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 476
 477         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 478                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 479         else
 480                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 481
 482         return 0;
 483 err_out:
 484         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 485                     vnic_id, rc);
 486         return rc;
 487 }
 488
 489 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 490 {
 491         int rc = 0;
 492
 493         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 494                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 495         if (rc)
 496                 return rc;
 497
 498         PMD_DRV_LOG(DEBUG,
 499                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 500                     " rx_fc_in_tbl.ctx_id = %d\n",
 501                     bp->flow_stat->rx_fc_in_tbl.va,
 502                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 503                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 504
 505         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 506                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 507         if (rc)
 508                 return rc;
 509
 510         PMD_DRV_LOG(DEBUG,
 511                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 512                     " rx_fc_out_tbl.ctx_id = %d\n",
 513                     bp->flow_stat->rx_fc_out_tbl.va,
 514                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 515                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 516
 517         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 518                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 519         if (rc)
 520                 return rc;
 521
 522         PMD_DRV_LOG(DEBUG,
 523                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 524                     " tx_fc_in_tbl.ctx_id = %d\n",
 525                     bp->flow_stat->tx_fc_in_tbl.va,
 526                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 527                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 528
 529         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 530                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 531         if (rc)
 532                 return rc;
 533
 534         PMD_DRV_LOG(DEBUG,
 535                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 536                     " tx_fc_out_tbl.ctx_id = %d\n",
 537                     bp->flow_stat->tx_fc_out_tbl.va,
 538                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 539                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 540
 541         memset(bp->flow_stat->rx_fc_out_tbl.va,
 542                0,
 543                bp->flow_stat->rx_fc_out_tbl.size);
 544         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 545                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 546                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 547                                        bp->flow_stat->max_fc,
 548                                        true);
 549         if (rc)
 550                 return rc;
 551
 552         memset(bp->flow_stat->tx_fc_out_tbl.va,
 553                0,
 554                bp->flow_stat->tx_fc_out_tbl.size);
 555         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 556                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 557                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 558                                        bp->flow_stat->max_fc,
 559                                        true);
 560
 561         return rc;
 562 }
 563
 564 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 565                                   struct bnxt_ctx_mem_buf_info *ctx)
 566 {
 567         if (!ctx)
 568                 return -EINVAL;
 569
 570         ctx->va = rte_zmalloc(type, size, 0);
 571         if (ctx->va == NULL)
 572                 return -ENOMEM;
 573         rte_mem_lock_page(ctx->va);
 574         ctx->size = size;
 575         ctx->dma = rte_mem_virt2iova(ctx->va);
 576         if (ctx->dma == RTE_BAD_IOVA)
 577                 return -ENOMEM;
 578
 579         return 0;
 580 }
 581
 582 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 583 {
 584         struct rte_pci_device *pdev = bp->pdev;
 585         char type[RTE_MEMZONE_NAMESIZE];
 586         uint16_t max_fc;
 587         int rc = 0;
 588
 589         max_fc = bp->flow_stat->max_fc;
 590
 591         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 592                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 593         /* 4 bytes for each counter-id */
 594         rc = bnxt_alloc_ctx_mem_buf(type,
 595                                     max_fc * 4,
 596                                     &bp->flow_stat->rx_fc_in_tbl);
 597         if (rc)
 598                 return rc;
 599
 600         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 601                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 602         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 603         rc = bnxt_alloc_ctx_mem_buf(type,
 604                                     max_fc * 16,
 605                                     &bp->flow_stat->rx_fc_out_tbl);
 606         if (rc)
 607                 return rc;
 608
 609         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 610                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 611         /* 4 bytes for each counter-id */
 612         rc = bnxt_alloc_ctx_mem_buf(type,
 613                                     max_fc * 4,
 614                                     &bp->flow_stat->tx_fc_in_tbl);
 615         if (rc)
 616                 return rc;
 617
 618         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 619                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 620         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 621         rc = bnxt_alloc_ctx_mem_buf(type,
 622                                     max_fc * 16,
 623                                     &bp->flow_stat->tx_fc_out_tbl);
 624         if (rc)
 625                 return rc;
 626
 627         rc = bnxt_register_fc_ctx_mem(bp);
 628
 629         return rc;
 630 }
 631
 632 static int bnxt_init_ctx_mem(struct bnxt *bp)
 633 {
 634         int rc = 0;
 635
 636         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 637             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 638             !BNXT_FLOW_XSTATS_EN(bp))
 639                 return 0;
 640
 641         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 642         if (rc)
 643                 return rc;
 644
 645         rc = bnxt_init_fc_ctx_mem(bp);
 646
 647         return rc;
 648 }
 649
 650 static int bnxt_update_phy_setting(struct bnxt *bp)
 651 {
 652         struct rte_eth_link new;
 653         int rc;
 654
 655         rc = bnxt_get_hwrm_link_config(bp, &new);
 656         if (rc) {
 657                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 658                 return rc;
 659         }
 660
 661         /*
 662          * On BCM957508-N2100 adapters, FW will not allow any user other
 663          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 664          * always returns link up. Force phy update always in that case.
 665          */
 666         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 667                 rc = bnxt_set_hwrm_link_config(bp, true);
 668                 if (rc) {
 669                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 670                         return rc;
 671                 }
 672         }
 673
 674         return rc;
 675 }
 676
 677 static int bnxt_init_chip(struct bnxt *bp)
 678 {
 679         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 680         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 681         uint32_t intr_vector = 0;
 682         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 683         uint32_t vec = BNXT_MISC_VEC_ID;
 684         unsigned int i, j;
 685         int rc;
 686
 687         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 688                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 689                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 690                 bp->flags |= BNXT_FLAG_JUMBO;
 691         } else {
 692                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 693                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 694                 bp->flags &= ~BNXT_FLAG_JUMBO;
 695         }
 696
 697         /* THOR does not support ring groups.
 698          * But we will use the array to save RSS context IDs.
 699          */
 700         if (BNXT_CHIP_THOR(bp))
 701                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 702
 703         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 704         if (rc) {
 705                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 706                 goto err_out;
 707         }
 708
 709         rc = bnxt_alloc_hwrm_rings(bp);
 710         if (rc) {
 711                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 712                 goto err_out;
 713         }
 714
 715         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 716         if (rc) {
 717                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 718                 goto err_out;
 719         }
 720
 721         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 722                 goto skip_cosq_cfg;
 723
 724         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 725                 if (bp->rx_cos_queue[i].id != 0xff) {
 726                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 727
 728                         if (!vnic) {
 729                                 PMD_DRV_LOG(ERR,
 730                                             "Num pools more than FW profile\n");
 731                                 rc = -EINVAL;
 732                                 goto err_out;
 733                         }
 734                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 735                         bp->rx_cosq_cnt++;
 736                 }
 737         }
 738
 739 skip_cosq_cfg:
 740         rc = bnxt_mq_rx_configure(bp);
 741         if (rc) {
 742                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 743                 goto err_out;
 744         }
 745
 746         /* VNIC configuration */
 747         for (i = 0; i < bp->nr_vnics; i++) {
 748                 rc = bnxt_setup_one_vnic(bp, i);
 749                 if (rc)
 750                         goto err_out;
 751         }
 752
 753         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 754         if (rc) {
 755                 PMD_DRV_LOG(ERR,
 756                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 757                 goto err_out;
 758         }
 759
 760         /* check and configure queue intr-vector mapping */
 761         if ((rte_intr_cap_multiple(intr_handle) ||
 762              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 763             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 764                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 765                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 766                 if (intr_vector > bp->rx_cp_nr_rings) {
 767                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 768                                         bp->rx_cp_nr_rings);
 769                         return -ENOTSUP;
 770                 }
 771                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 772                 if (rc)
 773                         return rc;
 774         }
 775
 776         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 777                 intr_handle->intr_vec =
 778                         rte_zmalloc("intr_vec",
 779                                     bp->eth_dev->data->nb_rx_queues *
 780                                     sizeof(int), 0);
 781                 if (intr_handle->intr_vec == NULL) {
 782                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 783                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 784                         rc = -ENOMEM;
 785                         goto err_disable;
 786                 }
 787                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 788                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 789                          intr_handle->intr_vec, intr_handle->nb_efd,
 790                         intr_handle->max_intr);
 791                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 792                      queue_id++) {
 793                         intr_handle->intr_vec[queue_id] =
 794                                                         vec + BNXT_RX_VEC_START;
 795                         if (vec < base + intr_handle->nb_efd - 1)
 796                                 vec++;
 797                 }
 798         }
 799
 800         /* enable uio/vfio intr/eventfd mapping */
 801         rc = rte_intr_enable(intr_handle);
 802 #ifndef RTE_EXEC_ENV_FREEBSD
 803         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 804         if (rc)
 805                 goto err_free;
 806 #endif
 807
 808         rc = bnxt_update_phy_setting(bp);
 809         if (rc)
 810                 goto err_free;
 811
 812         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 813         if (!bp->mark_table)
 814                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 815
 816         return 0;
 817
 818 err_free:
 819         rte_free(intr_handle->intr_vec);
 820 err_disable:
 821         rte_intr_efd_disable(intr_handle);
 822 err_out:
 823         /* Some of the error status returned by FW may not be from errno.h */
 824         if (rc > 0)
 825                 rc = -EIO;
 826
 827         return rc;
 828 }
 829
 830 static int bnxt_shutdown_nic(struct bnxt *bp)
 831 {
 832         bnxt_free_all_hwrm_resources(bp);
 833         bnxt_free_all_filters(bp);
 834         bnxt_free_all_vnics(bp);
 835         return 0;
 836 }
 837
 838 /*
 839  * Device configuration and status function
 840  */
 841
 842 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 843 {
 844         uint32_t link_speed = bp->link_info->support_speeds;
 845         uint32_t speed_capa = 0;
 846
 847         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 848                 speed_capa |= ETH_LINK_SPEED_100M;
 849         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 850                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 851         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 852                 speed_capa |= ETH_LINK_SPEED_1G;
 853         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 854                 speed_capa |= ETH_LINK_SPEED_2_5G;
 855         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 856                 speed_capa |= ETH_LINK_SPEED_10G;
 857         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 858                 speed_capa |= ETH_LINK_SPEED_20G;
 859         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 860                 speed_capa |= ETH_LINK_SPEED_25G;
 861         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 862                 speed_capa |= ETH_LINK_SPEED_40G;
 863         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 864                 speed_capa |= ETH_LINK_SPEED_50G;
 865         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 866                 speed_capa |= ETH_LINK_SPEED_100G;
 867         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
 868                 speed_capa |= ETH_LINK_SPEED_50G;
 869         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
 870                 speed_capa |= ETH_LINK_SPEED_100G;
 871         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
 872                 speed_capa |= ETH_LINK_SPEED_200G;
 873
 874         if (bp->link_info->auto_mode ==
 875             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 876                 speed_capa |= ETH_LINK_SPEED_FIXED;
 877         else
 878                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 879
 880         return speed_capa;
 881 }
 882
 883 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 884                                 struct rte_eth_dev_info *dev_info)
 885 {
 886         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 887         struct bnxt *bp = eth_dev->data->dev_private;
 888         uint16_t max_vnics, i, j, vpool, vrxq;
 889         unsigned int max_rx_rings;
 890         int rc;
 891
 892         rc = is_bnxt_in_error(bp);
 893         if (rc)
 894                 return rc;
 895
 896         /* MAC Specifics */
 897         dev_info->max_mac_addrs = bp->max_l2_ctx;
 898         dev_info->max_hash_mac_addrs = 0;
 899
 900         /* PF/VF specifics */
 901         if (BNXT_PF(bp))
 902                 dev_info->max_vfs = pdev->max_vfs;
 903
 904         max_rx_rings = BNXT_MAX_RINGS(bp);
 905         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 906         dev_info->max_rx_queues = max_rx_rings;
 907         dev_info->max_tx_queues = max_rx_rings;
 908         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 909         dev_info->hash_key_size = 40;
 910         max_vnics = bp->max_vnics;
 911
 912         /* MTU specifics */
 913         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 914         dev_info->max_mtu = BNXT_MAX_MTU;
 915
 916         /* Fast path specifics */
 917         dev_info->min_rx_bufsize = 1;
 918         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 919
 920         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 921         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 922                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 923         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 924         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 925
 926         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 927
 928         /* *INDENT-OFF* */
 929         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 930                 .rx_thresh = {
 931                         .pthresh = 8,
 932                         .hthresh = 8,
 933                         .wthresh = 0,
 934                 },
 935                 .rx_free_thresh = 32,
 936                 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
 937         };
 938
 939         dev_info->default_txconf = (struct rte_eth_txconf) {
 940                 .tx_thresh = {
 941                         .pthresh = 32,
 942                         .hthresh = 0,
 943                         .wthresh = 0,
 944                 },
 945                 .tx_free_thresh = 32,
 946                 .tx_rs_thresh = 32,
 947         };
 948         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 949
 950         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 951         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 952         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 953         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 954         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 955
 956         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
 957                 dev_info->switch_info.name = eth_dev->device->name;
 958                 dev_info->switch_info.domain_id = bp->switch_domain_id;
 959                 dev_info->switch_info.port_id =
 960                                 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
 961                                     BNXT_SWITCH_PORT_ID_TRUSTED_VF;
 962         }
 963
 964         /* *INDENT-ON* */
 965
 966         /*
 967          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 968          *       need further investigation.
 969          */
 970
 971         /* VMDq resources */
 972         vpool = 64; /* ETH_64_POOLS */
 973         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 974         for (i = 0; i < 4; vpool >>= 1, i++) {
 975                 if (max_vnics > vpool) {
 976                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 977                                 if (dev_info->max_rx_queues > vrxq) {
 978                                         if (vpool > vrxq)
 979                                                 vpool = vrxq;
 980                                         goto found;
 981                                 }
 982                         }
 983                         /* Not enough resources to support VMDq */
 984                         break;
 985                 }
 986         }
 987         /* Not enough resources to support VMDq */
 988         vpool = 0;
 989         vrxq = 0;
 990 found:
 991         dev_info->max_vmdq_pools = vpool;
 992         dev_info->vmdq_queue_num = vrxq;
 993
 994         dev_info->vmdq_pool_base = 0;
 995         dev_info->vmdq_queue_base = 0;
 996
 997         return 0;
 998 }
 999
1000 /* Configure the device based on the configuration provided */
1001 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1002 {
1003         struct bnxt *bp = eth_dev->data->dev_private;
1004         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1005         int rc;
1006
1007         bp->rx_queues = (void *)eth_dev->data->rx_queues;
1008         bp->tx_queues = (void *)eth_dev->data->tx_queues;
1009         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1010         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1011
1012         rc = is_bnxt_in_error(bp);
1013         if (rc)
1014                 return rc;
1015
1016         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1017                 rc = bnxt_hwrm_check_vf_rings(bp);
1018                 if (rc) {
1019                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1020                         return -ENOSPC;
1021                 }
1022
1023                 /* If a resource has already been allocated - in this case
1024                  * it is the async completion ring, free it. Reallocate it after
1025                  * resource reservation. This will ensure the resource counts
1026                  * are calculated correctly.
1027                  */
1028
1029                 pthread_mutex_lock(&bp->def_cp_lock);
1030
1031                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1032                         bnxt_disable_int(bp);
1033                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
1034                 }
1035
1036                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1037                 if (rc) {
1038                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1039                         pthread_mutex_unlock(&bp->def_cp_lock);
1040                         return -ENOSPC;
1041                 }
1042
1043                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1044                         rc = bnxt_alloc_async_cp_ring(bp);
1045                         if (rc) {
1046                                 pthread_mutex_unlock(&bp->def_cp_lock);
1047                                 return rc;
1048                         }
1049                         bnxt_enable_int(bp);
1050                 }
1051
1052                 pthread_mutex_unlock(&bp->def_cp_lock);
1053         } else {
1054                 /* legacy driver needs to get updated values */
1055                 rc = bnxt_hwrm_func_qcaps(bp);
1056                 if (rc) {
1057                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
1058                         return rc;
1059                 }
1060         }
1061
1062         /* Inherit new configurations */
1063         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1064             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1065             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1066                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1067             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1068             bp->max_stat_ctx)
1069                 goto resource_error;
1070
1071         if (BNXT_HAS_RING_GRPS(bp) &&
1072             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1073                 goto resource_error;
1074
1075         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1076             bp->max_vnics < eth_dev->data->nb_rx_queues)
1077                 goto resource_error;
1078
1079         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1080         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1081
1082         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1083                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1084         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1085
1086         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1087                 eth_dev->data->mtu =
1088                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1089                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1090                         BNXT_NUM_VLANS;
1091                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1092         }
1093         return 0;
1094
1095 resource_error:
1096         PMD_DRV_LOG(ERR,
1097                     "Insufficient resources to support requested config\n");
1098         PMD_DRV_LOG(ERR,
1099                     "Num Queues Requested: Tx %d, Rx %d\n",
1100                     eth_dev->data->nb_tx_queues,
1101                     eth_dev->data->nb_rx_queues);
1102         PMD_DRV_LOG(ERR,
1103                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1104                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1105                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1106         return -ENOSPC;
1107 }
1108
1109 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1110 {
1111         struct rte_eth_link *link = &eth_dev->data->dev_link;
1112
1113         if (link->link_status)
1114                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1115                         eth_dev->data->port_id,
1116                         (uint32_t)link->link_speed,
1117                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1118                         ("full-duplex") : ("half-duplex\n"));
1119         else
1120                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1121                         eth_dev->data->port_id);
1122 }
1123
1124 /*
1125  * Determine whether the current configuration requires support for scattered
1126  * receive; return 1 if scattered receive is required and 0 if not.
1127  */
1128 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1129 {
1130         uint16_t buf_size;
1131         int i;
1132
1133         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1134                 return 1;
1135
1136         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1137                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1138
1139                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1140                                       RTE_PKTMBUF_HEADROOM);
1141                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1142                         return 1;
1143         }
1144         return 0;
1145 }
1146
1147 static eth_rx_burst_t
1148 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1149 {
1150         struct bnxt *bp = eth_dev->data->dev_private;
1151
1152 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1153 #ifndef RTE_LIBRTE_IEEE1588
1154         /*
1155          * Vector mode receive can be enabled only if scatter rx is not
1156          * in use and rx offloads are limited to VLAN stripping and
1157          * CRC stripping.
1158          */
1159         if (!eth_dev->data->scattered_rx &&
1160             !(eth_dev->data->dev_conf.rxmode.offloads &
1161               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1162                 DEV_RX_OFFLOAD_KEEP_CRC |
1163                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1164                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1165                 DEV_RX_OFFLOAD_UDP_CKSUM |
1166                 DEV_RX_OFFLOAD_TCP_CKSUM |
1167                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1168                 DEV_RX_OFFLOAD_RSS_HASH |
1169                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1170             !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp)) {
1171                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1172                             eth_dev->data->port_id);
1173                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1174                 return bnxt_recv_pkts_vec;
1175         }
1176         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1177                     eth_dev->data->port_id);
1178         PMD_DRV_LOG(INFO,
1179                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1180                     eth_dev->data->port_id,
1181                     eth_dev->data->scattered_rx,
1182                     eth_dev->data->dev_conf.rxmode.offloads);
1183 #endif
1184 #endif
1185         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1186         return bnxt_recv_pkts;
1187 }
1188
1189 static eth_tx_burst_t
1190 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1191 {
1192 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1193 #ifndef RTE_LIBRTE_IEEE1588
1194         struct bnxt *bp = eth_dev->data->dev_private;
1195
1196         /*
1197          * Vector mode transmit can be enabled only if not using scatter rx
1198          * or tx offloads.
1199          */
1200         if (!eth_dev->data->scattered_rx &&
1201             !eth_dev->data->dev_conf.txmode.offloads &&
1202             !BNXT_TRUFLOW_EN(bp)) {
1203                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1204                             eth_dev->data->port_id);
1205                 return bnxt_xmit_pkts_vec;
1206         }
1207         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1208                     eth_dev->data->port_id);
1209         PMD_DRV_LOG(INFO,
1210                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1211                     eth_dev->data->port_id,
1212                     eth_dev->data->scattered_rx,
1213                     eth_dev->data->dev_conf.txmode.offloads);
1214 #endif
1215 #endif
1216         return bnxt_xmit_pkts;
1217 }
1218
1219 static int bnxt_handle_if_change_status(struct bnxt *bp)
1220 {
1221         int rc;
1222
1223         /* Since fw has undergone a reset and lost all contexts,
1224          * set fatal flag to not issue hwrm during cleanup
1225          */
1226         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1227         bnxt_uninit_resources(bp, true);
1228
1229         /* clear fatal flag so that re-init happens */
1230         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1231         rc = bnxt_init_resources(bp, true);
1232
1233         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1234
1235         return rc;
1236 }
1237
1238 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1239 {
1240         struct bnxt *bp = eth_dev->data->dev_private;
1241         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1242         int vlan_mask = 0;
1243         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1244
1245         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1246                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1247                 return -EINVAL;
1248         }
1249
1250         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1251                 PMD_DRV_LOG(ERR,
1252                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1253                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1254         }
1255
1256         do {
1257                 rc = bnxt_hwrm_if_change(bp, true);
1258                 if (rc == 0 || rc != -EAGAIN)
1259                         break;
1260
1261                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1262         } while (retry_cnt--);
1263
1264         if (rc)
1265                 return rc;
1266
1267         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1268                 rc = bnxt_handle_if_change_status(bp);
1269                 if (rc)
1270                         return rc;
1271         }
1272
1273         bnxt_enable_int(bp);
1274
1275         rc = bnxt_init_chip(bp);
1276         if (rc)
1277                 goto error;
1278
1279         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1280         eth_dev->data->dev_started = 1;
1281
1282         bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1283
1284         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1285                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1286         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1287                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1288         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1289         if (rc)
1290                 goto error;
1291
1292         /* Initialize bnxt ULP port details */
1293         rc = bnxt_ulp_port_init(bp);
1294         if (rc)
1295                 goto error;
1296
1297         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1298         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1299
1300         bnxt_schedule_fw_health_check(bp);
1301
1302         return 0;
1303
1304 error:
1305         bnxt_shutdown_nic(bp);
1306         bnxt_free_tx_mbufs(bp);
1307         bnxt_free_rx_mbufs(bp);
1308         bnxt_hwrm_if_change(bp, false);
1309         eth_dev->data->dev_started = 0;
1310         return rc;
1311 }
1312
1313 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1314 {
1315         struct bnxt *bp = eth_dev->data->dev_private;
1316         int rc = 0;
1317
1318         if (!bp->link_info->link_up)
1319                 rc = bnxt_set_hwrm_link_config(bp, true);
1320         if (!rc)
1321                 eth_dev->data->dev_link.link_status = 1;
1322
1323         bnxt_print_link_info(eth_dev);
1324         return rc;
1325 }
1326
1327 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1328 {
1329         struct bnxt *bp = eth_dev->data->dev_private;
1330
1331         eth_dev->data->dev_link.link_status = 0;
1332         bnxt_set_hwrm_link_config(bp, false);
1333         bp->link_info->link_up = 0;
1334
1335         return 0;
1336 }
1337
1338 static void bnxt_free_switch_domain(struct bnxt *bp)
1339 {
1340         if (bp->switch_domain_id)
1341                 rte_eth_switch_domain_free(bp->switch_domain_id);
1342 }
1343
1344 /* Unload the driver, release resources */
1345 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1346 {
1347         struct bnxt *bp = eth_dev->data->dev_private;
1348         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1349         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1350
1351         eth_dev->data->dev_started = 0;
1352         eth_dev->data->scattered_rx = 0;
1353
1354         /* Prevent crashes when queues are still in use */
1355         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1356         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1357
1358         bnxt_disable_int(bp);
1359
1360         /* disable uio/vfio intr/eventfd mapping */
1361         rte_intr_disable(intr_handle);
1362
1363         /* Stop the child representors for this device */
1364         bnxt_rep_stop_all(bp);
1365
1366         /* delete the bnxt ULP port details */
1367         bnxt_ulp_port_deinit(bp);
1368
1369         bnxt_cancel_fw_health_check(bp);
1370
1371         /* Do not bring link down during reset recovery */
1372         if (!is_bnxt_in_error(bp))
1373                 bnxt_dev_set_link_down_op(eth_dev);
1374
1375         /* Wait for link to be reset and the async notification to process.
1376          * During reset recovery, there is no need to wait and
1377          * VF/NPAR functions do not have privilege to change PHY config.
1378          */
1379         if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1380                 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1381
1382         /* Clean queue intr-vector mapping */
1383         rte_intr_efd_disable(intr_handle);
1384         if (intr_handle->intr_vec != NULL) {
1385                 rte_free(intr_handle->intr_vec);
1386                 intr_handle->intr_vec = NULL;
1387         }
1388
1389         bnxt_hwrm_port_clr_stats(bp);
1390         bnxt_free_tx_mbufs(bp);
1391         bnxt_free_rx_mbufs(bp);
1392         /* Process any remaining notifications in default completion queue */
1393         bnxt_int_handler(eth_dev);
1394         bnxt_shutdown_nic(bp);
1395         bnxt_hwrm_if_change(bp, false);
1396
1397         rte_free(bp->mark_table);
1398         bp->mark_table = NULL;
1399
1400         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1401         bp->rx_cosq_cnt = 0;
1402         /* All filters are deleted on a port stop. */
1403         if (BNXT_FLOW_XSTATS_EN(bp))
1404                 bp->flow_stat->flow_count = 0;
1405 }
1406
1407 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1408 {
1409         struct bnxt *bp = eth_dev->data->dev_private;
1410
1411         /* cancel the recovery handler before remove dev */
1412         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1413         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1414         bnxt_cancel_fc_thread(bp);
1415
1416         if (eth_dev->data->dev_started)
1417                 bnxt_dev_stop_op(eth_dev);
1418
1419         bnxt_free_switch_domain(bp);
1420
1421         bnxt_uninit_resources(bp, false);
1422
1423         bnxt_free_leds_info(bp);
1424         bnxt_free_cos_queues(bp);
1425         bnxt_free_link_info(bp);
1426         bnxt_free_pf_info(bp);
1427         bnxt_free_parent_info(bp);
1428
1429         eth_dev->dev_ops = NULL;
1430         eth_dev->rx_pkt_burst = NULL;
1431         eth_dev->tx_pkt_burst = NULL;
1432
1433         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1434         bp->tx_mem_zone = NULL;
1435         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1436         bp->rx_mem_zone = NULL;
1437
1438         bnxt_hwrm_free_vf_info(bp);
1439
1440         rte_free(bp->grp_info);
1441         bp->grp_info = NULL;
1442 }
1443
1444 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1445                                     uint32_t index)
1446 {
1447         struct bnxt *bp = eth_dev->data->dev_private;
1448         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1449         struct bnxt_vnic_info *vnic;
1450         struct bnxt_filter_info *filter, *temp_filter;
1451         uint32_t i;
1452
1453         if (is_bnxt_in_error(bp))
1454                 return;
1455
1456         /*
1457          * Loop through all VNICs from the specified filter flow pools to
1458          * remove the corresponding MAC addr filter
1459          */
1460         for (i = 0; i < bp->nr_vnics; i++) {
1461                 if (!(pool_mask & (1ULL << i)))
1462                         continue;
1463
1464                 vnic = &bp->vnic_info[i];
1465                 filter = STAILQ_FIRST(&vnic->filter);
1466                 while (filter) {
1467                         temp_filter = STAILQ_NEXT(filter, next);
1468                         if (filter->mac_index == index) {
1469                                 STAILQ_REMOVE(&vnic->filter, filter,
1470                                                 bnxt_filter_info, next);
1471                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1472                                 bnxt_free_filter(bp, filter);
1473                         }
1474                         filter = temp_filter;
1475                 }
1476         }
1477 }
1478
1479 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1480                                struct rte_ether_addr *mac_addr, uint32_t index,
1481                                uint32_t pool)
1482 {
1483         struct bnxt_filter_info *filter;
1484         int rc = 0;
1485
1486         /* Attach requested MAC address to the new l2_filter */
1487         STAILQ_FOREACH(filter, &vnic->filter, next) {
1488                 if (filter->mac_index == index) {
1489                         PMD_DRV_LOG(DEBUG,
1490                                     "MAC addr already existed for pool %d\n",
1491                                     pool);
1492                         return 0;
1493                 }
1494         }
1495
1496         filter = bnxt_alloc_filter(bp);
1497         if (!filter) {
1498                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1499                 return -ENODEV;
1500         }
1501
1502         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1503          * if the MAC that's been programmed now is a different one, then,
1504          * copy that addr to filter->l2_addr
1505          */
1506         if (mac_addr)
1507                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1508         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1509
1510         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1511         if (!rc) {
1512                 filter->mac_index = index;
1513                 if (filter->mac_index == 0)
1514                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1515                 else
1516                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1517         } else {
1518                 bnxt_free_filter(bp, filter);
1519         }
1520
1521         return rc;
1522 }
1523
1524 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1525                                 struct rte_ether_addr *mac_addr,
1526                                 uint32_t index, uint32_t pool)
1527 {
1528         struct bnxt *bp = eth_dev->data->dev_private;
1529         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1530         int rc = 0;
1531
1532         rc = is_bnxt_in_error(bp);
1533         if (rc)
1534                 return rc;
1535
1536         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1537                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1538                 return -ENOTSUP;
1539         }
1540
1541         if (!vnic) {
1542                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1543                 return -EINVAL;
1544         }
1545
1546         /* Filter settings will get applied when port is started */
1547         if (!eth_dev->data->dev_started)
1548                 return 0;
1549
1550         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1551
1552         return rc;
1553 }
1554
1555 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1556                      bool exp_link_status)
1557 {
1558         int rc = 0;
1559         struct bnxt *bp = eth_dev->data->dev_private;
1560         struct rte_eth_link new;
1561         int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1562                   BNXT_LINK_DOWN_WAIT_CNT;
1563
1564         rc = is_bnxt_in_error(bp);
1565         if (rc)
1566                 return rc;
1567
1568         memset(&new, 0, sizeof(new));
1569         do {
1570                 /* Retrieve link info from hardware */
1571                 rc = bnxt_get_hwrm_link_config(bp, &new);
1572                 if (rc) {
1573                         new.link_speed = ETH_LINK_SPEED_100M;
1574                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1575                         PMD_DRV_LOG(ERR,
1576                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1577                         goto out;
1578                 }
1579
1580                 if (!wait_to_complete || new.link_status == exp_link_status)
1581                         break;
1582
1583                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1584         } while (cnt--);
1585
1586 out:
1587         /* Timed out or success */
1588         if (new.link_status != eth_dev->data->dev_link.link_status ||
1589         new.link_speed != eth_dev->data->dev_link.link_speed) {
1590                 rte_eth_linkstatus_set(eth_dev, &new);
1591
1592                 rte_eth_dev_callback_process(eth_dev,
1593                                              RTE_ETH_EVENT_INTR_LSC,
1594                                              NULL);
1595
1596                 bnxt_print_link_info(eth_dev);
1597         }
1598
1599         return rc;
1600 }
1601
1602 int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1603                         int wait_to_complete)
1604 {
1605         return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1606 }
1607
1608 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1609 {
1610         struct bnxt *bp = eth_dev->data->dev_private;
1611         struct bnxt_vnic_info *vnic;
1612         uint32_t old_flags;
1613         int rc;
1614
1615         rc = is_bnxt_in_error(bp);
1616         if (rc)
1617                 return rc;
1618
1619         /* Filter settings will get applied when port is started */
1620         if (!eth_dev->data->dev_started)
1621                 return 0;
1622
1623         if (bp->vnic_info == NULL)
1624                 return 0;
1625
1626         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1627
1628         old_flags = vnic->flags;
1629         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1630         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1631         if (rc != 0)
1632                 vnic->flags = old_flags;
1633
1634         return rc;
1635 }
1636
1637 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1638 {
1639         struct bnxt *bp = eth_dev->data->dev_private;
1640         struct bnxt_vnic_info *vnic;
1641         uint32_t old_flags;
1642         int rc;
1643
1644         rc = is_bnxt_in_error(bp);
1645         if (rc)
1646                 return rc;
1647
1648         /* Filter settings will get applied when port is started */
1649         if (!eth_dev->data->dev_started)
1650                 return 0;
1651
1652         if (bp->vnic_info == NULL)
1653                 return 0;
1654
1655         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1656
1657         old_flags = vnic->flags;
1658         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1659         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1660         if (rc != 0)
1661                 vnic->flags = old_flags;
1662
1663         return rc;
1664 }
1665
1666 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1667 {
1668         struct bnxt *bp = eth_dev->data->dev_private;
1669         struct bnxt_vnic_info *vnic;
1670         uint32_t old_flags;
1671         int rc;
1672
1673         rc = is_bnxt_in_error(bp);
1674         if (rc)
1675                 return rc;
1676
1677         /* Filter settings will get applied when port is started */
1678         if (!eth_dev->data->dev_started)
1679                 return 0;
1680
1681         if (bp->vnic_info == NULL)
1682                 return 0;
1683
1684         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1685
1686         old_flags = vnic->flags;
1687         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1688         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1689         if (rc != 0)
1690                 vnic->flags = old_flags;
1691
1692         return rc;
1693 }
1694
1695 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1696 {
1697         struct bnxt *bp = eth_dev->data->dev_private;
1698         struct bnxt_vnic_info *vnic;
1699         uint32_t old_flags;
1700         int rc;
1701
1702         rc = is_bnxt_in_error(bp);
1703         if (rc)
1704                 return rc;
1705
1706         /* Filter settings will get applied when port is started */
1707         if (!eth_dev->data->dev_started)
1708                 return 0;
1709
1710         if (bp->vnic_info == NULL)
1711                 return 0;
1712
1713         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1714
1715         old_flags = vnic->flags;
1716         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1717         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1718         if (rc != 0)
1719                 vnic->flags = old_flags;
1720
1721         return rc;
1722 }
1723
1724 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1725 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1726 {
1727         if (qid >= bp->rx_nr_rings)
1728                 return NULL;
1729
1730         return bp->eth_dev->data->rx_queues[qid];
1731 }
1732
1733 /* Return rxq corresponding to a given rss table ring/group ID. */
1734 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1735 {
1736         struct bnxt_rx_queue *rxq;
1737         unsigned int i;
1738
1739         if (!BNXT_HAS_RING_GRPS(bp)) {
1740                 for (i = 0; i < bp->rx_nr_rings; i++) {
1741                         rxq = bp->eth_dev->data->rx_queues[i];
1742                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1743                                 return rxq->index;
1744                 }
1745         } else {
1746                 for (i = 0; i < bp->rx_nr_rings; i++) {
1747                         if (bp->grp_info[i].fw_grp_id == fwr)
1748                                 return i;
1749                 }
1750         }
1751
1752         return INVALID_HW_RING_ID;
1753 }
1754
1755 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1756                             struct rte_eth_rss_reta_entry64 *reta_conf,
1757                             uint16_t reta_size)
1758 {
1759         struct bnxt *bp = eth_dev->data->dev_private;
1760         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1761         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1762         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1763         uint16_t idx, sft;
1764         int i, rc;
1765
1766         rc = is_bnxt_in_error(bp);
1767         if (rc)
1768                 return rc;
1769
1770         if (!vnic->rss_table)
1771                 return -EINVAL;
1772
1773         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1774                 return -EINVAL;
1775
1776         if (reta_size != tbl_size) {
1777                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1778                         "(%d) must equal the size supported by the hardware "
1779                         "(%d)\n", reta_size, tbl_size);
1780                 return -EINVAL;
1781         }
1782
1783         for (i = 0; i < reta_size; i++) {
1784                 struct bnxt_rx_queue *rxq;
1785
1786                 idx = i / RTE_RETA_GROUP_SIZE;
1787                 sft = i % RTE_RETA_GROUP_SIZE;
1788
1789                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1790                         continue;
1791
1792                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1793                 if (!rxq) {
1794                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1795                         return -EINVAL;
1796                 }
1797
1798                 if (BNXT_CHIP_THOR(bp)) {
1799                         vnic->rss_table[i * 2] =
1800                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1801                         vnic->rss_table[i * 2 + 1] =
1802                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1803                 } else {
1804                         vnic->rss_table[i] =
1805                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1806                 }
1807         }
1808
1809         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1810         return 0;
1811 }
1812
1813 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1814                               struct rte_eth_rss_reta_entry64 *reta_conf,
1815                               uint16_t reta_size)
1816 {
1817         struct bnxt *bp = eth_dev->data->dev_private;
1818         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1819         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1820         uint16_t idx, sft, i;
1821         int rc;
1822
1823         rc = is_bnxt_in_error(bp);
1824         if (rc)
1825                 return rc;
1826
1827         /* Retrieve from the default VNIC */
1828         if (!vnic)
1829                 return -EINVAL;
1830         if (!vnic->rss_table)
1831                 return -EINVAL;
1832
1833         if (reta_size != tbl_size) {
1834                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1835                         "(%d) must equal the size supported by the hardware "
1836                         "(%d)\n", reta_size, tbl_size);
1837                 return -EINVAL;
1838         }
1839
1840         for (idx = 0, i = 0; i < reta_size; i++) {
1841                 idx = i / RTE_RETA_GROUP_SIZE;
1842                 sft = i % RTE_RETA_GROUP_SIZE;
1843
1844                 if (reta_conf[idx].mask & (1ULL << sft)) {
1845                         uint16_t qid;
1846
1847                         if (BNXT_CHIP_THOR(bp))
1848                                 qid = bnxt_rss_to_qid(bp,
1849                                                       vnic->rss_table[i * 2]);
1850                         else
1851                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1852
1853                         if (qid == INVALID_HW_RING_ID) {
1854                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1855                                 return -EINVAL;
1856                         }
1857                         reta_conf[idx].reta[sft] = qid;
1858                 }
1859         }
1860
1861         return 0;
1862 }
1863
1864 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1865                                    struct rte_eth_rss_conf *rss_conf)
1866 {
1867         struct bnxt *bp = eth_dev->data->dev_private;
1868         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1869         struct bnxt_vnic_info *vnic;
1870         int rc;
1871
1872         rc = is_bnxt_in_error(bp);
1873         if (rc)
1874                 return rc;
1875
1876         /*
1877          * If RSS enablement were different than dev_configure,
1878          * then return -EINVAL
1879          */
1880         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1881                 if (!rss_conf->rss_hf)
1882                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1883         } else {
1884                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1885                         return -EINVAL;
1886         }
1887
1888         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1889         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
1890                rss_conf,
1891                sizeof(*rss_conf));
1892
1893         /* Update the default RSS VNIC(s) */
1894         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1895         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1896
1897         /*
1898          * If hashkey is not specified, use the previously configured
1899          * hashkey
1900          */
1901         if (!rss_conf->rss_key)
1902                 goto rss_config;
1903
1904         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1905                 PMD_DRV_LOG(ERR,
1906                             "Invalid hashkey length, should be 16 bytes\n");
1907                 return -EINVAL;
1908         }
1909         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1910
1911 rss_config:
1912         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1913         return 0;
1914 }
1915
1916 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1917                                      struct rte_eth_rss_conf *rss_conf)
1918 {
1919         struct bnxt *bp = eth_dev->data->dev_private;
1920         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1921         int len, rc;
1922         uint32_t hash_types;
1923
1924         rc = is_bnxt_in_error(bp);
1925         if (rc)
1926                 return rc;
1927
1928         /* RSS configuration is the same for all VNICs */
1929         if (vnic && vnic->rss_hash_key) {
1930                 if (rss_conf->rss_key) {
1931                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1932                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1933                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1934                 }
1935
1936                 hash_types = vnic->hash_type;
1937                 rss_conf->rss_hf = 0;
1938                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1939                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1940                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1941                 }
1942                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1943                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1944                         hash_types &=
1945                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1946                 }
1947                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1948                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1949                         hash_types &=
1950                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1951                 }
1952                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1953                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1954                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1955                 }
1956                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1957                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1958                         hash_types &=
1959                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1960                 }
1961                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1962                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1963                         hash_types &=
1964                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1965                 }
1966                 if (hash_types) {
1967                         PMD_DRV_LOG(ERR,
1968                                 "Unknown RSS config from firmware (%08x), RSS disabled",
1969                                 vnic->hash_type);
1970                         return -ENOTSUP;
1971                 }
1972         } else {
1973                 rss_conf->rss_hf = 0;
1974         }
1975         return 0;
1976 }
1977
1978 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1979                                struct rte_eth_fc_conf *fc_conf)
1980 {
1981         struct bnxt *bp = dev->data->dev_private;
1982         struct rte_eth_link link_info;
1983         int rc;
1984
1985         rc = is_bnxt_in_error(bp);
1986         if (rc)
1987                 return rc;
1988
1989         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1990         if (rc)
1991                 return rc;
1992
1993         memset(fc_conf, 0, sizeof(*fc_conf));
1994         if (bp->link_info->auto_pause)
1995                 fc_conf->autoneg = 1;
1996         switch (bp->link_info->pause) {
1997         case 0:
1998                 fc_conf->mode = RTE_FC_NONE;
1999                 break;
2000         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2001                 fc_conf->mode = RTE_FC_TX_PAUSE;
2002                 break;
2003         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2004                 fc_conf->mode = RTE_FC_RX_PAUSE;
2005                 break;
2006         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2007                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2008                 fc_conf->mode = RTE_FC_FULL;
2009                 break;
2010         }
2011         return 0;
2012 }
2013
2014 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2015                                struct rte_eth_fc_conf *fc_conf)
2016 {
2017         struct bnxt *bp = dev->data->dev_private;
2018         int rc;
2019
2020         rc = is_bnxt_in_error(bp);
2021         if (rc)
2022                 return rc;
2023
2024         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2025                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2026                 return -ENOTSUP;
2027         }
2028
2029         switch (fc_conf->mode) {
2030         case RTE_FC_NONE:
2031                 bp->link_info->auto_pause = 0;
2032                 bp->link_info->force_pause = 0;
2033                 break;
2034         case RTE_FC_RX_PAUSE:
2035                 if (fc_conf->autoneg) {
2036                         bp->link_info->auto_pause =
2037                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2038                         bp->link_info->force_pause = 0;
2039                 } else {
2040                         bp->link_info->auto_pause = 0;
2041                         bp->link_info->force_pause =
2042                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2043                 }
2044                 break;
2045         case RTE_FC_TX_PAUSE:
2046                 if (fc_conf->autoneg) {
2047                         bp->link_info->auto_pause =
2048                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2049                         bp->link_info->force_pause = 0;
2050                 } else {
2051                         bp->link_info->auto_pause = 0;
2052                         bp->link_info->force_pause =
2053                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2054                 }
2055                 break;
2056         case RTE_FC_FULL:
2057                 if (fc_conf->autoneg) {
2058                         bp->link_info->auto_pause =
2059                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2060                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2061                         bp->link_info->force_pause = 0;
2062                 } else {
2063                         bp->link_info->auto_pause = 0;
2064                         bp->link_info->force_pause =
2065                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2066                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2067                 }
2068                 break;
2069         }
2070         return bnxt_set_hwrm_link_config(bp, true);
2071 }
2072
2073 /* Add UDP tunneling port */
2074 static int
2075 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2076                          struct rte_eth_udp_tunnel *udp_tunnel)
2077 {
2078         struct bnxt *bp = eth_dev->data->dev_private;
2079         uint16_t tunnel_type = 0;
2080         int rc = 0;
2081
2082         rc = is_bnxt_in_error(bp);
2083         if (rc)
2084                 return rc;
2085
2086         switch (udp_tunnel->prot_type) {
2087         case RTE_TUNNEL_TYPE_VXLAN:
2088                 if (bp->vxlan_port_cnt) {
2089                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2090                                 udp_tunnel->udp_port);
2091                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2092                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2093                                 return -ENOSPC;
2094                         }
2095                         bp->vxlan_port_cnt++;
2096                         return 0;
2097                 }
2098                 tunnel_type =
2099                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2100                 bp->vxlan_port_cnt++;
2101                 break;
2102         case RTE_TUNNEL_TYPE_GENEVE:
2103                 if (bp->geneve_port_cnt) {
2104                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2105                                 udp_tunnel->udp_port);
2106                         if (bp->geneve_port != udp_tunnel->udp_port) {
2107                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2108                                 return -ENOSPC;
2109                         }
2110                         bp->geneve_port_cnt++;
2111                         return 0;
2112                 }
2113                 tunnel_type =
2114                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2115                 bp->geneve_port_cnt++;
2116                 break;
2117         default:
2118                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2119                 return -ENOTSUP;
2120         }
2121         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2122                                              tunnel_type);
2123         return rc;
2124 }
2125
2126 static int
2127 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2128                          struct rte_eth_udp_tunnel *udp_tunnel)
2129 {
2130         struct bnxt *bp = eth_dev->data->dev_private;
2131         uint16_t tunnel_type = 0;
2132         uint16_t port = 0;
2133         int rc = 0;
2134
2135         rc = is_bnxt_in_error(bp);
2136         if (rc)
2137                 return rc;
2138
2139         switch (udp_tunnel->prot_type) {
2140         case RTE_TUNNEL_TYPE_VXLAN:
2141                 if (!bp->vxlan_port_cnt) {
2142                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2143                         return -EINVAL;
2144                 }
2145                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2146                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2147                                 udp_tunnel->udp_port, bp->vxlan_port);
2148                         return -EINVAL;
2149                 }
2150                 if (--bp->vxlan_port_cnt)
2151                         return 0;
2152
2153                 tunnel_type =
2154                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2155                 port = bp->vxlan_fw_dst_port_id;
2156                 break;
2157         case RTE_TUNNEL_TYPE_GENEVE:
2158                 if (!bp->geneve_port_cnt) {
2159                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2160                         return -EINVAL;
2161                 }
2162                 if (bp->geneve_port != udp_tunnel->udp_port) {
2163                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2164                                 udp_tunnel->udp_port, bp->geneve_port);
2165                         return -EINVAL;
2166                 }
2167                 if (--bp->geneve_port_cnt)
2168                         return 0;
2169
2170                 tunnel_type =
2171                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2172                 port = bp->geneve_fw_dst_port_id;
2173                 break;
2174         default:
2175                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2176                 return -ENOTSUP;
2177         }
2178
2179         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2180         if (!rc) {
2181                 if (tunnel_type ==
2182                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
2183                         bp->vxlan_port = 0;
2184                 if (tunnel_type ==
2185                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
2186                         bp->geneve_port = 0;
2187         }
2188         return rc;
2189 }
2190
2191 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2192 {
2193         struct bnxt_filter_info *filter;
2194         struct bnxt_vnic_info *vnic;
2195         int rc = 0;
2196         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2197
2198         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2199         filter = STAILQ_FIRST(&vnic->filter);
2200         while (filter) {
2201                 /* Search for this matching MAC+VLAN filter */
2202                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2203                         /* Delete the filter */
2204                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2205                         if (rc)
2206                                 return rc;
2207                         STAILQ_REMOVE(&vnic->filter, filter,
2208                                       bnxt_filter_info, next);
2209                         bnxt_free_filter(bp, filter);
2210                         PMD_DRV_LOG(INFO,
2211                                     "Deleted vlan filter for %d\n",
2212                                     vlan_id);
2213                         return 0;
2214                 }
2215                 filter = STAILQ_NEXT(filter, next);
2216         }
2217         return -ENOENT;
2218 }
2219
2220 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2221 {
2222         struct bnxt_filter_info *filter;
2223         struct bnxt_vnic_info *vnic;
2224         int rc = 0;
2225         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2226                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2227         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2228
2229         /* Implementation notes on the use of VNIC in this command:
2230          *
2231          * By default, these filters belong to default vnic for the function.
2232          * Once these filters are set up, only destination VNIC can be modified.
2233          * If the destination VNIC is not specified in this command,
2234          * then the HWRM shall only create an l2 context id.
2235          */
2236
2237         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2238         filter = STAILQ_FIRST(&vnic->filter);
2239         /* Check if the VLAN has already been added */
2240         while (filter) {
2241                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2242                         return -EEXIST;
2243
2244                 filter = STAILQ_NEXT(filter, next);
2245         }
2246
2247         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2248          * command to create MAC+VLAN filter with the right flags, enables set.
2249          */
2250         filter = bnxt_alloc_filter(bp);
2251         if (!filter) {
2252                 PMD_DRV_LOG(ERR,
2253                             "MAC/VLAN filter alloc failed\n");
2254                 return -ENOMEM;
2255         }
2256         /* MAC + VLAN ID filter */
2257         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2258          * untagged packets are received
2259          *
2260          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2261          * packets and only the programmed vlan's packets are received
2262          */
2263         filter->l2_ivlan = vlan_id;
2264         filter->l2_ivlan_mask = 0x0FFF;
2265         filter->enables |= en;
2266         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2267
2268         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2269         if (rc) {
2270                 /* Free the newly allocated filter as we were
2271                  * not able to create the filter in hardware.
2272                  */
2273                 bnxt_free_filter(bp, filter);
2274                 return rc;
2275         }
2276
2277         filter->mac_index = 0;
2278         /* Add this new filter to the list */
2279         if (vlan_id == 0)
2280                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2281         else
2282                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2283
2284         PMD_DRV_LOG(INFO,
2285                     "Added Vlan filter for %d\n", vlan_id);
2286         return rc;
2287 }
2288
2289 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2290                 uint16_t vlan_id, int on)
2291 {
2292         struct bnxt *bp = eth_dev->data->dev_private;
2293         int rc;
2294
2295         rc = is_bnxt_in_error(bp);
2296         if (rc)
2297                 return rc;
2298
2299         if (!eth_dev->data->dev_started) {
2300                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2301                 return -EINVAL;
2302         }
2303
2304         /* These operations apply to ALL existing MAC/VLAN filters */
2305         if (on)
2306                 return bnxt_add_vlan_filter(bp, vlan_id);
2307         else
2308                 return bnxt_del_vlan_filter(bp, vlan_id);
2309 }
2310
2311 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2312                                     struct bnxt_vnic_info *vnic)
2313 {
2314         struct bnxt_filter_info *filter;
2315         int rc;
2316
2317         filter = STAILQ_FIRST(&vnic->filter);
2318         while (filter) {
2319                 if (filter->mac_index == 0 &&
2320                     !memcmp(filter->l2_addr, bp->mac_addr,
2321                             RTE_ETHER_ADDR_LEN)) {
2322                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2323                         if (!rc) {
2324                                 STAILQ_REMOVE(&vnic->filter, filter,
2325                                               bnxt_filter_info, next);
2326                                 bnxt_free_filter(bp, filter);
2327                         }
2328                         return rc;
2329                 }
2330                 filter = STAILQ_NEXT(filter, next);
2331         }
2332         return 0;
2333 }
2334
2335 static int
2336 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2337 {
2338         struct bnxt_vnic_info *vnic;
2339         unsigned int i;
2340         int rc;
2341
2342         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2343         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2344                 /* Remove any VLAN filters programmed */
2345                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2346                         bnxt_del_vlan_filter(bp, i);
2347
2348                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2349                 if (rc)
2350                         return rc;
2351         } else {
2352                 /* Default filter will allow packets that match the
2353                  * dest mac. So, it has to be deleted, otherwise, we
2354                  * will endup receiving vlan packets for which the
2355                  * filter is not programmed, when hw-vlan-filter
2356                  * configuration is ON
2357                  */
2358                 bnxt_del_dflt_mac_filter(bp, vnic);
2359                 /* This filter will allow only untagged packets */
2360                 bnxt_add_vlan_filter(bp, 0);
2361         }
2362         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2363                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2364
2365         return 0;
2366 }
2367
2368 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2369 {
2370         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2371         unsigned int i;
2372         int rc;
2373
2374         /* Destroy vnic filters and vnic */
2375         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2376             DEV_RX_OFFLOAD_VLAN_FILTER) {
2377                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2378                         bnxt_del_vlan_filter(bp, i);
2379         }
2380         bnxt_del_dflt_mac_filter(bp, vnic);
2381
2382         rc = bnxt_hwrm_vnic_free(bp, vnic);
2383         if (rc)
2384                 return rc;
2385
2386         rte_free(vnic->fw_grp_ids);
2387         vnic->fw_grp_ids = NULL;
2388
2389         vnic->rx_queue_cnt = 0;
2390
2391         return 0;
2392 }
2393
2394 static int
2395 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2396 {
2397         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2398         int rc;
2399
2400         /* Destroy, recreate and reconfigure the default vnic */
2401         rc = bnxt_free_one_vnic(bp, 0);
2402         if (rc)
2403                 return rc;
2404
2405         /* default vnic 0 */
2406         rc = bnxt_setup_one_vnic(bp, 0);
2407         if (rc)
2408                 return rc;
2409
2410         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2411             DEV_RX_OFFLOAD_VLAN_FILTER) {
2412                 rc = bnxt_add_vlan_filter(bp, 0);
2413                 if (rc)
2414                         return rc;
2415                 rc = bnxt_restore_vlan_filters(bp);
2416                 if (rc)
2417                         return rc;
2418         } else {
2419                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2420                 if (rc)
2421                         return rc;
2422         }
2423
2424         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2425         if (rc)
2426                 return rc;
2427
2428         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2429                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2430
2431         return rc;
2432 }
2433
2434 static int
2435 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2436 {
2437         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2438         struct bnxt *bp = dev->data->dev_private;
2439         int rc;
2440
2441         rc = is_bnxt_in_error(bp);
2442         if (rc)
2443                 return rc;
2444
2445         /* Filter settings will get applied when port is started */
2446         if (!dev->data->dev_started)
2447                 return 0;
2448
2449         if (mask & ETH_VLAN_FILTER_MASK) {
2450                 /* Enable or disable VLAN filtering */
2451                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2452                 if (rc)
2453                         return rc;
2454         }
2455
2456         if (mask & ETH_VLAN_STRIP_MASK) {
2457                 /* Enable or disable VLAN stripping */
2458                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2459                 if (rc)
2460                         return rc;
2461         }
2462
2463         if (mask & ETH_VLAN_EXTEND_MASK) {
2464                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2465                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2466                 else
2467                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2468         }
2469
2470         return 0;
2471 }
2472
2473 static int
2474 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2475                       uint16_t tpid)
2476 {
2477         struct bnxt *bp = dev->data->dev_private;
2478         int qinq = dev->data->dev_conf.rxmode.offloads &
2479                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2480
2481         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2482             vlan_type != ETH_VLAN_TYPE_OUTER) {
2483                 PMD_DRV_LOG(ERR,
2484                             "Unsupported vlan type.");
2485                 return -EINVAL;
2486         }
2487         if (!qinq) {
2488                 PMD_DRV_LOG(ERR,
2489                             "QinQ not enabled. Needs to be ON as we can "
2490                             "accelerate only outer vlan\n");
2491                 return -EINVAL;
2492         }
2493
2494         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2495                 switch (tpid) {
2496                 case RTE_ETHER_TYPE_QINQ:
2497                         bp->outer_tpid_bd =
2498                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2499                                 break;
2500                 case RTE_ETHER_TYPE_VLAN:
2501                         bp->outer_tpid_bd =
2502                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2503                                 break;
2504                 case RTE_ETHER_TYPE_QINQ1:
2505                         bp->outer_tpid_bd =
2506                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2507                                 break;
2508                 case RTE_ETHER_TYPE_QINQ2:
2509                         bp->outer_tpid_bd =
2510                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2511                                 break;
2512                 case RTE_ETHER_TYPE_QINQ3:
2513                         bp->outer_tpid_bd =
2514                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2515                                 break;
2516                 default:
2517                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2518                         return -EINVAL;
2519                 }
2520                 bp->outer_tpid_bd |= tpid;
2521                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2522         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2523                 PMD_DRV_LOG(ERR,
2524                             "Can accelerate only outer vlan in QinQ\n");
2525                 return -EINVAL;
2526         }
2527
2528         return 0;
2529 }
2530
2531 static int
2532 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2533                              struct rte_ether_addr *addr)
2534 {
2535         struct bnxt *bp = dev->data->dev_private;
2536         /* Default Filter is tied to VNIC 0 */
2537         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2538         int rc;
2539
2540         rc = is_bnxt_in_error(bp);
2541         if (rc)
2542                 return rc;
2543
2544         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2545                 return -EPERM;
2546
2547         if (rte_is_zero_ether_addr(addr))
2548                 return -EINVAL;
2549
2550         /* Filter settings will get applied when port is started */
2551         if (!dev->data->dev_started)
2552                 return 0;
2553
2554         /* Check if the requested MAC is already added */
2555         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2556                 return 0;
2557
2558         /* Destroy filter and re-create it */
2559         bnxt_del_dflt_mac_filter(bp, vnic);
2560
2561         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2562         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2563                 /* This filter will allow only untagged packets */
2564                 rc = bnxt_add_vlan_filter(bp, 0);
2565         } else {
2566                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2567         }
2568
2569         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2570         return rc;
2571 }
2572
2573 static int
2574 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2575                           struct rte_ether_addr *mc_addr_set,
2576                           uint32_t nb_mc_addr)
2577 {
2578         struct bnxt *bp = eth_dev->data->dev_private;
2579         char *mc_addr_list = (char *)mc_addr_set;
2580         struct bnxt_vnic_info *vnic;
2581         uint32_t off = 0, i = 0;
2582         int rc;
2583
2584         rc = is_bnxt_in_error(bp);
2585         if (rc)
2586                 return rc;
2587
2588         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2589
2590         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2591                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2592                 goto allmulti;
2593         }
2594
2595         /* TODO Check for Duplicate mcast addresses */
2596         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2597         for (i = 0; i < nb_mc_addr; i++) {
2598                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2599                         RTE_ETHER_ADDR_LEN);
2600                 off += RTE_ETHER_ADDR_LEN;
2601         }
2602
2603         vnic->mc_addr_cnt = i;
2604         if (vnic->mc_addr_cnt)
2605                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2606         else
2607                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2608
2609 allmulti:
2610         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2611 }
2612
2613 static int
2614 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2615 {
2616         struct bnxt *bp = dev->data->dev_private;
2617         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2618         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2619         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2620         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2621         int ret;
2622
2623         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2624                         fw_major, fw_minor, fw_updt, fw_rsvd);
2625
2626         ret += 1; /* add the size of '\0' */
2627         if (fw_size < (uint32_t)ret)
2628                 return ret;
2629         else
2630                 return 0;
2631 }
2632
2633 static void
2634 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2635         struct rte_eth_rxq_info *qinfo)
2636 {
2637         struct bnxt *bp = dev->data->dev_private;
2638         struct bnxt_rx_queue *rxq;
2639
2640         if (is_bnxt_in_error(bp))
2641                 return;
2642
2643         rxq = dev->data->rx_queues[queue_id];
2644
2645         qinfo->mp = rxq->mb_pool;
2646         qinfo->scattered_rx = dev->data->scattered_rx;
2647         qinfo->nb_desc = rxq->nb_rx_desc;
2648
2649         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2650         qinfo->conf.rx_drop_en = rxq->drop_en;
2651         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2652         qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2653 }
2654
2655 static void
2656 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2657         struct rte_eth_txq_info *qinfo)
2658 {
2659         struct bnxt *bp = dev->data->dev_private;
2660         struct bnxt_tx_queue *txq;
2661
2662         if (is_bnxt_in_error(bp))
2663                 return;
2664
2665         txq = dev->data->tx_queues[queue_id];
2666
2667         qinfo->nb_desc = txq->nb_tx_desc;
2668
2669         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2670         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2671         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2672
2673         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2674         qinfo->conf.tx_rs_thresh = 0;
2675         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2676         qinfo->conf.offloads = dev->data->dev_conf.txmode.offloads;
2677 }
2678
2679 static const struct {
2680         eth_rx_burst_t pkt_burst;
2681         const char *info;
2682 } bnxt_rx_burst_info[] = {
2683         {bnxt_recv_pkts,        "Scalar"},
2684 #if defined(RTE_ARCH_X86)
2685         {bnxt_recv_pkts_vec,    "Vector SSE"},
2686 #elif defined(RTE_ARCH_ARM64)
2687         {bnxt_recv_pkts_vec,    "Vector Neon"},
2688 #endif
2689 };
2690
2691 static int
2692 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2693                        struct rte_eth_burst_mode *mode)
2694 {
2695         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2696         size_t i;
2697
2698         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2699                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2700                         snprintf(mode->info, sizeof(mode->info), "%s",
2701                                  bnxt_rx_burst_info[i].info);
2702                         return 0;
2703                 }
2704         }
2705
2706         return -EINVAL;
2707 }
2708
2709 static const struct {
2710         eth_tx_burst_t pkt_burst;
2711         const char *info;
2712 } bnxt_tx_burst_info[] = {
2713         {bnxt_xmit_pkts,        "Scalar"},
2714 #if defined(RTE_ARCH_X86)
2715         {bnxt_xmit_pkts_vec,    "Vector SSE"},
2716 #elif defined(RTE_ARCH_ARM64)
2717         {bnxt_xmit_pkts_vec,    "Vector Neon"},
2718 #endif
2719 };
2720
2721 static int
2722 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2723                        struct rte_eth_burst_mode *mode)
2724 {
2725         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2726         size_t i;
2727
2728         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2729                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2730                         snprintf(mode->info, sizeof(mode->info), "%s",
2731                                  bnxt_tx_burst_info[i].info);
2732                         return 0;
2733                 }
2734         }
2735
2736         return -EINVAL;
2737 }
2738
2739 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2740 {
2741         struct bnxt *bp = eth_dev->data->dev_private;
2742         uint32_t new_pkt_size;
2743         uint32_t rc = 0;
2744         uint32_t i;
2745
2746         rc = is_bnxt_in_error(bp);
2747         if (rc)
2748                 return rc;
2749
2750         /* Exit if receive queues are not configured yet */
2751         if (!eth_dev->data->nb_rx_queues)
2752                 return rc;
2753
2754         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2755                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2756
2757         /*
2758          * Disallow any MTU change that would require scattered receive support
2759          * if it is not already enabled.
2760          */
2761         if (eth_dev->data->dev_started &&
2762             !eth_dev->data->scattered_rx &&
2763             (new_pkt_size >
2764              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2765                 PMD_DRV_LOG(ERR,
2766                             "MTU change would require scattered rx support. ");
2767                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2768                 return -EINVAL;
2769         }
2770
2771         if (new_mtu > RTE_ETHER_MTU) {
2772                 bp->flags |= BNXT_FLAG_JUMBO;
2773                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2774                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2775         } else {
2776                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2777                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2778                 bp->flags &= ~BNXT_FLAG_JUMBO;
2779         }
2780
2781         /* Is there a change in mtu setting? */
2782         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2783                 return rc;
2784
2785         for (i = 0; i < bp->nr_vnics; i++) {
2786                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2787                 uint16_t size = 0;
2788
2789                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2790                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2791                 if (rc)
2792                         break;
2793
2794                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2795                 size -= RTE_PKTMBUF_HEADROOM;
2796
2797                 if (size < new_mtu) {
2798                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2799                         if (rc)
2800                                 return rc;
2801                 }
2802         }
2803
2804         if (!rc)
2805                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2806
2807         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2808
2809         return rc;
2810 }
2811
2812 static int
2813 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2814 {
2815         struct bnxt *bp = dev->data->dev_private;
2816         uint16_t vlan = bp->vlan;
2817         int rc;
2818
2819         rc = is_bnxt_in_error(bp);
2820         if (rc)
2821                 return rc;
2822
2823         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2824                 PMD_DRV_LOG(ERR,
2825                         "PVID cannot be modified for this function\n");
2826                 return -ENOTSUP;
2827         }
2828         bp->vlan = on ? pvid : 0;
2829
2830         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2831         if (rc)
2832                 bp->vlan = vlan;
2833         return rc;
2834 }
2835
2836 static int
2837 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2838 {
2839         struct bnxt *bp = dev->data->dev_private;
2840         int rc;
2841
2842         rc = is_bnxt_in_error(bp);
2843         if (rc)
2844                 return rc;
2845
2846         return bnxt_hwrm_port_led_cfg(bp, true);
2847 }
2848
2849 static int
2850 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2851 {
2852         struct bnxt *bp = dev->data->dev_private;
2853         int rc;
2854
2855         rc = is_bnxt_in_error(bp);
2856         if (rc)
2857                 return rc;
2858
2859         return bnxt_hwrm_port_led_cfg(bp, false);
2860 }
2861
2862 static uint32_t
2863 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2864 {
2865         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2866         uint32_t desc = 0, raw_cons = 0, cons;
2867         struct bnxt_cp_ring_info *cpr;
2868         struct bnxt_rx_queue *rxq;
2869         struct rx_pkt_cmpl *rxcmp;
2870         int rc;
2871
2872         rc = is_bnxt_in_error(bp);
2873         if (rc)
2874                 return rc;
2875
2876         rxq = dev->data->rx_queues[rx_queue_id];
2877         cpr = rxq->cp_ring;
2878         raw_cons = cpr->cp_raw_cons;
2879
2880         while (1) {
2881                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2882                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2883                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2884
2885                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2886                         break;
2887                 } else {
2888                         raw_cons++;
2889                         desc++;
2890                 }
2891         }
2892
2893         return desc;
2894 }
2895
2896 static int
2897 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2898 {
2899         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2900         struct bnxt_rx_ring_info *rxr;
2901         struct bnxt_cp_ring_info *cpr;
2902         struct rte_mbuf *rx_buf;
2903         struct rx_pkt_cmpl *rxcmp;
2904         uint32_t cons, cp_cons;
2905         int rc;
2906
2907         if (!rxq)
2908                 return -EINVAL;
2909
2910         rc = is_bnxt_in_error(rxq->bp);
2911         if (rc)
2912                 return rc;
2913
2914         cpr = rxq->cp_ring;
2915         rxr = rxq->rx_ring;
2916
2917         if (offset >= rxq->nb_rx_desc)
2918                 return -EINVAL;
2919
2920         cons = RING_CMP(cpr->cp_ring_struct, offset);
2921         cp_cons = cpr->cp_raw_cons;
2922         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2923
2924         if (cons > cp_cons) {
2925                 if (CMPL_VALID(rxcmp, cpr->valid))
2926                         return RTE_ETH_RX_DESC_DONE;
2927         } else {
2928                 if (CMPL_VALID(rxcmp, !cpr->valid))
2929                         return RTE_ETH_RX_DESC_DONE;
2930         }
2931         rx_buf = rxr->rx_buf_ring[cons];
2932         if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf)
2933                 return RTE_ETH_RX_DESC_UNAVAIL;
2934
2935
2936         return RTE_ETH_RX_DESC_AVAIL;
2937 }
2938
2939 static int
2940 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2941 {
2942         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2943         struct bnxt_tx_ring_info *txr;
2944         struct bnxt_cp_ring_info *cpr;
2945         struct bnxt_sw_tx_bd *tx_buf;
2946         struct tx_pkt_cmpl *txcmp;
2947         uint32_t cons, cp_cons;
2948         int rc;
2949
2950         if (!txq)
2951                 return -EINVAL;
2952
2953         rc = is_bnxt_in_error(txq->bp);
2954         if (rc)
2955                 return rc;
2956
2957         cpr = txq->cp_ring;
2958         txr = txq->tx_ring;
2959
2960         if (offset >= txq->nb_tx_desc)
2961                 return -EINVAL;
2962
2963         cons = RING_CMP(cpr->cp_ring_struct, offset);
2964         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2965         cp_cons = cpr->cp_raw_cons;
2966
2967         if (cons > cp_cons) {
2968                 if (CMPL_VALID(txcmp, cpr->valid))
2969                         return RTE_ETH_TX_DESC_UNAVAIL;
2970         } else {
2971                 if (CMPL_VALID(txcmp, !cpr->valid))
2972                         return RTE_ETH_TX_DESC_UNAVAIL;
2973         }
2974         tx_buf = &txr->tx_buf_ring[cons];
2975         if (tx_buf->mbuf == NULL)
2976                 return RTE_ETH_TX_DESC_DONE;
2977
2978         return RTE_ETH_TX_DESC_FULL;
2979 }
2980
2981 static struct bnxt_filter_info *
2982 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2983                                 struct rte_eth_ethertype_filter *efilter,
2984                                 struct bnxt_vnic_info *vnic0,
2985                                 struct bnxt_vnic_info *vnic,
2986                                 int *ret)
2987 {
2988         struct bnxt_filter_info *mfilter = NULL;
2989         int match = 0;
2990         *ret = 0;
2991
2992         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2993                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2994                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2995                         " ethertype filter.", efilter->ether_type);
2996                 *ret = -EINVAL;
2997                 goto exit;
2998         }
2999         if (efilter->queue >= bp->rx_nr_rings) {
3000                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
3001                 *ret = -EINVAL;
3002                 goto exit;
3003         }
3004
3005         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3006         vnic = &bp->vnic_info[efilter->queue];
3007         if (vnic == NULL) {
3008                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
3009                 *ret = -EINVAL;
3010                 goto exit;
3011         }
3012
3013         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3014                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
3015                         if ((!memcmp(efilter->mac_addr.addr_bytes,
3016                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
3017                              mfilter->flags ==
3018                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
3019                              mfilter->ethertype == efilter->ether_type)) {
3020                                 match = 1;
3021                                 break;
3022                         }
3023                 }
3024         } else {
3025                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
3026                         if ((!memcmp(efilter->mac_addr.addr_bytes,
3027                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
3028                              mfilter->ethertype == efilter->ether_type &&
3029                              mfilter->flags ==
3030                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
3031                                 match = 1;
3032                                 break;
3033                         }
3034         }
3035
3036         if (match)
3037                 *ret = -EEXIST;
3038
3039 exit:
3040         return mfilter;
3041 }
3042
3043 static int
3044 bnxt_ethertype_filter(struct rte_eth_dev *dev,
3045                         enum rte_filter_op filter_op,
3046                         void *arg)
3047 {
3048         struct bnxt *bp = dev->data->dev_private;
3049         struct rte_eth_ethertype_filter *efilter =
3050                         (struct rte_eth_ethertype_filter *)arg;
3051         struct bnxt_filter_info *bfilter, *filter1;
3052         struct bnxt_vnic_info *vnic, *vnic0;
3053         int ret;
3054
3055         if (filter_op == RTE_ETH_FILTER_NOP)
3056                 return 0;
3057
3058         if (arg == NULL) {
3059                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3060                             filter_op);
3061                 return -EINVAL;
3062         }
3063
3064         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3065         vnic = &bp->vnic_info[efilter->queue];
3066
3067         switch (filter_op) {
3068         case RTE_ETH_FILTER_ADD:
3069                 bnxt_match_and_validate_ether_filter(bp, efilter,
3070                                                         vnic0, vnic, &ret);
3071                 if (ret < 0)
3072                         return ret;
3073
3074                 bfilter = bnxt_get_unused_filter(bp);
3075                 if (bfilter == NULL) {
3076                         PMD_DRV_LOG(ERR,
3077                                 "Not enough resources for a new filter.\n");
3078                         return -ENOMEM;
3079                 }
3080                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3081                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
3082                        RTE_ETHER_ADDR_LEN);
3083                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
3084                        RTE_ETHER_ADDR_LEN);
3085                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3086                 bfilter->ethertype = efilter->ether_type;
3087                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3088
3089                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
3090                 if (filter1 == NULL) {
3091                         ret = -EINVAL;
3092                         goto cleanup;
3093                 }
3094                 bfilter->enables |=
3095                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3096                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3097
3098                 bfilter->dst_id = vnic->fw_vnic_id;
3099
3100                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3101                         bfilter->flags =
3102                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3103                 }
3104
3105                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3106                 if (ret)
3107                         goto cleanup;
3108                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3109                 break;
3110         case RTE_ETH_FILTER_DELETE:
3111                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
3112                                                         vnic0, vnic, &ret);
3113                 if (ret == -EEXIST) {
3114                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
3115
3116                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
3117                                       next);
3118                         bnxt_free_filter(bp, filter1);
3119                 } else if (ret == 0) {
3120                         PMD_DRV_LOG(ERR, "No matching filter found\n");
3121                 }
3122                 break;
3123         default:
3124                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3125                 ret = -EINVAL;
3126                 goto error;
3127         }
3128         return ret;
3129 cleanup:
3130         bnxt_free_filter(bp, bfilter);
3131 error:
3132         return ret;
3133 }
3134
3135 static inline int
3136 parse_ntuple_filter(struct bnxt *bp,
3137                     struct rte_eth_ntuple_filter *nfilter,
3138                     struct bnxt_filter_info *bfilter)
3139 {
3140         uint32_t en = 0;
3141
3142         if (nfilter->queue >= bp->rx_nr_rings) {
3143                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
3144                 return -EINVAL;
3145         }
3146
3147         switch (nfilter->dst_port_mask) {
3148         case UINT16_MAX:
3149                 bfilter->dst_port_mask = -1;
3150                 bfilter->dst_port = nfilter->dst_port;
3151                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
3152                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3153                 break;
3154         default:
3155                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3156                 return -EINVAL;
3157         }
3158
3159         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3160         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3161
3162         switch (nfilter->proto_mask) {
3163         case UINT8_MAX:
3164                 if (nfilter->proto == 17) /* IPPROTO_UDP */
3165                         bfilter->ip_protocol = 17;
3166                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
3167                         bfilter->ip_protocol = 6;
3168                 else
3169                         return -EINVAL;
3170                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3171                 break;
3172         default:
3173                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3174                 return -EINVAL;
3175         }
3176
3177         switch (nfilter->dst_ip_mask) {
3178         case UINT32_MAX:
3179                 bfilter->dst_ipaddr_mask[0] = -1;
3180                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
3181                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
3182                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3183                 break;
3184         default:
3185                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3186                 return -EINVAL;
3187         }
3188
3189         switch (nfilter->src_ip_mask) {
3190         case UINT32_MAX:
3191                 bfilter->src_ipaddr_mask[0] = -1;
3192                 bfilter->src_ipaddr[0] = nfilter->src_ip;
3193                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
3194                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3195                 break;
3196         default:
3197                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3198                 return -EINVAL;
3199         }
3200
3201         switch (nfilter->src_port_mask) {
3202         case UINT16_MAX:
3203                 bfilter->src_port_mask = -1;
3204                 bfilter->src_port = nfilter->src_port;
3205                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
3206                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3207                 break;
3208         default:
3209                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3210                 return -EINVAL;
3211         }
3212
3213         bfilter->enables = en;
3214         return 0;
3215 }
3216
3217 static struct bnxt_filter_info*
3218 bnxt_match_ntuple_filter(struct bnxt *bp,
3219                          struct bnxt_filter_info *bfilter,
3220                          struct bnxt_vnic_info **mvnic)
3221 {
3222         struct bnxt_filter_info *mfilter = NULL;
3223         int i;
3224
3225         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3226                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3227                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
3228                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
3229                             bfilter->src_ipaddr_mask[0] ==
3230                             mfilter->src_ipaddr_mask[0] &&
3231                             bfilter->src_port == mfilter->src_port &&
3232                             bfilter->src_port_mask == mfilter->src_port_mask &&
3233                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
3234                             bfilter->dst_ipaddr_mask[0] ==
3235                             mfilter->dst_ipaddr_mask[0] &&
3236                             bfilter->dst_port == mfilter->dst_port &&
3237                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
3238                             bfilter->flags == mfilter->flags &&
3239                             bfilter->enables == mfilter->enables) {
3240                                 if (mvnic)
3241                                         *mvnic = vnic;
3242                                 return mfilter;
3243                         }
3244                 }
3245         }
3246         return NULL;
3247 }
3248
3249 static int
3250 bnxt_cfg_ntuple_filter(struct bnxt *bp,
3251                        struct rte_eth_ntuple_filter *nfilter,
3252                        enum rte_filter_op filter_op)
3253 {
3254         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
3255         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
3256         int ret;
3257
3258         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
3259                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3260                 return -EINVAL;
3261         }
3262
3263         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
3264                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
3265                 return -EINVAL;
3266         }
3267
3268         bfilter = bnxt_get_unused_filter(bp);
3269         if (bfilter == NULL) {
3270                 PMD_DRV_LOG(ERR,
3271                         "Not enough resources for a new filter.\n");
3272                 return -ENOMEM;
3273         }
3274         ret = parse_ntuple_filter(bp, nfilter, bfilter);
3275         if (ret < 0)
3276                 goto free_filter;
3277
3278         vnic = &bp->vnic_info[nfilter->queue];
3279         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3280         filter1 = STAILQ_FIRST(&vnic0->filter);
3281         if (filter1 == NULL) {
3282                 ret = -EINVAL;
3283                 goto free_filter;
3284         }
3285
3286         bfilter->dst_id = vnic->fw_vnic_id;
3287         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3288         bfilter->enables |=
3289                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3290         bfilter->ethertype = 0x800;
3291         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3292
3293         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3294
3295         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3296             bfilter->dst_id == mfilter->dst_id) {
3297                 PMD_DRV_LOG(ERR, "filter exists.\n");
3298                 ret = -EEXIST;
3299                 goto free_filter;
3300         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3301                    bfilter->dst_id != mfilter->dst_id) {
3302                 mfilter->dst_id = vnic->fw_vnic_id;
3303                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3304                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3305                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3306                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3307                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3308                 goto free_filter;
3309         }
3310         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3311                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3312                 ret = -ENOENT;
3313                 goto free_filter;
3314         }
3315
3316         if (filter_op == RTE_ETH_FILTER_ADD) {
3317                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3318                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3319                 if (ret)
3320                         goto free_filter;
3321                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3322         } else {
3323                 if (mfilter == NULL) {
3324                         /* This should not happen. But for Coverity! */
3325                         ret = -ENOENT;
3326                         goto free_filter;
3327                 }
3328                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3329
3330                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3331                 bnxt_free_filter(bp, mfilter);
3332                 bnxt_free_filter(bp, bfilter);
3333         }
3334
3335         return 0;
3336 free_filter:
3337         bnxt_free_filter(bp, bfilter);
3338         return ret;
3339 }
3340
3341 static int
3342 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3343                         enum rte_filter_op filter_op,
3344                         void *arg)
3345 {
3346         struct bnxt *bp = dev->data->dev_private;
3347         int ret;
3348
3349         if (filter_op == RTE_ETH_FILTER_NOP)
3350                 return 0;
3351
3352         if (arg == NULL) {
3353                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3354                             filter_op);
3355                 return -EINVAL;
3356         }
3357
3358         switch (filter_op) {
3359         case RTE_ETH_FILTER_ADD:
3360                 ret = bnxt_cfg_ntuple_filter(bp,
3361                         (struct rte_eth_ntuple_filter *)arg,
3362                         filter_op);
3363                 break;
3364         case RTE_ETH_FILTER_DELETE:
3365                 ret = bnxt_cfg_ntuple_filter(bp,
3366                         (struct rte_eth_ntuple_filter *)arg,
3367                         filter_op);
3368                 break;
3369         default:
3370                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3371                 ret = -EINVAL;
3372                 break;
3373         }
3374         return ret;
3375 }
3376
3377 static int
3378 bnxt_parse_fdir_filter(struct bnxt *bp,
3379                        struct rte_eth_fdir_filter *fdir,
3380                        struct bnxt_filter_info *filter)
3381 {
3382         enum rte_fdir_mode fdir_mode =
3383                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3384         struct bnxt_vnic_info *vnic0, *vnic;
3385         struct bnxt_filter_info *filter1;
3386         uint32_t en = 0;
3387         int i;
3388
3389         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3390                 return -EINVAL;
3391
3392         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3393         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3394
3395         switch (fdir->input.flow_type) {
3396         case RTE_ETH_FLOW_IPV4:
3397         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3398                 /* FALLTHROUGH */
3399                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3400                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3401                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3402                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3403                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3404                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3405                 filter->ip_addr_type =
3406                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3407                 filter->src_ipaddr_mask[0] = 0xffffffff;
3408                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3409                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3410                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3411                 filter->ethertype = 0x800;
3412                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3413                 break;
3414         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3415                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3416                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3417                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3418                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3419                 filter->dst_port_mask = 0xffff;
3420                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3421                 filter->src_port_mask = 0xffff;
3422                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3423                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3424                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3425                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3426                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3427                 filter->ip_protocol = 6;
3428                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3429                 filter->ip_addr_type =
3430                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3431                 filter->src_ipaddr_mask[0] = 0xffffffff;
3432                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3433                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3434                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3435                 filter->ethertype = 0x800;
3436                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3437                 break;
3438         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3439                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3440                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3441                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3442                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3443                 filter->dst_port_mask = 0xffff;
3444                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3445                 filter->src_port_mask = 0xffff;
3446                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3447                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3448                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3449                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3450                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3451                 filter->ip_protocol = 17;
3452                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3453                 filter->ip_addr_type =
3454                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3455                 filter->src_ipaddr_mask[0] = 0xffffffff;
3456                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3457                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3458                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3459                 filter->ethertype = 0x800;
3460                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3461                 break;
3462         case RTE_ETH_FLOW_IPV6:
3463         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3464                 /* FALLTHROUGH */
3465                 filter->ip_addr_type =
3466                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3467                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3468                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3469                 rte_memcpy(filter->src_ipaddr,
3470                            fdir->input.flow.ipv6_flow.src_ip, 16);
3471                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3472                 rte_memcpy(filter->dst_ipaddr,
3473                            fdir->input.flow.ipv6_flow.dst_ip, 16);
3474                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3475                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3476                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3477                 memset(filter->src_ipaddr_mask, 0xff, 16);
3478                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3479                 filter->ethertype = 0x86dd;
3480                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3481                 break;
3482         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3483                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3484                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3485                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3486                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3487                 filter->dst_port_mask = 0xffff;
3488                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3489                 filter->src_port_mask = 0xffff;
3490                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3491                 filter->ip_addr_type =
3492                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3493                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3494                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3495                 rte_memcpy(filter->src_ipaddr,
3496                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3497                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3498                 rte_memcpy(filter->dst_ipaddr,
3499                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3500                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3501                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3502                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3503                 memset(filter->src_ipaddr_mask, 0xff, 16);
3504                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3505                 filter->ethertype = 0x86dd;
3506                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3507                 break;
3508         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3509                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3510                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3511                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3512                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3513                 filter->dst_port_mask = 0xffff;
3514                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3515                 filter->src_port_mask = 0xffff;
3516                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3517                 filter->ip_addr_type =
3518                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3519                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3520                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3521                 rte_memcpy(filter->src_ipaddr,
3522                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3523                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3524                 rte_memcpy(filter->dst_ipaddr,
3525                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3526                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3527                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3528                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3529                 memset(filter->src_ipaddr_mask, 0xff, 16);
3530                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3531                 filter->ethertype = 0x86dd;
3532                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3533                 break;
3534         case RTE_ETH_FLOW_L2_PAYLOAD:
3535                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3536                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3537                 break;
3538         case RTE_ETH_FLOW_VXLAN:
3539                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3540                         return -EINVAL;
3541                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3542                 filter->tunnel_type =
3543                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3544                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3545                 break;
3546         case RTE_ETH_FLOW_NVGRE:
3547                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3548                         return -EINVAL;
3549                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3550                 filter->tunnel_type =
3551                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3552                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3553                 break;
3554         case RTE_ETH_FLOW_UNKNOWN:
3555         case RTE_ETH_FLOW_RAW:
3556         case RTE_ETH_FLOW_FRAG_IPV4:
3557         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3558         case RTE_ETH_FLOW_FRAG_IPV6:
3559         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3560         case RTE_ETH_FLOW_IPV6_EX:
3561         case RTE_ETH_FLOW_IPV6_TCP_EX:
3562         case RTE_ETH_FLOW_IPV6_UDP_EX:
3563         case RTE_ETH_FLOW_GENEVE:
3564                 /* FALLTHROUGH */
3565         default:
3566                 return -EINVAL;
3567         }
3568
3569         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3570         vnic = &bp->vnic_info[fdir->action.rx_queue];
3571         if (vnic == NULL) {
3572                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3573                 return -EINVAL;
3574         }
3575
3576         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3577                 rte_memcpy(filter->dst_macaddr,
3578                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3579                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3580         }
3581
3582         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3583                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3584                 filter1 = STAILQ_FIRST(&vnic0->filter);
3585                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3586         } else {
3587                 filter->dst_id = vnic->fw_vnic_id;
3588                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3589                         if (filter->dst_macaddr[i] == 0x00)
3590                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3591                         else
3592                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3593         }
3594
3595         if (filter1 == NULL)
3596                 return -EINVAL;
3597
3598         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3599         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3600
3601         filter->enables = en;
3602
3603         return 0;
3604 }
3605
3606 static struct bnxt_filter_info *
3607 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3608                 struct bnxt_vnic_info **mvnic)
3609 {
3610         struct bnxt_filter_info *mf = NULL;
3611         int i;
3612
3613         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3614                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3615
3616                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3617                         if (mf->filter_type == nf->filter_type &&
3618                             mf->flags == nf->flags &&
3619                             mf->src_port == nf->src_port &&
3620                             mf->src_port_mask == nf->src_port_mask &&
3621                             mf->dst_port == nf->dst_port &&
3622                             mf->dst_port_mask == nf->dst_port_mask &&
3623                             mf->ip_protocol == nf->ip_protocol &&
3624                             mf->ip_addr_type == nf->ip_addr_type &&
3625                             mf->ethertype == nf->ethertype &&
3626                             mf->vni == nf->vni &&
3627                             mf->tunnel_type == nf->tunnel_type &&
3628                             mf->l2_ovlan == nf->l2_ovlan &&
3629                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3630                             mf->l2_ivlan == nf->l2_ivlan &&
3631                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3632                             !memcmp(mf->l2_addr, nf->l2_addr,
3633                                     RTE_ETHER_ADDR_LEN) &&
3634                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3635                                     RTE_ETHER_ADDR_LEN) &&
3636                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3637                                     RTE_ETHER_ADDR_LEN) &&
3638                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3639                                     RTE_ETHER_ADDR_LEN) &&
3640                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3641                                     sizeof(nf->src_ipaddr)) &&
3642                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3643                                     sizeof(nf->src_ipaddr_mask)) &&
3644                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3645                                     sizeof(nf->dst_ipaddr)) &&
3646                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3647                                     sizeof(nf->dst_ipaddr_mask))) {
3648                                 if (mvnic)
3649                                         *mvnic = vnic;
3650                                 return mf;
3651                         }
3652                 }
3653         }
3654         return NULL;
3655 }
3656
3657 static int
3658 bnxt_fdir_filter(struct rte_eth_dev *dev,
3659                  enum rte_filter_op filter_op,
3660                  void *arg)
3661 {
3662         struct bnxt *bp = dev->data->dev_private;
3663         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3664         struct bnxt_filter_info *filter, *match;
3665         struct bnxt_vnic_info *vnic, *mvnic;
3666         int ret = 0, i;
3667
3668         if (filter_op == RTE_ETH_FILTER_NOP)
3669                 return 0;
3670
3671         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3672                 return -EINVAL;
3673
3674         switch (filter_op) {
3675         case RTE_ETH_FILTER_ADD:
3676         case RTE_ETH_FILTER_DELETE:
3677                 /* FALLTHROUGH */
3678                 filter = bnxt_get_unused_filter(bp);
3679                 if (filter == NULL) {
3680                         PMD_DRV_LOG(ERR,
3681                                 "Not enough resources for a new flow.\n");
3682                         return -ENOMEM;
3683                 }
3684
3685                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3686                 if (ret != 0)
3687                         goto free_filter;
3688                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3689
3690                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3691                         vnic = &bp->vnic_info[0];
3692                 else
3693                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3694
3695                 match = bnxt_match_fdir(bp, filter, &mvnic);
3696                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3697                         if (match->dst_id == vnic->fw_vnic_id) {
3698                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3699                                 ret = -EEXIST;
3700                                 goto free_filter;
3701                         } else {
3702                                 match->dst_id = vnic->fw_vnic_id;
3703                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3704                                                                   match->dst_id,
3705                                                                   match);
3706                                 STAILQ_REMOVE(&mvnic->filter, match,
3707                                               bnxt_filter_info, next);
3708                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3709                                 PMD_DRV_LOG(ERR,
3710                                         "Filter with matching pattern exist\n");
3711                                 PMD_DRV_LOG(ERR,
3712                                         "Updated it to new destination q\n");
3713                                 goto free_filter;
3714                         }
3715                 }
3716                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3717                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3718                         ret = -ENOENT;
3719                         goto free_filter;
3720                 }
3721
3722                 if (filter_op == RTE_ETH_FILTER_ADD) {
3723                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3724                                                           filter->dst_id,
3725                                                           filter);
3726                         if (ret)
3727                                 goto free_filter;
3728                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3729                 } else {
3730                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3731                         STAILQ_REMOVE(&vnic->filter, match,
3732                                       bnxt_filter_info, next);
3733                         bnxt_free_filter(bp, match);
3734                         bnxt_free_filter(bp, filter);
3735                 }
3736                 break;
3737         case RTE_ETH_FILTER_FLUSH:
3738                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3739                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3740
3741                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3742                                 if (filter->filter_type ==
3743                                     HWRM_CFA_NTUPLE_FILTER) {
3744                                         ret =
3745                                         bnxt_hwrm_clear_ntuple_filter(bp,
3746                                                                       filter);
3747                                         STAILQ_REMOVE(&vnic->filter, filter,
3748                                                       bnxt_filter_info, next);
3749                                 }
3750                         }
3751                 }
3752                 return ret;
3753         case RTE_ETH_FILTER_UPDATE:
3754         case RTE_ETH_FILTER_STATS:
3755         case RTE_ETH_FILTER_INFO:
3756                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3757                 break;
3758         default:
3759                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3760                 ret = -EINVAL;
3761                 break;
3762         }
3763         return ret;
3764
3765 free_filter:
3766         bnxt_free_filter(bp, filter);
3767         return ret;
3768 }
3769
3770 int
3771 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3772                     enum rte_filter_type filter_type,
3773                     enum rte_filter_op filter_op, void *arg)
3774 {
3775         struct bnxt *bp = dev->data->dev_private;
3776         int ret = 0;
3777
3778         if (!bp)
3779                 return -EIO;
3780
3781         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3782                 struct bnxt_representor *vfr = dev->data->dev_private;
3783                 bp = vfr->parent_dev->data->dev_private;
3784                 /* parent is deleted while children are still valid */
3785                 if (!bp) {
3786                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n",
3787                                     dev->data->port_id,
3788                                     filter_type,
3789                                     filter_op);
3790                         return -EIO;
3791                 }
3792         }
3793
3794         ret = is_bnxt_in_error(bp);
3795         if (ret)
3796                 return ret;
3797
3798         switch (filter_type) {
3799         case RTE_ETH_FILTER_TUNNEL:
3800                 PMD_DRV_LOG(ERR,
3801                         "filter type: %d: To be implemented\n", filter_type);
3802                 break;
3803         case RTE_ETH_FILTER_FDIR:
3804                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3805                 break;
3806         case RTE_ETH_FILTER_NTUPLE:
3807                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3808                 break;
3809         case RTE_ETH_FILTER_ETHERTYPE:
3810                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3811                 break;
3812         case RTE_ETH_FILTER_GENERIC:
3813                 if (filter_op != RTE_ETH_FILTER_GET)
3814                         return -EINVAL;
3815                 if (BNXT_TRUFLOW_EN(bp))
3816                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3817                 else
3818                         *(const void **)arg = &bnxt_flow_ops;
3819                 break;
3820         default:
3821                 PMD_DRV_LOG(ERR,
3822                         "Filter type (%d) not supported", filter_type);
3823                 ret = -EINVAL;
3824                 break;
3825         }
3826         return ret;
3827 }
3828
3829 static const uint32_t *
3830 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3831 {
3832         static const uint32_t ptypes[] = {
3833                 RTE_PTYPE_L2_ETHER_VLAN,
3834                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3835                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3836                 RTE_PTYPE_L4_ICMP,
3837                 RTE_PTYPE_L4_TCP,
3838                 RTE_PTYPE_L4_UDP,
3839                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3840                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3841                 RTE_PTYPE_INNER_L4_ICMP,
3842                 RTE_PTYPE_INNER_L4_TCP,
3843                 RTE_PTYPE_INNER_L4_UDP,
3844                 RTE_PTYPE_UNKNOWN
3845         };
3846
3847         if (!dev->rx_pkt_burst)
3848                 return NULL;
3849
3850         return ptypes;
3851 }
3852
3853 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3854                          int reg_win)
3855 {
3856         uint32_t reg_base = *reg_arr & 0xfffff000;
3857         uint32_t win_off;
3858         int i;
3859
3860         for (i = 0; i < count; i++) {
3861                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3862                         return -ERANGE;
3863         }
3864         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3865         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3866         return 0;
3867 }
3868
3869 static int bnxt_map_ptp_regs(struct bnxt *bp)
3870 {
3871         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3872         uint32_t *reg_arr;
3873         int rc, i;
3874
3875         reg_arr = ptp->rx_regs;
3876         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3877         if (rc)
3878                 return rc;
3879
3880         reg_arr = ptp->tx_regs;
3881         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3882         if (rc)
3883                 return rc;
3884
3885         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3886                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3887
3888         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3889                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3890
3891         return 0;
3892 }
3893
3894 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3895 {
3896         rte_write32(0, (uint8_t *)bp->bar0 +
3897                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3898         rte_write32(0, (uint8_t *)bp->bar0 +
3899                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3900 }
3901
3902 static uint64_t bnxt_cc_read(struct bnxt *bp)
3903 {
3904         uint64_t ns;
3905
3906         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3907                               BNXT_GRCPF_REG_SYNC_TIME));
3908         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3909                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3910         return ns;
3911 }
3912
3913 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3914 {
3915         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3916         uint32_t fifo;
3917
3918         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3919                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3920         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3921                 return -EAGAIN;
3922
3923         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3924                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3925         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3926                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3927         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3928                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3929
3930         return 0;
3931 }
3932
3933 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3934 {
3935         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3936         struct bnxt_pf_info *pf = bp->pf;
3937         uint16_t port_id;
3938         uint32_t fifo;
3939
3940         if (!ptp)
3941                 return -ENODEV;
3942
3943         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3944                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3945         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3946                 return -EAGAIN;
3947
3948         port_id = pf->port_id;
3949         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3950                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3951
3952         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3953                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3954         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3955 /*              bnxt_clr_rx_ts(bp);       TBD  */
3956                 return -EBUSY;
3957         }
3958
3959         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3960                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3961         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3962                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3963
3964         return 0;
3965 }
3966
3967 static int
3968 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3969 {
3970         uint64_t ns;
3971         struct bnxt *bp = dev->data->dev_private;
3972         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3973
3974         if (!ptp)
3975                 return 0;
3976
3977         ns = rte_timespec_to_ns(ts);
3978         /* Set the timecounters to a new value. */
3979         ptp->tc.nsec = ns;
3980
3981         return 0;
3982 }
3983
3984 static int
3985 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3986 {
3987         struct bnxt *bp = dev->data->dev_private;
3988         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3989         uint64_t ns, systime_cycles = 0;
3990         int rc = 0;
3991
3992         if (!ptp)
3993                 return 0;
3994
3995         if (BNXT_CHIP_THOR(bp))
3996                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3997                                              &systime_cycles);
3998         else
3999                 systime_cycles = bnxt_cc_read(bp);
4000
4001         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
4002         *ts = rte_ns_to_timespec(ns);
4003
4004         return rc;
4005 }
4006 static int
4007 bnxt_timesync_enable(struct rte_eth_dev *dev)
4008 {
4009         struct bnxt *bp = dev->data->dev_private;
4010         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4011         uint32_t shift = 0;
4012         int rc;
4013
4014         if (!ptp)
4015                 return 0;
4016
4017         ptp->rx_filter = 1;
4018         ptp->tx_tstamp_en = 1;
4019         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
4020
4021         rc = bnxt_hwrm_ptp_cfg(bp);
4022         if (rc)
4023                 return rc;
4024
4025         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
4026         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4027         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4028
4029         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4030         ptp->tc.cc_shift = shift;
4031         ptp->tc.nsec_mask = (1ULL << shift) - 1;
4032
4033         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4034         ptp->rx_tstamp_tc.cc_shift = shift;
4035         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4036
4037         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4038         ptp->tx_tstamp_tc.cc_shift = shift;
4039         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4040
4041         if (!BNXT_CHIP_THOR(bp))
4042                 bnxt_map_ptp_regs(bp);
4043
4044         return 0;
4045 }
4046
4047 static int
4048 bnxt_timesync_disable(struct rte_eth_dev *dev)
4049 {
4050         struct bnxt *bp = dev->data->dev_private;
4051         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4052
4053         if (!ptp)
4054                 return 0;
4055
4056         ptp->rx_filter = 0;
4057         ptp->tx_tstamp_en = 0;
4058         ptp->rxctl = 0;
4059
4060         bnxt_hwrm_ptp_cfg(bp);
4061
4062         if (!BNXT_CHIP_THOR(bp))
4063                 bnxt_unmap_ptp_regs(bp);
4064
4065         return 0;
4066 }
4067
4068 static int
4069 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4070                                  struct timespec *timestamp,
4071                                  uint32_t flags __rte_unused)
4072 {
4073         struct bnxt *bp = dev->data->dev_private;
4074         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4075         uint64_t rx_tstamp_cycles = 0;
4076         uint64_t ns;
4077
4078         if (!ptp)
4079                 return 0;
4080
4081         if (BNXT_CHIP_THOR(bp))
4082                 rx_tstamp_cycles = ptp->rx_timestamp;
4083         else
4084                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
4085
4086         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
4087         *timestamp = rte_ns_to_timespec(ns);
4088         return  0;
4089 }
4090
4091 static int
4092 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4093                                  struct timespec *timestamp)
4094 {
4095         struct bnxt *bp = dev->data->dev_private;
4096         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4097         uint64_t tx_tstamp_cycles = 0;
4098         uint64_t ns;
4099         int rc = 0;
4100
4101         if (!ptp)
4102                 return 0;
4103
4104         if (BNXT_CHIP_THOR(bp))
4105                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
4106                                              &tx_tstamp_cycles);
4107         else
4108                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
4109
4110         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
4111         *timestamp = rte_ns_to_timespec(ns);
4112
4113         return rc;
4114 }
4115
4116 static int
4117 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4118 {
4119         struct bnxt *bp = dev->data->dev_private;
4120         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4121
4122         if (!ptp)
4123                 return 0;
4124
4125         ptp->tc.nsec += delta;
4126
4127         return 0;
4128 }
4129
4130 static int
4131 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
4132 {
4133         struct bnxt *bp = dev->data->dev_private;
4134         int rc;
4135         uint32_t dir_entries;
4136         uint32_t entry_length;
4137
4138         rc = is_bnxt_in_error(bp);
4139         if (rc)
4140                 return rc;
4141
4142         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
4143                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4144                     bp->pdev->addr.devid, bp->pdev->addr.function);
4145
4146         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4147         if (rc != 0)
4148                 return rc;
4149
4150         return dir_entries * entry_length;
4151 }
4152
4153 static int
4154 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
4155                 struct rte_dev_eeprom_info *in_eeprom)
4156 {
4157         struct bnxt *bp = dev->data->dev_private;
4158         uint32_t index;
4159         uint32_t offset;
4160         int rc;
4161
4162         rc = is_bnxt_in_error(bp);
4163         if (rc)
4164                 return rc;
4165
4166         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4167                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4168                     bp->pdev->addr.devid, bp->pdev->addr.function,
4169                     in_eeprom->offset, in_eeprom->length);
4170
4171         if (in_eeprom->offset == 0) /* special offset value to get directory */
4172                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
4173                                                 in_eeprom->data);
4174
4175         index = in_eeprom->offset >> 24;
4176         offset = in_eeprom->offset & 0xffffff;
4177
4178         if (index != 0)
4179                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
4180                                            in_eeprom->length, in_eeprom->data);
4181
4182         return 0;
4183 }
4184
4185 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
4186 {
4187         switch (dir_type) {
4188         case BNX_DIR_TYPE_CHIMP_PATCH:
4189         case BNX_DIR_TYPE_BOOTCODE:
4190         case BNX_DIR_TYPE_BOOTCODE_2:
4191         case BNX_DIR_TYPE_APE_FW:
4192         case BNX_DIR_TYPE_APE_PATCH:
4193         case BNX_DIR_TYPE_KONG_FW:
4194         case BNX_DIR_TYPE_KONG_PATCH:
4195         case BNX_DIR_TYPE_BONO_FW:
4196         case BNX_DIR_TYPE_BONO_PATCH:
4197                 /* FALLTHROUGH */
4198                 return true;
4199         }
4200
4201         return false;
4202 }
4203
4204 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
4205 {
4206         switch (dir_type) {
4207         case BNX_DIR_TYPE_AVS:
4208         case BNX_DIR_TYPE_EXP_ROM_MBA:
4209         case BNX_DIR_TYPE_PCIE:
4210         case BNX_DIR_TYPE_TSCF_UCODE:
4211         case BNX_DIR_TYPE_EXT_PHY:
4212         case BNX_DIR_TYPE_CCM:
4213         case BNX_DIR_TYPE_ISCSI_BOOT:
4214         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
4215         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
4216                 /* FALLTHROUGH */
4217                 return true;
4218         }
4219
4220         return false;
4221 }
4222
4223 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
4224 {
4225         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
4226                 bnxt_dir_type_is_other_exec_format(dir_type);
4227 }
4228
4229 static int
4230 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
4231                 struct rte_dev_eeprom_info *in_eeprom)
4232 {
4233         struct bnxt *bp = dev->data->dev_private;
4234         uint8_t index, dir_op;
4235         uint16_t type, ext, ordinal, attr;
4236         int rc;
4237
4238         rc = is_bnxt_in_error(bp);
4239         if (rc)
4240                 return rc;
4241
4242         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4243                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4244                     bp->pdev->addr.devid, bp->pdev->addr.function,
4245                     in_eeprom->offset, in_eeprom->length);
4246
4247         if (!BNXT_PF(bp)) {
4248                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
4249                 return -EINVAL;
4250         }
4251
4252         type = in_eeprom->magic >> 16;
4253
4254         if (type == 0xffff) { /* special value for directory operations */
4255                 index = in_eeprom->magic & 0xff;
4256                 dir_op = in_eeprom->magic >> 8;
4257                 if (index == 0)
4258                         return -EINVAL;
4259                 switch (dir_op) {
4260                 case 0x0e: /* erase */
4261                         if (in_eeprom->offset != ~in_eeprom->magic)
4262                                 return -EINVAL;
4263                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
4264                 default:
4265                         return -EINVAL;
4266                 }
4267         }
4268
4269         /* Create or re-write an NVM item: */
4270         if (bnxt_dir_type_is_executable(type) == true)
4271                 return -EOPNOTSUPP;
4272         ext = in_eeprom->magic & 0xffff;
4273         ordinal = in_eeprom->offset >> 16;
4274         attr = in_eeprom->offset & 0xffff;
4275
4276         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
4277                                      in_eeprom->data, in_eeprom->length);
4278 }
4279
4280 /*
4281  * Initialization
4282  */
4283
4284 static const struct eth_dev_ops bnxt_dev_ops = {
4285         .dev_infos_get = bnxt_dev_info_get_op,
4286         .dev_close = bnxt_dev_close_op,
4287         .dev_configure = bnxt_dev_configure_op,
4288         .dev_start = bnxt_dev_start_op,
4289         .dev_stop = bnxt_dev_stop_op,
4290         .dev_set_link_up = bnxt_dev_set_link_up_op,
4291         .dev_set_link_down = bnxt_dev_set_link_down_op,
4292         .stats_get = bnxt_stats_get_op,
4293         .stats_reset = bnxt_stats_reset_op,
4294         .rx_queue_setup = bnxt_rx_queue_setup_op,
4295         .rx_queue_release = bnxt_rx_queue_release_op,
4296         .tx_queue_setup = bnxt_tx_queue_setup_op,
4297         .tx_queue_release = bnxt_tx_queue_release_op,
4298         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4299         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4300         .reta_update = bnxt_reta_update_op,
4301         .reta_query = bnxt_reta_query_op,
4302         .rss_hash_update = bnxt_rss_hash_update_op,
4303         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4304         .link_update = bnxt_link_update_op,
4305         .promiscuous_enable = bnxt_promiscuous_enable_op,
4306         .promiscuous_disable = bnxt_promiscuous_disable_op,
4307         .allmulticast_enable = bnxt_allmulticast_enable_op,
4308         .allmulticast_disable = bnxt_allmulticast_disable_op,
4309         .mac_addr_add = bnxt_mac_addr_add_op,
4310         .mac_addr_remove = bnxt_mac_addr_remove_op,
4311         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4312         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4313         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4314         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4315         .vlan_filter_set = bnxt_vlan_filter_set_op,
4316         .vlan_offload_set = bnxt_vlan_offload_set_op,
4317         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4318         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4319         .mtu_set = bnxt_mtu_set_op,
4320         .mac_addr_set = bnxt_set_default_mac_addr_op,
4321         .xstats_get = bnxt_dev_xstats_get_op,
4322         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4323         .xstats_reset = bnxt_dev_xstats_reset_op,
4324         .fw_version_get = bnxt_fw_version_get,
4325         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4326         .rxq_info_get = bnxt_rxq_info_get_op,
4327         .txq_info_get = bnxt_txq_info_get_op,
4328         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4329         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4330         .dev_led_on = bnxt_dev_led_on_op,
4331         .dev_led_off = bnxt_dev_led_off_op,
4332         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4333         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4334         .rx_queue_start = bnxt_rx_queue_start,
4335         .rx_queue_stop = bnxt_rx_queue_stop,
4336         .tx_queue_start = bnxt_tx_queue_start,
4337         .tx_queue_stop = bnxt_tx_queue_stop,
4338         .filter_ctrl = bnxt_filter_ctrl_op,
4339         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4340         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4341         .get_eeprom           = bnxt_get_eeprom_op,
4342         .set_eeprom           = bnxt_set_eeprom_op,
4343         .timesync_enable      = bnxt_timesync_enable,
4344         .timesync_disable     = bnxt_timesync_disable,
4345         .timesync_read_time   = bnxt_timesync_read_time,
4346         .timesync_write_time   = bnxt_timesync_write_time,
4347         .timesync_adjust_time = bnxt_timesync_adjust_time,
4348         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4349         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4350 };
4351
4352 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4353 {
4354         uint32_t offset;
4355
4356         /* Only pre-map the reset GRC registers using window 3 */
4357         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4358                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4359
4360         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4361
4362         return offset;
4363 }
4364
4365 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4366 {
4367         struct bnxt_error_recovery_info *info = bp->recovery_info;
4368         uint32_t reg_base = 0xffffffff;
4369         int i;
4370
4371         /* Only pre-map the monitoring GRC registers using window 2 */
4372         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4373                 uint32_t reg = info->status_regs[i];
4374
4375                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4376                         continue;
4377
4378                 if (reg_base == 0xffffffff)
4379                         reg_base = reg & 0xfffff000;
4380                 if ((reg & 0xfffff000) != reg_base)
4381                         return -ERANGE;
4382
4383                 /* Use mask 0xffc as the Lower 2 bits indicates
4384                  * address space location
4385                  */
4386                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4387                                                 (reg & 0xffc);
4388         }
4389
4390         if (reg_base == 0xffffffff)
4391                 return 0;
4392
4393         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4394                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4395
4396         return 0;
4397 }
4398
4399 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4400 {
4401         struct bnxt_error_recovery_info *info = bp->recovery_info;
4402         uint32_t delay = info->delay_after_reset[index];
4403         uint32_t val = info->reset_reg_val[index];
4404         uint32_t reg = info->reset_reg[index];
4405         uint32_t type, offset;
4406
4407         type = BNXT_FW_STATUS_REG_TYPE(reg);
4408         offset = BNXT_FW_STATUS_REG_OFF(reg);
4409
4410         switch (type) {
4411         case BNXT_FW_STATUS_REG_TYPE_CFG:
4412                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4413                 break;
4414         case BNXT_FW_STATUS_REG_TYPE_GRC:
4415                 offset = bnxt_map_reset_regs(bp, offset);
4416                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4417                 break;
4418         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4419                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4420                 break;
4421         }
4422         /* wait on a specific interval of time until core reset is complete */
4423         if (delay)
4424                 rte_delay_ms(delay);
4425 }
4426
4427 static void bnxt_dev_cleanup(struct bnxt *bp)
4428 {
4429         bp->eth_dev->data->dev_link.link_status = 0;
4430         bp->link_info->link_up = 0;
4431         if (bp->eth_dev->data->dev_started)
4432                 bnxt_dev_stop_op(bp->eth_dev);
4433
4434         bnxt_uninit_resources(bp, true);
4435 }
4436
4437 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4438 {
4439         struct rte_eth_dev *dev = bp->eth_dev;
4440         struct rte_vlan_filter_conf *vfc;
4441         int vidx, vbit, rc;
4442         uint16_t vlan_id;
4443
4444         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4445                 vfc = &dev->data->vlan_filter_conf;
4446                 vidx = vlan_id / 64;
4447                 vbit = vlan_id % 64;
4448
4449                 /* Each bit corresponds to a VLAN id */
4450                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4451                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4452                         if (rc)
4453                                 return rc;
4454                 }
4455         }
4456
4457         return 0;
4458 }
4459
4460 static int bnxt_restore_mac_filters(struct bnxt *bp)
4461 {
4462         struct rte_eth_dev *dev = bp->eth_dev;
4463         struct rte_eth_dev_info dev_info;
4464         struct rte_ether_addr *addr;
4465         uint64_t pool_mask;
4466         uint32_t pool = 0;
4467         uint16_t i;
4468         int rc;
4469
4470         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4471                 return 0;
4472
4473         rc = bnxt_dev_info_get_op(dev, &dev_info);
4474         if (rc)
4475                 return rc;
4476
4477         /* replay MAC address configuration */
4478         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4479                 addr = &dev->data->mac_addrs[i];
4480
4481                 /* skip zero address */
4482                 if (rte_is_zero_ether_addr(addr))
4483                         continue;
4484
4485                 pool = 0;
4486                 pool_mask = dev->data->mac_pool_sel[i];
4487
4488                 do {
4489                         if (pool_mask & 1ULL) {
4490                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4491                                 if (rc)
4492                                         return rc;
4493                         }
4494                         pool_mask >>= 1;
4495                         pool++;
4496                 } while (pool_mask);
4497         }
4498
4499         return 0;
4500 }
4501
4502 static int bnxt_restore_filters(struct bnxt *bp)
4503 {
4504         struct rte_eth_dev *dev = bp->eth_dev;
4505         int ret = 0;
4506
4507         if (dev->data->all_multicast) {
4508                 ret = bnxt_allmulticast_enable_op(dev);
4509                 if (ret)
4510                         return ret;
4511         }
4512         if (dev->data->promiscuous) {
4513                 ret = bnxt_promiscuous_enable_op(dev);
4514                 if (ret)
4515                         return ret;
4516         }
4517
4518         ret = bnxt_restore_mac_filters(bp);
4519         if (ret)
4520                 return ret;
4521
4522         ret = bnxt_restore_vlan_filters(bp);
4523         /* TODO restore other filters as well */
4524         return ret;
4525 }
4526
4527 static void bnxt_dev_recover(void *arg)
4528 {
4529         struct bnxt *bp = arg;
4530         int timeout = bp->fw_reset_max_msecs;
4531         int rc = 0;
4532
4533         /* Clear Error flag so that device re-init should happen */
4534         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4535
4536         do {
4537                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4538                 if (rc == 0)
4539                         break;
4540                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4541                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4542         } while (rc && timeout);
4543
4544         if (rc) {
4545                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4546                 goto err;
4547         }
4548
4549         rc = bnxt_init_resources(bp, true);
4550         if (rc) {
4551                 PMD_DRV_LOG(ERR,
4552                             "Failed to initialize resources after reset\n");
4553                 goto err;
4554         }
4555         /* clear reset flag as the device is initialized now */
4556         bp->flags &= ~BNXT_FLAG_FW_RESET;
4557
4558         rc = bnxt_dev_start_op(bp->eth_dev);
4559         if (rc) {
4560                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4561                 goto err_start;
4562         }
4563
4564         rc = bnxt_restore_filters(bp);
4565         if (rc)
4566                 goto err_start;
4567
4568         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4569         return;
4570 err_start:
4571         bnxt_dev_stop_op(bp->eth_dev);
4572 err:
4573         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4574         bnxt_uninit_resources(bp, false);
4575         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4576 }
4577
4578 void bnxt_dev_reset_and_resume(void *arg)
4579 {
4580         struct bnxt *bp = arg;
4581         int rc;
4582
4583         bnxt_dev_cleanup(bp);
4584
4585         bnxt_wait_for_device_shutdown(bp);
4586
4587         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4588                                bnxt_dev_recover, (void *)bp);
4589         if (rc)
4590                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4591 }
4592
4593 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4594 {
4595         struct bnxt_error_recovery_info *info = bp->recovery_info;
4596         uint32_t reg = info->status_regs[index];
4597         uint32_t type, offset, val = 0;
4598
4599         type = BNXT_FW_STATUS_REG_TYPE(reg);
4600         offset = BNXT_FW_STATUS_REG_OFF(reg);
4601
4602         switch (type) {
4603         case BNXT_FW_STATUS_REG_TYPE_CFG:
4604                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4605                 break;
4606         case BNXT_FW_STATUS_REG_TYPE_GRC:
4607                 offset = info->mapped_status_regs[index];
4608                 /* FALLTHROUGH */
4609         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4610                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4611                                        offset));
4612                 break;
4613         }
4614
4615         return val;
4616 }
4617
4618 static int bnxt_fw_reset_all(struct bnxt *bp)
4619 {
4620         struct bnxt_error_recovery_info *info = bp->recovery_info;
4621         uint32_t i;
4622         int rc = 0;
4623
4624         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4625                 /* Reset through master function driver */
4626                 for (i = 0; i < info->reg_array_cnt; i++)
4627                         bnxt_write_fw_reset_reg(bp, i);
4628                 /* Wait for time specified by FW after triggering reset */
4629                 rte_delay_ms(info->master_func_wait_period_after_reset);
4630         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4631                 /* Reset with the help of Kong processor */
4632                 rc = bnxt_hwrm_fw_reset(bp);
4633                 if (rc)
4634                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4635         }
4636
4637         return rc;
4638 }
4639
4640 static void bnxt_fw_reset_cb(void *arg)
4641 {
4642         struct bnxt *bp = arg;
4643         struct bnxt_error_recovery_info *info = bp->recovery_info;
4644         int rc = 0;
4645
4646         /* Only Master function can do FW reset */
4647         if (bnxt_is_master_func(bp) &&
4648             bnxt_is_recovery_enabled(bp)) {
4649                 rc = bnxt_fw_reset_all(bp);
4650                 if (rc) {
4651                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4652                         return;
4653                 }
4654         }
4655
4656         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4657          * EXCEPTION_FATAL_ASYNC event to all the functions
4658          * (including MASTER FUNC). After receiving this Async, all the active
4659          * drivers should treat this case as FW initiated recovery
4660          */
4661         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4662                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4663                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4664
4665                 /* To recover from error */
4666                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4667                                   (void *)bp);
4668         }
4669 }
4670
4671 /* Driver should poll FW heartbeat, reset_counter with the frequency
4672  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4673  * When the driver detects heartbeat stop or change in reset_counter,
4674  * it has to trigger a reset to recover from the error condition.
4675  * A “master PF” is the function who will have the privilege to
4676  * initiate the chimp reset. The master PF will be elected by the
4677  * firmware and will be notified through async message.
4678  */
4679 static void bnxt_check_fw_health(void *arg)
4680 {
4681         struct bnxt *bp = arg;
4682         struct bnxt_error_recovery_info *info = bp->recovery_info;
4683         uint32_t val = 0, wait_msec;
4684
4685         if (!info || !bnxt_is_recovery_enabled(bp) ||
4686             is_bnxt_in_error(bp))
4687                 return;
4688
4689         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4690         if (val == info->last_heart_beat)
4691                 goto reset;
4692
4693         info->last_heart_beat = val;
4694
4695         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4696         if (val != info->last_reset_counter)
4697                 goto reset;
4698
4699         info->last_reset_counter = val;
4700
4701         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4702                           bnxt_check_fw_health, (void *)bp);
4703
4704         return;
4705 reset:
4706         /* Stop DMA to/from device */
4707         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4708         bp->flags |= BNXT_FLAG_FW_RESET;
4709
4710         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4711
4712         if (bnxt_is_master_func(bp))
4713                 wait_msec = info->master_func_wait_period;
4714         else
4715                 wait_msec = info->normal_func_wait_period;
4716
4717         rte_eal_alarm_set(US_PER_MS * wait_msec,
4718                           bnxt_fw_reset_cb, (void *)bp);
4719 }
4720
4721 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4722 {
4723         uint32_t polling_freq;
4724
4725         pthread_mutex_lock(&bp->health_check_lock);
4726
4727         if (!bnxt_is_recovery_enabled(bp))
4728                 goto done;
4729
4730         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4731                 goto done;
4732
4733         polling_freq = bp->recovery_info->driver_polling_freq;
4734
4735         rte_eal_alarm_set(US_PER_MS * polling_freq,
4736                           bnxt_check_fw_health, (void *)bp);
4737         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4738
4739 done:
4740         pthread_mutex_unlock(&bp->health_check_lock);
4741 }
4742
4743 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4744 {
4745         if (!bnxt_is_recovery_enabled(bp))
4746                 return;
4747
4748         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4749         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4750 }
4751
4752 static bool bnxt_vf_pciid(uint16_t device_id)
4753 {
4754         switch (device_id) {
4755         case BROADCOM_DEV_ID_57304_VF:
4756         case BROADCOM_DEV_ID_57406_VF:
4757         case BROADCOM_DEV_ID_5731X_VF:
4758         case BROADCOM_DEV_ID_5741X_VF:
4759         case BROADCOM_DEV_ID_57414_VF:
4760         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4761         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4762         case BROADCOM_DEV_ID_58802_VF:
4763         case BROADCOM_DEV_ID_57500_VF1:
4764         case BROADCOM_DEV_ID_57500_VF2:
4765                 /* FALLTHROUGH */
4766                 return true;
4767         default:
4768                 return false;
4769         }
4770 }
4771
4772 static bool bnxt_thor_device(uint16_t device_id)
4773 {
4774         switch (device_id) {
4775         case BROADCOM_DEV_ID_57508:
4776         case BROADCOM_DEV_ID_57504:
4777         case BROADCOM_DEV_ID_57502:
4778         case BROADCOM_DEV_ID_57508_MF1:
4779         case BROADCOM_DEV_ID_57504_MF1:
4780         case BROADCOM_DEV_ID_57502_MF1:
4781         case BROADCOM_DEV_ID_57508_MF2:
4782         case BROADCOM_DEV_ID_57504_MF2:
4783         case BROADCOM_DEV_ID_57502_MF2:
4784         case BROADCOM_DEV_ID_57500_VF1:
4785         case BROADCOM_DEV_ID_57500_VF2:
4786                 /* FALLTHROUGH */
4787                 return true;
4788         default:
4789                 return false;
4790         }
4791 }
4792
4793 bool bnxt_stratus_device(struct bnxt *bp)
4794 {
4795         uint16_t device_id = bp->pdev->id.device_id;
4796
4797         switch (device_id) {
4798         case BROADCOM_DEV_ID_STRATUS_NIC:
4799         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4800         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4801                 /* FALLTHROUGH */
4802                 return true;
4803         default:
4804                 return false;
4805         }
4806 }
4807
4808 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4809 {
4810         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4811         struct bnxt *bp = eth_dev->data->dev_private;
4812
4813         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4814         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4815         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4816         if (!bp->bar0 || !bp->doorbell_base) {
4817                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4818                 return -ENODEV;
4819         }
4820
4821         bp->eth_dev = eth_dev;
4822         bp->pdev = pci_dev;
4823
4824         return 0;
4825 }
4826
4827 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4828                                   struct bnxt_ctx_pg_info *ctx_pg,
4829                                   uint32_t mem_size,
4830                                   const char *suffix,
4831                                   uint16_t idx)
4832 {
4833         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4834         const struct rte_memzone *mz = NULL;
4835         char mz_name[RTE_MEMZONE_NAMESIZE];
4836         rte_iova_t mz_phys_addr;
4837         uint64_t valid_bits = 0;
4838         uint32_t sz;
4839         int i;
4840
4841         if (!mem_size)
4842                 return 0;
4843
4844         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4845                          BNXT_PAGE_SIZE;
4846         rmem->page_size = BNXT_PAGE_SIZE;
4847         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4848         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4849         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4850
4851         valid_bits = PTU_PTE_VALID;
4852
4853         if (rmem->nr_pages > 1) {
4854                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4855                          "bnxt_ctx_pg_tbl%s_%x_%d",
4856                          suffix, idx, bp->eth_dev->data->port_id);
4857                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4858                 mz = rte_memzone_lookup(mz_name);
4859                 if (!mz) {
4860                         mz = rte_memzone_reserve_aligned(mz_name,
4861                                                 rmem->nr_pages * 8,
4862                                                 SOCKET_ID_ANY,
4863                                                 RTE_MEMZONE_2MB |
4864                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4865                                                 RTE_MEMZONE_IOVA_CONTIG,
4866                                                 BNXT_PAGE_SIZE);
4867                         if (mz == NULL)
4868                                 return -ENOMEM;
4869                 }
4870
4871                 memset(mz->addr, 0, mz->len);
4872                 mz_phys_addr = mz->iova;
4873
4874                 rmem->pg_tbl = mz->addr;
4875                 rmem->pg_tbl_map = mz_phys_addr;
4876                 rmem->pg_tbl_mz = mz;
4877         }
4878
4879         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4880                  suffix, idx, bp->eth_dev->data->port_id);
4881         mz = rte_memzone_lookup(mz_name);
4882         if (!mz) {
4883                 mz = rte_memzone_reserve_aligned(mz_name,
4884                                                  mem_size,
4885                                                  SOCKET_ID_ANY,
4886                                                  RTE_MEMZONE_1GB |
4887                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4888                                                  RTE_MEMZONE_IOVA_CONTIG,
4889                                                  BNXT_PAGE_SIZE);
4890                 if (mz == NULL)
4891                         return -ENOMEM;
4892         }
4893
4894         memset(mz->addr, 0, mz->len);
4895         mz_phys_addr = mz->iova;
4896
4897         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4898                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4899                 rmem->dma_arr[i] = mz_phys_addr + sz;
4900
4901                 if (rmem->nr_pages > 1) {
4902                         if (i == rmem->nr_pages - 2 &&
4903                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4904                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4905                         else if (i == rmem->nr_pages - 1 &&
4906                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4907                                 valid_bits |= PTU_PTE_LAST;
4908
4909                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4910                                                            valid_bits);
4911                 }
4912         }
4913
4914         rmem->mz = mz;
4915         if (rmem->vmem_size)
4916                 rmem->vmem = (void **)mz->addr;
4917         rmem->dma_arr[0] = mz_phys_addr;
4918         return 0;
4919 }
4920
4921 static void bnxt_free_ctx_mem(struct bnxt *bp)
4922 {
4923         int i;
4924
4925         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4926                 return;
4927
4928         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4929         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4930         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4931         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4932         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4933         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4934         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4935         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4936         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4937         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4938         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4939
4940         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4941                 if (bp->ctx->tqm_mem[i])
4942                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4943         }
4944
4945         rte_free(bp->ctx);
4946         bp->ctx = NULL;
4947 }
4948
4949 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4950
4951 #define min_t(type, x, y) ({                    \
4952         type __min1 = (x);                      \
4953         type __min2 = (y);                      \
4954         __min1 < __min2 ? __min1 : __min2; })
4955
4956 #define max_t(type, x, y) ({                    \
4957         type __max1 = (x);                      \
4958         type __max2 = (y);                      \
4959         __max1 > __max2 ? __max1 : __max2; })
4960
4961 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4962
4963 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4964 {
4965         struct bnxt_ctx_pg_info *ctx_pg;
4966         struct bnxt_ctx_mem_info *ctx;
4967         uint32_t mem_size, ena, entries;
4968         uint32_t entries_sp, min;
4969         int i, rc;
4970
4971         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4972         if (rc) {
4973                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4974                 return rc;
4975         }
4976         ctx = bp->ctx;
4977         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4978                 return 0;
4979
4980         ctx_pg = &ctx->qp_mem;
4981         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4982         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4983         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4984         if (rc)
4985                 return rc;
4986
4987         ctx_pg = &ctx->srq_mem;
4988         ctx_pg->entries = ctx->srq_max_l2_entries;
4989         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4990         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4991         if (rc)
4992                 return rc;
4993
4994         ctx_pg = &ctx->cq_mem;
4995         ctx_pg->entries = ctx->cq_max_l2_entries;
4996         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4997         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4998         if (rc)
4999                 return rc;
5000
5001         ctx_pg = &ctx->vnic_mem;
5002         ctx_pg->entries = ctx->vnic_max_vnic_entries +
5003                 ctx->vnic_max_ring_table_entries;
5004         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
5005         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
5006         if (rc)
5007                 return rc;
5008
5009         ctx_pg = &ctx->stat_mem;
5010         ctx_pg->entries = ctx->stat_max_entries;
5011         mem_size = ctx->stat_entry_size * ctx_pg->entries;
5012         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
5013         if (rc)
5014                 return rc;
5015
5016         min = ctx->tqm_min_entries_per_ring;
5017
5018         entries_sp = ctx->qp_max_l2_entries +
5019                      ctx->vnic_max_vnic_entries +
5020                      2 * ctx->qp_min_qp1_entries + min;
5021         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
5022
5023         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
5024         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
5025         entries = clamp_t(uint32_t, entries, min,
5026                           ctx->tqm_max_entries_per_ring);
5027         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
5028                 ctx_pg = ctx->tqm_mem[i];
5029                 ctx_pg->entries = i ? entries : entries_sp;
5030                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
5031                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
5032                 if (rc)
5033                         return rc;
5034                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
5035         }
5036
5037         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
5038         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
5039         if (rc)
5040                 PMD_DRV_LOG(ERR,
5041                             "Failed to configure context mem: rc = %d\n", rc);
5042         else
5043                 ctx->flags |= BNXT_CTX_FLAG_INITED;
5044
5045         return rc;
5046 }
5047
5048 static int bnxt_alloc_stats_mem(struct bnxt *bp)
5049 {
5050         struct rte_pci_device *pci_dev = bp->pdev;
5051         char mz_name[RTE_MEMZONE_NAMESIZE];
5052         const struct rte_memzone *mz = NULL;
5053         uint32_t total_alloc_len;
5054         rte_iova_t mz_phys_addr;
5055
5056         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
5057                 return 0;
5058
5059         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5060                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5061                  pci_dev->addr.bus, pci_dev->addr.devid,
5062                  pci_dev->addr.function, "rx_port_stats");
5063         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5064         mz = rte_memzone_lookup(mz_name);
5065         total_alloc_len =
5066                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
5067                                        sizeof(struct rx_port_stats_ext) + 512);
5068         if (!mz) {
5069                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
5070                                          SOCKET_ID_ANY,
5071                                          RTE_MEMZONE_2MB |
5072                                          RTE_MEMZONE_SIZE_HINT_ONLY |
5073                                          RTE_MEMZONE_IOVA_CONTIG);
5074                 if (mz == NULL)
5075                         return -ENOMEM;
5076         }
5077         memset(mz->addr, 0, mz->len);
5078         mz_phys_addr = mz->iova;
5079
5080         bp->rx_mem_zone = (const void *)mz;
5081         bp->hw_rx_port_stats = mz->addr;
5082         bp->hw_rx_port_stats_map = mz_phys_addr;
5083
5084         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5085                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5086                  pci_dev->addr.bus, pci_dev->addr.devid,
5087                  pci_dev->addr.function, "tx_port_stats");
5088         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5089         mz = rte_memzone_lookup(mz_name);
5090         total_alloc_len =
5091                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
5092                                        sizeof(struct tx_port_stats_ext) + 512);
5093         if (!mz) {
5094                 mz = rte_memzone_reserve(mz_name,
5095                                          total_alloc_len,
5096                                          SOCKET_ID_ANY,
5097                                          RTE_MEMZONE_2MB |
5098                                          RTE_MEMZONE_SIZE_HINT_ONLY |
5099                                          RTE_MEMZONE_IOVA_CONTIG);
5100                 if (mz == NULL)
5101                         return -ENOMEM;
5102         }
5103         memset(mz->addr, 0, mz->len);
5104         mz_phys_addr = mz->iova;
5105
5106         bp->tx_mem_zone = (const void *)mz;
5107         bp->hw_tx_port_stats = mz->addr;
5108         bp->hw_tx_port_stats_map = mz_phys_addr;
5109         bp->flags |= BNXT_FLAG_PORT_STATS;
5110
5111         /* Display extended statistics if FW supports it */
5112         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
5113             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
5114             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
5115                 return 0;
5116
5117         bp->hw_rx_port_stats_ext = (void *)
5118                 ((uint8_t *)bp->hw_rx_port_stats +
5119                  sizeof(struct rx_port_stats));
5120         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
5121                 sizeof(struct rx_port_stats);
5122         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
5123
5124         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
5125             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
5126                 bp->hw_tx_port_stats_ext = (void *)
5127                         ((uint8_t *)bp->hw_tx_port_stats +
5128                          sizeof(struct tx_port_stats));
5129                 bp->hw_tx_port_stats_ext_map =
5130                         bp->hw_tx_port_stats_map +
5131                         sizeof(struct tx_port_stats);
5132                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
5133         }
5134
5135         return 0;
5136 }
5137
5138 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
5139 {
5140         struct bnxt *bp = eth_dev->data->dev_private;
5141         int rc = 0;
5142
5143         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
5144                                                RTE_ETHER_ADDR_LEN *
5145                                                bp->max_l2_ctx,
5146                                                0);
5147         if (eth_dev->data->mac_addrs == NULL) {
5148                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
5149                 return -ENOMEM;
5150         }
5151
5152         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
5153                 if (BNXT_PF(bp))
5154                         return -EINVAL;
5155
5156                 /* Generate a random MAC address, if none was assigned by PF */
5157                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5158                 bnxt_eth_hw_addr_random(bp->mac_addr);
5159                 PMD_DRV_LOG(INFO,
5160                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
5161                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5162                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5163
5164                 rc = bnxt_hwrm_set_mac(bp);
5165                 if (rc)
5166                         return rc;
5167         }
5168
5169         /* Copy the permanent MAC from the FUNC_QCAPS response */
5170         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5171
5172         return rc;
5173 }
5174
5175 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5176 {
5177         int rc = 0;
5178
5179         /* MAC is already configured in FW */
5180         if (BNXT_HAS_DFLT_MAC_SET(bp))
5181                 return 0;
5182
5183         /* Restore the old MAC configured */
5184         rc = bnxt_hwrm_set_mac(bp);
5185         if (rc)
5186                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5187
5188         return rc;
5189 }
5190
5191 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5192 {
5193         if (!BNXT_PF(bp))
5194                 return;
5195
5196 #define ALLOW_FUNC(x)   \
5197         { \
5198                 uint32_t arg = (x); \
5199                 bp->pf->vf_req_fwd[((arg) >> 5)] &= \
5200                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
5201         }
5202
5203         /* Forward all requests if firmware is new enough */
5204         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
5205              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
5206             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
5207                 memset(bp->pf->vf_req_fwd, 0xff, sizeof(bp->pf->vf_req_fwd));
5208         } else {
5209                 PMD_DRV_LOG(WARNING,
5210                             "Firmware too old for VF mailbox functionality\n");
5211                 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5212         }
5213
5214         /*
5215          * The following are used for driver cleanup. If we disallow these,
5216          * VF drivers can't clean up cleanly.
5217          */
5218         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
5219         ALLOW_FUNC(HWRM_VNIC_FREE);
5220         ALLOW_FUNC(HWRM_RING_FREE);
5221         ALLOW_FUNC(HWRM_RING_GRP_FREE);
5222         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
5223         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
5224         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
5225         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
5226         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
5227 }
5228
5229 uint16_t
5230 bnxt_get_svif(uint16_t port_id, bool func_svif,
5231               enum bnxt_ulp_intf_type type)
5232 {
5233         struct rte_eth_dev *eth_dev;
5234         struct bnxt *bp;
5235
5236         eth_dev = &rte_eth_devices[port_id];
5237         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5238                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5239                 if (!vfr)
5240                         return 0;
5241
5242                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5243                         return vfr->svif;
5244
5245                 eth_dev = vfr->parent_dev;
5246         }
5247
5248         bp = eth_dev->data->dev_private;
5249
5250         return func_svif ? bp->func_svif : bp->port_svif;
5251 }
5252
5253 uint16_t
5254 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5255 {
5256         struct rte_eth_dev *eth_dev;
5257         struct bnxt_vnic_info *vnic;
5258         struct bnxt *bp;
5259
5260         eth_dev = &rte_eth_devices[port];
5261         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5262                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5263                 if (!vfr)
5264                         return 0;
5265
5266                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5267                         return vfr->dflt_vnic_id;
5268
5269                 eth_dev = vfr->parent_dev;
5270         }
5271
5272         bp = eth_dev->data->dev_private;
5273
5274         vnic = BNXT_GET_DEFAULT_VNIC(bp);
5275
5276         return vnic->fw_vnic_id;
5277 }
5278
5279 uint16_t
5280 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5281 {
5282         struct rte_eth_dev *eth_dev;
5283         struct bnxt *bp;
5284
5285         eth_dev = &rte_eth_devices[port];
5286         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5287                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5288                 if (!vfr)
5289                         return 0;
5290
5291                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5292                         return vfr->fw_fid;
5293
5294                 eth_dev = vfr->parent_dev;
5295         }
5296
5297         bp = eth_dev->data->dev_private;
5298
5299         return bp->fw_fid;
5300 }
5301
5302 enum bnxt_ulp_intf_type
5303 bnxt_get_interface_type(uint16_t port)
5304 {
5305         struct rte_eth_dev *eth_dev;
5306         struct bnxt *bp;
5307
5308         eth_dev = &rte_eth_devices[port];
5309         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5310                 return BNXT_ULP_INTF_TYPE_VF_REP;
5311
5312         bp = eth_dev->data->dev_private;
5313         if (BNXT_PF(bp))
5314                 return BNXT_ULP_INTF_TYPE_PF;
5315         else if (BNXT_VF_IS_TRUSTED(bp))
5316                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5317         else if (BNXT_VF(bp))
5318                 return BNXT_ULP_INTF_TYPE_VF;
5319
5320         return BNXT_ULP_INTF_TYPE_INVALID;
5321 }
5322
5323 uint16_t
5324 bnxt_get_phy_port_id(uint16_t port_id)
5325 {
5326         struct bnxt_representor *vfr;
5327         struct rte_eth_dev *eth_dev;
5328         struct bnxt *bp;
5329
5330         eth_dev = &rte_eth_devices[port_id];
5331         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5332                 vfr = eth_dev->data->dev_private;
5333                 if (!vfr)
5334                         return 0;
5335
5336                 eth_dev = vfr->parent_dev;
5337         }
5338
5339         bp = eth_dev->data->dev_private;
5340
5341         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5342 }
5343
5344 uint16_t
5345 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5346 {
5347         struct rte_eth_dev *eth_dev;
5348         struct bnxt *bp;
5349
5350         eth_dev = &rte_eth_devices[port_id];
5351         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5352                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5353                 if (!vfr)
5354                         return 0;
5355
5356                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5357                         return vfr->fw_fid - 1;
5358
5359                 eth_dev = vfr->parent_dev;
5360         }
5361
5362         bp = eth_dev->data->dev_private;
5363
5364         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5365 }
5366
5367 uint16_t
5368 bnxt_get_vport(uint16_t port_id)
5369 {
5370         return (1 << bnxt_get_phy_port_id(port_id));
5371 }
5372
5373 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5374 {
5375         struct bnxt_error_recovery_info *info = bp->recovery_info;
5376
5377         if (info) {
5378                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5379                         memset(info, 0, sizeof(*info));
5380                 return;
5381         }
5382
5383         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5384                 return;
5385
5386         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5387                            sizeof(*info), 0);
5388         if (!info)
5389                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5390
5391         bp->recovery_info = info;
5392 }
5393
5394 static void bnxt_check_fw_status(struct bnxt *bp)
5395 {
5396         uint32_t fw_status;
5397
5398         if (!(bp->recovery_info &&
5399               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5400                 return;
5401
5402         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5403         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5404                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5405                             fw_status);
5406 }
5407
5408 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5409 {
5410         struct bnxt_error_recovery_info *info = bp->recovery_info;
5411         uint32_t status_loc;
5412         uint32_t sig_ver;
5413
5414         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5415                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5416         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5417                                    BNXT_GRCP_WINDOW_2_BASE +
5418                                    offsetof(struct hcomm_status,
5419                                             sig_ver)));
5420         /* If the signature is absent, then FW does not support this feature */
5421         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5422             HCOMM_STATUS_SIGNATURE_VAL)
5423                 return 0;
5424
5425         if (!info) {
5426                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5427                                    sizeof(*info), 0);
5428                 if (!info)
5429                         return -ENOMEM;
5430                 bp->recovery_info = info;
5431         } else {
5432                 memset(info, 0, sizeof(*info));
5433         }
5434
5435         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5436                                       BNXT_GRCP_WINDOW_2_BASE +
5437                                       offsetof(struct hcomm_status,
5438                                                fw_status_loc)));
5439
5440         /* Only pre-map the FW health status GRC register */
5441         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5442                 return 0;
5443
5444         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5445         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5446                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5447
5448         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5449                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5450
5451         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5452
5453         return 0;
5454 }
5455
5456 static int bnxt_init_fw(struct bnxt *bp)
5457 {
5458         uint16_t mtu;
5459         int rc = 0;
5460
5461         bp->fw_cap = 0;
5462
5463         rc = bnxt_map_hcomm_fw_status_reg(bp);
5464         if (rc)
5465                 return rc;
5466
5467         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5468         if (rc) {
5469                 bnxt_check_fw_status(bp);
5470                 return rc;
5471         }
5472
5473         rc = bnxt_hwrm_func_reset(bp);
5474         if (rc)
5475                 return -EIO;
5476
5477         rc = bnxt_hwrm_vnic_qcaps(bp);
5478         if (rc)
5479                 return rc;
5480
5481         rc = bnxt_hwrm_queue_qportcfg(bp);
5482         if (rc)
5483                 return rc;
5484
5485         /* Get the MAX capabilities for this function.
5486          * This function also allocates context memory for TQM rings and
5487          * informs the firmware about this allocated backing store memory.
5488          */
5489         rc = bnxt_hwrm_func_qcaps(bp);
5490         if (rc)
5491                 return rc;
5492
5493         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5494         if (rc)
5495                 return rc;
5496
5497         bnxt_hwrm_port_mac_qcfg(bp);
5498
5499         bnxt_hwrm_parent_pf_qcfg(bp);
5500
5501         bnxt_hwrm_port_phy_qcaps(bp);
5502
5503         bnxt_alloc_error_recovery_info(bp);
5504         /* Get the adapter error recovery support info */
5505         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5506         if (rc)
5507                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5508
5509         bnxt_hwrm_port_led_qcaps(bp);
5510
5511         return 0;
5512 }
5513
5514 static int
5515 bnxt_init_locks(struct bnxt *bp)
5516 {
5517         int err;
5518
5519         err = pthread_mutex_init(&bp->flow_lock, NULL);
5520         if (err) {
5521                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5522                 return err;
5523         }
5524
5525         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5526         if (err)
5527                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5528
5529         err = pthread_mutex_init(&bp->health_check_lock, NULL);
5530         if (err)
5531                 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5532         return err;
5533 }
5534
5535 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5536 {
5537         int rc = 0;
5538
5539         rc = bnxt_init_fw(bp);
5540         if (rc)
5541                 return rc;
5542
5543         if (!reconfig_dev) {
5544                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5545                 if (rc)
5546                         return rc;
5547         } else {
5548                 rc = bnxt_restore_dflt_mac(bp);
5549                 if (rc)
5550                         return rc;
5551         }
5552
5553         bnxt_config_vf_req_fwd(bp);
5554
5555         rc = bnxt_hwrm_func_driver_register(bp);
5556         if (rc) {
5557                 PMD_DRV_LOG(ERR, "Failed to register driver");
5558                 return -EBUSY;
5559         }
5560
5561         if (BNXT_PF(bp)) {
5562                 if (bp->pdev->max_vfs) {
5563                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5564                         if (rc) {
5565                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5566                                 return rc;
5567                         }
5568                 } else {
5569                         rc = bnxt_hwrm_allocate_pf_only(bp);
5570                         if (rc) {
5571                                 PMD_DRV_LOG(ERR,
5572                                             "Failed to allocate PF resources");
5573                                 return rc;
5574                         }
5575                 }
5576         }
5577
5578         rc = bnxt_alloc_mem(bp, reconfig_dev);
5579         if (rc)
5580                 return rc;
5581
5582         rc = bnxt_setup_int(bp);
5583         if (rc)
5584                 return rc;
5585
5586         rc = bnxt_request_int(bp);
5587         if (rc)
5588                 return rc;
5589
5590         rc = bnxt_init_ctx_mem(bp);
5591         if (rc) {
5592                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5593                 return rc;
5594         }
5595
5596         rc = bnxt_init_locks(bp);
5597         if (rc)
5598                 return rc;
5599
5600         return 0;
5601 }
5602
5603 static int
5604 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5605                           const char *value, void *opaque_arg)
5606 {
5607         struct bnxt *bp = opaque_arg;
5608         unsigned long truflow;
5609         char *end = NULL;
5610
5611         if (!value || !opaque_arg) {
5612                 PMD_DRV_LOG(ERR,
5613                             "Invalid parameter passed to truflow devargs.\n");
5614                 return -EINVAL;
5615         }
5616
5617         truflow = strtoul(value, &end, 10);
5618         if (end == NULL || *end != '\0' ||
5619             (truflow == ULONG_MAX && errno == ERANGE)) {
5620                 PMD_DRV_LOG(ERR,
5621                             "Invalid parameter passed to truflow devargs.\n");
5622                 return -EINVAL;
5623         }
5624
5625         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5626                 PMD_DRV_LOG(ERR,
5627                             "Invalid value passed to truflow devargs.\n");
5628                 return -EINVAL;
5629         }
5630
5631         if (truflow) {
5632                 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5633                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5634         } else {
5635                 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
5636                 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
5637         }
5638
5639         return 0;
5640 }
5641
5642 static int
5643 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5644                              const char *value, void *opaque_arg)
5645 {
5646         struct bnxt *bp = opaque_arg;
5647         unsigned long flow_xstat;
5648         char *end = NULL;
5649
5650         if (!value || !opaque_arg) {
5651                 PMD_DRV_LOG(ERR,
5652                             "Invalid parameter passed to flow_xstat devarg.\n");
5653                 return -EINVAL;
5654         }
5655
5656         flow_xstat = strtoul(value, &end, 10);
5657         if (end == NULL || *end != '\0' ||
5658             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5659                 PMD_DRV_LOG(ERR,
5660                             "Invalid parameter passed to flow_xstat devarg.\n");
5661                 return -EINVAL;
5662         }
5663
5664         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5665                 PMD_DRV_LOG(ERR,
5666                             "Invalid value passed to flow_xstat devarg.\n");
5667                 return -EINVAL;
5668         }
5669
5670         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5671         if (BNXT_FLOW_XSTATS_EN(bp))
5672                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5673
5674         return 0;
5675 }
5676
5677 static int
5678 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5679                                         const char *value, void *opaque_arg)
5680 {
5681         struct bnxt *bp = opaque_arg;
5682         unsigned long max_num_kflows;
5683         char *end = NULL;
5684
5685         if (!value || !opaque_arg) {
5686                 PMD_DRV_LOG(ERR,
5687                         "Invalid parameter passed to max_num_kflows devarg.\n");
5688                 return -EINVAL;
5689         }
5690
5691         max_num_kflows = strtoul(value, &end, 10);
5692         if (end == NULL || *end != '\0' ||
5693                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5694                 PMD_DRV_LOG(ERR,
5695                         "Invalid parameter passed to max_num_kflows devarg.\n");
5696                 return -EINVAL;
5697         }
5698
5699         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5700                 PMD_DRV_LOG(ERR,
5701                         "Invalid value passed to max_num_kflows devarg.\n");
5702                 return -EINVAL;
5703         }
5704
5705         bp->max_num_kflows = max_num_kflows;
5706         if (bp->max_num_kflows)
5707                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5708                                 max_num_kflows);
5709
5710         return 0;
5711 }
5712
5713 static int
5714 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5715                             const char *value, void *opaque_arg)
5716 {
5717         struct bnxt_representor *vfr_bp = opaque_arg;
5718         unsigned long rep_is_pf;
5719         char *end = NULL;
5720
5721         if (!value || !opaque_arg) {
5722                 PMD_DRV_LOG(ERR,
5723                             "Invalid parameter passed to rep_is_pf devargs.\n");
5724                 return -EINVAL;
5725         }
5726
5727         rep_is_pf = strtoul(value, &end, 10);
5728         if (end == NULL || *end != '\0' ||
5729             (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5730                 PMD_DRV_LOG(ERR,
5731                             "Invalid parameter passed to rep_is_pf devargs.\n");
5732                 return -EINVAL;
5733         }
5734
5735         if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5736                 PMD_DRV_LOG(ERR,
5737                             "Invalid value passed to rep_is_pf devargs.\n");
5738                 return -EINVAL;
5739         }
5740
5741         vfr_bp->flags |= rep_is_pf;
5742         if (BNXT_REP_PF(vfr_bp))
5743                 PMD_DRV_LOG(INFO, "PF representor\n");
5744         else
5745                 PMD_DRV_LOG(INFO, "VF representor\n");
5746
5747         return 0;
5748 }
5749
5750 static int
5751 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5752                                const char *value, void *opaque_arg)
5753 {
5754         struct bnxt_representor *vfr_bp = opaque_arg;
5755         unsigned long rep_based_pf;
5756         char *end = NULL;
5757
5758         if (!value || !opaque_arg) {
5759                 PMD_DRV_LOG(ERR,
5760                             "Invalid parameter passed to rep_based_pf "
5761                             "devargs.\n");
5762                 return -EINVAL;
5763         }
5764
5765         rep_based_pf = strtoul(value, &end, 10);
5766         if (end == NULL || *end != '\0' ||
5767             (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5768                 PMD_DRV_LOG(ERR,
5769                             "Invalid parameter passed to rep_based_pf "
5770                             "devargs.\n");
5771                 return -EINVAL;
5772         }
5773
5774         if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5775                 PMD_DRV_LOG(ERR,
5776                             "Invalid value passed to rep_based_pf devargs.\n");
5777                 return -EINVAL;
5778         }
5779
5780         vfr_bp->rep_based_pf = rep_based_pf;
5781         PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5782
5783         return 0;
5784 }
5785
5786 static int
5787 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5788                             const char *value, void *opaque_arg)
5789 {
5790         struct bnxt_representor *vfr_bp = opaque_arg;
5791         unsigned long rep_q_r2f;
5792         char *end = NULL;
5793
5794         if (!value || !opaque_arg) {
5795                 PMD_DRV_LOG(ERR,
5796                             "Invalid parameter passed to rep_q_r2f "
5797                             "devargs.\n");
5798                 return -EINVAL;
5799         }
5800
5801         rep_q_r2f = strtoul(value, &end, 10);
5802         if (end == NULL || *end != '\0' ||
5803             (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5804                 PMD_DRV_LOG(ERR,
5805                             "Invalid parameter passed to rep_q_r2f "
5806                             "devargs.\n");
5807                 return -EINVAL;
5808         }
5809
5810         if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5811                 PMD_DRV_LOG(ERR,
5812                             "Invalid value passed to rep_q_r2f devargs.\n");
5813                 return -EINVAL;
5814         }
5815
5816         vfr_bp->rep_q_r2f = rep_q_r2f;
5817         vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5818         PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5819
5820         return 0;
5821 }
5822
5823 static int
5824 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5825                             const char *value, void *opaque_arg)
5826 {
5827         struct bnxt_representor *vfr_bp = opaque_arg;
5828         unsigned long rep_q_f2r;
5829         char *end = NULL;
5830
5831         if (!value || !opaque_arg) {
5832                 PMD_DRV_LOG(ERR,
5833                             "Invalid parameter passed to rep_q_f2r "
5834                             "devargs.\n");
5835                 return -EINVAL;
5836         }
5837
5838         rep_q_f2r = strtoul(value, &end, 10);
5839         if (end == NULL || *end != '\0' ||
5840             (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5841                 PMD_DRV_LOG(ERR,
5842                             "Invalid parameter passed to rep_q_f2r "
5843                             "devargs.\n");
5844                 return -EINVAL;
5845         }
5846
5847         if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5848                 PMD_DRV_LOG(ERR,
5849                             "Invalid value passed to rep_q_f2r devargs.\n");
5850                 return -EINVAL;
5851         }
5852
5853         vfr_bp->rep_q_f2r = rep_q_f2r;
5854         vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5855         PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5856
5857         return 0;
5858 }
5859
5860 static int
5861 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5862                              const char *value, void *opaque_arg)
5863 {
5864         struct bnxt_representor *vfr_bp = opaque_arg;
5865         unsigned long rep_fc_r2f;
5866         char *end = NULL;
5867
5868         if (!value || !opaque_arg) {
5869                 PMD_DRV_LOG(ERR,
5870                             "Invalid parameter passed to rep_fc_r2f "
5871                             "devargs.\n");
5872                 return -EINVAL;
5873         }
5874
5875         rep_fc_r2f = strtoul(value, &end, 10);
5876         if (end == NULL || *end != '\0' ||
5877             (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5878                 PMD_DRV_LOG(ERR,
5879                             "Invalid parameter passed to rep_fc_r2f "
5880                             "devargs.\n");
5881                 return -EINVAL;
5882         }
5883
5884         if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5885                 PMD_DRV_LOG(ERR,
5886                             "Invalid value passed to rep_fc_r2f devargs.\n");
5887                 return -EINVAL;
5888         }
5889
5890         vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5891         vfr_bp->rep_fc_r2f = rep_fc_r2f;
5892         PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5893
5894         return 0;
5895 }
5896
5897 static int
5898 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5899                              const char *value, void *opaque_arg)
5900 {
5901         struct bnxt_representor *vfr_bp = opaque_arg;
5902         unsigned long rep_fc_f2r;
5903         char *end = NULL;
5904
5905         if (!value || !opaque_arg) {
5906                 PMD_DRV_LOG(ERR,
5907                             "Invalid parameter passed to rep_fc_f2r "
5908                             "devargs.\n");
5909                 return -EINVAL;
5910         }
5911
5912         rep_fc_f2r = strtoul(value, &end, 10);
5913         if (end == NULL || *end != '\0' ||
5914             (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5915                 PMD_DRV_LOG(ERR,
5916                             "Invalid parameter passed to rep_fc_f2r "
5917                             "devargs.\n");
5918                 return -EINVAL;
5919         }
5920
5921         if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5922                 PMD_DRV_LOG(ERR,
5923                             "Invalid value passed to rep_fc_f2r devargs.\n");
5924                 return -EINVAL;
5925         }
5926
5927         vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5928         vfr_bp->rep_fc_f2r = rep_fc_f2r;
5929         PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5930
5931         return 0;
5932 }
5933
5934 static void
5935 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5936 {
5937         struct rte_kvargs *kvlist;
5938
5939         if (devargs == NULL)
5940                 return;
5941
5942         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5943         if (kvlist == NULL)
5944                 return;
5945
5946         /*
5947          * Handler for "truflow" devarg.
5948          * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1"
5949          */
5950         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5951                            bnxt_parse_devarg_truflow, bp);
5952
5953         /*
5954          * Handler for "flow_xstat" devarg.
5955          * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1"
5956          */
5957         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5958                            bnxt_parse_devarg_flow_xstat, bp);
5959
5960         /*
5961          * Handler for "max_num_kflows" devarg.
5962          * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32"
5963          */
5964         rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5965                            bnxt_parse_devarg_max_num_kflows, bp);
5966
5967         rte_kvargs_free(kvlist);
5968 }
5969
5970 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5971 {
5972         int rc = 0;
5973
5974         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5975                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5976                 if (rc)
5977                         PMD_DRV_LOG(ERR,
5978                                     "Failed to alloc switch domain: %d\n", rc);
5979                 else
5980                         PMD_DRV_LOG(INFO,
5981                                     "Switch domain allocated %d\n",
5982                                     bp->switch_domain_id);
5983         }
5984
5985         return rc;
5986 }
5987
5988 static int
5989 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5990 {
5991         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5992         static int version_printed;
5993         struct bnxt *bp;
5994         int rc;
5995
5996         if (version_printed++ == 0)
5997                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5998
5999         eth_dev->dev_ops = &bnxt_dev_ops;
6000         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
6001         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
6002         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
6003         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
6004         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
6005
6006         /*
6007          * For secondary processes, we don't initialise any further
6008          * as primary has already done this work.
6009          */
6010         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6011                 return 0;
6012
6013         rte_eth_copy_pci_info(eth_dev, pci_dev);
6014
6015         bp = eth_dev->data->dev_private;
6016
6017         /* Parse dev arguments passed on when starting the DPDK application. */
6018         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
6019
6020         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
6021
6022         if (bnxt_vf_pciid(pci_dev->id.device_id))
6023                 bp->flags |= BNXT_FLAG_VF;
6024
6025         if (bnxt_thor_device(pci_dev->id.device_id))
6026                 bp->flags |= BNXT_FLAG_THOR_CHIP;
6027
6028         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
6029             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
6030             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
6031             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
6032                 bp->flags |= BNXT_FLAG_STINGRAY;
6033
6034         rc = bnxt_init_board(eth_dev);
6035         if (rc) {
6036                 PMD_DRV_LOG(ERR,
6037                             "Failed to initialize board rc: %x\n", rc);
6038                 return rc;
6039         }
6040
6041         rc = bnxt_alloc_pf_info(bp);
6042         if (rc)
6043                 goto error_free;
6044
6045         rc = bnxt_alloc_link_info(bp);
6046         if (rc)
6047                 goto error_free;
6048
6049         rc = bnxt_alloc_parent_info(bp);
6050         if (rc)
6051                 goto error_free;
6052
6053         rc = bnxt_alloc_hwrm_resources(bp);
6054         if (rc) {
6055                 PMD_DRV_LOG(ERR,
6056                             "Failed to allocate hwrm resource rc: %x\n", rc);
6057                 goto error_free;
6058         }
6059         rc = bnxt_alloc_leds_info(bp);
6060         if (rc)
6061                 goto error_free;
6062
6063         rc = bnxt_alloc_cos_queues(bp);
6064         if (rc)
6065                 goto error_free;
6066
6067         rc = bnxt_init_resources(bp, false);
6068         if (rc)
6069                 goto error_free;
6070
6071         rc = bnxt_alloc_stats_mem(bp);
6072         if (rc)
6073                 goto error_free;
6074
6075         bnxt_alloc_switch_domain(bp);
6076
6077         /* Pass the information to the rte_eth_dev_close() that it should also
6078          * release the private port resources.
6079          */
6080         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
6081
6082         PMD_DRV_LOG(INFO,
6083                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
6084                     pci_dev->mem_resource[0].phys_addr,
6085                     pci_dev->mem_resource[0].addr);
6086
6087         return 0;
6088
6089 error_free:
6090         bnxt_dev_uninit(eth_dev);
6091         return rc;
6092 }
6093
6094
6095 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
6096 {
6097         if (!ctx)
6098                 return;
6099
6100         if (ctx->va)
6101                 rte_free(ctx->va);
6102
6103         ctx->va = NULL;
6104         ctx->dma = RTE_BAD_IOVA;
6105         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
6106 }
6107
6108 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
6109 {
6110         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
6111                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6112                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
6113                                   bp->flow_stat->max_fc,
6114                                   false);
6115
6116         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
6117                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6118                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
6119                                   bp->flow_stat->max_fc,
6120                                   false);
6121
6122         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6123                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
6124         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6125
6126         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6127                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
6128         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6129
6130         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6131                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
6132         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6133
6134         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6135                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
6136         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6137 }
6138
6139 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
6140 {
6141         bnxt_unregister_fc_ctx_mem(bp);
6142
6143         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
6144         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
6145         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
6146         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
6147 }
6148
6149 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
6150 {
6151         if (BNXT_FLOW_XSTATS_EN(bp))
6152                 bnxt_uninit_fc_ctx_mem(bp);
6153 }
6154
6155 static void
6156 bnxt_free_error_recovery_info(struct bnxt *bp)
6157 {
6158         rte_free(bp->recovery_info);
6159         bp->recovery_info = NULL;
6160         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
6161 }
6162
6163 static void
6164 bnxt_uninit_locks(struct bnxt *bp)
6165 {
6166         pthread_mutex_destroy(&bp->flow_lock);
6167         pthread_mutex_destroy(&bp->def_cp_lock);
6168         pthread_mutex_destroy(&bp->health_check_lock);
6169         if (bp->rep_info) {
6170                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
6171                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
6172         }
6173 }
6174
6175 static int
6176 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
6177 {
6178         int rc;
6179
6180         bnxt_free_int(bp);
6181         bnxt_free_mem(bp, reconfig_dev);
6182         bnxt_hwrm_func_buf_unrgtr(bp);
6183         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
6184         bp->flags &= ~BNXT_FLAG_REGISTERED;
6185         bnxt_free_ctx_mem(bp);
6186         if (!reconfig_dev) {
6187                 bnxt_free_hwrm_resources(bp);
6188                 bnxt_free_error_recovery_info(bp);
6189         }
6190
6191         bnxt_uninit_ctx_mem(bp);
6192
6193         bnxt_uninit_locks(bp);
6194         bnxt_free_flow_stats_info(bp);
6195         bnxt_free_rep_info(bp);
6196         rte_free(bp->ptp_cfg);
6197         bp->ptp_cfg = NULL;
6198         return rc;
6199 }
6200
6201 static int
6202 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
6203 {
6204         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6205                 return -EPERM;
6206
6207         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
6208
6209         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
6210                 bnxt_dev_close_op(eth_dev);
6211
6212         return 0;
6213 }
6214
6215 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
6216 {
6217         struct bnxt *bp = eth_dev->data->dev_private;
6218         struct rte_eth_dev *vf_rep_eth_dev;
6219         int ret = 0, i;
6220
6221         if (!bp)
6222                 return -EINVAL;
6223
6224         for (i = 0; i < bp->num_reps; i++) {
6225                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
6226                 if (!vf_rep_eth_dev)
6227                         continue;
6228                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
6229                             vf_rep_eth_dev->data->port_id);
6230                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
6231         }
6232         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
6233                     eth_dev->data->port_id);
6234         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
6235
6236         return ret;
6237 }
6238
6239 static void bnxt_free_rep_info(struct bnxt *bp)
6240 {
6241         rte_free(bp->rep_info);
6242         bp->rep_info = NULL;
6243         rte_free(bp->cfa_code_map);
6244         bp->cfa_code_map = NULL;
6245 }
6246
6247 static int bnxt_init_rep_info(struct bnxt *bp)
6248 {
6249         int i = 0, rc;
6250
6251         if (bp->rep_info)
6252                 return 0;
6253
6254         bp->rep_info = rte_zmalloc("bnxt_rep_info",
6255                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
6256                                    0);
6257         if (!bp->rep_info) {
6258                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
6259                 return -ENOMEM;
6260         }
6261         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
6262                                        sizeof(*bp->cfa_code_map) *
6263                                        BNXT_MAX_CFA_CODE, 0);
6264         if (!bp->cfa_code_map) {
6265                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
6266                 bnxt_free_rep_info(bp);
6267                 return -ENOMEM;
6268         }
6269
6270         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
6271                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
6272
6273         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
6274         if (rc) {
6275                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
6276                 bnxt_free_rep_info(bp);
6277                 return rc;
6278         }
6279
6280         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
6281         if (rc) {
6282                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
6283                 bnxt_free_rep_info(bp);
6284                 return rc;
6285         }
6286
6287         return rc;
6288 }
6289
6290 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
6291                                struct rte_eth_devargs eth_da,
6292                                struct rte_eth_dev *backing_eth_dev,
6293                                const char *dev_args)
6294 {
6295         struct rte_eth_dev *vf_rep_eth_dev;
6296         char name[RTE_ETH_NAME_MAX_LEN];
6297         struct bnxt *backing_bp;
6298         uint16_t num_rep;
6299         int i, ret = 0;
6300         struct rte_kvargs *kvlist;
6301
6302         num_rep = eth_da.nb_representor_ports;
6303         if (num_rep > BNXT_MAX_VF_REPS) {
6304                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
6305                             num_rep, BNXT_MAX_VF_REPS);
6306                 return -EINVAL;
6307         }
6308
6309         if (num_rep >= RTE_MAX_ETHPORTS) {
6310                 PMD_DRV_LOG(ERR,
6311                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6312                             num_rep, RTE_MAX_ETHPORTS);
6313                 return -EINVAL;
6314         }
6315
6316         backing_bp = backing_eth_dev->data->dev_private;
6317
6318         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6319                 PMD_DRV_LOG(ERR,
6320                             "Not a PF or trusted VF. No Representor support\n");
6321                 /* Returning an error is not an option.
6322                  * Applications are not handling this correctly
6323                  */
6324                 return 0;
6325         }
6326
6327         if (bnxt_init_rep_info(backing_bp))
6328                 return 0;
6329
6330         for (i = 0; i < num_rep; i++) {
6331                 struct bnxt_representor representor = {
6332                         .vf_id = eth_da.representor_ports[i],
6333                         .switch_domain_id = backing_bp->switch_domain_id,
6334                         .parent_dev = backing_eth_dev
6335                 };
6336
6337                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6338                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6339                                     representor.vf_id, BNXT_MAX_VF_REPS);
6340                         continue;
6341                 }
6342
6343                 /* representor port net_bdf_port */
6344                 snprintf(name, sizeof(name), "net_%s_representor_%d",
6345                          pci_dev->device.name, eth_da.representor_ports[i]);
6346
6347                 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
6348                 if (kvlist) {
6349                         /*
6350                          * Handler for "rep_is_pf" devarg.
6351                          * Invoked as for ex: "-w 000:00:0d.0,
6352                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6353                          */
6354                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
6355                                            bnxt_parse_devarg_rep_is_pf,
6356                                            (void *)&representor);
6357                         /*
6358                          * Handler for "rep_based_pf" devarg.
6359                          * Invoked as for ex: "-w 000:00:0d.0,
6360                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6361                          */
6362                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_BASED_PF,
6363                                            bnxt_parse_devarg_rep_based_pf,
6364                                            (void *)&representor);
6365                         /*
6366                          * Handler for "rep_based_pf" devarg.
6367                          * Invoked as for ex: "-w 000:00:0d.0,
6368                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6369                          */
6370                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
6371                                            bnxt_parse_devarg_rep_q_r2f,
6372                                            (void *)&representor);
6373                         /*
6374                          * Handler for "rep_based_pf" devarg.
6375                          * Invoked as for ex: "-w 000:00:0d.0,
6376                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6377                          */
6378                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
6379                                            bnxt_parse_devarg_rep_q_f2r,
6380                                            (void *)&representor);
6381                         /*
6382                          * Handler for "rep_based_pf" devarg.
6383                          * Invoked as for ex: "-w 000:00:0d.0,
6384                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6385                          */
6386                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
6387                                            bnxt_parse_devarg_rep_fc_r2f,
6388                                            (void *)&representor);
6389                         /*
6390                          * Handler for "rep_based_pf" devarg.
6391                          * Invoked as for ex: "-w 000:00:0d.0,
6392                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6393                          */
6394                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
6395                                            bnxt_parse_devarg_rep_fc_f2r,
6396                                            (void *)&representor);
6397                 }
6398
6399                 ret = rte_eth_dev_create(&pci_dev->device, name,
6400                                          sizeof(struct bnxt_representor),
6401                                          NULL, NULL,
6402                                          bnxt_representor_init,
6403                                          &representor);
6404                 if (ret) {
6405                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6406                                     "representor %s.", name);
6407                         goto err;
6408                 }
6409
6410                 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6411                 if (!vf_rep_eth_dev) {
6412                         PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6413                                     " for VF-Rep: %s.", name);
6414                         ret = -ENODEV;
6415                         goto err;
6416                 }
6417
6418                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6419                             backing_eth_dev->data->port_id);
6420                 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6421                                                          vf_rep_eth_dev;
6422                 backing_bp->num_reps++;
6423
6424         }
6425
6426         return 0;
6427
6428 err:
6429         /* If num_rep > 1, then rollback already created
6430          * ports, since we'll be failing the probe anyway
6431          */
6432         if (num_rep > 1)
6433                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6434
6435         return ret;
6436 }
6437
6438 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6439                           struct rte_pci_device *pci_dev)
6440 {
6441         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6442         struct rte_eth_dev *backing_eth_dev;
6443         uint16_t num_rep;
6444         int ret = 0;
6445
6446         if (pci_dev->device.devargs) {
6447                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6448                                             &eth_da);
6449                 if (ret)
6450                         return ret;
6451         }
6452
6453         num_rep = eth_da.nb_representor_ports;
6454         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6455                     num_rep);
6456
6457         /* We could come here after first level of probe is already invoked
6458          * as part of an application bringup(OVS-DPDK vswitchd), so first check
6459          * for already allocated eth_dev for the backing device (PF/Trusted VF)
6460          */
6461         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6462         if (backing_eth_dev == NULL) {
6463                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6464                                          sizeof(struct bnxt),
6465                                          eth_dev_pci_specific_init, pci_dev,
6466                                          bnxt_dev_init, NULL);
6467
6468                 if (ret || !num_rep)
6469                         return ret;
6470
6471                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6472         }
6473         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6474                     backing_eth_dev->data->port_id);
6475
6476         if (!num_rep)
6477                 return ret;
6478
6479         /* probe representor ports now */
6480         ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev,
6481                                   pci_dev->device.devargs->args);
6482
6483         return ret;
6484 }
6485
6486 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6487 {
6488         struct rte_eth_dev *eth_dev;
6489
6490         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6491         if (!eth_dev)
6492                 return 0; /* Invoked typically only by OVS-DPDK, by the
6493                            * time it comes here the eth_dev is already
6494                            * deleted by rte_eth_dev_close(), so returning
6495                            * +ve value will at least help in proper cleanup
6496                            */
6497
6498         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6499         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6500                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6501                         return rte_eth_dev_destroy(eth_dev,
6502                                                    bnxt_representor_uninit);
6503                 else
6504                         return rte_eth_dev_destroy(eth_dev,
6505                                                    bnxt_dev_uninit);
6506         } else {
6507                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6508         }
6509 }
6510
6511 static struct rte_pci_driver bnxt_rte_pmd = {
6512         .id_table = bnxt_pci_id_map,
6513         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6514                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6515                                                   * and OVS-DPDK
6516                                                   */
6517         .probe = bnxt_pci_probe,
6518         .remove = bnxt_pci_remove,
6519 };
6520
6521 static bool
6522 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6523 {
6524         if (strcmp(dev->device->driver->name, drv->driver.name))
6525                 return false;
6526
6527         return true;
6528 }
6529
6530 bool is_bnxt_supported(struct rte_eth_dev *dev)
6531 {
6532         return is_device_supported(dev, &bnxt_rte_pmd);
6533 }
6534
6535 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
6536 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6537 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6538 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");