1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
20 #include "bnxt_ring.h"
23 #include "bnxt_stats.h"
26 #include "bnxt_vnic.h"
27 #include "hsi_struct_def_dpdk.h"
28 #include "bnxt_nvm_defs.h"
30 #define DRV_MODULE_NAME "bnxt"
31 static const char bnxt_version[] =
32 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
33 int bnxt_logtype_driver;
36 * The set of PCI devices this driver supports
38 static const struct rte_pci_id bnxt_pci_id_map[] = {
39 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
40 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
41 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
42 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
43 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
45 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
47 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
92 { .vendor_id = 0, /* sentinel */ },
95 #define BNXT_ETH_RSS_SUPPORT ( \
97 ETH_RSS_NONFRAG_IPV4_TCP | \
98 ETH_RSS_NONFRAG_IPV4_UDP | \
100 ETH_RSS_NONFRAG_IPV6_TCP | \
101 ETH_RSS_NONFRAG_IPV6_UDP)
103 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
104 DEV_TX_OFFLOAD_IPV4_CKSUM | \
105 DEV_TX_OFFLOAD_TCP_CKSUM | \
106 DEV_TX_OFFLOAD_UDP_CKSUM | \
107 DEV_TX_OFFLOAD_TCP_TSO | \
108 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
109 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
110 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
111 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
112 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
113 DEV_TX_OFFLOAD_QINQ_INSERT | \
114 DEV_TX_OFFLOAD_MULTI_SEGS)
116 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
117 DEV_RX_OFFLOAD_VLAN_STRIP | \
118 DEV_RX_OFFLOAD_IPV4_CKSUM | \
119 DEV_RX_OFFLOAD_UDP_CKSUM | \
120 DEV_RX_OFFLOAD_TCP_CKSUM | \
121 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
122 DEV_RX_OFFLOAD_JUMBO_FRAME | \
123 DEV_RX_OFFLOAD_KEEP_CRC | \
124 DEV_RX_OFFLOAD_VLAN_EXTEND | \
125 DEV_RX_OFFLOAD_TCP_LRO | \
126 DEV_RX_OFFLOAD_SCATTER | \
127 DEV_RX_OFFLOAD_RSS_HASH)
129 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
130 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
131 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
132 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
133 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
134 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
135 static int bnxt_restore_vlan_filters(struct bnxt *bp);
137 int is_bnxt_in_error(struct bnxt *bp)
139 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
141 if (bp->flags & BNXT_FLAG_FW_RESET)
147 /***********************/
150 * High level utility functions
153 uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
155 if (!BNXT_CHIP_THOR(bp))
158 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
159 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
160 BNXT_RSS_ENTRIES_PER_CTX_THOR;
163 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
165 if (!BNXT_CHIP_THOR(bp))
166 return HW_HASH_INDEX_SIZE;
168 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
171 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
173 bnxt_free_filter_mem(bp);
174 bnxt_free_vnic_attributes(bp);
175 bnxt_free_vnic_mem(bp);
177 /* tx/rx rings are configured as part of *_queue_setup callbacks.
178 * If the number of rings change across fw update,
179 * we don't have much choice except to warn the user.
183 bnxt_free_tx_rings(bp);
184 bnxt_free_rx_rings(bp);
186 bnxt_free_async_cp_ring(bp);
187 bnxt_free_rxtx_nq_ring(bp);
189 rte_free(bp->grp_info);
193 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
197 rc = bnxt_alloc_ring_grps(bp);
201 rc = bnxt_alloc_async_ring_struct(bp);
205 rc = bnxt_alloc_vnic_mem(bp);
209 rc = bnxt_alloc_vnic_attributes(bp);
213 rc = bnxt_alloc_filter_mem(bp);
217 rc = bnxt_alloc_async_cp_ring(bp);
221 rc = bnxt_alloc_rxtx_nq_ring(bp);
228 bnxt_free_mem(bp, reconfig);
232 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
234 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
235 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
236 uint64_t rx_offloads = dev_conf->rxmode.offloads;
237 struct bnxt_rx_queue *rxq;
241 rc = bnxt_vnic_grp_alloc(bp, vnic);
245 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
246 vnic_id, vnic, vnic->fw_grp_ids);
248 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
252 /* Alloc RSS context only if RSS mode is enabled */
253 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
254 int j, nr_ctxs = bnxt_rss_ctxts(bp);
257 for (j = 0; j < nr_ctxs; j++) {
258 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
264 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
268 vnic->num_lb_ctxts = nr_ctxs;
272 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
273 * setting is not available at this time, it will not be
274 * configured correctly in the CFA.
276 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
277 vnic->vlan_strip = true;
279 vnic->vlan_strip = false;
281 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
285 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
289 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
290 rxq = bp->eth_dev->data->rx_queues[j];
293 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
294 j, rxq->vnic, rxq->vnic->fw_grp_ids);
296 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
297 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
300 rc = bnxt_vnic_rss_configure(bp, vnic);
304 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
306 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
307 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
309 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
313 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
318 static int bnxt_init_chip(struct bnxt *bp)
320 struct rte_eth_link new;
321 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
322 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
323 uint32_t intr_vector = 0;
324 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
325 uint32_t vec = BNXT_MISC_VEC_ID;
329 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
330 bp->eth_dev->data->dev_conf.rxmode.offloads |=
331 DEV_RX_OFFLOAD_JUMBO_FRAME;
332 bp->flags |= BNXT_FLAG_JUMBO;
334 bp->eth_dev->data->dev_conf.rxmode.offloads &=
335 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
336 bp->flags &= ~BNXT_FLAG_JUMBO;
339 /* THOR does not support ring groups.
340 * But we will use the array to save RSS context IDs.
342 if (BNXT_CHIP_THOR(bp))
343 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
345 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
347 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
351 rc = bnxt_alloc_hwrm_rings(bp);
353 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
357 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
359 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
363 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
366 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
367 if (bp->rx_cos_queue[i].id != 0xff) {
368 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
372 "Num pools more than FW profile\n");
376 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
382 rc = bnxt_mq_rx_configure(bp);
384 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
388 /* VNIC configuration */
389 for (i = 0; i < bp->nr_vnics; i++) {
390 rc = bnxt_setup_one_vnic(bp, i);
395 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
398 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
402 /* check and configure queue intr-vector mapping */
403 if ((rte_intr_cap_multiple(intr_handle) ||
404 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
405 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
406 intr_vector = bp->eth_dev->data->nb_rx_queues;
407 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
408 if (intr_vector > bp->rx_cp_nr_rings) {
409 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
413 rc = rte_intr_efd_enable(intr_handle, intr_vector);
418 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
419 intr_handle->intr_vec =
420 rte_zmalloc("intr_vec",
421 bp->eth_dev->data->nb_rx_queues *
423 if (intr_handle->intr_vec == NULL) {
424 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
425 " intr_vec", bp->eth_dev->data->nb_rx_queues);
429 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
430 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
431 intr_handle->intr_vec, intr_handle->nb_efd,
432 intr_handle->max_intr);
433 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
435 intr_handle->intr_vec[queue_id] =
436 vec + BNXT_RX_VEC_START;
437 if (vec < base + intr_handle->nb_efd - 1)
442 /* enable uio/vfio intr/eventfd mapping */
443 rc = rte_intr_enable(intr_handle);
444 #ifndef RTE_EXEC_ENV_FREEBSD
445 /* In FreeBSD OS, nic_uio driver does not support interrupts */
450 rc = bnxt_get_hwrm_link_config(bp, &new);
452 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
456 if (!bp->link_info.link_up) {
457 rc = bnxt_set_hwrm_link_config(bp, true);
460 "HWRM link config failure rc: %x\n", rc);
464 bnxt_print_link_info(bp->eth_dev);
466 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
468 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
473 rte_free(intr_handle->intr_vec);
475 rte_intr_efd_disable(intr_handle);
477 /* Some of the error status returned by FW may not be from errno.h */
484 static int bnxt_shutdown_nic(struct bnxt *bp)
486 bnxt_free_all_hwrm_resources(bp);
487 bnxt_free_all_filters(bp);
488 bnxt_free_all_vnics(bp);
493 * Device configuration and status function
496 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
497 struct rte_eth_dev_info *dev_info)
499 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
500 struct bnxt *bp = eth_dev->data->dev_private;
501 uint16_t max_vnics, i, j, vpool, vrxq;
502 unsigned int max_rx_rings;
505 rc = is_bnxt_in_error(bp);
510 dev_info->max_mac_addrs = bp->max_l2_ctx;
511 dev_info->max_hash_mac_addrs = 0;
513 /* PF/VF specifics */
515 dev_info->max_vfs = pdev->max_vfs;
517 max_rx_rings = BNXT_MAX_RINGS(bp);
518 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
519 dev_info->max_rx_queues = max_rx_rings;
520 dev_info->max_tx_queues = max_rx_rings;
521 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
522 dev_info->hash_key_size = 40;
523 max_vnics = bp->max_vnics;
526 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
527 dev_info->max_mtu = BNXT_MAX_MTU;
529 /* Fast path specifics */
530 dev_info->min_rx_bufsize = 1;
531 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
533 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
534 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
535 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
536 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
537 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
540 dev_info->default_rxconf = (struct rte_eth_rxconf) {
546 .rx_free_thresh = 32,
547 /* If no descriptors available, pkts are dropped by default */
551 dev_info->default_txconf = (struct rte_eth_txconf) {
557 .tx_free_thresh = 32,
560 eth_dev->data->dev_conf.intr_conf.lsc = 1;
562 eth_dev->data->dev_conf.intr_conf.rxq = 1;
563 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
564 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
565 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
566 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
571 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
572 * need further investigation.
576 vpool = 64; /* ETH_64_POOLS */
577 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
578 for (i = 0; i < 4; vpool >>= 1, i++) {
579 if (max_vnics > vpool) {
580 for (j = 0; j < 5; vrxq >>= 1, j++) {
581 if (dev_info->max_rx_queues > vrxq) {
587 /* Not enough resources to support VMDq */
591 /* Not enough resources to support VMDq */
595 dev_info->max_vmdq_pools = vpool;
596 dev_info->vmdq_queue_num = vrxq;
598 dev_info->vmdq_pool_base = 0;
599 dev_info->vmdq_queue_base = 0;
604 /* Configure the device based on the configuration provided */
605 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
607 struct bnxt *bp = eth_dev->data->dev_private;
608 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
611 bp->rx_queues = (void *)eth_dev->data->rx_queues;
612 bp->tx_queues = (void *)eth_dev->data->tx_queues;
613 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
614 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
616 rc = is_bnxt_in_error(bp);
620 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
621 rc = bnxt_hwrm_check_vf_rings(bp);
623 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
627 /* If a resource has already been allocated - in this case
628 * it is the async completion ring, free it. Reallocate it after
629 * resource reservation. This will ensure the resource counts
630 * are calculated correctly.
633 pthread_mutex_lock(&bp->def_cp_lock);
635 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
636 bnxt_disable_int(bp);
637 bnxt_free_cp_ring(bp, bp->async_cp_ring);
640 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
642 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
643 pthread_mutex_unlock(&bp->def_cp_lock);
647 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
648 rc = bnxt_alloc_async_cp_ring(bp);
650 pthread_mutex_unlock(&bp->def_cp_lock);
656 pthread_mutex_unlock(&bp->def_cp_lock);
658 /* legacy driver needs to get updated values */
659 rc = bnxt_hwrm_func_qcaps(bp);
661 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
666 /* Inherit new configurations */
667 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
668 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
669 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
670 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
671 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
675 if (BNXT_HAS_RING_GRPS(bp) &&
676 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
679 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
680 bp->max_vnics < eth_dev->data->nb_rx_queues)
683 bp->rx_cp_nr_rings = bp->rx_nr_rings;
684 bp->tx_cp_nr_rings = bp->tx_nr_rings;
686 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
687 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
688 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
690 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
692 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
693 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
695 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
701 "Insufficient resources to support requested config\n");
703 "Num Queues Requested: Tx %d, Rx %d\n",
704 eth_dev->data->nb_tx_queues,
705 eth_dev->data->nb_rx_queues);
707 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
708 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
709 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
713 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
715 struct rte_eth_link *link = ð_dev->data->dev_link;
717 if (link->link_status)
718 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
719 eth_dev->data->port_id,
720 (uint32_t)link->link_speed,
721 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
722 ("full-duplex") : ("half-duplex\n"));
724 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
725 eth_dev->data->port_id);
729 * Determine whether the current configuration requires support for scattered
730 * receive; return 1 if scattered receive is required and 0 if not.
732 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
737 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
740 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
741 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
743 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
744 RTE_PKTMBUF_HEADROOM);
745 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
751 static eth_rx_burst_t
752 bnxt_receive_function(struct rte_eth_dev *eth_dev)
754 struct bnxt *bp = eth_dev->data->dev_private;
757 #ifndef RTE_LIBRTE_IEEE1588
759 * Vector mode receive can be enabled only if scatter rx is not
760 * in use and rx offloads are limited to VLAN stripping and
763 if (!eth_dev->data->scattered_rx &&
764 !(eth_dev->data->dev_conf.rxmode.offloads &
765 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
766 DEV_RX_OFFLOAD_KEEP_CRC |
767 DEV_RX_OFFLOAD_JUMBO_FRAME |
768 DEV_RX_OFFLOAD_IPV4_CKSUM |
769 DEV_RX_OFFLOAD_UDP_CKSUM |
770 DEV_RX_OFFLOAD_TCP_CKSUM |
771 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
772 DEV_RX_OFFLOAD_RSS_HASH |
773 DEV_RX_OFFLOAD_VLAN_FILTER))) {
774 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
775 eth_dev->data->port_id);
776 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
777 return bnxt_recv_pkts_vec;
779 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
780 eth_dev->data->port_id);
782 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
783 eth_dev->data->port_id,
784 eth_dev->data->scattered_rx,
785 eth_dev->data->dev_conf.rxmode.offloads);
788 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
789 return bnxt_recv_pkts;
792 static eth_tx_burst_t
793 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
796 #ifndef RTE_LIBRTE_IEEE1588
798 * Vector mode transmit can be enabled only if not using scatter rx
801 if (!eth_dev->data->scattered_rx &&
802 !eth_dev->data->dev_conf.txmode.offloads) {
803 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
804 eth_dev->data->port_id);
805 return bnxt_xmit_pkts_vec;
807 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
808 eth_dev->data->port_id);
810 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
811 eth_dev->data->port_id,
812 eth_dev->data->scattered_rx,
813 eth_dev->data->dev_conf.txmode.offloads);
816 return bnxt_xmit_pkts;
819 static int bnxt_handle_if_change_status(struct bnxt *bp)
823 /* Since fw has undergone a reset and lost all contexts,
824 * set fatal flag to not issue hwrm during cleanup
826 bp->flags |= BNXT_FLAG_FATAL_ERROR;
827 bnxt_uninit_resources(bp, true);
829 /* clear fatal flag so that re-init happens */
830 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
831 rc = bnxt_init_resources(bp, true);
833 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
838 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
840 struct bnxt *bp = eth_dev->data->dev_private;
841 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
845 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
846 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
850 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
852 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
853 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
856 rc = bnxt_hwrm_if_change(bp, 1);
858 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
859 rc = bnxt_handle_if_change_status(bp);
866 rc = bnxt_init_chip(bp);
870 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
872 bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
875 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
876 vlan_mask |= ETH_VLAN_FILTER_MASK;
877 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
878 vlan_mask |= ETH_VLAN_STRIP_MASK;
879 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
883 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
884 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
886 bp->flags |= BNXT_FLAG_INIT_DONE;
887 eth_dev->data->dev_started = 1;
888 pthread_mutex_lock(&bp->def_cp_lock);
889 bnxt_schedule_fw_health_check(bp);
890 pthread_mutex_unlock(&bp->def_cp_lock);
894 bnxt_hwrm_if_change(bp, 0);
895 bnxt_shutdown_nic(bp);
896 bnxt_free_tx_mbufs(bp);
897 bnxt_free_rx_mbufs(bp);
902 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
904 struct bnxt *bp = eth_dev->data->dev_private;
907 if (!bp->link_info.link_up)
908 rc = bnxt_set_hwrm_link_config(bp, true);
910 eth_dev->data->dev_link.link_status = 1;
912 bnxt_print_link_info(eth_dev);
916 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
918 struct bnxt *bp = eth_dev->data->dev_private;
920 eth_dev->data->dev_link.link_status = 0;
921 bnxt_set_hwrm_link_config(bp, false);
922 bp->link_info.link_up = 0;
927 /* Unload the driver, release resources */
928 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
930 struct bnxt *bp = eth_dev->data->dev_private;
931 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
932 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
934 eth_dev->data->dev_started = 0;
935 /* Prevent crashes when queues are still in use */
936 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
937 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
939 bnxt_disable_int(bp);
941 /* disable uio/vfio intr/eventfd mapping */
942 rte_intr_disable(intr_handle);
944 bnxt_cancel_fw_health_check(bp);
946 bp->flags &= ~BNXT_FLAG_INIT_DONE;
947 if (bp->eth_dev->data->dev_started) {
948 /* TBD: STOP HW queues DMA */
949 eth_dev->data->dev_link.link_status = 0;
951 bnxt_dev_set_link_down_op(eth_dev);
953 /* Wait for link to be reset and the async notification to process.
954 * During reset recovery, there is no need to wait
956 if (!is_bnxt_in_error(bp))
957 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
959 /* Clean queue intr-vector mapping */
960 rte_intr_efd_disable(intr_handle);
961 if (intr_handle->intr_vec != NULL) {
962 rte_free(intr_handle->intr_vec);
963 intr_handle->intr_vec = NULL;
966 bnxt_hwrm_port_clr_stats(bp);
967 bnxt_free_tx_mbufs(bp);
968 bnxt_free_rx_mbufs(bp);
969 /* Process any remaining notifications in default completion queue */
970 bnxt_int_handler(eth_dev);
971 bnxt_shutdown_nic(bp);
972 bnxt_hwrm_if_change(bp, 0);
974 rte_free(bp->mark_table);
975 bp->mark_table = NULL;
977 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
982 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
984 struct bnxt *bp = eth_dev->data->dev_private;
986 if (bp->dev_stopped == 0)
987 bnxt_dev_stop_op(eth_dev);
989 if (eth_dev->data->mac_addrs != NULL) {
990 rte_free(eth_dev->data->mac_addrs);
991 eth_dev->data->mac_addrs = NULL;
993 if (bp->grp_info != NULL) {
994 rte_free(bp->grp_info);
998 bnxt_dev_uninit(eth_dev);
1001 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1004 struct bnxt *bp = eth_dev->data->dev_private;
1005 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1006 struct bnxt_vnic_info *vnic;
1007 struct bnxt_filter_info *filter, *temp_filter;
1010 if (is_bnxt_in_error(bp))
1014 * Loop through all VNICs from the specified filter flow pools to
1015 * remove the corresponding MAC addr filter
1017 for (i = 0; i < bp->nr_vnics; i++) {
1018 if (!(pool_mask & (1ULL << i)))
1021 vnic = &bp->vnic_info[i];
1022 filter = STAILQ_FIRST(&vnic->filter);
1024 temp_filter = STAILQ_NEXT(filter, next);
1025 if (filter->mac_index == index) {
1026 STAILQ_REMOVE(&vnic->filter, filter,
1027 bnxt_filter_info, next);
1028 bnxt_hwrm_clear_l2_filter(bp, filter);
1029 bnxt_free_filter(bp, filter);
1031 filter = temp_filter;
1036 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1037 struct rte_ether_addr *mac_addr, uint32_t index,
1040 struct bnxt_filter_info *filter;
1043 /* Attach requested MAC address to the new l2_filter */
1044 STAILQ_FOREACH(filter, &vnic->filter, next) {
1045 if (filter->mac_index == index) {
1047 "MAC addr already existed for pool %d\n",
1053 filter = bnxt_alloc_filter(bp);
1055 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1059 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1060 * if the MAC that's been programmed now is a different one, then,
1061 * copy that addr to filter->l2_addr
1064 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1065 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1067 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1069 filter->mac_index = index;
1070 if (filter->mac_index == 0)
1071 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1073 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1075 bnxt_free_filter(bp, filter);
1081 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1082 struct rte_ether_addr *mac_addr,
1083 uint32_t index, uint32_t pool)
1085 struct bnxt *bp = eth_dev->data->dev_private;
1086 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1089 rc = is_bnxt_in_error(bp);
1093 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1094 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1099 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1103 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1108 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1109 bool exp_link_status)
1112 struct bnxt *bp = eth_dev->data->dev_private;
1113 struct rte_eth_link new;
1114 int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1115 BNXT_LINK_DOWN_WAIT_CNT;
1117 rc = is_bnxt_in_error(bp);
1121 memset(&new, 0, sizeof(new));
1123 /* Retrieve link info from hardware */
1124 rc = bnxt_get_hwrm_link_config(bp, &new);
1126 new.link_speed = ETH_LINK_SPEED_100M;
1127 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1129 "Failed to retrieve link rc = 0x%x!\n", rc);
1133 if (!wait_to_complete || new.link_status == exp_link_status)
1136 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1140 /* Timed out or success */
1141 if (new.link_status != eth_dev->data->dev_link.link_status ||
1142 new.link_speed != eth_dev->data->dev_link.link_speed) {
1143 rte_eth_linkstatus_set(eth_dev, &new);
1145 _rte_eth_dev_callback_process(eth_dev,
1146 RTE_ETH_EVENT_INTR_LSC,
1149 bnxt_print_link_info(eth_dev);
1155 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1156 int wait_to_complete)
1158 return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1161 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1163 struct bnxt *bp = eth_dev->data->dev_private;
1164 struct bnxt_vnic_info *vnic;
1168 rc = is_bnxt_in_error(bp);
1172 /* Filter settings will get applied when port is started */
1173 if (bp->dev_stopped == 1)
1176 if (bp->vnic_info == NULL)
1179 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1181 old_flags = vnic->flags;
1182 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1183 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1185 vnic->flags = old_flags;
1190 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1192 struct bnxt *bp = eth_dev->data->dev_private;
1193 struct bnxt_vnic_info *vnic;
1197 rc = is_bnxt_in_error(bp);
1201 /* Filter settings will get applied when port is started */
1202 if (bp->dev_stopped == 1)
1205 if (bp->vnic_info == NULL)
1208 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1210 old_flags = vnic->flags;
1211 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1212 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1214 vnic->flags = old_flags;
1219 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1221 struct bnxt *bp = eth_dev->data->dev_private;
1222 struct bnxt_vnic_info *vnic;
1226 rc = is_bnxt_in_error(bp);
1230 /* Filter settings will get applied when port is started */
1231 if (bp->dev_stopped == 1)
1234 if (bp->vnic_info == NULL)
1237 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1239 old_flags = vnic->flags;
1240 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1241 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1243 vnic->flags = old_flags;
1248 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1250 struct bnxt *bp = eth_dev->data->dev_private;
1251 struct bnxt_vnic_info *vnic;
1255 rc = is_bnxt_in_error(bp);
1259 /* Filter settings will get applied when port is started */
1260 if (bp->dev_stopped == 1)
1263 if (bp->vnic_info == NULL)
1266 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1268 old_flags = vnic->flags;
1269 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1270 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1272 vnic->flags = old_flags;
1277 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1278 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1280 if (qid >= bp->rx_nr_rings)
1283 return bp->eth_dev->data->rx_queues[qid];
1286 /* Return rxq corresponding to a given rss table ring/group ID. */
1287 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1289 struct bnxt_rx_queue *rxq;
1292 if (!BNXT_HAS_RING_GRPS(bp)) {
1293 for (i = 0; i < bp->rx_nr_rings; i++) {
1294 rxq = bp->eth_dev->data->rx_queues[i];
1295 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1299 for (i = 0; i < bp->rx_nr_rings; i++) {
1300 if (bp->grp_info[i].fw_grp_id == fwr)
1305 return INVALID_HW_RING_ID;
1308 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1309 struct rte_eth_rss_reta_entry64 *reta_conf,
1312 struct bnxt *bp = eth_dev->data->dev_private;
1313 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1314 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1315 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1319 rc = is_bnxt_in_error(bp);
1323 if (!vnic->rss_table)
1326 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1329 if (reta_size != tbl_size) {
1330 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1331 "(%d) must equal the size supported by the hardware "
1332 "(%d)\n", reta_size, tbl_size);
1336 for (i = 0; i < reta_size; i++) {
1337 struct bnxt_rx_queue *rxq;
1339 idx = i / RTE_RETA_GROUP_SIZE;
1340 sft = i % RTE_RETA_GROUP_SIZE;
1342 if (!(reta_conf[idx].mask & (1ULL << sft)))
1345 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1347 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1351 if (BNXT_CHIP_THOR(bp)) {
1352 vnic->rss_table[i * 2] =
1353 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1354 vnic->rss_table[i * 2 + 1] =
1355 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1357 vnic->rss_table[i] =
1358 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1362 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1366 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1367 struct rte_eth_rss_reta_entry64 *reta_conf,
1370 struct bnxt *bp = eth_dev->data->dev_private;
1371 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1372 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1373 uint16_t idx, sft, i;
1376 rc = is_bnxt_in_error(bp);
1380 /* Retrieve from the default VNIC */
1383 if (!vnic->rss_table)
1386 if (reta_size != tbl_size) {
1387 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1388 "(%d) must equal the size supported by the hardware "
1389 "(%d)\n", reta_size, tbl_size);
1393 for (idx = 0, i = 0; i < reta_size; i++) {
1394 idx = i / RTE_RETA_GROUP_SIZE;
1395 sft = i % RTE_RETA_GROUP_SIZE;
1397 if (reta_conf[idx].mask & (1ULL << sft)) {
1400 if (BNXT_CHIP_THOR(bp))
1401 qid = bnxt_rss_to_qid(bp,
1402 vnic->rss_table[i * 2]);
1404 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1406 if (qid == INVALID_HW_RING_ID) {
1407 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1410 reta_conf[idx].reta[sft] = qid;
1417 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1418 struct rte_eth_rss_conf *rss_conf)
1420 struct bnxt *bp = eth_dev->data->dev_private;
1421 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1422 struct bnxt_vnic_info *vnic;
1425 rc = is_bnxt_in_error(bp);
1430 * If RSS enablement were different than dev_configure,
1431 * then return -EINVAL
1433 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1434 if (!rss_conf->rss_hf)
1435 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1437 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1441 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1442 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1444 /* Update the default RSS VNIC(s) */
1445 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1446 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1449 * If hashkey is not specified, use the previously configured
1452 if (!rss_conf->rss_key)
1455 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1457 "Invalid hashkey length, should be 16 bytes\n");
1460 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1463 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1467 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1468 struct rte_eth_rss_conf *rss_conf)
1470 struct bnxt *bp = eth_dev->data->dev_private;
1471 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1473 uint32_t hash_types;
1475 rc = is_bnxt_in_error(bp);
1479 /* RSS configuration is the same for all VNICs */
1480 if (vnic && vnic->rss_hash_key) {
1481 if (rss_conf->rss_key) {
1482 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1483 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1484 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1487 hash_types = vnic->hash_type;
1488 rss_conf->rss_hf = 0;
1489 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1490 rss_conf->rss_hf |= ETH_RSS_IPV4;
1491 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1493 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1494 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1496 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1498 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1499 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1501 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1503 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1504 rss_conf->rss_hf |= ETH_RSS_IPV6;
1505 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1507 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1508 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1510 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1512 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1513 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1515 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1519 "Unknwon RSS config from firmware (%08x), RSS disabled",
1524 rss_conf->rss_hf = 0;
1529 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1530 struct rte_eth_fc_conf *fc_conf)
1532 struct bnxt *bp = dev->data->dev_private;
1533 struct rte_eth_link link_info;
1536 rc = is_bnxt_in_error(bp);
1540 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1544 memset(fc_conf, 0, sizeof(*fc_conf));
1545 if (bp->link_info.auto_pause)
1546 fc_conf->autoneg = 1;
1547 switch (bp->link_info.pause) {
1549 fc_conf->mode = RTE_FC_NONE;
1551 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1552 fc_conf->mode = RTE_FC_TX_PAUSE;
1554 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1555 fc_conf->mode = RTE_FC_RX_PAUSE;
1557 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1558 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1559 fc_conf->mode = RTE_FC_FULL;
1565 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1566 struct rte_eth_fc_conf *fc_conf)
1568 struct bnxt *bp = dev->data->dev_private;
1571 rc = is_bnxt_in_error(bp);
1575 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1576 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1580 switch (fc_conf->mode) {
1582 bp->link_info.auto_pause = 0;
1583 bp->link_info.force_pause = 0;
1585 case RTE_FC_RX_PAUSE:
1586 if (fc_conf->autoneg) {
1587 bp->link_info.auto_pause =
1588 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1589 bp->link_info.force_pause = 0;
1591 bp->link_info.auto_pause = 0;
1592 bp->link_info.force_pause =
1593 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1596 case RTE_FC_TX_PAUSE:
1597 if (fc_conf->autoneg) {
1598 bp->link_info.auto_pause =
1599 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1600 bp->link_info.force_pause = 0;
1602 bp->link_info.auto_pause = 0;
1603 bp->link_info.force_pause =
1604 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1608 if (fc_conf->autoneg) {
1609 bp->link_info.auto_pause =
1610 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1611 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1612 bp->link_info.force_pause = 0;
1614 bp->link_info.auto_pause = 0;
1615 bp->link_info.force_pause =
1616 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1617 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1621 return bnxt_set_hwrm_link_config(bp, true);
1624 /* Add UDP tunneling port */
1626 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1627 struct rte_eth_udp_tunnel *udp_tunnel)
1629 struct bnxt *bp = eth_dev->data->dev_private;
1630 uint16_t tunnel_type = 0;
1633 rc = is_bnxt_in_error(bp);
1637 switch (udp_tunnel->prot_type) {
1638 case RTE_TUNNEL_TYPE_VXLAN:
1639 if (bp->vxlan_port_cnt) {
1640 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1641 udp_tunnel->udp_port);
1642 if (bp->vxlan_port != udp_tunnel->udp_port) {
1643 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1646 bp->vxlan_port_cnt++;
1650 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1651 bp->vxlan_port_cnt++;
1653 case RTE_TUNNEL_TYPE_GENEVE:
1654 if (bp->geneve_port_cnt) {
1655 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1656 udp_tunnel->udp_port);
1657 if (bp->geneve_port != udp_tunnel->udp_port) {
1658 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1661 bp->geneve_port_cnt++;
1665 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1666 bp->geneve_port_cnt++;
1669 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1672 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1678 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1679 struct rte_eth_udp_tunnel *udp_tunnel)
1681 struct bnxt *bp = eth_dev->data->dev_private;
1682 uint16_t tunnel_type = 0;
1686 rc = is_bnxt_in_error(bp);
1690 switch (udp_tunnel->prot_type) {
1691 case RTE_TUNNEL_TYPE_VXLAN:
1692 if (!bp->vxlan_port_cnt) {
1693 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1696 if (bp->vxlan_port != udp_tunnel->udp_port) {
1697 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1698 udp_tunnel->udp_port, bp->vxlan_port);
1701 if (--bp->vxlan_port_cnt)
1705 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1706 port = bp->vxlan_fw_dst_port_id;
1708 case RTE_TUNNEL_TYPE_GENEVE:
1709 if (!bp->geneve_port_cnt) {
1710 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1713 if (bp->geneve_port != udp_tunnel->udp_port) {
1714 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1715 udp_tunnel->udp_port, bp->geneve_port);
1718 if (--bp->geneve_port_cnt)
1722 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1723 port = bp->geneve_fw_dst_port_id;
1726 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1730 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1733 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1736 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1737 bp->geneve_port = 0;
1742 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1744 struct bnxt_filter_info *filter;
1745 struct bnxt_vnic_info *vnic;
1747 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1749 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1750 filter = STAILQ_FIRST(&vnic->filter);
1752 /* Search for this matching MAC+VLAN filter */
1753 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
1754 /* Delete the filter */
1755 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1758 STAILQ_REMOVE(&vnic->filter, filter,
1759 bnxt_filter_info, next);
1760 bnxt_free_filter(bp, filter);
1762 "Deleted vlan filter for %d\n",
1766 filter = STAILQ_NEXT(filter, next);
1771 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1773 struct bnxt_filter_info *filter;
1774 struct bnxt_vnic_info *vnic;
1776 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1777 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1778 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1780 /* Implementation notes on the use of VNIC in this command:
1782 * By default, these filters belong to default vnic for the function.
1783 * Once these filters are set up, only destination VNIC can be modified.
1784 * If the destination VNIC is not specified in this command,
1785 * then the HWRM shall only create an l2 context id.
1788 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1789 filter = STAILQ_FIRST(&vnic->filter);
1790 /* Check if the VLAN has already been added */
1792 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
1795 filter = STAILQ_NEXT(filter, next);
1798 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1799 * command to create MAC+VLAN filter with the right flags, enables set.
1801 filter = bnxt_alloc_filter(bp);
1804 "MAC/VLAN filter alloc failed\n");
1807 /* MAC + VLAN ID filter */
1808 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1809 * untagged packets are received
1811 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
1812 * packets and only the programmed vlan's packets are received
1814 filter->l2_ivlan = vlan_id;
1815 filter->l2_ivlan_mask = 0x0FFF;
1816 filter->enables |= en;
1817 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1819 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1821 /* Free the newly allocated filter as we were
1822 * not able to create the filter in hardware.
1824 bnxt_free_filter(bp, filter);
1828 filter->mac_index = 0;
1829 /* Add this new filter to the list */
1831 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1833 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1836 "Added Vlan filter for %d\n", vlan_id);
1840 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1841 uint16_t vlan_id, int on)
1843 struct bnxt *bp = eth_dev->data->dev_private;
1846 rc = is_bnxt_in_error(bp);
1850 /* These operations apply to ALL existing MAC/VLAN filters */
1852 return bnxt_add_vlan_filter(bp, vlan_id);
1854 return bnxt_del_vlan_filter(bp, vlan_id);
1857 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
1858 struct bnxt_vnic_info *vnic)
1860 struct bnxt_filter_info *filter;
1863 filter = STAILQ_FIRST(&vnic->filter);
1865 if (filter->mac_index == 0 &&
1866 !memcmp(filter->l2_addr, bp->mac_addr,
1867 RTE_ETHER_ADDR_LEN)) {
1868 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1870 STAILQ_REMOVE(&vnic->filter, filter,
1871 bnxt_filter_info, next);
1872 bnxt_free_filter(bp, filter);
1876 filter = STAILQ_NEXT(filter, next);
1882 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
1884 struct bnxt_vnic_info *vnic;
1888 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1889 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1890 /* Remove any VLAN filters programmed */
1891 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1892 bnxt_del_vlan_filter(bp, i);
1894 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1898 /* Default filter will allow packets that match the
1899 * dest mac. So, it has to be deleted, otherwise, we
1900 * will endup receiving vlan packets for which the
1901 * filter is not programmed, when hw-vlan-filter
1902 * configuration is ON
1904 bnxt_del_dflt_mac_filter(bp, vnic);
1905 /* This filter will allow only untagged packets */
1906 bnxt_add_vlan_filter(bp, 0);
1908 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1909 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1914 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
1916 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
1920 /* Destroy vnic filters and vnic */
1921 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
1922 DEV_RX_OFFLOAD_VLAN_FILTER) {
1923 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1924 bnxt_del_vlan_filter(bp, i);
1926 bnxt_del_dflt_mac_filter(bp, vnic);
1928 rc = bnxt_hwrm_vnic_free(bp, vnic);
1932 rte_free(vnic->fw_grp_ids);
1933 vnic->fw_grp_ids = NULL;
1939 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
1941 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1944 /* Destroy, recreate and reconfigure the default vnic */
1945 rc = bnxt_free_one_vnic(bp, 0);
1949 /* default vnic 0 */
1950 rc = bnxt_setup_one_vnic(bp, 0);
1954 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
1955 DEV_RX_OFFLOAD_VLAN_FILTER) {
1956 rc = bnxt_add_vlan_filter(bp, 0);
1957 bnxt_restore_vlan_filters(bp);
1959 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1962 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1966 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1967 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1973 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1975 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1976 struct bnxt *bp = dev->data->dev_private;
1979 rc = is_bnxt_in_error(bp);
1983 /* Filter settings will get applied when port is started */
1984 if (bp->dev_stopped == 1)
1987 if (mask & ETH_VLAN_FILTER_MASK) {
1988 /* Enable or disable VLAN filtering */
1989 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
1994 if (mask & ETH_VLAN_STRIP_MASK) {
1995 /* Enable or disable VLAN stripping */
1996 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2001 if (mask & ETH_VLAN_EXTEND_MASK) {
2002 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2003 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2005 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2012 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2015 struct bnxt *bp = dev->data->dev_private;
2016 int qinq = dev->data->dev_conf.rxmode.offloads &
2017 DEV_RX_OFFLOAD_VLAN_EXTEND;
2019 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2020 vlan_type != ETH_VLAN_TYPE_OUTER) {
2022 "Unsupported vlan type.");
2027 "QinQ not enabled. Needs to be ON as we can "
2028 "accelerate only outer vlan\n");
2032 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2034 case RTE_ETHER_TYPE_QINQ:
2036 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2038 case RTE_ETHER_TYPE_VLAN:
2040 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2044 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2048 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2052 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2055 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2058 bp->outer_tpid_bd |= tpid;
2059 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2060 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2062 "Can accelerate only outer vlan in QinQ\n");
2070 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2071 struct rte_ether_addr *addr)
2073 struct bnxt *bp = dev->data->dev_private;
2074 /* Default Filter is tied to VNIC 0 */
2075 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2078 rc = is_bnxt_in_error(bp);
2082 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2085 if (rte_is_zero_ether_addr(addr))
2088 /* Check if the requested MAC is already added */
2089 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2092 /* Destroy filter and re-create it */
2093 bnxt_del_dflt_mac_filter(bp, vnic);
2095 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2096 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2097 /* This filter will allow only untagged packets */
2098 rc = bnxt_add_vlan_filter(bp, 0);
2100 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2103 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2108 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2109 struct rte_ether_addr *mc_addr_set,
2110 uint32_t nb_mc_addr)
2112 struct bnxt *bp = eth_dev->data->dev_private;
2113 char *mc_addr_list = (char *)mc_addr_set;
2114 struct bnxt_vnic_info *vnic;
2115 uint32_t off = 0, i = 0;
2118 rc = is_bnxt_in_error(bp);
2122 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2124 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2125 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2129 /* TODO Check for Duplicate mcast addresses */
2130 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2131 for (i = 0; i < nb_mc_addr; i++) {
2132 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2133 RTE_ETHER_ADDR_LEN);
2134 off += RTE_ETHER_ADDR_LEN;
2137 vnic->mc_addr_cnt = i;
2138 if (vnic->mc_addr_cnt)
2139 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2141 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2144 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2148 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2150 struct bnxt *bp = dev->data->dev_private;
2151 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2152 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2153 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2156 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2157 fw_major, fw_minor, fw_updt);
2159 ret += 1; /* add the size of '\0' */
2160 if (fw_size < (uint32_t)ret)
2167 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2168 struct rte_eth_rxq_info *qinfo)
2170 struct bnxt *bp = dev->data->dev_private;
2171 struct bnxt_rx_queue *rxq;
2173 if (is_bnxt_in_error(bp))
2176 rxq = dev->data->rx_queues[queue_id];
2178 qinfo->mp = rxq->mb_pool;
2179 qinfo->scattered_rx = dev->data->scattered_rx;
2180 qinfo->nb_desc = rxq->nb_rx_desc;
2182 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2183 qinfo->conf.rx_drop_en = 0;
2184 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2188 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2189 struct rte_eth_txq_info *qinfo)
2191 struct bnxt *bp = dev->data->dev_private;
2192 struct bnxt_tx_queue *txq;
2194 if (is_bnxt_in_error(bp))
2197 txq = dev->data->tx_queues[queue_id];
2199 qinfo->nb_desc = txq->nb_tx_desc;
2201 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2202 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2203 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2205 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2206 qinfo->conf.tx_rs_thresh = 0;
2207 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2210 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2212 struct bnxt *bp = eth_dev->data->dev_private;
2213 uint32_t new_pkt_size;
2217 rc = is_bnxt_in_error(bp);
2221 /* Exit if receive queues are not configured yet */
2222 if (!eth_dev->data->nb_rx_queues)
2225 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2226 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2230 * If vector-mode tx/rx is active, disallow any MTU change that would
2231 * require scattered receive support.
2233 if (eth_dev->data->dev_started &&
2234 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2235 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2237 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2239 "MTU change would require scattered rx support. ");
2240 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2245 if (new_mtu > RTE_ETHER_MTU) {
2246 bp->flags |= BNXT_FLAG_JUMBO;
2247 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2248 DEV_RX_OFFLOAD_JUMBO_FRAME;
2250 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2251 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2252 bp->flags &= ~BNXT_FLAG_JUMBO;
2255 /* Is there a change in mtu setting? */
2256 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2259 for (i = 0; i < bp->nr_vnics; i++) {
2260 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2263 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2264 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2268 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2269 size -= RTE_PKTMBUF_HEADROOM;
2271 if (size < new_mtu) {
2272 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2279 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2281 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2287 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2289 struct bnxt *bp = dev->data->dev_private;
2290 uint16_t vlan = bp->vlan;
2293 rc = is_bnxt_in_error(bp);
2297 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2299 "PVID cannot be modified for this function\n");
2302 bp->vlan = on ? pvid : 0;
2304 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2311 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2313 struct bnxt *bp = dev->data->dev_private;
2316 rc = is_bnxt_in_error(bp);
2320 return bnxt_hwrm_port_led_cfg(bp, true);
2324 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2326 struct bnxt *bp = dev->data->dev_private;
2329 rc = is_bnxt_in_error(bp);
2333 return bnxt_hwrm_port_led_cfg(bp, false);
2337 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2339 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2340 uint32_t desc = 0, raw_cons = 0, cons;
2341 struct bnxt_cp_ring_info *cpr;
2342 struct bnxt_rx_queue *rxq;
2343 struct rx_pkt_cmpl *rxcmp;
2346 rc = is_bnxt_in_error(bp);
2350 rxq = dev->data->rx_queues[rx_queue_id];
2352 raw_cons = cpr->cp_raw_cons;
2355 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2356 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2357 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2359 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2371 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2373 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2374 struct bnxt_rx_ring_info *rxr;
2375 struct bnxt_cp_ring_info *cpr;
2376 struct bnxt_sw_rx_bd *rx_buf;
2377 struct rx_pkt_cmpl *rxcmp;
2378 uint32_t cons, cp_cons;
2384 rc = is_bnxt_in_error(rxq->bp);
2391 if (offset >= rxq->nb_rx_desc)
2394 cons = RING_CMP(cpr->cp_ring_struct, offset);
2395 cp_cons = cpr->cp_raw_cons;
2396 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2398 if (cons > cp_cons) {
2399 if (CMPL_VALID(rxcmp, cpr->valid))
2400 return RTE_ETH_RX_DESC_DONE;
2402 if (CMPL_VALID(rxcmp, !cpr->valid))
2403 return RTE_ETH_RX_DESC_DONE;
2405 rx_buf = &rxr->rx_buf_ring[cons];
2406 if (rx_buf->mbuf == NULL)
2407 return RTE_ETH_RX_DESC_UNAVAIL;
2410 return RTE_ETH_RX_DESC_AVAIL;
2414 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2416 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2417 struct bnxt_tx_ring_info *txr;
2418 struct bnxt_cp_ring_info *cpr;
2419 struct bnxt_sw_tx_bd *tx_buf;
2420 struct tx_pkt_cmpl *txcmp;
2421 uint32_t cons, cp_cons;
2427 rc = is_bnxt_in_error(txq->bp);
2434 if (offset >= txq->nb_tx_desc)
2437 cons = RING_CMP(cpr->cp_ring_struct, offset);
2438 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2439 cp_cons = cpr->cp_raw_cons;
2441 if (cons > cp_cons) {
2442 if (CMPL_VALID(txcmp, cpr->valid))
2443 return RTE_ETH_TX_DESC_UNAVAIL;
2445 if (CMPL_VALID(txcmp, !cpr->valid))
2446 return RTE_ETH_TX_DESC_UNAVAIL;
2448 tx_buf = &txr->tx_buf_ring[cons];
2449 if (tx_buf->mbuf == NULL)
2450 return RTE_ETH_TX_DESC_DONE;
2452 return RTE_ETH_TX_DESC_FULL;
2455 static struct bnxt_filter_info *
2456 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2457 struct rte_eth_ethertype_filter *efilter,
2458 struct bnxt_vnic_info *vnic0,
2459 struct bnxt_vnic_info *vnic,
2462 struct bnxt_filter_info *mfilter = NULL;
2466 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2467 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2468 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2469 " ethertype filter.", efilter->ether_type);
2473 if (efilter->queue >= bp->rx_nr_rings) {
2474 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2479 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2480 vnic = &bp->vnic_info[efilter->queue];
2482 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2487 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2488 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2489 if ((!memcmp(efilter->mac_addr.addr_bytes,
2490 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2492 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2493 mfilter->ethertype == efilter->ether_type)) {
2499 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2500 if ((!memcmp(efilter->mac_addr.addr_bytes,
2501 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2502 mfilter->ethertype == efilter->ether_type &&
2504 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2518 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2519 enum rte_filter_op filter_op,
2522 struct bnxt *bp = dev->data->dev_private;
2523 struct rte_eth_ethertype_filter *efilter =
2524 (struct rte_eth_ethertype_filter *)arg;
2525 struct bnxt_filter_info *bfilter, *filter1;
2526 struct bnxt_vnic_info *vnic, *vnic0;
2529 if (filter_op == RTE_ETH_FILTER_NOP)
2533 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2538 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2539 vnic = &bp->vnic_info[efilter->queue];
2541 switch (filter_op) {
2542 case RTE_ETH_FILTER_ADD:
2543 bnxt_match_and_validate_ether_filter(bp, efilter,
2548 bfilter = bnxt_get_unused_filter(bp);
2549 if (bfilter == NULL) {
2551 "Not enough resources for a new filter.\n");
2554 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2555 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2556 RTE_ETHER_ADDR_LEN);
2557 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2558 RTE_ETHER_ADDR_LEN);
2559 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2560 bfilter->ethertype = efilter->ether_type;
2561 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2563 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2564 if (filter1 == NULL) {
2569 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2570 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2572 bfilter->dst_id = vnic->fw_vnic_id;
2574 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2576 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2579 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2582 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2584 case RTE_ETH_FILTER_DELETE:
2585 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2587 if (ret == -EEXIST) {
2588 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2590 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2592 bnxt_free_filter(bp, filter1);
2593 } else if (ret == 0) {
2594 PMD_DRV_LOG(ERR, "No matching filter found\n");
2598 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2604 bnxt_free_filter(bp, bfilter);
2610 parse_ntuple_filter(struct bnxt *bp,
2611 struct rte_eth_ntuple_filter *nfilter,
2612 struct bnxt_filter_info *bfilter)
2616 if (nfilter->queue >= bp->rx_nr_rings) {
2617 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2621 switch (nfilter->dst_port_mask) {
2623 bfilter->dst_port_mask = -1;
2624 bfilter->dst_port = nfilter->dst_port;
2625 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2626 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2629 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2633 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2634 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2636 switch (nfilter->proto_mask) {
2638 if (nfilter->proto == 17) /* IPPROTO_UDP */
2639 bfilter->ip_protocol = 17;
2640 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2641 bfilter->ip_protocol = 6;
2644 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2647 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2651 switch (nfilter->dst_ip_mask) {
2653 bfilter->dst_ipaddr_mask[0] = -1;
2654 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2655 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2656 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2659 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2663 switch (nfilter->src_ip_mask) {
2665 bfilter->src_ipaddr_mask[0] = -1;
2666 bfilter->src_ipaddr[0] = nfilter->src_ip;
2667 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2668 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2671 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2675 switch (nfilter->src_port_mask) {
2677 bfilter->src_port_mask = -1;
2678 bfilter->src_port = nfilter->src_port;
2679 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2680 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2683 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2687 bfilter->enables = en;
2691 static struct bnxt_filter_info*
2692 bnxt_match_ntuple_filter(struct bnxt *bp,
2693 struct bnxt_filter_info *bfilter,
2694 struct bnxt_vnic_info **mvnic)
2696 struct bnxt_filter_info *mfilter = NULL;
2699 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2700 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2701 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2702 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2703 bfilter->src_ipaddr_mask[0] ==
2704 mfilter->src_ipaddr_mask[0] &&
2705 bfilter->src_port == mfilter->src_port &&
2706 bfilter->src_port_mask == mfilter->src_port_mask &&
2707 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2708 bfilter->dst_ipaddr_mask[0] ==
2709 mfilter->dst_ipaddr_mask[0] &&
2710 bfilter->dst_port == mfilter->dst_port &&
2711 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2712 bfilter->flags == mfilter->flags &&
2713 bfilter->enables == mfilter->enables) {
2724 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2725 struct rte_eth_ntuple_filter *nfilter,
2726 enum rte_filter_op filter_op)
2728 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2729 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2732 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2733 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2737 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2738 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2742 bfilter = bnxt_get_unused_filter(bp);
2743 if (bfilter == NULL) {
2745 "Not enough resources for a new filter.\n");
2748 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2752 vnic = &bp->vnic_info[nfilter->queue];
2753 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2754 filter1 = STAILQ_FIRST(&vnic0->filter);
2755 if (filter1 == NULL) {
2760 bfilter->dst_id = vnic->fw_vnic_id;
2761 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2763 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2764 bfilter->ethertype = 0x800;
2765 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2767 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2769 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2770 bfilter->dst_id == mfilter->dst_id) {
2771 PMD_DRV_LOG(ERR, "filter exists.\n");
2774 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2775 bfilter->dst_id != mfilter->dst_id) {
2776 mfilter->dst_id = vnic->fw_vnic_id;
2777 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2778 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2779 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2780 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2781 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2784 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2785 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2790 if (filter_op == RTE_ETH_FILTER_ADD) {
2791 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2792 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2795 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2797 if (mfilter == NULL) {
2798 /* This should not happen. But for Coverity! */
2802 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2804 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2805 bnxt_free_filter(bp, mfilter);
2806 bnxt_free_filter(bp, bfilter);
2811 bnxt_free_filter(bp, bfilter);
2816 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2817 enum rte_filter_op filter_op,
2820 struct bnxt *bp = dev->data->dev_private;
2823 if (filter_op == RTE_ETH_FILTER_NOP)
2827 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2832 switch (filter_op) {
2833 case RTE_ETH_FILTER_ADD:
2834 ret = bnxt_cfg_ntuple_filter(bp,
2835 (struct rte_eth_ntuple_filter *)arg,
2838 case RTE_ETH_FILTER_DELETE:
2839 ret = bnxt_cfg_ntuple_filter(bp,
2840 (struct rte_eth_ntuple_filter *)arg,
2844 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2852 bnxt_parse_fdir_filter(struct bnxt *bp,
2853 struct rte_eth_fdir_filter *fdir,
2854 struct bnxt_filter_info *filter)
2856 enum rte_fdir_mode fdir_mode =
2857 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2858 struct bnxt_vnic_info *vnic0, *vnic;
2859 struct bnxt_filter_info *filter1;
2863 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2866 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2867 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2869 switch (fdir->input.flow_type) {
2870 case RTE_ETH_FLOW_IPV4:
2871 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2873 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2874 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2875 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2876 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2877 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2878 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2879 filter->ip_addr_type =
2880 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2881 filter->src_ipaddr_mask[0] = 0xffffffff;
2882 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2883 filter->dst_ipaddr_mask[0] = 0xffffffff;
2884 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2885 filter->ethertype = 0x800;
2886 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2888 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2889 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2890 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2891 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2892 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2893 filter->dst_port_mask = 0xffff;
2894 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2895 filter->src_port_mask = 0xffff;
2896 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2897 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2898 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2899 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2900 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2901 filter->ip_protocol = 6;
2902 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2903 filter->ip_addr_type =
2904 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2905 filter->src_ipaddr_mask[0] = 0xffffffff;
2906 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2907 filter->dst_ipaddr_mask[0] = 0xffffffff;
2908 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2909 filter->ethertype = 0x800;
2910 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2912 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2913 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2914 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2915 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2916 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2917 filter->dst_port_mask = 0xffff;
2918 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2919 filter->src_port_mask = 0xffff;
2920 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2921 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2922 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2923 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2924 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2925 filter->ip_protocol = 17;
2926 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2927 filter->ip_addr_type =
2928 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2929 filter->src_ipaddr_mask[0] = 0xffffffff;
2930 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2931 filter->dst_ipaddr_mask[0] = 0xffffffff;
2932 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2933 filter->ethertype = 0x800;
2934 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2936 case RTE_ETH_FLOW_IPV6:
2937 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2939 filter->ip_addr_type =
2940 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2941 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2942 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2943 rte_memcpy(filter->src_ipaddr,
2944 fdir->input.flow.ipv6_flow.src_ip, 16);
2945 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2946 rte_memcpy(filter->dst_ipaddr,
2947 fdir->input.flow.ipv6_flow.dst_ip, 16);
2948 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2949 memset(filter->dst_ipaddr_mask, 0xff, 16);
2950 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2951 memset(filter->src_ipaddr_mask, 0xff, 16);
2952 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2953 filter->ethertype = 0x86dd;
2954 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2956 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2957 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2958 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2959 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2960 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2961 filter->dst_port_mask = 0xffff;
2962 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2963 filter->src_port_mask = 0xffff;
2964 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2965 filter->ip_addr_type =
2966 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2967 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2968 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2969 rte_memcpy(filter->src_ipaddr,
2970 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2971 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2972 rte_memcpy(filter->dst_ipaddr,
2973 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2974 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2975 memset(filter->dst_ipaddr_mask, 0xff, 16);
2976 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2977 memset(filter->src_ipaddr_mask, 0xff, 16);
2978 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2979 filter->ethertype = 0x86dd;
2980 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2982 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2983 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2984 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2985 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2986 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2987 filter->dst_port_mask = 0xffff;
2988 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2989 filter->src_port_mask = 0xffff;
2990 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2991 filter->ip_addr_type =
2992 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2993 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2994 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2995 rte_memcpy(filter->src_ipaddr,
2996 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2997 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2998 rte_memcpy(filter->dst_ipaddr,
2999 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3000 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3001 memset(filter->dst_ipaddr_mask, 0xff, 16);
3002 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3003 memset(filter->src_ipaddr_mask, 0xff, 16);
3004 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3005 filter->ethertype = 0x86dd;
3006 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3008 case RTE_ETH_FLOW_L2_PAYLOAD:
3009 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3010 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3012 case RTE_ETH_FLOW_VXLAN:
3013 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3015 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3016 filter->tunnel_type =
3017 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3018 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3020 case RTE_ETH_FLOW_NVGRE:
3021 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3023 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3024 filter->tunnel_type =
3025 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3026 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3028 case RTE_ETH_FLOW_UNKNOWN:
3029 case RTE_ETH_FLOW_RAW:
3030 case RTE_ETH_FLOW_FRAG_IPV4:
3031 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3032 case RTE_ETH_FLOW_FRAG_IPV6:
3033 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3034 case RTE_ETH_FLOW_IPV6_EX:
3035 case RTE_ETH_FLOW_IPV6_TCP_EX:
3036 case RTE_ETH_FLOW_IPV6_UDP_EX:
3037 case RTE_ETH_FLOW_GENEVE:
3043 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3044 vnic = &bp->vnic_info[fdir->action.rx_queue];
3046 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3050 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3051 rte_memcpy(filter->dst_macaddr,
3052 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3053 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3056 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3057 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3058 filter1 = STAILQ_FIRST(&vnic0->filter);
3059 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3061 filter->dst_id = vnic->fw_vnic_id;
3062 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3063 if (filter->dst_macaddr[i] == 0x00)
3064 filter1 = STAILQ_FIRST(&vnic0->filter);
3066 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3069 if (filter1 == NULL)
3072 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3073 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3075 filter->enables = en;
3080 static struct bnxt_filter_info *
3081 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3082 struct bnxt_vnic_info **mvnic)
3084 struct bnxt_filter_info *mf = NULL;
3087 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3088 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3090 STAILQ_FOREACH(mf, &vnic->filter, next) {
3091 if (mf->filter_type == nf->filter_type &&
3092 mf->flags == nf->flags &&
3093 mf->src_port == nf->src_port &&
3094 mf->src_port_mask == nf->src_port_mask &&
3095 mf->dst_port == nf->dst_port &&
3096 mf->dst_port_mask == nf->dst_port_mask &&
3097 mf->ip_protocol == nf->ip_protocol &&
3098 mf->ip_addr_type == nf->ip_addr_type &&
3099 mf->ethertype == nf->ethertype &&
3100 mf->vni == nf->vni &&
3101 mf->tunnel_type == nf->tunnel_type &&
3102 mf->l2_ovlan == nf->l2_ovlan &&
3103 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3104 mf->l2_ivlan == nf->l2_ivlan &&
3105 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3106 !memcmp(mf->l2_addr, nf->l2_addr,
3107 RTE_ETHER_ADDR_LEN) &&
3108 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3109 RTE_ETHER_ADDR_LEN) &&
3110 !memcmp(mf->src_macaddr, nf->src_macaddr,
3111 RTE_ETHER_ADDR_LEN) &&
3112 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3113 RTE_ETHER_ADDR_LEN) &&
3114 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3115 sizeof(nf->src_ipaddr)) &&
3116 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3117 sizeof(nf->src_ipaddr_mask)) &&
3118 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3119 sizeof(nf->dst_ipaddr)) &&
3120 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3121 sizeof(nf->dst_ipaddr_mask))) {
3132 bnxt_fdir_filter(struct rte_eth_dev *dev,
3133 enum rte_filter_op filter_op,
3136 struct bnxt *bp = dev->data->dev_private;
3137 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
3138 struct bnxt_filter_info *filter, *match;
3139 struct bnxt_vnic_info *vnic, *mvnic;
3142 if (filter_op == RTE_ETH_FILTER_NOP)
3145 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3148 switch (filter_op) {
3149 case RTE_ETH_FILTER_ADD:
3150 case RTE_ETH_FILTER_DELETE:
3152 filter = bnxt_get_unused_filter(bp);
3153 if (filter == NULL) {
3155 "Not enough resources for a new flow.\n");
3159 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3162 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3164 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3165 vnic = &bp->vnic_info[0];
3167 vnic = &bp->vnic_info[fdir->action.rx_queue];
3169 match = bnxt_match_fdir(bp, filter, &mvnic);
3170 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3171 if (match->dst_id == vnic->fw_vnic_id) {
3172 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3176 match->dst_id = vnic->fw_vnic_id;
3177 ret = bnxt_hwrm_set_ntuple_filter(bp,
3180 STAILQ_REMOVE(&mvnic->filter, match,
3181 bnxt_filter_info, next);
3182 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3184 "Filter with matching pattern exist\n");
3186 "Updated it to new destination q\n");
3190 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3191 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3196 if (filter_op == RTE_ETH_FILTER_ADD) {
3197 ret = bnxt_hwrm_set_ntuple_filter(bp,
3202 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3204 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3205 STAILQ_REMOVE(&vnic->filter, match,
3206 bnxt_filter_info, next);
3207 bnxt_free_filter(bp, match);
3208 bnxt_free_filter(bp, filter);
3211 case RTE_ETH_FILTER_FLUSH:
3212 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3213 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3215 STAILQ_FOREACH(filter, &vnic->filter, next) {
3216 if (filter->filter_type ==
3217 HWRM_CFA_NTUPLE_FILTER) {
3219 bnxt_hwrm_clear_ntuple_filter(bp,
3221 STAILQ_REMOVE(&vnic->filter, filter,
3222 bnxt_filter_info, next);
3227 case RTE_ETH_FILTER_UPDATE:
3228 case RTE_ETH_FILTER_STATS:
3229 case RTE_ETH_FILTER_INFO:
3230 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3233 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3240 bnxt_free_filter(bp, filter);
3245 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3246 enum rte_filter_type filter_type,
3247 enum rte_filter_op filter_op, void *arg)
3251 ret = is_bnxt_in_error(dev->data->dev_private);
3255 switch (filter_type) {
3256 case RTE_ETH_FILTER_TUNNEL:
3258 "filter type: %d: To be implemented\n", filter_type);
3260 case RTE_ETH_FILTER_FDIR:
3261 ret = bnxt_fdir_filter(dev, filter_op, arg);
3263 case RTE_ETH_FILTER_NTUPLE:
3264 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3266 case RTE_ETH_FILTER_ETHERTYPE:
3267 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3269 case RTE_ETH_FILTER_GENERIC:
3270 if (filter_op != RTE_ETH_FILTER_GET)
3272 *(const void **)arg = &bnxt_flow_ops;
3276 "Filter type (%d) not supported", filter_type);
3283 static const uint32_t *
3284 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3286 static const uint32_t ptypes[] = {
3287 RTE_PTYPE_L2_ETHER_VLAN,
3288 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3289 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3293 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3294 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3295 RTE_PTYPE_INNER_L4_ICMP,
3296 RTE_PTYPE_INNER_L4_TCP,
3297 RTE_PTYPE_INNER_L4_UDP,
3301 if (!dev->rx_pkt_burst)
3307 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3310 uint32_t reg_base = *reg_arr & 0xfffff000;
3314 for (i = 0; i < count; i++) {
3315 if ((reg_arr[i] & 0xfffff000) != reg_base)
3318 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3319 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3323 static int bnxt_map_ptp_regs(struct bnxt *bp)
3325 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3329 reg_arr = ptp->rx_regs;
3330 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3334 reg_arr = ptp->tx_regs;
3335 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3339 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3340 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3342 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3343 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3348 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3350 rte_write32(0, (uint8_t *)bp->bar0 +
3351 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3352 rte_write32(0, (uint8_t *)bp->bar0 +
3353 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3356 static uint64_t bnxt_cc_read(struct bnxt *bp)
3360 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3361 BNXT_GRCPF_REG_SYNC_TIME));
3362 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3363 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3367 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3369 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3372 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3373 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3374 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3377 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3378 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3379 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3380 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3381 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3382 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3387 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3389 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3390 struct bnxt_pf_info *pf = &bp->pf;
3397 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3398 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3399 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3402 port_id = pf->port_id;
3403 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3404 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3406 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3407 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3408 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3409 /* bnxt_clr_rx_ts(bp); TBD */
3413 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3414 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3415 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3416 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3422 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3425 struct bnxt *bp = dev->data->dev_private;
3426 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3431 ns = rte_timespec_to_ns(ts);
3432 /* Set the timecounters to a new value. */
3439 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3441 struct bnxt *bp = dev->data->dev_private;
3442 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3443 uint64_t ns, systime_cycles = 0;
3449 if (BNXT_CHIP_THOR(bp))
3450 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3453 systime_cycles = bnxt_cc_read(bp);
3455 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3456 *ts = rte_ns_to_timespec(ns);
3461 bnxt_timesync_enable(struct rte_eth_dev *dev)
3463 struct bnxt *bp = dev->data->dev_private;
3464 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3472 ptp->tx_tstamp_en = 1;
3473 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3475 rc = bnxt_hwrm_ptp_cfg(bp);
3479 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3480 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3481 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3483 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3484 ptp->tc.cc_shift = shift;
3485 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3487 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3488 ptp->rx_tstamp_tc.cc_shift = shift;
3489 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3491 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3492 ptp->tx_tstamp_tc.cc_shift = shift;
3493 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3495 if (!BNXT_CHIP_THOR(bp))
3496 bnxt_map_ptp_regs(bp);
3502 bnxt_timesync_disable(struct rte_eth_dev *dev)
3504 struct bnxt *bp = dev->data->dev_private;
3505 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3511 ptp->tx_tstamp_en = 0;
3514 bnxt_hwrm_ptp_cfg(bp);
3516 if (!BNXT_CHIP_THOR(bp))
3517 bnxt_unmap_ptp_regs(bp);
3523 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3524 struct timespec *timestamp,
3525 uint32_t flags __rte_unused)
3527 struct bnxt *bp = dev->data->dev_private;
3528 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3529 uint64_t rx_tstamp_cycles = 0;
3535 if (BNXT_CHIP_THOR(bp))
3536 rx_tstamp_cycles = ptp->rx_timestamp;
3538 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3540 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3541 *timestamp = rte_ns_to_timespec(ns);
3546 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3547 struct timespec *timestamp)
3549 struct bnxt *bp = dev->data->dev_private;
3550 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3551 uint64_t tx_tstamp_cycles = 0;
3558 if (BNXT_CHIP_THOR(bp))
3559 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3562 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3564 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3565 *timestamp = rte_ns_to_timespec(ns);
3571 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3573 struct bnxt *bp = dev->data->dev_private;
3574 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3579 ptp->tc.nsec += delta;
3585 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3587 struct bnxt *bp = dev->data->dev_private;
3589 uint32_t dir_entries;
3590 uint32_t entry_length;
3592 rc = is_bnxt_in_error(bp);
3596 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3597 bp->pdev->addr.domain, bp->pdev->addr.bus,
3598 bp->pdev->addr.devid, bp->pdev->addr.function);
3600 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3604 return dir_entries * entry_length;
3608 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3609 struct rte_dev_eeprom_info *in_eeprom)
3611 struct bnxt *bp = dev->data->dev_private;
3616 rc = is_bnxt_in_error(bp);
3620 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3621 bp->pdev->addr.domain, bp->pdev->addr.bus,
3622 bp->pdev->addr.devid, bp->pdev->addr.function,
3623 in_eeprom->offset, in_eeprom->length);
3625 if (in_eeprom->offset == 0) /* special offset value to get directory */
3626 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3629 index = in_eeprom->offset >> 24;
3630 offset = in_eeprom->offset & 0xffffff;
3633 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3634 in_eeprom->length, in_eeprom->data);
3639 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3642 case BNX_DIR_TYPE_CHIMP_PATCH:
3643 case BNX_DIR_TYPE_BOOTCODE:
3644 case BNX_DIR_TYPE_BOOTCODE_2:
3645 case BNX_DIR_TYPE_APE_FW:
3646 case BNX_DIR_TYPE_APE_PATCH:
3647 case BNX_DIR_TYPE_KONG_FW:
3648 case BNX_DIR_TYPE_KONG_PATCH:
3649 case BNX_DIR_TYPE_BONO_FW:
3650 case BNX_DIR_TYPE_BONO_PATCH:
3658 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3661 case BNX_DIR_TYPE_AVS:
3662 case BNX_DIR_TYPE_EXP_ROM_MBA:
3663 case BNX_DIR_TYPE_PCIE:
3664 case BNX_DIR_TYPE_TSCF_UCODE:
3665 case BNX_DIR_TYPE_EXT_PHY:
3666 case BNX_DIR_TYPE_CCM:
3667 case BNX_DIR_TYPE_ISCSI_BOOT:
3668 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3669 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3677 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3679 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3680 bnxt_dir_type_is_other_exec_format(dir_type);
3684 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3685 struct rte_dev_eeprom_info *in_eeprom)
3687 struct bnxt *bp = dev->data->dev_private;
3688 uint8_t index, dir_op;
3689 uint16_t type, ext, ordinal, attr;
3692 rc = is_bnxt_in_error(bp);
3696 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3697 bp->pdev->addr.domain, bp->pdev->addr.bus,
3698 bp->pdev->addr.devid, bp->pdev->addr.function,
3699 in_eeprom->offset, in_eeprom->length);
3702 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3706 type = in_eeprom->magic >> 16;
3708 if (type == 0xffff) { /* special value for directory operations */
3709 index = in_eeprom->magic & 0xff;
3710 dir_op = in_eeprom->magic >> 8;
3714 case 0x0e: /* erase */
3715 if (in_eeprom->offset != ~in_eeprom->magic)
3717 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3723 /* Create or re-write an NVM item: */
3724 if (bnxt_dir_type_is_executable(type) == true)
3726 ext = in_eeprom->magic & 0xffff;
3727 ordinal = in_eeprom->offset >> 16;
3728 attr = in_eeprom->offset & 0xffff;
3730 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3731 in_eeprom->data, in_eeprom->length);
3738 static const struct eth_dev_ops bnxt_dev_ops = {
3739 .dev_infos_get = bnxt_dev_info_get_op,
3740 .dev_close = bnxt_dev_close_op,
3741 .dev_configure = bnxt_dev_configure_op,
3742 .dev_start = bnxt_dev_start_op,
3743 .dev_stop = bnxt_dev_stop_op,
3744 .dev_set_link_up = bnxt_dev_set_link_up_op,
3745 .dev_set_link_down = bnxt_dev_set_link_down_op,
3746 .stats_get = bnxt_stats_get_op,
3747 .stats_reset = bnxt_stats_reset_op,
3748 .rx_queue_setup = bnxt_rx_queue_setup_op,
3749 .rx_queue_release = bnxt_rx_queue_release_op,
3750 .tx_queue_setup = bnxt_tx_queue_setup_op,
3751 .tx_queue_release = bnxt_tx_queue_release_op,
3752 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3753 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3754 .reta_update = bnxt_reta_update_op,
3755 .reta_query = bnxt_reta_query_op,
3756 .rss_hash_update = bnxt_rss_hash_update_op,
3757 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3758 .link_update = bnxt_link_update_op,
3759 .promiscuous_enable = bnxt_promiscuous_enable_op,
3760 .promiscuous_disable = bnxt_promiscuous_disable_op,
3761 .allmulticast_enable = bnxt_allmulticast_enable_op,
3762 .allmulticast_disable = bnxt_allmulticast_disable_op,
3763 .mac_addr_add = bnxt_mac_addr_add_op,
3764 .mac_addr_remove = bnxt_mac_addr_remove_op,
3765 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3766 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3767 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3768 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3769 .vlan_filter_set = bnxt_vlan_filter_set_op,
3770 .vlan_offload_set = bnxt_vlan_offload_set_op,
3771 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3772 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3773 .mtu_set = bnxt_mtu_set_op,
3774 .mac_addr_set = bnxt_set_default_mac_addr_op,
3775 .xstats_get = bnxt_dev_xstats_get_op,
3776 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3777 .xstats_reset = bnxt_dev_xstats_reset_op,
3778 .fw_version_get = bnxt_fw_version_get,
3779 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3780 .rxq_info_get = bnxt_rxq_info_get_op,
3781 .txq_info_get = bnxt_txq_info_get_op,
3782 .dev_led_on = bnxt_dev_led_on_op,
3783 .dev_led_off = bnxt_dev_led_off_op,
3784 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3785 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3786 .rx_queue_count = bnxt_rx_queue_count_op,
3787 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3788 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3789 .rx_queue_start = bnxt_rx_queue_start,
3790 .rx_queue_stop = bnxt_rx_queue_stop,
3791 .tx_queue_start = bnxt_tx_queue_start,
3792 .tx_queue_stop = bnxt_tx_queue_stop,
3793 .filter_ctrl = bnxt_filter_ctrl_op,
3794 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3795 .get_eeprom_length = bnxt_get_eeprom_length_op,
3796 .get_eeprom = bnxt_get_eeprom_op,
3797 .set_eeprom = bnxt_set_eeprom_op,
3798 .timesync_enable = bnxt_timesync_enable,
3799 .timesync_disable = bnxt_timesync_disable,
3800 .timesync_read_time = bnxt_timesync_read_time,
3801 .timesync_write_time = bnxt_timesync_write_time,
3802 .timesync_adjust_time = bnxt_timesync_adjust_time,
3803 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3804 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3807 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3811 /* Only pre-map the reset GRC registers using window 3 */
3812 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3813 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3815 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3820 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3822 struct bnxt_error_recovery_info *info = bp->recovery_info;
3823 uint32_t reg_base = 0xffffffff;
3826 /* Only pre-map the monitoring GRC registers using window 2 */
3827 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3828 uint32_t reg = info->status_regs[i];
3830 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3833 if (reg_base == 0xffffffff)
3834 reg_base = reg & 0xfffff000;
3835 if ((reg & 0xfffff000) != reg_base)
3838 /* Use mask 0xffc as the Lower 2 bits indicates
3839 * address space location
3841 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3845 if (reg_base == 0xffffffff)
3848 rte_write32(reg_base, (uint8_t *)bp->bar0 +
3849 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3854 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3856 struct bnxt_error_recovery_info *info = bp->recovery_info;
3857 uint32_t delay = info->delay_after_reset[index];
3858 uint32_t val = info->reset_reg_val[index];
3859 uint32_t reg = info->reset_reg[index];
3860 uint32_t type, offset;
3862 type = BNXT_FW_STATUS_REG_TYPE(reg);
3863 offset = BNXT_FW_STATUS_REG_OFF(reg);
3866 case BNXT_FW_STATUS_REG_TYPE_CFG:
3867 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3869 case BNXT_FW_STATUS_REG_TYPE_GRC:
3870 offset = bnxt_map_reset_regs(bp, offset);
3871 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3873 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3874 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3877 /* wait on a specific interval of time until core reset is complete */
3879 rte_delay_ms(delay);
3882 static void bnxt_dev_cleanup(struct bnxt *bp)
3884 bnxt_set_hwrm_link_config(bp, false);
3885 bp->link_info.link_up = 0;
3886 if (bp->dev_stopped == 0)
3887 bnxt_dev_stop_op(bp->eth_dev);
3889 bnxt_uninit_resources(bp, true);
3892 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3894 struct rte_eth_dev *dev = bp->eth_dev;
3895 struct rte_vlan_filter_conf *vfc;
3899 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3900 vfc = &dev->data->vlan_filter_conf;
3901 vidx = vlan_id / 64;
3902 vbit = vlan_id % 64;
3904 /* Each bit corresponds to a VLAN id */
3905 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3906 rc = bnxt_add_vlan_filter(bp, vlan_id);
3915 static int bnxt_restore_mac_filters(struct bnxt *bp)
3917 struct rte_eth_dev *dev = bp->eth_dev;
3918 struct rte_eth_dev_info dev_info;
3919 struct rte_ether_addr *addr;
3925 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
3928 rc = bnxt_dev_info_get_op(dev, &dev_info);
3932 /* replay MAC address configuration */
3933 for (i = 1; i < dev_info.max_mac_addrs; i++) {
3934 addr = &dev->data->mac_addrs[i];
3936 /* skip zero address */
3937 if (rte_is_zero_ether_addr(addr))
3941 pool_mask = dev->data->mac_pool_sel[i];
3944 if (pool_mask & 1ULL) {
3945 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3951 } while (pool_mask);
3957 static int bnxt_restore_filters(struct bnxt *bp)
3959 struct rte_eth_dev *dev = bp->eth_dev;
3962 if (dev->data->all_multicast)
3963 ret = bnxt_allmulticast_enable_op(dev);
3964 if (dev->data->promiscuous)
3965 ret = bnxt_promiscuous_enable_op(dev);
3967 ret = bnxt_restore_mac_filters(bp);
3971 ret = bnxt_restore_vlan_filters(bp);
3972 /* TODO restore other filters as well */
3976 static void bnxt_dev_recover(void *arg)
3978 struct bnxt *bp = arg;
3979 int timeout = bp->fw_reset_max_msecs;
3982 /* Clear Error flag so that device re-init should happen */
3983 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3986 rc = bnxt_hwrm_ver_get(bp);
3989 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3990 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3991 } while (rc && timeout);
3994 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3998 rc = bnxt_init_resources(bp, true);
4001 "Failed to initialize resources after reset\n");
4004 /* clear reset flag as the device is initialized now */
4005 bp->flags &= ~BNXT_FLAG_FW_RESET;
4007 rc = bnxt_dev_start_op(bp->eth_dev);
4009 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4013 rc = bnxt_restore_filters(bp);
4017 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4020 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4021 bnxt_uninit_resources(bp, false);
4022 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4025 void bnxt_dev_reset_and_resume(void *arg)
4027 struct bnxt *bp = arg;
4030 bnxt_dev_cleanup(bp);
4032 bnxt_wait_for_device_shutdown(bp);
4034 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4035 bnxt_dev_recover, (void *)bp);
4037 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4040 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4042 struct bnxt_error_recovery_info *info = bp->recovery_info;
4043 uint32_t reg = info->status_regs[index];
4044 uint32_t type, offset, val = 0;
4046 type = BNXT_FW_STATUS_REG_TYPE(reg);
4047 offset = BNXT_FW_STATUS_REG_OFF(reg);
4050 case BNXT_FW_STATUS_REG_TYPE_CFG:
4051 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4053 case BNXT_FW_STATUS_REG_TYPE_GRC:
4054 offset = info->mapped_status_regs[index];
4056 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4057 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4065 static int bnxt_fw_reset_all(struct bnxt *bp)
4067 struct bnxt_error_recovery_info *info = bp->recovery_info;
4071 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4072 /* Reset through master function driver */
4073 for (i = 0; i < info->reg_array_cnt; i++)
4074 bnxt_write_fw_reset_reg(bp, i);
4075 /* Wait for time specified by FW after triggering reset */
4076 rte_delay_ms(info->master_func_wait_period_after_reset);
4077 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4078 /* Reset with the help of Kong processor */
4079 rc = bnxt_hwrm_fw_reset(bp);
4081 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4087 static void bnxt_fw_reset_cb(void *arg)
4089 struct bnxt *bp = arg;
4090 struct bnxt_error_recovery_info *info = bp->recovery_info;
4093 /* Only Master function can do FW reset */
4094 if (bnxt_is_master_func(bp) &&
4095 bnxt_is_recovery_enabled(bp)) {
4096 rc = bnxt_fw_reset_all(bp);
4098 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4103 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4104 * EXCEPTION_FATAL_ASYNC event to all the functions
4105 * (including MASTER FUNC). After receiving this Async, all the active
4106 * drivers should treat this case as FW initiated recovery
4108 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4109 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4110 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4112 /* To recover from error */
4113 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4118 /* Driver should poll FW heartbeat, reset_counter with the frequency
4119 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4120 * When the driver detects heartbeat stop or change in reset_counter,
4121 * it has to trigger a reset to recover from the error condition.
4122 * A “master PF” is the function who will have the privilege to
4123 * initiate the chimp reset. The master PF will be elected by the
4124 * firmware and will be notified through async message.
4126 static void bnxt_check_fw_health(void *arg)
4128 struct bnxt *bp = arg;
4129 struct bnxt_error_recovery_info *info = bp->recovery_info;
4130 uint32_t val = 0, wait_msec;
4132 if (!info || !bnxt_is_recovery_enabled(bp) ||
4133 is_bnxt_in_error(bp))
4136 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4137 if (val == info->last_heart_beat)
4140 info->last_heart_beat = val;
4142 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4143 if (val != info->last_reset_counter)
4146 info->last_reset_counter = val;
4148 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4149 bnxt_check_fw_health, (void *)bp);
4153 /* Stop DMA to/from device */
4154 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4155 bp->flags |= BNXT_FLAG_FW_RESET;
4157 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4159 if (bnxt_is_master_func(bp))
4160 wait_msec = info->master_func_wait_period;
4162 wait_msec = info->normal_func_wait_period;
4164 rte_eal_alarm_set(US_PER_MS * wait_msec,
4165 bnxt_fw_reset_cb, (void *)bp);
4168 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4170 uint32_t polling_freq;
4172 if (!bnxt_is_recovery_enabled(bp))
4175 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4178 polling_freq = bp->recovery_info->driver_polling_freq;
4180 rte_eal_alarm_set(US_PER_MS * polling_freq,
4181 bnxt_check_fw_health, (void *)bp);
4182 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4185 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4187 if (!bnxt_is_recovery_enabled(bp))
4190 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4191 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4194 static bool bnxt_vf_pciid(uint16_t device_id)
4196 switch (device_id) {
4197 case BROADCOM_DEV_ID_57304_VF:
4198 case BROADCOM_DEV_ID_57406_VF:
4199 case BROADCOM_DEV_ID_5731X_VF:
4200 case BROADCOM_DEV_ID_5741X_VF:
4201 case BROADCOM_DEV_ID_57414_VF:
4202 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4203 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4204 case BROADCOM_DEV_ID_58802_VF:
4205 case BROADCOM_DEV_ID_57500_VF1:
4206 case BROADCOM_DEV_ID_57500_VF2:
4214 static bool bnxt_thor_device(uint16_t device_id)
4216 switch (device_id) {
4217 case BROADCOM_DEV_ID_57508:
4218 case BROADCOM_DEV_ID_57504:
4219 case BROADCOM_DEV_ID_57502:
4220 case BROADCOM_DEV_ID_57508_MF1:
4221 case BROADCOM_DEV_ID_57504_MF1:
4222 case BROADCOM_DEV_ID_57502_MF1:
4223 case BROADCOM_DEV_ID_57508_MF2:
4224 case BROADCOM_DEV_ID_57504_MF2:
4225 case BROADCOM_DEV_ID_57502_MF2:
4226 case BROADCOM_DEV_ID_57500_VF1:
4227 case BROADCOM_DEV_ID_57500_VF2:
4235 bool bnxt_stratus_device(struct bnxt *bp)
4237 uint16_t device_id = bp->pdev->id.device_id;
4239 switch (device_id) {
4240 case BROADCOM_DEV_ID_STRATUS_NIC:
4241 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4242 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4250 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4252 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4253 struct bnxt *bp = eth_dev->data->dev_private;
4255 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4256 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4257 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4258 if (!bp->bar0 || !bp->doorbell_base) {
4259 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4263 bp->eth_dev = eth_dev;
4269 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4270 struct bnxt_ctx_pg_info *ctx_pg,
4275 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4276 const struct rte_memzone *mz = NULL;
4277 char mz_name[RTE_MEMZONE_NAMESIZE];
4278 rte_iova_t mz_phys_addr;
4279 uint64_t valid_bits = 0;
4286 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4288 rmem->page_size = BNXT_PAGE_SIZE;
4289 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4290 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4291 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4293 valid_bits = PTU_PTE_VALID;
4295 if (rmem->nr_pages > 1) {
4296 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4297 "bnxt_ctx_pg_tbl%s_%x_%d",
4298 suffix, idx, bp->eth_dev->data->port_id);
4299 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4300 mz = rte_memzone_lookup(mz_name);
4302 mz = rte_memzone_reserve_aligned(mz_name,
4306 RTE_MEMZONE_SIZE_HINT_ONLY |
4307 RTE_MEMZONE_IOVA_CONTIG,
4313 memset(mz->addr, 0, mz->len);
4314 mz_phys_addr = mz->iova;
4316 rmem->pg_tbl = mz->addr;
4317 rmem->pg_tbl_map = mz_phys_addr;
4318 rmem->pg_tbl_mz = mz;
4321 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4322 suffix, idx, bp->eth_dev->data->port_id);
4323 mz = rte_memzone_lookup(mz_name);
4325 mz = rte_memzone_reserve_aligned(mz_name,
4329 RTE_MEMZONE_SIZE_HINT_ONLY |
4330 RTE_MEMZONE_IOVA_CONTIG,
4336 memset(mz->addr, 0, mz->len);
4337 mz_phys_addr = mz->iova;
4339 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4340 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4341 rmem->dma_arr[i] = mz_phys_addr + sz;
4343 if (rmem->nr_pages > 1) {
4344 if (i == rmem->nr_pages - 2 &&
4345 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4346 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4347 else if (i == rmem->nr_pages - 1 &&
4348 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4349 valid_bits |= PTU_PTE_LAST;
4351 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4357 if (rmem->vmem_size)
4358 rmem->vmem = (void **)mz->addr;
4359 rmem->dma_arr[0] = mz_phys_addr;
4363 static void bnxt_free_ctx_mem(struct bnxt *bp)
4367 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4370 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4371 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4372 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4373 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4374 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4375 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4376 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4377 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4378 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4379 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4380 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4382 for (i = 0; i < BNXT_MAX_Q; i++) {
4383 if (bp->ctx->tqm_mem[i])
4384 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4391 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4393 #define min_t(type, x, y) ({ \
4394 type __min1 = (x); \
4395 type __min2 = (y); \
4396 __min1 < __min2 ? __min1 : __min2; })
4398 #define max_t(type, x, y) ({ \
4399 type __max1 = (x); \
4400 type __max2 = (y); \
4401 __max1 > __max2 ? __max1 : __max2; })
4403 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4405 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4407 struct bnxt_ctx_pg_info *ctx_pg;
4408 struct bnxt_ctx_mem_info *ctx;
4409 uint32_t mem_size, ena, entries;
4412 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4414 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4418 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4421 ctx_pg = &ctx->qp_mem;
4422 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4423 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4424 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4428 ctx_pg = &ctx->srq_mem;
4429 ctx_pg->entries = ctx->srq_max_l2_entries;
4430 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4431 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4435 ctx_pg = &ctx->cq_mem;
4436 ctx_pg->entries = ctx->cq_max_l2_entries;
4437 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4438 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4442 ctx_pg = &ctx->vnic_mem;
4443 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4444 ctx->vnic_max_ring_table_entries;
4445 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4446 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4450 ctx_pg = &ctx->stat_mem;
4451 ctx_pg->entries = ctx->stat_max_entries;
4452 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4453 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4457 entries = ctx->qp_max_l2_entries +
4458 ctx->vnic_max_vnic_entries +
4459 ctx->tqm_min_entries_per_ring;
4460 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4461 entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4462 ctx->tqm_max_entries_per_ring);
4463 for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4464 ctx_pg = ctx->tqm_mem[i];
4465 /* use min tqm entries for now. */
4466 ctx_pg->entries = entries;
4467 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4468 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4471 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4474 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4475 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4478 "Failed to configure context mem: rc = %d\n", rc);
4480 ctx->flags |= BNXT_CTX_FLAG_INITED;
4485 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4487 struct rte_pci_device *pci_dev = bp->pdev;
4488 char mz_name[RTE_MEMZONE_NAMESIZE];
4489 const struct rte_memzone *mz = NULL;
4490 uint32_t total_alloc_len;
4491 rte_iova_t mz_phys_addr;
4493 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4496 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4497 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4498 pci_dev->addr.bus, pci_dev->addr.devid,
4499 pci_dev->addr.function, "rx_port_stats");
4500 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4501 mz = rte_memzone_lookup(mz_name);
4503 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4504 sizeof(struct rx_port_stats_ext) + 512);
4506 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4509 RTE_MEMZONE_SIZE_HINT_ONLY |
4510 RTE_MEMZONE_IOVA_CONTIG);
4514 memset(mz->addr, 0, mz->len);
4515 mz_phys_addr = mz->iova;
4517 bp->rx_mem_zone = (const void *)mz;
4518 bp->hw_rx_port_stats = mz->addr;
4519 bp->hw_rx_port_stats_map = mz_phys_addr;
4521 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4522 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4523 pci_dev->addr.bus, pci_dev->addr.devid,
4524 pci_dev->addr.function, "tx_port_stats");
4525 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4526 mz = rte_memzone_lookup(mz_name);
4528 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4529 sizeof(struct tx_port_stats_ext) + 512);
4531 mz = rte_memzone_reserve(mz_name,
4535 RTE_MEMZONE_SIZE_HINT_ONLY |
4536 RTE_MEMZONE_IOVA_CONTIG);
4540 memset(mz->addr, 0, mz->len);
4541 mz_phys_addr = mz->iova;
4543 bp->tx_mem_zone = (const void *)mz;
4544 bp->hw_tx_port_stats = mz->addr;
4545 bp->hw_tx_port_stats_map = mz_phys_addr;
4546 bp->flags |= BNXT_FLAG_PORT_STATS;
4548 /* Display extended statistics if FW supports it */
4549 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4550 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4551 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4554 bp->hw_rx_port_stats_ext = (void *)
4555 ((uint8_t *)bp->hw_rx_port_stats +
4556 sizeof(struct rx_port_stats));
4557 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4558 sizeof(struct rx_port_stats);
4559 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4561 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4562 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4563 bp->hw_tx_port_stats_ext = (void *)
4564 ((uint8_t *)bp->hw_tx_port_stats +
4565 sizeof(struct tx_port_stats));
4566 bp->hw_tx_port_stats_ext_map =
4567 bp->hw_tx_port_stats_map +
4568 sizeof(struct tx_port_stats);
4569 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4575 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4577 struct bnxt *bp = eth_dev->data->dev_private;
4580 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4581 RTE_ETHER_ADDR_LEN *
4584 if (eth_dev->data->mac_addrs == NULL) {
4585 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4589 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4593 /* Generate a random MAC address, if none was assigned by PF */
4594 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4595 bnxt_eth_hw_addr_random(bp->mac_addr);
4597 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4598 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4599 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4601 rc = bnxt_hwrm_set_mac(bp);
4603 memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4604 RTE_ETHER_ADDR_LEN);
4608 /* Copy the permanent MAC from the FUNC_QCAPS response */
4609 memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4610 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4615 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4619 /* MAC is already configured in FW */
4620 if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4623 /* Restore the old MAC configured */
4624 rc = bnxt_hwrm_set_mac(bp);
4626 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4631 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4636 #define ALLOW_FUNC(x) \
4638 uint32_t arg = (x); \
4639 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4640 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4643 /* Forward all requests if firmware is new enough */
4644 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4645 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4646 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4647 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4649 PMD_DRV_LOG(WARNING,
4650 "Firmware too old for VF mailbox functionality\n");
4651 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4655 * The following are used for driver cleanup. If we disallow these,
4656 * VF drivers can't clean up cleanly.
4658 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4659 ALLOW_FUNC(HWRM_VNIC_FREE);
4660 ALLOW_FUNC(HWRM_RING_FREE);
4661 ALLOW_FUNC(HWRM_RING_GRP_FREE);
4662 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4663 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4664 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4665 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4666 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4669 static int bnxt_init_fw(struct bnxt *bp)
4676 rc = bnxt_hwrm_ver_get(bp);
4680 rc = bnxt_hwrm_func_reset(bp);
4684 rc = bnxt_hwrm_vnic_qcaps(bp);
4688 rc = bnxt_hwrm_queue_qportcfg(bp);
4692 /* Get the MAX capabilities for this function.
4693 * This function also allocates context memory for TQM rings and
4694 * informs the firmware about this allocated backing store memory.
4696 rc = bnxt_hwrm_func_qcaps(bp);
4700 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4704 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4708 /* Get the adapter error recovery support info */
4709 rc = bnxt_hwrm_error_recovery_qcfg(bp);
4711 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4713 bnxt_hwrm_port_led_qcaps(bp);
4719 bnxt_init_locks(struct bnxt *bp)
4723 err = pthread_mutex_init(&bp->flow_lock, NULL);
4725 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4729 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4731 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4735 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4739 rc = bnxt_init_fw(bp);
4743 if (!reconfig_dev) {
4744 rc = bnxt_setup_mac_addr(bp->eth_dev);
4748 rc = bnxt_restore_dflt_mac(bp);
4753 bnxt_config_vf_req_fwd(bp);
4755 rc = bnxt_hwrm_func_driver_register(bp);
4757 PMD_DRV_LOG(ERR, "Failed to register driver");
4762 if (bp->pdev->max_vfs) {
4763 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4765 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4769 rc = bnxt_hwrm_allocate_pf_only(bp);
4772 "Failed to allocate PF resources");
4778 rc = bnxt_alloc_mem(bp, reconfig_dev);
4782 rc = bnxt_setup_int(bp);
4786 rc = bnxt_request_int(bp);
4790 rc = bnxt_init_locks(bp);
4798 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4800 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4801 static int version_printed;
4805 if (version_printed++ == 0)
4806 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4808 eth_dev->dev_ops = &bnxt_dev_ops;
4809 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4810 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4813 * For secondary processes, we don't initialise any further
4814 * as primary has already done this work.
4816 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4819 rte_eth_copy_pci_info(eth_dev, pci_dev);
4821 bp = eth_dev->data->dev_private;
4823 bp->dev_stopped = 1;
4824 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
4826 if (bnxt_vf_pciid(pci_dev->id.device_id))
4827 bp->flags |= BNXT_FLAG_VF;
4829 if (bnxt_thor_device(pci_dev->id.device_id))
4830 bp->flags |= BNXT_FLAG_THOR_CHIP;
4832 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4833 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4834 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4835 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4836 bp->flags |= BNXT_FLAG_STINGRAY;
4838 rc = bnxt_init_board(eth_dev);
4841 "Failed to initialize board rc: %x\n", rc);
4845 rc = bnxt_alloc_hwrm_resources(bp);
4848 "Failed to allocate hwrm resource rc: %x\n", rc);
4851 rc = bnxt_init_resources(bp, false);
4855 rc = bnxt_alloc_stats_mem(bp);
4860 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4861 pci_dev->mem_resource[0].phys_addr,
4862 pci_dev->mem_resource[0].addr);
4867 bnxt_dev_uninit(eth_dev);
4872 bnxt_uninit_locks(struct bnxt *bp)
4874 pthread_mutex_destroy(&bp->flow_lock);
4875 pthread_mutex_destroy(&bp->def_cp_lock);
4879 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4884 bnxt_free_mem(bp, reconfig_dev);
4885 bnxt_hwrm_func_buf_unrgtr(bp);
4886 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4887 bp->flags &= ~BNXT_FLAG_REGISTERED;
4888 bnxt_free_ctx_mem(bp);
4889 if (!reconfig_dev) {
4890 bnxt_free_hwrm_resources(bp);
4892 if (bp->recovery_info != NULL) {
4893 rte_free(bp->recovery_info);
4894 bp->recovery_info = NULL;
4898 bnxt_uninit_locks(bp);
4899 rte_free(bp->ptp_cfg);
4905 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4907 struct bnxt *bp = eth_dev->data->dev_private;
4910 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4913 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4915 rc = bnxt_uninit_resources(bp, false);
4917 if (bp->tx_mem_zone) {
4918 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4919 bp->tx_mem_zone = NULL;
4922 if (bp->rx_mem_zone) {
4923 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4924 bp->rx_mem_zone = NULL;
4927 if (bp->dev_stopped == 0)
4928 bnxt_dev_close_op(eth_dev);
4930 rte_free(bp->pf.vf_info);
4931 eth_dev->dev_ops = NULL;
4932 eth_dev->rx_pkt_burst = NULL;
4933 eth_dev->tx_pkt_burst = NULL;
4938 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4939 struct rte_pci_device *pci_dev)
4941 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4945 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4947 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4948 return rte_eth_dev_pci_generic_remove(pci_dev,
4951 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4954 static struct rte_pci_driver bnxt_rte_pmd = {
4955 .id_table = bnxt_pci_id_map,
4956 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4957 .probe = bnxt_pci_probe,
4958 .remove = bnxt_pci_remove,
4962 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4964 if (strcmp(dev->device->driver->name, drv->driver.name))
4970 bool is_bnxt_supported(struct rte_eth_dev *dev)
4972 return is_device_supported(dev, &bnxt_rte_pmd);
4975 RTE_INIT(bnxt_init_log)
4977 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4978 if (bnxt_logtype_driver >= 0)
4979 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4982 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4983 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4984 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");