1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
15 #include <rte_kvargs.h>
19 #include "bnxt_filter.h"
20 #include "bnxt_hwrm.h"
22 #include "bnxt_reps.h"
23 #include "bnxt_ring.h"
26 #include "bnxt_stats.h"
29 #include "bnxt_vnic.h"
30 #include "hsi_struct_def_dpdk.h"
31 #include "bnxt_nvm_defs.h"
32 #include "bnxt_tf_common.h"
33 #include "ulp_flow_db.h"
34 #include "rte_pmd_bnxt.h"
36 #define DRV_MODULE_NAME "bnxt"
37 static const char bnxt_version[] =
38 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
41 * The set of PCI devices this driver supports
43 static const struct rte_pci_id bnxt_pci_id_map[] = {
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
45 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
47 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
87 { .vendor_id = 0, /* sentinel */ },
90 #define BNXT_DEVARG_TRUFLOW "host-based-truflow"
91 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat"
92 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows"
93 #define BNXT_DEVARG_REPRESENTOR "representor"
94 #define BNXT_DEVARG_REP_BASED_PF "rep-based-pf"
95 #define BNXT_DEVARG_REP_IS_PF "rep-is-pf"
96 #define BNXT_DEVARG_REP_Q_R2F "rep-q-r2f"
97 #define BNXT_DEVARG_REP_Q_F2R "rep-q-f2r"
98 #define BNXT_DEVARG_REP_FC_R2F "rep-fc-r2f"
99 #define BNXT_DEVARG_REP_FC_F2R "rep-fc-f2r"
101 static const char *const bnxt_dev_args[] = {
102 BNXT_DEVARG_REPRESENTOR,
104 BNXT_DEVARG_FLOW_XSTAT,
105 BNXT_DEVARG_MAX_NUM_KFLOWS,
106 BNXT_DEVARG_REP_BASED_PF,
107 BNXT_DEVARG_REP_IS_PF,
108 BNXT_DEVARG_REP_Q_R2F,
109 BNXT_DEVARG_REP_Q_F2R,
110 BNXT_DEVARG_REP_FC_R2F,
111 BNXT_DEVARG_REP_FC_F2R,
116 * truflow == false to disable the feature
117 * truflow == true to enable the feature
119 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1)
122 * flow_xstat == false to disable the feature
123 * flow_xstat == true to enable the feature
125 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1)
128 * rep_is_pf == false to indicate VF representor
129 * rep_is_pf == true to indicate PF representor
131 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf) ((rep_is_pf) > 1)
134 * rep_based_pf == Physical index of the PF
136 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf) ((rep_based_pf) > 15)
138 * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
140 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f) ((rep_q_r2f) > 3)
143 * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
145 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r) ((rep_q_f2r) > 3)
148 * rep_fc_r2f == Flow control for the representor to endpoint direction
150 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f) ((rep_fc_r2f) > 1)
153 * rep_fc_f2r == Flow control for the endpoint to representor direction
155 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r) ((rep_fc_f2r) > 1)
157 int bnxt_cfa_code_dynfield_offset = -1;
160 * max_num_kflows must be >= 32
161 * and must be a power-of-2 supported value
162 * return: 1 -> invalid
165 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
167 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
172 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
173 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
174 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
175 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
176 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
177 static int bnxt_restore_vlan_filters(struct bnxt *bp);
178 static void bnxt_dev_recover(void *arg);
179 static void bnxt_free_error_recovery_info(struct bnxt *bp);
180 static void bnxt_free_rep_info(struct bnxt *bp);
182 int is_bnxt_in_error(struct bnxt *bp)
184 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
186 if (bp->flags & BNXT_FLAG_FW_RESET)
192 /***********************/
195 * High level utility functions
198 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
200 unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
201 BNXT_RSS_TBL_SIZE_P5);
203 if (!BNXT_CHIP_P5(bp))
206 return RTE_ALIGN_MUL_CEIL(num_rss_rings,
207 BNXT_RSS_ENTRIES_PER_CTX_P5) /
208 BNXT_RSS_ENTRIES_PER_CTX_P5;
211 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
213 if (!BNXT_CHIP_P5(bp))
214 return HW_HASH_INDEX_SIZE;
216 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
219 static void bnxt_free_parent_info(struct bnxt *bp)
221 rte_free(bp->parent);
224 static void bnxt_free_pf_info(struct bnxt *bp)
229 static void bnxt_free_link_info(struct bnxt *bp)
231 rte_free(bp->link_info);
234 static void bnxt_free_leds_info(struct bnxt *bp)
243 static void bnxt_free_flow_stats_info(struct bnxt *bp)
245 rte_free(bp->flow_stat);
246 bp->flow_stat = NULL;
249 static void bnxt_free_cos_queues(struct bnxt *bp)
251 rte_free(bp->rx_cos_queue);
252 rte_free(bp->tx_cos_queue);
255 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
257 bnxt_free_filter_mem(bp);
258 bnxt_free_vnic_attributes(bp);
259 bnxt_free_vnic_mem(bp);
261 /* tx/rx rings are configured as part of *_queue_setup callbacks.
262 * If the number of rings change across fw update,
263 * we don't have much choice except to warn the user.
267 bnxt_free_tx_rings(bp);
268 bnxt_free_rx_rings(bp);
270 bnxt_free_async_cp_ring(bp);
271 bnxt_free_rxtx_nq_ring(bp);
273 rte_free(bp->grp_info);
277 static int bnxt_alloc_parent_info(struct bnxt *bp)
279 bp->parent = rte_zmalloc("bnxt_parent_info",
280 sizeof(struct bnxt_parent_info), 0);
281 if (bp->parent == NULL)
287 static int bnxt_alloc_pf_info(struct bnxt *bp)
289 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
296 static int bnxt_alloc_link_info(struct bnxt *bp)
299 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
300 if (bp->link_info == NULL)
306 static int bnxt_alloc_leds_info(struct bnxt *bp)
311 bp->leds = rte_zmalloc("bnxt_leds",
312 BNXT_MAX_LED * sizeof(struct bnxt_led_info),
314 if (bp->leds == NULL)
320 static int bnxt_alloc_cos_queues(struct bnxt *bp)
323 rte_zmalloc("bnxt_rx_cosq",
324 BNXT_COS_QUEUE_COUNT *
325 sizeof(struct bnxt_cos_queue_info),
327 if (bp->rx_cos_queue == NULL)
331 rte_zmalloc("bnxt_tx_cosq",
332 BNXT_COS_QUEUE_COUNT *
333 sizeof(struct bnxt_cos_queue_info),
335 if (bp->tx_cos_queue == NULL)
341 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
343 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
344 sizeof(struct bnxt_flow_stat_info), 0);
345 if (bp->flow_stat == NULL)
351 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
355 rc = bnxt_alloc_ring_grps(bp);
359 rc = bnxt_alloc_async_ring_struct(bp);
363 rc = bnxt_alloc_vnic_mem(bp);
367 rc = bnxt_alloc_vnic_attributes(bp);
371 rc = bnxt_alloc_filter_mem(bp);
375 rc = bnxt_alloc_async_cp_ring(bp);
379 rc = bnxt_alloc_rxtx_nq_ring(bp);
383 if (BNXT_FLOW_XSTATS_EN(bp)) {
384 rc = bnxt_alloc_flow_stats_info(bp);
392 bnxt_free_mem(bp, reconfig);
396 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
398 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
399 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
400 uint64_t rx_offloads = dev_conf->rxmode.offloads;
401 struct bnxt_rx_queue *rxq;
405 rc = bnxt_vnic_grp_alloc(bp, vnic);
409 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
410 vnic_id, vnic, vnic->fw_grp_ids);
412 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
416 /* Alloc RSS context only if RSS mode is enabled */
417 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
418 int j, nr_ctxs = bnxt_rss_ctxts(bp);
420 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
421 PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
422 bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
424 "Only queues 0-%d will be in RSS table\n",
425 BNXT_RSS_TBL_SIZE_P5 - 1);
429 for (j = 0; j < nr_ctxs; j++) {
430 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
436 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
440 vnic->num_lb_ctxts = nr_ctxs;
444 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
445 * setting is not available at this time, it will not be
446 * configured correctly in the CFA.
448 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
449 vnic->vlan_strip = true;
451 vnic->vlan_strip = false;
453 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
457 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
461 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
462 rxq = bp->eth_dev->data->rx_queues[j];
465 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
466 j, rxq->vnic, rxq->vnic->fw_grp_ids);
468 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
469 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
471 vnic->rx_queue_cnt++;
474 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
476 rc = bnxt_vnic_rss_configure(bp, vnic);
480 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
482 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
483 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
485 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
489 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
494 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
498 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
499 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
504 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
505 " rx_fc_in_tbl.ctx_id = %d\n",
506 bp->flow_stat->rx_fc_in_tbl.va,
507 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
508 bp->flow_stat->rx_fc_in_tbl.ctx_id);
510 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
511 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
516 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
517 " rx_fc_out_tbl.ctx_id = %d\n",
518 bp->flow_stat->rx_fc_out_tbl.va,
519 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
520 bp->flow_stat->rx_fc_out_tbl.ctx_id);
522 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
523 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
528 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
529 " tx_fc_in_tbl.ctx_id = %d\n",
530 bp->flow_stat->tx_fc_in_tbl.va,
531 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
532 bp->flow_stat->tx_fc_in_tbl.ctx_id);
534 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
535 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
540 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
541 " tx_fc_out_tbl.ctx_id = %d\n",
542 bp->flow_stat->tx_fc_out_tbl.va,
543 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
544 bp->flow_stat->tx_fc_out_tbl.ctx_id);
546 memset(bp->flow_stat->rx_fc_out_tbl.va,
548 bp->flow_stat->rx_fc_out_tbl.size);
549 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
550 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
551 bp->flow_stat->rx_fc_out_tbl.ctx_id,
552 bp->flow_stat->max_fc,
557 memset(bp->flow_stat->tx_fc_out_tbl.va,
559 bp->flow_stat->tx_fc_out_tbl.size);
560 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
561 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
562 bp->flow_stat->tx_fc_out_tbl.ctx_id,
563 bp->flow_stat->max_fc,
569 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
570 struct bnxt_ctx_mem_buf_info *ctx)
575 ctx->va = rte_zmalloc(type, size, 0);
578 rte_mem_lock_page(ctx->va);
580 ctx->dma = rte_mem_virt2iova(ctx->va);
581 if (ctx->dma == RTE_BAD_IOVA)
587 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
589 struct rte_pci_device *pdev = bp->pdev;
590 char type[RTE_MEMZONE_NAMESIZE];
594 max_fc = bp->flow_stat->max_fc;
596 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
597 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
598 /* 4 bytes for each counter-id */
599 rc = bnxt_alloc_ctx_mem_buf(type,
601 &bp->flow_stat->rx_fc_in_tbl);
605 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
606 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
607 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
608 rc = bnxt_alloc_ctx_mem_buf(type,
610 &bp->flow_stat->rx_fc_out_tbl);
614 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
615 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
616 /* 4 bytes for each counter-id */
617 rc = bnxt_alloc_ctx_mem_buf(type,
619 &bp->flow_stat->tx_fc_in_tbl);
623 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
624 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
625 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
626 rc = bnxt_alloc_ctx_mem_buf(type,
628 &bp->flow_stat->tx_fc_out_tbl);
632 rc = bnxt_register_fc_ctx_mem(bp);
637 static int bnxt_init_ctx_mem(struct bnxt *bp)
641 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
642 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
643 !BNXT_FLOW_XSTATS_EN(bp))
646 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
650 rc = bnxt_init_fc_ctx_mem(bp);
655 static int bnxt_update_phy_setting(struct bnxt *bp)
657 struct rte_eth_link new;
660 rc = bnxt_get_hwrm_link_config(bp, &new);
662 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
667 * On BCM957508-N2100 adapters, FW will not allow any user other
668 * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
669 * always returns link up. Force phy update always in that case.
671 if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
672 rc = bnxt_set_hwrm_link_config(bp, true);
674 PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
682 static int bnxt_init_chip(struct bnxt *bp)
684 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
685 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
686 uint32_t intr_vector = 0;
687 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
688 uint32_t vec = BNXT_MISC_VEC_ID;
692 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
693 bp->eth_dev->data->dev_conf.rxmode.offloads |=
694 DEV_RX_OFFLOAD_JUMBO_FRAME;
695 bp->flags |= BNXT_FLAG_JUMBO;
697 bp->eth_dev->data->dev_conf.rxmode.offloads &=
698 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
699 bp->flags &= ~BNXT_FLAG_JUMBO;
702 /* THOR does not support ring groups.
703 * But we will use the array to save RSS context IDs.
705 if (BNXT_CHIP_P5(bp))
706 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
708 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
710 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
714 rc = bnxt_alloc_hwrm_rings(bp);
716 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
720 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
722 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
726 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
729 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
730 if (bp->rx_cos_queue[i].id != 0xff) {
731 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
735 "Num pools more than FW profile\n");
739 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
745 rc = bnxt_mq_rx_configure(bp);
747 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
752 rc = bnxt_setup_one_vnic(bp, 0);
755 /* VNIC configuration */
756 if (BNXT_RFS_NEEDS_VNIC(bp)) {
757 for (i = 1; i < bp->nr_vnics; i++) {
758 rc = bnxt_setup_one_vnic(bp, i);
764 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
767 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
771 /* check and configure queue intr-vector mapping */
772 if ((rte_intr_cap_multiple(intr_handle) ||
773 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
774 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
775 intr_vector = bp->eth_dev->data->nb_rx_queues;
776 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
777 if (intr_vector > bp->rx_cp_nr_rings) {
778 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
782 rc = rte_intr_efd_enable(intr_handle, intr_vector);
787 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
788 intr_handle->intr_vec =
789 rte_zmalloc("intr_vec",
790 bp->eth_dev->data->nb_rx_queues *
792 if (intr_handle->intr_vec == NULL) {
793 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
794 " intr_vec", bp->eth_dev->data->nb_rx_queues);
798 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
799 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
800 intr_handle->intr_vec, intr_handle->nb_efd,
801 intr_handle->max_intr);
802 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
804 intr_handle->intr_vec[queue_id] =
805 vec + BNXT_RX_VEC_START;
806 if (vec < base + intr_handle->nb_efd - 1)
811 /* enable uio/vfio intr/eventfd mapping */
812 rc = rte_intr_enable(intr_handle);
813 #ifndef RTE_EXEC_ENV_FREEBSD
814 /* In FreeBSD OS, nic_uio driver does not support interrupts */
819 rc = bnxt_update_phy_setting(bp);
823 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
825 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
830 rte_free(intr_handle->intr_vec);
832 rte_intr_efd_disable(intr_handle);
834 /* Some of the error status returned by FW may not be from errno.h */
841 static int bnxt_shutdown_nic(struct bnxt *bp)
843 bnxt_free_all_hwrm_resources(bp);
844 bnxt_free_all_filters(bp);
845 bnxt_free_all_vnics(bp);
850 * Device configuration and status function
853 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
855 uint32_t link_speed = bp->link_info->support_speeds;
856 uint32_t speed_capa = 0;
858 /* If PAM4 is configured, use PAM4 supported speed */
859 if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
860 link_speed = bp->link_info->support_pam4_speeds;
862 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
863 speed_capa |= ETH_LINK_SPEED_100M;
864 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
865 speed_capa |= ETH_LINK_SPEED_100M_HD;
866 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
867 speed_capa |= ETH_LINK_SPEED_1G;
868 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
869 speed_capa |= ETH_LINK_SPEED_2_5G;
870 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
871 speed_capa |= ETH_LINK_SPEED_10G;
872 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
873 speed_capa |= ETH_LINK_SPEED_20G;
874 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
875 speed_capa |= ETH_LINK_SPEED_25G;
876 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
877 speed_capa |= ETH_LINK_SPEED_40G;
878 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
879 speed_capa |= ETH_LINK_SPEED_50G;
880 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
881 speed_capa |= ETH_LINK_SPEED_100G;
882 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
883 speed_capa |= ETH_LINK_SPEED_50G;
884 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
885 speed_capa |= ETH_LINK_SPEED_100G;
886 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
887 speed_capa |= ETH_LINK_SPEED_200G;
889 if (bp->link_info->auto_mode ==
890 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
891 speed_capa |= ETH_LINK_SPEED_FIXED;
893 speed_capa |= ETH_LINK_SPEED_AUTONEG;
898 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
899 struct rte_eth_dev_info *dev_info)
901 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
902 struct bnxt *bp = eth_dev->data->dev_private;
903 uint16_t max_vnics, i, j, vpool, vrxq;
904 unsigned int max_rx_rings;
907 rc = is_bnxt_in_error(bp);
912 dev_info->max_mac_addrs = bp->max_l2_ctx;
913 dev_info->max_hash_mac_addrs = 0;
915 /* PF/VF specifics */
917 dev_info->max_vfs = pdev->max_vfs;
919 max_rx_rings = bnxt_max_rings(bp);
920 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
921 dev_info->max_rx_queues = max_rx_rings;
922 dev_info->max_tx_queues = max_rx_rings;
923 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
924 dev_info->hash_key_size = 40;
925 max_vnics = bp->max_vnics;
928 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
929 dev_info->max_mtu = BNXT_MAX_MTU;
931 /* Fast path specifics */
932 dev_info->min_rx_bufsize = 1;
933 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
935 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
936 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
937 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
938 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
939 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
940 dev_info->tx_queue_offload_capa;
941 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
943 dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
946 dev_info->default_rxconf = (struct rte_eth_rxconf) {
952 .rx_free_thresh = 32,
953 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
956 dev_info->default_txconf = (struct rte_eth_txconf) {
962 .tx_free_thresh = 32,
965 eth_dev->data->dev_conf.intr_conf.lsc = 1;
967 eth_dev->data->dev_conf.intr_conf.rxq = 1;
968 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
969 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
970 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
971 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
973 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
974 dev_info->switch_info.name = eth_dev->device->name;
975 dev_info->switch_info.domain_id = bp->switch_domain_id;
976 dev_info->switch_info.port_id =
977 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
978 BNXT_SWITCH_PORT_ID_TRUSTED_VF;
984 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
985 * need further investigation.
989 vpool = 64; /* ETH_64_POOLS */
990 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
991 for (i = 0; i < 4; vpool >>= 1, i++) {
992 if (max_vnics > vpool) {
993 for (j = 0; j < 5; vrxq >>= 1, j++) {
994 if (dev_info->max_rx_queues > vrxq) {
1000 /* Not enough resources to support VMDq */
1004 /* Not enough resources to support VMDq */
1008 dev_info->max_vmdq_pools = vpool;
1009 dev_info->vmdq_queue_num = vrxq;
1011 dev_info->vmdq_pool_base = 0;
1012 dev_info->vmdq_queue_base = 0;
1017 /* Configure the device based on the configuration provided */
1018 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1020 struct bnxt *bp = eth_dev->data->dev_private;
1021 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1024 bp->rx_queues = (void *)eth_dev->data->rx_queues;
1025 bp->tx_queues = (void *)eth_dev->data->tx_queues;
1026 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1027 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1029 rc = is_bnxt_in_error(bp);
1033 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1034 rc = bnxt_hwrm_check_vf_rings(bp);
1036 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1040 /* If a resource has already been allocated - in this case
1041 * it is the async completion ring, free it. Reallocate it after
1042 * resource reservation. This will ensure the resource counts
1043 * are calculated correctly.
1046 pthread_mutex_lock(&bp->def_cp_lock);
1048 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1049 bnxt_disable_int(bp);
1050 bnxt_free_cp_ring(bp, bp->async_cp_ring);
1053 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1055 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1056 pthread_mutex_unlock(&bp->def_cp_lock);
1060 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1061 rc = bnxt_alloc_async_cp_ring(bp);
1063 pthread_mutex_unlock(&bp->def_cp_lock);
1066 bnxt_enable_int(bp);
1069 pthread_mutex_unlock(&bp->def_cp_lock);
1072 /* Inherit new configurations */
1073 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1074 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1075 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1076 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1077 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1079 goto resource_error;
1081 if (BNXT_HAS_RING_GRPS(bp) &&
1082 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1083 goto resource_error;
1085 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1086 bp->max_vnics < eth_dev->data->nb_rx_queues)
1087 goto resource_error;
1089 bp->rx_cp_nr_rings = bp->rx_nr_rings;
1090 bp->tx_cp_nr_rings = bp->tx_nr_rings;
1092 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1093 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1094 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1096 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1097 eth_dev->data->mtu =
1098 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1099 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1101 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1107 "Insufficient resources to support requested config\n");
1109 "Num Queues Requested: Tx %d, Rx %d\n",
1110 eth_dev->data->nb_tx_queues,
1111 eth_dev->data->nb_rx_queues);
1113 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1114 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1115 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1119 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1121 struct rte_eth_link *link = ð_dev->data->dev_link;
1123 if (link->link_status)
1124 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1125 eth_dev->data->port_id,
1126 (uint32_t)link->link_speed,
1127 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1128 ("full-duplex") : ("half-duplex\n"));
1130 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1131 eth_dev->data->port_id);
1135 * Determine whether the current configuration requires support for scattered
1136 * receive; return 1 if scattered receive is required and 0 if not.
1138 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1143 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1146 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1147 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1149 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1150 RTE_PKTMBUF_HEADROOM);
1151 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1157 static eth_rx_burst_t
1158 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1160 struct bnxt *bp = eth_dev->data->dev_private;
1162 /* Disable vector mode RX for Stingray2 for now */
1163 if (BNXT_CHIP_SR2(bp)) {
1164 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1165 return bnxt_recv_pkts;
1168 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1169 #ifndef RTE_LIBRTE_IEEE1588
1171 * Vector mode receive can be enabled only if scatter rx is not
1172 * in use and rx offloads are limited to VLAN stripping and
1175 if (!eth_dev->data->scattered_rx &&
1176 !(eth_dev->data->dev_conf.rxmode.offloads &
1177 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1178 DEV_RX_OFFLOAD_KEEP_CRC |
1179 DEV_RX_OFFLOAD_JUMBO_FRAME |
1180 DEV_RX_OFFLOAD_IPV4_CKSUM |
1181 DEV_RX_OFFLOAD_UDP_CKSUM |
1182 DEV_RX_OFFLOAD_TCP_CKSUM |
1183 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1184 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1185 DEV_RX_OFFLOAD_RSS_HASH |
1186 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1187 !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp) &&
1188 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1189 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1190 eth_dev->data->port_id);
1191 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1192 return bnxt_recv_pkts_vec;
1194 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1195 eth_dev->data->port_id);
1197 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1198 eth_dev->data->port_id,
1199 eth_dev->data->scattered_rx,
1200 eth_dev->data->dev_conf.rxmode.offloads);
1203 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1204 return bnxt_recv_pkts;
1207 static eth_tx_burst_t
1208 bnxt_transmit_function(struct rte_eth_dev *eth_dev)
1210 struct bnxt *bp = eth_dev->data->dev_private;
1212 /* Disable vector mode TX for Stingray2 for now */
1213 if (BNXT_CHIP_SR2(bp))
1214 return bnxt_xmit_pkts;
1216 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1217 #ifndef RTE_LIBRTE_IEEE1588
1218 uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1221 * Vector mode transmit can be enabled only if not using scatter rx
1224 if (!eth_dev->data->scattered_rx &&
1225 !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
1226 !BNXT_TRUFLOW_EN(bp) &&
1227 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1228 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1229 eth_dev->data->port_id);
1230 return bnxt_xmit_pkts_vec;
1232 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1233 eth_dev->data->port_id);
1235 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1236 eth_dev->data->port_id,
1237 eth_dev->data->scattered_rx,
1241 return bnxt_xmit_pkts;
1244 static int bnxt_handle_if_change_status(struct bnxt *bp)
1248 /* Since fw has undergone a reset and lost all contexts,
1249 * set fatal flag to not issue hwrm during cleanup
1251 bp->flags |= BNXT_FLAG_FATAL_ERROR;
1252 bnxt_uninit_resources(bp, true);
1254 /* clear fatal flag so that re-init happens */
1255 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1256 rc = bnxt_init_resources(bp, true);
1258 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1263 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1265 struct bnxt *bp = eth_dev->data->dev_private;
1266 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1268 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1270 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1271 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1275 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1277 "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1278 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1281 rc = bnxt_hwrm_if_change(bp, true);
1282 if (rc == 0 || rc != -EAGAIN)
1285 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1286 } while (retry_cnt--);
1291 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1292 rc = bnxt_handle_if_change_status(bp);
1297 bnxt_enable_int(bp);
1299 rc = bnxt_init_chip(bp);
1303 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1304 eth_dev->data->dev_started = 1;
1306 bnxt_link_update_op(eth_dev, 1);
1308 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1309 vlan_mask |= ETH_VLAN_FILTER_MASK;
1310 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1311 vlan_mask |= ETH_VLAN_STRIP_MASK;
1312 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1316 /* Initialize bnxt ULP port details */
1317 rc = bnxt_ulp_port_init(bp);
1321 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1322 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1324 bnxt_schedule_fw_health_check(bp);
1329 bnxt_shutdown_nic(bp);
1330 bnxt_free_tx_mbufs(bp);
1331 bnxt_free_rx_mbufs(bp);
1332 bnxt_hwrm_if_change(bp, false);
1333 eth_dev->data->dev_started = 0;
1337 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1339 struct bnxt *bp = eth_dev->data->dev_private;
1342 if (!bp->link_info->link_up)
1343 rc = bnxt_set_hwrm_link_config(bp, true);
1345 eth_dev->data->dev_link.link_status = 1;
1347 bnxt_print_link_info(eth_dev);
1351 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1353 struct bnxt *bp = eth_dev->data->dev_private;
1355 eth_dev->data->dev_link.link_status = 0;
1356 bnxt_set_hwrm_link_config(bp, false);
1357 bp->link_info->link_up = 0;
1362 static void bnxt_free_switch_domain(struct bnxt *bp)
1366 if (bp->switch_domain_id) {
1367 rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1369 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1370 bp->switch_domain_id, rc);
1374 /* Unload the driver, release resources */
1375 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1377 struct bnxt *bp = eth_dev->data->dev_private;
1378 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1379 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1380 struct rte_eth_link link;
1383 eth_dev->data->dev_started = 0;
1384 eth_dev->data->scattered_rx = 0;
1386 /* Prevent crashes when queues are still in use */
1387 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1388 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1390 bnxt_disable_int(bp);
1392 /* disable uio/vfio intr/eventfd mapping */
1393 rte_intr_disable(intr_handle);
1395 /* Stop the child representors for this device */
1396 ret = bnxt_rep_stop_all(bp);
1400 /* delete the bnxt ULP port details */
1401 bnxt_ulp_port_deinit(bp);
1403 bnxt_cancel_fw_health_check(bp);
1405 /* Do not bring link down during reset recovery */
1406 if (!is_bnxt_in_error(bp)) {
1407 bnxt_dev_set_link_down_op(eth_dev);
1408 /* Wait for link to be reset */
1409 if (BNXT_SINGLE_PF(bp))
1411 /* clear the recorded link status */
1412 memset(&link, 0, sizeof(link));
1413 rte_eth_linkstatus_set(eth_dev, &link);
1416 /* Clean queue intr-vector mapping */
1417 rte_intr_efd_disable(intr_handle);
1418 if (intr_handle->intr_vec != NULL) {
1419 rte_free(intr_handle->intr_vec);
1420 intr_handle->intr_vec = NULL;
1423 bnxt_hwrm_port_clr_stats(bp);
1424 bnxt_free_tx_mbufs(bp);
1425 bnxt_free_rx_mbufs(bp);
1426 /* Process any remaining notifications in default completion queue */
1427 bnxt_int_handler(eth_dev);
1428 bnxt_shutdown_nic(bp);
1429 bnxt_hwrm_if_change(bp, false);
1431 rte_free(bp->mark_table);
1432 bp->mark_table = NULL;
1434 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1435 bp->rx_cosq_cnt = 0;
1436 /* All filters are deleted on a port stop. */
1437 if (BNXT_FLOW_XSTATS_EN(bp))
1438 bp->flow_stat->flow_count = 0;
1444 bnxt_uninit_locks(struct bnxt *bp)
1446 pthread_mutex_destroy(&bp->flow_lock);
1447 pthread_mutex_destroy(&bp->def_cp_lock);
1448 pthread_mutex_destroy(&bp->health_check_lock);
1450 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
1451 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
1455 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1457 struct bnxt *bp = eth_dev->data->dev_private;
1460 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1463 /* cancel the recovery handler before remove dev */
1464 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1465 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1466 bnxt_cancel_fc_thread(bp);
1468 if (eth_dev->data->dev_started)
1469 ret = bnxt_dev_stop_op(eth_dev);
1471 bnxt_free_switch_domain(bp);
1473 bnxt_uninit_resources(bp, false);
1475 bnxt_free_leds_info(bp);
1476 bnxt_free_cos_queues(bp);
1477 bnxt_free_link_info(bp);
1478 bnxt_free_pf_info(bp);
1479 bnxt_free_parent_info(bp);
1480 bnxt_uninit_locks(bp);
1482 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1483 bp->tx_mem_zone = NULL;
1484 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1485 bp->rx_mem_zone = NULL;
1487 bnxt_hwrm_free_vf_info(bp);
1489 rte_free(bp->grp_info);
1490 bp->grp_info = NULL;
1495 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1498 struct bnxt *bp = eth_dev->data->dev_private;
1499 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1500 struct bnxt_vnic_info *vnic;
1501 struct bnxt_filter_info *filter, *temp_filter;
1504 if (is_bnxt_in_error(bp))
1508 * Loop through all VNICs from the specified filter flow pools to
1509 * remove the corresponding MAC addr filter
1511 for (i = 0; i < bp->nr_vnics; i++) {
1512 if (!(pool_mask & (1ULL << i)))
1515 vnic = &bp->vnic_info[i];
1516 filter = STAILQ_FIRST(&vnic->filter);
1518 temp_filter = STAILQ_NEXT(filter, next);
1519 if (filter->mac_index == index) {
1520 STAILQ_REMOVE(&vnic->filter, filter,
1521 bnxt_filter_info, next);
1522 bnxt_hwrm_clear_l2_filter(bp, filter);
1523 bnxt_free_filter(bp, filter);
1525 filter = temp_filter;
1530 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1531 struct rte_ether_addr *mac_addr, uint32_t index,
1534 struct bnxt_filter_info *filter;
1537 /* Attach requested MAC address to the new l2_filter */
1538 STAILQ_FOREACH(filter, &vnic->filter, next) {
1539 if (filter->mac_index == index) {
1541 "MAC addr already existed for pool %d\n",
1547 filter = bnxt_alloc_filter(bp);
1549 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1553 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1554 * if the MAC that's been programmed now is a different one, then,
1555 * copy that addr to filter->l2_addr
1558 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1559 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1561 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1563 filter->mac_index = index;
1564 if (filter->mac_index == 0)
1565 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1567 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1569 bnxt_free_filter(bp, filter);
1575 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1576 struct rte_ether_addr *mac_addr,
1577 uint32_t index, uint32_t pool)
1579 struct bnxt *bp = eth_dev->data->dev_private;
1580 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1583 rc = is_bnxt_in_error(bp);
1587 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1588 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1593 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1597 /* Filter settings will get applied when port is started */
1598 if (!eth_dev->data->dev_started)
1601 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1606 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1609 struct bnxt *bp = eth_dev->data->dev_private;
1610 struct rte_eth_link new;
1611 int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1612 BNXT_MIN_LINK_WAIT_CNT;
1614 rc = is_bnxt_in_error(bp);
1618 memset(&new, 0, sizeof(new));
1620 /* Retrieve link info from hardware */
1621 rc = bnxt_get_hwrm_link_config(bp, &new);
1623 new.link_speed = ETH_LINK_SPEED_100M;
1624 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1626 "Failed to retrieve link rc = 0x%x!\n", rc);
1630 if (!wait_to_complete || new.link_status)
1633 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1636 /* Only single function PF can bring phy down.
1637 * When port is stopped, report link down for VF/MH/NPAR functions.
1639 if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1640 memset(&new, 0, sizeof(new));
1643 /* Timed out or success */
1644 if (new.link_status != eth_dev->data->dev_link.link_status ||
1645 new.link_speed != eth_dev->data->dev_link.link_speed) {
1646 rte_eth_linkstatus_set(eth_dev, &new);
1648 rte_eth_dev_callback_process(eth_dev,
1649 RTE_ETH_EVENT_INTR_LSC,
1652 bnxt_print_link_info(eth_dev);
1658 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1660 struct bnxt *bp = eth_dev->data->dev_private;
1661 struct bnxt_vnic_info *vnic;
1665 rc = is_bnxt_in_error(bp);
1669 /* Filter settings will get applied when port is started */
1670 if (!eth_dev->data->dev_started)
1673 if (bp->vnic_info == NULL)
1676 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1678 old_flags = vnic->flags;
1679 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1680 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1682 vnic->flags = old_flags;
1687 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1689 struct bnxt *bp = eth_dev->data->dev_private;
1690 struct bnxt_vnic_info *vnic;
1694 rc = is_bnxt_in_error(bp);
1698 /* Filter settings will get applied when port is started */
1699 if (!eth_dev->data->dev_started)
1702 if (bp->vnic_info == NULL)
1705 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1707 old_flags = vnic->flags;
1708 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1709 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1711 vnic->flags = old_flags;
1716 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1718 struct bnxt *bp = eth_dev->data->dev_private;
1719 struct bnxt_vnic_info *vnic;
1723 rc = is_bnxt_in_error(bp);
1727 /* Filter settings will get applied when port is started */
1728 if (!eth_dev->data->dev_started)
1731 if (bp->vnic_info == NULL)
1734 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1736 old_flags = vnic->flags;
1737 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1738 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1740 vnic->flags = old_flags;
1745 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1747 struct bnxt *bp = eth_dev->data->dev_private;
1748 struct bnxt_vnic_info *vnic;
1752 rc = is_bnxt_in_error(bp);
1756 /* Filter settings will get applied when port is started */
1757 if (!eth_dev->data->dev_started)
1760 if (bp->vnic_info == NULL)
1763 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1765 old_flags = vnic->flags;
1766 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1767 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1769 vnic->flags = old_flags;
1774 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1775 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1777 if (qid >= bp->rx_nr_rings)
1780 return bp->eth_dev->data->rx_queues[qid];
1783 /* Return rxq corresponding to a given rss table ring/group ID. */
1784 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1786 struct bnxt_rx_queue *rxq;
1789 if (!BNXT_HAS_RING_GRPS(bp)) {
1790 for (i = 0; i < bp->rx_nr_rings; i++) {
1791 rxq = bp->eth_dev->data->rx_queues[i];
1792 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1796 for (i = 0; i < bp->rx_nr_rings; i++) {
1797 if (bp->grp_info[i].fw_grp_id == fwr)
1802 return INVALID_HW_RING_ID;
1805 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1806 struct rte_eth_rss_reta_entry64 *reta_conf,
1809 struct bnxt *bp = eth_dev->data->dev_private;
1810 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1811 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1812 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1816 rc = is_bnxt_in_error(bp);
1820 if (!vnic->rss_table)
1823 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1826 if (reta_size != tbl_size) {
1827 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1828 "(%d) must equal the size supported by the hardware "
1829 "(%d)\n", reta_size, tbl_size);
1833 for (i = 0; i < reta_size; i++) {
1834 struct bnxt_rx_queue *rxq;
1836 idx = i / RTE_RETA_GROUP_SIZE;
1837 sft = i % RTE_RETA_GROUP_SIZE;
1839 if (!(reta_conf[idx].mask & (1ULL << sft)))
1842 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1844 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1848 if (BNXT_CHIP_P5(bp)) {
1849 vnic->rss_table[i * 2] =
1850 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1851 vnic->rss_table[i * 2 + 1] =
1852 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1854 vnic->rss_table[i] =
1855 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1859 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1863 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1864 struct rte_eth_rss_reta_entry64 *reta_conf,
1867 struct bnxt *bp = eth_dev->data->dev_private;
1868 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1869 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1870 uint16_t idx, sft, i;
1873 rc = is_bnxt_in_error(bp);
1877 /* Retrieve from the default VNIC */
1880 if (!vnic->rss_table)
1883 if (reta_size != tbl_size) {
1884 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1885 "(%d) must equal the size supported by the hardware "
1886 "(%d)\n", reta_size, tbl_size);
1890 for (idx = 0, i = 0; i < reta_size; i++) {
1891 idx = i / RTE_RETA_GROUP_SIZE;
1892 sft = i % RTE_RETA_GROUP_SIZE;
1894 if (reta_conf[idx].mask & (1ULL << sft)) {
1897 if (BNXT_CHIP_P5(bp))
1898 qid = bnxt_rss_to_qid(bp,
1899 vnic->rss_table[i * 2]);
1901 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1903 if (qid == INVALID_HW_RING_ID) {
1904 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1907 reta_conf[idx].reta[sft] = qid;
1914 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1915 struct rte_eth_rss_conf *rss_conf)
1917 struct bnxt *bp = eth_dev->data->dev_private;
1918 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1919 struct bnxt_vnic_info *vnic;
1922 rc = is_bnxt_in_error(bp);
1927 * If RSS enablement were different than dev_configure,
1928 * then return -EINVAL
1930 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1931 if (!rss_conf->rss_hf)
1932 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1934 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1938 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1939 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf,
1943 /* Update the default RSS VNIC(s) */
1944 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1945 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1947 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
1948 ETH_RSS_LEVEL(rss_conf->rss_hf));
1951 * If hashkey is not specified, use the previously configured
1954 if (!rss_conf->rss_key)
1957 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1959 "Invalid hashkey length, should be 16 bytes\n");
1962 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1965 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1969 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1970 struct rte_eth_rss_conf *rss_conf)
1972 struct bnxt *bp = eth_dev->data->dev_private;
1973 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1975 uint32_t hash_types;
1977 rc = is_bnxt_in_error(bp);
1981 /* RSS configuration is the same for all VNICs */
1982 if (vnic && vnic->rss_hash_key) {
1983 if (rss_conf->rss_key) {
1984 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1985 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1986 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1989 hash_types = vnic->hash_type;
1990 rss_conf->rss_hf = 0;
1991 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1992 rss_conf->rss_hf |= ETH_RSS_IPV4;
1993 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1995 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1996 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1998 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
2000 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
2001 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2003 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
2005 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
2006 rss_conf->rss_hf |= ETH_RSS_IPV6;
2007 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
2009 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
2010 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2012 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
2014 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
2015 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2017 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2021 bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2025 "Unknown RSS config from firmware (%08x), RSS disabled",
2030 rss_conf->rss_hf = 0;
2035 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2036 struct rte_eth_fc_conf *fc_conf)
2038 struct bnxt *bp = dev->data->dev_private;
2039 struct rte_eth_link link_info;
2042 rc = is_bnxt_in_error(bp);
2046 rc = bnxt_get_hwrm_link_config(bp, &link_info);
2050 memset(fc_conf, 0, sizeof(*fc_conf));
2051 if (bp->link_info->auto_pause)
2052 fc_conf->autoneg = 1;
2053 switch (bp->link_info->pause) {
2055 fc_conf->mode = RTE_FC_NONE;
2057 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2058 fc_conf->mode = RTE_FC_TX_PAUSE;
2060 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2061 fc_conf->mode = RTE_FC_RX_PAUSE;
2063 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2064 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2065 fc_conf->mode = RTE_FC_FULL;
2071 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2072 struct rte_eth_fc_conf *fc_conf)
2074 struct bnxt *bp = dev->data->dev_private;
2077 rc = is_bnxt_in_error(bp);
2081 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2082 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2086 switch (fc_conf->mode) {
2088 bp->link_info->auto_pause = 0;
2089 bp->link_info->force_pause = 0;
2091 case RTE_FC_RX_PAUSE:
2092 if (fc_conf->autoneg) {
2093 bp->link_info->auto_pause =
2094 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2095 bp->link_info->force_pause = 0;
2097 bp->link_info->auto_pause = 0;
2098 bp->link_info->force_pause =
2099 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2102 case RTE_FC_TX_PAUSE:
2103 if (fc_conf->autoneg) {
2104 bp->link_info->auto_pause =
2105 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2106 bp->link_info->force_pause = 0;
2108 bp->link_info->auto_pause = 0;
2109 bp->link_info->force_pause =
2110 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2114 if (fc_conf->autoneg) {
2115 bp->link_info->auto_pause =
2116 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2117 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2118 bp->link_info->force_pause = 0;
2120 bp->link_info->auto_pause = 0;
2121 bp->link_info->force_pause =
2122 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2123 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2127 return bnxt_set_hwrm_link_config(bp, true);
2130 /* Add UDP tunneling port */
2132 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2133 struct rte_eth_udp_tunnel *udp_tunnel)
2135 struct bnxt *bp = eth_dev->data->dev_private;
2136 uint16_t tunnel_type = 0;
2139 rc = is_bnxt_in_error(bp);
2143 switch (udp_tunnel->prot_type) {
2144 case RTE_TUNNEL_TYPE_VXLAN:
2145 if (bp->vxlan_port_cnt) {
2146 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2147 udp_tunnel->udp_port);
2148 if (bp->vxlan_port != udp_tunnel->udp_port) {
2149 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2152 bp->vxlan_port_cnt++;
2156 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2157 bp->vxlan_port_cnt++;
2159 case RTE_TUNNEL_TYPE_GENEVE:
2160 if (bp->geneve_port_cnt) {
2161 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2162 udp_tunnel->udp_port);
2163 if (bp->geneve_port != udp_tunnel->udp_port) {
2164 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2167 bp->geneve_port_cnt++;
2171 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2172 bp->geneve_port_cnt++;
2175 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2178 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2184 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2185 struct rte_eth_udp_tunnel *udp_tunnel)
2187 struct bnxt *bp = eth_dev->data->dev_private;
2188 uint16_t tunnel_type = 0;
2192 rc = is_bnxt_in_error(bp);
2196 switch (udp_tunnel->prot_type) {
2197 case RTE_TUNNEL_TYPE_VXLAN:
2198 if (!bp->vxlan_port_cnt) {
2199 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2202 if (bp->vxlan_port != udp_tunnel->udp_port) {
2203 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2204 udp_tunnel->udp_port, bp->vxlan_port);
2207 if (--bp->vxlan_port_cnt)
2211 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2212 port = bp->vxlan_fw_dst_port_id;
2214 case RTE_TUNNEL_TYPE_GENEVE:
2215 if (!bp->geneve_port_cnt) {
2216 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2219 if (bp->geneve_port != udp_tunnel->udp_port) {
2220 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2221 udp_tunnel->udp_port, bp->geneve_port);
2224 if (--bp->geneve_port_cnt)
2228 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2229 port = bp->geneve_fw_dst_port_id;
2232 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2236 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2240 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2242 struct bnxt_filter_info *filter;
2243 struct bnxt_vnic_info *vnic;
2245 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2247 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2248 filter = STAILQ_FIRST(&vnic->filter);
2250 /* Search for this matching MAC+VLAN filter */
2251 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2252 /* Delete the filter */
2253 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2256 STAILQ_REMOVE(&vnic->filter, filter,
2257 bnxt_filter_info, next);
2258 bnxt_free_filter(bp, filter);
2260 "Deleted vlan filter for %d\n",
2264 filter = STAILQ_NEXT(filter, next);
2269 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2271 struct bnxt_filter_info *filter;
2272 struct bnxt_vnic_info *vnic;
2274 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2275 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2276 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2278 /* Implementation notes on the use of VNIC in this command:
2280 * By default, these filters belong to default vnic for the function.
2281 * Once these filters are set up, only destination VNIC can be modified.
2282 * If the destination VNIC is not specified in this command,
2283 * then the HWRM shall only create an l2 context id.
2286 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2287 filter = STAILQ_FIRST(&vnic->filter);
2288 /* Check if the VLAN has already been added */
2290 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2293 filter = STAILQ_NEXT(filter, next);
2296 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2297 * command to create MAC+VLAN filter with the right flags, enables set.
2299 filter = bnxt_alloc_filter(bp);
2302 "MAC/VLAN filter alloc failed\n");
2305 /* MAC + VLAN ID filter */
2306 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2307 * untagged packets are received
2309 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2310 * packets and only the programmed vlan's packets are received
2312 filter->l2_ivlan = vlan_id;
2313 filter->l2_ivlan_mask = 0x0FFF;
2314 filter->enables |= en;
2315 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2317 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2319 /* Free the newly allocated filter as we were
2320 * not able to create the filter in hardware.
2322 bnxt_free_filter(bp, filter);
2326 filter->mac_index = 0;
2327 /* Add this new filter to the list */
2329 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2331 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2334 "Added Vlan filter for %d\n", vlan_id);
2338 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2339 uint16_t vlan_id, int on)
2341 struct bnxt *bp = eth_dev->data->dev_private;
2344 rc = is_bnxt_in_error(bp);
2348 if (!eth_dev->data->dev_started) {
2349 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2353 /* These operations apply to ALL existing MAC/VLAN filters */
2355 return bnxt_add_vlan_filter(bp, vlan_id);
2357 return bnxt_del_vlan_filter(bp, vlan_id);
2360 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2361 struct bnxt_vnic_info *vnic)
2363 struct bnxt_filter_info *filter;
2366 filter = STAILQ_FIRST(&vnic->filter);
2368 if (filter->mac_index == 0 &&
2369 !memcmp(filter->l2_addr, bp->mac_addr,
2370 RTE_ETHER_ADDR_LEN)) {
2371 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2373 STAILQ_REMOVE(&vnic->filter, filter,
2374 bnxt_filter_info, next);
2375 bnxt_free_filter(bp, filter);
2379 filter = STAILQ_NEXT(filter, next);
2385 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2387 struct bnxt_vnic_info *vnic;
2391 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2392 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2393 /* Remove any VLAN filters programmed */
2394 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2395 bnxt_del_vlan_filter(bp, i);
2397 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2401 /* Default filter will allow packets that match the
2402 * dest mac. So, it has to be deleted, otherwise, we
2403 * will endup receiving vlan packets for which the
2404 * filter is not programmed, when hw-vlan-filter
2405 * configuration is ON
2407 bnxt_del_dflt_mac_filter(bp, vnic);
2408 /* This filter will allow only untagged packets */
2409 bnxt_add_vlan_filter(bp, 0);
2411 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2412 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2417 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2419 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2423 /* Destroy vnic filters and vnic */
2424 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2425 DEV_RX_OFFLOAD_VLAN_FILTER) {
2426 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2427 bnxt_del_vlan_filter(bp, i);
2429 bnxt_del_dflt_mac_filter(bp, vnic);
2431 rc = bnxt_hwrm_vnic_free(bp, vnic);
2435 rte_free(vnic->fw_grp_ids);
2436 vnic->fw_grp_ids = NULL;
2438 vnic->rx_queue_cnt = 0;
2444 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2446 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2449 /* Destroy, recreate and reconfigure the default vnic */
2450 rc = bnxt_free_one_vnic(bp, 0);
2454 /* default vnic 0 */
2455 rc = bnxt_setup_one_vnic(bp, 0);
2459 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2460 DEV_RX_OFFLOAD_VLAN_FILTER) {
2461 rc = bnxt_add_vlan_filter(bp, 0);
2464 rc = bnxt_restore_vlan_filters(bp);
2468 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2473 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2477 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2478 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2484 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2486 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2487 struct bnxt *bp = dev->data->dev_private;
2490 rc = is_bnxt_in_error(bp);
2494 /* Filter settings will get applied when port is started */
2495 if (!dev->data->dev_started)
2498 if (mask & ETH_VLAN_FILTER_MASK) {
2499 /* Enable or disable VLAN filtering */
2500 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2505 if (mask & ETH_VLAN_STRIP_MASK) {
2506 /* Enable or disable VLAN stripping */
2507 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2512 if (mask & ETH_VLAN_EXTEND_MASK) {
2513 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2514 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2516 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2523 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2526 struct bnxt *bp = dev->data->dev_private;
2527 int qinq = dev->data->dev_conf.rxmode.offloads &
2528 DEV_RX_OFFLOAD_VLAN_EXTEND;
2530 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2531 vlan_type != ETH_VLAN_TYPE_OUTER) {
2533 "Unsupported vlan type.");
2538 "QinQ not enabled. Needs to be ON as we can "
2539 "accelerate only outer vlan\n");
2543 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2545 case RTE_ETHER_TYPE_QINQ:
2547 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2549 case RTE_ETHER_TYPE_VLAN:
2551 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2553 case RTE_ETHER_TYPE_QINQ1:
2555 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2557 case RTE_ETHER_TYPE_QINQ2:
2559 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2561 case RTE_ETHER_TYPE_QINQ3:
2563 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2566 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2569 bp->outer_tpid_bd |= tpid;
2570 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2571 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2573 "Can accelerate only outer vlan in QinQ\n");
2581 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2582 struct rte_ether_addr *addr)
2584 struct bnxt *bp = dev->data->dev_private;
2585 /* Default Filter is tied to VNIC 0 */
2586 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2589 rc = is_bnxt_in_error(bp);
2593 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2596 if (rte_is_zero_ether_addr(addr))
2599 /* Filter settings will get applied when port is started */
2600 if (!dev->data->dev_started)
2603 /* Check if the requested MAC is already added */
2604 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2607 /* Destroy filter and re-create it */
2608 bnxt_del_dflt_mac_filter(bp, vnic);
2610 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2611 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2612 /* This filter will allow only untagged packets */
2613 rc = bnxt_add_vlan_filter(bp, 0);
2615 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2618 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2623 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2624 struct rte_ether_addr *mc_addr_set,
2625 uint32_t nb_mc_addr)
2627 struct bnxt *bp = eth_dev->data->dev_private;
2628 char *mc_addr_list = (char *)mc_addr_set;
2629 struct bnxt_vnic_info *vnic;
2630 uint32_t off = 0, i = 0;
2633 rc = is_bnxt_in_error(bp);
2637 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2639 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2640 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2644 /* TODO Check for Duplicate mcast addresses */
2645 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2646 for (i = 0; i < nb_mc_addr; i++) {
2647 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2648 RTE_ETHER_ADDR_LEN);
2649 off += RTE_ETHER_ADDR_LEN;
2652 vnic->mc_addr_cnt = i;
2653 if (vnic->mc_addr_cnt)
2654 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2656 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2659 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2663 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2665 struct bnxt *bp = dev->data->dev_private;
2666 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2667 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2668 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2669 uint8_t fw_rsvd = bp->fw_ver & 0xff;
2672 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2673 fw_major, fw_minor, fw_updt, fw_rsvd);
2675 ret += 1; /* add the size of '\0' */
2676 if (fw_size < (uint32_t)ret)
2683 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2684 struct rte_eth_rxq_info *qinfo)
2686 struct bnxt *bp = dev->data->dev_private;
2687 struct bnxt_rx_queue *rxq;
2689 if (is_bnxt_in_error(bp))
2692 rxq = dev->data->rx_queues[queue_id];
2694 qinfo->mp = rxq->mb_pool;
2695 qinfo->scattered_rx = dev->data->scattered_rx;
2696 qinfo->nb_desc = rxq->nb_rx_desc;
2698 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2699 qinfo->conf.rx_drop_en = rxq->drop_en;
2700 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2701 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2705 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2706 struct rte_eth_txq_info *qinfo)
2708 struct bnxt *bp = dev->data->dev_private;
2709 struct bnxt_tx_queue *txq;
2711 if (is_bnxt_in_error(bp))
2714 txq = dev->data->tx_queues[queue_id];
2716 qinfo->nb_desc = txq->nb_tx_desc;
2718 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2719 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2720 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2722 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2723 qinfo->conf.tx_rs_thresh = 0;
2724 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2725 qinfo->conf.offloads = txq->offloads;
2728 static const struct {
2729 eth_rx_burst_t pkt_burst;
2731 } bnxt_rx_burst_info[] = {
2732 {bnxt_recv_pkts, "Scalar"},
2733 #if defined(RTE_ARCH_X86)
2734 {bnxt_recv_pkts_vec, "Vector SSE"},
2735 #elif defined(RTE_ARCH_ARM64)
2736 {bnxt_recv_pkts_vec, "Vector Neon"},
2741 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2742 struct rte_eth_burst_mode *mode)
2744 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2747 for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2748 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2749 snprintf(mode->info, sizeof(mode->info), "%s",
2750 bnxt_rx_burst_info[i].info);
2758 static const struct {
2759 eth_tx_burst_t pkt_burst;
2761 } bnxt_tx_burst_info[] = {
2762 {bnxt_xmit_pkts, "Scalar"},
2763 #if defined(RTE_ARCH_X86)
2764 {bnxt_xmit_pkts_vec, "Vector SSE"},
2765 #elif defined(RTE_ARCH_ARM64)
2766 {bnxt_xmit_pkts_vec, "Vector Neon"},
2771 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2772 struct rte_eth_burst_mode *mode)
2774 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2777 for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2778 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2779 snprintf(mode->info, sizeof(mode->info), "%s",
2780 bnxt_tx_burst_info[i].info);
2788 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2790 struct bnxt *bp = eth_dev->data->dev_private;
2791 uint32_t new_pkt_size;
2795 rc = is_bnxt_in_error(bp);
2799 /* Exit if receive queues are not configured yet */
2800 if (!eth_dev->data->nb_rx_queues)
2803 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2804 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2807 * Disallow any MTU change that would require scattered receive support
2808 * if it is not already enabled.
2810 if (eth_dev->data->dev_started &&
2811 !eth_dev->data->scattered_rx &&
2813 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2815 "MTU change would require scattered rx support. ");
2816 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2820 if (new_mtu > RTE_ETHER_MTU) {
2821 bp->flags |= BNXT_FLAG_JUMBO;
2822 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2823 DEV_RX_OFFLOAD_JUMBO_FRAME;
2825 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2826 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2827 bp->flags &= ~BNXT_FLAG_JUMBO;
2830 /* Is there a change in mtu setting? */
2831 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2834 for (i = 0; i < bp->nr_vnics; i++) {
2835 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2838 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2839 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2843 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2844 size -= RTE_PKTMBUF_HEADROOM;
2846 if (size < new_mtu) {
2847 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2854 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2856 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2862 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2864 struct bnxt *bp = dev->data->dev_private;
2865 uint16_t vlan = bp->vlan;
2868 rc = is_bnxt_in_error(bp);
2872 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2874 "PVID cannot be modified for this function\n");
2877 bp->vlan = on ? pvid : 0;
2879 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2886 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2888 struct bnxt *bp = dev->data->dev_private;
2891 rc = is_bnxt_in_error(bp);
2895 return bnxt_hwrm_port_led_cfg(bp, true);
2899 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2901 struct bnxt *bp = dev->data->dev_private;
2904 rc = is_bnxt_in_error(bp);
2908 return bnxt_hwrm_port_led_cfg(bp, false);
2912 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2914 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2915 uint32_t desc = 0, raw_cons = 0, cons;
2916 struct bnxt_cp_ring_info *cpr;
2917 struct bnxt_rx_queue *rxq;
2918 struct rx_pkt_cmpl *rxcmp;
2921 rc = is_bnxt_in_error(bp);
2925 rxq = dev->data->rx_queues[rx_queue_id];
2927 raw_cons = cpr->cp_raw_cons;
2930 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2931 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2932 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2934 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2946 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2948 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2949 struct bnxt_rx_ring_info *rxr;
2950 struct bnxt_cp_ring_info *cpr;
2951 struct rte_mbuf *rx_buf;
2952 struct rx_pkt_cmpl *rxcmp;
2953 uint32_t cons, cp_cons;
2959 rc = is_bnxt_in_error(rxq->bp);
2966 if (offset >= rxq->nb_rx_desc)
2969 cons = RING_CMP(cpr->cp_ring_struct, offset);
2970 cp_cons = cpr->cp_raw_cons;
2971 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2973 if (cons > cp_cons) {
2974 if (CMPL_VALID(rxcmp, cpr->valid))
2975 return RTE_ETH_RX_DESC_DONE;
2977 if (CMPL_VALID(rxcmp, !cpr->valid))
2978 return RTE_ETH_RX_DESC_DONE;
2980 rx_buf = rxr->rx_buf_ring[cons];
2981 if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf)
2982 return RTE_ETH_RX_DESC_UNAVAIL;
2985 return RTE_ETH_RX_DESC_AVAIL;
2989 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2991 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2992 struct bnxt_tx_ring_info *txr;
2993 struct bnxt_cp_ring_info *cpr;
2994 struct bnxt_sw_tx_bd *tx_buf;
2995 struct tx_pkt_cmpl *txcmp;
2996 uint32_t cons, cp_cons;
3002 rc = is_bnxt_in_error(txq->bp);
3009 if (offset >= txq->nb_tx_desc)
3012 cons = RING_CMP(cpr->cp_ring_struct, offset);
3013 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3014 cp_cons = cpr->cp_raw_cons;
3016 if (cons > cp_cons) {
3017 if (CMPL_VALID(txcmp, cpr->valid))
3018 return RTE_ETH_TX_DESC_UNAVAIL;
3020 if (CMPL_VALID(txcmp, !cpr->valid))
3021 return RTE_ETH_TX_DESC_UNAVAIL;
3023 tx_buf = &txr->tx_buf_ring[cons];
3024 if (tx_buf->mbuf == NULL)
3025 return RTE_ETH_TX_DESC_DONE;
3027 return RTE_ETH_TX_DESC_FULL;
3031 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3032 enum rte_filter_type filter_type,
3033 enum rte_filter_op filter_op, void *arg)
3035 struct bnxt *bp = dev->data->dev_private;
3041 if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3042 struct bnxt_representor *vfr = dev->data->dev_private;
3043 bp = vfr->parent_dev->data->dev_private;
3044 /* parent is deleted while children are still valid */
3046 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n",
3054 ret = is_bnxt_in_error(bp);
3058 switch (filter_type) {
3059 case RTE_ETH_FILTER_GENERIC:
3060 if (filter_op != RTE_ETH_FILTER_GET)
3063 /* PMD supports thread-safe flow operations. rte_flow API
3064 * functions can avoid mutex for multi-thread safety.
3066 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3068 if (BNXT_TRUFLOW_EN(bp))
3069 *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3071 *(const void **)arg = &bnxt_flow_ops;
3075 "Filter type (%d) not supported", filter_type);
3082 static const uint32_t *
3083 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3085 static const uint32_t ptypes[] = {
3086 RTE_PTYPE_L2_ETHER_VLAN,
3087 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3088 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3092 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3093 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3094 RTE_PTYPE_INNER_L4_ICMP,
3095 RTE_PTYPE_INNER_L4_TCP,
3096 RTE_PTYPE_INNER_L4_UDP,
3100 if (!dev->rx_pkt_burst)
3106 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3109 uint32_t reg_base = *reg_arr & 0xfffff000;
3113 for (i = 0; i < count; i++) {
3114 if ((reg_arr[i] & 0xfffff000) != reg_base)
3117 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3118 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3122 static int bnxt_map_ptp_regs(struct bnxt *bp)
3124 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3128 reg_arr = ptp->rx_regs;
3129 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3133 reg_arr = ptp->tx_regs;
3134 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3138 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3139 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3141 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3142 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3147 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3149 rte_write32(0, (uint8_t *)bp->bar0 +
3150 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3151 rte_write32(0, (uint8_t *)bp->bar0 +
3152 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3155 static uint64_t bnxt_cc_read(struct bnxt *bp)
3159 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3160 BNXT_GRCPF_REG_SYNC_TIME));
3161 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3162 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3166 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3168 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3171 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3172 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3173 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3176 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3177 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3178 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3179 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3180 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3181 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3186 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3188 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3189 struct bnxt_pf_info *pf = bp->pf;
3196 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3197 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3198 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3201 port_id = pf->port_id;
3202 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3203 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3205 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3206 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3207 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3208 /* bnxt_clr_rx_ts(bp); TBD */
3212 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3213 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3214 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3215 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3221 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3224 struct bnxt *bp = dev->data->dev_private;
3225 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3230 ns = rte_timespec_to_ns(ts);
3231 /* Set the timecounters to a new value. */
3238 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3240 struct bnxt *bp = dev->data->dev_private;
3241 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3242 uint64_t ns, systime_cycles = 0;
3248 if (BNXT_CHIP_P5(bp))
3249 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3252 systime_cycles = bnxt_cc_read(bp);
3254 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3255 *ts = rte_ns_to_timespec(ns);
3260 bnxt_timesync_enable(struct rte_eth_dev *dev)
3262 struct bnxt *bp = dev->data->dev_private;
3263 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3271 ptp->tx_tstamp_en = 1;
3272 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3274 rc = bnxt_hwrm_ptp_cfg(bp);
3278 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3279 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3280 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3282 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3283 ptp->tc.cc_shift = shift;
3284 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3286 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3287 ptp->rx_tstamp_tc.cc_shift = shift;
3288 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3290 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3291 ptp->tx_tstamp_tc.cc_shift = shift;
3292 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3294 if (!BNXT_CHIP_P5(bp))
3295 bnxt_map_ptp_regs(bp);
3301 bnxt_timesync_disable(struct rte_eth_dev *dev)
3303 struct bnxt *bp = dev->data->dev_private;
3304 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3310 ptp->tx_tstamp_en = 0;
3313 bnxt_hwrm_ptp_cfg(bp);
3315 if (!BNXT_CHIP_P5(bp))
3316 bnxt_unmap_ptp_regs(bp);
3322 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3323 struct timespec *timestamp,
3324 uint32_t flags __rte_unused)
3326 struct bnxt *bp = dev->data->dev_private;
3327 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3328 uint64_t rx_tstamp_cycles = 0;
3334 if (BNXT_CHIP_P5(bp))
3335 rx_tstamp_cycles = ptp->rx_timestamp;
3337 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3339 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3340 *timestamp = rte_ns_to_timespec(ns);
3345 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3346 struct timespec *timestamp)
3348 struct bnxt *bp = dev->data->dev_private;
3349 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3350 uint64_t tx_tstamp_cycles = 0;
3357 if (BNXT_CHIP_P5(bp))
3358 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3361 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3363 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3364 *timestamp = rte_ns_to_timespec(ns);
3370 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3372 struct bnxt *bp = dev->data->dev_private;
3373 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3378 ptp->tc.nsec += delta;
3384 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3386 struct bnxt *bp = dev->data->dev_private;
3388 uint32_t dir_entries;
3389 uint32_t entry_length;
3391 rc = is_bnxt_in_error(bp);
3395 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3396 bp->pdev->addr.domain, bp->pdev->addr.bus,
3397 bp->pdev->addr.devid, bp->pdev->addr.function);
3399 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3403 return dir_entries * entry_length;
3407 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3408 struct rte_dev_eeprom_info *in_eeprom)
3410 struct bnxt *bp = dev->data->dev_private;
3415 rc = is_bnxt_in_error(bp);
3419 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3420 bp->pdev->addr.domain, bp->pdev->addr.bus,
3421 bp->pdev->addr.devid, bp->pdev->addr.function,
3422 in_eeprom->offset, in_eeprom->length);
3424 if (in_eeprom->offset == 0) /* special offset value to get directory */
3425 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3428 index = in_eeprom->offset >> 24;
3429 offset = in_eeprom->offset & 0xffffff;
3432 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3433 in_eeprom->length, in_eeprom->data);
3438 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3441 case BNX_DIR_TYPE_CHIMP_PATCH:
3442 case BNX_DIR_TYPE_BOOTCODE:
3443 case BNX_DIR_TYPE_BOOTCODE_2:
3444 case BNX_DIR_TYPE_APE_FW:
3445 case BNX_DIR_TYPE_APE_PATCH:
3446 case BNX_DIR_TYPE_KONG_FW:
3447 case BNX_DIR_TYPE_KONG_PATCH:
3448 case BNX_DIR_TYPE_BONO_FW:
3449 case BNX_DIR_TYPE_BONO_PATCH:
3457 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3460 case BNX_DIR_TYPE_AVS:
3461 case BNX_DIR_TYPE_EXP_ROM_MBA:
3462 case BNX_DIR_TYPE_PCIE:
3463 case BNX_DIR_TYPE_TSCF_UCODE:
3464 case BNX_DIR_TYPE_EXT_PHY:
3465 case BNX_DIR_TYPE_CCM:
3466 case BNX_DIR_TYPE_ISCSI_BOOT:
3467 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3468 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3476 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3478 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3479 bnxt_dir_type_is_other_exec_format(dir_type);
3483 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3484 struct rte_dev_eeprom_info *in_eeprom)
3486 struct bnxt *bp = dev->data->dev_private;
3487 uint8_t index, dir_op;
3488 uint16_t type, ext, ordinal, attr;
3491 rc = is_bnxt_in_error(bp);
3495 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3496 bp->pdev->addr.domain, bp->pdev->addr.bus,
3497 bp->pdev->addr.devid, bp->pdev->addr.function,
3498 in_eeprom->offset, in_eeprom->length);
3501 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3505 type = in_eeprom->magic >> 16;
3507 if (type == 0xffff) { /* special value for directory operations */
3508 index = in_eeprom->magic & 0xff;
3509 dir_op = in_eeprom->magic >> 8;
3513 case 0x0e: /* erase */
3514 if (in_eeprom->offset != ~in_eeprom->magic)
3516 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3522 /* Create or re-write an NVM item: */
3523 if (bnxt_dir_type_is_executable(type) == true)
3525 ext = in_eeprom->magic & 0xffff;
3526 ordinal = in_eeprom->offset >> 16;
3527 attr = in_eeprom->offset & 0xffff;
3529 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3530 in_eeprom->data, in_eeprom->length);
3537 static const struct eth_dev_ops bnxt_dev_ops = {
3538 .dev_infos_get = bnxt_dev_info_get_op,
3539 .dev_close = bnxt_dev_close_op,
3540 .dev_configure = bnxt_dev_configure_op,
3541 .dev_start = bnxt_dev_start_op,
3542 .dev_stop = bnxt_dev_stop_op,
3543 .dev_set_link_up = bnxt_dev_set_link_up_op,
3544 .dev_set_link_down = bnxt_dev_set_link_down_op,
3545 .stats_get = bnxt_stats_get_op,
3546 .stats_reset = bnxt_stats_reset_op,
3547 .rx_queue_setup = bnxt_rx_queue_setup_op,
3548 .rx_queue_release = bnxt_rx_queue_release_op,
3549 .tx_queue_setup = bnxt_tx_queue_setup_op,
3550 .tx_queue_release = bnxt_tx_queue_release_op,
3551 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3552 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3553 .reta_update = bnxt_reta_update_op,
3554 .reta_query = bnxt_reta_query_op,
3555 .rss_hash_update = bnxt_rss_hash_update_op,
3556 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3557 .link_update = bnxt_link_update_op,
3558 .promiscuous_enable = bnxt_promiscuous_enable_op,
3559 .promiscuous_disable = bnxt_promiscuous_disable_op,
3560 .allmulticast_enable = bnxt_allmulticast_enable_op,
3561 .allmulticast_disable = bnxt_allmulticast_disable_op,
3562 .mac_addr_add = bnxt_mac_addr_add_op,
3563 .mac_addr_remove = bnxt_mac_addr_remove_op,
3564 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3565 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3566 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3567 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3568 .vlan_filter_set = bnxt_vlan_filter_set_op,
3569 .vlan_offload_set = bnxt_vlan_offload_set_op,
3570 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3571 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3572 .mtu_set = bnxt_mtu_set_op,
3573 .mac_addr_set = bnxt_set_default_mac_addr_op,
3574 .xstats_get = bnxt_dev_xstats_get_op,
3575 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3576 .xstats_reset = bnxt_dev_xstats_reset_op,
3577 .fw_version_get = bnxt_fw_version_get,
3578 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3579 .rxq_info_get = bnxt_rxq_info_get_op,
3580 .txq_info_get = bnxt_txq_info_get_op,
3581 .rx_burst_mode_get = bnxt_rx_burst_mode_get,
3582 .tx_burst_mode_get = bnxt_tx_burst_mode_get,
3583 .dev_led_on = bnxt_dev_led_on_op,
3584 .dev_led_off = bnxt_dev_led_off_op,
3585 .rx_queue_start = bnxt_rx_queue_start,
3586 .rx_queue_stop = bnxt_rx_queue_stop,
3587 .tx_queue_start = bnxt_tx_queue_start,
3588 .tx_queue_stop = bnxt_tx_queue_stop,
3589 .filter_ctrl = bnxt_filter_ctrl_op,
3590 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3591 .get_eeprom_length = bnxt_get_eeprom_length_op,
3592 .get_eeprom = bnxt_get_eeprom_op,
3593 .set_eeprom = bnxt_set_eeprom_op,
3594 .timesync_enable = bnxt_timesync_enable,
3595 .timesync_disable = bnxt_timesync_disable,
3596 .timesync_read_time = bnxt_timesync_read_time,
3597 .timesync_write_time = bnxt_timesync_write_time,
3598 .timesync_adjust_time = bnxt_timesync_adjust_time,
3599 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3600 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3603 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3607 /* Only pre-map the reset GRC registers using window 3 */
3608 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3609 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3611 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3616 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3618 struct bnxt_error_recovery_info *info = bp->recovery_info;
3619 uint32_t reg_base = 0xffffffff;
3622 /* Only pre-map the monitoring GRC registers using window 2 */
3623 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3624 uint32_t reg = info->status_regs[i];
3626 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3629 if (reg_base == 0xffffffff)
3630 reg_base = reg & 0xfffff000;
3631 if ((reg & 0xfffff000) != reg_base)
3634 /* Use mask 0xffc as the Lower 2 bits indicates
3635 * address space location
3637 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3641 if (reg_base == 0xffffffff)
3644 rte_write32(reg_base, (uint8_t *)bp->bar0 +
3645 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3650 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3652 struct bnxt_error_recovery_info *info = bp->recovery_info;
3653 uint32_t delay = info->delay_after_reset[index];
3654 uint32_t val = info->reset_reg_val[index];
3655 uint32_t reg = info->reset_reg[index];
3656 uint32_t type, offset;
3658 type = BNXT_FW_STATUS_REG_TYPE(reg);
3659 offset = BNXT_FW_STATUS_REG_OFF(reg);
3662 case BNXT_FW_STATUS_REG_TYPE_CFG:
3663 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3665 case BNXT_FW_STATUS_REG_TYPE_GRC:
3666 offset = bnxt_map_reset_regs(bp, offset);
3667 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3669 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3670 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3673 /* wait on a specific interval of time until core reset is complete */
3675 rte_delay_ms(delay);
3678 static void bnxt_dev_cleanup(struct bnxt *bp)
3680 bp->eth_dev->data->dev_link.link_status = 0;
3681 bp->link_info->link_up = 0;
3682 if (bp->eth_dev->data->dev_started)
3683 bnxt_dev_stop_op(bp->eth_dev);
3685 bnxt_uninit_resources(bp, true);
3688 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3690 struct rte_eth_dev *dev = bp->eth_dev;
3691 struct rte_vlan_filter_conf *vfc;
3695 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3696 vfc = &dev->data->vlan_filter_conf;
3697 vidx = vlan_id / 64;
3698 vbit = vlan_id % 64;
3700 /* Each bit corresponds to a VLAN id */
3701 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3702 rc = bnxt_add_vlan_filter(bp, vlan_id);
3711 static int bnxt_restore_mac_filters(struct bnxt *bp)
3713 struct rte_eth_dev *dev = bp->eth_dev;
3714 struct rte_eth_dev_info dev_info;
3715 struct rte_ether_addr *addr;
3721 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3724 rc = bnxt_dev_info_get_op(dev, &dev_info);
3728 /* replay MAC address configuration */
3729 for (i = 1; i < dev_info.max_mac_addrs; i++) {
3730 addr = &dev->data->mac_addrs[i];
3732 /* skip zero address */
3733 if (rte_is_zero_ether_addr(addr))
3737 pool_mask = dev->data->mac_pool_sel[i];
3740 if (pool_mask & 1ULL) {
3741 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3747 } while (pool_mask);
3753 static int bnxt_restore_filters(struct bnxt *bp)
3755 struct rte_eth_dev *dev = bp->eth_dev;
3758 if (dev->data->all_multicast) {
3759 ret = bnxt_allmulticast_enable_op(dev);
3763 if (dev->data->promiscuous) {
3764 ret = bnxt_promiscuous_enable_op(dev);
3769 ret = bnxt_restore_mac_filters(bp);
3773 ret = bnxt_restore_vlan_filters(bp);
3774 /* TODO restore other filters as well */
3778 static void bnxt_dev_recover(void *arg)
3780 struct bnxt *bp = arg;
3781 int timeout = bp->fw_reset_max_msecs;
3784 /* Clear Error flag so that device re-init should happen */
3785 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3788 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
3791 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3792 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3793 } while (rc && timeout);
3796 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3800 rc = bnxt_init_resources(bp, true);
3803 "Failed to initialize resources after reset\n");
3806 /* clear reset flag as the device is initialized now */
3807 bp->flags &= ~BNXT_FLAG_FW_RESET;
3809 rc = bnxt_dev_start_op(bp->eth_dev);
3811 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3815 rc = bnxt_restore_filters(bp);
3819 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3822 bnxt_dev_stop_op(bp->eth_dev);
3824 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3825 bnxt_uninit_resources(bp, false);
3826 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3829 void bnxt_dev_reset_and_resume(void *arg)
3831 struct bnxt *bp = arg;
3834 bnxt_dev_cleanup(bp);
3836 bnxt_wait_for_device_shutdown(bp);
3838 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3839 bnxt_dev_recover, (void *)bp);
3841 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3844 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3846 struct bnxt_error_recovery_info *info = bp->recovery_info;
3847 uint32_t reg = info->status_regs[index];
3848 uint32_t type, offset, val = 0;
3850 type = BNXT_FW_STATUS_REG_TYPE(reg);
3851 offset = BNXT_FW_STATUS_REG_OFF(reg);
3854 case BNXT_FW_STATUS_REG_TYPE_CFG:
3855 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3857 case BNXT_FW_STATUS_REG_TYPE_GRC:
3858 offset = info->mapped_status_regs[index];
3860 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3861 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3869 static int bnxt_fw_reset_all(struct bnxt *bp)
3871 struct bnxt_error_recovery_info *info = bp->recovery_info;
3875 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3876 /* Reset through master function driver */
3877 for (i = 0; i < info->reg_array_cnt; i++)
3878 bnxt_write_fw_reset_reg(bp, i);
3879 /* Wait for time specified by FW after triggering reset */
3880 rte_delay_ms(info->master_func_wait_period_after_reset);
3881 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3882 /* Reset with the help of Kong processor */
3883 rc = bnxt_hwrm_fw_reset(bp);
3885 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3891 static void bnxt_fw_reset_cb(void *arg)
3893 struct bnxt *bp = arg;
3894 struct bnxt_error_recovery_info *info = bp->recovery_info;
3897 /* Only Master function can do FW reset */
3898 if (bnxt_is_master_func(bp) &&
3899 bnxt_is_recovery_enabled(bp)) {
3900 rc = bnxt_fw_reset_all(bp);
3902 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3907 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3908 * EXCEPTION_FATAL_ASYNC event to all the functions
3909 * (including MASTER FUNC). After receiving this Async, all the active
3910 * drivers should treat this case as FW initiated recovery
3912 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3913 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3914 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3916 /* To recover from error */
3917 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3922 /* Driver should poll FW heartbeat, reset_counter with the frequency
3923 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3924 * When the driver detects heartbeat stop or change in reset_counter,
3925 * it has to trigger a reset to recover from the error condition.
3926 * A “master PF” is the function who will have the privilege to
3927 * initiate the chimp reset. The master PF will be elected by the
3928 * firmware and will be notified through async message.
3930 static void bnxt_check_fw_health(void *arg)
3932 struct bnxt *bp = arg;
3933 struct bnxt_error_recovery_info *info = bp->recovery_info;
3934 uint32_t val = 0, wait_msec;
3936 if (!info || !bnxt_is_recovery_enabled(bp) ||
3937 is_bnxt_in_error(bp))
3940 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3941 if (val == info->last_heart_beat)
3944 info->last_heart_beat = val;
3946 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3947 if (val != info->last_reset_counter)
3950 info->last_reset_counter = val;
3952 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3953 bnxt_check_fw_health, (void *)bp);
3957 /* Stop DMA to/from device */
3958 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3959 bp->flags |= BNXT_FLAG_FW_RESET;
3961 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
3963 if (bnxt_is_master_func(bp))
3964 wait_msec = info->master_func_wait_period;
3966 wait_msec = info->normal_func_wait_period;
3968 rte_eal_alarm_set(US_PER_MS * wait_msec,
3969 bnxt_fw_reset_cb, (void *)bp);
3972 void bnxt_schedule_fw_health_check(struct bnxt *bp)
3974 uint32_t polling_freq;
3976 pthread_mutex_lock(&bp->health_check_lock);
3978 if (!bnxt_is_recovery_enabled(bp))
3981 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
3984 polling_freq = bp->recovery_info->driver_polling_freq;
3986 rte_eal_alarm_set(US_PER_MS * polling_freq,
3987 bnxt_check_fw_health, (void *)bp);
3988 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3991 pthread_mutex_unlock(&bp->health_check_lock);
3994 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
3996 if (!bnxt_is_recovery_enabled(bp))
3999 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4000 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4003 static bool bnxt_vf_pciid(uint16_t device_id)
4005 switch (device_id) {
4006 case BROADCOM_DEV_ID_57304_VF:
4007 case BROADCOM_DEV_ID_57406_VF:
4008 case BROADCOM_DEV_ID_5731X_VF:
4009 case BROADCOM_DEV_ID_5741X_VF:
4010 case BROADCOM_DEV_ID_57414_VF:
4011 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4012 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4013 case BROADCOM_DEV_ID_58802_VF:
4014 case BROADCOM_DEV_ID_57500_VF1:
4015 case BROADCOM_DEV_ID_57500_VF2:
4016 case BROADCOM_DEV_ID_58818_VF:
4024 /* Phase 5 device */
4025 static bool bnxt_p5_device(uint16_t device_id)
4027 switch (device_id) {
4028 case BROADCOM_DEV_ID_57508:
4029 case BROADCOM_DEV_ID_57504:
4030 case BROADCOM_DEV_ID_57502:
4031 case BROADCOM_DEV_ID_57508_MF1:
4032 case BROADCOM_DEV_ID_57504_MF1:
4033 case BROADCOM_DEV_ID_57502_MF1:
4034 case BROADCOM_DEV_ID_57508_MF2:
4035 case BROADCOM_DEV_ID_57504_MF2:
4036 case BROADCOM_DEV_ID_57502_MF2:
4037 case BROADCOM_DEV_ID_57500_VF1:
4038 case BROADCOM_DEV_ID_57500_VF2:
4039 case BROADCOM_DEV_ID_58812:
4040 case BROADCOM_DEV_ID_58814:
4041 case BROADCOM_DEV_ID_58818:
4042 case BROADCOM_DEV_ID_58818_VF:
4050 bool bnxt_stratus_device(struct bnxt *bp)
4052 uint16_t device_id = bp->pdev->id.device_id;
4054 switch (device_id) {
4055 case BROADCOM_DEV_ID_STRATUS_NIC:
4056 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4057 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4065 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4067 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4068 struct bnxt *bp = eth_dev->data->dev_private;
4070 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4071 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4072 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4073 if (!bp->bar0 || !bp->doorbell_base) {
4074 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4078 bp->eth_dev = eth_dev;
4084 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4085 struct bnxt_ctx_pg_info *ctx_pg,
4090 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4091 const struct rte_memzone *mz = NULL;
4092 char mz_name[RTE_MEMZONE_NAMESIZE];
4093 rte_iova_t mz_phys_addr;
4094 uint64_t valid_bits = 0;
4101 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4103 rmem->page_size = BNXT_PAGE_SIZE;
4104 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4105 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4106 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4108 valid_bits = PTU_PTE_VALID;
4110 if (rmem->nr_pages > 1) {
4111 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4112 "bnxt_ctx_pg_tbl%s_%x_%d",
4113 suffix, idx, bp->eth_dev->data->port_id);
4114 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4115 mz = rte_memzone_lookup(mz_name);
4117 mz = rte_memzone_reserve_aligned(mz_name,
4121 RTE_MEMZONE_SIZE_HINT_ONLY |
4122 RTE_MEMZONE_IOVA_CONTIG,
4128 memset(mz->addr, 0, mz->len);
4129 mz_phys_addr = mz->iova;
4131 rmem->pg_tbl = mz->addr;
4132 rmem->pg_tbl_map = mz_phys_addr;
4133 rmem->pg_tbl_mz = mz;
4136 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4137 suffix, idx, bp->eth_dev->data->port_id);
4138 mz = rte_memzone_lookup(mz_name);
4140 mz = rte_memzone_reserve_aligned(mz_name,
4144 RTE_MEMZONE_SIZE_HINT_ONLY |
4145 RTE_MEMZONE_IOVA_CONTIG,
4151 memset(mz->addr, 0, mz->len);
4152 mz_phys_addr = mz->iova;
4154 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4155 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4156 rmem->dma_arr[i] = mz_phys_addr + sz;
4158 if (rmem->nr_pages > 1) {
4159 if (i == rmem->nr_pages - 2 &&
4160 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4161 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4162 else if (i == rmem->nr_pages - 1 &&
4163 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4164 valid_bits |= PTU_PTE_LAST;
4166 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4172 if (rmem->vmem_size)
4173 rmem->vmem = (void **)mz->addr;
4174 rmem->dma_arr[0] = mz_phys_addr;
4178 static void bnxt_free_ctx_mem(struct bnxt *bp)
4182 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4185 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4186 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4187 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4188 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4189 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4190 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4191 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4192 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4193 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4194 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4195 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4197 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4198 if (bp->ctx->tqm_mem[i])
4199 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4206 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4208 #define min_t(type, x, y) ({ \
4209 type __min1 = (x); \
4210 type __min2 = (y); \
4211 __min1 < __min2 ? __min1 : __min2; })
4213 #define max_t(type, x, y) ({ \
4214 type __max1 = (x); \
4215 type __max2 = (y); \
4216 __max1 > __max2 ? __max1 : __max2; })
4218 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4220 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4222 struct bnxt_ctx_pg_info *ctx_pg;
4223 struct bnxt_ctx_mem_info *ctx;
4224 uint32_t mem_size, ena, entries;
4225 uint32_t entries_sp, min;
4228 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4230 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4234 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4237 ctx_pg = &ctx->qp_mem;
4238 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4239 if (ctx->qp_entry_size) {
4240 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4241 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4246 ctx_pg = &ctx->srq_mem;
4247 ctx_pg->entries = ctx->srq_max_l2_entries;
4248 if (ctx->srq_entry_size) {
4249 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4250 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4255 ctx_pg = &ctx->cq_mem;
4256 ctx_pg->entries = ctx->cq_max_l2_entries;
4257 if (ctx->cq_entry_size) {
4258 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4259 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4264 ctx_pg = &ctx->vnic_mem;
4265 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4266 ctx->vnic_max_ring_table_entries;
4267 if (ctx->vnic_entry_size) {
4268 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4269 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4274 ctx_pg = &ctx->stat_mem;
4275 ctx_pg->entries = ctx->stat_max_entries;
4276 if (ctx->stat_entry_size) {
4277 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4278 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4283 min = ctx->tqm_min_entries_per_ring;
4285 entries_sp = ctx->qp_max_l2_entries +
4286 ctx->vnic_max_vnic_entries +
4287 2 * ctx->qp_min_qp1_entries + min;
4288 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4290 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4291 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4292 entries = clamp_t(uint32_t, entries, min,
4293 ctx->tqm_max_entries_per_ring);
4294 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4295 ctx_pg = ctx->tqm_mem[i];
4296 ctx_pg->entries = i ? entries : entries_sp;
4297 if (ctx->tqm_entry_size) {
4298 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4299 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4303 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4306 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4307 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4310 "Failed to configure context mem: rc = %d\n", rc);
4312 ctx->flags |= BNXT_CTX_FLAG_INITED;
4317 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4319 struct rte_pci_device *pci_dev = bp->pdev;
4320 char mz_name[RTE_MEMZONE_NAMESIZE];
4321 const struct rte_memzone *mz = NULL;
4322 uint32_t total_alloc_len;
4323 rte_iova_t mz_phys_addr;
4325 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4328 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4329 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4330 pci_dev->addr.bus, pci_dev->addr.devid,
4331 pci_dev->addr.function, "rx_port_stats");
4332 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4333 mz = rte_memzone_lookup(mz_name);
4335 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4336 sizeof(struct rx_port_stats_ext) + 512);
4338 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4341 RTE_MEMZONE_SIZE_HINT_ONLY |
4342 RTE_MEMZONE_IOVA_CONTIG);
4346 memset(mz->addr, 0, mz->len);
4347 mz_phys_addr = mz->iova;
4349 bp->rx_mem_zone = (const void *)mz;
4350 bp->hw_rx_port_stats = mz->addr;
4351 bp->hw_rx_port_stats_map = mz_phys_addr;
4353 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4354 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4355 pci_dev->addr.bus, pci_dev->addr.devid,
4356 pci_dev->addr.function, "tx_port_stats");
4357 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4358 mz = rte_memzone_lookup(mz_name);
4360 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4361 sizeof(struct tx_port_stats_ext) + 512);
4363 mz = rte_memzone_reserve(mz_name,
4367 RTE_MEMZONE_SIZE_HINT_ONLY |
4368 RTE_MEMZONE_IOVA_CONTIG);
4372 memset(mz->addr, 0, mz->len);
4373 mz_phys_addr = mz->iova;
4375 bp->tx_mem_zone = (const void *)mz;
4376 bp->hw_tx_port_stats = mz->addr;
4377 bp->hw_tx_port_stats_map = mz_phys_addr;
4378 bp->flags |= BNXT_FLAG_PORT_STATS;
4380 /* Display extended statistics if FW supports it */
4381 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4382 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4383 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4386 bp->hw_rx_port_stats_ext = (void *)
4387 ((uint8_t *)bp->hw_rx_port_stats +
4388 sizeof(struct rx_port_stats));
4389 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4390 sizeof(struct rx_port_stats);
4391 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4393 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4394 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4395 bp->hw_tx_port_stats_ext = (void *)
4396 ((uint8_t *)bp->hw_tx_port_stats +
4397 sizeof(struct tx_port_stats));
4398 bp->hw_tx_port_stats_ext_map =
4399 bp->hw_tx_port_stats_map +
4400 sizeof(struct tx_port_stats);
4401 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4407 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4409 struct bnxt *bp = eth_dev->data->dev_private;
4412 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4413 RTE_ETHER_ADDR_LEN *
4416 if (eth_dev->data->mac_addrs == NULL) {
4417 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4421 if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4425 /* Generate a random MAC address, if none was assigned by PF */
4426 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4427 bnxt_eth_hw_addr_random(bp->mac_addr);
4429 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4430 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4431 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4433 rc = bnxt_hwrm_set_mac(bp);
4438 /* Copy the permanent MAC from the FUNC_QCAPS response */
4439 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4444 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4448 /* MAC is already configured in FW */
4449 if (BNXT_HAS_DFLT_MAC_SET(bp))
4452 /* Restore the old MAC configured */
4453 rc = bnxt_hwrm_set_mac(bp);
4455 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4460 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4465 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
4467 if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
4468 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
4469 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
4470 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
4471 BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
4472 BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
4476 bnxt_get_svif(uint16_t port_id, bool func_svif,
4477 enum bnxt_ulp_intf_type type)
4479 struct rte_eth_dev *eth_dev;
4482 eth_dev = &rte_eth_devices[port_id];
4483 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4484 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4488 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4491 eth_dev = vfr->parent_dev;
4494 bp = eth_dev->data->dev_private;
4496 return func_svif ? bp->func_svif : bp->port_svif;
4500 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
4502 struct rte_eth_dev *eth_dev;
4503 struct bnxt_vnic_info *vnic;
4506 eth_dev = &rte_eth_devices[port];
4507 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4508 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4512 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4513 return vfr->dflt_vnic_id;
4515 eth_dev = vfr->parent_dev;
4518 bp = eth_dev->data->dev_private;
4520 vnic = BNXT_GET_DEFAULT_VNIC(bp);
4522 return vnic->fw_vnic_id;
4526 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
4528 struct rte_eth_dev *eth_dev;
4531 eth_dev = &rte_eth_devices[port];
4532 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4533 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4537 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4540 eth_dev = vfr->parent_dev;
4543 bp = eth_dev->data->dev_private;
4548 enum bnxt_ulp_intf_type
4549 bnxt_get_interface_type(uint16_t port)
4551 struct rte_eth_dev *eth_dev;
4554 eth_dev = &rte_eth_devices[port];
4555 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
4556 return BNXT_ULP_INTF_TYPE_VF_REP;
4558 bp = eth_dev->data->dev_private;
4560 return BNXT_ULP_INTF_TYPE_PF;
4561 else if (BNXT_VF_IS_TRUSTED(bp))
4562 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
4563 else if (BNXT_VF(bp))
4564 return BNXT_ULP_INTF_TYPE_VF;
4566 return BNXT_ULP_INTF_TYPE_INVALID;
4570 bnxt_get_phy_port_id(uint16_t port_id)
4572 struct bnxt_representor *vfr;
4573 struct rte_eth_dev *eth_dev;
4576 eth_dev = &rte_eth_devices[port_id];
4577 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4578 vfr = eth_dev->data->dev_private;
4582 eth_dev = vfr->parent_dev;
4585 bp = eth_dev->data->dev_private;
4587 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
4591 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
4593 struct rte_eth_dev *eth_dev;
4596 eth_dev = &rte_eth_devices[port_id];
4597 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4598 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4602 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4603 return vfr->fw_fid - 1;
4605 eth_dev = vfr->parent_dev;
4608 bp = eth_dev->data->dev_private;
4610 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
4614 bnxt_get_vport(uint16_t port_id)
4616 return (1 << bnxt_get_phy_port_id(port_id));
4619 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
4621 struct bnxt_error_recovery_info *info = bp->recovery_info;
4624 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
4625 memset(info, 0, sizeof(*info));
4629 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4632 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4635 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4637 bp->recovery_info = info;
4640 static void bnxt_check_fw_status(struct bnxt *bp)
4644 if (!(bp->recovery_info &&
4645 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
4648 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
4649 if (fw_status != BNXT_FW_STATUS_HEALTHY)
4650 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
4654 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
4656 struct bnxt_error_recovery_info *info = bp->recovery_info;
4657 uint32_t status_loc;
4660 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
4661 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4662 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4663 BNXT_GRCP_WINDOW_2_BASE +
4664 offsetof(struct hcomm_status,
4666 /* If the signature is absent, then FW does not support this feature */
4667 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
4668 HCOMM_STATUS_SIGNATURE_VAL)
4672 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4676 bp->recovery_info = info;
4678 memset(info, 0, sizeof(*info));
4681 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4682 BNXT_GRCP_WINDOW_2_BASE +
4683 offsetof(struct hcomm_status,
4686 /* Only pre-map the FW health status GRC register */
4687 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
4690 info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
4691 info->mapped_status_regs[BNXT_FW_STATUS_REG] =
4692 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
4694 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
4695 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4697 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
4702 static int bnxt_init_fw(struct bnxt *bp)
4709 rc = bnxt_map_hcomm_fw_status_reg(bp);
4713 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
4715 bnxt_check_fw_status(bp);
4719 rc = bnxt_hwrm_func_reset(bp);
4723 rc = bnxt_hwrm_vnic_qcaps(bp);
4727 rc = bnxt_hwrm_queue_qportcfg(bp);
4731 /* Get the MAX capabilities for this function.
4732 * This function also allocates context memory for TQM rings and
4733 * informs the firmware about this allocated backing store memory.
4735 rc = bnxt_hwrm_func_qcaps(bp);
4739 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4743 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4747 bnxt_hwrm_port_mac_qcfg(bp);
4749 bnxt_hwrm_parent_pf_qcfg(bp);
4751 bnxt_hwrm_port_phy_qcaps(bp);
4753 bnxt_alloc_error_recovery_info(bp);
4754 /* Get the adapter error recovery support info */
4755 rc = bnxt_hwrm_error_recovery_qcfg(bp);
4757 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4759 bnxt_hwrm_port_led_qcaps(bp);
4765 bnxt_init_locks(struct bnxt *bp)
4769 err = pthread_mutex_init(&bp->flow_lock, NULL);
4771 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4775 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4777 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4781 err = pthread_mutex_init(&bp->health_check_lock, NULL);
4783 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
4787 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4791 rc = bnxt_init_fw(bp);
4795 if (!reconfig_dev) {
4796 rc = bnxt_setup_mac_addr(bp->eth_dev);
4800 rc = bnxt_restore_dflt_mac(bp);
4805 bnxt_config_vf_req_fwd(bp);
4807 rc = bnxt_hwrm_func_driver_register(bp);
4809 PMD_DRV_LOG(ERR, "Failed to register driver");
4814 if (bp->pdev->max_vfs) {
4815 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4817 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4821 rc = bnxt_hwrm_allocate_pf_only(bp);
4824 "Failed to allocate PF resources");
4830 rc = bnxt_alloc_mem(bp, reconfig_dev);
4834 rc = bnxt_setup_int(bp);
4838 rc = bnxt_request_int(bp);
4842 rc = bnxt_init_ctx_mem(bp);
4844 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
4852 bnxt_parse_devarg_truflow(__rte_unused const char *key,
4853 const char *value, void *opaque_arg)
4855 struct bnxt *bp = opaque_arg;
4856 unsigned long truflow;
4859 if (!value || !opaque_arg) {
4861 "Invalid parameter passed to truflow devargs.\n");
4865 truflow = strtoul(value, &end, 10);
4866 if (end == NULL || *end != '\0' ||
4867 (truflow == ULONG_MAX && errno == ERANGE)) {
4869 "Invalid parameter passed to truflow devargs.\n");
4873 if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
4875 "Invalid value passed to truflow devargs.\n");
4880 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
4881 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
4883 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
4884 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
4891 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
4892 const char *value, void *opaque_arg)
4894 struct bnxt *bp = opaque_arg;
4895 unsigned long flow_xstat;
4898 if (!value || !opaque_arg) {
4900 "Invalid parameter passed to flow_xstat devarg.\n");
4904 flow_xstat = strtoul(value, &end, 10);
4905 if (end == NULL || *end != '\0' ||
4906 (flow_xstat == ULONG_MAX && errno == ERANGE)) {
4908 "Invalid parameter passed to flow_xstat devarg.\n");
4912 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
4914 "Invalid value passed to flow_xstat devarg.\n");
4918 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
4919 if (BNXT_FLOW_XSTATS_EN(bp))
4920 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
4926 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
4927 const char *value, void *opaque_arg)
4929 struct bnxt *bp = opaque_arg;
4930 unsigned long max_num_kflows;
4933 if (!value || !opaque_arg) {
4935 "Invalid parameter passed to max_num_kflows devarg.\n");
4939 max_num_kflows = strtoul(value, &end, 10);
4940 if (end == NULL || *end != '\0' ||
4941 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
4943 "Invalid parameter passed to max_num_kflows devarg.\n");
4947 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
4949 "Invalid value passed to max_num_kflows devarg.\n");
4953 bp->max_num_kflows = max_num_kflows;
4954 if (bp->max_num_kflows)
4955 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
4962 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
4963 const char *value, void *opaque_arg)
4965 struct bnxt_representor *vfr_bp = opaque_arg;
4966 unsigned long rep_is_pf;
4969 if (!value || !opaque_arg) {
4971 "Invalid parameter passed to rep_is_pf devargs.\n");
4975 rep_is_pf = strtoul(value, &end, 10);
4976 if (end == NULL || *end != '\0' ||
4977 (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
4979 "Invalid parameter passed to rep_is_pf devargs.\n");
4983 if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
4985 "Invalid value passed to rep_is_pf devargs.\n");
4989 vfr_bp->flags |= rep_is_pf;
4990 if (BNXT_REP_PF(vfr_bp))
4991 PMD_DRV_LOG(INFO, "PF representor\n");
4993 PMD_DRV_LOG(INFO, "VF representor\n");
4999 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5000 const char *value, void *opaque_arg)
5002 struct bnxt_representor *vfr_bp = opaque_arg;
5003 unsigned long rep_based_pf;
5006 if (!value || !opaque_arg) {
5008 "Invalid parameter passed to rep_based_pf "
5013 rep_based_pf = strtoul(value, &end, 10);
5014 if (end == NULL || *end != '\0' ||
5015 (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5017 "Invalid parameter passed to rep_based_pf "
5022 if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5024 "Invalid value passed to rep_based_pf devargs.\n");
5028 vfr_bp->rep_based_pf = rep_based_pf;
5029 vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
5031 PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5037 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5038 const char *value, void *opaque_arg)
5040 struct bnxt_representor *vfr_bp = opaque_arg;
5041 unsigned long rep_q_r2f;
5044 if (!value || !opaque_arg) {
5046 "Invalid parameter passed to rep_q_r2f "
5051 rep_q_r2f = strtoul(value, &end, 10);
5052 if (end == NULL || *end != '\0' ||
5053 (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5055 "Invalid parameter passed to rep_q_r2f "
5060 if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5062 "Invalid value passed to rep_q_r2f devargs.\n");
5066 vfr_bp->rep_q_r2f = rep_q_r2f;
5067 vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5068 PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5074 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5075 const char *value, void *opaque_arg)
5077 struct bnxt_representor *vfr_bp = opaque_arg;
5078 unsigned long rep_q_f2r;
5081 if (!value || !opaque_arg) {
5083 "Invalid parameter passed to rep_q_f2r "
5088 rep_q_f2r = strtoul(value, &end, 10);
5089 if (end == NULL || *end != '\0' ||
5090 (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5092 "Invalid parameter passed to rep_q_f2r "
5097 if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5099 "Invalid value passed to rep_q_f2r devargs.\n");
5103 vfr_bp->rep_q_f2r = rep_q_f2r;
5104 vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5105 PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5111 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5112 const char *value, void *opaque_arg)
5114 struct bnxt_representor *vfr_bp = opaque_arg;
5115 unsigned long rep_fc_r2f;
5118 if (!value || !opaque_arg) {
5120 "Invalid parameter passed to rep_fc_r2f "
5125 rep_fc_r2f = strtoul(value, &end, 10);
5126 if (end == NULL || *end != '\0' ||
5127 (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5129 "Invalid parameter passed to rep_fc_r2f "
5134 if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5136 "Invalid value passed to rep_fc_r2f devargs.\n");
5140 vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5141 vfr_bp->rep_fc_r2f = rep_fc_r2f;
5142 PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5148 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5149 const char *value, void *opaque_arg)
5151 struct bnxt_representor *vfr_bp = opaque_arg;
5152 unsigned long rep_fc_f2r;
5155 if (!value || !opaque_arg) {
5157 "Invalid parameter passed to rep_fc_f2r "
5162 rep_fc_f2r = strtoul(value, &end, 10);
5163 if (end == NULL || *end != '\0' ||
5164 (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5166 "Invalid parameter passed to rep_fc_f2r "
5171 if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5173 "Invalid value passed to rep_fc_f2r devargs.\n");
5177 vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5178 vfr_bp->rep_fc_f2r = rep_fc_f2r;
5179 PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5185 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5187 struct rte_kvargs *kvlist;
5189 if (devargs == NULL)
5192 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5197 * Handler for "truflow" devarg.
5198 * Invoked as for ex: "-a 0000:00:0d.0,host-based-truflow=1"
5200 rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5201 bnxt_parse_devarg_truflow, bp);
5204 * Handler for "flow_xstat" devarg.
5205 * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5207 rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5208 bnxt_parse_devarg_flow_xstat, bp);
5211 * Handler for "max_num_kflows" devarg.
5212 * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5214 rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5215 bnxt_parse_devarg_max_num_kflows, bp);
5217 rte_kvargs_free(kvlist);
5220 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5224 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5225 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5228 "Failed to alloc switch domain: %d\n", rc);
5231 "Switch domain allocated %d\n",
5232 bp->switch_domain_id);
5239 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5241 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5242 static int version_printed;
5246 if (version_printed++ == 0)
5247 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5249 eth_dev->dev_ops = &bnxt_dev_ops;
5250 eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5251 eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5252 eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5253 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5254 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5257 * For secondary processes, we don't initialise any further
5258 * as primary has already done this work.
5260 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5263 rte_eth_copy_pci_info(eth_dev, pci_dev);
5264 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
5266 bp = eth_dev->data->dev_private;
5268 /* Parse dev arguments passed on when starting the DPDK application. */
5269 bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5271 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5273 if (bnxt_vf_pciid(pci_dev->id.device_id))
5274 bp->flags |= BNXT_FLAG_VF;
5276 if (bnxt_p5_device(pci_dev->id.device_id))
5277 bp->flags |= BNXT_FLAG_CHIP_P5;
5279 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5280 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5281 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5282 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5283 bp->flags |= BNXT_FLAG_STINGRAY;
5285 if (BNXT_TRUFLOW_EN(bp)) {
5286 /* extra mbuf field is required to store CFA code from mark */
5287 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5288 .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5289 .size = sizeof(bnxt_cfa_code_dynfield_t),
5290 .align = __alignof__(bnxt_cfa_code_dynfield_t),
5292 bnxt_cfa_code_dynfield_offset =
5293 rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5294 if (bnxt_cfa_code_dynfield_offset < 0) {
5296 "Failed to register mbuf field for TruFlow mark\n");
5301 rc = bnxt_init_board(eth_dev);
5304 "Failed to initialize board rc: %x\n", rc);
5308 rc = bnxt_alloc_pf_info(bp);
5312 rc = bnxt_alloc_link_info(bp);
5316 rc = bnxt_alloc_parent_info(bp);
5320 rc = bnxt_alloc_hwrm_resources(bp);
5323 "Failed to allocate hwrm resource rc: %x\n", rc);
5326 rc = bnxt_alloc_leds_info(bp);
5330 rc = bnxt_alloc_cos_queues(bp);
5334 rc = bnxt_init_locks(bp);
5338 rc = bnxt_init_resources(bp, false);
5342 rc = bnxt_alloc_stats_mem(bp);
5346 bnxt_alloc_switch_domain(bp);
5349 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5350 pci_dev->mem_resource[0].phys_addr,
5351 pci_dev->mem_resource[0].addr);
5356 bnxt_dev_uninit(eth_dev);
5361 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5370 ctx->dma = RTE_BAD_IOVA;
5371 ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5374 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5376 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5377 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5378 bp->flow_stat->rx_fc_out_tbl.ctx_id,
5379 bp->flow_stat->max_fc,
5382 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5383 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5384 bp->flow_stat->tx_fc_out_tbl.ctx_id,
5385 bp->flow_stat->max_fc,
5388 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5389 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5390 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5392 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5393 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5394 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5396 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5397 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5398 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5400 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5401 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5402 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5405 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5407 bnxt_unregister_fc_ctx_mem(bp);
5409 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5410 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5411 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5412 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5415 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5417 if (BNXT_FLOW_XSTATS_EN(bp))
5418 bnxt_uninit_fc_ctx_mem(bp);
5422 bnxt_free_error_recovery_info(struct bnxt *bp)
5424 rte_free(bp->recovery_info);
5425 bp->recovery_info = NULL;
5426 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5430 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5435 bnxt_free_mem(bp, reconfig_dev);
5437 bnxt_hwrm_func_buf_unrgtr(bp);
5438 rte_free(bp->pf->vf_req_buf);
5440 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5441 bp->flags &= ~BNXT_FLAG_REGISTERED;
5442 bnxt_free_ctx_mem(bp);
5443 if (!reconfig_dev) {
5444 bnxt_free_hwrm_resources(bp);
5445 bnxt_free_error_recovery_info(bp);
5448 bnxt_uninit_ctx_mem(bp);
5450 bnxt_free_flow_stats_info(bp);
5451 bnxt_free_rep_info(bp);
5452 rte_free(bp->ptp_cfg);
5458 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5460 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5463 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5465 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5466 bnxt_dev_close_op(eth_dev);
5471 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5473 struct bnxt *bp = eth_dev->data->dev_private;
5474 struct rte_eth_dev *vf_rep_eth_dev;
5480 for (i = 0; i < bp->num_reps; i++) {
5481 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5482 if (!vf_rep_eth_dev)
5484 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
5485 vf_rep_eth_dev->data->port_id);
5486 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
5488 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
5489 eth_dev->data->port_id);
5490 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5495 static void bnxt_free_rep_info(struct bnxt *bp)
5497 rte_free(bp->rep_info);
5498 bp->rep_info = NULL;
5499 rte_free(bp->cfa_code_map);
5500 bp->cfa_code_map = NULL;
5503 static int bnxt_init_rep_info(struct bnxt *bp)
5510 bp->rep_info = rte_zmalloc("bnxt_rep_info",
5511 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5513 if (!bp->rep_info) {
5514 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5517 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5518 sizeof(*bp->cfa_code_map) *
5519 BNXT_MAX_CFA_CODE, 0);
5520 if (!bp->cfa_code_map) {
5521 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5522 bnxt_free_rep_info(bp);
5526 for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5527 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5529 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5531 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5532 bnxt_free_rep_info(bp);
5536 rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
5538 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
5539 bnxt_free_rep_info(bp);
5546 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5547 struct rte_eth_devargs *eth_da,
5548 struct rte_eth_dev *backing_eth_dev,
5549 const char *dev_args)
5551 struct rte_eth_dev *vf_rep_eth_dev;
5552 char name[RTE_ETH_NAME_MAX_LEN];
5553 struct bnxt *backing_bp;
5556 struct rte_kvargs *kvlist = NULL;
5558 num_rep = eth_da->nb_representor_ports;
5559 if (num_rep > BNXT_MAX_VF_REPS) {
5560 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5561 num_rep, BNXT_MAX_VF_REPS);
5565 if (num_rep >= RTE_MAX_ETHPORTS) {
5567 "nb_representor_ports = %d > %d MAX ETHPORTS\n",
5568 num_rep, RTE_MAX_ETHPORTS);
5572 backing_bp = backing_eth_dev->data->dev_private;
5574 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
5576 "Not a PF or trusted VF. No Representor support\n");
5577 /* Returning an error is not an option.
5578 * Applications are not handling this correctly
5583 if (bnxt_init_rep_info(backing_bp))
5586 for (i = 0; i < num_rep; i++) {
5587 struct bnxt_representor representor = {
5588 .vf_id = eth_da->representor_ports[i],
5589 .switch_domain_id = backing_bp->switch_domain_id,
5590 .parent_dev = backing_eth_dev
5593 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
5594 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
5595 representor.vf_id, BNXT_MAX_VF_REPS);
5599 /* representor port net_bdf_port */
5600 snprintf(name, sizeof(name), "net_%s_representor_%d",
5601 pci_dev->device.name, eth_da->representor_ports[i]);
5603 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
5606 * Handler for "rep_is_pf" devarg.
5607 * Invoked as for ex: "-a 000:00:0d.0,
5608 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5610 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
5611 bnxt_parse_devarg_rep_is_pf,
5612 (void *)&representor);
5618 * Handler for "rep_based_pf" devarg.
5619 * Invoked as for ex: "-a 000:00:0d.0,
5620 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5622 ret = rte_kvargs_process(kvlist,
5623 BNXT_DEVARG_REP_BASED_PF,
5624 bnxt_parse_devarg_rep_based_pf,
5625 (void *)&representor);
5631 * Handler for "rep_based_pf" devarg.
5632 * Invoked as for ex: "-a 000:00:0d.0,
5633 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5635 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
5636 bnxt_parse_devarg_rep_q_r2f,
5637 (void *)&representor);
5643 * Handler for "rep_based_pf" devarg.
5644 * Invoked as for ex: "-a 000:00:0d.0,
5645 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5647 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
5648 bnxt_parse_devarg_rep_q_f2r,
5649 (void *)&representor);
5655 * Handler for "rep_based_pf" devarg.
5656 * Invoked as for ex: "-a 000:00:0d.0,
5657 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5659 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
5660 bnxt_parse_devarg_rep_fc_r2f,
5661 (void *)&representor);
5667 * Handler for "rep_based_pf" devarg.
5668 * Invoked as for ex: "-a 000:00:0d.0,
5669 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5671 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
5672 bnxt_parse_devarg_rep_fc_f2r,
5673 (void *)&representor);
5680 ret = rte_eth_dev_create(&pci_dev->device, name,
5681 sizeof(struct bnxt_representor),
5683 bnxt_representor_init,
5686 PMD_DRV_LOG(ERR, "failed to create bnxt vf "
5687 "representor %s.", name);
5691 vf_rep_eth_dev = rte_eth_dev_allocated(name);
5692 if (!vf_rep_eth_dev) {
5693 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
5694 " for VF-Rep: %s.", name);
5699 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
5700 backing_eth_dev->data->port_id);
5701 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
5703 backing_bp->num_reps++;
5707 rte_kvargs_free(kvlist);
5711 /* If num_rep > 1, then rollback already created
5712 * ports, since we'll be failing the probe anyway
5715 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
5717 rte_kvargs_free(kvlist);
5722 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5723 struct rte_pci_device *pci_dev)
5725 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
5726 struct rte_eth_dev *backing_eth_dev;
5730 if (pci_dev->device.devargs) {
5731 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
5737 num_rep = eth_da.nb_representor_ports;
5738 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
5741 /* We could come here after first level of probe is already invoked
5742 * as part of an application bringup(OVS-DPDK vswitchd), so first check
5743 * for already allocated eth_dev for the backing device (PF/Trusted VF)
5745 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5746 if (backing_eth_dev == NULL) {
5747 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
5748 sizeof(struct bnxt),
5749 eth_dev_pci_specific_init, pci_dev,
5750 bnxt_dev_init, NULL);
5752 if (ret || !num_rep)
5755 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5757 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
5758 backing_eth_dev->data->port_id);
5763 /* probe representor ports now */
5764 ret = bnxt_rep_port_probe(pci_dev, ð_da, backing_eth_dev,
5765 pci_dev->device.devargs->args);
5770 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5772 struct rte_eth_dev *eth_dev;
5774 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5776 return 0; /* Invoked typically only by OVS-DPDK, by the
5777 * time it comes here the eth_dev is already
5778 * deleted by rte_eth_dev_close(), so returning
5779 * +ve value will at least help in proper cleanup
5782 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
5783 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
5784 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
5785 return rte_eth_dev_destroy(eth_dev,
5786 bnxt_representor_uninit);
5788 return rte_eth_dev_destroy(eth_dev,
5791 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5795 static struct rte_pci_driver bnxt_rte_pmd = {
5796 .id_table = bnxt_pci_id_map,
5797 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
5798 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
5801 .probe = bnxt_pci_probe,
5802 .remove = bnxt_pci_remove,
5806 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5808 if (strcmp(dev->device->driver->name, drv->driver.name))
5814 bool is_bnxt_supported(struct rte_eth_dev *dev)
5816 return is_device_supported(dev, &bnxt_rte_pmd);
5819 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
5820 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5821 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5822 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");