1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
20 #include "bnxt_ring.h"
23 #include "bnxt_stats.h"
26 #include "bnxt_vnic.h"
27 #include "hsi_struct_def_dpdk.h"
28 #include "bnxt_nvm_defs.h"
29 #include "bnxt_util.h"
31 #define DRV_MODULE_NAME "bnxt"
32 static const char bnxt_version[] =
33 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
34 int bnxt_logtype_driver;
36 #define PCI_VENDOR_ID_BROADCOM 0x14E4
38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
40 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
41 #define BROADCOM_DEV_ID_57414_VF 0x16c1
42 #define BROADCOM_DEV_ID_57301 0x16c8
43 #define BROADCOM_DEV_ID_57302 0x16c9
44 #define BROADCOM_DEV_ID_57304_PF 0x16ca
45 #define BROADCOM_DEV_ID_57304_VF 0x16cb
46 #define BROADCOM_DEV_ID_57417_MF 0x16cc
47 #define BROADCOM_DEV_ID_NS2 0x16cd
48 #define BROADCOM_DEV_ID_57311 0x16ce
49 #define BROADCOM_DEV_ID_57312 0x16cf
50 #define BROADCOM_DEV_ID_57402 0x16d0
51 #define BROADCOM_DEV_ID_57404 0x16d1
52 #define BROADCOM_DEV_ID_57406_PF 0x16d2
53 #define BROADCOM_DEV_ID_57406_VF 0x16d3
54 #define BROADCOM_DEV_ID_57402_MF 0x16d4
55 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
56 #define BROADCOM_DEV_ID_57412 0x16d6
57 #define BROADCOM_DEV_ID_57414 0x16d7
58 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
59 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
60 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
61 #define BROADCOM_DEV_ID_57412_MF 0x16de
62 #define BROADCOM_DEV_ID_57314 0x16df
63 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
64 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
65 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
66 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
67 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
68 #define BROADCOM_DEV_ID_57404_MF 0x16e7
69 #define BROADCOM_DEV_ID_57406_MF 0x16e8
70 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
71 #define BROADCOM_DEV_ID_57407_MF 0x16ea
72 #define BROADCOM_DEV_ID_57414_MF 0x16ec
73 #define BROADCOM_DEV_ID_57416_MF 0x16ee
74 #define BROADCOM_DEV_ID_57508 0x1750
75 #define BROADCOM_DEV_ID_57504 0x1751
76 #define BROADCOM_DEV_ID_57502 0x1752
77 #define BROADCOM_DEV_ID_57500_VF 0x1807
78 #define BROADCOM_DEV_ID_58802 0xd802
79 #define BROADCOM_DEV_ID_58804 0xd804
80 #define BROADCOM_DEV_ID_58808 0x16f0
81 #define BROADCOM_DEV_ID_58802_VF 0xd800
83 static const struct rte_pci_id bnxt_pci_id_map[] = {
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
85 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
87 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
98 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
122 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
123 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
124 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
125 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
126 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
127 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
128 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
129 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF) },
130 { .vendor_id = 0, /* sentinel */ },
133 #define BNXT_ETH_RSS_SUPPORT ( \
135 ETH_RSS_NONFRAG_IPV4_TCP | \
136 ETH_RSS_NONFRAG_IPV4_UDP | \
138 ETH_RSS_NONFRAG_IPV6_TCP | \
139 ETH_RSS_NONFRAG_IPV6_UDP)
141 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
142 DEV_TX_OFFLOAD_IPV4_CKSUM | \
143 DEV_TX_OFFLOAD_TCP_CKSUM | \
144 DEV_TX_OFFLOAD_UDP_CKSUM | \
145 DEV_TX_OFFLOAD_TCP_TSO | \
146 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
147 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
148 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
149 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
150 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
151 DEV_TX_OFFLOAD_MULTI_SEGS)
153 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
154 DEV_RX_OFFLOAD_VLAN_STRIP | \
155 DEV_RX_OFFLOAD_IPV4_CKSUM | \
156 DEV_RX_OFFLOAD_UDP_CKSUM | \
157 DEV_RX_OFFLOAD_TCP_CKSUM | \
158 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
159 DEV_RX_OFFLOAD_JUMBO_FRAME | \
160 DEV_RX_OFFLOAD_KEEP_CRC | \
161 DEV_RX_OFFLOAD_TCP_LRO)
163 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
164 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
165 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
166 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
168 /***********************/
171 * High level utility functions
174 static void bnxt_free_mem(struct bnxt *bp)
176 bnxt_free_filter_mem(bp);
177 bnxt_free_vnic_attributes(bp);
178 bnxt_free_vnic_mem(bp);
181 bnxt_free_tx_rings(bp);
182 bnxt_free_rx_rings(bp);
185 static int bnxt_alloc_mem(struct bnxt *bp)
189 rc = bnxt_alloc_vnic_mem(bp);
193 rc = bnxt_alloc_vnic_attributes(bp);
197 rc = bnxt_alloc_filter_mem(bp);
208 static int bnxt_init_chip(struct bnxt *bp)
210 struct bnxt_rx_queue *rxq;
211 struct rte_eth_link new;
212 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
213 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
214 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
215 uint64_t rx_offloads = dev_conf->rxmode.offloads;
216 uint32_t intr_vector = 0;
217 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
218 uint32_t vec = BNXT_MISC_VEC_ID;
222 /* disable uio/vfio intr/eventfd mapping */
223 rte_intr_disable(intr_handle);
225 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
226 bp->eth_dev->data->dev_conf.rxmode.offloads |=
227 DEV_RX_OFFLOAD_JUMBO_FRAME;
228 bp->flags |= BNXT_FLAG_JUMBO;
230 bp->eth_dev->data->dev_conf.rxmode.offloads &=
231 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
232 bp->flags &= ~BNXT_FLAG_JUMBO;
235 /* THOR does not support ring groups.
236 * But we will use the array to save RSS context IDs.
238 if (BNXT_CHIP_THOR(bp))
239 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
241 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
243 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
247 rc = bnxt_alloc_hwrm_rings(bp);
249 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
253 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
255 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
259 rc = bnxt_mq_rx_configure(bp);
261 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
265 /* VNIC configuration */
266 for (i = 0; i < bp->nr_vnics; i++) {
267 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
268 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
269 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
271 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
272 if (!vnic->fw_grp_ids) {
274 "Failed to alloc %d bytes for group ids\n",
279 memset(vnic->fw_grp_ids, -1, size);
281 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
282 i, vnic, vnic->fw_grp_ids);
284 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
286 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
291 /* Alloc RSS context only if RSS mode is enabled */
292 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
293 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
296 "HWRM vnic %d ctx alloc failure rc: %x\n",
303 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
304 * setting is not available at this time, it will not be
305 * configured correctly in the CFA.
307 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
308 vnic->vlan_strip = true;
310 vnic->vlan_strip = false;
312 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
314 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
319 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
322 "HWRM vnic %d filter failure rc: %x\n",
327 for (j = 0; j < bp->rx_nr_rings; j++) {
328 rxq = bp->eth_dev->data->rx_queues[j];
331 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
332 j, rxq->vnic, rxq->vnic->fw_grp_ids);
334 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
335 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
338 rc = bnxt_vnic_rss_configure(bp, vnic);
341 "HWRM vnic set RSS failure rc: %x\n", rc);
345 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
347 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
348 DEV_RX_OFFLOAD_TCP_LRO)
349 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
351 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
353 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
356 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
360 /* check and configure queue intr-vector mapping */
361 if ((rte_intr_cap_multiple(intr_handle) ||
362 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
363 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
364 intr_vector = bp->eth_dev->data->nb_rx_queues;
365 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
366 if (intr_vector > bp->rx_cp_nr_rings) {
367 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
371 if (rte_intr_efd_enable(intr_handle, intr_vector))
375 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
376 intr_handle->intr_vec =
377 rte_zmalloc("intr_vec",
378 bp->eth_dev->data->nb_rx_queues *
380 if (intr_handle->intr_vec == NULL) {
381 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
382 " intr_vec", bp->eth_dev->data->nb_rx_queues);
385 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
386 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
387 intr_handle->intr_vec, intr_handle->nb_efd,
388 intr_handle->max_intr);
391 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
393 intr_handle->intr_vec[queue_id] = vec;
394 if (vec < base + intr_handle->nb_efd - 1)
398 /* enable uio/vfio intr/eventfd mapping */
399 rte_intr_enable(intr_handle);
401 rc = bnxt_get_hwrm_link_config(bp, &new);
403 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
407 if (!bp->link_info.link_up) {
408 rc = bnxt_set_hwrm_link_config(bp, true);
411 "HWRM link config failure rc: %x\n", rc);
415 bnxt_print_link_info(bp->eth_dev);
420 bnxt_free_all_hwrm_resources(bp);
422 /* Some of the error status returned by FW may not be from errno.h */
429 static int bnxt_shutdown_nic(struct bnxt *bp)
431 bnxt_free_all_hwrm_resources(bp);
432 bnxt_free_all_filters(bp);
433 bnxt_free_all_vnics(bp);
437 static int bnxt_init_nic(struct bnxt *bp)
441 rc = bnxt_init_ring_grps(bp);
446 bnxt_init_filters(bp);
452 * Device configuration and status function
455 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
456 struct rte_eth_dev_info *dev_info)
458 struct bnxt *bp = eth_dev->data->dev_private;
459 uint16_t max_vnics, i, j, vpool, vrxq;
460 unsigned int max_rx_rings;
463 dev_info->max_mac_addrs = bp->max_l2_ctx;
464 dev_info->max_hash_mac_addrs = 0;
466 /* PF/VF specifics */
468 dev_info->max_vfs = bp->pdev->max_vfs;
469 max_rx_rings = RTE_MIN(bp->max_vnics, bp->max_stat_ctx);
470 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
471 dev_info->max_rx_queues = max_rx_rings;
472 dev_info->max_tx_queues = max_rx_rings;
473 dev_info->reta_size = HW_HASH_INDEX_SIZE;
474 dev_info->hash_key_size = 40;
475 max_vnics = bp->max_vnics;
477 /* Fast path specifics */
478 dev_info->min_rx_bufsize = 1;
479 dev_info->max_rx_pktlen = BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +
480 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
482 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
483 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
484 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
485 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
486 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
489 dev_info->default_rxconf = (struct rte_eth_rxconf) {
495 .rx_free_thresh = 32,
496 /* If no descriptors available, pkts are dropped by default */
500 dev_info->default_txconf = (struct rte_eth_txconf) {
506 .tx_free_thresh = 32,
509 eth_dev->data->dev_conf.intr_conf.lsc = 1;
511 eth_dev->data->dev_conf.intr_conf.rxq = 1;
512 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
513 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
514 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
515 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
520 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
521 * need further investigation.
525 vpool = 64; /* ETH_64_POOLS */
526 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
527 for (i = 0; i < 4; vpool >>= 1, i++) {
528 if (max_vnics > vpool) {
529 for (j = 0; j < 5; vrxq >>= 1, j++) {
530 if (dev_info->max_rx_queues > vrxq) {
536 /* Not enough resources to support VMDq */
540 /* Not enough resources to support VMDq */
544 dev_info->max_vmdq_pools = vpool;
545 dev_info->vmdq_queue_num = vrxq;
547 dev_info->vmdq_pool_base = 0;
548 dev_info->vmdq_queue_base = 0;
551 /* Configure the device based on the configuration provided */
552 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
554 struct bnxt *bp = eth_dev->data->dev_private;
555 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
558 bp->rx_queues = (void *)eth_dev->data->rx_queues;
559 bp->tx_queues = (void *)eth_dev->data->tx_queues;
560 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
561 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
563 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
564 rc = bnxt_hwrm_check_vf_rings(bp);
566 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
570 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
572 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
576 /* legacy driver needs to get updated values */
577 rc = bnxt_hwrm_func_qcaps(bp);
579 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
584 /* Inherit new configurations */
585 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
586 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
587 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
589 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
593 if (BNXT_HAS_RING_GRPS(bp) &&
594 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
597 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
598 bp->max_vnics < eth_dev->data->nb_rx_queues)
601 bp->rx_cp_nr_rings = bp->rx_nr_rings;
602 bp->tx_cp_nr_rings = bp->tx_nr_rings;
604 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
606 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
607 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
609 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
615 "Insufficient resources to support requested config\n");
617 "Num Queues Requested: Tx %d, Rx %d\n",
618 eth_dev->data->nb_tx_queues,
619 eth_dev->data->nb_rx_queues);
621 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
622 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
623 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
627 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
629 struct rte_eth_link *link = ð_dev->data->dev_link;
631 if (link->link_status)
632 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
633 eth_dev->data->port_id,
634 (uint32_t)link->link_speed,
635 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
636 ("full-duplex") : ("half-duplex\n"));
638 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
639 eth_dev->data->port_id);
643 * Determine whether the current configuration requires support for scattered
644 * receive; return 1 if scattered receive is required and 0 if not.
646 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
651 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
652 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
654 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
655 RTE_PKTMBUF_HEADROOM);
656 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
662 static eth_rx_burst_t
663 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
667 * Vector mode receive can be enabled only if scatter rx is not
668 * in use and rx offloads are limited to VLAN stripping and
671 if (!eth_dev->data->scattered_rx &&
672 !(eth_dev->data->dev_conf.rxmode.offloads &
673 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
674 DEV_RX_OFFLOAD_KEEP_CRC |
675 DEV_RX_OFFLOAD_JUMBO_FRAME |
676 DEV_RX_OFFLOAD_IPV4_CKSUM |
677 DEV_RX_OFFLOAD_UDP_CKSUM |
678 DEV_RX_OFFLOAD_TCP_CKSUM |
679 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
680 DEV_RX_OFFLOAD_VLAN_FILTER))) {
681 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
682 eth_dev->data->port_id);
683 return bnxt_recv_pkts_vec;
685 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
686 eth_dev->data->port_id);
688 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
689 eth_dev->data->port_id,
690 eth_dev->data->scattered_rx,
691 eth_dev->data->dev_conf.rxmode.offloads);
693 return bnxt_recv_pkts;
696 static eth_tx_burst_t
697 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
701 * Vector mode receive can be enabled only if scatter tx is not
702 * in use and tx offloads other than VLAN insertion are not
705 if (!eth_dev->data->scattered_rx &&
706 !(eth_dev->data->dev_conf.txmode.offloads &
707 ~DEV_TX_OFFLOAD_VLAN_INSERT)) {
708 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
709 eth_dev->data->port_id);
710 return bnxt_xmit_pkts_vec;
712 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
713 eth_dev->data->port_id);
715 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
716 eth_dev->data->port_id,
717 eth_dev->data->scattered_rx,
718 eth_dev->data->dev_conf.txmode.offloads);
720 return bnxt_xmit_pkts;
723 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
725 struct bnxt *bp = eth_dev->data->dev_private;
726 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
730 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
732 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
733 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
737 rc = bnxt_init_chip(bp);
741 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
743 bnxt_link_update_op(eth_dev, 1);
745 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
746 vlan_mask |= ETH_VLAN_FILTER_MASK;
747 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
748 vlan_mask |= ETH_VLAN_STRIP_MASK;
749 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
753 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
754 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
755 bp->flags |= BNXT_FLAG_INIT_DONE;
759 bnxt_shutdown_nic(bp);
760 bnxt_free_tx_mbufs(bp);
761 bnxt_free_rx_mbufs(bp);
765 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
767 struct bnxt *bp = eth_dev->data->dev_private;
770 if (!bp->link_info.link_up)
771 rc = bnxt_set_hwrm_link_config(bp, true);
773 eth_dev->data->dev_link.link_status = 1;
775 bnxt_print_link_info(eth_dev);
779 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
781 struct bnxt *bp = eth_dev->data->dev_private;
783 eth_dev->data->dev_link.link_status = 0;
784 bnxt_set_hwrm_link_config(bp, false);
785 bp->link_info.link_up = 0;
790 /* Unload the driver, release resources */
791 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
793 struct bnxt *bp = eth_dev->data->dev_private;
795 bp->flags &= ~BNXT_FLAG_INIT_DONE;
796 if (bp->eth_dev->data->dev_started) {
797 /* TBD: STOP HW queues DMA */
798 eth_dev->data->dev_link.link_status = 0;
800 bnxt_set_hwrm_link_config(bp, false);
801 bnxt_hwrm_port_clr_stats(bp);
802 bnxt_free_tx_mbufs(bp);
803 bnxt_free_rx_mbufs(bp);
804 bnxt_shutdown_nic(bp);
808 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
810 struct bnxt *bp = eth_dev->data->dev_private;
812 if (bp->dev_stopped == 0)
813 bnxt_dev_stop_op(eth_dev);
815 if (eth_dev->data->mac_addrs != NULL) {
816 rte_free(eth_dev->data->mac_addrs);
817 eth_dev->data->mac_addrs = NULL;
819 if (bp->grp_info != NULL) {
820 rte_free(bp->grp_info);
824 bnxt_dev_uninit(eth_dev);
827 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
830 struct bnxt *bp = eth_dev->data->dev_private;
831 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
832 struct bnxt_vnic_info *vnic;
833 struct bnxt_filter_info *filter, *temp_filter;
837 * Loop through all VNICs from the specified filter flow pools to
838 * remove the corresponding MAC addr filter
840 for (i = 0; i < bp->nr_vnics; i++) {
841 if (!(pool_mask & (1ULL << i)))
844 vnic = &bp->vnic_info[i];
845 filter = STAILQ_FIRST(&vnic->filter);
847 temp_filter = STAILQ_NEXT(filter, next);
848 if (filter->mac_index == index) {
849 STAILQ_REMOVE(&vnic->filter, filter,
850 bnxt_filter_info, next);
851 bnxt_hwrm_clear_l2_filter(bp, filter);
852 filter->mac_index = INVALID_MAC_INDEX;
853 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
854 STAILQ_INSERT_TAIL(&bp->free_filter_list,
857 filter = temp_filter;
862 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
863 struct rte_ether_addr *mac_addr,
864 uint32_t index, uint32_t pool)
866 struct bnxt *bp = eth_dev->data->dev_private;
867 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
868 struct bnxt_filter_info *filter;
870 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
871 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
876 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
879 /* Attach requested MAC address to the new l2_filter */
880 STAILQ_FOREACH(filter, &vnic->filter, next) {
881 if (filter->mac_index == index) {
883 "MAC addr already existed for pool %d\n", pool);
887 filter = bnxt_alloc_filter(bp);
889 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
892 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
893 filter->mac_index = index;
894 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
895 return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
898 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
901 struct bnxt *bp = eth_dev->data->dev_private;
902 struct rte_eth_link new;
903 unsigned int cnt = BNXT_LINK_WAIT_CNT;
905 memset(&new, 0, sizeof(new));
907 /* Retrieve link info from hardware */
908 rc = bnxt_get_hwrm_link_config(bp, &new);
910 new.link_speed = ETH_LINK_SPEED_100M;
911 new.link_duplex = ETH_LINK_FULL_DUPLEX;
913 "Failed to retrieve link rc = 0x%x!\n", rc);
916 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
918 if (!wait_to_complete)
920 } while (!new.link_status && cnt--);
923 /* Timed out or success */
924 if (new.link_status != eth_dev->data->dev_link.link_status ||
925 new.link_speed != eth_dev->data->dev_link.link_speed) {
926 memcpy(ð_dev->data->dev_link, &new,
927 sizeof(struct rte_eth_link));
929 _rte_eth_dev_callback_process(eth_dev,
930 RTE_ETH_EVENT_INTR_LSC,
933 bnxt_print_link_info(eth_dev);
939 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
941 struct bnxt *bp = eth_dev->data->dev_private;
942 struct bnxt_vnic_info *vnic;
944 if (bp->vnic_info == NULL)
947 vnic = &bp->vnic_info[0];
949 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
950 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
953 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
955 struct bnxt *bp = eth_dev->data->dev_private;
956 struct bnxt_vnic_info *vnic;
958 if (bp->vnic_info == NULL)
961 vnic = &bp->vnic_info[0];
963 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
964 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
967 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
969 struct bnxt *bp = eth_dev->data->dev_private;
970 struct bnxt_vnic_info *vnic;
972 if (bp->vnic_info == NULL)
975 vnic = &bp->vnic_info[0];
977 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
978 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
981 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
983 struct bnxt *bp = eth_dev->data->dev_private;
984 struct bnxt_vnic_info *vnic;
986 if (bp->vnic_info == NULL)
989 vnic = &bp->vnic_info[0];
991 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
992 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
995 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
996 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
998 if (qid >= bp->rx_nr_rings)
1001 return bp->eth_dev->data->rx_queues[qid];
1004 /* Return rxq corresponding to a given rss table ring/group ID. */
1005 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1009 for (i = 0; i < bp->rx_nr_rings; i++) {
1010 if (bp->grp_info[i].fw_grp_id == fwr)
1014 return INVALID_HW_RING_ID;
1017 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1018 struct rte_eth_rss_reta_entry64 *reta_conf,
1021 struct bnxt *bp = eth_dev->data->dev_private;
1022 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1023 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1024 uint16_t tbl_size = HW_HASH_INDEX_SIZE;
1028 if (!vnic->rss_table)
1031 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1034 if (reta_size != tbl_size) {
1035 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1036 "(%d) must equal the size supported by the hardware "
1037 "(%d)\n", reta_size, tbl_size);
1041 for (i = 0; i < reta_size; i++) {
1042 struct bnxt_rx_queue *rxq;
1044 idx = i / RTE_RETA_GROUP_SIZE;
1045 sft = i % RTE_RETA_GROUP_SIZE;
1047 if (!(reta_conf[idx].mask & (1ULL << sft)))
1050 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1052 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1056 vnic->rss_table[i] =
1057 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1060 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1064 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1065 struct rte_eth_rss_reta_entry64 *reta_conf,
1068 struct bnxt *bp = eth_dev->data->dev_private;
1069 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1070 uint16_t tbl_size = HW_HASH_INDEX_SIZE;
1071 uint16_t idx, sft, i;
1073 /* Retrieve from the default VNIC */
1076 if (!vnic->rss_table)
1079 if (reta_size != tbl_size) {
1080 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1081 "(%d) must equal the size supported by the hardware "
1082 "(%d)\n", reta_size, tbl_size);
1086 for (idx = 0, i = 0; i < reta_size; i++) {
1087 idx = i / RTE_RETA_GROUP_SIZE;
1088 sft = i % RTE_RETA_GROUP_SIZE;
1090 if (reta_conf[idx].mask & (1ULL << sft)) {
1093 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1095 if (qid == INVALID_HW_RING_ID) {
1096 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1099 reta_conf[idx].reta[sft] = qid;
1106 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1107 struct rte_eth_rss_conf *rss_conf)
1109 struct bnxt *bp = eth_dev->data->dev_private;
1110 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1111 struct bnxt_vnic_info *vnic;
1112 uint16_t hash_type = 0;
1116 * If RSS enablement were different than dev_configure,
1117 * then return -EINVAL
1119 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1120 if (!rss_conf->rss_hf)
1121 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1123 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1127 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1128 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1130 if (rss_conf->rss_hf & ETH_RSS_IPV4)
1131 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1132 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1133 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1134 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1135 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1136 if (rss_conf->rss_hf & ETH_RSS_IPV6)
1137 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1138 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1139 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1140 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1141 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1143 /* Update the RSS VNIC(s) */
1144 for (i = 0; i < bp->nr_vnics; i++) {
1145 vnic = &bp->vnic_info[i];
1146 vnic->hash_type = hash_type;
1149 * Use the supplied key if the key length is
1150 * acceptable and the rss_key is not NULL
1152 if (rss_conf->rss_key &&
1153 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1154 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
1155 rss_conf->rss_key_len);
1157 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1162 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1163 struct rte_eth_rss_conf *rss_conf)
1165 struct bnxt *bp = eth_dev->data->dev_private;
1166 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1168 uint32_t hash_types;
1170 /* RSS configuration is the same for all VNICs */
1171 if (vnic && vnic->rss_hash_key) {
1172 if (rss_conf->rss_key) {
1173 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1174 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1175 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1178 hash_types = vnic->hash_type;
1179 rss_conf->rss_hf = 0;
1180 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1181 rss_conf->rss_hf |= ETH_RSS_IPV4;
1182 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1184 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1185 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1187 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1189 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1190 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1192 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1194 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1195 rss_conf->rss_hf |= ETH_RSS_IPV6;
1196 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1198 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1199 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1201 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1203 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1204 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1206 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1210 "Unknwon RSS config from firmware (%08x), RSS disabled",
1215 rss_conf->rss_hf = 0;
1220 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1221 struct rte_eth_fc_conf *fc_conf)
1223 struct bnxt *bp = dev->data->dev_private;
1224 struct rte_eth_link link_info;
1227 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1231 memset(fc_conf, 0, sizeof(*fc_conf));
1232 if (bp->link_info.auto_pause)
1233 fc_conf->autoneg = 1;
1234 switch (bp->link_info.pause) {
1236 fc_conf->mode = RTE_FC_NONE;
1238 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1239 fc_conf->mode = RTE_FC_TX_PAUSE;
1241 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1242 fc_conf->mode = RTE_FC_RX_PAUSE;
1244 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1245 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1246 fc_conf->mode = RTE_FC_FULL;
1252 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1253 struct rte_eth_fc_conf *fc_conf)
1255 struct bnxt *bp = dev->data->dev_private;
1257 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1258 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1262 switch (fc_conf->mode) {
1264 bp->link_info.auto_pause = 0;
1265 bp->link_info.force_pause = 0;
1267 case RTE_FC_RX_PAUSE:
1268 if (fc_conf->autoneg) {
1269 bp->link_info.auto_pause =
1270 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1271 bp->link_info.force_pause = 0;
1273 bp->link_info.auto_pause = 0;
1274 bp->link_info.force_pause =
1275 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1278 case RTE_FC_TX_PAUSE:
1279 if (fc_conf->autoneg) {
1280 bp->link_info.auto_pause =
1281 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1282 bp->link_info.force_pause = 0;
1284 bp->link_info.auto_pause = 0;
1285 bp->link_info.force_pause =
1286 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1290 if (fc_conf->autoneg) {
1291 bp->link_info.auto_pause =
1292 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1293 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1294 bp->link_info.force_pause = 0;
1296 bp->link_info.auto_pause = 0;
1297 bp->link_info.force_pause =
1298 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1299 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1303 return bnxt_set_hwrm_link_config(bp, true);
1306 /* Add UDP tunneling port */
1308 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1309 struct rte_eth_udp_tunnel *udp_tunnel)
1311 struct bnxt *bp = eth_dev->data->dev_private;
1312 uint16_t tunnel_type = 0;
1315 switch (udp_tunnel->prot_type) {
1316 case RTE_TUNNEL_TYPE_VXLAN:
1317 if (bp->vxlan_port_cnt) {
1318 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1319 udp_tunnel->udp_port);
1320 if (bp->vxlan_port != udp_tunnel->udp_port) {
1321 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1324 bp->vxlan_port_cnt++;
1328 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1329 bp->vxlan_port_cnt++;
1331 case RTE_TUNNEL_TYPE_GENEVE:
1332 if (bp->geneve_port_cnt) {
1333 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1334 udp_tunnel->udp_port);
1335 if (bp->geneve_port != udp_tunnel->udp_port) {
1336 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1339 bp->geneve_port_cnt++;
1343 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1344 bp->geneve_port_cnt++;
1347 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1350 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1356 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1357 struct rte_eth_udp_tunnel *udp_tunnel)
1359 struct bnxt *bp = eth_dev->data->dev_private;
1360 uint16_t tunnel_type = 0;
1364 switch (udp_tunnel->prot_type) {
1365 case RTE_TUNNEL_TYPE_VXLAN:
1366 if (!bp->vxlan_port_cnt) {
1367 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1370 if (bp->vxlan_port != udp_tunnel->udp_port) {
1371 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1372 udp_tunnel->udp_port, bp->vxlan_port);
1375 if (--bp->vxlan_port_cnt)
1379 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1380 port = bp->vxlan_fw_dst_port_id;
1382 case RTE_TUNNEL_TYPE_GENEVE:
1383 if (!bp->geneve_port_cnt) {
1384 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1387 if (bp->geneve_port != udp_tunnel->udp_port) {
1388 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1389 udp_tunnel->udp_port, bp->geneve_port);
1392 if (--bp->geneve_port_cnt)
1396 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1397 port = bp->geneve_fw_dst_port_id;
1400 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1404 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1407 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1410 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1411 bp->geneve_port = 0;
1416 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1418 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1419 struct bnxt_vnic_info *vnic;
1422 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1424 /* Cycle through all VNICs */
1425 for (i = 0; i < bp->nr_vnics; i++) {
1427 * For each VNIC and each associated filter(s)
1428 * if VLAN exists && VLAN matches vlan_id
1429 * remove the MAC+VLAN filter
1430 * add a new MAC only filter
1432 * VLAN filter doesn't exist, just skip and continue
1434 vnic = &bp->vnic_info[i];
1435 filter = STAILQ_FIRST(&vnic->filter);
1437 temp_filter = STAILQ_NEXT(filter, next);
1439 if (filter->enables & chk &&
1440 filter->l2_ovlan == vlan_id) {
1441 /* Must delete the filter */
1442 STAILQ_REMOVE(&vnic->filter, filter,
1443 bnxt_filter_info, next);
1444 bnxt_hwrm_clear_l2_filter(bp, filter);
1445 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1449 * Need to examine to see if the MAC
1450 * filter already existed or not before
1451 * allocating a new one
1454 new_filter = bnxt_alloc_filter(bp);
1457 "MAC/VLAN filter alloc failed\n");
1461 STAILQ_INSERT_TAIL(&vnic->filter,
1463 /* Inherit MAC from previous filter */
1464 new_filter->mac_index =
1466 memcpy(new_filter->l2_addr, filter->l2_addr,
1467 RTE_ETHER_ADDR_LEN);
1468 /* MAC only filter */
1469 rc = bnxt_hwrm_set_l2_filter(bp,
1475 "Del Vlan filter for %d\n",
1478 filter = temp_filter;
1485 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1487 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1488 struct bnxt_vnic_info *vnic;
1491 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1492 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1493 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1495 /* Cycle through all VNICs */
1496 for (i = 0; i < bp->nr_vnics; i++) {
1498 * For each VNIC and each associated filter(s)
1500 * if VLAN matches vlan_id
1501 * VLAN filter already exists, just skip and continue
1503 * add a new MAC+VLAN filter
1505 * Remove the old MAC only filter
1506 * Add a new MAC+VLAN filter
1508 vnic = &bp->vnic_info[i];
1509 filter = STAILQ_FIRST(&vnic->filter);
1511 temp_filter = STAILQ_NEXT(filter, next);
1513 if (filter->enables & chk) {
1514 if (filter->l2_ivlan == vlan_id)
1517 /* Must delete the MAC filter */
1518 STAILQ_REMOVE(&vnic->filter, filter,
1519 bnxt_filter_info, next);
1520 bnxt_hwrm_clear_l2_filter(bp, filter);
1521 filter->l2_ovlan = 0;
1522 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1525 new_filter = bnxt_alloc_filter(bp);
1528 "MAC/VLAN filter alloc failed\n");
1532 STAILQ_INSERT_TAIL(&vnic->filter, new_filter, next);
1533 /* Inherit MAC from the previous filter */
1534 new_filter->mac_index = filter->mac_index;
1535 memcpy(new_filter->l2_addr, filter->l2_addr,
1536 RTE_ETHER_ADDR_LEN);
1537 /* MAC + VLAN ID filter */
1538 new_filter->l2_ivlan = vlan_id;
1539 new_filter->l2_ivlan_mask = 0xF000;
1540 new_filter->enables |= en;
1541 rc = bnxt_hwrm_set_l2_filter(bp,
1547 "Added Vlan filter for %d\n", vlan_id);
1549 filter = temp_filter;
1556 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1557 uint16_t vlan_id, int on)
1559 struct bnxt *bp = eth_dev->data->dev_private;
1561 /* These operations apply to ALL existing MAC/VLAN filters */
1563 return bnxt_add_vlan_filter(bp, vlan_id);
1565 return bnxt_del_vlan_filter(bp, vlan_id);
1569 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1571 struct bnxt *bp = dev->data->dev_private;
1572 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1575 if (mask & ETH_VLAN_FILTER_MASK) {
1576 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1577 /* Remove any VLAN filters programmed */
1578 for (i = 0; i < 4095; i++)
1579 bnxt_del_vlan_filter(bp, i);
1581 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1582 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1585 if (mask & ETH_VLAN_STRIP_MASK) {
1586 /* Enable or disable VLAN stripping */
1587 for (i = 0; i < bp->nr_vnics; i++) {
1588 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1589 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1590 vnic->vlan_strip = true;
1592 vnic->vlan_strip = false;
1593 bnxt_hwrm_vnic_cfg(bp, vnic);
1595 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1596 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1599 if (mask & ETH_VLAN_EXTEND_MASK)
1600 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1606 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1607 struct rte_ether_addr *addr)
1609 struct bnxt *bp = dev->data->dev_private;
1610 /* Default Filter is tied to VNIC 0 */
1611 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1612 struct bnxt_filter_info *filter;
1615 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1618 memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1620 STAILQ_FOREACH(filter, &vnic->filter, next) {
1621 /* Default Filter is at Index 0 */
1622 if (filter->mac_index != 0)
1624 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1627 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
1628 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1629 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1631 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1632 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1633 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1636 filter->mac_index = 0;
1637 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1644 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1645 struct rte_ether_addr *mc_addr_set,
1646 uint32_t nb_mc_addr)
1648 struct bnxt *bp = eth_dev->data->dev_private;
1649 char *mc_addr_list = (char *)mc_addr_set;
1650 struct bnxt_vnic_info *vnic;
1651 uint32_t off = 0, i = 0;
1653 vnic = &bp->vnic_info[0];
1655 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1656 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1660 /* TODO Check for Duplicate mcast addresses */
1661 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1662 for (i = 0; i < nb_mc_addr; i++) {
1663 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1664 RTE_ETHER_ADDR_LEN);
1665 off += RTE_ETHER_ADDR_LEN;
1668 vnic->mc_addr_cnt = i;
1671 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1675 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1677 struct bnxt *bp = dev->data->dev_private;
1678 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1679 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1680 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1683 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1684 fw_major, fw_minor, fw_updt);
1686 ret += 1; /* add the size of '\0' */
1687 if (fw_size < (uint32_t)ret)
1694 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1695 struct rte_eth_rxq_info *qinfo)
1697 struct bnxt_rx_queue *rxq;
1699 rxq = dev->data->rx_queues[queue_id];
1701 qinfo->mp = rxq->mb_pool;
1702 qinfo->scattered_rx = dev->data->scattered_rx;
1703 qinfo->nb_desc = rxq->nb_rx_desc;
1705 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1706 qinfo->conf.rx_drop_en = 0;
1707 qinfo->conf.rx_deferred_start = 0;
1711 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1712 struct rte_eth_txq_info *qinfo)
1714 struct bnxt_tx_queue *txq;
1716 txq = dev->data->tx_queues[queue_id];
1718 qinfo->nb_desc = txq->nb_tx_desc;
1720 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1721 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1722 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1724 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1725 qinfo->conf.tx_rs_thresh = 0;
1726 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1729 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1731 struct bnxt *bp = eth_dev->data->dev_private;
1732 struct rte_eth_dev_info dev_info;
1733 uint32_t new_pkt_size;
1737 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1738 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
1740 bnxt_dev_info_get_op(eth_dev, &dev_info);
1742 if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > BNXT_MAX_MTU) {
1743 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1744 RTE_ETHER_MIN_MTU, BNXT_MAX_MTU);
1750 * If vector-mode tx/rx is active, disallow any MTU change that would
1751 * require scattered receive support.
1753 if (eth_dev->data->dev_started &&
1754 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
1755 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
1757 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
1759 "MTU change would require scattered rx support. ");
1760 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
1765 if (new_mtu > RTE_ETHER_MTU) {
1766 bp->flags |= BNXT_FLAG_JUMBO;
1767 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1768 DEV_RX_OFFLOAD_JUMBO_FRAME;
1770 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1771 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1772 bp->flags &= ~BNXT_FLAG_JUMBO;
1775 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
1777 eth_dev->data->mtu = new_mtu;
1778 PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1780 for (i = 0; i < bp->nr_vnics; i++) {
1781 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1784 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1785 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1786 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1790 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1791 size -= RTE_PKTMBUF_HEADROOM;
1793 if (size < new_mtu) {
1794 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1804 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1806 struct bnxt *bp = dev->data->dev_private;
1807 uint16_t vlan = bp->vlan;
1810 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1812 "PVID cannot be modified for this function\n");
1815 bp->vlan = on ? pvid : 0;
1817 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1824 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1826 struct bnxt *bp = dev->data->dev_private;
1828 return bnxt_hwrm_port_led_cfg(bp, true);
1832 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1834 struct bnxt *bp = dev->data->dev_private;
1836 return bnxt_hwrm_port_led_cfg(bp, false);
1840 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1842 uint32_t desc = 0, raw_cons = 0, cons;
1843 struct bnxt_cp_ring_info *cpr;
1844 struct bnxt_rx_queue *rxq;
1845 struct rx_pkt_cmpl *rxcmp;
1850 rxq = dev->data->rx_queues[rx_queue_id];
1854 while (raw_cons < rxq->nb_rx_desc) {
1855 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1856 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1858 if (!CMPL_VALID(rxcmp, valid))
1860 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1861 cmp_type = CMP_TYPE(rxcmp);
1862 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1863 cmp = (rte_le_to_cpu_32(
1864 ((struct rx_tpa_end_cmpl *)
1865 (rxcmp))->agg_bufs_v1) &
1866 RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1867 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1869 } else if (cmp_type == 0x11) {
1871 cmp = (rxcmp->agg_bufs_v1 &
1872 RX_PKT_CMPL_AGG_BUFS_MASK) >>
1873 RX_PKT_CMPL_AGG_BUFS_SFT;
1878 raw_cons += cmp ? cmp : 2;
1885 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1887 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1888 struct bnxt_rx_ring_info *rxr;
1889 struct bnxt_cp_ring_info *cpr;
1890 struct bnxt_sw_rx_bd *rx_buf;
1891 struct rx_pkt_cmpl *rxcmp;
1892 uint32_t cons, cp_cons;
1900 if (offset >= rxq->nb_rx_desc)
1903 cons = RING_CMP(cpr->cp_ring_struct, offset);
1904 cp_cons = cpr->cp_raw_cons;
1905 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1907 if (cons > cp_cons) {
1908 if (CMPL_VALID(rxcmp, cpr->valid))
1909 return RTE_ETH_RX_DESC_DONE;
1911 if (CMPL_VALID(rxcmp, !cpr->valid))
1912 return RTE_ETH_RX_DESC_DONE;
1914 rx_buf = &rxr->rx_buf_ring[cons];
1915 if (rx_buf->mbuf == NULL)
1916 return RTE_ETH_RX_DESC_UNAVAIL;
1919 return RTE_ETH_RX_DESC_AVAIL;
1923 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1925 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1926 struct bnxt_tx_ring_info *txr;
1927 struct bnxt_cp_ring_info *cpr;
1928 struct bnxt_sw_tx_bd *tx_buf;
1929 struct tx_pkt_cmpl *txcmp;
1930 uint32_t cons, cp_cons;
1938 if (offset >= txq->nb_tx_desc)
1941 cons = RING_CMP(cpr->cp_ring_struct, offset);
1942 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1943 cp_cons = cpr->cp_raw_cons;
1945 if (cons > cp_cons) {
1946 if (CMPL_VALID(txcmp, cpr->valid))
1947 return RTE_ETH_TX_DESC_UNAVAIL;
1949 if (CMPL_VALID(txcmp, !cpr->valid))
1950 return RTE_ETH_TX_DESC_UNAVAIL;
1952 tx_buf = &txr->tx_buf_ring[cons];
1953 if (tx_buf->mbuf == NULL)
1954 return RTE_ETH_TX_DESC_DONE;
1956 return RTE_ETH_TX_DESC_FULL;
1959 static struct bnxt_filter_info *
1960 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
1961 struct rte_eth_ethertype_filter *efilter,
1962 struct bnxt_vnic_info *vnic0,
1963 struct bnxt_vnic_info *vnic,
1966 struct bnxt_filter_info *mfilter = NULL;
1970 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
1971 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
1972 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
1973 " ethertype filter.", efilter->ether_type);
1977 if (efilter->queue >= bp->rx_nr_rings) {
1978 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1983 vnic0 = &bp->vnic_info[0];
1984 vnic = &bp->vnic_info[efilter->queue];
1986 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1991 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1992 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
1993 if ((!memcmp(efilter->mac_addr.addr_bytes,
1994 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
1996 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
1997 mfilter->ethertype == efilter->ether_type)) {
2003 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2004 if ((!memcmp(efilter->mac_addr.addr_bytes,
2005 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2006 mfilter->ethertype == efilter->ether_type &&
2008 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2022 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2023 enum rte_filter_op filter_op,
2026 struct bnxt *bp = dev->data->dev_private;
2027 struct rte_eth_ethertype_filter *efilter =
2028 (struct rte_eth_ethertype_filter *)arg;
2029 struct bnxt_filter_info *bfilter, *filter1;
2030 struct bnxt_vnic_info *vnic, *vnic0;
2033 if (filter_op == RTE_ETH_FILTER_NOP)
2037 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2042 vnic0 = &bp->vnic_info[0];
2043 vnic = &bp->vnic_info[efilter->queue];
2045 switch (filter_op) {
2046 case RTE_ETH_FILTER_ADD:
2047 bnxt_match_and_validate_ether_filter(bp, efilter,
2052 bfilter = bnxt_get_unused_filter(bp);
2053 if (bfilter == NULL) {
2055 "Not enough resources for a new filter.\n");
2058 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2059 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2060 RTE_ETHER_ADDR_LEN);
2061 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2062 RTE_ETHER_ADDR_LEN);
2063 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2064 bfilter->ethertype = efilter->ether_type;
2065 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2067 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2068 if (filter1 == NULL) {
2073 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2074 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2076 bfilter->dst_id = vnic->fw_vnic_id;
2078 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2080 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2083 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2086 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2088 case RTE_ETH_FILTER_DELETE:
2089 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2091 if (ret == -EEXIST) {
2092 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2094 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2096 bnxt_free_filter(bp, filter1);
2097 } else if (ret == 0) {
2098 PMD_DRV_LOG(ERR, "No matching filter found\n");
2102 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2108 bnxt_free_filter(bp, bfilter);
2114 parse_ntuple_filter(struct bnxt *bp,
2115 struct rte_eth_ntuple_filter *nfilter,
2116 struct bnxt_filter_info *bfilter)
2120 if (nfilter->queue >= bp->rx_nr_rings) {
2121 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2125 switch (nfilter->dst_port_mask) {
2127 bfilter->dst_port_mask = -1;
2128 bfilter->dst_port = nfilter->dst_port;
2129 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2130 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2133 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2137 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2138 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2140 switch (nfilter->proto_mask) {
2142 if (nfilter->proto == 17) /* IPPROTO_UDP */
2143 bfilter->ip_protocol = 17;
2144 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2145 bfilter->ip_protocol = 6;
2148 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2151 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2155 switch (nfilter->dst_ip_mask) {
2157 bfilter->dst_ipaddr_mask[0] = -1;
2158 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2159 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2160 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2163 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2167 switch (nfilter->src_ip_mask) {
2169 bfilter->src_ipaddr_mask[0] = -1;
2170 bfilter->src_ipaddr[0] = nfilter->src_ip;
2171 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2172 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2175 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2179 switch (nfilter->src_port_mask) {
2181 bfilter->src_port_mask = -1;
2182 bfilter->src_port = nfilter->src_port;
2183 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2184 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2187 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2192 //nfilter->priority = (uint8_t)filter->priority;
2194 bfilter->enables = en;
2198 static struct bnxt_filter_info*
2199 bnxt_match_ntuple_filter(struct bnxt *bp,
2200 struct bnxt_filter_info *bfilter,
2201 struct bnxt_vnic_info **mvnic)
2203 struct bnxt_filter_info *mfilter = NULL;
2206 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2207 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2208 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2209 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2210 bfilter->src_ipaddr_mask[0] ==
2211 mfilter->src_ipaddr_mask[0] &&
2212 bfilter->src_port == mfilter->src_port &&
2213 bfilter->src_port_mask == mfilter->src_port_mask &&
2214 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2215 bfilter->dst_ipaddr_mask[0] ==
2216 mfilter->dst_ipaddr_mask[0] &&
2217 bfilter->dst_port == mfilter->dst_port &&
2218 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2219 bfilter->flags == mfilter->flags &&
2220 bfilter->enables == mfilter->enables) {
2231 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2232 struct rte_eth_ntuple_filter *nfilter,
2233 enum rte_filter_op filter_op)
2235 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2236 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2239 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2240 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2244 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2245 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2249 bfilter = bnxt_get_unused_filter(bp);
2250 if (bfilter == NULL) {
2252 "Not enough resources for a new filter.\n");
2255 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2259 vnic = &bp->vnic_info[nfilter->queue];
2260 vnic0 = &bp->vnic_info[0];
2261 filter1 = STAILQ_FIRST(&vnic0->filter);
2262 if (filter1 == NULL) {
2267 bfilter->dst_id = vnic->fw_vnic_id;
2268 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2270 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2271 bfilter->ethertype = 0x800;
2272 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2274 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2276 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2277 bfilter->dst_id == mfilter->dst_id) {
2278 PMD_DRV_LOG(ERR, "filter exists.\n");
2281 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2282 bfilter->dst_id != mfilter->dst_id) {
2283 mfilter->dst_id = vnic->fw_vnic_id;
2284 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2285 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2286 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2287 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2288 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2291 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2292 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2297 if (filter_op == RTE_ETH_FILTER_ADD) {
2298 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2299 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2302 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2304 if (mfilter == NULL) {
2305 /* This should not happen. But for Coverity! */
2309 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2311 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2312 bnxt_free_filter(bp, mfilter);
2313 mfilter->fw_l2_filter_id = -1;
2314 bnxt_free_filter(bp, bfilter);
2315 bfilter->fw_l2_filter_id = -1;
2320 bfilter->fw_l2_filter_id = -1;
2321 bnxt_free_filter(bp, bfilter);
2326 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2327 enum rte_filter_op filter_op,
2330 struct bnxt *bp = dev->data->dev_private;
2333 if (filter_op == RTE_ETH_FILTER_NOP)
2337 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2342 switch (filter_op) {
2343 case RTE_ETH_FILTER_ADD:
2344 ret = bnxt_cfg_ntuple_filter(bp,
2345 (struct rte_eth_ntuple_filter *)arg,
2348 case RTE_ETH_FILTER_DELETE:
2349 ret = bnxt_cfg_ntuple_filter(bp,
2350 (struct rte_eth_ntuple_filter *)arg,
2354 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2362 bnxt_parse_fdir_filter(struct bnxt *bp,
2363 struct rte_eth_fdir_filter *fdir,
2364 struct bnxt_filter_info *filter)
2366 enum rte_fdir_mode fdir_mode =
2367 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2368 struct bnxt_vnic_info *vnic0, *vnic;
2369 struct bnxt_filter_info *filter1;
2373 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2376 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2377 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2379 switch (fdir->input.flow_type) {
2380 case RTE_ETH_FLOW_IPV4:
2381 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2383 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2384 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2385 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2386 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2387 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2388 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2389 filter->ip_addr_type =
2390 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2391 filter->src_ipaddr_mask[0] = 0xffffffff;
2392 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2393 filter->dst_ipaddr_mask[0] = 0xffffffff;
2394 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2395 filter->ethertype = 0x800;
2396 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2398 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2399 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2400 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2401 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2402 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2403 filter->dst_port_mask = 0xffff;
2404 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2405 filter->src_port_mask = 0xffff;
2406 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2407 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2408 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2409 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2410 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2411 filter->ip_protocol = 6;
2412 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2413 filter->ip_addr_type =
2414 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2415 filter->src_ipaddr_mask[0] = 0xffffffff;
2416 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2417 filter->dst_ipaddr_mask[0] = 0xffffffff;
2418 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2419 filter->ethertype = 0x800;
2420 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2422 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2423 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2424 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2425 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2426 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2427 filter->dst_port_mask = 0xffff;
2428 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2429 filter->src_port_mask = 0xffff;
2430 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2431 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2432 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2433 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2434 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2435 filter->ip_protocol = 17;
2436 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2437 filter->ip_addr_type =
2438 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2439 filter->src_ipaddr_mask[0] = 0xffffffff;
2440 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2441 filter->dst_ipaddr_mask[0] = 0xffffffff;
2442 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2443 filter->ethertype = 0x800;
2444 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2446 case RTE_ETH_FLOW_IPV6:
2447 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2449 filter->ip_addr_type =
2450 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2451 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2452 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2453 rte_memcpy(filter->src_ipaddr,
2454 fdir->input.flow.ipv6_flow.src_ip, 16);
2455 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2456 rte_memcpy(filter->dst_ipaddr,
2457 fdir->input.flow.ipv6_flow.dst_ip, 16);
2458 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2459 memset(filter->dst_ipaddr_mask, 0xff, 16);
2460 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2461 memset(filter->src_ipaddr_mask, 0xff, 16);
2462 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2463 filter->ethertype = 0x86dd;
2464 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2466 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2467 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2468 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2469 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2470 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2471 filter->dst_port_mask = 0xffff;
2472 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2473 filter->src_port_mask = 0xffff;
2474 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2475 filter->ip_addr_type =
2476 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2477 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2478 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2479 rte_memcpy(filter->src_ipaddr,
2480 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2481 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2482 rte_memcpy(filter->dst_ipaddr,
2483 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2484 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2485 memset(filter->dst_ipaddr_mask, 0xff, 16);
2486 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2487 memset(filter->src_ipaddr_mask, 0xff, 16);
2488 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2489 filter->ethertype = 0x86dd;
2490 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2492 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2493 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2494 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2495 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2496 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2497 filter->dst_port_mask = 0xffff;
2498 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2499 filter->src_port_mask = 0xffff;
2500 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2501 filter->ip_addr_type =
2502 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2503 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2504 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2505 rte_memcpy(filter->src_ipaddr,
2506 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2507 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2508 rte_memcpy(filter->dst_ipaddr,
2509 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2510 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2511 memset(filter->dst_ipaddr_mask, 0xff, 16);
2512 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2513 memset(filter->src_ipaddr_mask, 0xff, 16);
2514 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2515 filter->ethertype = 0x86dd;
2516 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2518 case RTE_ETH_FLOW_L2_PAYLOAD:
2519 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2520 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2522 case RTE_ETH_FLOW_VXLAN:
2523 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2525 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2526 filter->tunnel_type =
2527 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2528 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2530 case RTE_ETH_FLOW_NVGRE:
2531 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2533 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2534 filter->tunnel_type =
2535 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2536 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2538 case RTE_ETH_FLOW_UNKNOWN:
2539 case RTE_ETH_FLOW_RAW:
2540 case RTE_ETH_FLOW_FRAG_IPV4:
2541 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2542 case RTE_ETH_FLOW_FRAG_IPV6:
2543 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2544 case RTE_ETH_FLOW_IPV6_EX:
2545 case RTE_ETH_FLOW_IPV6_TCP_EX:
2546 case RTE_ETH_FLOW_IPV6_UDP_EX:
2547 case RTE_ETH_FLOW_GENEVE:
2553 vnic0 = &bp->vnic_info[0];
2554 vnic = &bp->vnic_info[fdir->action.rx_queue];
2556 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2561 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2562 rte_memcpy(filter->dst_macaddr,
2563 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2564 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2567 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2568 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2569 filter1 = STAILQ_FIRST(&vnic0->filter);
2570 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2572 filter->dst_id = vnic->fw_vnic_id;
2573 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2574 if (filter->dst_macaddr[i] == 0x00)
2575 filter1 = STAILQ_FIRST(&vnic0->filter);
2577 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2580 if (filter1 == NULL)
2583 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2584 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2586 filter->enables = en;
2591 static struct bnxt_filter_info *
2592 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2593 struct bnxt_vnic_info **mvnic)
2595 struct bnxt_filter_info *mf = NULL;
2598 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2599 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2601 STAILQ_FOREACH(mf, &vnic->filter, next) {
2602 if (mf->filter_type == nf->filter_type &&
2603 mf->flags == nf->flags &&
2604 mf->src_port == nf->src_port &&
2605 mf->src_port_mask == nf->src_port_mask &&
2606 mf->dst_port == nf->dst_port &&
2607 mf->dst_port_mask == nf->dst_port_mask &&
2608 mf->ip_protocol == nf->ip_protocol &&
2609 mf->ip_addr_type == nf->ip_addr_type &&
2610 mf->ethertype == nf->ethertype &&
2611 mf->vni == nf->vni &&
2612 mf->tunnel_type == nf->tunnel_type &&
2613 mf->l2_ovlan == nf->l2_ovlan &&
2614 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2615 mf->l2_ivlan == nf->l2_ivlan &&
2616 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2617 !memcmp(mf->l2_addr, nf->l2_addr,
2618 RTE_ETHER_ADDR_LEN) &&
2619 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2620 RTE_ETHER_ADDR_LEN) &&
2621 !memcmp(mf->src_macaddr, nf->src_macaddr,
2622 RTE_ETHER_ADDR_LEN) &&
2623 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2624 RTE_ETHER_ADDR_LEN) &&
2625 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2626 sizeof(nf->src_ipaddr)) &&
2627 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2628 sizeof(nf->src_ipaddr_mask)) &&
2629 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2630 sizeof(nf->dst_ipaddr)) &&
2631 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2632 sizeof(nf->dst_ipaddr_mask))) {
2643 bnxt_fdir_filter(struct rte_eth_dev *dev,
2644 enum rte_filter_op filter_op,
2647 struct bnxt *bp = dev->data->dev_private;
2648 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
2649 struct bnxt_filter_info *filter, *match;
2650 struct bnxt_vnic_info *vnic, *mvnic;
2653 if (filter_op == RTE_ETH_FILTER_NOP)
2656 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2659 switch (filter_op) {
2660 case RTE_ETH_FILTER_ADD:
2661 case RTE_ETH_FILTER_DELETE:
2663 filter = bnxt_get_unused_filter(bp);
2664 if (filter == NULL) {
2666 "Not enough resources for a new flow.\n");
2670 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2673 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2675 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2676 vnic = &bp->vnic_info[0];
2678 vnic = &bp->vnic_info[fdir->action.rx_queue];
2680 match = bnxt_match_fdir(bp, filter, &mvnic);
2681 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2682 if (match->dst_id == vnic->fw_vnic_id) {
2683 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2687 match->dst_id = vnic->fw_vnic_id;
2688 ret = bnxt_hwrm_set_ntuple_filter(bp,
2691 STAILQ_REMOVE(&mvnic->filter, match,
2692 bnxt_filter_info, next);
2693 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2695 "Filter with matching pattern exist\n");
2697 "Updated it to new destination q\n");
2701 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2702 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2707 if (filter_op == RTE_ETH_FILTER_ADD) {
2708 ret = bnxt_hwrm_set_ntuple_filter(bp,
2713 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2715 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2716 STAILQ_REMOVE(&vnic->filter, match,
2717 bnxt_filter_info, next);
2718 bnxt_free_filter(bp, match);
2719 filter->fw_l2_filter_id = -1;
2720 bnxt_free_filter(bp, filter);
2723 case RTE_ETH_FILTER_FLUSH:
2724 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2725 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2727 STAILQ_FOREACH(filter, &vnic->filter, next) {
2728 if (filter->filter_type ==
2729 HWRM_CFA_NTUPLE_FILTER) {
2731 bnxt_hwrm_clear_ntuple_filter(bp,
2733 STAILQ_REMOVE(&vnic->filter, filter,
2734 bnxt_filter_info, next);
2739 case RTE_ETH_FILTER_UPDATE:
2740 case RTE_ETH_FILTER_STATS:
2741 case RTE_ETH_FILTER_INFO:
2742 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2745 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2752 filter->fw_l2_filter_id = -1;
2753 bnxt_free_filter(bp, filter);
2758 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2759 enum rte_filter_type filter_type,
2760 enum rte_filter_op filter_op, void *arg)
2764 switch (filter_type) {
2765 case RTE_ETH_FILTER_TUNNEL:
2767 "filter type: %d: To be implemented\n", filter_type);
2769 case RTE_ETH_FILTER_FDIR:
2770 ret = bnxt_fdir_filter(dev, filter_op, arg);
2772 case RTE_ETH_FILTER_NTUPLE:
2773 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2775 case RTE_ETH_FILTER_ETHERTYPE:
2776 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2778 case RTE_ETH_FILTER_GENERIC:
2779 if (filter_op != RTE_ETH_FILTER_GET)
2781 *(const void **)arg = &bnxt_flow_ops;
2785 "Filter type (%d) not supported", filter_type);
2792 static const uint32_t *
2793 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2795 static const uint32_t ptypes[] = {
2796 RTE_PTYPE_L2_ETHER_VLAN,
2797 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2798 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2802 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2803 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2804 RTE_PTYPE_INNER_L4_ICMP,
2805 RTE_PTYPE_INNER_L4_TCP,
2806 RTE_PTYPE_INNER_L4_UDP,
2810 if (!dev->rx_pkt_burst)
2816 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2819 uint32_t reg_base = *reg_arr & 0xfffff000;
2823 for (i = 0; i < count; i++) {
2824 if ((reg_arr[i] & 0xfffff000) != reg_base)
2827 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2828 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
2832 static int bnxt_map_ptp_regs(struct bnxt *bp)
2834 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2838 reg_arr = ptp->rx_regs;
2839 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2843 reg_arr = ptp->tx_regs;
2844 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2848 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2849 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2851 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2852 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2857 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2859 rte_write32(0, (uint8_t *)bp->bar0 +
2860 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
2861 rte_write32(0, (uint8_t *)bp->bar0 +
2862 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
2865 static uint64_t bnxt_cc_read(struct bnxt *bp)
2869 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2870 BNXT_GRCPF_REG_SYNC_TIME));
2871 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2872 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2876 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2878 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2881 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2882 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2883 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2886 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2887 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2888 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2889 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2890 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2891 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2896 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2898 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2899 struct bnxt_pf_info *pf = &bp->pf;
2906 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2907 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2908 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2911 port_id = pf->port_id;
2912 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2913 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
2915 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2916 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2917 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
2918 /* bnxt_clr_rx_ts(bp); TBD */
2922 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2923 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
2924 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2925 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
2931 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
2934 struct bnxt *bp = dev->data->dev_private;
2935 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2940 ns = rte_timespec_to_ns(ts);
2941 /* Set the timecounters to a new value. */
2948 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
2950 uint64_t ns, systime_cycles;
2951 struct bnxt *bp = dev->data->dev_private;
2952 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2957 systime_cycles = bnxt_cc_read(bp);
2958 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
2959 *ts = rte_ns_to_timespec(ns);
2964 bnxt_timesync_enable(struct rte_eth_dev *dev)
2966 struct bnxt *bp = dev->data->dev_private;
2967 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2974 ptp->tx_tstamp_en = 1;
2975 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
2977 if (!bnxt_hwrm_ptp_cfg(bp))
2978 bnxt_map_ptp_regs(bp);
2980 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
2981 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2982 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2984 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2985 ptp->tc.cc_shift = shift;
2986 ptp->tc.nsec_mask = (1ULL << shift) - 1;
2988 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2989 ptp->rx_tstamp_tc.cc_shift = shift;
2990 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2992 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2993 ptp->tx_tstamp_tc.cc_shift = shift;
2994 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3000 bnxt_timesync_disable(struct rte_eth_dev *dev)
3002 struct bnxt *bp = dev->data->dev_private;
3003 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3009 ptp->tx_tstamp_en = 0;
3012 bnxt_hwrm_ptp_cfg(bp);
3014 bnxt_unmap_ptp_regs(bp);
3020 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3021 struct timespec *timestamp,
3022 uint32_t flags __rte_unused)
3024 struct bnxt *bp = dev->data->dev_private;
3025 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3026 uint64_t rx_tstamp_cycles = 0;
3032 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3033 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3034 *timestamp = rte_ns_to_timespec(ns);
3039 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3040 struct timespec *timestamp)
3042 struct bnxt *bp = dev->data->dev_private;
3043 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3044 uint64_t tx_tstamp_cycles = 0;
3050 bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3051 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3052 *timestamp = rte_ns_to_timespec(ns);
3058 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3060 struct bnxt *bp = dev->data->dev_private;
3061 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3066 ptp->tc.nsec += delta;
3072 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3074 struct bnxt *bp = dev->data->dev_private;
3076 uint32_t dir_entries;
3077 uint32_t entry_length;
3079 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3080 bp->pdev->addr.domain, bp->pdev->addr.bus,
3081 bp->pdev->addr.devid, bp->pdev->addr.function);
3083 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3087 return dir_entries * entry_length;
3091 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3092 struct rte_dev_eeprom_info *in_eeprom)
3094 struct bnxt *bp = dev->data->dev_private;
3098 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3099 "len = %d\n", bp->pdev->addr.domain,
3100 bp->pdev->addr.bus, bp->pdev->addr.devid,
3101 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3103 if (in_eeprom->offset == 0) /* special offset value to get directory */
3104 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3107 index = in_eeprom->offset >> 24;
3108 offset = in_eeprom->offset & 0xffffff;
3111 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3112 in_eeprom->length, in_eeprom->data);
3117 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3120 case BNX_DIR_TYPE_CHIMP_PATCH:
3121 case BNX_DIR_TYPE_BOOTCODE:
3122 case BNX_DIR_TYPE_BOOTCODE_2:
3123 case BNX_DIR_TYPE_APE_FW:
3124 case BNX_DIR_TYPE_APE_PATCH:
3125 case BNX_DIR_TYPE_KONG_FW:
3126 case BNX_DIR_TYPE_KONG_PATCH:
3127 case BNX_DIR_TYPE_BONO_FW:
3128 case BNX_DIR_TYPE_BONO_PATCH:
3136 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3139 case BNX_DIR_TYPE_AVS:
3140 case BNX_DIR_TYPE_EXP_ROM_MBA:
3141 case BNX_DIR_TYPE_PCIE:
3142 case BNX_DIR_TYPE_TSCF_UCODE:
3143 case BNX_DIR_TYPE_EXT_PHY:
3144 case BNX_DIR_TYPE_CCM:
3145 case BNX_DIR_TYPE_ISCSI_BOOT:
3146 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3147 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3155 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3157 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3158 bnxt_dir_type_is_other_exec_format(dir_type);
3162 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3163 struct rte_dev_eeprom_info *in_eeprom)
3165 struct bnxt *bp = dev->data->dev_private;
3166 uint8_t index, dir_op;
3167 uint16_t type, ext, ordinal, attr;
3169 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3170 "len = %d\n", bp->pdev->addr.domain,
3171 bp->pdev->addr.bus, bp->pdev->addr.devid,
3172 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3175 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3179 type = in_eeprom->magic >> 16;
3181 if (type == 0xffff) { /* special value for directory operations */
3182 index = in_eeprom->magic & 0xff;
3183 dir_op = in_eeprom->magic >> 8;
3187 case 0x0e: /* erase */
3188 if (in_eeprom->offset != ~in_eeprom->magic)
3190 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3196 /* Create or re-write an NVM item: */
3197 if (bnxt_dir_type_is_executable(type) == true)
3199 ext = in_eeprom->magic & 0xffff;
3200 ordinal = in_eeprom->offset >> 16;
3201 attr = in_eeprom->offset & 0xffff;
3203 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3204 in_eeprom->data, in_eeprom->length);
3212 static const struct eth_dev_ops bnxt_dev_ops = {
3213 .dev_infos_get = bnxt_dev_info_get_op,
3214 .dev_close = bnxt_dev_close_op,
3215 .dev_configure = bnxt_dev_configure_op,
3216 .dev_start = bnxt_dev_start_op,
3217 .dev_stop = bnxt_dev_stop_op,
3218 .dev_set_link_up = bnxt_dev_set_link_up_op,
3219 .dev_set_link_down = bnxt_dev_set_link_down_op,
3220 .stats_get = bnxt_stats_get_op,
3221 .stats_reset = bnxt_stats_reset_op,
3222 .rx_queue_setup = bnxt_rx_queue_setup_op,
3223 .rx_queue_release = bnxt_rx_queue_release_op,
3224 .tx_queue_setup = bnxt_tx_queue_setup_op,
3225 .tx_queue_release = bnxt_tx_queue_release_op,
3226 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3227 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3228 .reta_update = bnxt_reta_update_op,
3229 .reta_query = bnxt_reta_query_op,
3230 .rss_hash_update = bnxt_rss_hash_update_op,
3231 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3232 .link_update = bnxt_link_update_op,
3233 .promiscuous_enable = bnxt_promiscuous_enable_op,
3234 .promiscuous_disable = bnxt_promiscuous_disable_op,
3235 .allmulticast_enable = bnxt_allmulticast_enable_op,
3236 .allmulticast_disable = bnxt_allmulticast_disable_op,
3237 .mac_addr_add = bnxt_mac_addr_add_op,
3238 .mac_addr_remove = bnxt_mac_addr_remove_op,
3239 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3240 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3241 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3242 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3243 .vlan_filter_set = bnxt_vlan_filter_set_op,
3244 .vlan_offload_set = bnxt_vlan_offload_set_op,
3245 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3246 .mtu_set = bnxt_mtu_set_op,
3247 .mac_addr_set = bnxt_set_default_mac_addr_op,
3248 .xstats_get = bnxt_dev_xstats_get_op,
3249 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3250 .xstats_reset = bnxt_dev_xstats_reset_op,
3251 .fw_version_get = bnxt_fw_version_get,
3252 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3253 .rxq_info_get = bnxt_rxq_info_get_op,
3254 .txq_info_get = bnxt_txq_info_get_op,
3255 .dev_led_on = bnxt_dev_led_on_op,
3256 .dev_led_off = bnxt_dev_led_off_op,
3257 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3258 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3259 .rx_queue_count = bnxt_rx_queue_count_op,
3260 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3261 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3262 .rx_queue_start = bnxt_rx_queue_start,
3263 .rx_queue_stop = bnxt_rx_queue_stop,
3264 .tx_queue_start = bnxt_tx_queue_start,
3265 .tx_queue_stop = bnxt_tx_queue_stop,
3266 .filter_ctrl = bnxt_filter_ctrl_op,
3267 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3268 .get_eeprom_length = bnxt_get_eeprom_length_op,
3269 .get_eeprom = bnxt_get_eeprom_op,
3270 .set_eeprom = bnxt_set_eeprom_op,
3271 .timesync_enable = bnxt_timesync_enable,
3272 .timesync_disable = bnxt_timesync_disable,
3273 .timesync_read_time = bnxt_timesync_read_time,
3274 .timesync_write_time = bnxt_timesync_write_time,
3275 .timesync_adjust_time = bnxt_timesync_adjust_time,
3276 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3277 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3280 static bool bnxt_vf_pciid(uint16_t id)
3282 if (id == BROADCOM_DEV_ID_57304_VF ||
3283 id == BROADCOM_DEV_ID_57406_VF ||
3284 id == BROADCOM_DEV_ID_5731X_VF ||
3285 id == BROADCOM_DEV_ID_5741X_VF ||
3286 id == BROADCOM_DEV_ID_57414_VF ||
3287 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3288 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3289 id == BROADCOM_DEV_ID_58802_VF ||
3290 id == BROADCOM_DEV_ID_57500_VF)
3295 bool bnxt_stratus_device(struct bnxt *bp)
3297 uint16_t id = bp->pdev->id.device_id;
3299 if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3300 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3301 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3306 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3308 struct bnxt *bp = eth_dev->data->dev_private;
3309 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3312 /* enable device (incl. PCI PM wakeup), and bus-mastering */
3313 if (!pci_dev->mem_resource[0].addr) {
3315 "Cannot find PCI device base address, aborting\n");
3317 goto init_err_disable;
3320 bp->eth_dev = eth_dev;
3323 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3325 PMD_DRV_LOG(ERR, "Cannot map device registers, aborting\n");
3327 goto init_err_release;
3330 if (!pci_dev->mem_resource[2].addr) {
3332 "Cannot find PCI device BAR 2 address, aborting\n");
3334 goto init_err_release;
3336 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3344 if (bp->doorbell_base)
3345 bp->doorbell_base = NULL;
3352 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
3353 struct bnxt_ctx_pg_info *ctx_pg,
3358 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
3359 const struct rte_memzone *mz = NULL;
3360 char mz_name[RTE_MEMZONE_NAMESIZE];
3361 rte_iova_t mz_phys_addr;
3362 uint64_t valid_bits = 0;
3369 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
3371 rmem->page_size = BNXT_PAGE_SIZE;
3372 rmem->pg_arr = ctx_pg->ctx_pg_arr;
3373 rmem->dma_arr = ctx_pg->ctx_dma_arr;
3374 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
3376 valid_bits = PTU_PTE_VALID;
3378 if (rmem->nr_pages > 1) {
3379 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_pg_tbl%s_%x",
3381 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3382 mz = rte_memzone_lookup(mz_name);
3384 mz = rte_memzone_reserve_aligned(mz_name,
3388 RTE_MEMZONE_SIZE_HINT_ONLY |
3389 RTE_MEMZONE_IOVA_CONTIG,
3395 memset(mz->addr, 0, mz->len);
3396 mz_phys_addr = mz->iova;
3397 if ((unsigned long)mz->addr == mz_phys_addr) {
3398 PMD_DRV_LOG(WARNING,
3399 "Memzone physical address same as virtual.\n");
3400 PMD_DRV_LOG(WARNING,
3401 "Using rte_mem_virt2iova()\n");
3402 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3403 if (mz_phys_addr == 0) {
3405 "unable to map addr to phys memory\n");
3409 rte_mem_lock_page(((char *)mz->addr));
3411 rmem->pg_tbl = mz->addr;
3412 rmem->pg_tbl_map = mz_phys_addr;
3413 rmem->pg_tbl_mz = mz;
3416 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x", suffix, idx);
3417 mz = rte_memzone_lookup(mz_name);
3419 mz = rte_memzone_reserve_aligned(mz_name,
3423 RTE_MEMZONE_SIZE_HINT_ONLY |
3424 RTE_MEMZONE_IOVA_CONTIG,
3430 memset(mz->addr, 0, mz->len);
3431 mz_phys_addr = mz->iova;
3432 if ((unsigned long)mz->addr == mz_phys_addr) {
3433 PMD_DRV_LOG(WARNING,
3434 "Memzone physical address same as virtual.\n");
3435 PMD_DRV_LOG(WARNING,
3436 "Using rte_mem_virt2iova()\n");
3437 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
3438 rte_mem_lock_page(((char *)mz->addr) + sz);
3439 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3440 if (mz_phys_addr == RTE_BAD_IOVA) {
3442 "unable to map addr to phys memory\n");
3447 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
3448 rte_mem_lock_page(((char *)mz->addr) + sz);
3449 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
3450 rmem->dma_arr[i] = mz_phys_addr + sz;
3452 if (rmem->nr_pages > 1) {
3453 if (i == rmem->nr_pages - 2 &&
3454 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3455 valid_bits |= PTU_PTE_NEXT_TO_LAST;
3456 else if (i == rmem->nr_pages - 1 &&
3457 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3458 valid_bits |= PTU_PTE_LAST;
3460 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
3466 if (rmem->vmem_size)
3467 rmem->vmem = (void **)mz->addr;
3468 rmem->dma_arr[0] = mz_phys_addr;
3472 static void bnxt_free_ctx_mem(struct bnxt *bp)
3476 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
3479 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
3480 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
3481 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
3482 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
3483 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
3484 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
3485 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
3486 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
3487 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
3488 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
3489 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
3491 for (i = 0; i < BNXT_MAX_Q; i++) {
3492 if (bp->ctx->tqm_mem[i])
3493 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
3500 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
3502 #define min_t(type, x, y) ({ \
3503 type __min1 = (x); \
3504 type __min2 = (y); \
3505 __min1 < __min2 ? __min1 : __min2; })
3507 #define max_t(type, x, y) ({ \
3508 type __max1 = (x); \
3509 type __max2 = (y); \
3510 __max1 > __max2 ? __max1 : __max2; })
3512 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
3514 int bnxt_alloc_ctx_mem(struct bnxt *bp)
3516 struct bnxt_ctx_pg_info *ctx_pg;
3517 struct bnxt_ctx_mem_info *ctx;
3518 uint32_t mem_size, ena, entries;
3521 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
3523 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
3527 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
3530 ctx_pg = &ctx->qp_mem;
3531 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
3532 mem_size = ctx->qp_entry_size * ctx_pg->entries;
3533 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
3537 ctx_pg = &ctx->srq_mem;
3538 ctx_pg->entries = ctx->srq_max_l2_entries;
3539 mem_size = ctx->srq_entry_size * ctx_pg->entries;
3540 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
3544 ctx_pg = &ctx->cq_mem;
3545 ctx_pg->entries = ctx->cq_max_l2_entries;
3546 mem_size = ctx->cq_entry_size * ctx_pg->entries;
3547 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
3551 ctx_pg = &ctx->vnic_mem;
3552 ctx_pg->entries = ctx->vnic_max_vnic_entries +
3553 ctx->vnic_max_ring_table_entries;
3554 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
3555 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
3559 ctx_pg = &ctx->stat_mem;
3560 ctx_pg->entries = ctx->stat_max_entries;
3561 mem_size = ctx->stat_entry_size * ctx_pg->entries;
3562 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
3566 entries = ctx->qp_max_l2_entries;
3567 entries = roundup(entries, ctx->tqm_entries_multiple);
3568 entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
3569 ctx->tqm_max_entries_per_ring);
3570 for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
3571 ctx_pg = ctx->tqm_mem[i];
3572 /* use min tqm entries for now. */
3573 ctx_pg->entries = entries;
3574 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
3575 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
3578 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
3581 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
3582 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
3585 "Failed to configure context mem: rc = %d\n", rc);
3587 ctx->flags |= BNXT_CTX_FLAG_INITED;
3592 #define ALLOW_FUNC(x) \
3594 typeof(x) arg = (x); \
3595 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3596 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3599 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3601 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3602 char mz_name[RTE_MEMZONE_NAMESIZE];
3603 const struct rte_memzone *mz = NULL;
3604 static int version_printed;
3605 uint32_t total_alloc_len;
3606 rte_iova_t mz_phys_addr;
3610 if (version_printed++ == 0)
3611 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
3613 rte_eth_copy_pci_info(eth_dev, pci_dev);
3615 bp = eth_dev->data->dev_private;
3617 bp->dev_stopped = 1;
3619 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3622 if (bnxt_vf_pciid(pci_dev->id.device_id))
3623 bp->flags |= BNXT_FLAG_VF;
3625 if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
3626 pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
3627 pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
3628 pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF)
3629 bp->flags |= BNXT_FLAG_THOR_CHIP;
3631 rc = bnxt_init_board(eth_dev);
3634 "Board initialization failed rc: %x\n", rc);
3638 eth_dev->dev_ops = &bnxt_dev_ops;
3639 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3640 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3641 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3644 if (pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) {
3645 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3646 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3647 pci_dev->addr.bus, pci_dev->addr.devid,
3648 pci_dev->addr.function, "rx_port_stats");
3649 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3650 mz = rte_memzone_lookup(mz_name);
3651 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3652 sizeof(struct rx_port_stats) +
3653 sizeof(struct rx_port_stats_ext) +
3656 mz = rte_memzone_reserve(mz_name, total_alloc_len,
3659 RTE_MEMZONE_SIZE_HINT_ONLY |
3660 RTE_MEMZONE_IOVA_CONTIG);
3664 memset(mz->addr, 0, mz->len);
3665 mz_phys_addr = mz->iova;
3666 if ((unsigned long)mz->addr == mz_phys_addr) {
3668 "Memzone physical address same as virtual using rte_mem_virt2iova()\n");
3669 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3670 if (mz_phys_addr == 0) {
3672 "unable to map address to physical memory\n");
3677 bp->rx_mem_zone = (const void *)mz;
3678 bp->hw_rx_port_stats = mz->addr;
3679 bp->hw_rx_port_stats_map = mz_phys_addr;
3681 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3682 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3683 pci_dev->addr.bus, pci_dev->addr.devid,
3684 pci_dev->addr.function, "tx_port_stats");
3685 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3686 mz = rte_memzone_lookup(mz_name);
3687 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3688 sizeof(struct tx_port_stats) +
3689 sizeof(struct tx_port_stats_ext) +
3692 mz = rte_memzone_reserve(mz_name,
3696 RTE_MEMZONE_SIZE_HINT_ONLY |
3697 RTE_MEMZONE_IOVA_CONTIG);
3701 memset(mz->addr, 0, mz->len);
3702 mz_phys_addr = mz->iova;
3703 if ((unsigned long)mz->addr == mz_phys_addr) {
3704 PMD_DRV_LOG(WARNING,
3705 "Memzone physical address same as virtual.\n");
3706 PMD_DRV_LOG(WARNING,
3707 "Using rte_mem_virt2iova()\n");
3708 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3709 if (mz_phys_addr == 0) {
3711 "unable to map address to physical memory\n");
3716 bp->tx_mem_zone = (const void *)mz;
3717 bp->hw_tx_port_stats = mz->addr;
3718 bp->hw_tx_port_stats_map = mz_phys_addr;
3720 bp->flags |= BNXT_FLAG_PORT_STATS;
3722 /* Display extended statistics if FW supports it */
3723 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
3724 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0)
3725 goto skip_ext_stats;
3727 bp->hw_rx_port_stats_ext = (void *)
3728 (bp->hw_rx_port_stats + sizeof(struct rx_port_stats));
3729 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
3730 sizeof(struct rx_port_stats);
3731 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
3734 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2) {
3735 bp->hw_tx_port_stats_ext = (void *)
3736 (bp->hw_tx_port_stats + sizeof(struct tx_port_stats));
3737 bp->hw_tx_port_stats_ext_map =
3738 bp->hw_tx_port_stats_map +
3739 sizeof(struct tx_port_stats);
3740 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
3745 rc = bnxt_alloc_hwrm_resources(bp);
3748 "hwrm resource allocation failure rc: %x\n", rc);
3751 rc = bnxt_hwrm_ver_get(bp);
3755 rc = bnxt_hwrm_func_reset(bp);
3757 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc);
3762 rc = bnxt_hwrm_queue_qportcfg(bp);
3764 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n");
3767 /* Get the MAX capabilities for this function */
3768 rc = bnxt_hwrm_func_qcaps(bp);
3770 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc);
3773 if (bp->max_tx_rings == 0) {
3774 PMD_DRV_LOG(ERR, "No TX rings available!\n");
3778 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3779 RTE_ETHER_ADDR_LEN * bp->max_l2_ctx, 0);
3780 if (eth_dev->data->mac_addrs == NULL) {
3782 "Failed to alloc %u bytes needed to store MAC addr tbl",
3783 RTE_ETHER_ADDR_LEN * bp->max_l2_ctx);
3788 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
3790 "Invalid MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
3791 bp->dflt_mac_addr[0], bp->dflt_mac_addr[1],
3792 bp->dflt_mac_addr[2], bp->dflt_mac_addr[3],
3793 bp->dflt_mac_addr[4], bp->dflt_mac_addr[5]);
3797 /* Copy the permanent MAC from the qcap response address now. */
3798 memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr));
3799 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
3801 /* THOR does not support ring groups.
3802 * But we will use the array to save RSS context IDs.
3804 if (BNXT_CHIP_THOR(bp)) {
3805 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
3806 } else if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3807 /* 1 ring is for default completion ring */
3808 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
3813 bp->grp_info = rte_zmalloc("bnxt_grp_info",
3814 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
3815 if (!bp->grp_info) {
3817 "Failed to alloc %zu bytes to store group info table\n",
3818 sizeof(*bp->grp_info) * bp->max_ring_grps);
3823 /* Forward all requests if firmware is new enough */
3824 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3825 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3826 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3827 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3829 PMD_DRV_LOG(WARNING,
3830 "Firmware too old for VF mailbox functionality\n");
3831 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3835 * The following are used for driver cleanup. If we disallow these,
3836 * VF drivers can't clean up cleanly.
3838 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3839 ALLOW_FUNC(HWRM_VNIC_FREE);
3840 ALLOW_FUNC(HWRM_RING_FREE);
3841 ALLOW_FUNC(HWRM_RING_GRP_FREE);
3842 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3843 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3844 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3845 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3846 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3847 rc = bnxt_hwrm_func_driver_register(bp);
3850 "Failed to register driver");
3856 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3857 pci_dev->mem_resource[0].phys_addr,
3858 pci_dev->mem_resource[0].addr);
3860 rc = bnxt_hwrm_func_qcfg(bp);
3862 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n");
3867 //if (bp->pf.active_vfs) {
3868 // TODO: Deallocate VF resources?
3870 if (bp->pdev->max_vfs) {
3871 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
3873 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
3877 rc = bnxt_hwrm_allocate_pf_only(bp);
3880 "Failed to allocate PF resources\n");
3886 bnxt_hwrm_port_led_qcaps(bp);
3888 rc = bnxt_setup_int(bp);
3892 rc = bnxt_alloc_mem(bp);
3894 goto error_free_int;
3896 rc = bnxt_request_int(bp);
3898 goto error_free_int;
3900 bnxt_enable_int(bp);
3906 bnxt_disable_int(bp);
3907 bnxt_hwrm_func_buf_unrgtr(bp);
3911 bnxt_dev_uninit(eth_dev);
3917 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
3919 struct bnxt *bp = eth_dev->data->dev_private;
3922 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3925 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
3926 bnxt_disable_int(bp);
3929 if (bp->grp_info != NULL) {
3930 rte_free(bp->grp_info);
3931 bp->grp_info = NULL;
3933 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
3934 bnxt_free_hwrm_resources(bp);
3936 if (bp->tx_mem_zone) {
3937 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
3938 bp->tx_mem_zone = NULL;
3941 if (bp->rx_mem_zone) {
3942 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
3943 bp->rx_mem_zone = NULL;
3946 if (bp->dev_stopped == 0)
3947 bnxt_dev_close_op(eth_dev);
3949 rte_free(bp->pf.vf_info);
3950 bnxt_free_ctx_mem(bp);
3951 eth_dev->dev_ops = NULL;
3952 eth_dev->rx_pkt_burst = NULL;
3953 eth_dev->tx_pkt_burst = NULL;
3958 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3959 struct rte_pci_device *pci_dev)
3961 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
3965 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
3967 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
3968 return rte_eth_dev_pci_generic_remove(pci_dev,
3971 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
3974 static struct rte_pci_driver bnxt_rte_pmd = {
3975 .id_table = bnxt_pci_id_map,
3976 .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
3977 RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_IOVA_AS_VA,
3978 .probe = bnxt_pci_probe,
3979 .remove = bnxt_pci_remove,
3983 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
3985 if (strcmp(dev->device->driver->name, drv->driver.name))
3991 bool is_bnxt_supported(struct rte_eth_dev *dev)
3993 return is_device_supported(dev, &bnxt_rte_pmd);
3996 RTE_INIT(bnxt_init_log)
3998 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
3999 if (bnxt_logtype_driver >= 0)
4000 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4003 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4004 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4005 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");