1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2021 Broadcom
10 #include <ethdev_driver.h>
11 #include <ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
15 #include <rte_kvargs.h>
19 #include "bnxt_filter.h"
20 #include "bnxt_hwrm.h"
22 #include "bnxt_reps.h"
23 #include "bnxt_ring.h"
26 #include "bnxt_stats.h"
29 #include "bnxt_vnic.h"
30 #include "hsi_struct_def_dpdk.h"
31 #include "bnxt_nvm_defs.h"
32 #include "bnxt_tf_common.h"
33 #include "ulp_flow_db.h"
34 #include "rte_pmd_bnxt.h"
36 #define DRV_MODULE_NAME "bnxt"
37 static const char bnxt_version[] =
38 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
41 * The set of PCI devices this driver supports
43 static const struct rte_pci_id bnxt_pci_id_map[] = {
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
45 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
47 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
87 { .vendor_id = 0, /* sentinel */ },
90 #define BNXT_DEVARG_TRUFLOW "host-based-truflow"
91 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat"
92 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows"
93 #define BNXT_DEVARG_REPRESENTOR "representor"
94 #define BNXT_DEVARG_REP_BASED_PF "rep-based-pf"
95 #define BNXT_DEVARG_REP_IS_PF "rep-is-pf"
96 #define BNXT_DEVARG_REP_Q_R2F "rep-q-r2f"
97 #define BNXT_DEVARG_REP_Q_F2R "rep-q-f2r"
98 #define BNXT_DEVARG_REP_FC_R2F "rep-fc-r2f"
99 #define BNXT_DEVARG_REP_FC_F2R "rep-fc-f2r"
101 static const char *const bnxt_dev_args[] = {
102 BNXT_DEVARG_REPRESENTOR,
104 BNXT_DEVARG_FLOW_XSTAT,
105 BNXT_DEVARG_MAX_NUM_KFLOWS,
106 BNXT_DEVARG_REP_BASED_PF,
107 BNXT_DEVARG_REP_IS_PF,
108 BNXT_DEVARG_REP_Q_R2F,
109 BNXT_DEVARG_REP_Q_F2R,
110 BNXT_DEVARG_REP_FC_R2F,
111 BNXT_DEVARG_REP_FC_F2R,
116 * truflow == false to disable the feature
117 * truflow == true to enable the feature
119 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1)
122 * flow_xstat == false to disable the feature
123 * flow_xstat == true to enable the feature
125 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1)
128 * rep_is_pf == false to indicate VF representor
129 * rep_is_pf == true to indicate PF representor
131 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf) ((rep_is_pf) > 1)
134 * rep_based_pf == Physical index of the PF
136 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf) ((rep_based_pf) > 15)
138 * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
140 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f) ((rep_q_r2f) > 3)
143 * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
145 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r) ((rep_q_f2r) > 3)
148 * rep_fc_r2f == Flow control for the representor to endpoint direction
150 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f) ((rep_fc_r2f) > 1)
153 * rep_fc_f2r == Flow control for the endpoint to representor direction
155 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r) ((rep_fc_f2r) > 1)
157 int bnxt_cfa_code_dynfield_offset = -1;
160 * max_num_kflows must be >= 32
161 * and must be a power-of-2 supported value
162 * return: 1 -> invalid
165 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
167 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
172 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
173 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
174 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
175 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
176 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
177 static int bnxt_restore_vlan_filters(struct bnxt *bp);
178 static void bnxt_dev_recover(void *arg);
179 static void bnxt_free_error_recovery_info(struct bnxt *bp);
180 static void bnxt_free_rep_info(struct bnxt *bp);
182 int is_bnxt_in_error(struct bnxt *bp)
184 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
186 if (bp->flags & BNXT_FLAG_FW_RESET)
192 /***********************/
195 * High level utility functions
198 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
200 unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
201 BNXT_RSS_TBL_SIZE_P5);
203 if (!BNXT_CHIP_P5(bp))
206 return RTE_ALIGN_MUL_CEIL(num_rss_rings,
207 BNXT_RSS_ENTRIES_PER_CTX_P5) /
208 BNXT_RSS_ENTRIES_PER_CTX_P5;
211 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
213 if (!BNXT_CHIP_P5(bp))
214 return HW_HASH_INDEX_SIZE;
216 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
219 static void bnxt_free_parent_info(struct bnxt *bp)
221 rte_free(bp->parent);
225 static void bnxt_free_pf_info(struct bnxt *bp)
231 static void bnxt_free_link_info(struct bnxt *bp)
233 rte_free(bp->link_info);
234 bp->link_info = NULL;
237 static void bnxt_free_leds_info(struct bnxt *bp)
246 static void bnxt_free_flow_stats_info(struct bnxt *bp)
248 rte_free(bp->flow_stat);
249 bp->flow_stat = NULL;
252 static void bnxt_free_cos_queues(struct bnxt *bp)
254 rte_free(bp->rx_cos_queue);
255 bp->rx_cos_queue = NULL;
256 rte_free(bp->tx_cos_queue);
257 bp->tx_cos_queue = NULL;
260 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
262 bnxt_free_filter_mem(bp);
263 bnxt_free_vnic_attributes(bp);
264 bnxt_free_vnic_mem(bp);
266 /* tx/rx rings are configured as part of *_queue_setup callbacks.
267 * If the number of rings change across fw update,
268 * we don't have much choice except to warn the user.
272 bnxt_free_tx_rings(bp);
273 bnxt_free_rx_rings(bp);
275 bnxt_free_async_cp_ring(bp);
276 bnxt_free_rxtx_nq_ring(bp);
278 rte_free(bp->grp_info);
282 static int bnxt_alloc_parent_info(struct bnxt *bp)
284 bp->parent = rte_zmalloc("bnxt_parent_info",
285 sizeof(struct bnxt_parent_info), 0);
286 if (bp->parent == NULL)
292 static int bnxt_alloc_pf_info(struct bnxt *bp)
294 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
301 static int bnxt_alloc_link_info(struct bnxt *bp)
304 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
305 if (bp->link_info == NULL)
311 static int bnxt_alloc_leds_info(struct bnxt *bp)
316 bp->leds = rte_zmalloc("bnxt_leds",
317 BNXT_MAX_LED * sizeof(struct bnxt_led_info),
319 if (bp->leds == NULL)
325 static int bnxt_alloc_cos_queues(struct bnxt *bp)
328 rte_zmalloc("bnxt_rx_cosq",
329 BNXT_COS_QUEUE_COUNT *
330 sizeof(struct bnxt_cos_queue_info),
332 if (bp->rx_cos_queue == NULL)
336 rte_zmalloc("bnxt_tx_cosq",
337 BNXT_COS_QUEUE_COUNT *
338 sizeof(struct bnxt_cos_queue_info),
340 if (bp->tx_cos_queue == NULL)
346 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
348 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
349 sizeof(struct bnxt_flow_stat_info), 0);
350 if (bp->flow_stat == NULL)
356 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
360 rc = bnxt_alloc_ring_grps(bp);
364 rc = bnxt_alloc_async_ring_struct(bp);
368 rc = bnxt_alloc_vnic_mem(bp);
372 rc = bnxt_alloc_vnic_attributes(bp);
376 rc = bnxt_alloc_filter_mem(bp);
380 rc = bnxt_alloc_async_cp_ring(bp);
384 rc = bnxt_alloc_rxtx_nq_ring(bp);
388 if (BNXT_FLOW_XSTATS_EN(bp)) {
389 rc = bnxt_alloc_flow_stats_info(bp);
397 bnxt_free_mem(bp, reconfig);
401 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
403 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
404 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
405 uint64_t rx_offloads = dev_conf->rxmode.offloads;
406 struct bnxt_rx_queue *rxq;
410 rc = bnxt_vnic_grp_alloc(bp, vnic);
414 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
415 vnic_id, vnic, vnic->fw_grp_ids);
417 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
421 /* Alloc RSS context only if RSS mode is enabled */
422 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
423 int j, nr_ctxs = bnxt_rss_ctxts(bp);
425 /* RSS table size in Thor is 512.
426 * Cap max Rx rings to same value
428 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
429 PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
430 bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
435 for (j = 0; j < nr_ctxs; j++) {
436 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
442 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
446 vnic->num_lb_ctxts = nr_ctxs;
450 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
451 * setting is not available at this time, it will not be
452 * configured correctly in the CFA.
454 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
455 vnic->vlan_strip = true;
457 vnic->vlan_strip = false;
459 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
463 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
467 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
468 rxq = bp->eth_dev->data->rx_queues[j];
471 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
472 j, rxq->vnic, rxq->vnic->fw_grp_ids);
474 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
475 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
477 vnic->rx_queue_cnt++;
480 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
482 rc = bnxt_vnic_rss_configure(bp, vnic);
486 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
488 rc = bnxt_hwrm_vnic_tpa_cfg(bp, vnic,
489 (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) ?
496 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
501 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
505 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
506 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
511 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
512 " rx_fc_in_tbl.ctx_id = %d\n",
513 bp->flow_stat->rx_fc_in_tbl.va,
514 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
515 bp->flow_stat->rx_fc_in_tbl.ctx_id);
517 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
518 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
523 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
524 " rx_fc_out_tbl.ctx_id = %d\n",
525 bp->flow_stat->rx_fc_out_tbl.va,
526 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
527 bp->flow_stat->rx_fc_out_tbl.ctx_id);
529 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
530 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
535 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
536 " tx_fc_in_tbl.ctx_id = %d\n",
537 bp->flow_stat->tx_fc_in_tbl.va,
538 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
539 bp->flow_stat->tx_fc_in_tbl.ctx_id);
541 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
542 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
547 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
548 " tx_fc_out_tbl.ctx_id = %d\n",
549 bp->flow_stat->tx_fc_out_tbl.va,
550 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
551 bp->flow_stat->tx_fc_out_tbl.ctx_id);
553 memset(bp->flow_stat->rx_fc_out_tbl.va,
555 bp->flow_stat->rx_fc_out_tbl.size);
556 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
557 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
558 bp->flow_stat->rx_fc_out_tbl.ctx_id,
559 bp->flow_stat->max_fc,
564 memset(bp->flow_stat->tx_fc_out_tbl.va,
566 bp->flow_stat->tx_fc_out_tbl.size);
567 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
568 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
569 bp->flow_stat->tx_fc_out_tbl.ctx_id,
570 bp->flow_stat->max_fc,
576 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
577 struct bnxt_ctx_mem_buf_info *ctx)
582 ctx->va = rte_zmalloc(type, size, 0);
585 rte_mem_lock_page(ctx->va);
587 ctx->dma = rte_mem_virt2iova(ctx->va);
588 if (ctx->dma == RTE_BAD_IOVA)
594 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
596 struct rte_pci_device *pdev = bp->pdev;
597 char type[RTE_MEMZONE_NAMESIZE];
601 max_fc = bp->flow_stat->max_fc;
603 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
604 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
605 /* 4 bytes for each counter-id */
606 rc = bnxt_alloc_ctx_mem_buf(type,
608 &bp->flow_stat->rx_fc_in_tbl);
612 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
613 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
614 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
615 rc = bnxt_alloc_ctx_mem_buf(type,
617 &bp->flow_stat->rx_fc_out_tbl);
621 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
622 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
623 /* 4 bytes for each counter-id */
624 rc = bnxt_alloc_ctx_mem_buf(type,
626 &bp->flow_stat->tx_fc_in_tbl);
630 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
631 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
632 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
633 rc = bnxt_alloc_ctx_mem_buf(type,
635 &bp->flow_stat->tx_fc_out_tbl);
639 rc = bnxt_register_fc_ctx_mem(bp);
644 static int bnxt_init_ctx_mem(struct bnxt *bp)
648 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
649 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
650 !BNXT_FLOW_XSTATS_EN(bp))
653 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
657 rc = bnxt_init_fc_ctx_mem(bp);
662 static int bnxt_update_phy_setting(struct bnxt *bp)
664 struct rte_eth_link new;
667 rc = bnxt_get_hwrm_link_config(bp, &new);
669 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
674 * On BCM957508-N2100 adapters, FW will not allow any user other
675 * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
676 * always returns link up. Force phy update always in that case.
678 if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
679 rc = bnxt_set_hwrm_link_config(bp, true);
681 PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
689 static void bnxt_free_prev_ring_stats(struct bnxt *bp)
691 rte_free(bp->prev_rx_ring_stats);
692 rte_free(bp->prev_tx_ring_stats);
694 bp->prev_rx_ring_stats = NULL;
695 bp->prev_tx_ring_stats = NULL;
698 static int bnxt_alloc_prev_ring_stats(struct bnxt *bp)
700 bp->prev_rx_ring_stats = rte_zmalloc("bnxt_prev_rx_ring_stats",
701 sizeof(struct bnxt_ring_stats) *
704 if (bp->prev_rx_ring_stats == NULL)
707 bp->prev_tx_ring_stats = rte_zmalloc("bnxt_prev_tx_ring_stats",
708 sizeof(struct bnxt_ring_stats) *
711 if (bp->prev_tx_ring_stats == NULL)
717 bnxt_free_prev_ring_stats(bp);
721 static int bnxt_start_nic(struct bnxt *bp)
723 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
724 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
725 uint32_t intr_vector = 0;
726 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
727 uint32_t vec = BNXT_MISC_VEC_ID;
731 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
732 bp->eth_dev->data->dev_conf.rxmode.offloads |=
733 DEV_RX_OFFLOAD_JUMBO_FRAME;
734 bp->flags |= BNXT_FLAG_JUMBO;
736 bp->eth_dev->data->dev_conf.rxmode.offloads &=
737 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
738 bp->flags &= ~BNXT_FLAG_JUMBO;
741 /* THOR does not support ring groups.
742 * But we will use the array to save RSS context IDs.
744 if (BNXT_CHIP_P5(bp))
745 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
747 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
749 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
753 rc = bnxt_alloc_hwrm_rings(bp);
755 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
759 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
761 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
765 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
768 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
769 if (bp->rx_cos_queue[i].id != 0xff) {
770 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
774 "Num pools more than FW profile\n");
778 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
784 rc = bnxt_mq_rx_configure(bp);
786 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
791 rc = bnxt_setup_one_vnic(bp, 0);
794 /* VNIC configuration */
795 if (BNXT_RFS_NEEDS_VNIC(bp)) {
796 for (i = 1; i < bp->nr_vnics; i++) {
797 rc = bnxt_setup_one_vnic(bp, i);
803 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
806 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
810 /* check and configure queue intr-vector mapping */
811 if ((rte_intr_cap_multiple(intr_handle) ||
812 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
813 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
814 intr_vector = bp->eth_dev->data->nb_rx_queues;
815 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
816 if (intr_vector > bp->rx_cp_nr_rings) {
817 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
821 rc = rte_intr_efd_enable(intr_handle, intr_vector);
826 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
827 intr_handle->intr_vec =
828 rte_zmalloc("intr_vec",
829 bp->eth_dev->data->nb_rx_queues *
831 if (intr_handle->intr_vec == NULL) {
832 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
833 " intr_vec", bp->eth_dev->data->nb_rx_queues);
837 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
838 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
839 intr_handle->intr_vec, intr_handle->nb_efd,
840 intr_handle->max_intr);
841 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
843 intr_handle->intr_vec[queue_id] =
844 vec + BNXT_RX_VEC_START;
845 if (vec < base + intr_handle->nb_efd - 1)
850 /* enable uio/vfio intr/eventfd mapping */
851 rc = rte_intr_enable(intr_handle);
852 #ifndef RTE_EXEC_ENV_FREEBSD
853 /* In FreeBSD OS, nic_uio driver does not support interrupts */
858 rc = bnxt_update_phy_setting(bp);
862 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
864 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
869 /* Some of the error status returned by FW may not be from errno.h */
876 static int bnxt_shutdown_nic(struct bnxt *bp)
878 bnxt_free_all_hwrm_resources(bp);
879 bnxt_free_all_filters(bp);
880 bnxt_free_all_vnics(bp);
885 * Device configuration and status function
888 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
890 uint32_t link_speed = 0;
891 uint32_t speed_capa = 0;
893 if (bp->link_info == NULL)
896 link_speed = bp->link_info->support_speeds;
898 /* If PAM4 is configured, use PAM4 supported speed */
899 if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
900 link_speed = bp->link_info->support_pam4_speeds;
902 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
903 speed_capa |= ETH_LINK_SPEED_100M;
904 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
905 speed_capa |= ETH_LINK_SPEED_100M_HD;
906 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
907 speed_capa |= ETH_LINK_SPEED_1G;
908 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
909 speed_capa |= ETH_LINK_SPEED_2_5G;
910 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
911 speed_capa |= ETH_LINK_SPEED_10G;
912 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
913 speed_capa |= ETH_LINK_SPEED_20G;
914 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
915 speed_capa |= ETH_LINK_SPEED_25G;
916 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
917 speed_capa |= ETH_LINK_SPEED_40G;
918 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
919 speed_capa |= ETH_LINK_SPEED_50G;
920 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
921 speed_capa |= ETH_LINK_SPEED_100G;
922 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
923 speed_capa |= ETH_LINK_SPEED_50G;
924 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
925 speed_capa |= ETH_LINK_SPEED_100G;
926 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
927 speed_capa |= ETH_LINK_SPEED_200G;
929 if (bp->link_info->auto_mode ==
930 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
931 speed_capa |= ETH_LINK_SPEED_FIXED;
936 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
937 struct rte_eth_dev_info *dev_info)
939 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
940 struct bnxt *bp = eth_dev->data->dev_private;
941 uint16_t max_vnics, i, j, vpool, vrxq;
942 unsigned int max_rx_rings;
945 rc = is_bnxt_in_error(bp);
950 dev_info->max_mac_addrs = bp->max_l2_ctx;
951 dev_info->max_hash_mac_addrs = 0;
953 /* PF/VF specifics */
955 dev_info->max_vfs = pdev->max_vfs;
957 max_rx_rings = bnxt_max_rings(bp);
958 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
959 dev_info->max_rx_queues = max_rx_rings;
960 dev_info->max_tx_queues = max_rx_rings;
961 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
962 dev_info->hash_key_size = 40;
963 max_vnics = bp->max_vnics;
966 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
967 dev_info->max_mtu = BNXT_MAX_MTU;
969 /* Fast path specifics */
970 dev_info->min_rx_bufsize = 1;
971 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
973 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
974 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
975 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
976 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
977 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
978 dev_info->tx_queue_offload_capa;
979 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
981 dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
983 dev_info->default_rxconf = (struct rte_eth_rxconf) {
989 .rx_free_thresh = 32,
990 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
993 dev_info->default_txconf = (struct rte_eth_txconf) {
999 .tx_free_thresh = 32,
1002 eth_dev->data->dev_conf.intr_conf.lsc = 1;
1004 eth_dev->data->dev_conf.intr_conf.rxq = 1;
1005 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
1006 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
1007 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
1008 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
1010 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
1011 dev_info->switch_info.name = eth_dev->device->name;
1012 dev_info->switch_info.domain_id = bp->switch_domain_id;
1013 dev_info->switch_info.port_id =
1014 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
1015 BNXT_SWITCH_PORT_ID_TRUSTED_VF;
1019 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
1020 * need further investigation.
1023 /* VMDq resources */
1024 vpool = 64; /* ETH_64_POOLS */
1025 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
1026 for (i = 0; i < 4; vpool >>= 1, i++) {
1027 if (max_vnics > vpool) {
1028 for (j = 0; j < 5; vrxq >>= 1, j++) {
1029 if (dev_info->max_rx_queues > vrxq) {
1035 /* Not enough resources to support VMDq */
1039 /* Not enough resources to support VMDq */
1043 dev_info->max_vmdq_pools = vpool;
1044 dev_info->vmdq_queue_num = vrxq;
1046 dev_info->vmdq_pool_base = 0;
1047 dev_info->vmdq_queue_base = 0;
1052 /* Configure the device based on the configuration provided */
1053 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1055 struct bnxt *bp = eth_dev->data->dev_private;
1056 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1059 bp->rx_queues = (void *)eth_dev->data->rx_queues;
1060 bp->tx_queues = (void *)eth_dev->data->tx_queues;
1061 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1062 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1064 rc = is_bnxt_in_error(bp);
1068 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1069 rc = bnxt_hwrm_check_vf_rings(bp);
1071 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1075 /* If a resource has already been allocated - in this case
1076 * it is the async completion ring, free it. Reallocate it after
1077 * resource reservation. This will ensure the resource counts
1078 * are calculated correctly.
1081 pthread_mutex_lock(&bp->def_cp_lock);
1083 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1084 bnxt_disable_int(bp);
1085 bnxt_free_cp_ring(bp, bp->async_cp_ring);
1088 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1090 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1091 pthread_mutex_unlock(&bp->def_cp_lock);
1095 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1096 rc = bnxt_alloc_async_cp_ring(bp);
1098 pthread_mutex_unlock(&bp->def_cp_lock);
1101 bnxt_enable_int(bp);
1104 pthread_mutex_unlock(&bp->def_cp_lock);
1107 /* Inherit new configurations */
1108 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1109 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1110 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1111 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1112 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1114 goto resource_error;
1116 if (BNXT_HAS_RING_GRPS(bp) &&
1117 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1118 goto resource_error;
1120 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1121 bp->max_vnics < eth_dev->data->nb_rx_queues)
1122 goto resource_error;
1124 bp->rx_cp_nr_rings = bp->rx_nr_rings;
1125 bp->tx_cp_nr_rings = bp->tx_nr_rings;
1127 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1128 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1129 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1131 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1132 eth_dev->data->mtu =
1133 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1134 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1136 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1142 "Insufficient resources to support requested config\n");
1144 "Num Queues Requested: Tx %d, Rx %d\n",
1145 eth_dev->data->nb_tx_queues,
1146 eth_dev->data->nb_rx_queues);
1148 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1149 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1150 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1154 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1156 struct rte_eth_link *link = ð_dev->data->dev_link;
1158 if (link->link_status)
1159 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1160 eth_dev->data->port_id,
1161 (uint32_t)link->link_speed,
1162 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1163 ("full-duplex") : ("half-duplex\n"));
1165 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1166 eth_dev->data->port_id);
1170 * Determine whether the current configuration requires support for scattered
1171 * receive; return 1 if scattered receive is required and 0 if not.
1173 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1178 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1181 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO)
1184 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1185 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1187 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1188 RTE_PKTMBUF_HEADROOM);
1189 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1195 static eth_rx_burst_t
1196 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1198 struct bnxt *bp = eth_dev->data->dev_private;
1200 /* Disable vector mode RX for Stingray2 for now */
1201 if (BNXT_CHIP_SR2(bp)) {
1202 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1203 return bnxt_recv_pkts;
1206 #if (defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)) && \
1207 !defined(RTE_LIBRTE_IEEE1588)
1209 /* Vector mode receive cannot be enabled if scattered rx is in use. */
1210 if (eth_dev->data->scattered_rx)
1214 * Vector mode receive cannot be enabled if Truflow is enabled or if
1215 * asynchronous completions and receive completions can be placed in
1216 * the same completion ring.
1218 if (BNXT_TRUFLOW_EN(bp) || !BNXT_NUM_ASYNC_CPR(bp))
1222 * Vector mode receive cannot be enabled if any receive offloads outside
1223 * a limited subset have been enabled.
1225 if (eth_dev->data->dev_conf.rxmode.offloads &
1226 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1227 DEV_RX_OFFLOAD_KEEP_CRC |
1228 DEV_RX_OFFLOAD_JUMBO_FRAME |
1229 DEV_RX_OFFLOAD_IPV4_CKSUM |
1230 DEV_RX_OFFLOAD_UDP_CKSUM |
1231 DEV_RX_OFFLOAD_TCP_CKSUM |
1232 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1233 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1234 DEV_RX_OFFLOAD_RSS_HASH |
1235 DEV_RX_OFFLOAD_VLAN_FILTER))
1238 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1239 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1240 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1242 "Using AVX2 vector mode receive for port %d\n",
1243 eth_dev->data->port_id);
1244 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1245 return bnxt_recv_pkts_vec_avx2;
1248 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1250 "Using SSE vector mode receive for port %d\n",
1251 eth_dev->data->port_id);
1252 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1253 return bnxt_recv_pkts_vec;
1257 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1258 eth_dev->data->port_id);
1260 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1261 eth_dev->data->port_id,
1262 eth_dev->data->scattered_rx,
1263 eth_dev->data->dev_conf.rxmode.offloads);
1265 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1266 return bnxt_recv_pkts;
1269 static eth_tx_burst_t
1270 bnxt_transmit_function(struct rte_eth_dev *eth_dev)
1272 struct bnxt *bp = eth_dev->data->dev_private;
1274 /* Disable vector mode TX for Stingray2 for now */
1275 if (BNXT_CHIP_SR2(bp))
1276 return bnxt_xmit_pkts;
1278 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) && \
1279 !defined(RTE_LIBRTE_IEEE1588)
1280 uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1283 * Vector mode transmit can be enabled only if not using scatter rx
1286 if (eth_dev->data->scattered_rx ||
1287 (offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) ||
1288 BNXT_TRUFLOW_EN(bp))
1291 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1292 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1293 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1295 "Using AVX2 vector mode transmit for port %d\n",
1296 eth_dev->data->port_id);
1297 return bnxt_xmit_pkts_vec_avx2;
1300 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1302 "Using SSE vector mode transmit for port %d\n",
1303 eth_dev->data->port_id);
1304 return bnxt_xmit_pkts_vec;
1308 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1309 eth_dev->data->port_id);
1311 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1312 eth_dev->data->port_id,
1313 eth_dev->data->scattered_rx,
1316 return bnxt_xmit_pkts;
1319 static int bnxt_handle_if_change_status(struct bnxt *bp)
1323 /* Since fw has undergone a reset and lost all contexts,
1324 * set fatal flag to not issue hwrm during cleanup
1326 bp->flags |= BNXT_FLAG_FATAL_ERROR;
1327 bnxt_uninit_resources(bp, true);
1329 /* clear fatal flag so that re-init happens */
1330 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1331 rc = bnxt_init_resources(bp, true);
1333 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1338 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1340 struct bnxt *bp = eth_dev->data->dev_private;
1343 if (!BNXT_SINGLE_PF(bp))
1346 if (!bp->link_info->link_up)
1347 rc = bnxt_set_hwrm_link_config(bp, true);
1349 eth_dev->data->dev_link.link_status = 1;
1351 bnxt_print_link_info(eth_dev);
1355 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1357 struct bnxt *bp = eth_dev->data->dev_private;
1359 if (!BNXT_SINGLE_PF(bp))
1362 eth_dev->data->dev_link.link_status = 0;
1363 bnxt_set_hwrm_link_config(bp, false);
1364 bp->link_info->link_up = 0;
1369 static void bnxt_free_switch_domain(struct bnxt *bp)
1373 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)))
1376 rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1378 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1379 bp->switch_domain_id, rc);
1382 static void bnxt_ptp_get_current_time(void *arg)
1384 struct bnxt *bp = arg;
1385 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1388 rc = is_bnxt_in_error(bp);
1395 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1396 &ptp->current_time);
1398 rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1400 PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n");
1401 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1405 static int bnxt_schedule_ptp_alarm(struct bnxt *bp)
1407 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1410 if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED)
1413 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1414 &ptp->current_time);
1416 rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1420 static void bnxt_cancel_ptp_alarm(struct bnxt *bp)
1422 if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) {
1423 rte_eal_alarm_cancel(bnxt_ptp_get_current_time, (void *)bp);
1424 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1428 static void bnxt_ptp_stop(struct bnxt *bp)
1430 bnxt_cancel_ptp_alarm(bp);
1431 bp->flags2 &= ~BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1434 static int bnxt_ptp_start(struct bnxt *bp)
1438 rc = bnxt_schedule_ptp_alarm(bp);
1440 PMD_DRV_LOG(ERR, "Failed to schedule PTP alarm\n");
1442 bp->flags2 |= BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1443 bp->flags2 |= BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1449 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev)
1451 struct bnxt *bp = eth_dev->data->dev_private;
1452 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1453 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1454 struct rte_eth_link link;
1457 eth_dev->data->dev_started = 0;
1458 eth_dev->data->scattered_rx = 0;
1460 /* Prevent crashes when queues are still in use */
1461 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1462 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1464 bnxt_disable_int(bp);
1466 /* disable uio/vfio intr/eventfd mapping */
1467 rte_intr_disable(intr_handle);
1469 /* Stop the child representors for this device */
1470 ret = bnxt_rep_stop_all(bp);
1474 /* delete the bnxt ULP port details */
1475 bnxt_ulp_port_deinit(bp);
1477 bnxt_cancel_fw_health_check(bp);
1479 if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1480 bnxt_cancel_ptp_alarm(bp);
1482 /* Do not bring link down during reset recovery */
1483 if (!is_bnxt_in_error(bp)) {
1484 bnxt_dev_set_link_down_op(eth_dev);
1485 /* Wait for link to be reset */
1486 if (BNXT_SINGLE_PF(bp))
1488 /* clear the recorded link status */
1489 memset(&link, 0, sizeof(link));
1490 rte_eth_linkstatus_set(eth_dev, &link);
1493 /* Clean queue intr-vector mapping */
1494 rte_intr_efd_disable(intr_handle);
1495 if (intr_handle->intr_vec != NULL) {
1496 rte_free(intr_handle->intr_vec);
1497 intr_handle->intr_vec = NULL;
1500 bnxt_hwrm_port_clr_stats(bp);
1501 bnxt_free_tx_mbufs(bp);
1502 bnxt_free_rx_mbufs(bp);
1503 /* Process any remaining notifications in default completion queue */
1504 bnxt_int_handler(eth_dev);
1505 bnxt_shutdown_nic(bp);
1506 bnxt_hwrm_if_change(bp, false);
1508 bnxt_free_prev_ring_stats(bp);
1509 rte_free(bp->mark_table);
1510 bp->mark_table = NULL;
1512 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1513 bp->rx_cosq_cnt = 0;
1514 /* All filters are deleted on a port stop. */
1515 if (BNXT_FLOW_XSTATS_EN(bp))
1516 bp->flow_stat->flow_count = 0;
1521 /* Unload the driver, release resources */
1522 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1524 struct bnxt *bp = eth_dev->data->dev_private;
1526 pthread_mutex_lock(&bp->err_recovery_lock);
1527 if (bp->flags & BNXT_FLAG_FW_RESET) {
1529 "Adapter recovering from error..Please retry\n");
1530 pthread_mutex_unlock(&bp->err_recovery_lock);
1533 pthread_mutex_unlock(&bp->err_recovery_lock);
1535 return bnxt_dev_stop(eth_dev);
1538 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1540 struct bnxt *bp = eth_dev->data->dev_private;
1541 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1543 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1545 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1546 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1550 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1552 "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1553 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1556 rc = bnxt_hwrm_if_change(bp, true);
1557 if (rc == 0 || rc != -EAGAIN)
1560 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1561 } while (retry_cnt--);
1566 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1567 rc = bnxt_handle_if_change_status(bp);
1572 bnxt_enable_int(bp);
1574 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1576 rc = bnxt_start_nic(bp);
1580 rc = bnxt_alloc_prev_ring_stats(bp);
1584 eth_dev->data->dev_started = 1;
1586 bnxt_link_update_op(eth_dev, 1);
1588 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1589 vlan_mask |= ETH_VLAN_FILTER_MASK;
1590 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1591 vlan_mask |= ETH_VLAN_STRIP_MASK;
1592 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1596 /* Initialize bnxt ULP port details */
1597 rc = bnxt_ulp_port_init(bp);
1601 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1602 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1604 bnxt_schedule_fw_health_check(bp);
1606 if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1607 bnxt_schedule_ptp_alarm(bp);
1612 bnxt_dev_stop(eth_dev);
1617 bnxt_uninit_locks(struct bnxt *bp)
1619 pthread_mutex_destroy(&bp->flow_lock);
1620 pthread_mutex_destroy(&bp->def_cp_lock);
1621 pthread_mutex_destroy(&bp->health_check_lock);
1622 pthread_mutex_destroy(&bp->err_recovery_lock);
1624 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
1625 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
1629 static void bnxt_drv_uninit(struct bnxt *bp)
1631 bnxt_free_leds_info(bp);
1632 bnxt_free_cos_queues(bp);
1633 bnxt_free_link_info(bp);
1634 bnxt_free_parent_info(bp);
1635 bnxt_uninit_locks(bp);
1637 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1638 bp->tx_mem_zone = NULL;
1639 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1640 bp->rx_mem_zone = NULL;
1642 bnxt_free_vf_info(bp);
1643 bnxt_free_pf_info(bp);
1645 rte_free(bp->grp_info);
1646 bp->grp_info = NULL;
1649 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1651 struct bnxt *bp = eth_dev->data->dev_private;
1654 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1657 pthread_mutex_lock(&bp->err_recovery_lock);
1658 if (bp->flags & BNXT_FLAG_FW_RESET) {
1660 "Adapter recovering from error...Please retry\n");
1661 pthread_mutex_unlock(&bp->err_recovery_lock);
1664 pthread_mutex_unlock(&bp->err_recovery_lock);
1666 /* cancel the recovery handler before remove dev */
1667 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1668 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1669 bnxt_cancel_fc_thread(bp);
1671 if (eth_dev->data->dev_started)
1672 ret = bnxt_dev_stop(eth_dev);
1674 bnxt_uninit_resources(bp, false);
1676 bnxt_drv_uninit(bp);
1681 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1684 struct bnxt *bp = eth_dev->data->dev_private;
1685 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1686 struct bnxt_vnic_info *vnic;
1687 struct bnxt_filter_info *filter, *temp_filter;
1690 if (is_bnxt_in_error(bp))
1694 * Loop through all VNICs from the specified filter flow pools to
1695 * remove the corresponding MAC addr filter
1697 for (i = 0; i < bp->nr_vnics; i++) {
1698 if (!(pool_mask & (1ULL << i)))
1701 vnic = &bp->vnic_info[i];
1702 filter = STAILQ_FIRST(&vnic->filter);
1704 temp_filter = STAILQ_NEXT(filter, next);
1705 if (filter->mac_index == index) {
1706 STAILQ_REMOVE(&vnic->filter, filter,
1707 bnxt_filter_info, next);
1708 bnxt_hwrm_clear_l2_filter(bp, filter);
1709 bnxt_free_filter(bp, filter);
1711 filter = temp_filter;
1716 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1717 struct rte_ether_addr *mac_addr, uint32_t index,
1720 struct bnxt_filter_info *filter;
1723 /* Attach requested MAC address to the new l2_filter */
1724 STAILQ_FOREACH(filter, &vnic->filter, next) {
1725 if (filter->mac_index == index) {
1727 "MAC addr already existed for pool %d\n",
1733 filter = bnxt_alloc_filter(bp);
1735 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1739 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1740 * if the MAC that's been programmed now is a different one, then,
1741 * copy that addr to filter->l2_addr
1744 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1745 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1747 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1749 filter->mac_index = index;
1750 if (filter->mac_index == 0)
1751 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1753 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1755 bnxt_free_filter(bp, filter);
1761 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1762 struct rte_ether_addr *mac_addr,
1763 uint32_t index, uint32_t pool)
1765 struct bnxt *bp = eth_dev->data->dev_private;
1766 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1769 rc = is_bnxt_in_error(bp);
1773 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1774 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1779 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1783 /* Filter settings will get applied when port is started */
1784 if (!eth_dev->data->dev_started)
1787 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1792 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1795 struct bnxt *bp = eth_dev->data->dev_private;
1796 struct rte_eth_link new;
1797 int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1798 BNXT_MIN_LINK_WAIT_CNT;
1800 rc = is_bnxt_in_error(bp);
1804 memset(&new, 0, sizeof(new));
1806 if (bp->link_info == NULL)
1810 /* Retrieve link info from hardware */
1811 rc = bnxt_get_hwrm_link_config(bp, &new);
1813 new.link_speed = ETH_LINK_SPEED_100M;
1814 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1816 "Failed to retrieve link rc = 0x%x!\n", rc);
1820 if (!wait_to_complete || new.link_status)
1823 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1826 /* Only single function PF can bring phy down.
1827 * When port is stopped, report link down for VF/MH/NPAR functions.
1829 if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1830 memset(&new, 0, sizeof(new));
1833 /* Timed out or success */
1834 if (new.link_status != eth_dev->data->dev_link.link_status ||
1835 new.link_speed != eth_dev->data->dev_link.link_speed) {
1836 rte_eth_linkstatus_set(eth_dev, &new);
1838 rte_eth_dev_callback_process(eth_dev,
1839 RTE_ETH_EVENT_INTR_LSC,
1842 bnxt_print_link_info(eth_dev);
1848 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1850 struct bnxt *bp = eth_dev->data->dev_private;
1851 struct bnxt_vnic_info *vnic;
1855 rc = is_bnxt_in_error(bp);
1859 /* Filter settings will get applied when port is started */
1860 if (!eth_dev->data->dev_started)
1863 if (bp->vnic_info == NULL)
1866 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1868 old_flags = vnic->flags;
1869 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1870 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1872 vnic->flags = old_flags;
1877 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1879 struct bnxt *bp = eth_dev->data->dev_private;
1880 struct bnxt_vnic_info *vnic;
1884 rc = is_bnxt_in_error(bp);
1888 /* Filter settings will get applied when port is started */
1889 if (!eth_dev->data->dev_started)
1892 if (bp->vnic_info == NULL)
1895 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1897 old_flags = vnic->flags;
1898 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1899 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1901 vnic->flags = old_flags;
1906 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1908 struct bnxt *bp = eth_dev->data->dev_private;
1909 struct bnxt_vnic_info *vnic;
1913 rc = is_bnxt_in_error(bp);
1917 /* Filter settings will get applied when port is started */
1918 if (!eth_dev->data->dev_started)
1921 if (bp->vnic_info == NULL)
1924 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1926 old_flags = vnic->flags;
1927 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1928 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1930 vnic->flags = old_flags;
1935 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1937 struct bnxt *bp = eth_dev->data->dev_private;
1938 struct bnxt_vnic_info *vnic;
1942 rc = is_bnxt_in_error(bp);
1946 /* Filter settings will get applied when port is started */
1947 if (!eth_dev->data->dev_started)
1950 if (bp->vnic_info == NULL)
1953 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1955 old_flags = vnic->flags;
1956 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1957 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1959 vnic->flags = old_flags;
1964 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1965 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1967 if (qid >= bp->rx_nr_rings)
1970 return bp->eth_dev->data->rx_queues[qid];
1973 /* Return rxq corresponding to a given rss table ring/group ID. */
1974 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1976 struct bnxt_rx_queue *rxq;
1979 if (!BNXT_HAS_RING_GRPS(bp)) {
1980 for (i = 0; i < bp->rx_nr_rings; i++) {
1981 rxq = bp->eth_dev->data->rx_queues[i];
1982 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1986 for (i = 0; i < bp->rx_nr_rings; i++) {
1987 if (bp->grp_info[i].fw_grp_id == fwr)
1992 return INVALID_HW_RING_ID;
1995 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1996 struct rte_eth_rss_reta_entry64 *reta_conf,
1999 struct bnxt *bp = eth_dev->data->dev_private;
2000 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2001 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2002 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
2006 rc = is_bnxt_in_error(bp);
2010 if (!vnic->rss_table)
2013 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
2016 if (reta_size != tbl_size) {
2017 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2018 "(%d) must equal the size supported by the hardware "
2019 "(%d)\n", reta_size, tbl_size);
2023 for (i = 0; i < reta_size; i++) {
2024 struct bnxt_rx_queue *rxq;
2026 idx = i / RTE_RETA_GROUP_SIZE;
2027 sft = i % RTE_RETA_GROUP_SIZE;
2029 if (!(reta_conf[idx].mask & (1ULL << sft)))
2032 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
2034 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
2038 if (BNXT_CHIP_P5(bp)) {
2039 vnic->rss_table[i * 2] =
2040 rxq->rx_ring->rx_ring_struct->fw_ring_id;
2041 vnic->rss_table[i * 2 + 1] =
2042 rxq->cp_ring->cp_ring_struct->fw_ring_id;
2044 vnic->rss_table[i] =
2045 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
2049 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2053 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
2054 struct rte_eth_rss_reta_entry64 *reta_conf,
2057 struct bnxt *bp = eth_dev->data->dev_private;
2058 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2059 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
2060 uint16_t idx, sft, i;
2063 rc = is_bnxt_in_error(bp);
2067 /* Retrieve from the default VNIC */
2070 if (!vnic->rss_table)
2073 if (reta_size != tbl_size) {
2074 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2075 "(%d) must equal the size supported by the hardware "
2076 "(%d)\n", reta_size, tbl_size);
2080 for (idx = 0, i = 0; i < reta_size; i++) {
2081 idx = i / RTE_RETA_GROUP_SIZE;
2082 sft = i % RTE_RETA_GROUP_SIZE;
2084 if (reta_conf[idx].mask & (1ULL << sft)) {
2087 if (BNXT_CHIP_P5(bp))
2088 qid = bnxt_rss_to_qid(bp,
2089 vnic->rss_table[i * 2]);
2091 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
2093 if (qid == INVALID_HW_RING_ID) {
2094 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
2097 reta_conf[idx].reta[sft] = qid;
2104 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
2105 struct rte_eth_rss_conf *rss_conf)
2107 struct bnxt *bp = eth_dev->data->dev_private;
2108 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2109 struct bnxt_vnic_info *vnic;
2112 rc = is_bnxt_in_error(bp);
2117 * If RSS enablement were different than dev_configure,
2118 * then return -EINVAL
2120 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
2121 if (!rss_conf->rss_hf)
2122 PMD_DRV_LOG(ERR, "Hash type NONE\n");
2124 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
2128 bp->flags |= BNXT_FLAG_UPDATE_HASH;
2129 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf,
2133 /* Update the default RSS VNIC(s) */
2134 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2135 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
2137 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
2138 ETH_RSS_LEVEL(rss_conf->rss_hf));
2141 * If hashkey is not specified, use the previously configured
2144 if (!rss_conf->rss_key)
2147 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
2149 "Invalid hashkey length, should be 16 bytes\n");
2152 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
2155 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2159 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
2160 struct rte_eth_rss_conf *rss_conf)
2162 struct bnxt *bp = eth_dev->data->dev_private;
2163 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2165 uint32_t hash_types;
2167 rc = is_bnxt_in_error(bp);
2171 /* RSS configuration is the same for all VNICs */
2172 if (vnic && vnic->rss_hash_key) {
2173 if (rss_conf->rss_key) {
2174 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
2175 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
2176 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
2179 hash_types = vnic->hash_type;
2180 rss_conf->rss_hf = 0;
2181 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
2182 rss_conf->rss_hf |= ETH_RSS_IPV4;
2183 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
2185 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
2186 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2188 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
2190 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
2191 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2193 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
2195 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
2196 rss_conf->rss_hf |= ETH_RSS_IPV6;
2197 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
2199 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
2200 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2202 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
2204 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
2205 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2207 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2211 bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2215 "Unknown RSS config from firmware (%08x), RSS disabled",
2220 rss_conf->rss_hf = 0;
2225 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2226 struct rte_eth_fc_conf *fc_conf)
2228 struct bnxt *bp = dev->data->dev_private;
2229 struct rte_eth_link link_info;
2232 rc = is_bnxt_in_error(bp);
2236 rc = bnxt_get_hwrm_link_config(bp, &link_info);
2240 memset(fc_conf, 0, sizeof(*fc_conf));
2241 if (bp->link_info->auto_pause)
2242 fc_conf->autoneg = 1;
2243 switch (bp->link_info->pause) {
2245 fc_conf->mode = RTE_FC_NONE;
2247 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2248 fc_conf->mode = RTE_FC_TX_PAUSE;
2250 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2251 fc_conf->mode = RTE_FC_RX_PAUSE;
2253 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2254 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2255 fc_conf->mode = RTE_FC_FULL;
2261 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2262 struct rte_eth_fc_conf *fc_conf)
2264 struct bnxt *bp = dev->data->dev_private;
2267 rc = is_bnxt_in_error(bp);
2271 if (!BNXT_SINGLE_PF(bp)) {
2273 "Flow Control Settings cannot be modified on VF or on shared PF\n");
2277 switch (fc_conf->mode) {
2279 bp->link_info->auto_pause = 0;
2280 bp->link_info->force_pause = 0;
2282 case RTE_FC_RX_PAUSE:
2283 if (fc_conf->autoneg) {
2284 bp->link_info->auto_pause =
2285 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2286 bp->link_info->force_pause = 0;
2288 bp->link_info->auto_pause = 0;
2289 bp->link_info->force_pause =
2290 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2293 case RTE_FC_TX_PAUSE:
2294 if (fc_conf->autoneg) {
2295 bp->link_info->auto_pause =
2296 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2297 bp->link_info->force_pause = 0;
2299 bp->link_info->auto_pause = 0;
2300 bp->link_info->force_pause =
2301 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2305 if (fc_conf->autoneg) {
2306 bp->link_info->auto_pause =
2307 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2308 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2309 bp->link_info->force_pause = 0;
2311 bp->link_info->auto_pause = 0;
2312 bp->link_info->force_pause =
2313 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2314 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2318 return bnxt_set_hwrm_link_config(bp, true);
2321 /* Add UDP tunneling port */
2323 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2324 struct rte_eth_udp_tunnel *udp_tunnel)
2326 struct bnxt *bp = eth_dev->data->dev_private;
2327 uint16_t tunnel_type = 0;
2330 rc = is_bnxt_in_error(bp);
2334 switch (udp_tunnel->prot_type) {
2335 case RTE_TUNNEL_TYPE_VXLAN:
2336 if (bp->vxlan_port_cnt) {
2337 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2338 udp_tunnel->udp_port);
2339 if (bp->vxlan_port != udp_tunnel->udp_port) {
2340 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2343 bp->vxlan_port_cnt++;
2347 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2348 bp->vxlan_port_cnt++;
2350 case RTE_TUNNEL_TYPE_GENEVE:
2351 if (bp->geneve_port_cnt) {
2352 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2353 udp_tunnel->udp_port);
2354 if (bp->geneve_port != udp_tunnel->udp_port) {
2355 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2358 bp->geneve_port_cnt++;
2362 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2363 bp->geneve_port_cnt++;
2366 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2369 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2375 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2376 struct rte_eth_udp_tunnel *udp_tunnel)
2378 struct bnxt *bp = eth_dev->data->dev_private;
2379 uint16_t tunnel_type = 0;
2383 rc = is_bnxt_in_error(bp);
2387 switch (udp_tunnel->prot_type) {
2388 case RTE_TUNNEL_TYPE_VXLAN:
2389 if (!bp->vxlan_port_cnt) {
2390 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2393 if (bp->vxlan_port != udp_tunnel->udp_port) {
2394 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2395 udp_tunnel->udp_port, bp->vxlan_port);
2398 if (--bp->vxlan_port_cnt)
2402 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2403 port = bp->vxlan_fw_dst_port_id;
2405 case RTE_TUNNEL_TYPE_GENEVE:
2406 if (!bp->geneve_port_cnt) {
2407 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2410 if (bp->geneve_port != udp_tunnel->udp_port) {
2411 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2412 udp_tunnel->udp_port, bp->geneve_port);
2415 if (--bp->geneve_port_cnt)
2419 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2420 port = bp->geneve_fw_dst_port_id;
2423 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2427 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2431 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2433 struct bnxt_filter_info *filter;
2434 struct bnxt_vnic_info *vnic;
2436 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2438 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2439 filter = STAILQ_FIRST(&vnic->filter);
2441 /* Search for this matching MAC+VLAN filter */
2442 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2443 /* Delete the filter */
2444 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2447 STAILQ_REMOVE(&vnic->filter, filter,
2448 bnxt_filter_info, next);
2449 bnxt_free_filter(bp, filter);
2451 "Deleted vlan filter for %d\n",
2455 filter = STAILQ_NEXT(filter, next);
2460 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2462 struct bnxt_filter_info *filter;
2463 struct bnxt_vnic_info *vnic;
2465 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2466 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2467 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2469 /* Implementation notes on the use of VNIC in this command:
2471 * By default, these filters belong to default vnic for the function.
2472 * Once these filters are set up, only destination VNIC can be modified.
2473 * If the destination VNIC is not specified in this command,
2474 * then the HWRM shall only create an l2 context id.
2477 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2478 filter = STAILQ_FIRST(&vnic->filter);
2479 /* Check if the VLAN has already been added */
2481 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2484 filter = STAILQ_NEXT(filter, next);
2487 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2488 * command to create MAC+VLAN filter with the right flags, enables set.
2490 filter = bnxt_alloc_filter(bp);
2493 "MAC/VLAN filter alloc failed\n");
2496 /* MAC + VLAN ID filter */
2497 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2498 * untagged packets are received
2500 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2501 * packets and only the programmed vlan's packets are received
2503 filter->l2_ivlan = vlan_id;
2504 filter->l2_ivlan_mask = 0x0FFF;
2505 filter->enables |= en;
2506 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2508 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2510 /* Free the newly allocated filter as we were
2511 * not able to create the filter in hardware.
2513 bnxt_free_filter(bp, filter);
2517 filter->mac_index = 0;
2518 /* Add this new filter to the list */
2520 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2522 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2525 "Added Vlan filter for %d\n", vlan_id);
2529 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2530 uint16_t vlan_id, int on)
2532 struct bnxt *bp = eth_dev->data->dev_private;
2535 rc = is_bnxt_in_error(bp);
2539 if (!eth_dev->data->dev_started) {
2540 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2544 /* These operations apply to ALL existing MAC/VLAN filters */
2546 return bnxt_add_vlan_filter(bp, vlan_id);
2548 return bnxt_del_vlan_filter(bp, vlan_id);
2551 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2552 struct bnxt_vnic_info *vnic)
2554 struct bnxt_filter_info *filter;
2557 filter = STAILQ_FIRST(&vnic->filter);
2559 if (filter->mac_index == 0 &&
2560 !memcmp(filter->l2_addr, bp->mac_addr,
2561 RTE_ETHER_ADDR_LEN)) {
2562 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2564 STAILQ_REMOVE(&vnic->filter, filter,
2565 bnxt_filter_info, next);
2566 bnxt_free_filter(bp, filter);
2570 filter = STAILQ_NEXT(filter, next);
2576 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2578 struct bnxt_vnic_info *vnic;
2582 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2583 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2584 /* Remove any VLAN filters programmed */
2585 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2586 bnxt_del_vlan_filter(bp, i);
2588 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2592 /* Default filter will allow packets that match the
2593 * dest mac. So, it has to be deleted, otherwise, we
2594 * will endup receiving vlan packets for which the
2595 * filter is not programmed, when hw-vlan-filter
2596 * configuration is ON
2598 bnxt_del_dflt_mac_filter(bp, vnic);
2599 /* This filter will allow only untagged packets */
2600 bnxt_add_vlan_filter(bp, 0);
2602 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2603 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2608 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2610 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2614 /* Destroy vnic filters and vnic */
2615 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2616 DEV_RX_OFFLOAD_VLAN_FILTER) {
2617 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2618 bnxt_del_vlan_filter(bp, i);
2620 bnxt_del_dflt_mac_filter(bp, vnic);
2622 rc = bnxt_hwrm_vnic_ctx_free(bp, vnic);
2626 rc = bnxt_hwrm_vnic_free(bp, vnic);
2630 rte_free(vnic->fw_grp_ids);
2631 vnic->fw_grp_ids = NULL;
2633 vnic->rx_queue_cnt = 0;
2639 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2641 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2644 /* Destroy, recreate and reconfigure the default vnic */
2645 rc = bnxt_free_one_vnic(bp, 0);
2649 /* default vnic 0 */
2650 rc = bnxt_setup_one_vnic(bp, 0);
2654 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2655 DEV_RX_OFFLOAD_VLAN_FILTER) {
2656 rc = bnxt_add_vlan_filter(bp, 0);
2659 rc = bnxt_restore_vlan_filters(bp);
2663 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2668 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2672 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2673 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2679 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2681 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2682 struct bnxt *bp = dev->data->dev_private;
2685 rc = is_bnxt_in_error(bp);
2689 /* Filter settings will get applied when port is started */
2690 if (!dev->data->dev_started)
2693 if (mask & ETH_VLAN_FILTER_MASK) {
2694 /* Enable or disable VLAN filtering */
2695 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2700 if (mask & ETH_VLAN_STRIP_MASK) {
2701 /* Enable or disable VLAN stripping */
2702 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2707 if (mask & ETH_VLAN_EXTEND_MASK) {
2708 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2709 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2711 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2718 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2721 struct bnxt *bp = dev->data->dev_private;
2722 int qinq = dev->data->dev_conf.rxmode.offloads &
2723 DEV_RX_OFFLOAD_VLAN_EXTEND;
2725 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2726 vlan_type != ETH_VLAN_TYPE_OUTER) {
2728 "Unsupported vlan type.");
2733 "QinQ not enabled. Needs to be ON as we can "
2734 "accelerate only outer vlan\n");
2738 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2740 case RTE_ETHER_TYPE_QINQ:
2742 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2744 case RTE_ETHER_TYPE_VLAN:
2746 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2748 case RTE_ETHER_TYPE_QINQ1:
2750 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2752 case RTE_ETHER_TYPE_QINQ2:
2754 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2756 case RTE_ETHER_TYPE_QINQ3:
2758 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2761 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2764 bp->outer_tpid_bd |= tpid;
2765 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2766 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2768 "Can accelerate only outer vlan in QinQ\n");
2776 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2777 struct rte_ether_addr *addr)
2779 struct bnxt *bp = dev->data->dev_private;
2780 /* Default Filter is tied to VNIC 0 */
2781 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2784 rc = is_bnxt_in_error(bp);
2788 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2791 if (rte_is_zero_ether_addr(addr))
2794 /* Filter settings will get applied when port is started */
2795 if (!dev->data->dev_started)
2798 /* Check if the requested MAC is already added */
2799 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2802 /* Destroy filter and re-create it */
2803 bnxt_del_dflt_mac_filter(bp, vnic);
2805 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2806 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2807 /* This filter will allow only untagged packets */
2808 rc = bnxt_add_vlan_filter(bp, 0);
2810 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2813 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2818 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2819 struct rte_ether_addr *mc_addr_set,
2820 uint32_t nb_mc_addr)
2822 struct bnxt *bp = eth_dev->data->dev_private;
2823 char *mc_addr_list = (char *)mc_addr_set;
2824 struct bnxt_vnic_info *vnic;
2825 uint32_t off = 0, i = 0;
2828 rc = is_bnxt_in_error(bp);
2832 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2834 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2835 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2839 /* TODO Check for Duplicate mcast addresses */
2840 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2841 for (i = 0; i < nb_mc_addr; i++) {
2842 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2843 RTE_ETHER_ADDR_LEN);
2844 off += RTE_ETHER_ADDR_LEN;
2847 vnic->mc_addr_cnt = i;
2848 if (vnic->mc_addr_cnt)
2849 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2851 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2854 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2858 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2860 struct bnxt *bp = dev->data->dev_private;
2861 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2862 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2863 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2864 uint8_t fw_rsvd = bp->fw_ver & 0xff;
2867 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2868 fw_major, fw_minor, fw_updt, fw_rsvd);
2872 ret += 1; /* add the size of '\0' */
2873 if (fw_size < (size_t)ret)
2880 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2881 struct rte_eth_rxq_info *qinfo)
2883 struct bnxt *bp = dev->data->dev_private;
2884 struct bnxt_rx_queue *rxq;
2886 if (is_bnxt_in_error(bp))
2889 rxq = dev->data->rx_queues[queue_id];
2891 qinfo->mp = rxq->mb_pool;
2892 qinfo->scattered_rx = dev->data->scattered_rx;
2893 qinfo->nb_desc = rxq->nb_rx_desc;
2895 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2896 qinfo->conf.rx_drop_en = rxq->drop_en;
2897 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2898 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2902 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2903 struct rte_eth_txq_info *qinfo)
2905 struct bnxt *bp = dev->data->dev_private;
2906 struct bnxt_tx_queue *txq;
2908 if (is_bnxt_in_error(bp))
2911 txq = dev->data->tx_queues[queue_id];
2913 qinfo->nb_desc = txq->nb_tx_desc;
2915 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2916 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2917 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2919 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2920 qinfo->conf.tx_rs_thresh = 0;
2921 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2922 qinfo->conf.offloads = txq->offloads;
2925 static const struct {
2926 eth_rx_burst_t pkt_burst;
2928 } bnxt_rx_burst_info[] = {
2929 {bnxt_recv_pkts, "Scalar"},
2930 #if defined(RTE_ARCH_X86)
2931 {bnxt_recv_pkts_vec, "Vector SSE"},
2933 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2934 {bnxt_recv_pkts_vec_avx2, "Vector AVX2"},
2936 #if defined(RTE_ARCH_ARM64)
2937 {bnxt_recv_pkts_vec, "Vector Neon"},
2942 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2943 struct rte_eth_burst_mode *mode)
2945 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2948 for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2949 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2950 snprintf(mode->info, sizeof(mode->info), "%s",
2951 bnxt_rx_burst_info[i].info);
2959 static const struct {
2960 eth_tx_burst_t pkt_burst;
2962 } bnxt_tx_burst_info[] = {
2963 {bnxt_xmit_pkts, "Scalar"},
2964 #if defined(RTE_ARCH_X86)
2965 {bnxt_xmit_pkts_vec, "Vector SSE"},
2967 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2968 {bnxt_xmit_pkts_vec_avx2, "Vector AVX2"},
2970 #if defined(RTE_ARCH_ARM64)
2971 {bnxt_xmit_pkts_vec, "Vector Neon"},
2976 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2977 struct rte_eth_burst_mode *mode)
2979 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2982 for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2983 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2984 snprintf(mode->info, sizeof(mode->info), "%s",
2985 bnxt_tx_burst_info[i].info);
2993 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2995 struct bnxt *bp = eth_dev->data->dev_private;
2996 uint32_t new_pkt_size;
3000 rc = is_bnxt_in_error(bp);
3004 /* Exit if receive queues are not configured yet */
3005 if (!eth_dev->data->nb_rx_queues)
3008 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
3009 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
3012 * Disallow any MTU change that would require scattered receive support
3013 * if it is not already enabled.
3015 if (eth_dev->data->dev_started &&
3016 !eth_dev->data->scattered_rx &&
3018 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
3020 "MTU change would require scattered rx support. ");
3021 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
3025 if (new_mtu > RTE_ETHER_MTU) {
3026 bp->flags |= BNXT_FLAG_JUMBO;
3027 bp->eth_dev->data->dev_conf.rxmode.offloads |=
3028 DEV_RX_OFFLOAD_JUMBO_FRAME;
3030 bp->eth_dev->data->dev_conf.rxmode.offloads &=
3031 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3032 bp->flags &= ~BNXT_FLAG_JUMBO;
3035 /* Is there a change in mtu setting? */
3036 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
3039 for (i = 0; i < bp->nr_vnics; i++) {
3040 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3043 vnic->mru = BNXT_VNIC_MRU(new_mtu);
3044 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
3048 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
3049 size -= RTE_PKTMBUF_HEADROOM;
3051 if (size < new_mtu) {
3052 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
3059 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
3061 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
3067 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
3069 struct bnxt *bp = dev->data->dev_private;
3070 uint16_t vlan = bp->vlan;
3073 rc = is_bnxt_in_error(bp);
3077 if (!BNXT_SINGLE_PF(bp)) {
3078 PMD_DRV_LOG(ERR, "PVID cannot be modified on VF or on shared PF\n");
3081 bp->vlan = on ? pvid : 0;
3083 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
3090 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
3092 struct bnxt *bp = dev->data->dev_private;
3095 rc = is_bnxt_in_error(bp);
3099 return bnxt_hwrm_port_led_cfg(bp, true);
3103 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
3105 struct bnxt *bp = dev->data->dev_private;
3108 rc = is_bnxt_in_error(bp);
3112 return bnxt_hwrm_port_led_cfg(bp, false);
3116 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3118 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
3119 struct bnxt_cp_ring_info *cpr;
3120 uint32_t desc = 0, raw_cons;
3121 struct bnxt_rx_queue *rxq;
3122 struct rx_pkt_cmpl *rxcmp;
3125 rc = is_bnxt_in_error(bp);
3129 rxq = dev->data->rx_queues[rx_queue_id];
3131 raw_cons = cpr->cp_raw_cons;
3134 uint32_t agg_cnt, cons, cmpl_type;
3136 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3137 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3139 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3142 cmpl_type = CMP_TYPE(rxcmp);
3144 switch (cmpl_type) {
3145 case CMPL_BASE_TYPE_RX_L2:
3146 case CMPL_BASE_TYPE_RX_L2_V2:
3147 agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3148 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3152 case CMPL_BASE_TYPE_RX_TPA_END:
3153 if (BNXT_CHIP_P5(rxq->bp)) {
3154 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3156 p5_tpa_end = (void *)rxcmp;
3157 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3159 struct rx_tpa_end_cmpl *tpa_end;
3161 tpa_end = (void *)rxcmp;
3162 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3165 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3170 raw_cons += CMP_LEN(cmpl_type);
3178 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
3180 struct bnxt_rx_queue *rxq = rx_queue;
3181 struct bnxt_cp_ring_info *cpr;
3182 struct bnxt_rx_ring_info *rxr;
3183 uint32_t desc, raw_cons;
3184 struct bnxt *bp = rxq->bp;
3185 struct rx_pkt_cmpl *rxcmp;
3188 rc = is_bnxt_in_error(bp);
3192 if (offset >= rxq->nb_rx_desc)
3199 * For the vector receive case, the completion at the requested
3200 * offset can be indexed directly.
3202 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
3203 if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) {
3204 struct rx_pkt_cmpl *rxcmp;
3207 /* Check status of completion descriptor. */
3208 raw_cons = cpr->cp_raw_cons +
3209 offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2);
3210 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3211 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3213 if (CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3214 return RTE_ETH_RX_DESC_DONE;
3216 /* Check whether rx desc has an mbuf attached. */
3217 cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2);
3218 if (cons >= rxq->rxrearm_start &&
3219 cons < rxq->rxrearm_start + rxq->rxrearm_nb) {
3220 return RTE_ETH_RX_DESC_UNAVAIL;
3223 return RTE_ETH_RX_DESC_AVAIL;
3228 * For the non-vector receive case, scan the completion ring to
3229 * locate the completion descriptor for the requested offset.
3231 raw_cons = cpr->cp_raw_cons;
3234 uint32_t agg_cnt, cons, cmpl_type;
3236 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3237 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3239 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3242 cmpl_type = CMP_TYPE(rxcmp);
3244 switch (cmpl_type) {
3245 case CMPL_BASE_TYPE_RX_L2:
3246 case CMPL_BASE_TYPE_RX_L2_V2:
3247 if (desc == offset) {
3248 cons = rxcmp->opaque;
3249 if (rxr->rx_buf_ring[cons])
3250 return RTE_ETH_RX_DESC_DONE;
3252 return RTE_ETH_RX_DESC_UNAVAIL;
3254 agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3255 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3259 case CMPL_BASE_TYPE_RX_TPA_END:
3261 return RTE_ETH_RX_DESC_DONE;
3263 if (BNXT_CHIP_P5(rxq->bp)) {
3264 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3266 p5_tpa_end = (void *)rxcmp;
3267 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3269 struct rx_tpa_end_cmpl *tpa_end;
3271 tpa_end = (void *)rxcmp;
3272 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3275 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3280 raw_cons += CMP_LEN(cmpl_type);
3284 return RTE_ETH_RX_DESC_AVAIL;
3288 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
3290 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
3291 struct bnxt_tx_ring_info *txr;
3292 struct bnxt_cp_ring_info *cpr;
3293 struct rte_mbuf **tx_buf;
3294 struct tx_pkt_cmpl *txcmp;
3295 uint32_t cons, cp_cons;
3301 rc = is_bnxt_in_error(txq->bp);
3308 if (offset >= txq->nb_tx_desc)
3311 cons = RING_CMP(cpr->cp_ring_struct, offset);
3312 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3313 cp_cons = cpr->cp_raw_cons;
3315 if (cons > cp_cons) {
3316 if (CMPL_VALID(txcmp, cpr->valid))
3317 return RTE_ETH_TX_DESC_UNAVAIL;
3319 if (CMPL_VALID(txcmp, !cpr->valid))
3320 return RTE_ETH_TX_DESC_UNAVAIL;
3322 tx_buf = &txr->tx_buf_ring[cons];
3323 if (*tx_buf == NULL)
3324 return RTE_ETH_TX_DESC_DONE;
3326 return RTE_ETH_TX_DESC_FULL;
3330 bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
3331 const struct rte_flow_ops **ops)
3333 struct bnxt *bp = dev->data->dev_private;
3339 if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3340 struct bnxt_representor *vfr = dev->data->dev_private;
3341 bp = vfr->parent_dev->data->dev_private;
3342 /* parent is deleted while children are still valid */
3344 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error\n",
3345 dev->data->port_id);
3350 ret = is_bnxt_in_error(bp);
3354 /* PMD supports thread-safe flow operations. rte_flow API
3355 * functions can avoid mutex for multi-thread safety.
3357 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3359 if (BNXT_TRUFLOW_EN(bp))
3360 *ops = &bnxt_ulp_rte_flow_ops;
3362 *ops = &bnxt_flow_ops;
3367 static const uint32_t *
3368 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3370 static const uint32_t ptypes[] = {
3371 RTE_PTYPE_L2_ETHER_VLAN,
3372 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3373 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3377 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3378 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3379 RTE_PTYPE_INNER_L4_ICMP,
3380 RTE_PTYPE_INNER_L4_TCP,
3381 RTE_PTYPE_INNER_L4_UDP,
3385 if (!dev->rx_pkt_burst)
3391 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3394 uint32_t reg_base = *reg_arr & 0xfffff000;
3398 for (i = 0; i < count; i++) {
3399 if ((reg_arr[i] & 0xfffff000) != reg_base)
3402 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3403 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3407 static int bnxt_map_ptp_regs(struct bnxt *bp)
3409 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3413 reg_arr = ptp->rx_regs;
3414 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3418 reg_arr = ptp->tx_regs;
3419 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3423 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3424 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3426 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3427 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3432 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3434 rte_write32(0, (uint8_t *)bp->bar0 +
3435 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3436 rte_write32(0, (uint8_t *)bp->bar0 +
3437 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3440 static uint64_t bnxt_cc_read(struct bnxt *bp)
3444 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3445 BNXT_GRCPF_REG_SYNC_TIME));
3446 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3447 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3451 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3453 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3456 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3457 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3458 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3461 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3462 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3463 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3464 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3465 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3466 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3467 rte_read32((uint8_t *)bp->bar0 + ptp->tx_mapped_regs[BNXT_PTP_TX_SEQ]);
3472 static int bnxt_clr_rx_ts(struct bnxt *bp, uint64_t *last_ts)
3474 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3475 struct bnxt_pf_info *pf = bp->pf;
3480 if (!ptp || (bp->flags & BNXT_FLAG_CHIP_P5))
3483 port_id = pf->port_id;
3484 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3485 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3486 while ((fifo & BNXT_PTP_RX_FIFO_PENDING) && (i < BNXT_PTP_RX_PND_CNT)) {
3487 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3488 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3489 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3490 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3491 *last_ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3492 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3493 *last_ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3494 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3498 if (i >= BNXT_PTP_RX_PND_CNT)
3504 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3506 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3507 struct bnxt_pf_info *pf = bp->pf;
3511 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3512 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3513 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3516 port_id = pf->port_id;
3517 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3518 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3520 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3521 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3522 if (fifo & BNXT_PTP_RX_FIFO_PENDING)
3523 return bnxt_clr_rx_ts(bp, ts);
3525 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3526 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3527 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3528 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3534 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3537 struct bnxt *bp = dev->data->dev_private;
3538 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3543 ns = rte_timespec_to_ns(ts);
3544 /* Set the timecounters to a new value. */
3546 ptp->tx_tstamp_tc.nsec = ns;
3547 ptp->rx_tstamp_tc.nsec = ns;
3553 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3555 struct bnxt *bp = dev->data->dev_private;
3556 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3557 uint64_t ns, systime_cycles = 0;
3563 if (BNXT_CHIP_P5(bp))
3564 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3567 systime_cycles = bnxt_cc_read(bp);
3569 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3570 *ts = rte_ns_to_timespec(ns);
3575 bnxt_timesync_enable(struct rte_eth_dev *dev)
3577 struct bnxt *bp = dev->data->dev_private;
3578 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3586 ptp->tx_tstamp_en = 1;
3587 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3589 rc = bnxt_hwrm_ptp_cfg(bp);
3593 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3594 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3595 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3597 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3598 ptp->tc.cc_shift = shift;
3599 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3601 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3602 ptp->rx_tstamp_tc.cc_shift = shift;
3603 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3605 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3606 ptp->tx_tstamp_tc.cc_shift = shift;
3607 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3609 if (!BNXT_CHIP_P5(bp))
3610 bnxt_map_ptp_regs(bp);
3612 rc = bnxt_ptp_start(bp);
3618 bnxt_timesync_disable(struct rte_eth_dev *dev)
3620 struct bnxt *bp = dev->data->dev_private;
3621 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3627 ptp->tx_tstamp_en = 0;
3630 bnxt_hwrm_ptp_cfg(bp);
3632 if (!BNXT_CHIP_P5(bp))
3633 bnxt_unmap_ptp_regs(bp);
3641 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3642 struct timespec *timestamp,
3643 uint32_t flags __rte_unused)
3645 struct bnxt *bp = dev->data->dev_private;
3646 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3647 uint64_t rx_tstamp_cycles = 0;
3653 if (BNXT_CHIP_P5(bp))
3654 rx_tstamp_cycles = ptp->rx_timestamp;
3656 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3658 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3659 *timestamp = rte_ns_to_timespec(ns);
3664 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3665 struct timespec *timestamp)
3667 struct bnxt *bp = dev->data->dev_private;
3668 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3669 uint64_t tx_tstamp_cycles = 0;
3676 if (BNXT_CHIP_P5(bp))
3677 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3680 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3682 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3683 *timestamp = rte_ns_to_timespec(ns);
3689 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3691 struct bnxt *bp = dev->data->dev_private;
3692 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3697 ptp->tc.nsec += delta;
3698 ptp->tx_tstamp_tc.nsec += delta;
3699 ptp->rx_tstamp_tc.nsec += delta;
3705 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3707 struct bnxt *bp = dev->data->dev_private;
3709 uint32_t dir_entries;
3710 uint32_t entry_length;
3712 rc = is_bnxt_in_error(bp);
3716 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3717 bp->pdev->addr.domain, bp->pdev->addr.bus,
3718 bp->pdev->addr.devid, bp->pdev->addr.function);
3720 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3724 return dir_entries * entry_length;
3728 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3729 struct rte_dev_eeprom_info *in_eeprom)
3731 struct bnxt *bp = dev->data->dev_private;
3736 rc = is_bnxt_in_error(bp);
3740 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3741 bp->pdev->addr.domain, bp->pdev->addr.bus,
3742 bp->pdev->addr.devid, bp->pdev->addr.function,
3743 in_eeprom->offset, in_eeprom->length);
3745 if (in_eeprom->offset == 0) /* special offset value to get directory */
3746 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3749 index = in_eeprom->offset >> 24;
3750 offset = in_eeprom->offset & 0xffffff;
3753 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3754 in_eeprom->length, in_eeprom->data);
3759 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3762 case BNX_DIR_TYPE_CHIMP_PATCH:
3763 case BNX_DIR_TYPE_BOOTCODE:
3764 case BNX_DIR_TYPE_BOOTCODE_2:
3765 case BNX_DIR_TYPE_APE_FW:
3766 case BNX_DIR_TYPE_APE_PATCH:
3767 case BNX_DIR_TYPE_KONG_FW:
3768 case BNX_DIR_TYPE_KONG_PATCH:
3769 case BNX_DIR_TYPE_BONO_FW:
3770 case BNX_DIR_TYPE_BONO_PATCH:
3778 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3781 case BNX_DIR_TYPE_AVS:
3782 case BNX_DIR_TYPE_EXP_ROM_MBA:
3783 case BNX_DIR_TYPE_PCIE:
3784 case BNX_DIR_TYPE_TSCF_UCODE:
3785 case BNX_DIR_TYPE_EXT_PHY:
3786 case BNX_DIR_TYPE_CCM:
3787 case BNX_DIR_TYPE_ISCSI_BOOT:
3788 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3789 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3797 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3799 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3800 bnxt_dir_type_is_other_exec_format(dir_type);
3804 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3805 struct rte_dev_eeprom_info *in_eeprom)
3807 struct bnxt *bp = dev->data->dev_private;
3808 uint8_t index, dir_op;
3809 uint16_t type, ext, ordinal, attr;
3812 rc = is_bnxt_in_error(bp);
3816 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3817 bp->pdev->addr.domain, bp->pdev->addr.bus,
3818 bp->pdev->addr.devid, bp->pdev->addr.function,
3819 in_eeprom->offset, in_eeprom->length);
3822 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3826 type = in_eeprom->magic >> 16;
3828 if (type == 0xffff) { /* special value for directory operations */
3829 index = in_eeprom->magic & 0xff;
3830 dir_op = in_eeprom->magic >> 8;
3834 case 0x0e: /* erase */
3835 if (in_eeprom->offset != ~in_eeprom->magic)
3837 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3843 /* Create or re-write an NVM item: */
3844 if (bnxt_dir_type_is_executable(type) == true)
3846 ext = in_eeprom->magic & 0xffff;
3847 ordinal = in_eeprom->offset >> 16;
3848 attr = in_eeprom->offset & 0xffff;
3850 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3851 in_eeprom->data, in_eeprom->length);
3858 static const struct eth_dev_ops bnxt_dev_ops = {
3859 .dev_infos_get = bnxt_dev_info_get_op,
3860 .dev_close = bnxt_dev_close_op,
3861 .dev_configure = bnxt_dev_configure_op,
3862 .dev_start = bnxt_dev_start_op,
3863 .dev_stop = bnxt_dev_stop_op,
3864 .dev_set_link_up = bnxt_dev_set_link_up_op,
3865 .dev_set_link_down = bnxt_dev_set_link_down_op,
3866 .stats_get = bnxt_stats_get_op,
3867 .stats_reset = bnxt_stats_reset_op,
3868 .rx_queue_setup = bnxt_rx_queue_setup_op,
3869 .rx_queue_release = bnxt_rx_queue_release_op,
3870 .tx_queue_setup = bnxt_tx_queue_setup_op,
3871 .tx_queue_release = bnxt_tx_queue_release_op,
3872 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3873 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3874 .reta_update = bnxt_reta_update_op,
3875 .reta_query = bnxt_reta_query_op,
3876 .rss_hash_update = bnxt_rss_hash_update_op,
3877 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3878 .link_update = bnxt_link_update_op,
3879 .promiscuous_enable = bnxt_promiscuous_enable_op,
3880 .promiscuous_disable = bnxt_promiscuous_disable_op,
3881 .allmulticast_enable = bnxt_allmulticast_enable_op,
3882 .allmulticast_disable = bnxt_allmulticast_disable_op,
3883 .mac_addr_add = bnxt_mac_addr_add_op,
3884 .mac_addr_remove = bnxt_mac_addr_remove_op,
3885 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3886 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3887 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3888 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3889 .vlan_filter_set = bnxt_vlan_filter_set_op,
3890 .vlan_offload_set = bnxt_vlan_offload_set_op,
3891 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3892 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3893 .mtu_set = bnxt_mtu_set_op,
3894 .mac_addr_set = bnxt_set_default_mac_addr_op,
3895 .xstats_get = bnxt_dev_xstats_get_op,
3896 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3897 .xstats_reset = bnxt_dev_xstats_reset_op,
3898 .fw_version_get = bnxt_fw_version_get,
3899 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3900 .rxq_info_get = bnxt_rxq_info_get_op,
3901 .txq_info_get = bnxt_txq_info_get_op,
3902 .rx_burst_mode_get = bnxt_rx_burst_mode_get,
3903 .tx_burst_mode_get = bnxt_tx_burst_mode_get,
3904 .dev_led_on = bnxt_dev_led_on_op,
3905 .dev_led_off = bnxt_dev_led_off_op,
3906 .rx_queue_start = bnxt_rx_queue_start,
3907 .rx_queue_stop = bnxt_rx_queue_stop,
3908 .tx_queue_start = bnxt_tx_queue_start,
3909 .tx_queue_stop = bnxt_tx_queue_stop,
3910 .flow_ops_get = bnxt_flow_ops_get_op,
3911 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3912 .get_eeprom_length = bnxt_get_eeprom_length_op,
3913 .get_eeprom = bnxt_get_eeprom_op,
3914 .set_eeprom = bnxt_set_eeprom_op,
3915 .timesync_enable = bnxt_timesync_enable,
3916 .timesync_disable = bnxt_timesync_disable,
3917 .timesync_read_time = bnxt_timesync_read_time,
3918 .timesync_write_time = bnxt_timesync_write_time,
3919 .timesync_adjust_time = bnxt_timesync_adjust_time,
3920 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3921 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3924 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3928 /* Only pre-map the reset GRC registers using window 3 */
3929 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3930 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3932 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3937 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3939 struct bnxt_error_recovery_info *info = bp->recovery_info;
3940 uint32_t reg_base = 0xffffffff;
3943 /* Only pre-map the monitoring GRC registers using window 2 */
3944 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3945 uint32_t reg = info->status_regs[i];
3947 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3950 if (reg_base == 0xffffffff)
3951 reg_base = reg & 0xfffff000;
3952 if ((reg & 0xfffff000) != reg_base)
3955 /* Use mask 0xffc as the Lower 2 bits indicates
3956 * address space location
3958 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3962 if (reg_base == 0xffffffff)
3965 rte_write32(reg_base, (uint8_t *)bp->bar0 +
3966 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3971 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3973 struct bnxt_error_recovery_info *info = bp->recovery_info;
3974 uint32_t delay = info->delay_after_reset[index];
3975 uint32_t val = info->reset_reg_val[index];
3976 uint32_t reg = info->reset_reg[index];
3977 uint32_t type, offset;
3980 type = BNXT_FW_STATUS_REG_TYPE(reg);
3981 offset = BNXT_FW_STATUS_REG_OFF(reg);
3984 case BNXT_FW_STATUS_REG_TYPE_CFG:
3985 ret = rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3987 PMD_DRV_LOG(ERR, "Failed to write %#x at PCI offset %#x",
3992 case BNXT_FW_STATUS_REG_TYPE_GRC:
3993 offset = bnxt_map_reset_regs(bp, offset);
3994 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3996 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3997 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4000 /* wait on a specific interval of time until core reset is complete */
4002 rte_delay_ms(delay);
4005 static void bnxt_dev_cleanup(struct bnxt *bp)
4007 bp->eth_dev->data->dev_link.link_status = 0;
4008 bp->link_info->link_up = 0;
4009 if (bp->eth_dev->data->dev_started)
4010 bnxt_dev_stop(bp->eth_dev);
4012 bnxt_uninit_resources(bp, true);
4016 bnxt_check_fw_reset_done(struct bnxt *bp)
4018 int timeout = bp->fw_reset_max_msecs;
4023 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4025 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4031 } while (timeout--);
4033 if (val == 0xffff) {
4034 PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n");
4041 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4043 struct rte_eth_dev *dev = bp->eth_dev;
4044 struct rte_vlan_filter_conf *vfc;
4048 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4049 vfc = &dev->data->vlan_filter_conf;
4050 vidx = vlan_id / 64;
4051 vbit = vlan_id % 64;
4053 /* Each bit corresponds to a VLAN id */
4054 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4055 rc = bnxt_add_vlan_filter(bp, vlan_id);
4064 static int bnxt_restore_mac_filters(struct bnxt *bp)
4066 struct rte_eth_dev *dev = bp->eth_dev;
4067 struct rte_eth_dev_info dev_info;
4068 struct rte_ether_addr *addr;
4074 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4077 rc = bnxt_dev_info_get_op(dev, &dev_info);
4081 /* replay MAC address configuration */
4082 for (i = 1; i < dev_info.max_mac_addrs; i++) {
4083 addr = &dev->data->mac_addrs[i];
4085 /* skip zero address */
4086 if (rte_is_zero_ether_addr(addr))
4090 pool_mask = dev->data->mac_pool_sel[i];
4093 if (pool_mask & 1ULL) {
4094 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4100 } while (pool_mask);
4106 static int bnxt_restore_filters(struct bnxt *bp)
4108 struct rte_eth_dev *dev = bp->eth_dev;
4111 if (dev->data->all_multicast) {
4112 ret = bnxt_allmulticast_enable_op(dev);
4116 if (dev->data->promiscuous) {
4117 ret = bnxt_promiscuous_enable_op(dev);
4122 ret = bnxt_restore_mac_filters(bp);
4126 ret = bnxt_restore_vlan_filters(bp);
4127 /* TODO restore other filters as well */
4131 static int bnxt_check_fw_ready(struct bnxt *bp)
4133 int timeout = bp->fw_reset_max_msecs;
4137 rc = bnxt_hwrm_poll_ver_get(bp);
4140 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4141 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4142 } while (rc && timeout > 0);
4145 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4150 static void bnxt_dev_recover(void *arg)
4152 struct bnxt *bp = arg;
4155 pthread_mutex_lock(&bp->err_recovery_lock);
4157 if (!bp->fw_reset_min_msecs) {
4158 rc = bnxt_check_fw_reset_done(bp);
4163 /* Clear Error flag so that device re-init should happen */
4164 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4166 rc = bnxt_check_fw_ready(bp);
4170 rc = bnxt_init_resources(bp, true);
4173 "Failed to initialize resources after reset\n");
4176 /* clear reset flag as the device is initialized now */
4177 bp->flags &= ~BNXT_FLAG_FW_RESET;
4179 rc = bnxt_dev_start_op(bp->eth_dev);
4181 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4185 rc = bnxt_restore_filters(bp);
4189 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4190 pthread_mutex_unlock(&bp->err_recovery_lock);
4194 bnxt_dev_stop(bp->eth_dev);
4196 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4197 bnxt_uninit_resources(bp, false);
4198 pthread_mutex_unlock(&bp->err_recovery_lock);
4199 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4202 void bnxt_dev_reset_and_resume(void *arg)
4204 struct bnxt *bp = arg;
4205 uint32_t us = US_PER_MS * bp->fw_reset_min_msecs;
4209 bnxt_dev_cleanup(bp);
4211 bnxt_wait_for_device_shutdown(bp);
4213 /* During some fatal firmware error conditions, the PCI config space
4214 * register 0x2e which normally contains the subsystem ID will become
4215 * 0xffff. This register will revert back to the normal value after
4216 * the chip has completed core reset. If we detect this condition,
4217 * we can poll this config register immediately for the value to revert.
4219 if (bp->flags & BNXT_FLAG_FATAL_ERROR) {
4220 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4222 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4225 if (val == 0xffff) {
4226 bp->fw_reset_min_msecs = 0;
4231 rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp);
4233 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4236 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4238 struct bnxt_error_recovery_info *info = bp->recovery_info;
4239 uint32_t reg = info->status_regs[index];
4240 uint32_t type, offset, val = 0;
4243 type = BNXT_FW_STATUS_REG_TYPE(reg);
4244 offset = BNXT_FW_STATUS_REG_OFF(reg);
4247 case BNXT_FW_STATUS_REG_TYPE_CFG:
4248 ret = rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4250 PMD_DRV_LOG(ERR, "Failed to read PCI offset %#x",
4253 case BNXT_FW_STATUS_REG_TYPE_GRC:
4254 offset = info->mapped_status_regs[index];
4256 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4257 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4265 static int bnxt_fw_reset_all(struct bnxt *bp)
4267 struct bnxt_error_recovery_info *info = bp->recovery_info;
4271 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4272 /* Reset through master function driver */
4273 for (i = 0; i < info->reg_array_cnt; i++)
4274 bnxt_write_fw_reset_reg(bp, i);
4275 /* Wait for time specified by FW after triggering reset */
4276 rte_delay_ms(info->master_func_wait_period_after_reset);
4277 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4278 /* Reset with the help of Kong processor */
4279 rc = bnxt_hwrm_fw_reset(bp);
4281 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4287 static void bnxt_fw_reset_cb(void *arg)
4289 struct bnxt *bp = arg;
4290 struct bnxt_error_recovery_info *info = bp->recovery_info;
4293 /* Only Master function can do FW reset */
4294 if (bnxt_is_master_func(bp) &&
4295 bnxt_is_recovery_enabled(bp)) {
4296 rc = bnxt_fw_reset_all(bp);
4298 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4303 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4304 * EXCEPTION_FATAL_ASYNC event to all the functions
4305 * (including MASTER FUNC). After receiving this Async, all the active
4306 * drivers should treat this case as FW initiated recovery
4308 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4309 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4310 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4312 /* To recover from error */
4313 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4318 /* Driver should poll FW heartbeat, reset_counter with the frequency
4319 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4320 * When the driver detects heartbeat stop or change in reset_counter,
4321 * it has to trigger a reset to recover from the error condition.
4322 * A “master PF” is the function who will have the privilege to
4323 * initiate the chimp reset. The master PF will be elected by the
4324 * firmware and will be notified through async message.
4326 static void bnxt_check_fw_health(void *arg)
4328 struct bnxt *bp = arg;
4329 struct bnxt_error_recovery_info *info = bp->recovery_info;
4330 uint32_t val = 0, wait_msec;
4332 if (!info || !bnxt_is_recovery_enabled(bp) ||
4333 is_bnxt_in_error(bp))
4336 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4337 if (val == info->last_heart_beat)
4340 info->last_heart_beat = val;
4342 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4343 if (val != info->last_reset_counter)
4346 info->last_reset_counter = val;
4348 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4349 bnxt_check_fw_health, (void *)bp);
4353 /* Stop DMA to/from device */
4354 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4355 bp->flags |= BNXT_FLAG_FW_RESET;
4359 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4361 if (bnxt_is_master_func(bp))
4362 wait_msec = info->master_func_wait_period;
4364 wait_msec = info->normal_func_wait_period;
4366 rte_eal_alarm_set(US_PER_MS * wait_msec,
4367 bnxt_fw_reset_cb, (void *)bp);
4370 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4372 uint32_t polling_freq;
4374 pthread_mutex_lock(&bp->health_check_lock);
4376 if (!bnxt_is_recovery_enabled(bp))
4379 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4382 polling_freq = bp->recovery_info->driver_polling_freq;
4384 rte_eal_alarm_set(US_PER_MS * polling_freq,
4385 bnxt_check_fw_health, (void *)bp);
4386 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4389 pthread_mutex_unlock(&bp->health_check_lock);
4392 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4394 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4395 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4398 static bool bnxt_vf_pciid(uint16_t device_id)
4400 switch (device_id) {
4401 case BROADCOM_DEV_ID_57304_VF:
4402 case BROADCOM_DEV_ID_57406_VF:
4403 case BROADCOM_DEV_ID_5731X_VF:
4404 case BROADCOM_DEV_ID_5741X_VF:
4405 case BROADCOM_DEV_ID_57414_VF:
4406 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4407 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4408 case BROADCOM_DEV_ID_58802_VF:
4409 case BROADCOM_DEV_ID_57500_VF1:
4410 case BROADCOM_DEV_ID_57500_VF2:
4411 case BROADCOM_DEV_ID_58818_VF:
4419 /* Phase 5 device */
4420 static bool bnxt_p5_device(uint16_t device_id)
4422 switch (device_id) {
4423 case BROADCOM_DEV_ID_57508:
4424 case BROADCOM_DEV_ID_57504:
4425 case BROADCOM_DEV_ID_57502:
4426 case BROADCOM_DEV_ID_57508_MF1:
4427 case BROADCOM_DEV_ID_57504_MF1:
4428 case BROADCOM_DEV_ID_57502_MF1:
4429 case BROADCOM_DEV_ID_57508_MF2:
4430 case BROADCOM_DEV_ID_57504_MF2:
4431 case BROADCOM_DEV_ID_57502_MF2:
4432 case BROADCOM_DEV_ID_57500_VF1:
4433 case BROADCOM_DEV_ID_57500_VF2:
4434 case BROADCOM_DEV_ID_58812:
4435 case BROADCOM_DEV_ID_58814:
4436 case BROADCOM_DEV_ID_58818:
4437 case BROADCOM_DEV_ID_58818_VF:
4445 bool bnxt_stratus_device(struct bnxt *bp)
4447 uint16_t device_id = bp->pdev->id.device_id;
4449 switch (device_id) {
4450 case BROADCOM_DEV_ID_STRATUS_NIC:
4451 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4452 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4460 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev)
4462 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4463 struct bnxt *bp = eth_dev->data->dev_private;
4465 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4466 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4467 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4468 if (!bp->bar0 || !bp->doorbell_base) {
4469 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4473 bp->eth_dev = eth_dev;
4479 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4480 struct bnxt_ctx_pg_info *ctx_pg,
4485 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4486 const struct rte_memzone *mz = NULL;
4487 char mz_name[RTE_MEMZONE_NAMESIZE];
4488 rte_iova_t mz_phys_addr;
4489 uint64_t valid_bits = 0;
4496 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4498 rmem->page_size = BNXT_PAGE_SIZE;
4499 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4500 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4501 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4503 valid_bits = PTU_PTE_VALID;
4505 if (rmem->nr_pages > 1) {
4506 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4507 "bnxt_ctx_pg_tbl%s_%x_%d",
4508 suffix, idx, bp->eth_dev->data->port_id);
4509 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4510 mz = rte_memzone_lookup(mz_name);
4512 mz = rte_memzone_reserve_aligned(mz_name,
4516 RTE_MEMZONE_SIZE_HINT_ONLY |
4517 RTE_MEMZONE_IOVA_CONTIG,
4523 memset(mz->addr, 0, mz->len);
4524 mz_phys_addr = mz->iova;
4526 rmem->pg_tbl = mz->addr;
4527 rmem->pg_tbl_map = mz_phys_addr;
4528 rmem->pg_tbl_mz = mz;
4531 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4532 suffix, idx, bp->eth_dev->data->port_id);
4533 mz = rte_memzone_lookup(mz_name);
4535 mz = rte_memzone_reserve_aligned(mz_name,
4539 RTE_MEMZONE_SIZE_HINT_ONLY |
4540 RTE_MEMZONE_IOVA_CONTIG,
4546 memset(mz->addr, 0, mz->len);
4547 mz_phys_addr = mz->iova;
4549 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4550 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4551 rmem->dma_arr[i] = mz_phys_addr + sz;
4553 if (rmem->nr_pages > 1) {
4554 if (i == rmem->nr_pages - 2 &&
4555 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4556 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4557 else if (i == rmem->nr_pages - 1 &&
4558 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4559 valid_bits |= PTU_PTE_LAST;
4561 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4567 if (rmem->vmem_size)
4568 rmem->vmem = (void **)mz->addr;
4569 rmem->dma_arr[0] = mz_phys_addr;
4573 static void bnxt_free_ctx_mem(struct bnxt *bp)
4577 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4580 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4581 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4582 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4583 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4584 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4585 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4586 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4587 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4588 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4589 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4590 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4592 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4593 if (bp->ctx->tqm_mem[i])
4594 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4601 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4603 #define min_t(type, x, y) ({ \
4604 type __min1 = (x); \
4605 type __min2 = (y); \
4606 __min1 < __min2 ? __min1 : __min2; })
4608 #define max_t(type, x, y) ({ \
4609 type __max1 = (x); \
4610 type __max2 = (y); \
4611 __max1 > __max2 ? __max1 : __max2; })
4613 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4615 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4617 struct bnxt_ctx_pg_info *ctx_pg;
4618 struct bnxt_ctx_mem_info *ctx;
4619 uint32_t mem_size, ena, entries;
4620 uint32_t entries_sp, min;
4623 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4625 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4629 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4632 ctx_pg = &ctx->qp_mem;
4633 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4634 if (ctx->qp_entry_size) {
4635 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4636 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4641 ctx_pg = &ctx->srq_mem;
4642 ctx_pg->entries = ctx->srq_max_l2_entries;
4643 if (ctx->srq_entry_size) {
4644 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4645 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4650 ctx_pg = &ctx->cq_mem;
4651 ctx_pg->entries = ctx->cq_max_l2_entries;
4652 if (ctx->cq_entry_size) {
4653 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4654 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4659 ctx_pg = &ctx->vnic_mem;
4660 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4661 ctx->vnic_max_ring_table_entries;
4662 if (ctx->vnic_entry_size) {
4663 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4664 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4669 ctx_pg = &ctx->stat_mem;
4670 ctx_pg->entries = ctx->stat_max_entries;
4671 if (ctx->stat_entry_size) {
4672 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4673 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4678 min = ctx->tqm_min_entries_per_ring;
4680 entries_sp = ctx->qp_max_l2_entries +
4681 ctx->vnic_max_vnic_entries +
4682 2 * ctx->qp_min_qp1_entries + min;
4683 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4685 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4686 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4687 entries = clamp_t(uint32_t, entries, min,
4688 ctx->tqm_max_entries_per_ring);
4689 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4690 /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7.
4691 * i > 8 is other ext rings.
4693 ctx_pg = ctx->tqm_mem[i];
4694 ctx_pg->entries = i ? entries : entries_sp;
4695 if (ctx->tqm_entry_size) {
4696 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4697 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size,
4702 if (i < BNXT_MAX_TQM_LEGACY_RINGS)
4703 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4705 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8;
4708 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4709 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4712 "Failed to configure context mem: rc = %d\n", rc);
4714 ctx->flags |= BNXT_CTX_FLAG_INITED;
4719 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4721 struct rte_pci_device *pci_dev = bp->pdev;
4722 char mz_name[RTE_MEMZONE_NAMESIZE];
4723 const struct rte_memzone *mz = NULL;
4724 uint32_t total_alloc_len;
4725 rte_iova_t mz_phys_addr;
4727 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4730 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4731 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4732 pci_dev->addr.bus, pci_dev->addr.devid,
4733 pci_dev->addr.function, "rx_port_stats");
4734 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4735 mz = rte_memzone_lookup(mz_name);
4737 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4738 sizeof(struct rx_port_stats_ext) + 512);
4740 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4743 RTE_MEMZONE_SIZE_HINT_ONLY |
4744 RTE_MEMZONE_IOVA_CONTIG);
4748 memset(mz->addr, 0, mz->len);
4749 mz_phys_addr = mz->iova;
4751 bp->rx_mem_zone = (const void *)mz;
4752 bp->hw_rx_port_stats = mz->addr;
4753 bp->hw_rx_port_stats_map = mz_phys_addr;
4755 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4756 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4757 pci_dev->addr.bus, pci_dev->addr.devid,
4758 pci_dev->addr.function, "tx_port_stats");
4759 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4760 mz = rte_memzone_lookup(mz_name);
4762 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4763 sizeof(struct tx_port_stats_ext) + 512);
4765 mz = rte_memzone_reserve(mz_name,
4769 RTE_MEMZONE_SIZE_HINT_ONLY |
4770 RTE_MEMZONE_IOVA_CONTIG);
4774 memset(mz->addr, 0, mz->len);
4775 mz_phys_addr = mz->iova;
4777 bp->tx_mem_zone = (const void *)mz;
4778 bp->hw_tx_port_stats = mz->addr;
4779 bp->hw_tx_port_stats_map = mz_phys_addr;
4780 bp->flags |= BNXT_FLAG_PORT_STATS;
4782 /* Display extended statistics if FW supports it */
4783 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4784 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4785 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4788 bp->hw_rx_port_stats_ext = (void *)
4789 ((uint8_t *)bp->hw_rx_port_stats +
4790 sizeof(struct rx_port_stats));
4791 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4792 sizeof(struct rx_port_stats);
4793 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4795 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4796 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4797 bp->hw_tx_port_stats_ext = (void *)
4798 ((uint8_t *)bp->hw_tx_port_stats +
4799 sizeof(struct tx_port_stats));
4800 bp->hw_tx_port_stats_ext_map =
4801 bp->hw_tx_port_stats_map +
4802 sizeof(struct tx_port_stats);
4803 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4809 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4811 struct bnxt *bp = eth_dev->data->dev_private;
4814 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4815 RTE_ETHER_ADDR_LEN *
4818 if (eth_dev->data->mac_addrs == NULL) {
4819 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4823 if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4827 /* Generate a random MAC address, if none was assigned by PF */
4828 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4829 bnxt_eth_hw_addr_random(bp->mac_addr);
4831 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4832 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4833 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4835 rc = bnxt_hwrm_set_mac(bp);
4840 /* Copy the permanent MAC from the FUNC_QCAPS response */
4841 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4846 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4850 /* MAC is already configured in FW */
4851 if (BNXT_HAS_DFLT_MAC_SET(bp))
4854 /* Restore the old MAC configured */
4855 rc = bnxt_hwrm_set_mac(bp);
4857 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4862 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4867 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
4869 if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
4870 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
4871 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
4872 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
4873 BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
4874 BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
4878 bnxt_get_svif(uint16_t port_id, bool func_svif,
4879 enum bnxt_ulp_intf_type type)
4881 struct rte_eth_dev *eth_dev;
4884 eth_dev = &rte_eth_devices[port_id];
4885 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4886 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4890 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4893 eth_dev = vfr->parent_dev;
4896 bp = eth_dev->data->dev_private;
4898 return func_svif ? bp->func_svif : bp->port_svif;
4902 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
4904 struct rte_eth_dev *eth_dev;
4905 struct bnxt_vnic_info *vnic;
4908 eth_dev = &rte_eth_devices[port];
4909 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4910 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4914 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4915 return vfr->dflt_vnic_id;
4917 eth_dev = vfr->parent_dev;
4920 bp = eth_dev->data->dev_private;
4922 vnic = BNXT_GET_DEFAULT_VNIC(bp);
4924 return vnic->fw_vnic_id;
4928 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
4930 struct rte_eth_dev *eth_dev;
4933 eth_dev = &rte_eth_devices[port];
4934 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4935 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4939 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4942 eth_dev = vfr->parent_dev;
4945 bp = eth_dev->data->dev_private;
4950 enum bnxt_ulp_intf_type
4951 bnxt_get_interface_type(uint16_t port)
4953 struct rte_eth_dev *eth_dev;
4956 eth_dev = &rte_eth_devices[port];
4957 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
4958 return BNXT_ULP_INTF_TYPE_VF_REP;
4960 bp = eth_dev->data->dev_private;
4962 return BNXT_ULP_INTF_TYPE_PF;
4963 else if (BNXT_VF_IS_TRUSTED(bp))
4964 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
4965 else if (BNXT_VF(bp))
4966 return BNXT_ULP_INTF_TYPE_VF;
4968 return BNXT_ULP_INTF_TYPE_INVALID;
4972 bnxt_get_phy_port_id(uint16_t port_id)
4974 struct bnxt_representor *vfr;
4975 struct rte_eth_dev *eth_dev;
4978 eth_dev = &rte_eth_devices[port_id];
4979 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4980 vfr = eth_dev->data->dev_private;
4984 eth_dev = vfr->parent_dev;
4987 bp = eth_dev->data->dev_private;
4989 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
4993 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
4995 struct rte_eth_dev *eth_dev;
4998 eth_dev = &rte_eth_devices[port_id];
4999 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5000 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5004 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5005 return vfr->fw_fid - 1;
5007 eth_dev = vfr->parent_dev;
5010 bp = eth_dev->data->dev_private;
5012 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5016 bnxt_get_vport(uint16_t port_id)
5018 return (1 << bnxt_get_phy_port_id(port_id));
5021 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5023 struct bnxt_error_recovery_info *info = bp->recovery_info;
5026 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5027 memset(info, 0, sizeof(*info));
5031 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5034 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5037 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5039 bp->recovery_info = info;
5042 static void bnxt_check_fw_status(struct bnxt *bp)
5046 if (!(bp->recovery_info &&
5047 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5050 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5051 if (fw_status != BNXT_FW_STATUS_HEALTHY)
5052 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5056 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5058 struct bnxt_error_recovery_info *info = bp->recovery_info;
5059 uint32_t status_loc;
5062 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5063 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5064 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5065 BNXT_GRCP_WINDOW_2_BASE +
5066 offsetof(struct hcomm_status,
5068 /* If the signature is absent, then FW does not support this feature */
5069 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5070 HCOMM_STATUS_SIGNATURE_VAL)
5074 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5078 bp->recovery_info = info;
5080 memset(info, 0, sizeof(*info));
5083 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5084 BNXT_GRCP_WINDOW_2_BASE +
5085 offsetof(struct hcomm_status,
5088 /* Only pre-map the FW health status GRC register */
5089 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5092 info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5093 info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5094 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5096 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5097 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5099 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5104 /* This function gets the FW version along with the
5105 * capabilities(MAX and current) of the function, vnic,
5106 * error recovery, phy and other chip related info
5108 static int bnxt_get_config(struct bnxt *bp)
5115 rc = bnxt_map_hcomm_fw_status_reg(bp);
5119 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5121 bnxt_check_fw_status(bp);
5125 rc = bnxt_hwrm_func_reset(bp);
5129 rc = bnxt_hwrm_vnic_qcaps(bp);
5133 rc = bnxt_hwrm_queue_qportcfg(bp);
5137 /* Get the MAX capabilities for this function.
5138 * This function also allocates context memory for TQM rings and
5139 * informs the firmware about this allocated backing store memory.
5141 rc = bnxt_hwrm_func_qcaps(bp);
5145 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5149 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5153 bnxt_hwrm_port_mac_qcfg(bp);
5155 bnxt_hwrm_parent_pf_qcfg(bp);
5157 bnxt_hwrm_port_phy_qcaps(bp);
5159 bnxt_alloc_error_recovery_info(bp);
5160 /* Get the adapter error recovery support info */
5161 rc = bnxt_hwrm_error_recovery_qcfg(bp);
5163 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5165 bnxt_hwrm_port_led_qcaps(bp);
5171 bnxt_init_locks(struct bnxt *bp)
5175 err = pthread_mutex_init(&bp->flow_lock, NULL);
5177 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5181 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5183 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5187 err = pthread_mutex_init(&bp->health_check_lock, NULL);
5189 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5193 err = pthread_mutex_init(&bp->err_recovery_lock, NULL);
5195 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n");
5200 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5204 rc = bnxt_get_config(bp);
5208 if (!reconfig_dev) {
5209 rc = bnxt_setup_mac_addr(bp->eth_dev);
5213 rc = bnxt_restore_dflt_mac(bp);
5218 bnxt_config_vf_req_fwd(bp);
5220 rc = bnxt_hwrm_func_driver_register(bp);
5222 PMD_DRV_LOG(ERR, "Failed to register driver");
5227 if (bp->pdev->max_vfs) {
5228 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5230 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5234 rc = bnxt_hwrm_allocate_pf_only(bp);
5237 "Failed to allocate PF resources");
5243 rc = bnxt_alloc_mem(bp, reconfig_dev);
5247 rc = bnxt_setup_int(bp);
5251 rc = bnxt_request_int(bp);
5255 rc = bnxt_init_ctx_mem(bp);
5257 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5265 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5266 const char *value, void *opaque_arg)
5268 struct bnxt *bp = opaque_arg;
5269 unsigned long truflow;
5272 if (!value || !opaque_arg) {
5274 "Invalid parameter passed to truflow devargs.\n");
5278 truflow = strtoul(value, &end, 10);
5279 if (end == NULL || *end != '\0' ||
5280 (truflow == ULONG_MAX && errno == ERANGE)) {
5282 "Invalid parameter passed to truflow devargs.\n");
5286 if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5288 "Invalid value passed to truflow devargs.\n");
5293 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5294 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5296 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
5297 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
5304 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5305 const char *value, void *opaque_arg)
5307 struct bnxt *bp = opaque_arg;
5308 unsigned long flow_xstat;
5311 if (!value || !opaque_arg) {
5313 "Invalid parameter passed to flow_xstat devarg.\n");
5317 flow_xstat = strtoul(value, &end, 10);
5318 if (end == NULL || *end != '\0' ||
5319 (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5321 "Invalid parameter passed to flow_xstat devarg.\n");
5325 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5327 "Invalid value passed to flow_xstat devarg.\n");
5331 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5332 if (BNXT_FLOW_XSTATS_EN(bp))
5333 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5339 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5340 const char *value, void *opaque_arg)
5342 struct bnxt *bp = opaque_arg;
5343 unsigned long max_num_kflows;
5346 if (!value || !opaque_arg) {
5348 "Invalid parameter passed to max_num_kflows devarg.\n");
5352 max_num_kflows = strtoul(value, &end, 10);
5353 if (end == NULL || *end != '\0' ||
5354 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5356 "Invalid parameter passed to max_num_kflows devarg.\n");
5360 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5362 "Invalid value passed to max_num_kflows devarg.\n");
5366 bp->max_num_kflows = max_num_kflows;
5367 if (bp->max_num_kflows)
5368 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5375 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5376 const char *value, void *opaque_arg)
5378 struct bnxt_representor *vfr_bp = opaque_arg;
5379 unsigned long rep_is_pf;
5382 if (!value || !opaque_arg) {
5384 "Invalid parameter passed to rep_is_pf devargs.\n");
5388 rep_is_pf = strtoul(value, &end, 10);
5389 if (end == NULL || *end != '\0' ||
5390 (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5392 "Invalid parameter passed to rep_is_pf devargs.\n");
5396 if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5398 "Invalid value passed to rep_is_pf devargs.\n");
5402 vfr_bp->flags |= rep_is_pf;
5403 if (BNXT_REP_PF(vfr_bp))
5404 PMD_DRV_LOG(INFO, "PF representor\n");
5406 PMD_DRV_LOG(INFO, "VF representor\n");
5412 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5413 const char *value, void *opaque_arg)
5415 struct bnxt_representor *vfr_bp = opaque_arg;
5416 unsigned long rep_based_pf;
5419 if (!value || !opaque_arg) {
5421 "Invalid parameter passed to rep_based_pf "
5426 rep_based_pf = strtoul(value, &end, 10);
5427 if (end == NULL || *end != '\0' ||
5428 (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5430 "Invalid parameter passed to rep_based_pf "
5435 if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5437 "Invalid value passed to rep_based_pf devargs.\n");
5441 vfr_bp->rep_based_pf = rep_based_pf;
5442 vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
5444 PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5450 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5451 const char *value, void *opaque_arg)
5453 struct bnxt_representor *vfr_bp = opaque_arg;
5454 unsigned long rep_q_r2f;
5457 if (!value || !opaque_arg) {
5459 "Invalid parameter passed to rep_q_r2f "
5464 rep_q_r2f = strtoul(value, &end, 10);
5465 if (end == NULL || *end != '\0' ||
5466 (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5468 "Invalid parameter passed to rep_q_r2f "
5473 if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5475 "Invalid value passed to rep_q_r2f devargs.\n");
5479 vfr_bp->rep_q_r2f = rep_q_r2f;
5480 vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5481 PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5487 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5488 const char *value, void *opaque_arg)
5490 struct bnxt_representor *vfr_bp = opaque_arg;
5491 unsigned long rep_q_f2r;
5494 if (!value || !opaque_arg) {
5496 "Invalid parameter passed to rep_q_f2r "
5501 rep_q_f2r = strtoul(value, &end, 10);
5502 if (end == NULL || *end != '\0' ||
5503 (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5505 "Invalid parameter passed to rep_q_f2r "
5510 if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5512 "Invalid value passed to rep_q_f2r devargs.\n");
5516 vfr_bp->rep_q_f2r = rep_q_f2r;
5517 vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5518 PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5524 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5525 const char *value, void *opaque_arg)
5527 struct bnxt_representor *vfr_bp = opaque_arg;
5528 unsigned long rep_fc_r2f;
5531 if (!value || !opaque_arg) {
5533 "Invalid parameter passed to rep_fc_r2f "
5538 rep_fc_r2f = strtoul(value, &end, 10);
5539 if (end == NULL || *end != '\0' ||
5540 (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5542 "Invalid parameter passed to rep_fc_r2f "
5547 if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5549 "Invalid value passed to rep_fc_r2f devargs.\n");
5553 vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5554 vfr_bp->rep_fc_r2f = rep_fc_r2f;
5555 PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5561 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5562 const char *value, void *opaque_arg)
5564 struct bnxt_representor *vfr_bp = opaque_arg;
5565 unsigned long rep_fc_f2r;
5568 if (!value || !opaque_arg) {
5570 "Invalid parameter passed to rep_fc_f2r "
5575 rep_fc_f2r = strtoul(value, &end, 10);
5576 if (end == NULL || *end != '\0' ||
5577 (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5579 "Invalid parameter passed to rep_fc_f2r "
5584 if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5586 "Invalid value passed to rep_fc_f2r devargs.\n");
5590 vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5591 vfr_bp->rep_fc_f2r = rep_fc_f2r;
5592 PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5598 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5600 struct rte_kvargs *kvlist;
5603 if (devargs == NULL)
5606 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5611 * Handler for "truflow" devarg.
5612 * Invoked as for ex: "-a 0000:00:0d.0,host-based-truflow=1"
5614 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5615 bnxt_parse_devarg_truflow, bp);
5620 * Handler for "flow_xstat" devarg.
5621 * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5623 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5624 bnxt_parse_devarg_flow_xstat, bp);
5629 * Handler for "max_num_kflows" devarg.
5630 * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5632 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5633 bnxt_parse_devarg_max_num_kflows, bp);
5638 rte_kvargs_free(kvlist);
5642 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5646 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5647 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5650 "Failed to alloc switch domain: %d\n", rc);
5653 "Switch domain allocated %d\n",
5654 bp->switch_domain_id);
5660 /* Allocate and initialize various fields in bnxt struct that
5661 * need to be allocated/destroyed only once in the lifetime of the driver
5663 static int bnxt_drv_init(struct rte_eth_dev *eth_dev)
5665 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5666 struct bnxt *bp = eth_dev->data->dev_private;
5669 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5671 if (bnxt_vf_pciid(pci_dev->id.device_id))
5672 bp->flags |= BNXT_FLAG_VF;
5674 if (bnxt_p5_device(pci_dev->id.device_id))
5675 bp->flags |= BNXT_FLAG_CHIP_P5;
5677 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5678 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5679 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5680 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5681 bp->flags |= BNXT_FLAG_STINGRAY;
5683 if (BNXT_TRUFLOW_EN(bp)) {
5684 /* extra mbuf field is required to store CFA code from mark */
5685 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5686 .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5687 .size = sizeof(bnxt_cfa_code_dynfield_t),
5688 .align = __alignof__(bnxt_cfa_code_dynfield_t),
5690 bnxt_cfa_code_dynfield_offset =
5691 rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5692 if (bnxt_cfa_code_dynfield_offset < 0) {
5694 "Failed to register mbuf field for TruFlow mark\n");
5699 rc = bnxt_map_pci_bars(eth_dev);
5702 "Failed to initialize board rc: %x\n", rc);
5706 rc = bnxt_alloc_pf_info(bp);
5710 rc = bnxt_alloc_link_info(bp);
5714 rc = bnxt_alloc_parent_info(bp);
5718 rc = bnxt_alloc_hwrm_resources(bp);
5721 "Failed to allocate response buffer rc: %x\n", rc);
5724 rc = bnxt_alloc_leds_info(bp);
5728 rc = bnxt_alloc_cos_queues(bp);
5732 rc = bnxt_init_locks(bp);
5736 rc = bnxt_alloc_switch_domain(bp);
5744 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5746 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5747 static int version_printed;
5751 if (version_printed++ == 0)
5752 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5754 eth_dev->dev_ops = &bnxt_dev_ops;
5755 eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5756 eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5757 eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5758 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5759 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5762 * For secondary processes, we don't initialise any further
5763 * as primary has already done this work.
5765 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5768 rte_eth_copy_pci_info(eth_dev, pci_dev);
5769 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
5771 bp = eth_dev->data->dev_private;
5773 /* Parse dev arguments passed on when starting the DPDK application. */
5774 rc = bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5778 rc = bnxt_drv_init(eth_dev);
5782 rc = bnxt_init_resources(bp, false);
5786 rc = bnxt_alloc_stats_mem(bp);
5791 "Found %s device at mem %" PRIX64 ", node addr %pM\n",
5793 pci_dev->mem_resource[0].phys_addr,
5794 pci_dev->mem_resource[0].addr);
5799 bnxt_dev_uninit(eth_dev);
5804 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5813 ctx->dma = RTE_BAD_IOVA;
5814 ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5817 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5819 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5820 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5821 bp->flow_stat->rx_fc_out_tbl.ctx_id,
5822 bp->flow_stat->max_fc,
5825 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5826 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5827 bp->flow_stat->tx_fc_out_tbl.ctx_id,
5828 bp->flow_stat->max_fc,
5831 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5832 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5833 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5835 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5836 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5837 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5839 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5840 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5841 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5843 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5844 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5845 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5848 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5850 bnxt_unregister_fc_ctx_mem(bp);
5852 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5853 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5854 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5855 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5858 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5860 if (BNXT_FLOW_XSTATS_EN(bp))
5861 bnxt_uninit_fc_ctx_mem(bp);
5865 bnxt_free_error_recovery_info(struct bnxt *bp)
5867 rte_free(bp->recovery_info);
5868 bp->recovery_info = NULL;
5869 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5873 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5878 bnxt_free_mem(bp, reconfig_dev);
5880 bnxt_hwrm_func_buf_unrgtr(bp);
5881 if (bp->pf != NULL) {
5882 rte_free(bp->pf->vf_req_buf);
5883 bp->pf->vf_req_buf = NULL;
5886 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5887 bp->flags &= ~BNXT_FLAG_REGISTERED;
5888 bnxt_free_ctx_mem(bp);
5889 if (!reconfig_dev) {
5890 bnxt_free_hwrm_resources(bp);
5891 bnxt_free_error_recovery_info(bp);
5894 bnxt_uninit_ctx_mem(bp);
5896 bnxt_free_flow_stats_info(bp);
5897 if (bp->rep_info != NULL)
5898 bnxt_free_switch_domain(bp);
5899 bnxt_free_rep_info(bp);
5900 rte_free(bp->ptp_cfg);
5906 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5908 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5911 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5913 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5914 bnxt_dev_close_op(eth_dev);
5919 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5921 struct bnxt *bp = eth_dev->data->dev_private;
5922 struct rte_eth_dev *vf_rep_eth_dev;
5928 for (i = 0; i < bp->num_reps; i++) {
5929 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5930 if (!vf_rep_eth_dev)
5932 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
5933 vf_rep_eth_dev->data->port_id);
5934 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
5936 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
5937 eth_dev->data->port_id);
5938 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5943 static void bnxt_free_rep_info(struct bnxt *bp)
5945 rte_free(bp->rep_info);
5946 bp->rep_info = NULL;
5947 rte_free(bp->cfa_code_map);
5948 bp->cfa_code_map = NULL;
5951 static int bnxt_init_rep_info(struct bnxt *bp)
5958 bp->rep_info = rte_zmalloc("bnxt_rep_info",
5959 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5961 if (!bp->rep_info) {
5962 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5965 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5966 sizeof(*bp->cfa_code_map) *
5967 BNXT_MAX_CFA_CODE, 0);
5968 if (!bp->cfa_code_map) {
5969 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5970 bnxt_free_rep_info(bp);
5974 for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5975 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5977 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5979 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5980 bnxt_free_rep_info(bp);
5984 rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
5986 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
5987 bnxt_free_rep_info(bp);
5994 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5995 struct rte_eth_devargs *eth_da,
5996 struct rte_eth_dev *backing_eth_dev,
5997 const char *dev_args)
5999 struct rte_eth_dev *vf_rep_eth_dev;
6000 char name[RTE_ETH_NAME_MAX_LEN];
6001 struct bnxt *backing_bp;
6004 struct rte_kvargs *kvlist = NULL;
6006 if (eth_da->type == RTE_ETH_REPRESENTOR_NONE)
6008 if (eth_da->type != RTE_ETH_REPRESENTOR_VF) {
6009 PMD_DRV_LOG(ERR, "unsupported representor type %d\n",
6013 num_rep = eth_da->nb_representor_ports;
6014 if (num_rep > BNXT_MAX_VF_REPS) {
6015 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
6016 num_rep, BNXT_MAX_VF_REPS);
6020 if (num_rep >= RTE_MAX_ETHPORTS) {
6022 "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6023 num_rep, RTE_MAX_ETHPORTS);
6027 backing_bp = backing_eth_dev->data->dev_private;
6029 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6031 "Not a PF or trusted VF. No Representor support\n");
6032 /* Returning an error is not an option.
6033 * Applications are not handling this correctly
6038 if (bnxt_init_rep_info(backing_bp))
6041 for (i = 0; i < num_rep; i++) {
6042 struct bnxt_representor representor = {
6043 .vf_id = eth_da->representor_ports[i],
6044 .switch_domain_id = backing_bp->switch_domain_id,
6045 .parent_dev = backing_eth_dev
6048 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6049 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6050 representor.vf_id, BNXT_MAX_VF_REPS);
6054 /* representor port net_bdf_port */
6055 snprintf(name, sizeof(name), "net_%s_representor_%d",
6056 pci_dev->device.name, eth_da->representor_ports[i]);
6058 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
6061 * Handler for "rep_is_pf" devarg.
6062 * Invoked as for ex: "-a 000:00:0d.0,
6063 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6065 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
6066 bnxt_parse_devarg_rep_is_pf,
6067 (void *)&representor);
6073 * Handler for "rep_based_pf" devarg.
6074 * Invoked as for ex: "-a 000:00:0d.0,
6075 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6077 ret = rte_kvargs_process(kvlist,
6078 BNXT_DEVARG_REP_BASED_PF,
6079 bnxt_parse_devarg_rep_based_pf,
6080 (void *)&representor);
6086 * Handler for "rep_based_pf" devarg.
6087 * Invoked as for ex: "-a 000:00:0d.0,
6088 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6090 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
6091 bnxt_parse_devarg_rep_q_r2f,
6092 (void *)&representor);
6098 * Handler for "rep_based_pf" devarg.
6099 * Invoked as for ex: "-a 000:00:0d.0,
6100 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6102 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
6103 bnxt_parse_devarg_rep_q_f2r,
6104 (void *)&representor);
6110 * Handler for "rep_based_pf" devarg.
6111 * Invoked as for ex: "-a 000:00:0d.0,
6112 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6114 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
6115 bnxt_parse_devarg_rep_fc_r2f,
6116 (void *)&representor);
6122 * Handler for "rep_based_pf" devarg.
6123 * Invoked as for ex: "-a 000:00:0d.0,
6124 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6126 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
6127 bnxt_parse_devarg_rep_fc_f2r,
6128 (void *)&representor);
6135 ret = rte_eth_dev_create(&pci_dev->device, name,
6136 sizeof(struct bnxt_representor),
6138 bnxt_representor_init,
6141 PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6142 "representor %s.", name);
6146 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6147 if (!vf_rep_eth_dev) {
6148 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6149 " for VF-Rep: %s.", name);
6154 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6155 backing_eth_dev->data->port_id);
6156 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6158 backing_bp->num_reps++;
6162 rte_kvargs_free(kvlist);
6166 /* If num_rep > 1, then rollback already created
6167 * ports, since we'll be failing the probe anyway
6170 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6172 rte_kvargs_free(kvlist);
6177 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6178 struct rte_pci_device *pci_dev)
6180 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6181 struct rte_eth_dev *backing_eth_dev;
6185 if (pci_dev->device.devargs) {
6186 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6192 num_rep = eth_da.nb_representor_ports;
6193 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6196 /* We could come here after first level of probe is already invoked
6197 * as part of an application bringup(OVS-DPDK vswitchd), so first check
6198 * for already allocated eth_dev for the backing device (PF/Trusted VF)
6200 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6201 if (backing_eth_dev == NULL) {
6202 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6203 sizeof(struct bnxt),
6204 eth_dev_pci_specific_init, pci_dev,
6205 bnxt_dev_init, NULL);
6207 if (ret || !num_rep)
6210 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6212 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6213 backing_eth_dev->data->port_id);
6218 /* probe representor ports now */
6219 ret = bnxt_rep_port_probe(pci_dev, ð_da, backing_eth_dev,
6220 pci_dev->device.devargs->args);
6225 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6227 struct rte_eth_dev *eth_dev;
6229 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6231 return 0; /* Invoked typically only by OVS-DPDK, by the
6232 * time it comes here the eth_dev is already
6233 * deleted by rte_eth_dev_close(), so returning
6234 * +ve value will at least help in proper cleanup
6237 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6238 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6239 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6240 return rte_eth_dev_destroy(eth_dev,
6241 bnxt_representor_uninit);
6243 return rte_eth_dev_destroy(eth_dev,
6246 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6250 static struct rte_pci_driver bnxt_rte_pmd = {
6251 .id_table = bnxt_pci_id_map,
6252 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6253 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6256 .probe = bnxt_pci_probe,
6257 .remove = bnxt_pci_remove,
6261 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6263 if (strcmp(dev->device->driver->name, drv->driver.name))
6269 bool is_bnxt_supported(struct rte_eth_dev *dev)
6271 return is_device_supported(dev, &bnxt_rte_pmd);
6274 RTE_LOG_REGISTER_SUFFIX(bnxt_logtype_driver, driver, NOTICE);
6275 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6276 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6277 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");