1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2021 Broadcom
10 #include <ethdev_driver.h>
11 #include <ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
15 #include <rte_kvargs.h>
19 #include "bnxt_filter.h"
20 #include "bnxt_hwrm.h"
22 #include "bnxt_reps.h"
23 #include "bnxt_ring.h"
26 #include "bnxt_stats.h"
29 #include "bnxt_vnic.h"
30 #include "hsi_struct_def_dpdk.h"
31 #include "bnxt_nvm_defs.h"
32 #include "bnxt_tf_common.h"
33 #include "ulp_flow_db.h"
34 #include "rte_pmd_bnxt.h"
36 #define DRV_MODULE_NAME "bnxt"
37 static const char bnxt_version[] =
38 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
41 * The set of PCI devices this driver supports
43 static const struct rte_pci_id bnxt_pci_id_map[] = {
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
45 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
47 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
87 { .vendor_id = 0, /* sentinel */ },
90 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat"
91 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows"
92 #define BNXT_DEVARG_REPRESENTOR "representor"
93 #define BNXT_DEVARG_REP_BASED_PF "rep-based-pf"
94 #define BNXT_DEVARG_REP_IS_PF "rep-is-pf"
95 #define BNXT_DEVARG_REP_Q_R2F "rep-q-r2f"
96 #define BNXT_DEVARG_REP_Q_F2R "rep-q-f2r"
97 #define BNXT_DEVARG_REP_FC_R2F "rep-fc-r2f"
98 #define BNXT_DEVARG_REP_FC_F2R "rep-fc-f2r"
99 #define BNXT_DEVARG_APP_ID "app-id"
101 static const char *const bnxt_dev_args[] = {
102 BNXT_DEVARG_REPRESENTOR,
103 BNXT_DEVARG_FLOW_XSTAT,
104 BNXT_DEVARG_MAX_NUM_KFLOWS,
105 BNXT_DEVARG_REP_BASED_PF,
106 BNXT_DEVARG_REP_IS_PF,
107 BNXT_DEVARG_REP_Q_R2F,
108 BNXT_DEVARG_REP_Q_F2R,
109 BNXT_DEVARG_REP_FC_R2F,
110 BNXT_DEVARG_REP_FC_F2R,
116 * app-id = an non-negative 8-bit number
118 #define BNXT_DEVARG_APP_ID_INVALID(val) ((val) > 255)
121 * flow_xstat == false to disable the feature
122 * flow_xstat == true to enable the feature
124 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1)
127 * rep_is_pf == false to indicate VF representor
128 * rep_is_pf == true to indicate PF representor
130 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf) ((rep_is_pf) > 1)
133 * rep_based_pf == Physical index of the PF
135 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf) ((rep_based_pf) > 15)
137 * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
139 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f) ((rep_q_r2f) > 3)
142 * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
144 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r) ((rep_q_f2r) > 3)
147 * rep_fc_r2f == Flow control for the representor to endpoint direction
149 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f) ((rep_fc_r2f) > 1)
152 * rep_fc_f2r == Flow control for the endpoint to representor direction
154 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r) ((rep_fc_f2r) > 1)
156 int bnxt_cfa_code_dynfield_offset = -1;
159 * max_num_kflows must be >= 32
160 * and must be a power-of-2 supported value
161 * return: 1 -> invalid
164 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
166 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
171 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
172 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
173 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
174 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
175 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
176 static int bnxt_restore_vlan_filters(struct bnxt *bp);
177 static void bnxt_dev_recover(void *arg);
178 static void bnxt_free_error_recovery_info(struct bnxt *bp);
179 static void bnxt_free_rep_info(struct bnxt *bp);
181 int is_bnxt_in_error(struct bnxt *bp)
183 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
185 if (bp->flags & BNXT_FLAG_FW_RESET)
191 /***********************/
194 * High level utility functions
197 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
199 unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
200 BNXT_RSS_TBL_SIZE_P5);
202 if (!BNXT_CHIP_P5(bp))
205 return RTE_ALIGN_MUL_CEIL(num_rss_rings,
206 BNXT_RSS_ENTRIES_PER_CTX_P5) /
207 BNXT_RSS_ENTRIES_PER_CTX_P5;
210 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
212 if (!BNXT_CHIP_P5(bp))
213 return HW_HASH_INDEX_SIZE;
215 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
218 static void bnxt_free_parent_info(struct bnxt *bp)
220 rte_free(bp->parent);
224 static void bnxt_free_pf_info(struct bnxt *bp)
230 static void bnxt_free_link_info(struct bnxt *bp)
232 rte_free(bp->link_info);
233 bp->link_info = NULL;
236 static void bnxt_free_leds_info(struct bnxt *bp)
245 static void bnxt_free_flow_stats_info(struct bnxt *bp)
247 rte_free(bp->flow_stat);
248 bp->flow_stat = NULL;
251 static void bnxt_free_cos_queues(struct bnxt *bp)
253 rte_free(bp->rx_cos_queue);
254 bp->rx_cos_queue = NULL;
255 rte_free(bp->tx_cos_queue);
256 bp->tx_cos_queue = NULL;
259 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
261 bnxt_free_filter_mem(bp);
262 bnxt_free_vnic_attributes(bp);
263 bnxt_free_vnic_mem(bp);
265 /* tx/rx rings are configured as part of *_queue_setup callbacks.
266 * If the number of rings change across fw update,
267 * we don't have much choice except to warn the user.
271 bnxt_free_tx_rings(bp);
272 bnxt_free_rx_rings(bp);
274 bnxt_free_async_cp_ring(bp);
275 bnxt_free_rxtx_nq_ring(bp);
277 rte_free(bp->grp_info);
281 static int bnxt_alloc_parent_info(struct bnxt *bp)
283 bp->parent = rte_zmalloc("bnxt_parent_info",
284 sizeof(struct bnxt_parent_info), 0);
285 if (bp->parent == NULL)
291 static int bnxt_alloc_pf_info(struct bnxt *bp)
293 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
300 static int bnxt_alloc_link_info(struct bnxt *bp)
303 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
304 if (bp->link_info == NULL)
310 static int bnxt_alloc_leds_info(struct bnxt *bp)
315 bp->leds = rte_zmalloc("bnxt_leds",
316 BNXT_MAX_LED * sizeof(struct bnxt_led_info),
318 if (bp->leds == NULL)
324 static int bnxt_alloc_cos_queues(struct bnxt *bp)
327 rte_zmalloc("bnxt_rx_cosq",
328 BNXT_COS_QUEUE_COUNT *
329 sizeof(struct bnxt_cos_queue_info),
331 if (bp->rx_cos_queue == NULL)
335 rte_zmalloc("bnxt_tx_cosq",
336 BNXT_COS_QUEUE_COUNT *
337 sizeof(struct bnxt_cos_queue_info),
339 if (bp->tx_cos_queue == NULL)
345 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
347 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
348 sizeof(struct bnxt_flow_stat_info), 0);
349 if (bp->flow_stat == NULL)
355 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
359 rc = bnxt_alloc_ring_grps(bp);
363 rc = bnxt_alloc_async_ring_struct(bp);
367 rc = bnxt_alloc_vnic_mem(bp);
371 rc = bnxt_alloc_vnic_attributes(bp, reconfig);
375 rc = bnxt_alloc_filter_mem(bp);
379 rc = bnxt_alloc_async_cp_ring(bp);
383 rc = bnxt_alloc_rxtx_nq_ring(bp);
387 if (BNXT_FLOW_XSTATS_EN(bp)) {
388 rc = bnxt_alloc_flow_stats_info(bp);
396 bnxt_free_mem(bp, reconfig);
400 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
402 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
403 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
404 uint64_t rx_offloads = dev_conf->rxmode.offloads;
405 struct bnxt_rx_queue *rxq;
409 rc = bnxt_vnic_grp_alloc(bp, vnic);
413 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
414 vnic_id, vnic, vnic->fw_grp_ids);
416 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
420 /* Alloc RSS context only if RSS mode is enabled */
421 if (dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS) {
422 int j, nr_ctxs = bnxt_rss_ctxts(bp);
424 /* RSS table size in Thor is 512.
425 * Cap max Rx rings to same value
427 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
428 PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
429 bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
434 for (j = 0; j < nr_ctxs; j++) {
435 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
441 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
445 vnic->num_lb_ctxts = nr_ctxs;
449 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
450 * setting is not available at this time, it will not be
451 * configured correctly in the CFA.
453 if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
454 vnic->vlan_strip = true;
456 vnic->vlan_strip = false;
458 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
462 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
466 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
467 rxq = bp->eth_dev->data->rx_queues[j];
470 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
471 j, rxq->vnic, rxq->vnic->fw_grp_ids);
473 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
474 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
476 vnic->rx_queue_cnt++;
479 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
481 rc = bnxt_vnic_rss_configure(bp, vnic);
485 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
487 rc = bnxt_hwrm_vnic_tpa_cfg(bp, vnic,
488 (rx_offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO) ?
495 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
500 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
504 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
505 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
510 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
511 " rx_fc_in_tbl.ctx_id = %d\n",
512 bp->flow_stat->rx_fc_in_tbl.va,
513 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
514 bp->flow_stat->rx_fc_in_tbl.ctx_id);
516 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
517 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
522 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
523 " rx_fc_out_tbl.ctx_id = %d\n",
524 bp->flow_stat->rx_fc_out_tbl.va,
525 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
526 bp->flow_stat->rx_fc_out_tbl.ctx_id);
528 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
529 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
534 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
535 " tx_fc_in_tbl.ctx_id = %d\n",
536 bp->flow_stat->tx_fc_in_tbl.va,
537 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
538 bp->flow_stat->tx_fc_in_tbl.ctx_id);
540 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
541 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
546 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
547 " tx_fc_out_tbl.ctx_id = %d\n",
548 bp->flow_stat->tx_fc_out_tbl.va,
549 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
550 bp->flow_stat->tx_fc_out_tbl.ctx_id);
552 memset(bp->flow_stat->rx_fc_out_tbl.va,
554 bp->flow_stat->rx_fc_out_tbl.size);
555 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
556 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
557 bp->flow_stat->rx_fc_out_tbl.ctx_id,
558 bp->flow_stat->max_fc,
563 memset(bp->flow_stat->tx_fc_out_tbl.va,
565 bp->flow_stat->tx_fc_out_tbl.size);
566 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
567 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
568 bp->flow_stat->tx_fc_out_tbl.ctx_id,
569 bp->flow_stat->max_fc,
575 static int bnxt_alloc_ctx_mem_buf(struct bnxt *bp, char *type, size_t size,
576 struct bnxt_ctx_mem_buf_info *ctx)
581 ctx->va = rte_zmalloc_socket(type, size, 0,
582 bp->eth_dev->device->numa_node);
585 rte_mem_lock_page(ctx->va);
587 ctx->dma = rte_mem_virt2iova(ctx->va);
588 if (ctx->dma == RTE_BAD_IOVA)
594 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
596 struct rte_pci_device *pdev = bp->pdev;
597 char type[RTE_MEMZONE_NAMESIZE];
601 max_fc = bp->flow_stat->max_fc;
603 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
604 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
605 /* 4 bytes for each counter-id */
606 rc = bnxt_alloc_ctx_mem_buf(bp, type,
608 &bp->flow_stat->rx_fc_in_tbl);
612 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
613 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
614 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
615 rc = bnxt_alloc_ctx_mem_buf(bp, type,
617 &bp->flow_stat->rx_fc_out_tbl);
621 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
622 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
623 /* 4 bytes for each counter-id */
624 rc = bnxt_alloc_ctx_mem_buf(bp, type,
626 &bp->flow_stat->tx_fc_in_tbl);
630 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
631 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
632 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
633 rc = bnxt_alloc_ctx_mem_buf(bp, type,
635 &bp->flow_stat->tx_fc_out_tbl);
639 rc = bnxt_register_fc_ctx_mem(bp);
644 static int bnxt_init_ctx_mem(struct bnxt *bp)
648 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
649 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
650 !BNXT_FLOW_XSTATS_EN(bp))
653 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
657 rc = bnxt_init_fc_ctx_mem(bp);
662 static int bnxt_update_phy_setting(struct bnxt *bp)
664 struct rte_eth_link new;
667 rc = bnxt_get_hwrm_link_config(bp, &new);
669 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
674 * On BCM957508-N2100 adapters, FW will not allow any user other
675 * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
676 * always returns link up. Force phy update always in that case.
678 if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
679 rc = bnxt_set_hwrm_link_config(bp, true);
681 PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
689 static void bnxt_free_prev_ring_stats(struct bnxt *bp)
691 rte_free(bp->prev_rx_ring_stats);
692 rte_free(bp->prev_tx_ring_stats);
694 bp->prev_rx_ring_stats = NULL;
695 bp->prev_tx_ring_stats = NULL;
698 static int bnxt_alloc_prev_ring_stats(struct bnxt *bp)
700 bp->prev_rx_ring_stats = rte_zmalloc("bnxt_prev_rx_ring_stats",
701 sizeof(struct bnxt_ring_stats) *
704 if (bp->prev_rx_ring_stats == NULL)
707 bp->prev_tx_ring_stats = rte_zmalloc("bnxt_prev_tx_ring_stats",
708 sizeof(struct bnxt_ring_stats) *
711 if (bp->prev_tx_ring_stats == NULL)
717 bnxt_free_prev_ring_stats(bp);
721 static int bnxt_start_nic(struct bnxt *bp)
723 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
724 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
725 uint32_t intr_vector = 0;
726 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
727 uint32_t vec = BNXT_MISC_VEC_ID;
731 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU)
732 bp->flags |= BNXT_FLAG_JUMBO;
734 bp->flags &= ~BNXT_FLAG_JUMBO;
736 /* THOR does not support ring groups.
737 * But we will use the array to save RSS context IDs.
739 if (BNXT_CHIP_P5(bp))
740 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
742 rc = bnxt_alloc_hwrm_rings(bp);
744 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
748 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
750 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
754 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
757 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
758 if (bp->rx_cos_queue[i].id != 0xff) {
759 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
763 "Num pools more than FW profile\n");
767 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
773 rc = bnxt_mq_rx_configure(bp);
775 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
779 for (j = 0; j < bp->rx_nr_rings; j++) {
780 struct bnxt_rx_queue *rxq = bp->rx_queues[j];
782 if (!rxq->rx_deferred_start) {
783 bp->eth_dev->data->rx_queue_state[j] =
784 RTE_ETH_QUEUE_STATE_STARTED;
785 rxq->rx_started = true;
789 /* VNIC configuration */
790 for (i = 0; i < bp->nr_vnics; i++) {
791 rc = bnxt_setup_one_vnic(bp, i);
796 for (j = 0; j < bp->tx_nr_rings; j++) {
797 struct bnxt_tx_queue *txq = bp->tx_queues[j];
799 if (!txq->tx_deferred_start) {
800 bp->eth_dev->data->tx_queue_state[j] =
801 RTE_ETH_QUEUE_STATE_STARTED;
802 txq->tx_started = true;
806 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
809 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
813 /* check and configure queue intr-vector mapping */
814 if ((rte_intr_cap_multiple(intr_handle) ||
815 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
816 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
817 intr_vector = bp->eth_dev->data->nb_rx_queues;
818 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
819 if (intr_vector > bp->rx_cp_nr_rings) {
820 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
824 rc = rte_intr_efd_enable(intr_handle, intr_vector);
829 if (rte_intr_dp_is_en(intr_handle)) {
830 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
831 bp->eth_dev->data->nb_rx_queues)) {
832 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
833 " intr_vec", bp->eth_dev->data->nb_rx_queues);
837 PMD_DRV_LOG(DEBUG, "intr_handle->nb_efd = %d "
838 "intr_handle->max_intr = %d\n",
839 rte_intr_nb_efd_get(intr_handle),
840 rte_intr_max_intr_get(intr_handle));
841 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
843 rte_intr_vec_list_index_set(intr_handle,
844 queue_id, vec + BNXT_RX_VEC_START);
845 if (vec < base + rte_intr_nb_efd_get(intr_handle)
851 /* enable uio/vfio intr/eventfd mapping */
852 rc = rte_intr_enable(intr_handle);
853 #ifndef RTE_EXEC_ENV_FREEBSD
854 /* In FreeBSD OS, nic_uio driver does not support interrupts */
859 rc = bnxt_update_phy_setting(bp);
863 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
865 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
870 /* Some of the error status returned by FW may not be from errno.h */
877 static int bnxt_shutdown_nic(struct bnxt *bp)
879 bnxt_free_all_hwrm_resources(bp);
880 bnxt_free_all_filters(bp);
881 bnxt_free_all_vnics(bp);
886 * Device configuration and status function
889 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
891 uint32_t link_speed = 0;
892 uint32_t speed_capa = 0;
894 if (bp->link_info == NULL)
897 link_speed = bp->link_info->support_speeds;
899 /* If PAM4 is configured, use PAM4 supported speed */
900 if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
901 link_speed = bp->link_info->support_pam4_speeds;
903 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
904 speed_capa |= RTE_ETH_LINK_SPEED_100M;
905 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
906 speed_capa |= RTE_ETH_LINK_SPEED_100M_HD;
907 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
908 speed_capa |= RTE_ETH_LINK_SPEED_1G;
909 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
910 speed_capa |= RTE_ETH_LINK_SPEED_2_5G;
911 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
912 speed_capa |= RTE_ETH_LINK_SPEED_10G;
913 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
914 speed_capa |= RTE_ETH_LINK_SPEED_20G;
915 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
916 speed_capa |= RTE_ETH_LINK_SPEED_25G;
917 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
918 speed_capa |= RTE_ETH_LINK_SPEED_40G;
919 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
920 speed_capa |= RTE_ETH_LINK_SPEED_50G;
921 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
922 speed_capa |= RTE_ETH_LINK_SPEED_100G;
923 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
924 speed_capa |= RTE_ETH_LINK_SPEED_50G;
925 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
926 speed_capa |= RTE_ETH_LINK_SPEED_100G;
927 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
928 speed_capa |= RTE_ETH_LINK_SPEED_200G;
930 if (bp->link_info->auto_mode ==
931 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
932 speed_capa |= RTE_ETH_LINK_SPEED_FIXED;
937 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
938 struct rte_eth_dev_info *dev_info)
940 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
941 struct bnxt *bp = eth_dev->data->dev_private;
942 uint16_t max_vnics, i, j, vpool, vrxq;
943 unsigned int max_rx_rings;
946 rc = is_bnxt_in_error(bp);
951 dev_info->max_mac_addrs = RTE_MIN(bp->max_l2_ctx, RTE_ETH_NUM_RECEIVE_MAC_ADDR);
952 dev_info->max_hash_mac_addrs = 0;
954 /* PF/VF specifics */
956 dev_info->max_vfs = pdev->max_vfs;
958 max_rx_rings = bnxt_max_rings(bp);
959 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
960 dev_info->max_rx_queues = max_rx_rings;
961 dev_info->max_tx_queues = max_rx_rings;
962 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
963 dev_info->hash_key_size = HW_HASH_KEY_SIZE;
964 max_vnics = bp->max_vnics;
967 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
968 dev_info->max_mtu = BNXT_MAX_MTU;
970 /* Fast path specifics */
971 dev_info->min_rx_bufsize = 1;
972 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
974 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
975 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
976 dev_info->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_TIMESTAMP;
977 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_VLAN_RX_STRIP)
978 dev_info->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_VLAN_STRIP;
979 dev_info->tx_queue_offload_capa = RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE;
980 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
981 dev_info->tx_queue_offload_capa;
982 if (bp->fw_cap & BNXT_FW_CAP_VLAN_TX_INSERT)
983 dev_info->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_VLAN_INSERT;
984 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
986 dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
987 dev_info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
988 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
989 dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
991 dev_info->default_rxconf = (struct rte_eth_rxconf) {
997 .rx_free_thresh = 32,
998 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
1001 dev_info->default_txconf = (struct rte_eth_txconf) {
1007 .tx_free_thresh = 32,
1010 eth_dev->data->dev_conf.intr_conf.lsc = 1;
1012 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
1013 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
1014 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
1015 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
1017 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
1018 dev_info->switch_info.name = eth_dev->device->name;
1019 dev_info->switch_info.domain_id = bp->switch_domain_id;
1020 dev_info->switch_info.port_id =
1021 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
1022 BNXT_SWITCH_PORT_ID_TRUSTED_VF;
1026 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
1027 * need further investigation.
1030 /* VMDq resources */
1031 vpool = 64; /* RTE_ETH_64_POOLS */
1032 vrxq = 128; /* RTE_ETH_VMDQ_DCB_NUM_QUEUES */
1033 for (i = 0; i < 4; vpool >>= 1, i++) {
1034 if (max_vnics > vpool) {
1035 for (j = 0; j < 5; vrxq >>= 1, j++) {
1036 if (dev_info->max_rx_queues > vrxq) {
1042 /* Not enough resources to support VMDq */
1046 /* Not enough resources to support VMDq */
1050 dev_info->max_vmdq_pools = vpool;
1051 dev_info->vmdq_queue_num = vrxq;
1053 dev_info->vmdq_pool_base = 0;
1054 dev_info->vmdq_queue_base = 0;
1059 /* Configure the device based on the configuration provided */
1060 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1062 struct bnxt *bp = eth_dev->data->dev_private;
1063 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1064 struct rte_eth_rss_conf *rss_conf = ð_dev->data->dev_conf.rx_adv_conf.rss_conf;
1067 bp->rx_queues = (void *)eth_dev->data->rx_queues;
1068 bp->tx_queues = (void *)eth_dev->data->tx_queues;
1069 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1070 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1072 rc = is_bnxt_in_error(bp);
1076 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1077 rc = bnxt_hwrm_check_vf_rings(bp);
1079 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1083 /* If a resource has already been allocated - in this case
1084 * it is the async completion ring, free it. Reallocate it after
1085 * resource reservation. This will ensure the resource counts
1086 * are calculated correctly.
1089 pthread_mutex_lock(&bp->def_cp_lock);
1091 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1092 bnxt_disable_int(bp);
1093 bnxt_free_cp_ring(bp, bp->async_cp_ring);
1096 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1098 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1099 pthread_mutex_unlock(&bp->def_cp_lock);
1103 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1104 rc = bnxt_alloc_async_cp_ring(bp);
1106 pthread_mutex_unlock(&bp->def_cp_lock);
1109 bnxt_enable_int(bp);
1112 pthread_mutex_unlock(&bp->def_cp_lock);
1115 /* Inherit new configurations */
1116 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1117 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1118 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1119 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1120 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1122 goto resource_error;
1124 if (BNXT_HAS_RING_GRPS(bp) &&
1125 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1126 goto resource_error;
1128 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS) &&
1129 bp->max_vnics < eth_dev->data->nb_rx_queues)
1130 goto resource_error;
1132 bp->rx_cp_nr_rings = bp->rx_nr_rings;
1133 bp->tx_cp_nr_rings = bp->tx_nr_rings;
1135 if (eth_dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)
1136 rx_offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
1137 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1139 /* application provides the hash key to program */
1140 if (rss_conf->rss_key != NULL) {
1141 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE)
1142 PMD_DRV_LOG(WARNING, "port %u RSS key len must be %d bytes long",
1143 eth_dev->data->port_id, HW_HASH_KEY_SIZE);
1145 memcpy(bp->rss_conf.rss_key, rss_conf->rss_key, HW_HASH_KEY_SIZE);
1147 bp->rss_conf.rss_key_len = HW_HASH_KEY_SIZE;
1148 bp->rss_conf.rss_hf = rss_conf->rss_hf;
1150 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1156 "Insufficient resources to support requested config\n");
1158 "Num Queues Requested: Tx %d, Rx %d\n",
1159 eth_dev->data->nb_tx_queues,
1160 eth_dev->data->nb_rx_queues);
1162 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1163 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1164 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1168 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1170 struct rte_eth_link *link = ð_dev->data->dev_link;
1172 if (link->link_status)
1173 PMD_DRV_LOG(DEBUG, "Port %d Link Up - speed %u Mbps - %s\n",
1174 eth_dev->data->port_id,
1175 (uint32_t)link->link_speed,
1176 (link->link_duplex == RTE_ETH_LINK_FULL_DUPLEX) ?
1177 ("full-duplex") : ("half-duplex\n"));
1179 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1180 eth_dev->data->port_id);
1184 * Determine whether the current configuration requires support for scattered
1185 * receive; return 1 if scattered receive is required and 0 if not.
1187 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1189 uint32_t overhead = BNXT_MAX_PKT_LEN - BNXT_MAX_MTU;
1193 if (eth_dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_SCATTER)
1196 if (eth_dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO)
1199 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1200 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1202 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1203 RTE_PKTMBUF_HEADROOM);
1204 if (eth_dev->data->mtu + overhead > buf_size)
1210 static eth_rx_burst_t
1211 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1213 struct bnxt *bp = eth_dev->data->dev_private;
1215 /* Disable vector mode RX for Stingray2 for now */
1216 if (BNXT_CHIP_SR2(bp)) {
1217 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1218 return bnxt_recv_pkts;
1221 #if (defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)) && \
1222 !defined(RTE_LIBRTE_IEEE1588)
1224 /* Vector mode receive cannot be enabled if scattered rx is in use. */
1225 if (eth_dev->data->scattered_rx)
1229 * Vector mode receive cannot be enabled if Truflow is enabled or if
1230 * asynchronous completions and receive completions can be placed in
1231 * the same completion ring.
1233 if (BNXT_TRUFLOW_EN(bp) || !BNXT_NUM_ASYNC_CPR(bp))
1237 * Vector mode receive cannot be enabled if any receive offloads outside
1238 * a limited subset have been enabled.
1240 if (eth_dev->data->dev_conf.rxmode.offloads &
1241 ~(RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
1242 RTE_ETH_RX_OFFLOAD_KEEP_CRC |
1243 RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
1244 RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
1245 RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
1246 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1247 RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM |
1248 RTE_ETH_RX_OFFLOAD_RSS_HASH |
1249 RTE_ETH_RX_OFFLOAD_VLAN_FILTER))
1252 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1253 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1254 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1256 "Using AVX2 vector mode receive for port %d\n",
1257 eth_dev->data->port_id);
1258 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1259 return bnxt_recv_pkts_vec_avx2;
1262 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1264 "Using SSE vector mode receive for port %d\n",
1265 eth_dev->data->port_id);
1266 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1267 return bnxt_recv_pkts_vec;
1271 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1272 eth_dev->data->port_id);
1274 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1275 eth_dev->data->port_id,
1276 eth_dev->data->scattered_rx,
1277 eth_dev->data->dev_conf.rxmode.offloads);
1279 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1280 return bnxt_recv_pkts;
1283 static eth_tx_burst_t
1284 bnxt_transmit_function(struct rte_eth_dev *eth_dev)
1286 struct bnxt *bp = eth_dev->data->dev_private;
1288 /* Disable vector mode TX for Stingray2 for now */
1289 if (BNXT_CHIP_SR2(bp))
1290 return bnxt_xmit_pkts;
1292 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) && \
1293 !defined(RTE_LIBRTE_IEEE1588)
1294 uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1297 * Vector mode transmit can be enabled only if not using scatter rx
1300 if (eth_dev->data->scattered_rx ||
1301 (offloads & ~RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) ||
1302 BNXT_TRUFLOW_EN(bp))
1305 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1306 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1307 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1309 "Using AVX2 vector mode transmit for port %d\n",
1310 eth_dev->data->port_id);
1311 return bnxt_xmit_pkts_vec_avx2;
1314 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1316 "Using SSE vector mode transmit for port %d\n",
1317 eth_dev->data->port_id);
1318 return bnxt_xmit_pkts_vec;
1322 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1323 eth_dev->data->port_id);
1325 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1326 eth_dev->data->port_id,
1327 eth_dev->data->scattered_rx,
1330 return bnxt_xmit_pkts;
1333 static int bnxt_handle_if_change_status(struct bnxt *bp)
1337 /* Since fw has undergone a reset and lost all contexts,
1338 * set fatal flag to not issue hwrm during cleanup
1340 bp->flags |= BNXT_FLAG_FATAL_ERROR;
1341 bnxt_uninit_resources(bp, true);
1343 /* clear fatal flag so that re-init happens */
1344 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1345 rc = bnxt_init_resources(bp, true);
1347 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1352 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1354 struct bnxt *bp = eth_dev->data->dev_private;
1357 if (!BNXT_SINGLE_PF(bp))
1360 if (!bp->link_info->link_up)
1361 rc = bnxt_set_hwrm_link_config(bp, true);
1363 eth_dev->data->dev_link.link_status = 1;
1365 bnxt_print_link_info(eth_dev);
1369 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1371 struct bnxt *bp = eth_dev->data->dev_private;
1373 if (!BNXT_SINGLE_PF(bp))
1376 eth_dev->data->dev_link.link_status = 0;
1377 bnxt_set_hwrm_link_config(bp, false);
1378 bp->link_info->link_up = 0;
1383 static void bnxt_free_switch_domain(struct bnxt *bp)
1387 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)))
1390 rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1392 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1393 bp->switch_domain_id, rc);
1396 static void bnxt_ptp_get_current_time(void *arg)
1398 struct bnxt *bp = arg;
1399 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1402 rc = is_bnxt_in_error(bp);
1409 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1410 &ptp->current_time);
1412 rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1414 PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n");
1415 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1419 static int bnxt_schedule_ptp_alarm(struct bnxt *bp)
1421 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1424 if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED)
1427 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1428 &ptp->current_time);
1430 rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1434 static void bnxt_cancel_ptp_alarm(struct bnxt *bp)
1436 if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) {
1437 rte_eal_alarm_cancel(bnxt_ptp_get_current_time, (void *)bp);
1438 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1442 static void bnxt_ptp_stop(struct bnxt *bp)
1444 bnxt_cancel_ptp_alarm(bp);
1445 bp->flags2 &= ~BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1448 static int bnxt_ptp_start(struct bnxt *bp)
1452 rc = bnxt_schedule_ptp_alarm(bp);
1454 PMD_DRV_LOG(ERR, "Failed to schedule PTP alarm\n");
1456 bp->flags2 |= BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1457 bp->flags2 |= BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1463 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev)
1465 struct bnxt *bp = eth_dev->data->dev_private;
1466 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1467 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1468 struct rte_eth_link link;
1471 eth_dev->data->dev_started = 0;
1473 /* Prevent crashes when queues are still in use */
1474 bnxt_stop_rxtx(eth_dev);
1476 bnxt_disable_int(bp);
1478 /* disable uio/vfio intr/eventfd mapping */
1479 rte_intr_disable(intr_handle);
1481 /* Stop the child representors for this device */
1482 ret = bnxt_rep_stop_all(bp);
1486 /* delete the bnxt ULP port details */
1487 bnxt_ulp_port_deinit(bp);
1489 bnxt_cancel_fw_health_check(bp);
1491 if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1492 bnxt_cancel_ptp_alarm(bp);
1494 /* Do not bring link down during reset recovery */
1495 if (!is_bnxt_in_error(bp)) {
1496 bnxt_dev_set_link_down_op(eth_dev);
1497 /* Wait for link to be reset */
1498 if (BNXT_SINGLE_PF(bp))
1500 /* clear the recorded link status */
1501 memset(&link, 0, sizeof(link));
1502 rte_eth_linkstatus_set(eth_dev, &link);
1505 /* Clean queue intr-vector mapping */
1506 rte_intr_efd_disable(intr_handle);
1507 rte_intr_vec_list_free(intr_handle);
1509 bnxt_hwrm_port_clr_stats(bp);
1510 bnxt_free_tx_mbufs(bp);
1511 bnxt_free_rx_mbufs(bp);
1512 /* Process any remaining notifications in default completion queue */
1513 bnxt_int_handler(eth_dev);
1514 bnxt_shutdown_nic(bp);
1515 bnxt_hwrm_if_change(bp, false);
1517 bnxt_free_prev_ring_stats(bp);
1518 rte_free(bp->mark_table);
1519 bp->mark_table = NULL;
1521 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1522 bp->rx_cosq_cnt = 0;
1523 /* All filters are deleted on a port stop. */
1524 if (BNXT_FLOW_XSTATS_EN(bp))
1525 bp->flow_stat->flow_count = 0;
1527 eth_dev->data->scattered_rx = 0;
1532 /* Unload the driver, release resources */
1533 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1535 struct bnxt *bp = eth_dev->data->dev_private;
1537 pthread_mutex_lock(&bp->err_recovery_lock);
1538 if (bp->flags & BNXT_FLAG_FW_RESET) {
1540 "Adapter recovering from error..Please retry\n");
1541 pthread_mutex_unlock(&bp->err_recovery_lock);
1544 pthread_mutex_unlock(&bp->err_recovery_lock);
1546 return bnxt_dev_stop(eth_dev);
1549 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1551 struct bnxt *bp = eth_dev->data->dev_private;
1552 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1554 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1556 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1557 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1561 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1563 "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1564 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1567 rc = bnxt_hwrm_if_change(bp, true);
1568 if (rc == 0 || rc != -EAGAIN)
1571 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1572 } while (retry_cnt--);
1577 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1578 rc = bnxt_handle_if_change_status(bp);
1583 bnxt_enable_int(bp);
1585 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1587 rc = bnxt_start_nic(bp);
1591 rc = bnxt_alloc_prev_ring_stats(bp);
1595 eth_dev->data->dev_started = 1;
1597 bnxt_link_update_op(eth_dev, 1);
1599 if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
1600 vlan_mask |= RTE_ETH_VLAN_FILTER_MASK;
1601 if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
1602 vlan_mask |= RTE_ETH_VLAN_STRIP_MASK;
1603 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1607 /* Initialize bnxt ULP port details */
1608 rc = bnxt_ulp_port_init(bp);
1612 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1613 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1615 bnxt_schedule_fw_health_check(bp);
1617 if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1618 bnxt_schedule_ptp_alarm(bp);
1623 bnxt_dev_stop(eth_dev);
1628 bnxt_uninit_locks(struct bnxt *bp)
1630 pthread_mutex_destroy(&bp->flow_lock);
1631 pthread_mutex_destroy(&bp->def_cp_lock);
1632 pthread_mutex_destroy(&bp->health_check_lock);
1633 pthread_mutex_destroy(&bp->err_recovery_lock);
1635 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
1636 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
1640 static void bnxt_drv_uninit(struct bnxt *bp)
1642 bnxt_free_leds_info(bp);
1643 bnxt_free_cos_queues(bp);
1644 bnxt_free_link_info(bp);
1645 bnxt_free_parent_info(bp);
1646 bnxt_uninit_locks(bp);
1648 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1649 bp->tx_mem_zone = NULL;
1650 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1651 bp->rx_mem_zone = NULL;
1653 bnxt_free_vf_info(bp);
1654 bnxt_free_pf_info(bp);
1656 rte_free(bp->grp_info);
1657 bp->grp_info = NULL;
1660 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1662 struct bnxt *bp = eth_dev->data->dev_private;
1665 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1668 pthread_mutex_lock(&bp->err_recovery_lock);
1669 if (bp->flags & BNXT_FLAG_FW_RESET) {
1671 "Adapter recovering from error...Please retry\n");
1672 pthread_mutex_unlock(&bp->err_recovery_lock);
1675 pthread_mutex_unlock(&bp->err_recovery_lock);
1677 /* cancel the recovery handler before remove dev */
1678 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1679 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1680 bnxt_cancel_fc_thread(bp);
1682 if (eth_dev->data->dev_started)
1683 ret = bnxt_dev_stop(eth_dev);
1685 bnxt_uninit_resources(bp, false);
1687 bnxt_drv_uninit(bp);
1692 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1695 struct bnxt *bp = eth_dev->data->dev_private;
1696 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1697 struct bnxt_vnic_info *vnic;
1698 struct bnxt_filter_info *filter, *temp_filter;
1701 if (is_bnxt_in_error(bp))
1705 * Loop through all VNICs from the specified filter flow pools to
1706 * remove the corresponding MAC addr filter
1708 for (i = 0; i < bp->nr_vnics; i++) {
1709 if (!(pool_mask & (1ULL << i)))
1712 vnic = &bp->vnic_info[i];
1713 filter = STAILQ_FIRST(&vnic->filter);
1715 temp_filter = STAILQ_NEXT(filter, next);
1716 if (filter->mac_index == index) {
1717 STAILQ_REMOVE(&vnic->filter, filter,
1718 bnxt_filter_info, next);
1719 bnxt_hwrm_clear_l2_filter(bp, filter);
1720 bnxt_free_filter(bp, filter);
1722 filter = temp_filter;
1727 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1728 struct rte_ether_addr *mac_addr, uint32_t index,
1731 struct bnxt_filter_info *filter;
1734 /* Attach requested MAC address to the new l2_filter */
1735 STAILQ_FOREACH(filter, &vnic->filter, next) {
1736 if (filter->mac_index == index) {
1738 "MAC addr already existed for pool %d\n",
1744 filter = bnxt_alloc_filter(bp);
1746 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1750 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1751 * if the MAC that's been programmed now is a different one, then,
1752 * copy that addr to filter->l2_addr
1755 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1756 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1758 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1760 filter->mac_index = index;
1761 if (filter->mac_index == 0)
1762 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1764 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1766 bnxt_free_filter(bp, filter);
1772 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1773 struct rte_ether_addr *mac_addr,
1774 uint32_t index, uint32_t pool)
1776 struct bnxt *bp = eth_dev->data->dev_private;
1777 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1780 rc = is_bnxt_in_error(bp);
1784 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1785 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1790 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1794 /* Filter settings will get applied when port is started */
1795 if (!eth_dev->data->dev_started)
1798 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1803 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1806 struct bnxt *bp = eth_dev->data->dev_private;
1807 struct rte_eth_link new;
1808 int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1809 BNXT_MIN_LINK_WAIT_CNT;
1811 rc = is_bnxt_in_error(bp);
1815 memset(&new, 0, sizeof(new));
1817 if (bp->link_info == NULL)
1821 /* Retrieve link info from hardware */
1822 rc = bnxt_get_hwrm_link_config(bp, &new);
1824 new.link_speed = RTE_ETH_LINK_SPEED_100M;
1825 new.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
1827 "Failed to retrieve link rc = 0x%x!\n", rc);
1831 if (!wait_to_complete || new.link_status)
1834 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1837 /* Only single function PF can bring phy down.
1838 * When port is stopped, report link down for VF/MH/NPAR functions.
1840 if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1841 memset(&new, 0, sizeof(new));
1844 /* Timed out or success */
1845 if (new.link_status != eth_dev->data->dev_link.link_status ||
1846 new.link_speed != eth_dev->data->dev_link.link_speed) {
1847 rte_eth_linkstatus_set(eth_dev, &new);
1848 bnxt_print_link_info(eth_dev);
1854 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1856 struct bnxt *bp = eth_dev->data->dev_private;
1857 struct bnxt_vnic_info *vnic;
1861 rc = is_bnxt_in_error(bp);
1865 /* Filter settings will get applied when port is started */
1866 if (!eth_dev->data->dev_started)
1869 if (bp->vnic_info == NULL)
1872 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1874 old_flags = vnic->flags;
1875 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1876 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1878 vnic->flags = old_flags;
1883 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1885 struct bnxt *bp = eth_dev->data->dev_private;
1886 struct bnxt_vnic_info *vnic;
1890 rc = is_bnxt_in_error(bp);
1894 /* Filter settings will get applied when port is started */
1895 if (!eth_dev->data->dev_started)
1898 if (bp->vnic_info == NULL)
1901 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1903 old_flags = vnic->flags;
1904 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1905 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1907 vnic->flags = old_flags;
1912 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1914 struct bnxt *bp = eth_dev->data->dev_private;
1915 struct bnxt_vnic_info *vnic;
1919 rc = is_bnxt_in_error(bp);
1923 /* Filter settings will get applied when port is started */
1924 if (!eth_dev->data->dev_started)
1927 if (bp->vnic_info == NULL)
1930 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1932 old_flags = vnic->flags;
1933 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1934 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1936 vnic->flags = old_flags;
1941 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1943 struct bnxt *bp = eth_dev->data->dev_private;
1944 struct bnxt_vnic_info *vnic;
1948 rc = is_bnxt_in_error(bp);
1952 /* Filter settings will get applied when port is started */
1953 if (!eth_dev->data->dev_started)
1956 if (bp->vnic_info == NULL)
1959 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1961 old_flags = vnic->flags;
1962 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1963 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1965 vnic->flags = old_flags;
1970 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1971 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1973 if (qid >= bp->rx_nr_rings)
1976 return bp->eth_dev->data->rx_queues[qid];
1979 /* Return rxq corresponding to a given rss table ring/group ID. */
1980 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1982 struct bnxt_rx_queue *rxq;
1985 if (!BNXT_HAS_RING_GRPS(bp)) {
1986 for (i = 0; i < bp->rx_nr_rings; i++) {
1987 rxq = bp->eth_dev->data->rx_queues[i];
1988 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1992 for (i = 0; i < bp->rx_nr_rings; i++) {
1993 if (bp->grp_info[i].fw_grp_id == fwr)
1998 return INVALID_HW_RING_ID;
2001 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
2002 struct rte_eth_rss_reta_entry64 *reta_conf,
2005 struct bnxt *bp = eth_dev->data->dev_private;
2006 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2007 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2008 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
2012 rc = is_bnxt_in_error(bp);
2016 if (!vnic->rss_table)
2019 if (!(dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG))
2022 if (reta_size != tbl_size) {
2023 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2024 "(%d) must equal the size supported by the hardware "
2025 "(%d)\n", reta_size, tbl_size);
2029 for (i = 0; i < reta_size; i++) {
2030 struct bnxt_rx_queue *rxq;
2032 idx = i / RTE_ETH_RETA_GROUP_SIZE;
2033 sft = i % RTE_ETH_RETA_GROUP_SIZE;
2035 if (!(reta_conf[idx].mask & (1ULL << sft)))
2038 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
2040 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
2044 if (BNXT_CHIP_P5(bp)) {
2045 vnic->rss_table[i * 2] =
2046 rxq->rx_ring->rx_ring_struct->fw_ring_id;
2047 vnic->rss_table[i * 2 + 1] =
2048 rxq->cp_ring->cp_ring_struct->fw_ring_id;
2050 vnic->rss_table[i] =
2051 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
2055 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2059 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
2060 struct rte_eth_rss_reta_entry64 *reta_conf,
2063 struct bnxt *bp = eth_dev->data->dev_private;
2064 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2065 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
2066 uint16_t idx, sft, i;
2069 rc = is_bnxt_in_error(bp);
2075 if (!vnic->rss_table)
2078 if (reta_size != tbl_size) {
2079 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2080 "(%d) must equal the size supported by the hardware "
2081 "(%d)\n", reta_size, tbl_size);
2085 for (idx = 0, i = 0; i < reta_size; i++) {
2086 idx = i / RTE_ETH_RETA_GROUP_SIZE;
2087 sft = i % RTE_ETH_RETA_GROUP_SIZE;
2089 if (reta_conf[idx].mask & (1ULL << sft)) {
2092 if (BNXT_CHIP_P5(bp))
2093 qid = bnxt_rss_to_qid(bp,
2094 vnic->rss_table[i * 2]);
2096 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
2098 if (qid == INVALID_HW_RING_ID) {
2099 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
2102 reta_conf[idx].reta[sft] = qid;
2109 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
2110 struct rte_eth_rss_conf *rss_conf)
2112 struct bnxt *bp = eth_dev->data->dev_private;
2113 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2114 struct bnxt_vnic_info *vnic;
2117 rc = is_bnxt_in_error(bp);
2122 * If RSS enablement were different than dev_configure,
2123 * then return -EINVAL
2125 if (dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
2126 if (!rss_conf->rss_hf)
2127 PMD_DRV_LOG(ERR, "Hash type NONE\n");
2129 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
2133 bp->flags |= BNXT_FLAG_UPDATE_HASH;
2135 /* Update the default RSS VNIC(s) */
2136 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2137 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
2139 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
2140 RTE_ETH_RSS_LEVEL(rss_conf->rss_hf));
2142 /* Cache the hash function */
2143 bp->rss_conf.rss_hf = rss_conf->rss_hf;
2146 * If hashkey is not specified, use the previously configured
2149 if (!rss_conf->rss_key)
2152 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
2154 "Invalid hashkey length, should be %d bytes\n",
2158 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
2160 /* Cache the hash key */
2161 memcpy(bp->rss_conf.rss_key, rss_conf->rss_key, HW_HASH_KEY_SIZE);
2164 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2168 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
2169 struct rte_eth_rss_conf *rss_conf)
2171 struct bnxt *bp = eth_dev->data->dev_private;
2172 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2174 uint32_t hash_types;
2176 rc = is_bnxt_in_error(bp);
2180 /* RSS configuration is the same for all VNICs */
2181 if (vnic && vnic->rss_hash_key) {
2182 if (rss_conf->rss_key) {
2183 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
2184 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
2185 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
2188 hash_types = vnic->hash_type;
2189 rss_conf->rss_hf = 0;
2190 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
2191 rss_conf->rss_hf |= RTE_ETH_RSS_IPV4;
2192 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
2194 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
2195 rss_conf->rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_TCP;
2197 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
2199 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
2200 rss_conf->rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_UDP;
2202 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
2204 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
2205 rss_conf->rss_hf |= RTE_ETH_RSS_IPV6;
2206 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
2208 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
2209 rss_conf->rss_hf |= RTE_ETH_RSS_NONFRAG_IPV6_TCP;
2211 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
2213 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
2214 rss_conf->rss_hf |= RTE_ETH_RSS_NONFRAG_IPV6_UDP;
2216 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2220 bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2224 "Unknown RSS config from firmware (%08x), RSS disabled",
2229 rss_conf->rss_hf = 0;
2234 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2235 struct rte_eth_fc_conf *fc_conf)
2237 struct bnxt *bp = dev->data->dev_private;
2238 struct rte_eth_link link_info;
2241 rc = is_bnxt_in_error(bp);
2245 rc = bnxt_get_hwrm_link_config(bp, &link_info);
2249 memset(fc_conf, 0, sizeof(*fc_conf));
2250 if (bp->link_info->auto_pause)
2251 fc_conf->autoneg = 1;
2252 switch (bp->link_info->pause) {
2254 fc_conf->mode = RTE_ETH_FC_NONE;
2256 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2257 fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
2259 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2260 fc_conf->mode = RTE_ETH_FC_RX_PAUSE;
2262 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2263 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2264 fc_conf->mode = RTE_ETH_FC_FULL;
2270 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2271 struct rte_eth_fc_conf *fc_conf)
2273 struct bnxt *bp = dev->data->dev_private;
2276 rc = is_bnxt_in_error(bp);
2280 if (!BNXT_SINGLE_PF(bp)) {
2282 "Flow Control Settings cannot be modified on VF or on shared PF\n");
2286 switch (fc_conf->mode) {
2287 case RTE_ETH_FC_NONE:
2288 bp->link_info->auto_pause = 0;
2289 bp->link_info->force_pause = 0;
2291 case RTE_ETH_FC_RX_PAUSE:
2292 if (fc_conf->autoneg) {
2293 bp->link_info->auto_pause =
2294 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2295 bp->link_info->force_pause = 0;
2297 bp->link_info->auto_pause = 0;
2298 bp->link_info->force_pause =
2299 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2302 case RTE_ETH_FC_TX_PAUSE:
2303 if (fc_conf->autoneg) {
2304 bp->link_info->auto_pause =
2305 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2306 bp->link_info->force_pause = 0;
2308 bp->link_info->auto_pause = 0;
2309 bp->link_info->force_pause =
2310 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2313 case RTE_ETH_FC_FULL:
2314 if (fc_conf->autoneg) {
2315 bp->link_info->auto_pause =
2316 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2317 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2318 bp->link_info->force_pause = 0;
2320 bp->link_info->auto_pause = 0;
2321 bp->link_info->force_pause =
2322 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2323 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2327 return bnxt_set_hwrm_link_config(bp, true);
2330 /* Add UDP tunneling port */
2332 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2333 struct rte_eth_udp_tunnel *udp_tunnel)
2335 struct bnxt *bp = eth_dev->data->dev_private;
2336 uint16_t tunnel_type = 0;
2339 rc = is_bnxt_in_error(bp);
2343 switch (udp_tunnel->prot_type) {
2344 case RTE_ETH_TUNNEL_TYPE_VXLAN:
2345 if (bp->vxlan_port_cnt) {
2346 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2347 udp_tunnel->udp_port);
2348 if (bp->vxlan_port != udp_tunnel->udp_port) {
2349 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2352 bp->vxlan_port_cnt++;
2356 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2358 case RTE_ETH_TUNNEL_TYPE_GENEVE:
2359 if (bp->geneve_port_cnt) {
2360 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2361 udp_tunnel->udp_port);
2362 if (bp->geneve_port != udp_tunnel->udp_port) {
2363 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2366 bp->geneve_port_cnt++;
2370 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2373 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2376 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2383 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN)
2384 bp->vxlan_port_cnt++;
2387 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE)
2388 bp->geneve_port_cnt++;
2394 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2395 struct rte_eth_udp_tunnel *udp_tunnel)
2397 struct bnxt *bp = eth_dev->data->dev_private;
2398 uint16_t tunnel_type = 0;
2402 rc = is_bnxt_in_error(bp);
2406 switch (udp_tunnel->prot_type) {
2407 case RTE_ETH_TUNNEL_TYPE_VXLAN:
2408 if (!bp->vxlan_port_cnt) {
2409 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2412 if (bp->vxlan_port != udp_tunnel->udp_port) {
2413 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2414 udp_tunnel->udp_port, bp->vxlan_port);
2417 if (--bp->vxlan_port_cnt)
2421 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2422 port = bp->vxlan_fw_dst_port_id;
2424 case RTE_ETH_TUNNEL_TYPE_GENEVE:
2425 if (!bp->geneve_port_cnt) {
2426 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2429 if (bp->geneve_port != udp_tunnel->udp_port) {
2430 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2431 udp_tunnel->udp_port, bp->geneve_port);
2434 if (--bp->geneve_port_cnt)
2438 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2439 port = bp->geneve_fw_dst_port_id;
2442 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2446 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2450 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2452 struct bnxt_filter_info *filter;
2453 struct bnxt_vnic_info *vnic;
2455 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2457 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2458 filter = STAILQ_FIRST(&vnic->filter);
2460 /* Search for this matching MAC+VLAN filter */
2461 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2462 /* Delete the filter */
2463 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2466 STAILQ_REMOVE(&vnic->filter, filter,
2467 bnxt_filter_info, next);
2468 bnxt_free_filter(bp, filter);
2470 "Deleted vlan filter for %d\n",
2474 filter = STAILQ_NEXT(filter, next);
2479 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2481 struct bnxt_filter_info *filter;
2482 struct bnxt_vnic_info *vnic;
2484 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2485 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2486 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2488 /* Implementation notes on the use of VNIC in this command:
2490 * By default, these filters belong to default vnic for the function.
2491 * Once these filters are set up, only destination VNIC can be modified.
2492 * If the destination VNIC is not specified in this command,
2493 * then the HWRM shall only create an l2 context id.
2496 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2497 filter = STAILQ_FIRST(&vnic->filter);
2498 /* Check if the VLAN has already been added */
2500 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2503 filter = STAILQ_NEXT(filter, next);
2506 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2507 * command to create MAC+VLAN filter with the right flags, enables set.
2509 filter = bnxt_alloc_filter(bp);
2512 "MAC/VLAN filter alloc failed\n");
2515 /* MAC + VLAN ID filter */
2516 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2517 * untagged packets are received
2519 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2520 * packets and only the programmed vlan's packets are received
2522 filter->l2_ivlan = vlan_id;
2523 filter->l2_ivlan_mask = 0x0FFF;
2524 filter->enables |= en;
2525 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2527 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2529 /* Free the newly allocated filter as we were
2530 * not able to create the filter in hardware.
2532 bnxt_free_filter(bp, filter);
2536 filter->mac_index = 0;
2537 /* Add this new filter to the list */
2539 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2541 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2544 "Added Vlan filter for %d\n", vlan_id);
2548 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2549 uint16_t vlan_id, int on)
2551 struct bnxt *bp = eth_dev->data->dev_private;
2554 rc = is_bnxt_in_error(bp);
2558 if (!eth_dev->data->dev_started) {
2559 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2563 /* These operations apply to ALL existing MAC/VLAN filters */
2565 return bnxt_add_vlan_filter(bp, vlan_id);
2567 return bnxt_del_vlan_filter(bp, vlan_id);
2570 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2571 struct bnxt_vnic_info *vnic)
2573 struct bnxt_filter_info *filter;
2576 filter = STAILQ_FIRST(&vnic->filter);
2578 if (filter->mac_index == 0 &&
2579 !memcmp(filter->l2_addr, bp->mac_addr,
2580 RTE_ETHER_ADDR_LEN)) {
2581 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2583 STAILQ_REMOVE(&vnic->filter, filter,
2584 bnxt_filter_info, next);
2585 bnxt_free_filter(bp, filter);
2589 filter = STAILQ_NEXT(filter, next);
2595 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2597 struct bnxt_vnic_info *vnic;
2601 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2602 if (!(rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)) {
2603 /* Remove any VLAN filters programmed */
2604 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2605 bnxt_del_vlan_filter(bp, i);
2607 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2611 /* Default filter will allow packets that match the
2612 * dest mac. So, it has to be deleted, otherwise, we
2613 * will endup receiving vlan packets for which the
2614 * filter is not programmed, when hw-vlan-filter
2615 * configuration is ON
2617 bnxt_del_dflt_mac_filter(bp, vnic);
2618 /* This filter will allow only untagged packets */
2619 bnxt_add_vlan_filter(bp, 0);
2621 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2622 !!(rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER));
2627 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2629 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2633 /* Destroy vnic filters and vnic */
2634 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2635 RTE_ETH_RX_OFFLOAD_VLAN_FILTER) {
2636 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2637 bnxt_del_vlan_filter(bp, i);
2639 bnxt_del_dflt_mac_filter(bp, vnic);
2641 rc = bnxt_hwrm_vnic_ctx_free(bp, vnic);
2645 rc = bnxt_hwrm_vnic_free(bp, vnic);
2649 rte_free(vnic->fw_grp_ids);
2650 vnic->fw_grp_ids = NULL;
2652 vnic->rx_queue_cnt = 0;
2658 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2660 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2663 /* Destroy, recreate and reconfigure the default vnic */
2664 rc = bnxt_free_one_vnic(bp, 0);
2668 /* default vnic 0 */
2669 rc = bnxt_setup_one_vnic(bp, 0);
2673 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2674 RTE_ETH_RX_OFFLOAD_VLAN_FILTER) {
2675 rc = bnxt_add_vlan_filter(bp, 0);
2678 rc = bnxt_restore_vlan_filters(bp);
2682 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2687 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2691 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2692 !!(rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP));
2698 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2700 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2701 struct bnxt *bp = dev->data->dev_private;
2704 rc = is_bnxt_in_error(bp);
2708 /* Filter settings will get applied when port is started */
2709 if (!dev->data->dev_started)
2712 if (mask & RTE_ETH_VLAN_FILTER_MASK) {
2713 /* Enable or disable VLAN filtering */
2714 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2719 if (mask & RTE_ETH_VLAN_STRIP_MASK) {
2720 /* Enable or disable VLAN stripping */
2721 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2726 if (mask & RTE_ETH_VLAN_EXTEND_MASK) {
2727 if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND)
2728 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2730 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2737 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2740 struct bnxt *bp = dev->data->dev_private;
2741 int qinq = dev->data->dev_conf.rxmode.offloads &
2742 RTE_ETH_RX_OFFLOAD_VLAN_EXTEND;
2744 if (vlan_type != RTE_ETH_VLAN_TYPE_INNER &&
2745 vlan_type != RTE_ETH_VLAN_TYPE_OUTER) {
2747 "Unsupported vlan type.");
2752 "QinQ not enabled. Needs to be ON as we can "
2753 "accelerate only outer vlan\n");
2757 if (vlan_type == RTE_ETH_VLAN_TYPE_OUTER) {
2759 case RTE_ETHER_TYPE_QINQ:
2761 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2763 case RTE_ETHER_TYPE_VLAN:
2765 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2767 case RTE_ETHER_TYPE_QINQ1:
2769 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2771 case RTE_ETHER_TYPE_QINQ2:
2773 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2775 case RTE_ETHER_TYPE_QINQ3:
2777 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2780 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2783 bp->outer_tpid_bd |= tpid;
2784 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2785 } else if (vlan_type == RTE_ETH_VLAN_TYPE_INNER) {
2787 "Can accelerate only outer vlan in QinQ\n");
2795 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2796 struct rte_ether_addr *addr)
2798 struct bnxt *bp = dev->data->dev_private;
2799 /* Default Filter is tied to VNIC 0 */
2800 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2803 rc = is_bnxt_in_error(bp);
2807 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2810 if (rte_is_zero_ether_addr(addr))
2813 /* Filter settings will get applied when port is started */
2814 if (!dev->data->dev_started)
2817 /* Check if the requested MAC is already added */
2818 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2821 /* Destroy filter and re-create it */
2822 bnxt_del_dflt_mac_filter(bp, vnic);
2824 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2825 if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) {
2826 /* This filter will allow only untagged packets */
2827 rc = bnxt_add_vlan_filter(bp, 0);
2829 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2832 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2837 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2838 struct rte_ether_addr *mc_addr_set,
2839 uint32_t nb_mc_addr)
2841 struct bnxt *bp = eth_dev->data->dev_private;
2842 struct bnxt_vnic_info *vnic;
2846 rc = is_bnxt_in_error(bp);
2850 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2852 bp->nb_mc_addr = nb_mc_addr;
2854 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2855 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2859 /* TODO Check for Duplicate mcast addresses */
2860 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2861 for (i = 0; i < nb_mc_addr; i++)
2862 rte_ether_addr_copy(&mc_addr_set[i], &bp->mcast_addr_list[i]);
2865 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2867 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2870 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2874 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2876 struct bnxt *bp = dev->data->dev_private;
2877 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2878 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2879 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2880 uint8_t fw_rsvd = bp->fw_ver & 0xff;
2883 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2884 fw_major, fw_minor, fw_updt, fw_rsvd);
2888 ret += 1; /* add the size of '\0' */
2889 if (fw_size < (size_t)ret)
2896 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2897 struct rte_eth_rxq_info *qinfo)
2899 struct bnxt *bp = dev->data->dev_private;
2900 struct bnxt_rx_queue *rxq;
2902 if (is_bnxt_in_error(bp))
2905 rxq = dev->data->rx_queues[queue_id];
2907 qinfo->mp = rxq->mb_pool;
2908 qinfo->scattered_rx = dev->data->scattered_rx;
2909 qinfo->nb_desc = rxq->nb_rx_desc;
2911 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2912 qinfo->conf.rx_drop_en = rxq->drop_en;
2913 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2914 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2918 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2919 struct rte_eth_txq_info *qinfo)
2921 struct bnxt *bp = dev->data->dev_private;
2922 struct bnxt_tx_queue *txq;
2924 if (is_bnxt_in_error(bp))
2927 txq = dev->data->tx_queues[queue_id];
2929 qinfo->nb_desc = txq->nb_tx_desc;
2931 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2932 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2933 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2935 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2936 qinfo->conf.tx_rs_thresh = 0;
2937 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2938 qinfo->conf.offloads = txq->offloads;
2941 static const struct {
2942 eth_rx_burst_t pkt_burst;
2944 } bnxt_rx_burst_info[] = {
2945 {bnxt_recv_pkts, "Scalar"},
2946 #if defined(RTE_ARCH_X86)
2947 {bnxt_recv_pkts_vec, "Vector SSE"},
2949 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2950 {bnxt_recv_pkts_vec_avx2, "Vector AVX2"},
2952 #if defined(RTE_ARCH_ARM64)
2953 {bnxt_recv_pkts_vec, "Vector Neon"},
2958 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2959 struct rte_eth_burst_mode *mode)
2961 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2964 for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2965 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2966 snprintf(mode->info, sizeof(mode->info), "%s",
2967 bnxt_rx_burst_info[i].info);
2975 static const struct {
2976 eth_tx_burst_t pkt_burst;
2978 } bnxt_tx_burst_info[] = {
2979 {bnxt_xmit_pkts, "Scalar"},
2980 #if defined(RTE_ARCH_X86)
2981 {bnxt_xmit_pkts_vec, "Vector SSE"},
2983 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2984 {bnxt_xmit_pkts_vec_avx2, "Vector AVX2"},
2986 #if defined(RTE_ARCH_ARM64)
2987 {bnxt_xmit_pkts_vec, "Vector Neon"},
2992 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2993 struct rte_eth_burst_mode *mode)
2995 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2998 for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2999 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
3000 snprintf(mode->info, sizeof(mode->info), "%s",
3001 bnxt_tx_burst_info[i].info);
3009 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
3011 uint32_t overhead = BNXT_MAX_PKT_LEN - BNXT_MAX_MTU;
3012 struct bnxt *bp = eth_dev->data->dev_private;
3013 uint32_t new_pkt_size;
3017 rc = is_bnxt_in_error(bp);
3021 /* Exit if receive queues are not configured yet */
3022 if (!eth_dev->data->nb_rx_queues)
3025 new_pkt_size = new_mtu + overhead;
3028 * Disallow any MTU change that would require scattered receive support
3029 * if it is not already enabled.
3031 if (eth_dev->data->dev_started &&
3032 !eth_dev->data->scattered_rx &&
3034 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
3036 "MTU change would require scattered rx support. ");
3037 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
3041 if (new_mtu > RTE_ETHER_MTU)
3042 bp->flags |= BNXT_FLAG_JUMBO;
3044 bp->flags &= ~BNXT_FLAG_JUMBO;
3046 /* Is there a change in mtu setting? */
3047 if (eth_dev->data->mtu == new_mtu)
3050 for (i = 0; i < bp->nr_vnics; i++) {
3051 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3054 vnic->mru = BNXT_VNIC_MRU(new_mtu);
3055 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
3059 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
3060 size -= RTE_PKTMBUF_HEADROOM;
3062 if (size < new_mtu) {
3063 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
3069 if (bnxt_hwrm_config_host_mtu(bp))
3070 PMD_DRV_LOG(WARNING, "Failed to configure host MTU\n");
3072 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
3078 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
3080 struct bnxt *bp = dev->data->dev_private;
3081 uint16_t vlan = bp->vlan;
3084 rc = is_bnxt_in_error(bp);
3088 if (!BNXT_SINGLE_PF(bp)) {
3089 PMD_DRV_LOG(ERR, "PVID cannot be modified on VF or on shared PF\n");
3092 bp->vlan = on ? pvid : 0;
3094 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
3101 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
3103 struct bnxt *bp = dev->data->dev_private;
3106 rc = is_bnxt_in_error(bp);
3110 return bnxt_hwrm_port_led_cfg(bp, true);
3114 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
3116 struct bnxt *bp = dev->data->dev_private;
3119 rc = is_bnxt_in_error(bp);
3123 return bnxt_hwrm_port_led_cfg(bp, false);
3127 bnxt_rx_queue_count_op(void *rx_queue)
3130 struct bnxt_cp_ring_info *cpr;
3131 uint32_t desc = 0, raw_cons, cp_ring_size;
3132 struct bnxt_rx_queue *rxq;
3133 struct rx_pkt_cmpl *rxcmp;
3139 rc = is_bnxt_in_error(bp);
3144 raw_cons = cpr->cp_raw_cons;
3145 cp_ring_size = cpr->cp_ring_struct->ring_size;
3148 uint32_t agg_cnt, cons, cmpl_type;
3150 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3151 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3153 if (!bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size))
3156 cmpl_type = CMP_TYPE(rxcmp);
3158 switch (cmpl_type) {
3159 case CMPL_BASE_TYPE_RX_L2:
3160 case CMPL_BASE_TYPE_RX_L2_V2:
3161 agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3162 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3166 case CMPL_BASE_TYPE_RX_TPA_END:
3167 if (BNXT_CHIP_P5(rxq->bp)) {
3168 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3170 p5_tpa_end = (void *)rxcmp;
3171 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3173 struct rx_tpa_end_cmpl *tpa_end;
3175 tpa_end = (void *)rxcmp;
3176 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3179 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3184 raw_cons += CMP_LEN(cmpl_type);
3192 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
3194 struct bnxt_rx_queue *rxq = rx_queue;
3195 struct bnxt_cp_ring_info *cpr;
3196 struct bnxt_rx_ring_info *rxr;
3197 uint32_t desc, raw_cons, cp_ring_size;
3198 struct bnxt *bp = rxq->bp;
3199 struct rx_pkt_cmpl *rxcmp;
3202 rc = is_bnxt_in_error(bp);
3206 if (offset >= rxq->nb_rx_desc)
3211 cp_ring_size = cpr->cp_ring_struct->ring_size;
3214 * For the vector receive case, the completion at the requested
3215 * offset can be indexed directly.
3217 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
3218 if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) {
3219 struct rx_pkt_cmpl *rxcmp;
3222 /* Check status of completion descriptor. */
3223 raw_cons = cpr->cp_raw_cons +
3224 offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2);
3225 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3226 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3228 if (bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size))
3229 return RTE_ETH_RX_DESC_DONE;
3231 /* Check whether rx desc has an mbuf attached. */
3232 cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2);
3233 if (cons >= rxq->rxrearm_start &&
3234 cons < rxq->rxrearm_start + rxq->rxrearm_nb) {
3235 return RTE_ETH_RX_DESC_UNAVAIL;
3238 return RTE_ETH_RX_DESC_AVAIL;
3243 * For the non-vector receive case, scan the completion ring to
3244 * locate the completion descriptor for the requested offset.
3246 raw_cons = cpr->cp_raw_cons;
3249 uint32_t agg_cnt, cons, cmpl_type;
3251 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3252 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3254 if (!bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size))
3257 cmpl_type = CMP_TYPE(rxcmp);
3259 switch (cmpl_type) {
3260 case CMPL_BASE_TYPE_RX_L2:
3261 case CMPL_BASE_TYPE_RX_L2_V2:
3262 if (desc == offset) {
3263 cons = rxcmp->opaque;
3264 if (rxr->rx_buf_ring[cons])
3265 return RTE_ETH_RX_DESC_DONE;
3267 return RTE_ETH_RX_DESC_UNAVAIL;
3269 agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3270 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3274 case CMPL_BASE_TYPE_RX_TPA_END:
3276 return RTE_ETH_RX_DESC_DONE;
3278 if (BNXT_CHIP_P5(rxq->bp)) {
3279 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3281 p5_tpa_end = (void *)rxcmp;
3282 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3284 struct rx_tpa_end_cmpl *tpa_end;
3286 tpa_end = (void *)rxcmp;
3287 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3290 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3295 raw_cons += CMP_LEN(cmpl_type);
3299 return RTE_ETH_RX_DESC_AVAIL;
3303 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
3305 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
3306 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
3307 uint32_t ring_mask, raw_cons, nb_tx_pkts = 0;
3308 struct cmpl_base *cp_desc_ring;
3311 rc = is_bnxt_in_error(txq->bp);
3315 if (offset >= txq->nb_tx_desc)
3318 /* Return "desc done" if descriptor is available for use. */
3319 if (bnxt_tx_bds_in_hw(txq) <= offset)
3320 return RTE_ETH_TX_DESC_DONE;
3322 raw_cons = cpr->cp_raw_cons;
3323 cp_desc_ring = cpr->cp_desc_ring;
3324 ring_mask = cpr->cp_ring_struct->ring_mask;
3326 /* Check to see if hw has posted a completion for the descriptor. */
3328 struct tx_cmpl *txcmp;
3331 cons = RING_CMPL(ring_mask, raw_cons);
3332 txcmp = (struct tx_cmpl *)&cp_desc_ring[cons];
3334 if (!bnxt_cpr_cmp_valid(txcmp, raw_cons, ring_mask + 1))
3337 if (CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2)
3338 nb_tx_pkts += rte_le_to_cpu_32(txcmp->opaque);
3340 if (nb_tx_pkts > offset)
3341 return RTE_ETH_TX_DESC_DONE;
3343 raw_cons = NEXT_RAW_CMP(raw_cons);
3346 /* Descriptor is pending transmit, not yet completed by hardware. */
3347 return RTE_ETH_TX_DESC_FULL;
3351 bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
3352 const struct rte_flow_ops **ops)
3354 struct bnxt *bp = dev->data->dev_private;
3360 if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3361 struct bnxt_representor *vfr = dev->data->dev_private;
3362 bp = vfr->parent_dev->data->dev_private;
3363 /* parent is deleted while children are still valid */
3365 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error\n",
3366 dev->data->port_id);
3371 ret = is_bnxt_in_error(bp);
3375 /* PMD supports thread-safe flow operations. rte_flow API
3376 * functions can avoid mutex for multi-thread safety.
3378 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3380 if (BNXT_TRUFLOW_EN(bp))
3381 *ops = &bnxt_ulp_rte_flow_ops;
3383 *ops = &bnxt_flow_ops;
3388 static const uint32_t *
3389 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3391 static const uint32_t ptypes[] = {
3392 RTE_PTYPE_L2_ETHER_VLAN,
3393 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3394 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3398 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3399 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3400 RTE_PTYPE_INNER_L4_ICMP,
3401 RTE_PTYPE_INNER_L4_TCP,
3402 RTE_PTYPE_INNER_L4_UDP,
3406 if (!dev->rx_pkt_burst)
3412 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3415 uint32_t reg_base = *reg_arr & 0xfffff000;
3419 for (i = 0; i < count; i++) {
3420 if ((reg_arr[i] & 0xfffff000) != reg_base)
3423 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3424 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3428 static int bnxt_map_ptp_regs(struct bnxt *bp)
3430 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3434 reg_arr = ptp->rx_regs;
3435 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3439 reg_arr = ptp->tx_regs;
3440 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3444 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3445 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3447 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3448 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3453 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3455 rte_write32(0, (uint8_t *)bp->bar0 +
3456 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3457 rte_write32(0, (uint8_t *)bp->bar0 +
3458 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3461 static uint64_t bnxt_cc_read(struct bnxt *bp)
3465 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3466 BNXT_GRCPF_REG_SYNC_TIME));
3467 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3468 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3472 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3474 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3477 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3478 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3479 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3482 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3483 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3484 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3485 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3486 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3487 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3488 rte_read32((uint8_t *)bp->bar0 + ptp->tx_mapped_regs[BNXT_PTP_TX_SEQ]);
3493 static int bnxt_clr_rx_ts(struct bnxt *bp, uint64_t *last_ts)
3495 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3496 struct bnxt_pf_info *pf = bp->pf;
3501 if (!ptp || (bp->flags & BNXT_FLAG_CHIP_P5))
3504 port_id = pf->port_id;
3505 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3506 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3507 while ((fifo & BNXT_PTP_RX_FIFO_PENDING) && (i < BNXT_PTP_RX_PND_CNT)) {
3508 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3509 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3510 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3511 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3512 *last_ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3513 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3514 *last_ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3515 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3519 if (i >= BNXT_PTP_RX_PND_CNT)
3525 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3527 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3528 struct bnxt_pf_info *pf = bp->pf;
3532 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3533 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3534 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3537 port_id = pf->port_id;
3538 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3539 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3541 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3542 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3543 if (fifo & BNXT_PTP_RX_FIFO_PENDING)
3544 return bnxt_clr_rx_ts(bp, ts);
3546 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3547 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3548 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3549 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3555 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3558 struct bnxt *bp = dev->data->dev_private;
3559 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3564 ns = rte_timespec_to_ns(ts);
3565 /* Set the timecounters to a new value. */
3567 ptp->tx_tstamp_tc.nsec = ns;
3568 ptp->rx_tstamp_tc.nsec = ns;
3574 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3576 struct bnxt *bp = dev->data->dev_private;
3577 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3578 uint64_t ns, systime_cycles = 0;
3584 if (BNXT_CHIP_P5(bp))
3585 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3588 systime_cycles = bnxt_cc_read(bp);
3590 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3591 *ts = rte_ns_to_timespec(ns);
3596 bnxt_timesync_enable(struct rte_eth_dev *dev)
3598 struct bnxt *bp = dev->data->dev_private;
3599 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3607 ptp->tx_tstamp_en = 1;
3608 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3610 rc = bnxt_hwrm_ptp_cfg(bp);
3614 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3615 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3616 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3618 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3619 ptp->tc.cc_shift = shift;
3620 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3622 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3623 ptp->rx_tstamp_tc.cc_shift = shift;
3624 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3626 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3627 ptp->tx_tstamp_tc.cc_shift = shift;
3628 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3630 if (!BNXT_CHIP_P5(bp))
3631 bnxt_map_ptp_regs(bp);
3633 rc = bnxt_ptp_start(bp);
3639 bnxt_timesync_disable(struct rte_eth_dev *dev)
3641 struct bnxt *bp = dev->data->dev_private;
3642 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3648 ptp->tx_tstamp_en = 0;
3651 bnxt_hwrm_ptp_cfg(bp);
3653 if (!BNXT_CHIP_P5(bp))
3654 bnxt_unmap_ptp_regs(bp);
3662 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3663 struct timespec *timestamp,
3664 uint32_t flags __rte_unused)
3666 struct bnxt *bp = dev->data->dev_private;
3667 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3668 uint64_t rx_tstamp_cycles = 0;
3674 if (BNXT_CHIP_P5(bp))
3675 rx_tstamp_cycles = ptp->rx_timestamp;
3677 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3679 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3680 *timestamp = rte_ns_to_timespec(ns);
3685 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3686 struct timespec *timestamp)
3688 struct bnxt *bp = dev->data->dev_private;
3689 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3690 uint64_t tx_tstamp_cycles = 0;
3697 if (BNXT_CHIP_P5(bp))
3698 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3701 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3703 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3704 *timestamp = rte_ns_to_timespec(ns);
3710 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3712 struct bnxt *bp = dev->data->dev_private;
3713 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3718 ptp->tc.nsec += delta;
3719 ptp->tx_tstamp_tc.nsec += delta;
3720 ptp->rx_tstamp_tc.nsec += delta;
3726 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3728 struct bnxt *bp = dev->data->dev_private;
3730 uint32_t dir_entries;
3731 uint32_t entry_length;
3733 rc = is_bnxt_in_error(bp);
3737 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3738 bp->pdev->addr.domain, bp->pdev->addr.bus,
3739 bp->pdev->addr.devid, bp->pdev->addr.function);
3741 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3745 return dir_entries * entry_length;
3749 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3750 struct rte_dev_eeprom_info *in_eeprom)
3752 struct bnxt *bp = dev->data->dev_private;
3757 rc = is_bnxt_in_error(bp);
3761 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3762 bp->pdev->addr.domain, bp->pdev->addr.bus,
3763 bp->pdev->addr.devid, bp->pdev->addr.function,
3764 in_eeprom->offset, in_eeprom->length);
3766 if (in_eeprom->offset == 0) /* special offset value to get directory */
3767 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3770 index = in_eeprom->offset >> 24;
3771 offset = in_eeprom->offset & 0xffffff;
3774 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3775 in_eeprom->length, in_eeprom->data);
3780 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3783 case BNX_DIR_TYPE_CHIMP_PATCH:
3784 case BNX_DIR_TYPE_BOOTCODE:
3785 case BNX_DIR_TYPE_BOOTCODE_2:
3786 case BNX_DIR_TYPE_APE_FW:
3787 case BNX_DIR_TYPE_APE_PATCH:
3788 case BNX_DIR_TYPE_KONG_FW:
3789 case BNX_DIR_TYPE_KONG_PATCH:
3790 case BNX_DIR_TYPE_BONO_FW:
3791 case BNX_DIR_TYPE_BONO_PATCH:
3799 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3802 case BNX_DIR_TYPE_AVS:
3803 case BNX_DIR_TYPE_EXP_ROM_MBA:
3804 case BNX_DIR_TYPE_PCIE:
3805 case BNX_DIR_TYPE_TSCF_UCODE:
3806 case BNX_DIR_TYPE_EXT_PHY:
3807 case BNX_DIR_TYPE_CCM:
3808 case BNX_DIR_TYPE_ISCSI_BOOT:
3809 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3810 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3818 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3820 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3821 bnxt_dir_type_is_other_exec_format(dir_type);
3825 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3826 struct rte_dev_eeprom_info *in_eeprom)
3828 struct bnxt *bp = dev->data->dev_private;
3829 uint8_t index, dir_op;
3830 uint16_t type, ext, ordinal, attr;
3833 rc = is_bnxt_in_error(bp);
3837 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3838 bp->pdev->addr.domain, bp->pdev->addr.bus,
3839 bp->pdev->addr.devid, bp->pdev->addr.function,
3840 in_eeprom->offset, in_eeprom->length);
3843 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3847 type = in_eeprom->magic >> 16;
3849 if (type == 0xffff) { /* special value for directory operations */
3850 index = in_eeprom->magic & 0xff;
3851 dir_op = in_eeprom->magic >> 8;
3855 case 0x0e: /* erase */
3856 if (in_eeprom->offset != ~in_eeprom->magic)
3858 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3864 /* Create or re-write an NVM item: */
3865 if (bnxt_dir_type_is_executable(type) == true)
3867 ext = in_eeprom->magic & 0xffff;
3868 ordinal = in_eeprom->offset >> 16;
3869 attr = in_eeprom->offset & 0xffff;
3871 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3872 in_eeprom->data, in_eeprom->length);
3875 static int bnxt_get_module_info(struct rte_eth_dev *dev,
3876 struct rte_eth_dev_module_info *modinfo)
3878 uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1];
3879 struct bnxt *bp = dev->data->dev_private;
3882 /* No point in going further if phy status indicates
3883 * module is not inserted or if it is powered down or
3884 * if it is of type 10GBase-T
3886 if (bp->link_info->module_status >
3887 HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG) {
3888 PMD_DRV_LOG(NOTICE, "Port %u : Module is not inserted or is powered down\n",
3889 dev->data->port_id);
3893 /* This feature is not supported in older firmware versions */
3894 if (bp->hwrm_spec_code < 0x10202) {
3895 PMD_DRV_LOG(NOTICE, "Port %u : Feature is not supported in older firmware\n",
3896 dev->data->port_id);
3900 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
3901 SFF_DIAG_SUPPORT_OFFSET + 1,
3907 switch (module_info[0]) {
3908 case SFF_MODULE_ID_SFP:
3909 modinfo->type = RTE_ETH_MODULE_SFF_8472;
3910 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
3911 if (module_info[SFF_DIAG_SUPPORT_OFFSET] == 0)
3912 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN;
3914 case SFF_MODULE_ID_QSFP:
3915 case SFF_MODULE_ID_QSFP_PLUS:
3916 modinfo->type = RTE_ETH_MODULE_SFF_8436;
3917 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN;
3919 case SFF_MODULE_ID_QSFP28:
3920 modinfo->type = RTE_ETH_MODULE_SFF_8636;
3921 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
3922 if (module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK)
3923 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_LEN;
3926 PMD_DRV_LOG(NOTICE, "Port %u : Unsupported module\n", dev->data->port_id);
3930 PMD_DRV_LOG(INFO, "Port %u : modinfo->type = %d modinfo->eeprom_len = %d\n",
3931 dev->data->port_id, modinfo->type, modinfo->eeprom_len);
3936 static int bnxt_get_module_eeprom(struct rte_eth_dev *dev,
3937 struct rte_dev_eeprom_info *info)
3939 uint8_t pg_addr[5] = { I2C_DEV_ADDR_A0, I2C_DEV_ADDR_A0 };
3940 uint32_t offset = info->offset, length = info->length;
3941 uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1];
3942 struct bnxt *bp = dev->data->dev_private;
3943 uint8_t *data = info->data;
3944 uint8_t page = offset >> 7;
3945 uint8_t max_pages = 2;
3949 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
3950 SFF_DIAG_SUPPORT_OFFSET + 1,
3955 switch (module_info[0]) {
3956 case SFF_MODULE_ID_SFP:
3957 module_info[SFF_DIAG_SUPPORT_OFFSET] = 0;
3958 if (module_info[SFF_DIAG_SUPPORT_OFFSET]) {
3959 pg_addr[2] = I2C_DEV_ADDR_A2;
3960 pg_addr[3] = I2C_DEV_ADDR_A2;
3964 case SFF_MODULE_ID_QSFP28:
3965 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0,
3966 SFF8636_OPT_PAGES_OFFSET,
3971 if (opt_pages & SFF8636_PAGE1_MASK) {
3972 pg_addr[2] = I2C_DEV_ADDR_A0;
3975 if (opt_pages & SFF8636_PAGE2_MASK) {
3976 pg_addr[3] = I2C_DEV_ADDR_A0;
3979 if (~module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK) {
3980 pg_addr[4] = I2C_DEV_ADDR_A0;
3988 memset(data, 0, length);
3991 while (length && page < max_pages) {
3992 uint8_t raw_page = page ? page - 1 : 0;
3995 if (pg_addr[page] == I2C_DEV_ADDR_A2)
3999 chunk = RTE_MIN(length, 256 - offset);
4001 if (pg_addr[page]) {
4002 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, pg_addr[page],
4012 page += 1 + (chunk > 128);
4015 return length ? -EINVAL : 0;
4022 static const struct eth_dev_ops bnxt_dev_ops = {
4023 .dev_infos_get = bnxt_dev_info_get_op,
4024 .dev_close = bnxt_dev_close_op,
4025 .dev_configure = bnxt_dev_configure_op,
4026 .dev_start = bnxt_dev_start_op,
4027 .dev_stop = bnxt_dev_stop_op,
4028 .dev_set_link_up = bnxt_dev_set_link_up_op,
4029 .dev_set_link_down = bnxt_dev_set_link_down_op,
4030 .stats_get = bnxt_stats_get_op,
4031 .stats_reset = bnxt_stats_reset_op,
4032 .rx_queue_setup = bnxt_rx_queue_setup_op,
4033 .rx_queue_release = bnxt_rx_queue_release_op,
4034 .tx_queue_setup = bnxt_tx_queue_setup_op,
4035 .tx_queue_release = bnxt_tx_queue_release_op,
4036 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4037 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4038 .reta_update = bnxt_reta_update_op,
4039 .reta_query = bnxt_reta_query_op,
4040 .rss_hash_update = bnxt_rss_hash_update_op,
4041 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4042 .link_update = bnxt_link_update_op,
4043 .promiscuous_enable = bnxt_promiscuous_enable_op,
4044 .promiscuous_disable = bnxt_promiscuous_disable_op,
4045 .allmulticast_enable = bnxt_allmulticast_enable_op,
4046 .allmulticast_disable = bnxt_allmulticast_disable_op,
4047 .mac_addr_add = bnxt_mac_addr_add_op,
4048 .mac_addr_remove = bnxt_mac_addr_remove_op,
4049 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4050 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4051 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
4052 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
4053 .vlan_filter_set = bnxt_vlan_filter_set_op,
4054 .vlan_offload_set = bnxt_vlan_offload_set_op,
4055 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4056 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4057 .mtu_set = bnxt_mtu_set_op,
4058 .mac_addr_set = bnxt_set_default_mac_addr_op,
4059 .xstats_get = bnxt_dev_xstats_get_op,
4060 .xstats_get_names = bnxt_dev_xstats_get_names_op,
4061 .xstats_reset = bnxt_dev_xstats_reset_op,
4062 .fw_version_get = bnxt_fw_version_get,
4063 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4064 .rxq_info_get = bnxt_rxq_info_get_op,
4065 .txq_info_get = bnxt_txq_info_get_op,
4066 .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4067 .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4068 .dev_led_on = bnxt_dev_led_on_op,
4069 .dev_led_off = bnxt_dev_led_off_op,
4070 .rx_queue_start = bnxt_rx_queue_start,
4071 .rx_queue_stop = bnxt_rx_queue_stop,
4072 .tx_queue_start = bnxt_tx_queue_start,
4073 .tx_queue_stop = bnxt_tx_queue_stop,
4074 .flow_ops_get = bnxt_flow_ops_get_op,
4075 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4076 .get_eeprom_length = bnxt_get_eeprom_length_op,
4077 .get_eeprom = bnxt_get_eeprom_op,
4078 .set_eeprom = bnxt_set_eeprom_op,
4079 .get_module_info = bnxt_get_module_info,
4080 .get_module_eeprom = bnxt_get_module_eeprom,
4081 .timesync_enable = bnxt_timesync_enable,
4082 .timesync_disable = bnxt_timesync_disable,
4083 .timesync_read_time = bnxt_timesync_read_time,
4084 .timesync_write_time = bnxt_timesync_write_time,
4085 .timesync_adjust_time = bnxt_timesync_adjust_time,
4086 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4087 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4090 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4094 /* Only pre-map the reset GRC registers using window 3 */
4095 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4096 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4098 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4103 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4105 struct bnxt_error_recovery_info *info = bp->recovery_info;
4106 uint32_t reg_base = 0xffffffff;
4109 /* Only pre-map the monitoring GRC registers using window 2 */
4110 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4111 uint32_t reg = info->status_regs[i];
4113 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4116 if (reg_base == 0xffffffff)
4117 reg_base = reg & 0xfffff000;
4118 if ((reg & 0xfffff000) != reg_base)
4121 /* Use mask 0xffc as the Lower 2 bits indicates
4122 * address space location
4124 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4128 if (reg_base == 0xffffffff)
4131 rte_write32(reg_base, (uint8_t *)bp->bar0 +
4132 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4137 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4139 struct bnxt_error_recovery_info *info = bp->recovery_info;
4140 uint32_t delay = info->delay_after_reset[index];
4141 uint32_t val = info->reset_reg_val[index];
4142 uint32_t reg = info->reset_reg[index];
4143 uint32_t type, offset;
4146 type = BNXT_FW_STATUS_REG_TYPE(reg);
4147 offset = BNXT_FW_STATUS_REG_OFF(reg);
4150 case BNXT_FW_STATUS_REG_TYPE_CFG:
4151 ret = rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4153 PMD_DRV_LOG(ERR, "Failed to write %#x at PCI offset %#x",
4158 case BNXT_FW_STATUS_REG_TYPE_GRC:
4159 offset = bnxt_map_reset_regs(bp, offset);
4160 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4162 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4163 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4166 /* wait on a specific interval of time until core reset is complete */
4168 rte_delay_ms(delay);
4171 static void bnxt_dev_cleanup(struct bnxt *bp)
4173 bp->eth_dev->data->dev_link.link_status = 0;
4174 bp->link_info->link_up = 0;
4175 if (bp->eth_dev->data->dev_started)
4176 bnxt_dev_stop(bp->eth_dev);
4178 bnxt_uninit_resources(bp, true);
4182 bnxt_check_fw_reset_done(struct bnxt *bp)
4184 int timeout = bp->fw_reset_max_msecs;
4189 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4191 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4197 } while (timeout--);
4199 if (val == 0xffff) {
4200 PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n");
4207 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4209 struct rte_eth_dev *dev = bp->eth_dev;
4210 struct rte_vlan_filter_conf *vfc;
4214 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4215 vfc = &dev->data->vlan_filter_conf;
4216 vidx = vlan_id / 64;
4217 vbit = vlan_id % 64;
4219 /* Each bit corresponds to a VLAN id */
4220 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4221 rc = bnxt_add_vlan_filter(bp, vlan_id);
4230 static int bnxt_restore_mac_filters(struct bnxt *bp)
4232 struct rte_eth_dev *dev = bp->eth_dev;
4233 struct rte_eth_dev_info dev_info;
4234 struct rte_ether_addr *addr;
4240 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4243 rc = bnxt_dev_info_get_op(dev, &dev_info);
4247 /* replay MAC address configuration */
4248 for (i = 1; i < dev_info.max_mac_addrs; i++) {
4249 addr = &dev->data->mac_addrs[i];
4251 /* skip zero address */
4252 if (rte_is_zero_ether_addr(addr))
4256 pool_mask = dev->data->mac_pool_sel[i];
4259 if (pool_mask & 1ULL) {
4260 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4266 } while (pool_mask);
4272 static int bnxt_restore_mcast_mac_filters(struct bnxt *bp)
4276 ret = bnxt_dev_set_mc_addr_list_op(bp->eth_dev, bp->mcast_addr_list,
4279 PMD_DRV_LOG(ERR, "Failed to restore multicast MAC addreeses\n");
4284 static int bnxt_restore_filters(struct bnxt *bp)
4286 struct rte_eth_dev *dev = bp->eth_dev;
4289 if (dev->data->all_multicast) {
4290 ret = bnxt_allmulticast_enable_op(dev);
4294 if (dev->data->promiscuous) {
4295 ret = bnxt_promiscuous_enable_op(dev);
4300 ret = bnxt_restore_mac_filters(bp);
4304 /* if vlans are already programmed, this can fail with -EEXIST */
4305 ret = bnxt_restore_vlan_filters(bp);
4306 if (ret && ret != -EEXIST)
4309 ret = bnxt_restore_mcast_mac_filters(bp);
4316 static int bnxt_check_fw_ready(struct bnxt *bp)
4318 int timeout = bp->fw_reset_max_msecs;
4322 rc = bnxt_hwrm_poll_ver_get(bp);
4325 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4326 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4327 } while (rc && timeout > 0);
4330 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4335 static void bnxt_dev_recover(void *arg)
4337 struct bnxt *bp = arg;
4340 pthread_mutex_lock(&bp->err_recovery_lock);
4342 if (!bp->fw_reset_min_msecs) {
4343 rc = bnxt_check_fw_reset_done(bp);
4348 /* Clear Error flag so that device re-init should happen */
4349 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4350 PMD_DRV_LOG(INFO, "Port: %u Starting recovery...\n",
4351 bp->eth_dev->data->port_id);
4353 rc = bnxt_check_fw_ready(bp);
4357 rc = bnxt_init_resources(bp, true);
4360 "Failed to initialize resources after reset\n");
4363 /* clear reset flag as the device is initialized now */
4364 bp->flags &= ~BNXT_FLAG_FW_RESET;
4366 rc = bnxt_dev_start_op(bp->eth_dev);
4368 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4372 rc = bnxt_restore_filters(bp);
4376 rte_eth_fp_ops[bp->eth_dev->data->port_id].rx_pkt_burst =
4377 bp->eth_dev->rx_pkt_burst;
4378 rte_eth_fp_ops[bp->eth_dev->data->port_id].tx_pkt_burst =
4379 bp->eth_dev->tx_pkt_burst;
4382 PMD_DRV_LOG(INFO, "Port: %u Recovered from FW reset\n",
4383 bp->eth_dev->data->port_id);
4384 pthread_mutex_unlock(&bp->err_recovery_lock);
4388 bnxt_dev_stop(bp->eth_dev);
4390 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4391 bnxt_uninit_resources(bp, false);
4392 if (bp->eth_dev->data->dev_conf.intr_conf.rmv)
4393 rte_eth_dev_callback_process(bp->eth_dev,
4394 RTE_ETH_EVENT_INTR_RMV,
4396 pthread_mutex_unlock(&bp->err_recovery_lock);
4397 PMD_DRV_LOG(ERR, "Port %u: Failed to recover from FW reset\n",
4398 bp->eth_dev->data->port_id);
4401 void bnxt_dev_reset_and_resume(void *arg)
4403 struct bnxt *bp = arg;
4404 uint32_t us = US_PER_MS * bp->fw_reset_min_msecs;
4408 bnxt_dev_cleanup(bp);
4409 PMD_DRV_LOG(INFO, "Port: %u Finished bnxt_dev_cleanup\n",
4410 bp->eth_dev->data->port_id);
4412 bnxt_wait_for_device_shutdown(bp);
4414 /* During some fatal firmware error conditions, the PCI config space
4415 * register 0x2e which normally contains the subsystem ID will become
4416 * 0xffff. This register will revert back to the normal value after
4417 * the chip has completed core reset. If we detect this condition,
4418 * we can poll this config register immediately for the value to revert.
4420 if (bp->flags & BNXT_FLAG_FATAL_ERROR) {
4421 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4423 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4426 if (val == 0xffff) {
4427 bp->fw_reset_min_msecs = 0;
4432 rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp);
4434 PMD_DRV_LOG(ERR, "Port %u: Error setting recovery alarm",
4435 bp->eth_dev->data->port_id);
4438 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4440 struct bnxt_error_recovery_info *info = bp->recovery_info;
4441 uint32_t reg = info->status_regs[index];
4442 uint32_t type, offset, val = 0;
4445 type = BNXT_FW_STATUS_REG_TYPE(reg);
4446 offset = BNXT_FW_STATUS_REG_OFF(reg);
4449 case BNXT_FW_STATUS_REG_TYPE_CFG:
4450 ret = rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4452 PMD_DRV_LOG(ERR, "Failed to read PCI offset %#x",
4455 case BNXT_FW_STATUS_REG_TYPE_GRC:
4456 offset = info->mapped_status_regs[index];
4458 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4459 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4467 static int bnxt_fw_reset_all(struct bnxt *bp)
4469 struct bnxt_error_recovery_info *info = bp->recovery_info;
4473 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4474 /* Reset through primary function driver */
4475 for (i = 0; i < info->reg_array_cnt; i++)
4476 bnxt_write_fw_reset_reg(bp, i);
4477 /* Wait for time specified by FW after triggering reset */
4478 rte_delay_ms(info->primary_func_wait_period_after_reset);
4479 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4480 /* Reset with the help of Kong processor */
4481 rc = bnxt_hwrm_fw_reset(bp);
4483 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4489 static void bnxt_fw_reset_cb(void *arg)
4491 struct bnxt *bp = arg;
4492 struct bnxt_error_recovery_info *info = bp->recovery_info;
4495 /* Only Primary function can do FW reset */
4496 if (bnxt_is_primary_func(bp) &&
4497 bnxt_is_recovery_enabled(bp)) {
4498 rc = bnxt_fw_reset_all(bp);
4500 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4505 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4506 * EXCEPTION_FATAL_ASYNC event to all the functions
4507 * (including MASTER FUNC). After receiving this Async, all the active
4508 * drivers should treat this case as FW initiated recovery
4510 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4511 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4512 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4514 /* To recover from error */
4515 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4520 /* Driver should poll FW heartbeat, reset_counter with the frequency
4521 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4522 * When the driver detects heartbeat stop or change in reset_counter,
4523 * it has to trigger a reset to recover from the error condition.
4524 * A “primary function” is the function who will have the privilege to
4525 * initiate the chimp reset. The primary function will be elected by the
4526 * firmware and will be notified through async message.
4528 static void bnxt_check_fw_health(void *arg)
4530 struct bnxt *bp = arg;
4531 struct bnxt_error_recovery_info *info = bp->recovery_info;
4532 uint32_t val = 0, wait_msec;
4534 if (!info || !bnxt_is_recovery_enabled(bp) ||
4535 is_bnxt_in_error(bp))
4538 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4539 if (val == info->last_heart_beat)
4542 info->last_heart_beat = val;
4544 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4545 if (val != info->last_reset_counter)
4548 info->last_reset_counter = val;
4550 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4551 bnxt_check_fw_health, (void *)bp);
4555 /* Stop DMA to/from device */
4556 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4557 bp->flags |= BNXT_FLAG_FW_RESET;
4559 bnxt_stop_rxtx(bp->eth_dev);
4561 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4563 if (bnxt_is_primary_func(bp))
4564 wait_msec = info->primary_func_wait_period;
4566 wait_msec = info->normal_func_wait_period;
4568 rte_eal_alarm_set(US_PER_MS * wait_msec,
4569 bnxt_fw_reset_cb, (void *)bp);
4572 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4574 uint32_t polling_freq;
4576 pthread_mutex_lock(&bp->health_check_lock);
4578 if (!bnxt_is_recovery_enabled(bp))
4581 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4584 polling_freq = bp->recovery_info->driver_polling_freq;
4586 rte_eal_alarm_set(US_PER_MS * polling_freq,
4587 bnxt_check_fw_health, (void *)bp);
4588 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4591 pthread_mutex_unlock(&bp->health_check_lock);
4594 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4596 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4597 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4600 static bool bnxt_vf_pciid(uint16_t device_id)
4602 switch (device_id) {
4603 case BROADCOM_DEV_ID_57304_VF:
4604 case BROADCOM_DEV_ID_57406_VF:
4605 case BROADCOM_DEV_ID_5731X_VF:
4606 case BROADCOM_DEV_ID_5741X_VF:
4607 case BROADCOM_DEV_ID_57414_VF:
4608 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4609 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4610 case BROADCOM_DEV_ID_58802_VF:
4611 case BROADCOM_DEV_ID_57500_VF1:
4612 case BROADCOM_DEV_ID_57500_VF2:
4613 case BROADCOM_DEV_ID_58818_VF:
4621 /* Phase 5 device */
4622 static bool bnxt_p5_device(uint16_t device_id)
4624 switch (device_id) {
4625 case BROADCOM_DEV_ID_57508:
4626 case BROADCOM_DEV_ID_57504:
4627 case BROADCOM_DEV_ID_57502:
4628 case BROADCOM_DEV_ID_57508_MF1:
4629 case BROADCOM_DEV_ID_57504_MF1:
4630 case BROADCOM_DEV_ID_57502_MF1:
4631 case BROADCOM_DEV_ID_57508_MF2:
4632 case BROADCOM_DEV_ID_57504_MF2:
4633 case BROADCOM_DEV_ID_57502_MF2:
4634 case BROADCOM_DEV_ID_57500_VF1:
4635 case BROADCOM_DEV_ID_57500_VF2:
4636 case BROADCOM_DEV_ID_58812:
4637 case BROADCOM_DEV_ID_58814:
4638 case BROADCOM_DEV_ID_58818:
4639 case BROADCOM_DEV_ID_58818_VF:
4647 bool bnxt_stratus_device(struct bnxt *bp)
4649 uint16_t device_id = bp->pdev->id.device_id;
4651 switch (device_id) {
4652 case BROADCOM_DEV_ID_STRATUS_NIC:
4653 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4654 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4662 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev)
4664 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4665 struct bnxt *bp = eth_dev->data->dev_private;
4667 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4668 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4669 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4670 if (!bp->bar0 || !bp->doorbell_base) {
4671 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4675 bp->eth_dev = eth_dev;
4681 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4682 struct bnxt_ctx_pg_info *ctx_pg,
4687 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4688 const struct rte_memzone *mz = NULL;
4689 char mz_name[RTE_MEMZONE_NAMESIZE];
4690 rte_iova_t mz_phys_addr;
4691 uint64_t valid_bits = 0;
4698 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4700 rmem->page_size = BNXT_PAGE_SIZE;
4701 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4702 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4703 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4705 valid_bits = PTU_PTE_VALID;
4707 if (rmem->nr_pages > 1) {
4708 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4709 "bnxt_ctx_pg_tbl%s_%x_%d",
4710 suffix, idx, bp->eth_dev->data->port_id);
4711 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4712 mz = rte_memzone_lookup(mz_name);
4714 mz = rte_memzone_reserve_aligned(mz_name,
4716 bp->eth_dev->device->numa_node,
4718 RTE_MEMZONE_SIZE_HINT_ONLY |
4719 RTE_MEMZONE_IOVA_CONTIG,
4725 memset(mz->addr, 0, mz->len);
4726 mz_phys_addr = mz->iova;
4728 rmem->pg_tbl = mz->addr;
4729 rmem->pg_tbl_map = mz_phys_addr;
4730 rmem->pg_tbl_mz = mz;
4733 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4734 suffix, idx, bp->eth_dev->data->port_id);
4735 mz = rte_memzone_lookup(mz_name);
4737 mz = rte_memzone_reserve_aligned(mz_name,
4739 bp->eth_dev->device->numa_node,
4741 RTE_MEMZONE_SIZE_HINT_ONLY |
4742 RTE_MEMZONE_IOVA_CONTIG,
4748 memset(mz->addr, 0, mz->len);
4749 mz_phys_addr = mz->iova;
4751 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4752 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4753 rmem->dma_arr[i] = mz_phys_addr + sz;
4755 if (rmem->nr_pages > 1) {
4756 if (i == rmem->nr_pages - 2 &&
4757 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4758 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4759 else if (i == rmem->nr_pages - 1 &&
4760 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4761 valid_bits |= PTU_PTE_LAST;
4763 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4769 if (rmem->vmem_size)
4770 rmem->vmem = (void **)mz->addr;
4771 rmem->dma_arr[0] = mz_phys_addr;
4775 static void bnxt_free_ctx_mem(struct bnxt *bp)
4779 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4782 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4783 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4784 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4785 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4786 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4787 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4788 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4789 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4790 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4791 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4792 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4794 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4795 if (bp->ctx->tqm_mem[i])
4796 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4803 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4805 #define min_t(type, x, y) ({ \
4806 type __min1 = (x); \
4807 type __min2 = (y); \
4808 __min1 < __min2 ? __min1 : __min2; })
4810 #define max_t(type, x, y) ({ \
4811 type __max1 = (x); \
4812 type __max2 = (y); \
4813 __max1 > __max2 ? __max1 : __max2; })
4815 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4817 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4819 struct bnxt_ctx_pg_info *ctx_pg;
4820 struct bnxt_ctx_mem_info *ctx;
4821 uint32_t mem_size, ena, entries;
4822 uint32_t entries_sp, min;
4825 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4827 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4831 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4834 ctx_pg = &ctx->qp_mem;
4835 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4836 if (ctx->qp_entry_size) {
4837 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4838 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4843 ctx_pg = &ctx->srq_mem;
4844 ctx_pg->entries = ctx->srq_max_l2_entries;
4845 if (ctx->srq_entry_size) {
4846 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4847 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4852 ctx_pg = &ctx->cq_mem;
4853 ctx_pg->entries = ctx->cq_max_l2_entries;
4854 if (ctx->cq_entry_size) {
4855 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4856 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4861 ctx_pg = &ctx->vnic_mem;
4862 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4863 ctx->vnic_max_ring_table_entries;
4864 if (ctx->vnic_entry_size) {
4865 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4866 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4871 ctx_pg = &ctx->stat_mem;
4872 ctx_pg->entries = ctx->stat_max_entries;
4873 if (ctx->stat_entry_size) {
4874 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4875 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4880 min = ctx->tqm_min_entries_per_ring;
4882 entries_sp = ctx->qp_max_l2_entries +
4883 ctx->vnic_max_vnic_entries +
4884 2 * ctx->qp_min_qp1_entries + min;
4885 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4887 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4888 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4889 entries = clamp_t(uint32_t, entries, min,
4890 ctx->tqm_max_entries_per_ring);
4891 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4892 /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7.
4893 * i > 8 is other ext rings.
4895 ctx_pg = ctx->tqm_mem[i];
4896 ctx_pg->entries = i ? entries : entries_sp;
4897 if (ctx->tqm_entry_size) {
4898 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4899 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size,
4904 if (i < BNXT_MAX_TQM_LEGACY_RINGS)
4905 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4907 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8;
4910 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4911 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4914 "Failed to configure context mem: rc = %d\n", rc);
4916 ctx->flags |= BNXT_CTX_FLAG_INITED;
4921 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4923 struct rte_pci_device *pci_dev = bp->pdev;
4924 char mz_name[RTE_MEMZONE_NAMESIZE];
4925 const struct rte_memzone *mz = NULL;
4926 uint32_t total_alloc_len;
4927 rte_iova_t mz_phys_addr;
4929 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4932 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4933 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4934 pci_dev->addr.bus, pci_dev->addr.devid,
4935 pci_dev->addr.function, "rx_port_stats");
4936 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4937 mz = rte_memzone_lookup(mz_name);
4939 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4940 sizeof(struct rx_port_stats_ext) + 512);
4942 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4945 RTE_MEMZONE_SIZE_HINT_ONLY |
4946 RTE_MEMZONE_IOVA_CONTIG);
4950 memset(mz->addr, 0, mz->len);
4951 mz_phys_addr = mz->iova;
4953 bp->rx_mem_zone = (const void *)mz;
4954 bp->hw_rx_port_stats = mz->addr;
4955 bp->hw_rx_port_stats_map = mz_phys_addr;
4957 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4958 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4959 pci_dev->addr.bus, pci_dev->addr.devid,
4960 pci_dev->addr.function, "tx_port_stats");
4961 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4962 mz = rte_memzone_lookup(mz_name);
4964 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4965 sizeof(struct tx_port_stats_ext) + 512);
4967 mz = rte_memzone_reserve(mz_name,
4971 RTE_MEMZONE_SIZE_HINT_ONLY |
4972 RTE_MEMZONE_IOVA_CONTIG);
4976 memset(mz->addr, 0, mz->len);
4977 mz_phys_addr = mz->iova;
4979 bp->tx_mem_zone = (const void *)mz;
4980 bp->hw_tx_port_stats = mz->addr;
4981 bp->hw_tx_port_stats_map = mz_phys_addr;
4982 bp->flags |= BNXT_FLAG_PORT_STATS;
4984 /* Display extended statistics if FW supports it */
4985 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4986 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4987 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4990 bp->hw_rx_port_stats_ext = (void *)
4991 ((uint8_t *)bp->hw_rx_port_stats +
4992 sizeof(struct rx_port_stats));
4993 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4994 sizeof(struct rx_port_stats);
4995 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4997 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4998 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4999 bp->hw_tx_port_stats_ext = (void *)
5000 ((uint8_t *)bp->hw_tx_port_stats +
5001 sizeof(struct tx_port_stats));
5002 bp->hw_tx_port_stats_ext_map =
5003 bp->hw_tx_port_stats_map +
5004 sizeof(struct tx_port_stats);
5005 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
5011 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
5013 struct bnxt *bp = eth_dev->data->dev_private;
5014 size_t max_mac_addr = RTE_MIN(bp->max_l2_ctx, RTE_ETH_NUM_RECEIVE_MAC_ADDR);
5017 if (bp->max_l2_ctx > RTE_ETH_NUM_RECEIVE_MAC_ADDR)
5018 PMD_DRV_LOG(INFO, "Max number of MAC addrs supported is %d, but will be limited to %d\n",
5019 bp->max_l2_ctx, RTE_ETH_NUM_RECEIVE_MAC_ADDR);
5021 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
5022 RTE_ETHER_ADDR_LEN * max_mac_addr,
5024 if (eth_dev->data->mac_addrs == NULL) {
5025 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
5029 if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
5033 /* Generate a random MAC address, if none was assigned by PF */
5034 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5035 bnxt_eth_hw_addr_random(bp->mac_addr);
5037 "Assign random MAC:" RTE_ETHER_ADDR_PRT_FMT "\n",
5038 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5039 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5041 rc = bnxt_hwrm_set_mac(bp);
5046 /* Copy the permanent MAC from the FUNC_QCAPS response */
5047 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5050 * Allocate memory to hold multicast mac addresses added.
5051 * Used to restore them during reset recovery
5053 bp->mcast_addr_list = rte_zmalloc("bnxt_mcast_addr_tbl",
5054 sizeof(struct rte_ether_addr) *
5055 BNXT_MAX_MC_ADDRS, 0);
5056 if (bp->mcast_addr_list == NULL) {
5057 PMD_DRV_LOG(ERR, "Failed to allocate multicast addr table\n");
5060 bp->mc_list_dma_addr = rte_malloc_virt2iova(bp->mcast_addr_list);
5061 if (bp->mc_list_dma_addr == RTE_BAD_IOVA) {
5062 PMD_DRV_LOG(ERR, "Fail to map mcast_addr_list to physical memory\n");
5069 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5073 /* MAC is already configured in FW */
5074 if (BNXT_HAS_DFLT_MAC_SET(bp))
5077 /* Restore the old MAC configured */
5078 rc = bnxt_hwrm_set_mac(bp);
5080 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5085 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5090 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5092 if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
5093 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
5094 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
5095 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
5096 BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
5097 BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
5100 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5102 struct bnxt_error_recovery_info *info = bp->recovery_info;
5105 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5106 memset(info, 0, sizeof(*info));
5110 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5113 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5116 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5118 bp->recovery_info = info;
5121 static void bnxt_check_fw_status(struct bnxt *bp)
5125 if (!(bp->recovery_info &&
5126 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5129 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5130 if (fw_status != BNXT_FW_STATUS_HEALTHY)
5131 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5135 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5137 struct bnxt_error_recovery_info *info = bp->recovery_info;
5138 uint32_t status_loc;
5141 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5142 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5143 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5144 BNXT_GRCP_WINDOW_2_BASE +
5145 offsetof(struct hcomm_status,
5147 /* If the signature is absent, then FW does not support this feature */
5148 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5149 HCOMM_STATUS_SIGNATURE_VAL)
5153 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5157 bp->recovery_info = info;
5159 memset(info, 0, sizeof(*info));
5162 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5163 BNXT_GRCP_WINDOW_2_BASE +
5164 offsetof(struct hcomm_status,
5167 /* Only pre-map the FW health status GRC register */
5168 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5171 info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5172 info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5173 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5175 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5176 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5178 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5183 /* This function gets the FW version along with the
5184 * capabilities(MAX and current) of the function, vnic,
5185 * error recovery, phy and other chip related info
5187 static int bnxt_get_config(struct bnxt *bp)
5194 rc = bnxt_map_hcomm_fw_status_reg(bp);
5198 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5200 bnxt_check_fw_status(bp);
5204 rc = bnxt_hwrm_func_reset(bp);
5208 rc = bnxt_hwrm_vnic_qcaps(bp);
5212 rc = bnxt_hwrm_queue_qportcfg(bp);
5216 /* Get the MAX capabilities for this function.
5217 * This function also allocates context memory for TQM rings and
5218 * informs the firmware about this allocated backing store memory.
5220 rc = bnxt_hwrm_func_qcaps(bp);
5224 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5228 bnxt_hwrm_port_mac_qcfg(bp);
5230 bnxt_hwrm_parent_pf_qcfg(bp);
5232 bnxt_hwrm_port_phy_qcaps(bp);
5234 bnxt_alloc_error_recovery_info(bp);
5235 /* Get the adapter error recovery support info */
5236 rc = bnxt_hwrm_error_recovery_qcfg(bp);
5238 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5240 bnxt_hwrm_port_led_qcaps(bp);
5246 bnxt_init_locks(struct bnxt *bp)
5250 err = pthread_mutex_init(&bp->flow_lock, NULL);
5252 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5256 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5258 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5262 err = pthread_mutex_init(&bp->health_check_lock, NULL);
5264 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5268 err = pthread_mutex_init(&bp->err_recovery_lock, NULL);
5270 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n");
5275 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5279 rc = bnxt_get_config(bp);
5283 if (!reconfig_dev) {
5284 rc = bnxt_setup_mac_addr(bp->eth_dev);
5288 rc = bnxt_restore_dflt_mac(bp);
5293 bnxt_config_vf_req_fwd(bp);
5295 rc = bnxt_hwrm_func_driver_register(bp);
5297 PMD_DRV_LOG(ERR, "Failed to register driver");
5302 if (bp->pdev->max_vfs) {
5303 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5305 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5309 rc = bnxt_hwrm_allocate_pf_only(bp);
5312 "Failed to allocate PF resources");
5318 if (!reconfig_dev) {
5319 bp->rss_conf.rss_key = rte_zmalloc("bnxt_rss_key",
5320 HW_HASH_KEY_SIZE, 0);
5321 if (bp->rss_conf.rss_key == NULL) {
5322 PMD_DRV_LOG(ERR, "port %u cannot allocate RSS hash key memory",
5323 bp->eth_dev->data->port_id);
5328 rc = bnxt_alloc_mem(bp, reconfig_dev);
5332 rc = bnxt_setup_int(bp);
5336 rc = bnxt_request_int(bp);
5340 rc = bnxt_init_ctx_mem(bp);
5342 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5350 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5351 const char *value, void *opaque_arg)
5353 struct bnxt *bp = opaque_arg;
5354 unsigned long flow_xstat;
5357 if (!value || !opaque_arg) {
5359 "Invalid parameter passed to flow_xstat devarg.\n");
5363 flow_xstat = strtoul(value, &end, 10);
5364 if (end == NULL || *end != '\0' ||
5365 (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5367 "Invalid parameter passed to flow_xstat devarg.\n");
5371 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5373 "Invalid value passed to flow_xstat devarg.\n");
5377 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5378 if (BNXT_FLOW_XSTATS_EN(bp))
5379 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5385 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5386 const char *value, void *opaque_arg)
5388 struct bnxt *bp = opaque_arg;
5389 unsigned long max_num_kflows;
5392 if (!value || !opaque_arg) {
5394 "Invalid parameter passed to max_num_kflows devarg.\n");
5398 max_num_kflows = strtoul(value, &end, 10);
5399 if (end == NULL || *end != '\0' ||
5400 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5402 "Invalid parameter passed to max_num_kflows devarg.\n");
5406 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5408 "Invalid value passed to max_num_kflows devarg.\n");
5412 bp->max_num_kflows = max_num_kflows;
5413 if (bp->max_num_kflows)
5414 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5421 bnxt_parse_devarg_app_id(__rte_unused const char *key,
5422 const char *value, void *opaque_arg)
5424 struct bnxt *bp = opaque_arg;
5425 unsigned long app_id;
5428 if (!value || !opaque_arg) {
5430 "Invalid parameter passed to app-id "
5435 app_id = strtoul(value, &end, 10);
5436 if (end == NULL || *end != '\0' ||
5437 (app_id == ULONG_MAX && errno == ERANGE)) {
5439 "Invalid parameter passed to app_id "
5444 if (BNXT_DEVARG_APP_ID_INVALID(app_id)) {
5445 PMD_DRV_LOG(ERR, "Invalid app-id(%d) devargs.\n",
5450 bp->app_id = app_id;
5451 PMD_DRV_LOG(INFO, "app-id=%d feature enabled.\n", (uint16_t)app_id);
5457 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5458 const char *value, void *opaque_arg)
5460 struct bnxt_representor *vfr_bp = opaque_arg;
5461 unsigned long rep_is_pf;
5464 if (!value || !opaque_arg) {
5466 "Invalid parameter passed to rep_is_pf devargs.\n");
5470 rep_is_pf = strtoul(value, &end, 10);
5471 if (end == NULL || *end != '\0' ||
5472 (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5474 "Invalid parameter passed to rep_is_pf devargs.\n");
5478 if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5480 "Invalid value passed to rep_is_pf devargs.\n");
5484 vfr_bp->flags |= rep_is_pf;
5485 if (BNXT_REP_PF(vfr_bp))
5486 PMD_DRV_LOG(INFO, "PF representor\n");
5488 PMD_DRV_LOG(INFO, "VF representor\n");
5494 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5495 const char *value, void *opaque_arg)
5497 struct bnxt_representor *vfr_bp = opaque_arg;
5498 unsigned long rep_based_pf;
5501 if (!value || !opaque_arg) {
5503 "Invalid parameter passed to rep_based_pf "
5508 rep_based_pf = strtoul(value, &end, 10);
5509 if (end == NULL || *end != '\0' ||
5510 (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5512 "Invalid parameter passed to rep_based_pf "
5517 if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5519 "Invalid value passed to rep_based_pf devargs.\n");
5523 vfr_bp->rep_based_pf = rep_based_pf;
5524 vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
5526 PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5532 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5533 const char *value, void *opaque_arg)
5535 struct bnxt_representor *vfr_bp = opaque_arg;
5536 unsigned long rep_q_r2f;
5539 if (!value || !opaque_arg) {
5541 "Invalid parameter passed to rep_q_r2f "
5546 rep_q_r2f = strtoul(value, &end, 10);
5547 if (end == NULL || *end != '\0' ||
5548 (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5550 "Invalid parameter passed to rep_q_r2f "
5555 if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5557 "Invalid value passed to rep_q_r2f devargs.\n");
5561 vfr_bp->rep_q_r2f = rep_q_r2f;
5562 vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5563 PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5569 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5570 const char *value, void *opaque_arg)
5572 struct bnxt_representor *vfr_bp = opaque_arg;
5573 unsigned long rep_q_f2r;
5576 if (!value || !opaque_arg) {
5578 "Invalid parameter passed to rep_q_f2r "
5583 rep_q_f2r = strtoul(value, &end, 10);
5584 if (end == NULL || *end != '\0' ||
5585 (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5587 "Invalid parameter passed to rep_q_f2r "
5592 if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5594 "Invalid value passed to rep_q_f2r devargs.\n");
5598 vfr_bp->rep_q_f2r = rep_q_f2r;
5599 vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5600 PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5606 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5607 const char *value, void *opaque_arg)
5609 struct bnxt_representor *vfr_bp = opaque_arg;
5610 unsigned long rep_fc_r2f;
5613 if (!value || !opaque_arg) {
5615 "Invalid parameter passed to rep_fc_r2f "
5620 rep_fc_r2f = strtoul(value, &end, 10);
5621 if (end == NULL || *end != '\0' ||
5622 (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5624 "Invalid parameter passed to rep_fc_r2f "
5629 if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5631 "Invalid value passed to rep_fc_r2f devargs.\n");
5635 vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5636 vfr_bp->rep_fc_r2f = rep_fc_r2f;
5637 PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5643 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5644 const char *value, void *opaque_arg)
5646 struct bnxt_representor *vfr_bp = opaque_arg;
5647 unsigned long rep_fc_f2r;
5650 if (!value || !opaque_arg) {
5652 "Invalid parameter passed to rep_fc_f2r "
5657 rep_fc_f2r = strtoul(value, &end, 10);
5658 if (end == NULL || *end != '\0' ||
5659 (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5661 "Invalid parameter passed to rep_fc_f2r "
5666 if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5668 "Invalid value passed to rep_fc_f2r devargs.\n");
5672 vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5673 vfr_bp->rep_fc_f2r = rep_fc_f2r;
5674 PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5680 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5682 struct rte_kvargs *kvlist;
5685 if (devargs == NULL)
5688 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5693 * Handler for "flow_xstat" devarg.
5694 * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5696 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5697 bnxt_parse_devarg_flow_xstat, bp);
5702 * Handler for "max_num_kflows" devarg.
5703 * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5705 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5706 bnxt_parse_devarg_max_num_kflows, bp);
5712 * Handler for "app-id" devarg.
5713 * Invoked as for ex: "-a 000:00:0d.0,app-id=1"
5715 rte_kvargs_process(kvlist, BNXT_DEVARG_APP_ID,
5716 bnxt_parse_devarg_app_id, bp);
5718 rte_kvargs_free(kvlist);
5722 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5726 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5727 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5730 "Failed to alloc switch domain: %d\n", rc);
5733 "Switch domain allocated %d\n",
5734 bp->switch_domain_id);
5740 /* Allocate and initialize various fields in bnxt struct that
5741 * need to be allocated/destroyed only once in the lifetime of the driver
5743 static int bnxt_drv_init(struct rte_eth_dev *eth_dev)
5745 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5746 struct bnxt *bp = eth_dev->data->dev_private;
5749 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5751 if (bnxt_vf_pciid(pci_dev->id.device_id))
5752 bp->flags |= BNXT_FLAG_VF;
5754 if (bnxt_p5_device(pci_dev->id.device_id))
5755 bp->flags |= BNXT_FLAG_CHIP_P5;
5757 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5758 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5759 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5760 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5761 bp->flags |= BNXT_FLAG_STINGRAY;
5763 if (BNXT_TRUFLOW_EN(bp)) {
5764 /* extra mbuf field is required to store CFA code from mark */
5765 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5766 .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5767 .size = sizeof(bnxt_cfa_code_dynfield_t),
5768 .align = __alignof__(bnxt_cfa_code_dynfield_t),
5770 bnxt_cfa_code_dynfield_offset =
5771 rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5772 if (bnxt_cfa_code_dynfield_offset < 0) {
5774 "Failed to register mbuf field for TruFlow mark\n");
5779 rc = bnxt_map_pci_bars(eth_dev);
5782 "Failed to initialize board rc: %x\n", rc);
5786 rc = bnxt_alloc_pf_info(bp);
5790 rc = bnxt_alloc_link_info(bp);
5794 rc = bnxt_alloc_parent_info(bp);
5798 rc = bnxt_alloc_hwrm_resources(bp);
5801 "Failed to allocate response buffer rc: %x\n", rc);
5804 rc = bnxt_alloc_leds_info(bp);
5808 rc = bnxt_alloc_cos_queues(bp);
5812 rc = bnxt_init_locks(bp);
5816 rc = bnxt_alloc_switch_domain(bp);
5824 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5826 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5827 static int version_printed;
5831 if (version_printed++ == 0)
5832 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5834 eth_dev->dev_ops = &bnxt_dev_ops;
5835 eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5836 eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5837 eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5838 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5839 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5842 * For secondary processes, we don't initialise any further
5843 * as primary has already done this work.
5845 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5848 rte_eth_copy_pci_info(eth_dev, pci_dev);
5849 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
5851 bp = eth_dev->data->dev_private;
5853 /* Parse dev arguments passed on when starting the DPDK application. */
5854 rc = bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5858 rc = bnxt_drv_init(eth_dev);
5862 rc = bnxt_init_resources(bp, false);
5866 rc = bnxt_alloc_stats_mem(bp);
5871 "Found %s device at mem %" PRIX64 ", node addr %pM\n",
5873 pci_dev->mem_resource[0].phys_addr,
5874 pci_dev->mem_resource[0].addr);
5879 bnxt_dev_uninit(eth_dev);
5884 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5893 ctx->dma = RTE_BAD_IOVA;
5894 ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5897 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5899 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5900 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5901 bp->flow_stat->rx_fc_out_tbl.ctx_id,
5902 bp->flow_stat->max_fc,
5905 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5906 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5907 bp->flow_stat->tx_fc_out_tbl.ctx_id,
5908 bp->flow_stat->max_fc,
5911 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5912 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5913 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5915 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5916 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5917 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5919 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5920 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5921 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5923 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5924 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5925 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5928 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5930 bnxt_unregister_fc_ctx_mem(bp);
5932 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5933 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5934 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5935 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5938 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5940 if (BNXT_FLOW_XSTATS_EN(bp))
5941 bnxt_uninit_fc_ctx_mem(bp);
5945 bnxt_free_error_recovery_info(struct bnxt *bp)
5947 rte_free(bp->recovery_info);
5948 bp->recovery_info = NULL;
5949 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5953 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5958 bnxt_free_mem(bp, reconfig_dev);
5960 bnxt_hwrm_func_buf_unrgtr(bp);
5961 if (bp->pf != NULL) {
5962 rte_free(bp->pf->vf_req_buf);
5963 bp->pf->vf_req_buf = NULL;
5966 rc = bnxt_hwrm_func_driver_unregister(bp);
5967 bp->flags &= ~BNXT_FLAG_REGISTERED;
5968 bnxt_free_ctx_mem(bp);
5969 if (!reconfig_dev) {
5970 bnxt_free_hwrm_resources(bp);
5971 bnxt_free_error_recovery_info(bp);
5972 rte_free(bp->mcast_addr_list);
5973 bp->mcast_addr_list = NULL;
5974 rte_free(bp->rss_conf.rss_key);
5975 bp->rss_conf.rss_key = NULL;
5978 bnxt_uninit_ctx_mem(bp);
5980 bnxt_free_flow_stats_info(bp);
5981 if (bp->rep_info != NULL)
5982 bnxt_free_switch_domain(bp);
5983 bnxt_free_rep_info(bp);
5984 rte_free(bp->ptp_cfg);
5990 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5992 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5995 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5997 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5998 bnxt_dev_close_op(eth_dev);
6003 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
6005 struct bnxt *bp = eth_dev->data->dev_private;
6006 struct rte_eth_dev *vf_rep_eth_dev;
6012 for (i = 0; i < bp->num_reps; i++) {
6013 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
6014 if (!vf_rep_eth_dev)
6016 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
6017 vf_rep_eth_dev->data->port_id);
6018 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
6020 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
6021 eth_dev->data->port_id);
6022 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
6027 static void bnxt_free_rep_info(struct bnxt *bp)
6029 rte_free(bp->rep_info);
6030 bp->rep_info = NULL;
6031 rte_free(bp->cfa_code_map);
6032 bp->cfa_code_map = NULL;
6035 static int bnxt_init_rep_info(struct bnxt *bp)
6042 bp->rep_info = rte_zmalloc("bnxt_rep_info",
6043 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS(bp),
6045 if (!bp->rep_info) {
6046 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
6049 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
6050 sizeof(*bp->cfa_code_map) *
6051 BNXT_MAX_CFA_CODE, 0);
6052 if (!bp->cfa_code_map) {
6053 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
6054 bnxt_free_rep_info(bp);
6058 for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
6059 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
6061 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
6063 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
6064 bnxt_free_rep_info(bp);
6068 rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
6070 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
6071 bnxt_free_rep_info(bp);
6078 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
6079 struct rte_eth_devargs *eth_da,
6080 struct rte_eth_dev *backing_eth_dev,
6081 const char *dev_args)
6083 struct rte_eth_dev *vf_rep_eth_dev;
6084 char name[RTE_ETH_NAME_MAX_LEN];
6085 struct bnxt *backing_bp = backing_eth_dev->data->dev_private;
6086 uint16_t max_vf_reps = BNXT_MAX_VF_REPS(backing_bp);
6090 struct rte_kvargs *kvlist = NULL;
6092 if (eth_da->type == RTE_ETH_REPRESENTOR_NONE)
6094 if (eth_da->type != RTE_ETH_REPRESENTOR_VF) {
6095 PMD_DRV_LOG(ERR, "unsupported representor type %d\n",
6099 num_rep = eth_da->nb_representor_ports;
6100 if (num_rep > max_vf_reps) {
6101 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
6102 num_rep, max_vf_reps);
6106 if (num_rep >= RTE_MAX_ETHPORTS) {
6108 "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6109 num_rep, RTE_MAX_ETHPORTS);
6113 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6115 "Not a PF or trusted VF. No Representor support\n");
6116 /* Returning an error is not an option.
6117 * Applications are not handling this correctly
6122 if (bnxt_init_rep_info(backing_bp))
6125 for (i = 0; i < num_rep; i++) {
6126 struct bnxt_representor representor = {
6127 .vf_id = eth_da->representor_ports[i],
6128 .switch_domain_id = backing_bp->switch_domain_id,
6129 .parent_dev = backing_eth_dev
6132 if (representor.vf_id >= max_vf_reps) {
6133 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6134 representor.vf_id, max_vf_reps);
6138 /* representor port net_bdf_port */
6139 snprintf(name, sizeof(name), "net_%s_representor_%d",
6140 pci_dev->device.name, eth_da->representor_ports[i]);
6142 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
6145 * Handler for "rep_is_pf" devarg.
6146 * Invoked as for ex: "-a 000:00:0d.0,
6147 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6149 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
6150 bnxt_parse_devarg_rep_is_pf,
6151 (void *)&representor);
6157 * Handler for "rep_based_pf" devarg.
6158 * Invoked as for ex: "-a 000:00:0d.0,
6159 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6161 ret = rte_kvargs_process(kvlist,
6162 BNXT_DEVARG_REP_BASED_PF,
6163 bnxt_parse_devarg_rep_based_pf,
6164 (void *)&representor);
6170 * Handler for "rep_based_pf" devarg.
6171 * Invoked as for ex: "-a 000:00:0d.0,
6172 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6174 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
6175 bnxt_parse_devarg_rep_q_r2f,
6176 (void *)&representor);
6182 * Handler for "rep_based_pf" devarg.
6183 * Invoked as for ex: "-a 000:00:0d.0,
6184 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6186 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
6187 bnxt_parse_devarg_rep_q_f2r,
6188 (void *)&representor);
6194 * Handler for "rep_based_pf" devarg.
6195 * Invoked as for ex: "-a 000:00:0d.0,
6196 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6198 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
6199 bnxt_parse_devarg_rep_fc_r2f,
6200 (void *)&representor);
6206 * Handler for "rep_based_pf" devarg.
6207 * Invoked as for ex: "-a 000:00:0d.0,
6208 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6210 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
6211 bnxt_parse_devarg_rep_fc_f2r,
6212 (void *)&representor);
6219 ret = rte_eth_dev_create(&pci_dev->device, name,
6220 sizeof(struct bnxt_representor),
6222 bnxt_representor_init,
6225 PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6226 "representor %s.", name);
6230 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6231 if (!vf_rep_eth_dev) {
6232 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6233 " for VF-Rep: %s.", name);
6238 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6239 backing_eth_dev->data->port_id);
6240 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6242 backing_bp->num_reps++;
6246 rte_kvargs_free(kvlist);
6250 /* If num_rep > 1, then rollback already created
6251 * ports, since we'll be failing the probe anyway
6254 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6256 rte_kvargs_free(kvlist);
6261 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6262 struct rte_pci_device *pci_dev)
6264 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6265 struct rte_eth_dev *backing_eth_dev;
6269 if (pci_dev->device.devargs) {
6270 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6276 num_rep = eth_da.nb_representor_ports;
6277 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6280 /* We could come here after first level of probe is already invoked
6281 * as part of an application bringup(OVS-DPDK vswitchd), so first check
6282 * for already allocated eth_dev for the backing device (PF/Trusted VF)
6284 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6285 if (backing_eth_dev == NULL) {
6286 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6287 sizeof(struct bnxt),
6288 eth_dev_pci_specific_init, pci_dev,
6289 bnxt_dev_init, NULL);
6291 if (ret || !num_rep)
6294 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6296 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6297 backing_eth_dev->data->port_id);
6302 /* probe representor ports now */
6303 ret = bnxt_rep_port_probe(pci_dev, ð_da, backing_eth_dev,
6304 pci_dev->device.devargs->args);
6309 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6311 struct rte_eth_dev *eth_dev;
6313 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6315 return 0; /* Invoked typically only by OVS-DPDK, by the
6316 * time it comes here the eth_dev is already
6317 * deleted by rte_eth_dev_close(), so returning
6318 * +ve value will at least help in proper cleanup
6321 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6322 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6323 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6324 return rte_eth_dev_destroy(eth_dev,
6325 bnxt_representor_uninit);
6327 return rte_eth_dev_destroy(eth_dev,
6330 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6334 static struct rte_pci_driver bnxt_rte_pmd = {
6335 .id_table = bnxt_pci_id_map,
6336 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6337 RTE_PCI_DRV_INTR_RMV |
6338 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6341 .probe = bnxt_pci_probe,
6342 .remove = bnxt_pci_remove,
6346 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6348 if (strcmp(dev->device->driver->name, drv->driver.name))
6354 bool is_bnxt_supported(struct rte_eth_dev *dev)
6356 return is_device_supported(dev, &bnxt_rte_pmd);
6359 RTE_LOG_REGISTER_SUFFIX(bnxt_logtype_driver, driver, NOTICE);
6360 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6361 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);