drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16
  17 #include "bnxt.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_reps.h"
  22 #include "bnxt_ring.h"
  23 #include "bnxt_rxq.h"
  24 #include "bnxt_rxr.h"
  25 #include "bnxt_stats.h"
  26 #include "bnxt_txq.h"
  27 #include "bnxt_txr.h"
  28 #include "bnxt_vnic.h"
  29 #include "hsi_struct_def_dpdk.h"
  30 #include "bnxt_nvm_defs.h"
  31 #include "bnxt_tf_common.h"
  32 #include "ulp_flow_db.h"
  33
  34 #define DRV_MODULE_NAME         "bnxt"
  35 static const char bnxt_version[] =
  36         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  37
  38 /*
  39  * The set of PCI devices this driver supports
  40  */
  41 static const struct rte_pci_id bnxt_pci_id_map[] = {
  42         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  43                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  95         { .vendor_id = 0, /* sentinel */ },
  96 };
  97
  98 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
  99 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
 100 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
 101 #define BNXT_DEVARG_REPRESENTOR "representor"
 102 #define BNXT_DEVARG_REP_BASED_PF  "rep-based-pf"
 103 #define BNXT_DEVARG_REP_IS_PF  "rep-is-pf"
 104 #define BNXT_DEVARG_REP_Q_R2F  "rep-q-r2f"
 105 #define BNXT_DEVARG_REP_Q_F2R  "rep-q-f2r"
 106 #define BNXT_DEVARG_REP_FC_R2F  "rep-fc-r2f"
 107 #define BNXT_DEVARG_REP_FC_F2R  "rep-fc-f2r"
 108
 109 static const char *const bnxt_dev_args[] = {
 110         BNXT_DEVARG_REPRESENTOR,
 111         BNXT_DEVARG_TRUFLOW,
 112         BNXT_DEVARG_FLOW_XSTAT,
 113         BNXT_DEVARG_MAX_NUM_KFLOWS,
 114         BNXT_DEVARG_REP_BASED_PF,
 115         BNXT_DEVARG_REP_IS_PF,
 116         BNXT_DEVARG_REP_Q_R2F,
 117         BNXT_DEVARG_REP_Q_F2R,
 118         BNXT_DEVARG_REP_FC_R2F,
 119         BNXT_DEVARG_REP_FC_F2R,
 120         NULL
 121 };
 122
 123 /*
 124  * truflow == false to disable the feature
 125  * truflow == true to enable the feature
 126  */
 127 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 128
 129 /*
 130  * flow_xstat == false to disable the feature
 131  * flow_xstat == true to enable the feature
 132  */
 133 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 134
 135 /*
 136  * rep_is_pf == false to indicate VF representor
 137  * rep_is_pf == true to indicate PF representor
 138  */
 139 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)        ((rep_is_pf) > 1)
 140
 141 /*
 142  * rep_based_pf == Physical index of the PF
 143  */
 144 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)  ((rep_based_pf) > 15)
 145 /*
 146  * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
 147  */
 148 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)        ((rep_q_r2f) > 3)
 149
 150 /*
 151  * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
 152  */
 153 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)        ((rep_q_f2r) > 3)
 154
 155 /*
 156  * rep_fc_r2f == Flow control for the representor to endpoint direction
 157  */
 158 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)      ((rep_fc_r2f) > 1)
 159
 160 /*
 161  * rep_fc_f2r == Flow control for the endpoint to representor direction
 162  */
 163 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)      ((rep_fc_f2r) > 1)
 164
 165 /*
 166  * max_num_kflows must be >= 32
 167  * and must be a power-of-2 supported value
 168  * return: 1 -> invalid
 169  *         0 -> valid
 170  */
 171 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 172 {
 173         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 174                 return 1;
 175         return 0;
 176 }
 177
 178 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 179 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 180 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 181 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 182 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 183 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 184 static void bnxt_dev_recover(void *arg);
 185 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 186 static void bnxt_free_rep_info(struct bnxt *bp);
 187
 188 int is_bnxt_in_error(struct bnxt *bp)
 189 {
 190         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 191                 return -EIO;
 192         if (bp->flags & BNXT_FLAG_FW_RESET)
 193                 return -EBUSY;
 194
 195         return 0;
 196 }
 197
 198 /***********************/
 199
 200 /*
 201  * High level utility functions
 202  */
 203
 204 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 205 {
 206         if (!BNXT_CHIP_THOR(bp))
 207                 return 1;
 208
 209         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 210                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 211                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 212 }
 213
 214 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 215 {
 216         if (!BNXT_CHIP_THOR(bp))
 217                 return HW_HASH_INDEX_SIZE;
 218
 219         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 220 }
 221
 222 static void bnxt_free_parent_info(struct bnxt *bp)
 223 {
 224         rte_free(bp->parent);
 225 }
 226
 227 static void bnxt_free_pf_info(struct bnxt *bp)
 228 {
 229         rte_free(bp->pf);
 230 }
 231
 232 static void bnxt_free_link_info(struct bnxt *bp)
 233 {
 234         rte_free(bp->link_info);
 235 }
 236
 237 static void bnxt_free_leds_info(struct bnxt *bp)
 238 {
 239         if (BNXT_VF(bp))
 240                 return;
 241
 242         rte_free(bp->leds);
 243         bp->leds = NULL;
 244 }
 245
 246 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 247 {
 248         rte_free(bp->flow_stat);
 249         bp->flow_stat = NULL;
 250 }
 251
 252 static void bnxt_free_cos_queues(struct bnxt *bp)
 253 {
 254         rte_free(bp->rx_cos_queue);
 255         rte_free(bp->tx_cos_queue);
 256 }
 257
 258 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 259 {
 260         bnxt_free_filter_mem(bp);
 261         bnxt_free_vnic_attributes(bp);
 262         bnxt_free_vnic_mem(bp);
 263
 264         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 265          * If the number of rings change across fw update,
 266          * we don't have much choice except to warn the user.
 267          */
 268         if (!reconfig) {
 269                 bnxt_free_stats(bp);
 270                 bnxt_free_tx_rings(bp);
 271                 bnxt_free_rx_rings(bp);
 272         }
 273         bnxt_free_async_cp_ring(bp);
 274         bnxt_free_rxtx_nq_ring(bp);
 275
 276         rte_free(bp->grp_info);
 277         bp->grp_info = NULL;
 278 }
 279
 280 static int bnxt_alloc_parent_info(struct bnxt *bp)
 281 {
 282         bp->parent = rte_zmalloc("bnxt_parent_info",
 283                                  sizeof(struct bnxt_parent_info), 0);
 284         if (bp->parent == NULL)
 285                 return -ENOMEM;
 286
 287         return 0;
 288 }
 289
 290 static int bnxt_alloc_pf_info(struct bnxt *bp)
 291 {
 292         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 293         if (bp->pf == NULL)
 294                 return -ENOMEM;
 295
 296         return 0;
 297 }
 298
 299 static int bnxt_alloc_link_info(struct bnxt *bp)
 300 {
 301         bp->link_info =
 302                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 303         if (bp->link_info == NULL)
 304                 return -ENOMEM;
 305
 306         return 0;
 307 }
 308
 309 static int bnxt_alloc_leds_info(struct bnxt *bp)
 310 {
 311         if (BNXT_VF(bp))
 312                 return 0;
 313
 314         bp->leds = rte_zmalloc("bnxt_leds",
 315                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 316                                0);
 317         if (bp->leds == NULL)
 318                 return -ENOMEM;
 319
 320         return 0;
 321 }
 322
 323 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 324 {
 325         bp->rx_cos_queue =
 326                 rte_zmalloc("bnxt_rx_cosq",
 327                             BNXT_COS_QUEUE_COUNT *
 328                             sizeof(struct bnxt_cos_queue_info),
 329                             0);
 330         if (bp->rx_cos_queue == NULL)
 331                 return -ENOMEM;
 332
 333         bp->tx_cos_queue =
 334                 rte_zmalloc("bnxt_tx_cosq",
 335                             BNXT_COS_QUEUE_COUNT *
 336                             sizeof(struct bnxt_cos_queue_info),
 337                             0);
 338         if (bp->tx_cos_queue == NULL)
 339                 return -ENOMEM;
 340
 341         return 0;
 342 }
 343
 344 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 345 {
 346         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 347                                     sizeof(struct bnxt_flow_stat_info), 0);
 348         if (bp->flow_stat == NULL)
 349                 return -ENOMEM;
 350
 351         return 0;
 352 }
 353
 354 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 355 {
 356         int rc;
 357
 358         rc = bnxt_alloc_ring_grps(bp);
 359         if (rc)
 360                 goto alloc_mem_err;
 361
 362         rc = bnxt_alloc_async_ring_struct(bp);
 363         if (rc)
 364                 goto alloc_mem_err;
 365
 366         rc = bnxt_alloc_vnic_mem(bp);
 367         if (rc)
 368                 goto alloc_mem_err;
 369
 370         rc = bnxt_alloc_vnic_attributes(bp);
 371         if (rc)
 372                 goto alloc_mem_err;
 373
 374         rc = bnxt_alloc_filter_mem(bp);
 375         if (rc)
 376                 goto alloc_mem_err;
 377
 378         rc = bnxt_alloc_async_cp_ring(bp);
 379         if (rc)
 380                 goto alloc_mem_err;
 381
 382         rc = bnxt_alloc_rxtx_nq_ring(bp);
 383         if (rc)
 384                 goto alloc_mem_err;
 385
 386         if (BNXT_FLOW_XSTATS_EN(bp)) {
 387                 rc = bnxt_alloc_flow_stats_info(bp);
 388                 if (rc)
 389                         goto alloc_mem_err;
 390         }
 391
 392         return 0;
 393
 394 alloc_mem_err:
 395         bnxt_free_mem(bp, reconfig);
 396         return rc;
 397 }
 398
 399 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 400 {
 401         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 402         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 403         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 404         struct bnxt_rx_queue *rxq;
 405         unsigned int j;
 406         int rc;
 407
 408         rc = bnxt_vnic_grp_alloc(bp, vnic);
 409         if (rc)
 410                 goto err_out;
 411
 412         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 413                     vnic_id, vnic, vnic->fw_grp_ids);
 414
 415         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 416         if (rc)
 417                 goto err_out;
 418
 419         /* Alloc RSS context only if RSS mode is enabled */
 420         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 421                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 422
 423                 rc = 0;
 424                 for (j = 0; j < nr_ctxs; j++) {
 425                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 426                         if (rc)
 427                                 break;
 428                 }
 429                 if (rc) {
 430                         PMD_DRV_LOG(ERR,
 431                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 432                                     vnic_id, j, rc);
 433                         goto err_out;
 434                 }
 435                 vnic->num_lb_ctxts = nr_ctxs;
 436         }
 437
 438         /*
 439          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 440          * setting is not available at this time, it will not be
 441          * configured correctly in the CFA.
 442          */
 443         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 444                 vnic->vlan_strip = true;
 445         else
 446                 vnic->vlan_strip = false;
 447
 448         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 449         if (rc)
 450                 goto err_out;
 451
 452         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 453         if (rc)
 454                 goto err_out;
 455
 456         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 457                 rxq = bp->eth_dev->data->rx_queues[j];
 458
 459                 PMD_DRV_LOG(DEBUG,
 460                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 461                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 462
 463                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 464                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 465                 else
 466                         vnic->rx_queue_cnt++;
 467         }
 468
 469         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 470
 471         rc = bnxt_vnic_rss_configure(bp, vnic);
 472         if (rc)
 473                 goto err_out;
 474
 475         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 476
 477         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 478                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 479         else
 480                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 481
 482         return 0;
 483 err_out:
 484         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 485                     vnic_id, rc);
 486         return rc;
 487 }
 488
 489 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 490 {
 491         int rc = 0;
 492
 493         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 494                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 495         if (rc)
 496                 return rc;
 497
 498         PMD_DRV_LOG(DEBUG,
 499                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 500                     " rx_fc_in_tbl.ctx_id = %d\n",
 501                     bp->flow_stat->rx_fc_in_tbl.va,
 502                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 503                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 504
 505         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 506                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 507         if (rc)
 508                 return rc;
 509
 510         PMD_DRV_LOG(DEBUG,
 511                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 512                     " rx_fc_out_tbl.ctx_id = %d\n",
 513                     bp->flow_stat->rx_fc_out_tbl.va,
 514                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 515                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 516
 517         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 518                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 519         if (rc)
 520                 return rc;
 521
 522         PMD_DRV_LOG(DEBUG,
 523                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 524                     " tx_fc_in_tbl.ctx_id = %d\n",
 525                     bp->flow_stat->tx_fc_in_tbl.va,
 526                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 527                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 528
 529         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 530                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 531         if (rc)
 532                 return rc;
 533
 534         PMD_DRV_LOG(DEBUG,
 535                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 536                     " tx_fc_out_tbl.ctx_id = %d\n",
 537                     bp->flow_stat->tx_fc_out_tbl.va,
 538                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 539                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 540
 541         memset(bp->flow_stat->rx_fc_out_tbl.va,
 542                0,
 543                bp->flow_stat->rx_fc_out_tbl.size);
 544         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 545                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 546                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 547                                        bp->flow_stat->max_fc,
 548                                        true);
 549         if (rc)
 550                 return rc;
 551
 552         memset(bp->flow_stat->tx_fc_out_tbl.va,
 553                0,
 554                bp->flow_stat->tx_fc_out_tbl.size);
 555         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 556                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 557                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 558                                        bp->flow_stat->max_fc,
 559                                        true);
 560
 561         return rc;
 562 }
 563
 564 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 565                                   struct bnxt_ctx_mem_buf_info *ctx)
 566 {
 567         if (!ctx)
 568                 return -EINVAL;
 569
 570         ctx->va = rte_zmalloc(type, size, 0);
 571         if (ctx->va == NULL)
 572                 return -ENOMEM;
 573         rte_mem_lock_page(ctx->va);
 574         ctx->size = size;
 575         ctx->dma = rte_mem_virt2iova(ctx->va);
 576         if (ctx->dma == RTE_BAD_IOVA)
 577                 return -ENOMEM;
 578
 579         return 0;
 580 }
 581
 582 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 583 {
 584         struct rte_pci_device *pdev = bp->pdev;
 585         char type[RTE_MEMZONE_NAMESIZE];
 586         uint16_t max_fc;
 587         int rc = 0;
 588
 589         max_fc = bp->flow_stat->max_fc;
 590
 591         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 592                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 593         /* 4 bytes for each counter-id */
 594         rc = bnxt_alloc_ctx_mem_buf(type,
 595                                     max_fc * 4,
 596                                     &bp->flow_stat->rx_fc_in_tbl);
 597         if (rc)
 598                 return rc;
 599
 600         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 601                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 602         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 603         rc = bnxt_alloc_ctx_mem_buf(type,
 604                                     max_fc * 16,
 605                                     &bp->flow_stat->rx_fc_out_tbl);
 606         if (rc)
 607                 return rc;
 608
 609         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 610                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 611         /* 4 bytes for each counter-id */
 612         rc = bnxt_alloc_ctx_mem_buf(type,
 613                                     max_fc * 4,
 614                                     &bp->flow_stat->tx_fc_in_tbl);
 615         if (rc)
 616                 return rc;
 617
 618         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 619                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 620         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 621         rc = bnxt_alloc_ctx_mem_buf(type,
 622                                     max_fc * 16,
 623                                     &bp->flow_stat->tx_fc_out_tbl);
 624         if (rc)
 625                 return rc;
 626
 627         rc = bnxt_register_fc_ctx_mem(bp);
 628
 629         return rc;
 630 }
 631
 632 static int bnxt_init_ctx_mem(struct bnxt *bp)
 633 {
 634         int rc = 0;
 635
 636         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 637             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 638             !BNXT_FLOW_XSTATS_EN(bp))
 639                 return 0;
 640
 641         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 642         if (rc)
 643                 return rc;
 644
 645         rc = bnxt_init_fc_ctx_mem(bp);
 646
 647         return rc;
 648 }
 649
 650 static int bnxt_update_phy_setting(struct bnxt *bp)
 651 {
 652         struct rte_eth_link new;
 653         int rc;
 654
 655         rc = bnxt_get_hwrm_link_config(bp, &new);
 656         if (rc) {
 657                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 658                 return rc;
 659         }
 660
 661         /*
 662          * On BCM957508-N2100 adapters, FW will not allow any user other
 663          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 664          * always returns link up. Force phy update always in that case.
 665          */
 666         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 667                 rc = bnxt_set_hwrm_link_config(bp, true);
 668                 if (rc) {
 669                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 670                         return rc;
 671                 }
 672         }
 673
 674         return rc;
 675 }
 676
 677 static int bnxt_init_chip(struct bnxt *bp)
 678 {
 679         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 680         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 681         uint32_t intr_vector = 0;
 682         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 683         uint32_t vec = BNXT_MISC_VEC_ID;
 684         unsigned int i, j;
 685         int rc;
 686
 687         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 688                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 689                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 690                 bp->flags |= BNXT_FLAG_JUMBO;
 691         } else {
 692                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 693                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 694                 bp->flags &= ~BNXT_FLAG_JUMBO;
 695         }
 696
 697         /* THOR does not support ring groups.
 698          * But we will use the array to save RSS context IDs.
 699          */
 700         if (BNXT_CHIP_THOR(bp))
 701                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 702
 703         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 704         if (rc) {
 705                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 706                 goto err_out;
 707         }
 708
 709         rc = bnxt_alloc_hwrm_rings(bp);
 710         if (rc) {
 711                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 712                 goto err_out;
 713         }
 714
 715         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 716         if (rc) {
 717                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 718                 goto err_out;
 719         }
 720
 721         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 722                 goto skip_cosq_cfg;
 723
 724         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 725                 if (bp->rx_cos_queue[i].id != 0xff) {
 726                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 727
 728                         if (!vnic) {
 729                                 PMD_DRV_LOG(ERR,
 730                                             "Num pools more than FW profile\n");
 731                                 rc = -EINVAL;
 732                                 goto err_out;
 733                         }
 734                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 735                         bp->rx_cosq_cnt++;
 736                 }
 737         }
 738
 739 skip_cosq_cfg:
 740         rc = bnxt_mq_rx_configure(bp);
 741         if (rc) {
 742                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 743                 goto err_out;
 744         }
 745
 746         /* VNIC configuration */
 747         for (i = 0; i < bp->nr_vnics; i++) {
 748                 rc = bnxt_setup_one_vnic(bp, i);
 749                 if (rc)
 750                         goto err_out;
 751         }
 752
 753         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 754         if (rc) {
 755                 PMD_DRV_LOG(ERR,
 756                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 757                 goto err_out;
 758         }
 759
 760         /* check and configure queue intr-vector mapping */
 761         if ((rte_intr_cap_multiple(intr_handle) ||
 762              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 763             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 764                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 765                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 766                 if (intr_vector > bp->rx_cp_nr_rings) {
 767                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 768                                         bp->rx_cp_nr_rings);
 769                         return -ENOTSUP;
 770                 }
 771                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 772                 if (rc)
 773                         return rc;
 774         }
 775
 776         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 777                 intr_handle->intr_vec =
 778                         rte_zmalloc("intr_vec",
 779                                     bp->eth_dev->data->nb_rx_queues *
 780                                     sizeof(int), 0);
 781                 if (intr_handle->intr_vec == NULL) {
 782                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 783                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 784                         rc = -ENOMEM;
 785                         goto err_disable;
 786                 }
 787                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 788                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 789                          intr_handle->intr_vec, intr_handle->nb_efd,
 790                         intr_handle->max_intr);
 791                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 792                      queue_id++) {
 793                         intr_handle->intr_vec[queue_id] =
 794                                                         vec + BNXT_RX_VEC_START;
 795                         if (vec < base + intr_handle->nb_efd - 1)
 796                                 vec++;
 797                 }
 798         }
 799
 800         /* enable uio/vfio intr/eventfd mapping */
 801         rc = rte_intr_enable(intr_handle);
 802 #ifndef RTE_EXEC_ENV_FREEBSD
 803         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 804         if (rc)
 805                 goto err_free;
 806 #endif
 807
 808         rc = bnxt_update_phy_setting(bp);
 809         if (rc)
 810                 goto err_free;
 811
 812         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 813         if (!bp->mark_table)
 814                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 815
 816         return 0;
 817
 818 err_free:
 819         rte_free(intr_handle->intr_vec);
 820 err_disable:
 821         rte_intr_efd_disable(intr_handle);
 822 err_out:
 823         /* Some of the error status returned by FW may not be from errno.h */
 824         if (rc > 0)
 825                 rc = -EIO;
 826
 827         return rc;
 828 }
 829
 830 static int bnxt_shutdown_nic(struct bnxt *bp)
 831 {
 832         bnxt_free_all_hwrm_resources(bp);
 833         bnxt_free_all_filters(bp);
 834         bnxt_free_all_vnics(bp);
 835         return 0;
 836 }
 837
 838 /*
 839  * Device configuration and status function
 840  */
 841
 842 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 843 {
 844         uint32_t link_speed = bp->link_info->support_speeds;
 845         uint32_t speed_capa = 0;
 846
 847         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 848                 speed_capa |= ETH_LINK_SPEED_100M;
 849         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 850                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 851         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 852                 speed_capa |= ETH_LINK_SPEED_1G;
 853         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 854                 speed_capa |= ETH_LINK_SPEED_2_5G;
 855         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 856                 speed_capa |= ETH_LINK_SPEED_10G;
 857         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 858                 speed_capa |= ETH_LINK_SPEED_20G;
 859         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 860                 speed_capa |= ETH_LINK_SPEED_25G;
 861         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 862                 speed_capa |= ETH_LINK_SPEED_40G;
 863         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 864                 speed_capa |= ETH_LINK_SPEED_50G;
 865         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 866                 speed_capa |= ETH_LINK_SPEED_100G;
 867         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB)
 868                 speed_capa |= ETH_LINK_SPEED_200G;
 869
 870         if (bp->link_info->auto_mode ==
 871             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 872                 speed_capa |= ETH_LINK_SPEED_FIXED;
 873         else
 874                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 875
 876         return speed_capa;
 877 }
 878
 879 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 880                                 struct rte_eth_dev_info *dev_info)
 881 {
 882         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 883         struct bnxt *bp = eth_dev->data->dev_private;
 884         uint16_t max_vnics, i, j, vpool, vrxq;
 885         unsigned int max_rx_rings;
 886         int rc;
 887
 888         rc = is_bnxt_in_error(bp);
 889         if (rc)
 890                 return rc;
 891
 892         /* MAC Specifics */
 893         dev_info->max_mac_addrs = bp->max_l2_ctx;
 894         dev_info->max_hash_mac_addrs = 0;
 895
 896         /* PF/VF specifics */
 897         if (BNXT_PF(bp))
 898                 dev_info->max_vfs = pdev->max_vfs;
 899
 900         max_rx_rings = BNXT_MAX_RINGS(bp);
 901         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 902         dev_info->max_rx_queues = max_rx_rings;
 903         dev_info->max_tx_queues = max_rx_rings;
 904         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 905         dev_info->hash_key_size = 40;
 906         max_vnics = bp->max_vnics;
 907
 908         /* MTU specifics */
 909         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 910         dev_info->max_mtu = BNXT_MAX_MTU;
 911
 912         /* Fast path specifics */
 913         dev_info->min_rx_bufsize = 1;
 914         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 915
 916         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 917         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 918                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 919         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 920         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 921
 922         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 923
 924         /* *INDENT-OFF* */
 925         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 926                 .rx_thresh = {
 927                         .pthresh = 8,
 928                         .hthresh = 8,
 929                         .wthresh = 0,
 930                 },
 931                 .rx_free_thresh = 32,
 932                 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
 933         };
 934
 935         dev_info->default_txconf = (struct rte_eth_txconf) {
 936                 .tx_thresh = {
 937                         .pthresh = 32,
 938                         .hthresh = 0,
 939                         .wthresh = 0,
 940                 },
 941                 .tx_free_thresh = 32,
 942                 .tx_rs_thresh = 32,
 943         };
 944         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 945
 946         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 947         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 948         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 949         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 950         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 951
 952         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
 953                 dev_info->switch_info.name = eth_dev->device->name;
 954                 dev_info->switch_info.domain_id = bp->switch_domain_id;
 955                 dev_info->switch_info.port_id =
 956                                 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
 957                                     BNXT_SWITCH_PORT_ID_TRUSTED_VF;
 958         }
 959
 960         /* *INDENT-ON* */
 961
 962         /*
 963          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 964          *       need further investigation.
 965          */
 966
 967         /* VMDq resources */
 968         vpool = 64; /* ETH_64_POOLS */
 969         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 970         for (i = 0; i < 4; vpool >>= 1, i++) {
 971                 if (max_vnics > vpool) {
 972                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 973                                 if (dev_info->max_rx_queues > vrxq) {
 974                                         if (vpool > vrxq)
 975                                                 vpool = vrxq;
 976                                         goto found;
 977                                 }
 978                         }
 979                         /* Not enough resources to support VMDq */
 980                         break;
 981                 }
 982         }
 983         /* Not enough resources to support VMDq */
 984         vpool = 0;
 985         vrxq = 0;
 986 found:
 987         dev_info->max_vmdq_pools = vpool;
 988         dev_info->vmdq_queue_num = vrxq;
 989
 990         dev_info->vmdq_pool_base = 0;
 991         dev_info->vmdq_queue_base = 0;
 992
 993         return 0;
 994 }
 995
 996 /* Configure the device based on the configuration provided */
 997 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 998 {
 999         struct bnxt *bp = eth_dev->data->dev_private;
1000         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1001         int rc;
1002
1003         bp->rx_queues = (void *)eth_dev->data->rx_queues;
1004         bp->tx_queues = (void *)eth_dev->data->tx_queues;
1005         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1006         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1007
1008         rc = is_bnxt_in_error(bp);
1009         if (rc)
1010                 return rc;
1011
1012         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1013                 rc = bnxt_hwrm_check_vf_rings(bp);
1014                 if (rc) {
1015                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1016                         return -ENOSPC;
1017                 }
1018
1019                 /* If a resource has already been allocated - in this case
1020                  * it is the async completion ring, free it. Reallocate it after
1021                  * resource reservation. This will ensure the resource counts
1022                  * are calculated correctly.
1023                  */
1024
1025                 pthread_mutex_lock(&bp->def_cp_lock);
1026
1027                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1028                         bnxt_disable_int(bp);
1029                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
1030                 }
1031
1032                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1033                 if (rc) {
1034                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1035                         pthread_mutex_unlock(&bp->def_cp_lock);
1036                         return -ENOSPC;
1037                 }
1038
1039                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1040                         rc = bnxt_alloc_async_cp_ring(bp);
1041                         if (rc) {
1042                                 pthread_mutex_unlock(&bp->def_cp_lock);
1043                                 return rc;
1044                         }
1045                         bnxt_enable_int(bp);
1046                 }
1047
1048                 pthread_mutex_unlock(&bp->def_cp_lock);
1049         } else {
1050                 /* legacy driver needs to get updated values */
1051                 rc = bnxt_hwrm_func_qcaps(bp);
1052                 if (rc) {
1053                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
1054                         return rc;
1055                 }
1056         }
1057
1058         /* Inherit new configurations */
1059         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1060             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1061             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1062                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1063             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1064             bp->max_stat_ctx)
1065                 goto resource_error;
1066
1067         if (BNXT_HAS_RING_GRPS(bp) &&
1068             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1069                 goto resource_error;
1070
1071         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1072             bp->max_vnics < eth_dev->data->nb_rx_queues)
1073                 goto resource_error;
1074
1075         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1076         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1077
1078         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1079                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1080         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1081
1082         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1083                 eth_dev->data->mtu =
1084                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1085                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1086                         BNXT_NUM_VLANS;
1087                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1088         }
1089         return 0;
1090
1091 resource_error:
1092         PMD_DRV_LOG(ERR,
1093                     "Insufficient resources to support requested config\n");
1094         PMD_DRV_LOG(ERR,
1095                     "Num Queues Requested: Tx %d, Rx %d\n",
1096                     eth_dev->data->nb_tx_queues,
1097                     eth_dev->data->nb_rx_queues);
1098         PMD_DRV_LOG(ERR,
1099                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1100                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1101                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1102         return -ENOSPC;
1103 }
1104
1105 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1106 {
1107         struct rte_eth_link *link = &eth_dev->data->dev_link;
1108
1109         if (link->link_status)
1110                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1111                         eth_dev->data->port_id,
1112                         (uint32_t)link->link_speed,
1113                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1114                         ("full-duplex") : ("half-duplex\n"));
1115         else
1116                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1117                         eth_dev->data->port_id);
1118 }
1119
1120 /*
1121  * Determine whether the current configuration requires support for scattered
1122  * receive; return 1 if scattered receive is required and 0 if not.
1123  */
1124 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1125 {
1126         uint16_t buf_size;
1127         int i;
1128
1129         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1130                 return 1;
1131
1132         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1133                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1134
1135                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1136                                       RTE_PKTMBUF_HEADROOM);
1137                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1138                         return 1;
1139         }
1140         return 0;
1141 }
1142
1143 static eth_rx_burst_t
1144 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1145 {
1146         struct bnxt *bp = eth_dev->data->dev_private;
1147
1148 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1149 #ifndef RTE_LIBRTE_IEEE1588
1150         /*
1151          * Vector mode receive can be enabled only if scatter rx is not
1152          * in use and rx offloads are limited to VLAN stripping and
1153          * CRC stripping.
1154          */
1155         if (!eth_dev->data->scattered_rx &&
1156             !(eth_dev->data->dev_conf.rxmode.offloads &
1157               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1158                 DEV_RX_OFFLOAD_KEEP_CRC |
1159                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1160                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1161                 DEV_RX_OFFLOAD_UDP_CKSUM |
1162                 DEV_RX_OFFLOAD_TCP_CKSUM |
1163                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1164                 DEV_RX_OFFLOAD_RSS_HASH |
1165                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1166             !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp)) {
1167                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1168                             eth_dev->data->port_id);
1169                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1170                 return bnxt_recv_pkts_vec;
1171         }
1172         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1173                     eth_dev->data->port_id);
1174         PMD_DRV_LOG(INFO,
1175                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1176                     eth_dev->data->port_id,
1177                     eth_dev->data->scattered_rx,
1178                     eth_dev->data->dev_conf.rxmode.offloads);
1179 #endif
1180 #endif
1181         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1182         return bnxt_recv_pkts;
1183 }
1184
1185 static eth_tx_burst_t
1186 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1187 {
1188 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1189 #ifndef RTE_LIBRTE_IEEE1588
1190         struct bnxt *bp = eth_dev->data->dev_private;
1191
1192         /*
1193          * Vector mode transmit can be enabled only if not using scatter rx
1194          * or tx offloads.
1195          */
1196         if (!eth_dev->data->scattered_rx &&
1197             !eth_dev->data->dev_conf.txmode.offloads &&
1198             !BNXT_TRUFLOW_EN(bp)) {
1199                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1200                             eth_dev->data->port_id);
1201                 return bnxt_xmit_pkts_vec;
1202         }
1203         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1204                     eth_dev->data->port_id);
1205         PMD_DRV_LOG(INFO,
1206                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1207                     eth_dev->data->port_id,
1208                     eth_dev->data->scattered_rx,
1209                     eth_dev->data->dev_conf.txmode.offloads);
1210 #endif
1211 #endif
1212         return bnxt_xmit_pkts;
1213 }
1214
1215 static int bnxt_handle_if_change_status(struct bnxt *bp)
1216 {
1217         int rc;
1218
1219         /* Since fw has undergone a reset and lost all contexts,
1220          * set fatal flag to not issue hwrm during cleanup
1221          */
1222         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1223         bnxt_uninit_resources(bp, true);
1224
1225         /* clear fatal flag so that re-init happens */
1226         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1227         rc = bnxt_init_resources(bp, true);
1228
1229         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1230
1231         return rc;
1232 }
1233
1234 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1235 {
1236         struct bnxt *bp = eth_dev->data->dev_private;
1237         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1238         int vlan_mask = 0;
1239         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1240
1241         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1242                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1243                 return -EINVAL;
1244         }
1245
1246         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1247                 PMD_DRV_LOG(ERR,
1248                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1249                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1250         }
1251
1252         do {
1253                 rc = bnxt_hwrm_if_change(bp, true);
1254                 if (rc == 0 || rc != -EAGAIN)
1255                         break;
1256
1257                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1258         } while (retry_cnt--);
1259
1260         if (rc)
1261                 return rc;
1262
1263         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1264                 rc = bnxt_handle_if_change_status(bp);
1265                 if (rc)
1266                         return rc;
1267         }
1268
1269         bnxt_enable_int(bp);
1270
1271         rc = bnxt_init_chip(bp);
1272         if (rc)
1273                 goto error;
1274
1275         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1276         eth_dev->data->dev_started = 1;
1277
1278         bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1279
1280         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1281                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1282         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1283                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1284         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1285         if (rc)
1286                 goto error;
1287
1288         /* Initialize bnxt ULP port details */
1289         rc = bnxt_ulp_port_init(bp);
1290         if (rc)
1291                 goto error;
1292
1293         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1294         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1295
1296         bnxt_schedule_fw_health_check(bp);
1297
1298         return 0;
1299
1300 error:
1301         bnxt_shutdown_nic(bp);
1302         bnxt_free_tx_mbufs(bp);
1303         bnxt_free_rx_mbufs(bp);
1304         bnxt_hwrm_if_change(bp, false);
1305         eth_dev->data->dev_started = 0;
1306         return rc;
1307 }
1308
1309 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1310 {
1311         struct bnxt *bp = eth_dev->data->dev_private;
1312         int rc = 0;
1313
1314         if (!bp->link_info->link_up)
1315                 rc = bnxt_set_hwrm_link_config(bp, true);
1316         if (!rc)
1317                 eth_dev->data->dev_link.link_status = 1;
1318
1319         bnxt_print_link_info(eth_dev);
1320         return rc;
1321 }
1322
1323 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1324 {
1325         struct bnxt *bp = eth_dev->data->dev_private;
1326
1327         eth_dev->data->dev_link.link_status = 0;
1328         bnxt_set_hwrm_link_config(bp, false);
1329         bp->link_info->link_up = 0;
1330
1331         return 0;
1332 }
1333
1334 static void bnxt_free_switch_domain(struct bnxt *bp)
1335 {
1336         if (bp->switch_domain_id)
1337                 rte_eth_switch_domain_free(bp->switch_domain_id);
1338 }
1339
1340 /* Unload the driver, release resources */
1341 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1342 {
1343         struct bnxt *bp = eth_dev->data->dev_private;
1344         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1345         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1346
1347         eth_dev->data->dev_started = 0;
1348         eth_dev->data->scattered_rx = 0;
1349
1350         /* Prevent crashes when queues are still in use */
1351         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1352         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1353
1354         bnxt_disable_int(bp);
1355
1356         /* disable uio/vfio intr/eventfd mapping */
1357         rte_intr_disable(intr_handle);
1358
1359         /* Stop the child representors for this device */
1360         bnxt_rep_stop_all(bp);
1361
1362         /* delete the bnxt ULP port details */
1363         bnxt_ulp_port_deinit(bp);
1364
1365         bnxt_cancel_fw_health_check(bp);
1366
1367         /* Do not bring link down during reset recovery */
1368         if (!is_bnxt_in_error(bp))
1369                 bnxt_dev_set_link_down_op(eth_dev);
1370
1371         /* Wait for link to be reset and the async notification to process.
1372          * During reset recovery, there is no need to wait and
1373          * VF/NPAR functions do not have privilege to change PHY config.
1374          */
1375         if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1376                 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1377
1378         /* Clean queue intr-vector mapping */
1379         rte_intr_efd_disable(intr_handle);
1380         if (intr_handle->intr_vec != NULL) {
1381                 rte_free(intr_handle->intr_vec);
1382                 intr_handle->intr_vec = NULL;
1383         }
1384
1385         bnxt_hwrm_port_clr_stats(bp);
1386         bnxt_free_tx_mbufs(bp);
1387         bnxt_free_rx_mbufs(bp);
1388         /* Process any remaining notifications in default completion queue */
1389         bnxt_int_handler(eth_dev);
1390         bnxt_shutdown_nic(bp);
1391         bnxt_hwrm_if_change(bp, false);
1392
1393         rte_free(bp->mark_table);
1394         bp->mark_table = NULL;
1395
1396         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1397         bp->rx_cosq_cnt = 0;
1398         /* All filters are deleted on a port stop. */
1399         if (BNXT_FLOW_XSTATS_EN(bp))
1400                 bp->flow_stat->flow_count = 0;
1401 }
1402
1403 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1404 {
1405         struct bnxt *bp = eth_dev->data->dev_private;
1406
1407         /* cancel the recovery handler before remove dev */
1408         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1409         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1410         bnxt_cancel_fc_thread(bp);
1411
1412         if (eth_dev->data->dev_started)
1413                 bnxt_dev_stop_op(eth_dev);
1414
1415         bnxt_free_switch_domain(bp);
1416
1417         bnxt_uninit_resources(bp, false);
1418
1419         bnxt_free_leds_info(bp);
1420         bnxt_free_cos_queues(bp);
1421         bnxt_free_link_info(bp);
1422         bnxt_free_pf_info(bp);
1423         bnxt_free_parent_info(bp);
1424
1425         eth_dev->dev_ops = NULL;
1426         eth_dev->rx_pkt_burst = NULL;
1427         eth_dev->tx_pkt_burst = NULL;
1428
1429         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1430         bp->tx_mem_zone = NULL;
1431         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1432         bp->rx_mem_zone = NULL;
1433
1434         bnxt_hwrm_free_vf_info(bp);
1435
1436         rte_free(bp->grp_info);
1437         bp->grp_info = NULL;
1438 }
1439
1440 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1441                                     uint32_t index)
1442 {
1443         struct bnxt *bp = eth_dev->data->dev_private;
1444         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1445         struct bnxt_vnic_info *vnic;
1446         struct bnxt_filter_info *filter, *temp_filter;
1447         uint32_t i;
1448
1449         if (is_bnxt_in_error(bp))
1450                 return;
1451
1452         /*
1453          * Loop through all VNICs from the specified filter flow pools to
1454          * remove the corresponding MAC addr filter
1455          */
1456         for (i = 0; i < bp->nr_vnics; i++) {
1457                 if (!(pool_mask & (1ULL << i)))
1458                         continue;
1459
1460                 vnic = &bp->vnic_info[i];
1461                 filter = STAILQ_FIRST(&vnic->filter);
1462                 while (filter) {
1463                         temp_filter = STAILQ_NEXT(filter, next);
1464                         if (filter->mac_index == index) {
1465                                 STAILQ_REMOVE(&vnic->filter, filter,
1466                                                 bnxt_filter_info, next);
1467                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1468                                 bnxt_free_filter(bp, filter);
1469                         }
1470                         filter = temp_filter;
1471                 }
1472         }
1473 }
1474
1475 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1476                                struct rte_ether_addr *mac_addr, uint32_t index,
1477                                uint32_t pool)
1478 {
1479         struct bnxt_filter_info *filter;
1480         int rc = 0;
1481
1482         /* Attach requested MAC address to the new l2_filter */
1483         STAILQ_FOREACH(filter, &vnic->filter, next) {
1484                 if (filter->mac_index == index) {
1485                         PMD_DRV_LOG(DEBUG,
1486                                     "MAC addr already existed for pool %d\n",
1487                                     pool);
1488                         return 0;
1489                 }
1490         }
1491
1492         filter = bnxt_alloc_filter(bp);
1493         if (!filter) {
1494                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1495                 return -ENODEV;
1496         }
1497
1498         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1499          * if the MAC that's been programmed now is a different one, then,
1500          * copy that addr to filter->l2_addr
1501          */
1502         if (mac_addr)
1503                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1504         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1505
1506         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1507         if (!rc) {
1508                 filter->mac_index = index;
1509                 if (filter->mac_index == 0)
1510                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1511                 else
1512                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1513         } else {
1514                 bnxt_free_filter(bp, filter);
1515         }
1516
1517         return rc;
1518 }
1519
1520 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1521                                 struct rte_ether_addr *mac_addr,
1522                                 uint32_t index, uint32_t pool)
1523 {
1524         struct bnxt *bp = eth_dev->data->dev_private;
1525         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1526         int rc = 0;
1527
1528         rc = is_bnxt_in_error(bp);
1529         if (rc)
1530                 return rc;
1531
1532         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1533                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1534                 return -ENOTSUP;
1535         }
1536
1537         if (!vnic) {
1538                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1539                 return -EINVAL;
1540         }
1541
1542         /* Filter settings will get applied when port is started */
1543         if (!eth_dev->data->dev_started)
1544                 return 0;
1545
1546         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1547
1548         return rc;
1549 }
1550
1551 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1552                      bool exp_link_status)
1553 {
1554         int rc = 0;
1555         struct bnxt *bp = eth_dev->data->dev_private;
1556         struct rte_eth_link new;
1557         int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1558                   BNXT_LINK_DOWN_WAIT_CNT;
1559
1560         rc = is_bnxt_in_error(bp);
1561         if (rc)
1562                 return rc;
1563
1564         memset(&new, 0, sizeof(new));
1565         do {
1566                 /* Retrieve link info from hardware */
1567                 rc = bnxt_get_hwrm_link_config(bp, &new);
1568                 if (rc) {
1569                         new.link_speed = ETH_LINK_SPEED_100M;
1570                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1571                         PMD_DRV_LOG(ERR,
1572                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1573                         goto out;
1574                 }
1575
1576                 if (!wait_to_complete || new.link_status == exp_link_status)
1577                         break;
1578
1579                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1580         } while (cnt--);
1581
1582 out:
1583         /* Timed out or success */
1584         if (new.link_status != eth_dev->data->dev_link.link_status ||
1585         new.link_speed != eth_dev->data->dev_link.link_speed) {
1586                 rte_eth_linkstatus_set(eth_dev, &new);
1587
1588                 rte_eth_dev_callback_process(eth_dev,
1589                                              RTE_ETH_EVENT_INTR_LSC,
1590                                              NULL);
1591
1592                 bnxt_print_link_info(eth_dev);
1593         }
1594
1595         return rc;
1596 }
1597
1598 int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1599                         int wait_to_complete)
1600 {
1601         return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1602 }
1603
1604 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1605 {
1606         struct bnxt *bp = eth_dev->data->dev_private;
1607         struct bnxt_vnic_info *vnic;
1608         uint32_t old_flags;
1609         int rc;
1610
1611         rc = is_bnxt_in_error(bp);
1612         if (rc)
1613                 return rc;
1614
1615         /* Filter settings will get applied when port is started */
1616         if (!eth_dev->data->dev_started)
1617                 return 0;
1618
1619         if (bp->vnic_info == NULL)
1620                 return 0;
1621
1622         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1623
1624         old_flags = vnic->flags;
1625         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1626         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1627         if (rc != 0)
1628                 vnic->flags = old_flags;
1629
1630         return rc;
1631 }
1632
1633 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1634 {
1635         struct bnxt *bp = eth_dev->data->dev_private;
1636         struct bnxt_vnic_info *vnic;
1637         uint32_t old_flags;
1638         int rc;
1639
1640         rc = is_bnxt_in_error(bp);
1641         if (rc)
1642                 return rc;
1643
1644         /* Filter settings will get applied when port is started */
1645         if (!eth_dev->data->dev_started)
1646                 return 0;
1647
1648         if (bp->vnic_info == NULL)
1649                 return 0;
1650
1651         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1652
1653         old_flags = vnic->flags;
1654         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1655         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1656         if (rc != 0)
1657                 vnic->flags = old_flags;
1658
1659         return rc;
1660 }
1661
1662 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1663 {
1664         struct bnxt *bp = eth_dev->data->dev_private;
1665         struct bnxt_vnic_info *vnic;
1666         uint32_t old_flags;
1667         int rc;
1668
1669         rc = is_bnxt_in_error(bp);
1670         if (rc)
1671                 return rc;
1672
1673         /* Filter settings will get applied when port is started */
1674         if (!eth_dev->data->dev_started)
1675                 return 0;
1676
1677         if (bp->vnic_info == NULL)
1678                 return 0;
1679
1680         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1681
1682         old_flags = vnic->flags;
1683         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1684         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1685         if (rc != 0)
1686                 vnic->flags = old_flags;
1687
1688         return rc;
1689 }
1690
1691 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1692 {
1693         struct bnxt *bp = eth_dev->data->dev_private;
1694         struct bnxt_vnic_info *vnic;
1695         uint32_t old_flags;
1696         int rc;
1697
1698         rc = is_bnxt_in_error(bp);
1699         if (rc)
1700                 return rc;
1701
1702         /* Filter settings will get applied when port is started */
1703         if (!eth_dev->data->dev_started)
1704                 return 0;
1705
1706         if (bp->vnic_info == NULL)
1707                 return 0;
1708
1709         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1710
1711         old_flags = vnic->flags;
1712         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1713         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1714         if (rc != 0)
1715                 vnic->flags = old_flags;
1716
1717         return rc;
1718 }
1719
1720 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1721 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1722 {
1723         if (qid >= bp->rx_nr_rings)
1724                 return NULL;
1725
1726         return bp->eth_dev->data->rx_queues[qid];
1727 }
1728
1729 /* Return rxq corresponding to a given rss table ring/group ID. */
1730 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1731 {
1732         struct bnxt_rx_queue *rxq;
1733         unsigned int i;
1734
1735         if (!BNXT_HAS_RING_GRPS(bp)) {
1736                 for (i = 0; i < bp->rx_nr_rings; i++) {
1737                         rxq = bp->eth_dev->data->rx_queues[i];
1738                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1739                                 return rxq->index;
1740                 }
1741         } else {
1742                 for (i = 0; i < bp->rx_nr_rings; i++) {
1743                         if (bp->grp_info[i].fw_grp_id == fwr)
1744                                 return i;
1745                 }
1746         }
1747
1748         return INVALID_HW_RING_ID;
1749 }
1750
1751 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1752                             struct rte_eth_rss_reta_entry64 *reta_conf,
1753                             uint16_t reta_size)
1754 {
1755         struct bnxt *bp = eth_dev->data->dev_private;
1756         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1757         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1758         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1759         uint16_t idx, sft;
1760         int i, rc;
1761
1762         rc = is_bnxt_in_error(bp);
1763         if (rc)
1764                 return rc;
1765
1766         if (!vnic->rss_table)
1767                 return -EINVAL;
1768
1769         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1770                 return -EINVAL;
1771
1772         if (reta_size != tbl_size) {
1773                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1774                         "(%d) must equal the size supported by the hardware "
1775                         "(%d)\n", reta_size, tbl_size);
1776                 return -EINVAL;
1777         }
1778
1779         for (i = 0; i < reta_size; i++) {
1780                 struct bnxt_rx_queue *rxq;
1781
1782                 idx = i / RTE_RETA_GROUP_SIZE;
1783                 sft = i % RTE_RETA_GROUP_SIZE;
1784
1785                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1786                         continue;
1787
1788                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1789                 if (!rxq) {
1790                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1791                         return -EINVAL;
1792                 }
1793
1794                 if (BNXT_CHIP_THOR(bp)) {
1795                         vnic->rss_table[i * 2] =
1796                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1797                         vnic->rss_table[i * 2 + 1] =
1798                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1799                 } else {
1800                         vnic->rss_table[i] =
1801                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1802                 }
1803         }
1804
1805         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1806         return 0;
1807 }
1808
1809 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1810                               struct rte_eth_rss_reta_entry64 *reta_conf,
1811                               uint16_t reta_size)
1812 {
1813         struct bnxt *bp = eth_dev->data->dev_private;
1814         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1815         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1816         uint16_t idx, sft, i;
1817         int rc;
1818
1819         rc = is_bnxt_in_error(bp);
1820         if (rc)
1821                 return rc;
1822
1823         /* Retrieve from the default VNIC */
1824         if (!vnic)
1825                 return -EINVAL;
1826         if (!vnic->rss_table)
1827                 return -EINVAL;
1828
1829         if (reta_size != tbl_size) {
1830                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1831                         "(%d) must equal the size supported by the hardware "
1832                         "(%d)\n", reta_size, tbl_size);
1833                 return -EINVAL;
1834         }
1835
1836         for (idx = 0, i = 0; i < reta_size; i++) {
1837                 idx = i / RTE_RETA_GROUP_SIZE;
1838                 sft = i % RTE_RETA_GROUP_SIZE;
1839
1840                 if (reta_conf[idx].mask & (1ULL << sft)) {
1841                         uint16_t qid;
1842
1843                         if (BNXT_CHIP_THOR(bp))
1844                                 qid = bnxt_rss_to_qid(bp,
1845                                                       vnic->rss_table[i * 2]);
1846                         else
1847                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1848
1849                         if (qid == INVALID_HW_RING_ID) {
1850                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1851                                 return -EINVAL;
1852                         }
1853                         reta_conf[idx].reta[sft] = qid;
1854                 }
1855         }
1856
1857         return 0;
1858 }
1859
1860 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1861                                    struct rte_eth_rss_conf *rss_conf)
1862 {
1863         struct bnxt *bp = eth_dev->data->dev_private;
1864         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1865         struct bnxt_vnic_info *vnic;
1866         int rc;
1867
1868         rc = is_bnxt_in_error(bp);
1869         if (rc)
1870                 return rc;
1871
1872         /*
1873          * If RSS enablement were different than dev_configure,
1874          * then return -EINVAL
1875          */
1876         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1877                 if (!rss_conf->rss_hf)
1878                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1879         } else {
1880                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1881                         return -EINVAL;
1882         }
1883
1884         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1885         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
1886                rss_conf,
1887                sizeof(*rss_conf));
1888
1889         /* Update the default RSS VNIC(s) */
1890         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1891         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1892
1893         /*
1894          * If hashkey is not specified, use the previously configured
1895          * hashkey
1896          */
1897         if (!rss_conf->rss_key)
1898                 goto rss_config;
1899
1900         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1901                 PMD_DRV_LOG(ERR,
1902                             "Invalid hashkey length, should be 16 bytes\n");
1903                 return -EINVAL;
1904         }
1905         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1906
1907 rss_config:
1908         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1909         return 0;
1910 }
1911
1912 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1913                                      struct rte_eth_rss_conf *rss_conf)
1914 {
1915         struct bnxt *bp = eth_dev->data->dev_private;
1916         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1917         int len, rc;
1918         uint32_t hash_types;
1919
1920         rc = is_bnxt_in_error(bp);
1921         if (rc)
1922                 return rc;
1923
1924         /* RSS configuration is the same for all VNICs */
1925         if (vnic && vnic->rss_hash_key) {
1926                 if (rss_conf->rss_key) {
1927                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1928                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1929                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1930                 }
1931
1932                 hash_types = vnic->hash_type;
1933                 rss_conf->rss_hf = 0;
1934                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1935                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1936                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1937                 }
1938                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1939                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1940                         hash_types &=
1941                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1942                 }
1943                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1944                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1945                         hash_types &=
1946                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1947                 }
1948                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1949                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1950                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1951                 }
1952                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1953                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1954                         hash_types &=
1955                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1956                 }
1957                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1958                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1959                         hash_types &=
1960                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1961                 }
1962                 if (hash_types) {
1963                         PMD_DRV_LOG(ERR,
1964                                 "Unknown RSS config from firmware (%08x), RSS disabled",
1965                                 vnic->hash_type);
1966                         return -ENOTSUP;
1967                 }
1968         } else {
1969                 rss_conf->rss_hf = 0;
1970         }
1971         return 0;
1972 }
1973
1974 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1975                                struct rte_eth_fc_conf *fc_conf)
1976 {
1977         struct bnxt *bp = dev->data->dev_private;
1978         struct rte_eth_link link_info;
1979         int rc;
1980
1981         rc = is_bnxt_in_error(bp);
1982         if (rc)
1983                 return rc;
1984
1985         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1986         if (rc)
1987                 return rc;
1988
1989         memset(fc_conf, 0, sizeof(*fc_conf));
1990         if (bp->link_info->auto_pause)
1991                 fc_conf->autoneg = 1;
1992         switch (bp->link_info->pause) {
1993         case 0:
1994                 fc_conf->mode = RTE_FC_NONE;
1995                 break;
1996         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1997                 fc_conf->mode = RTE_FC_TX_PAUSE;
1998                 break;
1999         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2000                 fc_conf->mode = RTE_FC_RX_PAUSE;
2001                 break;
2002         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2003                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2004                 fc_conf->mode = RTE_FC_FULL;
2005                 break;
2006         }
2007         return 0;
2008 }
2009
2010 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2011                                struct rte_eth_fc_conf *fc_conf)
2012 {
2013         struct bnxt *bp = dev->data->dev_private;
2014         int rc;
2015
2016         rc = is_bnxt_in_error(bp);
2017         if (rc)
2018                 return rc;
2019
2020         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2021                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2022                 return -ENOTSUP;
2023         }
2024
2025         switch (fc_conf->mode) {
2026         case RTE_FC_NONE:
2027                 bp->link_info->auto_pause = 0;
2028                 bp->link_info->force_pause = 0;
2029                 break;
2030         case RTE_FC_RX_PAUSE:
2031                 if (fc_conf->autoneg) {
2032                         bp->link_info->auto_pause =
2033                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2034                         bp->link_info->force_pause = 0;
2035                 } else {
2036                         bp->link_info->auto_pause = 0;
2037                         bp->link_info->force_pause =
2038                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2039                 }
2040                 break;
2041         case RTE_FC_TX_PAUSE:
2042                 if (fc_conf->autoneg) {
2043                         bp->link_info->auto_pause =
2044                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2045                         bp->link_info->force_pause = 0;
2046                 } else {
2047                         bp->link_info->auto_pause = 0;
2048                         bp->link_info->force_pause =
2049                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2050                 }
2051                 break;
2052         case RTE_FC_FULL:
2053                 if (fc_conf->autoneg) {
2054                         bp->link_info->auto_pause =
2055                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2056                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2057                         bp->link_info->force_pause = 0;
2058                 } else {
2059                         bp->link_info->auto_pause = 0;
2060                         bp->link_info->force_pause =
2061                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2062                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2063                 }
2064                 break;
2065         }
2066         return bnxt_set_hwrm_link_config(bp, true);
2067 }
2068
2069 /* Add UDP tunneling port */
2070 static int
2071 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2072                          struct rte_eth_udp_tunnel *udp_tunnel)
2073 {
2074         struct bnxt *bp = eth_dev->data->dev_private;
2075         uint16_t tunnel_type = 0;
2076         int rc = 0;
2077
2078         rc = is_bnxt_in_error(bp);
2079         if (rc)
2080                 return rc;
2081
2082         switch (udp_tunnel->prot_type) {
2083         case RTE_TUNNEL_TYPE_VXLAN:
2084                 if (bp->vxlan_port_cnt) {
2085                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2086                                 udp_tunnel->udp_port);
2087                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2088                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2089                                 return -ENOSPC;
2090                         }
2091                         bp->vxlan_port_cnt++;
2092                         return 0;
2093                 }
2094                 tunnel_type =
2095                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2096                 bp->vxlan_port_cnt++;
2097                 break;
2098         case RTE_TUNNEL_TYPE_GENEVE:
2099                 if (bp->geneve_port_cnt) {
2100                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2101                                 udp_tunnel->udp_port);
2102                         if (bp->geneve_port != udp_tunnel->udp_port) {
2103                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2104                                 return -ENOSPC;
2105                         }
2106                         bp->geneve_port_cnt++;
2107                         return 0;
2108                 }
2109                 tunnel_type =
2110                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2111                 bp->geneve_port_cnt++;
2112                 break;
2113         default:
2114                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2115                 return -ENOTSUP;
2116         }
2117         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2118                                              tunnel_type);
2119         return rc;
2120 }
2121
2122 static int
2123 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2124                          struct rte_eth_udp_tunnel *udp_tunnel)
2125 {
2126         struct bnxt *bp = eth_dev->data->dev_private;
2127         uint16_t tunnel_type = 0;
2128         uint16_t port = 0;
2129         int rc = 0;
2130
2131         rc = is_bnxt_in_error(bp);
2132         if (rc)
2133                 return rc;
2134
2135         switch (udp_tunnel->prot_type) {
2136         case RTE_TUNNEL_TYPE_VXLAN:
2137                 if (!bp->vxlan_port_cnt) {
2138                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2139                         return -EINVAL;
2140                 }
2141                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2142                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2143                                 udp_tunnel->udp_port, bp->vxlan_port);
2144                         return -EINVAL;
2145                 }
2146                 if (--bp->vxlan_port_cnt)
2147                         return 0;
2148
2149                 tunnel_type =
2150                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2151                 port = bp->vxlan_fw_dst_port_id;
2152                 break;
2153         case RTE_TUNNEL_TYPE_GENEVE:
2154                 if (!bp->geneve_port_cnt) {
2155                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2156                         return -EINVAL;
2157                 }
2158                 if (bp->geneve_port != udp_tunnel->udp_port) {
2159                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2160                                 udp_tunnel->udp_port, bp->geneve_port);
2161                         return -EINVAL;
2162                 }
2163                 if (--bp->geneve_port_cnt)
2164                         return 0;
2165
2166                 tunnel_type =
2167                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2168                 port = bp->geneve_fw_dst_port_id;
2169                 break;
2170         default:
2171                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2172                 return -ENOTSUP;
2173         }
2174
2175         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2176         if (!rc) {
2177                 if (tunnel_type ==
2178                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
2179                         bp->vxlan_port = 0;
2180                 if (tunnel_type ==
2181                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
2182                         bp->geneve_port = 0;
2183         }
2184         return rc;
2185 }
2186
2187 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2188 {
2189         struct bnxt_filter_info *filter;
2190         struct bnxt_vnic_info *vnic;
2191         int rc = 0;
2192         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2193
2194         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2195         filter = STAILQ_FIRST(&vnic->filter);
2196         while (filter) {
2197                 /* Search for this matching MAC+VLAN filter */
2198                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2199                         /* Delete the filter */
2200                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2201                         if (rc)
2202                                 return rc;
2203                         STAILQ_REMOVE(&vnic->filter, filter,
2204                                       bnxt_filter_info, next);
2205                         bnxt_free_filter(bp, filter);
2206                         PMD_DRV_LOG(INFO,
2207                                     "Deleted vlan filter for %d\n",
2208                                     vlan_id);
2209                         return 0;
2210                 }
2211                 filter = STAILQ_NEXT(filter, next);
2212         }
2213         return -ENOENT;
2214 }
2215
2216 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2217 {
2218         struct bnxt_filter_info *filter;
2219         struct bnxt_vnic_info *vnic;
2220         int rc = 0;
2221         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2222                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2223         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2224
2225         /* Implementation notes on the use of VNIC in this command:
2226          *
2227          * By default, these filters belong to default vnic for the function.
2228          * Once these filters are set up, only destination VNIC can be modified.
2229          * If the destination VNIC is not specified in this command,
2230          * then the HWRM shall only create an l2 context id.
2231          */
2232
2233         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2234         filter = STAILQ_FIRST(&vnic->filter);
2235         /* Check if the VLAN has already been added */
2236         while (filter) {
2237                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2238                         return -EEXIST;
2239
2240                 filter = STAILQ_NEXT(filter, next);
2241         }
2242
2243         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2244          * command to create MAC+VLAN filter with the right flags, enables set.
2245          */
2246         filter = bnxt_alloc_filter(bp);
2247         if (!filter) {
2248                 PMD_DRV_LOG(ERR,
2249                             "MAC/VLAN filter alloc failed\n");
2250                 return -ENOMEM;
2251         }
2252         /* MAC + VLAN ID filter */
2253         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2254          * untagged packets are received
2255          *
2256          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2257          * packets and only the programmed vlan's packets are received
2258          */
2259         filter->l2_ivlan = vlan_id;
2260         filter->l2_ivlan_mask = 0x0FFF;
2261         filter->enables |= en;
2262         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2263
2264         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2265         if (rc) {
2266                 /* Free the newly allocated filter as we were
2267                  * not able to create the filter in hardware.
2268                  */
2269                 bnxt_free_filter(bp, filter);
2270                 return rc;
2271         }
2272
2273         filter->mac_index = 0;
2274         /* Add this new filter to the list */
2275         if (vlan_id == 0)
2276                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2277         else
2278                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2279
2280         PMD_DRV_LOG(INFO,
2281                     "Added Vlan filter for %d\n", vlan_id);
2282         return rc;
2283 }
2284
2285 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2286                 uint16_t vlan_id, int on)
2287 {
2288         struct bnxt *bp = eth_dev->data->dev_private;
2289         int rc;
2290
2291         rc = is_bnxt_in_error(bp);
2292         if (rc)
2293                 return rc;
2294
2295         if (!eth_dev->data->dev_started) {
2296                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2297                 return -EINVAL;
2298         }
2299
2300         /* These operations apply to ALL existing MAC/VLAN filters */
2301         if (on)
2302                 return bnxt_add_vlan_filter(bp, vlan_id);
2303         else
2304                 return bnxt_del_vlan_filter(bp, vlan_id);
2305 }
2306
2307 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2308                                     struct bnxt_vnic_info *vnic)
2309 {
2310         struct bnxt_filter_info *filter;
2311         int rc;
2312
2313         filter = STAILQ_FIRST(&vnic->filter);
2314         while (filter) {
2315                 if (filter->mac_index == 0 &&
2316                     !memcmp(filter->l2_addr, bp->mac_addr,
2317                             RTE_ETHER_ADDR_LEN)) {
2318                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2319                         if (!rc) {
2320                                 STAILQ_REMOVE(&vnic->filter, filter,
2321                                               bnxt_filter_info, next);
2322                                 bnxt_free_filter(bp, filter);
2323                         }
2324                         return rc;
2325                 }
2326                 filter = STAILQ_NEXT(filter, next);
2327         }
2328         return 0;
2329 }
2330
2331 static int
2332 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2333 {
2334         struct bnxt_vnic_info *vnic;
2335         unsigned int i;
2336         int rc;
2337
2338         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2339         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2340                 /* Remove any VLAN filters programmed */
2341                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2342                         bnxt_del_vlan_filter(bp, i);
2343
2344                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2345                 if (rc)
2346                         return rc;
2347         } else {
2348                 /* Default filter will allow packets that match the
2349                  * dest mac. So, it has to be deleted, otherwise, we
2350                  * will endup receiving vlan packets for which the
2351                  * filter is not programmed, when hw-vlan-filter
2352                  * configuration is ON
2353                  */
2354                 bnxt_del_dflt_mac_filter(bp, vnic);
2355                 /* This filter will allow only untagged packets */
2356                 bnxt_add_vlan_filter(bp, 0);
2357         }
2358         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2359                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2360
2361         return 0;
2362 }
2363
2364 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2365 {
2366         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2367         unsigned int i;
2368         int rc;
2369
2370         /* Destroy vnic filters and vnic */
2371         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2372             DEV_RX_OFFLOAD_VLAN_FILTER) {
2373                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2374                         bnxt_del_vlan_filter(bp, i);
2375         }
2376         bnxt_del_dflt_mac_filter(bp, vnic);
2377
2378         rc = bnxt_hwrm_vnic_free(bp, vnic);
2379         if (rc)
2380                 return rc;
2381
2382         rte_free(vnic->fw_grp_ids);
2383         vnic->fw_grp_ids = NULL;
2384
2385         vnic->rx_queue_cnt = 0;
2386
2387         return 0;
2388 }
2389
2390 static int
2391 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2392 {
2393         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2394         int rc;
2395
2396         /* Destroy, recreate and reconfigure the default vnic */
2397         rc = bnxt_free_one_vnic(bp, 0);
2398         if (rc)
2399                 return rc;
2400
2401         /* default vnic 0 */
2402         rc = bnxt_setup_one_vnic(bp, 0);
2403         if (rc)
2404                 return rc;
2405
2406         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2407             DEV_RX_OFFLOAD_VLAN_FILTER) {
2408                 rc = bnxt_add_vlan_filter(bp, 0);
2409                 if (rc)
2410                         return rc;
2411                 rc = bnxt_restore_vlan_filters(bp);
2412                 if (rc)
2413                         return rc;
2414         } else {
2415                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2416                 if (rc)
2417                         return rc;
2418         }
2419
2420         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2421         if (rc)
2422                 return rc;
2423
2424         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2425                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2426
2427         return rc;
2428 }
2429
2430 static int
2431 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2432 {
2433         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2434         struct bnxt *bp = dev->data->dev_private;
2435         int rc;
2436
2437         rc = is_bnxt_in_error(bp);
2438         if (rc)
2439                 return rc;
2440
2441         /* Filter settings will get applied when port is started */
2442         if (!dev->data->dev_started)
2443                 return 0;
2444
2445         if (mask & ETH_VLAN_FILTER_MASK) {
2446                 /* Enable or disable VLAN filtering */
2447                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2448                 if (rc)
2449                         return rc;
2450         }
2451
2452         if (mask & ETH_VLAN_STRIP_MASK) {
2453                 /* Enable or disable VLAN stripping */
2454                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2455                 if (rc)
2456                         return rc;
2457         }
2458
2459         if (mask & ETH_VLAN_EXTEND_MASK) {
2460                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2461                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2462                 else
2463                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2464         }
2465
2466         return 0;
2467 }
2468
2469 static int
2470 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2471                       uint16_t tpid)
2472 {
2473         struct bnxt *bp = dev->data->dev_private;
2474         int qinq = dev->data->dev_conf.rxmode.offloads &
2475                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2476
2477         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2478             vlan_type != ETH_VLAN_TYPE_OUTER) {
2479                 PMD_DRV_LOG(ERR,
2480                             "Unsupported vlan type.");
2481                 return -EINVAL;
2482         }
2483         if (!qinq) {
2484                 PMD_DRV_LOG(ERR,
2485                             "QinQ not enabled. Needs to be ON as we can "
2486                             "accelerate only outer vlan\n");
2487                 return -EINVAL;
2488         }
2489
2490         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2491                 switch (tpid) {
2492                 case RTE_ETHER_TYPE_QINQ:
2493                         bp->outer_tpid_bd =
2494                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2495                                 break;
2496                 case RTE_ETHER_TYPE_VLAN:
2497                         bp->outer_tpid_bd =
2498                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2499                                 break;
2500                 case RTE_ETHER_TYPE_QINQ1:
2501                         bp->outer_tpid_bd =
2502                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2503                                 break;
2504                 case RTE_ETHER_TYPE_QINQ2:
2505                         bp->outer_tpid_bd =
2506                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2507                                 break;
2508                 case RTE_ETHER_TYPE_QINQ3:
2509                         bp->outer_tpid_bd =
2510                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2511                                 break;
2512                 default:
2513                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2514                         return -EINVAL;
2515                 }
2516                 bp->outer_tpid_bd |= tpid;
2517                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2518         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2519                 PMD_DRV_LOG(ERR,
2520                             "Can accelerate only outer vlan in QinQ\n");
2521                 return -EINVAL;
2522         }
2523
2524         return 0;
2525 }
2526
2527 static int
2528 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2529                              struct rte_ether_addr *addr)
2530 {
2531         struct bnxt *bp = dev->data->dev_private;
2532         /* Default Filter is tied to VNIC 0 */
2533         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2534         int rc;
2535
2536         rc = is_bnxt_in_error(bp);
2537         if (rc)
2538                 return rc;
2539
2540         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2541                 return -EPERM;
2542
2543         if (rte_is_zero_ether_addr(addr))
2544                 return -EINVAL;
2545
2546         /* Filter settings will get applied when port is started */
2547         if (!dev->data->dev_started)
2548                 return 0;
2549
2550         /* Check if the requested MAC is already added */
2551         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2552                 return 0;
2553
2554         /* Destroy filter and re-create it */
2555         bnxt_del_dflt_mac_filter(bp, vnic);
2556
2557         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2558         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2559                 /* This filter will allow only untagged packets */
2560                 rc = bnxt_add_vlan_filter(bp, 0);
2561         } else {
2562                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2563         }
2564
2565         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2566         return rc;
2567 }
2568
2569 static int
2570 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2571                           struct rte_ether_addr *mc_addr_set,
2572                           uint32_t nb_mc_addr)
2573 {
2574         struct bnxt *bp = eth_dev->data->dev_private;
2575         char *mc_addr_list = (char *)mc_addr_set;
2576         struct bnxt_vnic_info *vnic;
2577         uint32_t off = 0, i = 0;
2578         int rc;
2579
2580         rc = is_bnxt_in_error(bp);
2581         if (rc)
2582                 return rc;
2583
2584         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2585
2586         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2587                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2588                 goto allmulti;
2589         }
2590
2591         /* TODO Check for Duplicate mcast addresses */
2592         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2593         for (i = 0; i < nb_mc_addr; i++) {
2594                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2595                         RTE_ETHER_ADDR_LEN);
2596                 off += RTE_ETHER_ADDR_LEN;
2597         }
2598
2599         vnic->mc_addr_cnt = i;
2600         if (vnic->mc_addr_cnt)
2601                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2602         else
2603                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2604
2605 allmulti:
2606         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2607 }
2608
2609 static int
2610 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2611 {
2612         struct bnxt *bp = dev->data->dev_private;
2613         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2614         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2615         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2616         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2617         int ret;
2618
2619         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2620                         fw_major, fw_minor, fw_updt, fw_rsvd);
2621
2622         ret += 1; /* add the size of '\0' */
2623         if (fw_size < (uint32_t)ret)
2624                 return ret;
2625         else
2626                 return 0;
2627 }
2628
2629 static void
2630 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2631         struct rte_eth_rxq_info *qinfo)
2632 {
2633         struct bnxt *bp = dev->data->dev_private;
2634         struct bnxt_rx_queue *rxq;
2635
2636         if (is_bnxt_in_error(bp))
2637                 return;
2638
2639         rxq = dev->data->rx_queues[queue_id];
2640
2641         qinfo->mp = rxq->mb_pool;
2642         qinfo->scattered_rx = dev->data->scattered_rx;
2643         qinfo->nb_desc = rxq->nb_rx_desc;
2644
2645         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2646         qinfo->conf.rx_drop_en = rxq->drop_en;
2647         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2648 }
2649
2650 static void
2651 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2652         struct rte_eth_txq_info *qinfo)
2653 {
2654         struct bnxt *bp = dev->data->dev_private;
2655         struct bnxt_tx_queue *txq;
2656
2657         if (is_bnxt_in_error(bp))
2658                 return;
2659
2660         txq = dev->data->tx_queues[queue_id];
2661
2662         qinfo->nb_desc = txq->nb_tx_desc;
2663
2664         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2665         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2666         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2667
2668         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2669         qinfo->conf.tx_rs_thresh = 0;
2670         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2671 }
2672
2673 static const struct {
2674         eth_rx_burst_t pkt_burst;
2675         const char *info;
2676 } bnxt_rx_burst_info[] = {
2677         {bnxt_recv_pkts,        "Scalar"},
2678 #if defined(RTE_ARCH_X86)
2679         {bnxt_recv_pkts_vec,    "Vector SSE"},
2680 #elif defined(RTE_ARCH_ARM64)
2681         {bnxt_recv_pkts_vec,    "Vector Neon"},
2682 #endif
2683 };
2684
2685 static int
2686 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2687                        struct rte_eth_burst_mode *mode)
2688 {
2689         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2690         size_t i;
2691
2692         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2693                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2694                         snprintf(mode->info, sizeof(mode->info), "%s",
2695                                  bnxt_rx_burst_info[i].info);
2696                         return 0;
2697                 }
2698         }
2699
2700         return -EINVAL;
2701 }
2702
2703 static const struct {
2704         eth_tx_burst_t pkt_burst;
2705         const char *info;
2706 } bnxt_tx_burst_info[] = {
2707         {bnxt_xmit_pkts,        "Scalar"},
2708 #if defined(RTE_ARCH_X86)
2709         {bnxt_xmit_pkts_vec,    "Vector SSE"},
2710 #elif defined(RTE_ARCH_ARM64)
2711         {bnxt_xmit_pkts_vec,    "Vector Neon"},
2712 #endif
2713 };
2714
2715 static int
2716 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2717                        struct rte_eth_burst_mode *mode)
2718 {
2719         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2720         size_t i;
2721
2722         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2723                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2724                         snprintf(mode->info, sizeof(mode->info), "%s",
2725                                  bnxt_tx_burst_info[i].info);
2726                         return 0;
2727                 }
2728         }
2729
2730         return -EINVAL;
2731 }
2732
2733 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2734 {
2735         struct bnxt *bp = eth_dev->data->dev_private;
2736         uint32_t new_pkt_size;
2737         uint32_t rc = 0;
2738         uint32_t i;
2739
2740         rc = is_bnxt_in_error(bp);
2741         if (rc)
2742                 return rc;
2743
2744         /* Exit if receive queues are not configured yet */
2745         if (!eth_dev->data->nb_rx_queues)
2746                 return rc;
2747
2748         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2749                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2750
2751         /*
2752          * Disallow any MTU change that would require scattered receive support
2753          * if it is not already enabled.
2754          */
2755         if (eth_dev->data->dev_started &&
2756             !eth_dev->data->scattered_rx &&
2757             (new_pkt_size >
2758              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2759                 PMD_DRV_LOG(ERR,
2760                             "MTU change would require scattered rx support. ");
2761                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2762                 return -EINVAL;
2763         }
2764
2765         if (new_mtu > RTE_ETHER_MTU) {
2766                 bp->flags |= BNXT_FLAG_JUMBO;
2767                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2768                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2769         } else {
2770                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2771                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2772                 bp->flags &= ~BNXT_FLAG_JUMBO;
2773         }
2774
2775         /* Is there a change in mtu setting? */
2776         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2777                 return rc;
2778
2779         for (i = 0; i < bp->nr_vnics; i++) {
2780                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2781                 uint16_t size = 0;
2782
2783                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2784                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2785                 if (rc)
2786                         break;
2787
2788                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2789                 size -= RTE_PKTMBUF_HEADROOM;
2790
2791                 if (size < new_mtu) {
2792                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2793                         if (rc)
2794                                 return rc;
2795                 }
2796         }
2797
2798         if (!rc)
2799                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2800
2801         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2802
2803         return rc;
2804 }
2805
2806 static int
2807 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2808 {
2809         struct bnxt *bp = dev->data->dev_private;
2810         uint16_t vlan = bp->vlan;
2811         int rc;
2812
2813         rc = is_bnxt_in_error(bp);
2814         if (rc)
2815                 return rc;
2816
2817         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2818                 PMD_DRV_LOG(ERR,
2819                         "PVID cannot be modified for this function\n");
2820                 return -ENOTSUP;
2821         }
2822         bp->vlan = on ? pvid : 0;
2823
2824         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2825         if (rc)
2826                 bp->vlan = vlan;
2827         return rc;
2828 }
2829
2830 static int
2831 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2832 {
2833         struct bnxt *bp = dev->data->dev_private;
2834         int rc;
2835
2836         rc = is_bnxt_in_error(bp);
2837         if (rc)
2838                 return rc;
2839
2840         return bnxt_hwrm_port_led_cfg(bp, true);
2841 }
2842
2843 static int
2844 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2845 {
2846         struct bnxt *bp = dev->data->dev_private;
2847         int rc;
2848
2849         rc = is_bnxt_in_error(bp);
2850         if (rc)
2851                 return rc;
2852
2853         return bnxt_hwrm_port_led_cfg(bp, false);
2854 }
2855
2856 static uint32_t
2857 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2858 {
2859         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2860         uint32_t desc = 0, raw_cons = 0, cons;
2861         struct bnxt_cp_ring_info *cpr;
2862         struct bnxt_rx_queue *rxq;
2863         struct rx_pkt_cmpl *rxcmp;
2864         int rc;
2865
2866         rc = is_bnxt_in_error(bp);
2867         if (rc)
2868                 return rc;
2869
2870         rxq = dev->data->rx_queues[rx_queue_id];
2871         cpr = rxq->cp_ring;
2872         raw_cons = cpr->cp_raw_cons;
2873
2874         while (1) {
2875                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2876                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2877                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2878
2879                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2880                         break;
2881                 } else {
2882                         raw_cons++;
2883                         desc++;
2884                 }
2885         }
2886
2887         return desc;
2888 }
2889
2890 static int
2891 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2892 {
2893         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2894         struct bnxt_rx_ring_info *rxr;
2895         struct bnxt_cp_ring_info *cpr;
2896         struct rte_mbuf *rx_buf;
2897         struct rx_pkt_cmpl *rxcmp;
2898         uint32_t cons, cp_cons;
2899         int rc;
2900
2901         if (!rxq)
2902                 return -EINVAL;
2903
2904         rc = is_bnxt_in_error(rxq->bp);
2905         if (rc)
2906                 return rc;
2907
2908         cpr = rxq->cp_ring;
2909         rxr = rxq->rx_ring;
2910
2911         if (offset >= rxq->nb_rx_desc)
2912                 return -EINVAL;
2913
2914         cons = RING_CMP(cpr->cp_ring_struct, offset);
2915         cp_cons = cpr->cp_raw_cons;
2916         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2917
2918         if (cons > cp_cons) {
2919                 if (CMPL_VALID(rxcmp, cpr->valid))
2920                         return RTE_ETH_RX_DESC_DONE;
2921         } else {
2922                 if (CMPL_VALID(rxcmp, !cpr->valid))
2923                         return RTE_ETH_RX_DESC_DONE;
2924         }
2925         rx_buf = rxr->rx_buf_ring[cons];
2926         if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf)
2927                 return RTE_ETH_RX_DESC_UNAVAIL;
2928
2929
2930         return RTE_ETH_RX_DESC_AVAIL;
2931 }
2932
2933 static int
2934 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2935 {
2936         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2937         struct bnxt_tx_ring_info *txr;
2938         struct bnxt_cp_ring_info *cpr;
2939         struct bnxt_sw_tx_bd *tx_buf;
2940         struct tx_pkt_cmpl *txcmp;
2941         uint32_t cons, cp_cons;
2942         int rc;
2943
2944         if (!txq)
2945                 return -EINVAL;
2946
2947         rc = is_bnxt_in_error(txq->bp);
2948         if (rc)
2949                 return rc;
2950
2951         cpr = txq->cp_ring;
2952         txr = txq->tx_ring;
2953
2954         if (offset >= txq->nb_tx_desc)
2955                 return -EINVAL;
2956
2957         cons = RING_CMP(cpr->cp_ring_struct, offset);
2958         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2959         cp_cons = cpr->cp_raw_cons;
2960
2961         if (cons > cp_cons) {
2962                 if (CMPL_VALID(txcmp, cpr->valid))
2963                         return RTE_ETH_TX_DESC_UNAVAIL;
2964         } else {
2965                 if (CMPL_VALID(txcmp, !cpr->valid))
2966                         return RTE_ETH_TX_DESC_UNAVAIL;
2967         }
2968         tx_buf = &txr->tx_buf_ring[cons];
2969         if (tx_buf->mbuf == NULL)
2970                 return RTE_ETH_TX_DESC_DONE;
2971
2972         return RTE_ETH_TX_DESC_FULL;
2973 }
2974
2975 static struct bnxt_filter_info *
2976 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2977                                 struct rte_eth_ethertype_filter *efilter,
2978                                 struct bnxt_vnic_info *vnic0,
2979                                 struct bnxt_vnic_info *vnic,
2980                                 int *ret)
2981 {
2982         struct bnxt_filter_info *mfilter = NULL;
2983         int match = 0;
2984         *ret = 0;
2985
2986         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2987                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2988                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2989                         " ethertype filter.", efilter->ether_type);
2990                 *ret = -EINVAL;
2991                 goto exit;
2992         }
2993         if (efilter->queue >= bp->rx_nr_rings) {
2994                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2995                 *ret = -EINVAL;
2996                 goto exit;
2997         }
2998
2999         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3000         vnic = &bp->vnic_info[efilter->queue];
3001         if (vnic == NULL) {
3002                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
3003                 *ret = -EINVAL;
3004                 goto exit;
3005         }
3006
3007         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3008                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
3009                         if ((!memcmp(efilter->mac_addr.addr_bytes,
3010                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
3011                              mfilter->flags ==
3012                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
3013                              mfilter->ethertype == efilter->ether_type)) {
3014                                 match = 1;
3015                                 break;
3016                         }
3017                 }
3018         } else {
3019                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
3020                         if ((!memcmp(efilter->mac_addr.addr_bytes,
3021                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
3022                              mfilter->ethertype == efilter->ether_type &&
3023                              mfilter->flags ==
3024                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
3025                                 match = 1;
3026                                 break;
3027                         }
3028         }
3029
3030         if (match)
3031                 *ret = -EEXIST;
3032
3033 exit:
3034         return mfilter;
3035 }
3036
3037 static int
3038 bnxt_ethertype_filter(struct rte_eth_dev *dev,
3039                         enum rte_filter_op filter_op,
3040                         void *arg)
3041 {
3042         struct bnxt *bp = dev->data->dev_private;
3043         struct rte_eth_ethertype_filter *efilter =
3044                         (struct rte_eth_ethertype_filter *)arg;
3045         struct bnxt_filter_info *bfilter, *filter1;
3046         struct bnxt_vnic_info *vnic, *vnic0;
3047         int ret;
3048
3049         if (filter_op == RTE_ETH_FILTER_NOP)
3050                 return 0;
3051
3052         if (arg == NULL) {
3053                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3054                             filter_op);
3055                 return -EINVAL;
3056         }
3057
3058         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3059         vnic = &bp->vnic_info[efilter->queue];
3060
3061         switch (filter_op) {
3062         case RTE_ETH_FILTER_ADD:
3063                 bnxt_match_and_validate_ether_filter(bp, efilter,
3064                                                         vnic0, vnic, &ret);
3065                 if (ret < 0)
3066                         return ret;
3067
3068                 bfilter = bnxt_get_unused_filter(bp);
3069                 if (bfilter == NULL) {
3070                         PMD_DRV_LOG(ERR,
3071                                 "Not enough resources for a new filter.\n");
3072                         return -ENOMEM;
3073                 }
3074                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3075                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
3076                        RTE_ETHER_ADDR_LEN);
3077                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
3078                        RTE_ETHER_ADDR_LEN);
3079                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3080                 bfilter->ethertype = efilter->ether_type;
3081                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3082
3083                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
3084                 if (filter1 == NULL) {
3085                         ret = -EINVAL;
3086                         goto cleanup;
3087                 }
3088                 bfilter->enables |=
3089                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3090                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3091
3092                 bfilter->dst_id = vnic->fw_vnic_id;
3093
3094                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3095                         bfilter->flags =
3096                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3097                 }
3098
3099                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3100                 if (ret)
3101                         goto cleanup;
3102                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3103                 break;
3104         case RTE_ETH_FILTER_DELETE:
3105                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
3106                                                         vnic0, vnic, &ret);
3107                 if (ret == -EEXIST) {
3108                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
3109
3110                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
3111                                       next);
3112                         bnxt_free_filter(bp, filter1);
3113                 } else if (ret == 0) {
3114                         PMD_DRV_LOG(ERR, "No matching filter found\n");
3115                 }
3116                 break;
3117         default:
3118                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3119                 ret = -EINVAL;
3120                 goto error;
3121         }
3122         return ret;
3123 cleanup:
3124         bnxt_free_filter(bp, bfilter);
3125 error:
3126         return ret;
3127 }
3128
3129 static inline int
3130 parse_ntuple_filter(struct bnxt *bp,
3131                     struct rte_eth_ntuple_filter *nfilter,
3132                     struct bnxt_filter_info *bfilter)
3133 {
3134         uint32_t en = 0;
3135
3136         if (nfilter->queue >= bp->rx_nr_rings) {
3137                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
3138                 return -EINVAL;
3139         }
3140
3141         switch (nfilter->dst_port_mask) {
3142         case UINT16_MAX:
3143                 bfilter->dst_port_mask = -1;
3144                 bfilter->dst_port = nfilter->dst_port;
3145                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
3146                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3147                 break;
3148         default:
3149                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3150                 return -EINVAL;
3151         }
3152
3153         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3154         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3155
3156         switch (nfilter->proto_mask) {
3157         case UINT8_MAX:
3158                 if (nfilter->proto == 17) /* IPPROTO_UDP */
3159                         bfilter->ip_protocol = 17;
3160                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
3161                         bfilter->ip_protocol = 6;
3162                 else
3163                         return -EINVAL;
3164                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3165                 break;
3166         default:
3167                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3168                 return -EINVAL;
3169         }
3170
3171         switch (nfilter->dst_ip_mask) {
3172         case UINT32_MAX:
3173                 bfilter->dst_ipaddr_mask[0] = -1;
3174                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
3175                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
3176                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3177                 break;
3178         default:
3179                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3180                 return -EINVAL;
3181         }
3182
3183         switch (nfilter->src_ip_mask) {
3184         case UINT32_MAX:
3185                 bfilter->src_ipaddr_mask[0] = -1;
3186                 bfilter->src_ipaddr[0] = nfilter->src_ip;
3187                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
3188                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3189                 break;
3190         default:
3191                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3192                 return -EINVAL;
3193         }
3194
3195         switch (nfilter->src_port_mask) {
3196         case UINT16_MAX:
3197                 bfilter->src_port_mask = -1;
3198                 bfilter->src_port = nfilter->src_port;
3199                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
3200                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3201                 break;
3202         default:
3203                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3204                 return -EINVAL;
3205         }
3206
3207         bfilter->enables = en;
3208         return 0;
3209 }
3210
3211 static struct bnxt_filter_info*
3212 bnxt_match_ntuple_filter(struct bnxt *bp,
3213                          struct bnxt_filter_info *bfilter,
3214                          struct bnxt_vnic_info **mvnic)
3215 {
3216         struct bnxt_filter_info *mfilter = NULL;
3217         int i;
3218
3219         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3220                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3221                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
3222                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
3223                             bfilter->src_ipaddr_mask[0] ==
3224                             mfilter->src_ipaddr_mask[0] &&
3225                             bfilter->src_port == mfilter->src_port &&
3226                             bfilter->src_port_mask == mfilter->src_port_mask &&
3227                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
3228                             bfilter->dst_ipaddr_mask[0] ==
3229                             mfilter->dst_ipaddr_mask[0] &&
3230                             bfilter->dst_port == mfilter->dst_port &&
3231                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
3232                             bfilter->flags == mfilter->flags &&
3233                             bfilter->enables == mfilter->enables) {
3234                                 if (mvnic)
3235                                         *mvnic = vnic;
3236                                 return mfilter;
3237                         }
3238                 }
3239         }
3240         return NULL;
3241 }
3242
3243 static int
3244 bnxt_cfg_ntuple_filter(struct bnxt *bp,
3245                        struct rte_eth_ntuple_filter *nfilter,
3246                        enum rte_filter_op filter_op)
3247 {
3248         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
3249         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
3250         int ret;
3251
3252         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
3253                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3254                 return -EINVAL;
3255         }
3256
3257         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
3258                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
3259                 return -EINVAL;
3260         }
3261
3262         bfilter = bnxt_get_unused_filter(bp);
3263         if (bfilter == NULL) {
3264                 PMD_DRV_LOG(ERR,
3265                         "Not enough resources for a new filter.\n");
3266                 return -ENOMEM;
3267         }
3268         ret = parse_ntuple_filter(bp, nfilter, bfilter);
3269         if (ret < 0)
3270                 goto free_filter;
3271
3272         vnic = &bp->vnic_info[nfilter->queue];
3273         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3274         filter1 = STAILQ_FIRST(&vnic0->filter);
3275         if (filter1 == NULL) {
3276                 ret = -EINVAL;
3277                 goto free_filter;
3278         }
3279
3280         bfilter->dst_id = vnic->fw_vnic_id;
3281         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3282         bfilter->enables |=
3283                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3284         bfilter->ethertype = 0x800;
3285         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3286
3287         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3288
3289         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3290             bfilter->dst_id == mfilter->dst_id) {
3291                 PMD_DRV_LOG(ERR, "filter exists.\n");
3292                 ret = -EEXIST;
3293                 goto free_filter;
3294         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3295                    bfilter->dst_id != mfilter->dst_id) {
3296                 mfilter->dst_id = vnic->fw_vnic_id;
3297                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3298                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3299                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3300                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3301                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3302                 goto free_filter;
3303         }
3304         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3305                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3306                 ret = -ENOENT;
3307                 goto free_filter;
3308         }
3309
3310         if (filter_op == RTE_ETH_FILTER_ADD) {
3311                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3312                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3313                 if (ret)
3314                         goto free_filter;
3315                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3316         } else {
3317                 if (mfilter == NULL) {
3318                         /* This should not happen. But for Coverity! */
3319                         ret = -ENOENT;
3320                         goto free_filter;
3321                 }
3322                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3323
3324                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3325                 bnxt_free_filter(bp, mfilter);
3326                 bnxt_free_filter(bp, bfilter);
3327         }
3328
3329         return 0;
3330 free_filter:
3331         bnxt_free_filter(bp, bfilter);
3332         return ret;
3333 }
3334
3335 static int
3336 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3337                         enum rte_filter_op filter_op,
3338                         void *arg)
3339 {
3340         struct bnxt *bp = dev->data->dev_private;
3341         int ret;
3342
3343         if (filter_op == RTE_ETH_FILTER_NOP)
3344                 return 0;
3345
3346         if (arg == NULL) {
3347                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3348                             filter_op);
3349                 return -EINVAL;
3350         }
3351
3352         switch (filter_op) {
3353         case RTE_ETH_FILTER_ADD:
3354                 ret = bnxt_cfg_ntuple_filter(bp,
3355                         (struct rte_eth_ntuple_filter *)arg,
3356                         filter_op);
3357                 break;
3358         case RTE_ETH_FILTER_DELETE:
3359                 ret = bnxt_cfg_ntuple_filter(bp,
3360                         (struct rte_eth_ntuple_filter *)arg,
3361                         filter_op);
3362                 break;
3363         default:
3364                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3365                 ret = -EINVAL;
3366                 break;
3367         }
3368         return ret;
3369 }
3370
3371 static int
3372 bnxt_parse_fdir_filter(struct bnxt *bp,
3373                        struct rte_eth_fdir_filter *fdir,
3374                        struct bnxt_filter_info *filter)
3375 {
3376         enum rte_fdir_mode fdir_mode =
3377                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3378         struct bnxt_vnic_info *vnic0, *vnic;
3379         struct bnxt_filter_info *filter1;
3380         uint32_t en = 0;
3381         int i;
3382
3383         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3384                 return -EINVAL;
3385
3386         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3387         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3388
3389         switch (fdir->input.flow_type) {
3390         case RTE_ETH_FLOW_IPV4:
3391         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3392                 /* FALLTHROUGH */
3393                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3394                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3395                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3396                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3397                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3398                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3399                 filter->ip_addr_type =
3400                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3401                 filter->src_ipaddr_mask[0] = 0xffffffff;
3402                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3403                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3404                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3405                 filter->ethertype = 0x800;
3406                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3407                 break;
3408         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3409                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3410                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3411                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3412                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3413                 filter->dst_port_mask = 0xffff;
3414                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3415                 filter->src_port_mask = 0xffff;
3416                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3417                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3418                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3419                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3420                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3421                 filter->ip_protocol = 6;
3422                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3423                 filter->ip_addr_type =
3424                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3425                 filter->src_ipaddr_mask[0] = 0xffffffff;
3426                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3427                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3428                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3429                 filter->ethertype = 0x800;
3430                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3431                 break;
3432         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3433                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3434                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3435                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3436                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3437                 filter->dst_port_mask = 0xffff;
3438                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3439                 filter->src_port_mask = 0xffff;
3440                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3441                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3442                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3443                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3444                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3445                 filter->ip_protocol = 17;
3446                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3447                 filter->ip_addr_type =
3448                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3449                 filter->src_ipaddr_mask[0] = 0xffffffff;
3450                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3451                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3452                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3453                 filter->ethertype = 0x800;
3454                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3455                 break;
3456         case RTE_ETH_FLOW_IPV6:
3457         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3458                 /* FALLTHROUGH */
3459                 filter->ip_addr_type =
3460                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3461                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3462                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3463                 rte_memcpy(filter->src_ipaddr,
3464                            fdir->input.flow.ipv6_flow.src_ip, 16);
3465                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3466                 rte_memcpy(filter->dst_ipaddr,
3467                            fdir->input.flow.ipv6_flow.dst_ip, 16);
3468                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3469                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3470                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3471                 memset(filter->src_ipaddr_mask, 0xff, 16);
3472                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3473                 filter->ethertype = 0x86dd;
3474                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3475                 break;
3476         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3477                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3478                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3479                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3480                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3481                 filter->dst_port_mask = 0xffff;
3482                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3483                 filter->src_port_mask = 0xffff;
3484                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3485                 filter->ip_addr_type =
3486                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3487                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3488                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3489                 rte_memcpy(filter->src_ipaddr,
3490                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3491                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3492                 rte_memcpy(filter->dst_ipaddr,
3493                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3494                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3495                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3496                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3497                 memset(filter->src_ipaddr_mask, 0xff, 16);
3498                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3499                 filter->ethertype = 0x86dd;
3500                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3501                 break;
3502         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3503                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3504                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3505                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3506                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3507                 filter->dst_port_mask = 0xffff;
3508                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3509                 filter->src_port_mask = 0xffff;
3510                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3511                 filter->ip_addr_type =
3512                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3513                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3514                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3515                 rte_memcpy(filter->src_ipaddr,
3516                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3517                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3518                 rte_memcpy(filter->dst_ipaddr,
3519                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3520                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3521                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3522                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3523                 memset(filter->src_ipaddr_mask, 0xff, 16);
3524                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3525                 filter->ethertype = 0x86dd;
3526                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3527                 break;
3528         case RTE_ETH_FLOW_L2_PAYLOAD:
3529                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3530                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3531                 break;
3532         case RTE_ETH_FLOW_VXLAN:
3533                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3534                         return -EINVAL;
3535                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3536                 filter->tunnel_type =
3537                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3538                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3539                 break;
3540         case RTE_ETH_FLOW_NVGRE:
3541                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3542                         return -EINVAL;
3543                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3544                 filter->tunnel_type =
3545                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3546                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3547                 break;
3548         case RTE_ETH_FLOW_UNKNOWN:
3549         case RTE_ETH_FLOW_RAW:
3550         case RTE_ETH_FLOW_FRAG_IPV4:
3551         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3552         case RTE_ETH_FLOW_FRAG_IPV6:
3553         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3554         case RTE_ETH_FLOW_IPV6_EX:
3555         case RTE_ETH_FLOW_IPV6_TCP_EX:
3556         case RTE_ETH_FLOW_IPV6_UDP_EX:
3557         case RTE_ETH_FLOW_GENEVE:
3558                 /* FALLTHROUGH */
3559         default:
3560                 return -EINVAL;
3561         }
3562
3563         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3564         vnic = &bp->vnic_info[fdir->action.rx_queue];
3565         if (vnic == NULL) {
3566                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3567                 return -EINVAL;
3568         }
3569
3570         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3571                 rte_memcpy(filter->dst_macaddr,
3572                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3573                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3574         }
3575
3576         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3577                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3578                 filter1 = STAILQ_FIRST(&vnic0->filter);
3579                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3580         } else {
3581                 filter->dst_id = vnic->fw_vnic_id;
3582                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3583                         if (filter->dst_macaddr[i] == 0x00)
3584                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3585                         else
3586                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3587         }
3588
3589         if (filter1 == NULL)
3590                 return -EINVAL;
3591
3592         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3593         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3594
3595         filter->enables = en;
3596
3597         return 0;
3598 }
3599
3600 static struct bnxt_filter_info *
3601 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3602                 struct bnxt_vnic_info **mvnic)
3603 {
3604         struct bnxt_filter_info *mf = NULL;
3605         int i;
3606
3607         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3608                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3609
3610                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3611                         if (mf->filter_type == nf->filter_type &&
3612                             mf->flags == nf->flags &&
3613                             mf->src_port == nf->src_port &&
3614                             mf->src_port_mask == nf->src_port_mask &&
3615                             mf->dst_port == nf->dst_port &&
3616                             mf->dst_port_mask == nf->dst_port_mask &&
3617                             mf->ip_protocol == nf->ip_protocol &&
3618                             mf->ip_addr_type == nf->ip_addr_type &&
3619                             mf->ethertype == nf->ethertype &&
3620                             mf->vni == nf->vni &&
3621                             mf->tunnel_type == nf->tunnel_type &&
3622                             mf->l2_ovlan == nf->l2_ovlan &&
3623                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3624                             mf->l2_ivlan == nf->l2_ivlan &&
3625                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3626                             !memcmp(mf->l2_addr, nf->l2_addr,
3627                                     RTE_ETHER_ADDR_LEN) &&
3628                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3629                                     RTE_ETHER_ADDR_LEN) &&
3630                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3631                                     RTE_ETHER_ADDR_LEN) &&
3632                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3633                                     RTE_ETHER_ADDR_LEN) &&
3634                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3635                                     sizeof(nf->src_ipaddr)) &&
3636                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3637                                     sizeof(nf->src_ipaddr_mask)) &&
3638                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3639                                     sizeof(nf->dst_ipaddr)) &&
3640                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3641                                     sizeof(nf->dst_ipaddr_mask))) {
3642                                 if (mvnic)
3643                                         *mvnic = vnic;
3644                                 return mf;
3645                         }
3646                 }
3647         }
3648         return NULL;
3649 }
3650
3651 static int
3652 bnxt_fdir_filter(struct rte_eth_dev *dev,
3653                  enum rte_filter_op filter_op,
3654                  void *arg)
3655 {
3656         struct bnxt *bp = dev->data->dev_private;
3657         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3658         struct bnxt_filter_info *filter, *match;
3659         struct bnxt_vnic_info *vnic, *mvnic;
3660         int ret = 0, i;
3661
3662         if (filter_op == RTE_ETH_FILTER_NOP)
3663                 return 0;
3664
3665         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3666                 return -EINVAL;
3667
3668         switch (filter_op) {
3669         case RTE_ETH_FILTER_ADD:
3670         case RTE_ETH_FILTER_DELETE:
3671                 /* FALLTHROUGH */
3672                 filter = bnxt_get_unused_filter(bp);
3673                 if (filter == NULL) {
3674                         PMD_DRV_LOG(ERR,
3675                                 "Not enough resources for a new flow.\n");
3676                         return -ENOMEM;
3677                 }
3678
3679                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3680                 if (ret != 0)
3681                         goto free_filter;
3682                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3683
3684                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3685                         vnic = &bp->vnic_info[0];
3686                 else
3687                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3688
3689                 match = bnxt_match_fdir(bp, filter, &mvnic);
3690                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3691                         if (match->dst_id == vnic->fw_vnic_id) {
3692                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3693                                 ret = -EEXIST;
3694                                 goto free_filter;
3695                         } else {
3696                                 match->dst_id = vnic->fw_vnic_id;
3697                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3698                                                                   match->dst_id,
3699                                                                   match);
3700                                 STAILQ_REMOVE(&mvnic->filter, match,
3701                                               bnxt_filter_info, next);
3702                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3703                                 PMD_DRV_LOG(ERR,
3704                                         "Filter with matching pattern exist\n");
3705                                 PMD_DRV_LOG(ERR,
3706                                         "Updated it to new destination q\n");
3707                                 goto free_filter;
3708                         }
3709                 }
3710                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3711                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3712                         ret = -ENOENT;
3713                         goto free_filter;
3714                 }
3715
3716                 if (filter_op == RTE_ETH_FILTER_ADD) {
3717                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3718                                                           filter->dst_id,
3719                                                           filter);
3720                         if (ret)
3721                                 goto free_filter;
3722                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3723                 } else {
3724                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3725                         STAILQ_REMOVE(&vnic->filter, match,
3726                                       bnxt_filter_info, next);
3727                         bnxt_free_filter(bp, match);
3728                         bnxt_free_filter(bp, filter);
3729                 }
3730                 break;
3731         case RTE_ETH_FILTER_FLUSH:
3732                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3733                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3734
3735                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3736                                 if (filter->filter_type ==
3737                                     HWRM_CFA_NTUPLE_FILTER) {
3738                                         ret =
3739                                         bnxt_hwrm_clear_ntuple_filter(bp,
3740                                                                       filter);
3741                                         STAILQ_REMOVE(&vnic->filter, filter,
3742                                                       bnxt_filter_info, next);
3743                                 }
3744                         }
3745                 }
3746                 return ret;
3747         case RTE_ETH_FILTER_UPDATE:
3748         case RTE_ETH_FILTER_STATS:
3749         case RTE_ETH_FILTER_INFO:
3750                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3751                 break;
3752         default:
3753                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3754                 ret = -EINVAL;
3755                 break;
3756         }
3757         return ret;
3758
3759 free_filter:
3760         bnxt_free_filter(bp, filter);
3761         return ret;
3762 }
3763
3764 int
3765 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3766                     enum rte_filter_type filter_type,
3767                     enum rte_filter_op filter_op, void *arg)
3768 {
3769         struct bnxt *bp = dev->data->dev_private;
3770         int ret = 0;
3771
3772         if (!bp)
3773                 return -EIO;
3774
3775         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3776                 struct bnxt_representor *vfr = dev->data->dev_private;
3777                 bp = vfr->parent_dev->data->dev_private;
3778                 /* parent is deleted while children are still valid */
3779                 if (!bp) {
3780                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n",
3781                                     dev->data->port_id,
3782                                     filter_type,
3783                                     filter_op);
3784                         return -EIO;
3785                 }
3786         }
3787
3788         ret = is_bnxt_in_error(bp);
3789         if (ret)
3790                 return ret;
3791
3792         switch (filter_type) {
3793         case RTE_ETH_FILTER_TUNNEL:
3794                 PMD_DRV_LOG(ERR,
3795                         "filter type: %d: To be implemented\n", filter_type);
3796                 break;
3797         case RTE_ETH_FILTER_FDIR:
3798                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3799                 break;
3800         case RTE_ETH_FILTER_NTUPLE:
3801                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3802                 break;
3803         case RTE_ETH_FILTER_ETHERTYPE:
3804                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3805                 break;
3806         case RTE_ETH_FILTER_GENERIC:
3807                 if (filter_op != RTE_ETH_FILTER_GET)
3808                         return -EINVAL;
3809                 if (BNXT_TRUFLOW_EN(bp))
3810                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3811                 else
3812                         *(const void **)arg = &bnxt_flow_ops;
3813                 break;
3814         default:
3815                 PMD_DRV_LOG(ERR,
3816                         "Filter type (%d) not supported", filter_type);
3817                 ret = -EINVAL;
3818                 break;
3819         }
3820         return ret;
3821 }
3822
3823 static const uint32_t *
3824 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3825 {
3826         static const uint32_t ptypes[] = {
3827                 RTE_PTYPE_L2_ETHER_VLAN,
3828                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3829                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3830                 RTE_PTYPE_L4_ICMP,
3831                 RTE_PTYPE_L4_TCP,
3832                 RTE_PTYPE_L4_UDP,
3833                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3834                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3835                 RTE_PTYPE_INNER_L4_ICMP,
3836                 RTE_PTYPE_INNER_L4_TCP,
3837                 RTE_PTYPE_INNER_L4_UDP,
3838                 RTE_PTYPE_UNKNOWN
3839         };
3840
3841         if (!dev->rx_pkt_burst)
3842                 return NULL;
3843
3844         return ptypes;
3845 }
3846
3847 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3848                          int reg_win)
3849 {
3850         uint32_t reg_base = *reg_arr & 0xfffff000;
3851         uint32_t win_off;
3852         int i;
3853
3854         for (i = 0; i < count; i++) {
3855                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3856                         return -ERANGE;
3857         }
3858         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3859         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3860         return 0;
3861 }
3862
3863 static int bnxt_map_ptp_regs(struct bnxt *bp)
3864 {
3865         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3866         uint32_t *reg_arr;
3867         int rc, i;
3868
3869         reg_arr = ptp->rx_regs;
3870         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3871         if (rc)
3872                 return rc;
3873
3874         reg_arr = ptp->tx_regs;
3875         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3876         if (rc)
3877                 return rc;
3878
3879         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3880                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3881
3882         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3883                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3884
3885         return 0;
3886 }
3887
3888 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3889 {
3890         rte_write32(0, (uint8_t *)bp->bar0 +
3891                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3892         rte_write32(0, (uint8_t *)bp->bar0 +
3893                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3894 }
3895
3896 static uint64_t bnxt_cc_read(struct bnxt *bp)
3897 {
3898         uint64_t ns;
3899
3900         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3901                               BNXT_GRCPF_REG_SYNC_TIME));
3902         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3903                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3904         return ns;
3905 }
3906
3907 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3908 {
3909         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3910         uint32_t fifo;
3911
3912         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3913                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3914         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3915                 return -EAGAIN;
3916
3917         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3918                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3919         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3920                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3921         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3922                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3923
3924         return 0;
3925 }
3926
3927 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3928 {
3929         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3930         struct bnxt_pf_info *pf = bp->pf;
3931         uint16_t port_id;
3932         uint32_t fifo;
3933
3934         if (!ptp)
3935                 return -ENODEV;
3936
3937         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3938                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3939         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3940                 return -EAGAIN;
3941
3942         port_id = pf->port_id;
3943         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3944                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3945
3946         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3947                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3948         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3949 /*              bnxt_clr_rx_ts(bp);       TBD  */
3950                 return -EBUSY;
3951         }
3952
3953         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3954                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3955         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3956                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3957
3958         return 0;
3959 }
3960
3961 static int
3962 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3963 {
3964         uint64_t ns;
3965         struct bnxt *bp = dev->data->dev_private;
3966         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3967
3968         if (!ptp)
3969                 return 0;
3970
3971         ns = rte_timespec_to_ns(ts);
3972         /* Set the timecounters to a new value. */
3973         ptp->tc.nsec = ns;
3974
3975         return 0;
3976 }
3977
3978 static int
3979 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3980 {
3981         struct bnxt *bp = dev->data->dev_private;
3982         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3983         uint64_t ns, systime_cycles = 0;
3984         int rc = 0;
3985
3986         if (!ptp)
3987                 return 0;
3988
3989         if (BNXT_CHIP_THOR(bp))
3990                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3991                                              &systime_cycles);
3992         else
3993                 systime_cycles = bnxt_cc_read(bp);
3994
3995         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3996         *ts = rte_ns_to_timespec(ns);
3997
3998         return rc;
3999 }
4000 static int
4001 bnxt_timesync_enable(struct rte_eth_dev *dev)
4002 {
4003         struct bnxt *bp = dev->data->dev_private;
4004         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4005         uint32_t shift = 0;
4006         int rc;
4007
4008         if (!ptp)
4009                 return 0;
4010
4011         ptp->rx_filter = 1;
4012         ptp->tx_tstamp_en = 1;
4013         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
4014
4015         rc = bnxt_hwrm_ptp_cfg(bp);
4016         if (rc)
4017                 return rc;
4018
4019         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
4020         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4021         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4022
4023         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4024         ptp->tc.cc_shift = shift;
4025         ptp->tc.nsec_mask = (1ULL << shift) - 1;
4026
4027         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4028         ptp->rx_tstamp_tc.cc_shift = shift;
4029         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4030
4031         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4032         ptp->tx_tstamp_tc.cc_shift = shift;
4033         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4034
4035         if (!BNXT_CHIP_THOR(bp))
4036                 bnxt_map_ptp_regs(bp);
4037
4038         return 0;
4039 }
4040
4041 static int
4042 bnxt_timesync_disable(struct rte_eth_dev *dev)
4043 {
4044         struct bnxt *bp = dev->data->dev_private;
4045         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4046
4047         if (!ptp)
4048                 return 0;
4049
4050         ptp->rx_filter = 0;
4051         ptp->tx_tstamp_en = 0;
4052         ptp->rxctl = 0;
4053
4054         bnxt_hwrm_ptp_cfg(bp);
4055
4056         if (!BNXT_CHIP_THOR(bp))
4057                 bnxt_unmap_ptp_regs(bp);
4058
4059         return 0;
4060 }
4061
4062 static int
4063 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4064                                  struct timespec *timestamp,
4065                                  uint32_t flags __rte_unused)
4066 {
4067         struct bnxt *bp = dev->data->dev_private;
4068         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4069         uint64_t rx_tstamp_cycles = 0;
4070         uint64_t ns;
4071
4072         if (!ptp)
4073                 return 0;
4074
4075         if (BNXT_CHIP_THOR(bp))
4076                 rx_tstamp_cycles = ptp->rx_timestamp;
4077         else
4078                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
4079
4080         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
4081         *timestamp = rte_ns_to_timespec(ns);
4082         return  0;
4083 }
4084
4085 static int
4086 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4087                                  struct timespec *timestamp)
4088 {
4089         struct bnxt *bp = dev->data->dev_private;
4090         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4091         uint64_t tx_tstamp_cycles = 0;
4092         uint64_t ns;
4093         int rc = 0;
4094
4095         if (!ptp)
4096                 return 0;
4097
4098         if (BNXT_CHIP_THOR(bp))
4099                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
4100                                              &tx_tstamp_cycles);
4101         else
4102                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
4103
4104         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
4105         *timestamp = rte_ns_to_timespec(ns);
4106
4107         return rc;
4108 }
4109
4110 static int
4111 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4112 {
4113         struct bnxt *bp = dev->data->dev_private;
4114         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4115
4116         if (!ptp)
4117                 return 0;
4118
4119         ptp->tc.nsec += delta;
4120
4121         return 0;
4122 }
4123
4124 static int
4125 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
4126 {
4127         struct bnxt *bp = dev->data->dev_private;
4128         int rc;
4129         uint32_t dir_entries;
4130         uint32_t entry_length;
4131
4132         rc = is_bnxt_in_error(bp);
4133         if (rc)
4134                 return rc;
4135
4136         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
4137                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4138                     bp->pdev->addr.devid, bp->pdev->addr.function);
4139
4140         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4141         if (rc != 0)
4142                 return rc;
4143
4144         return dir_entries * entry_length;
4145 }
4146
4147 static int
4148 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
4149                 struct rte_dev_eeprom_info *in_eeprom)
4150 {
4151         struct bnxt *bp = dev->data->dev_private;
4152         uint32_t index;
4153         uint32_t offset;
4154         int rc;
4155
4156         rc = is_bnxt_in_error(bp);
4157         if (rc)
4158                 return rc;
4159
4160         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4161                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4162                     bp->pdev->addr.devid, bp->pdev->addr.function,
4163                     in_eeprom->offset, in_eeprom->length);
4164
4165         if (in_eeprom->offset == 0) /* special offset value to get directory */
4166                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
4167                                                 in_eeprom->data);
4168
4169         index = in_eeprom->offset >> 24;
4170         offset = in_eeprom->offset & 0xffffff;
4171
4172         if (index != 0)
4173                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
4174                                            in_eeprom->length, in_eeprom->data);
4175
4176         return 0;
4177 }
4178
4179 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
4180 {
4181         switch (dir_type) {
4182         case BNX_DIR_TYPE_CHIMP_PATCH:
4183         case BNX_DIR_TYPE_BOOTCODE:
4184         case BNX_DIR_TYPE_BOOTCODE_2:
4185         case BNX_DIR_TYPE_APE_FW:
4186         case BNX_DIR_TYPE_APE_PATCH:
4187         case BNX_DIR_TYPE_KONG_FW:
4188         case BNX_DIR_TYPE_KONG_PATCH:
4189         case BNX_DIR_TYPE_BONO_FW:
4190         case BNX_DIR_TYPE_BONO_PATCH:
4191                 /* FALLTHROUGH */
4192                 return true;
4193         }
4194
4195         return false;
4196 }
4197
4198 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
4199 {
4200         switch (dir_type) {
4201         case BNX_DIR_TYPE_AVS:
4202         case BNX_DIR_TYPE_EXP_ROM_MBA:
4203         case BNX_DIR_TYPE_PCIE:
4204         case BNX_DIR_TYPE_TSCF_UCODE:
4205         case BNX_DIR_TYPE_EXT_PHY:
4206         case BNX_DIR_TYPE_CCM:
4207         case BNX_DIR_TYPE_ISCSI_BOOT:
4208         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
4209         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
4210                 /* FALLTHROUGH */
4211                 return true;
4212         }
4213
4214         return false;
4215 }
4216
4217 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
4218 {
4219         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
4220                 bnxt_dir_type_is_other_exec_format(dir_type);
4221 }
4222
4223 static int
4224 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
4225                 struct rte_dev_eeprom_info *in_eeprom)
4226 {
4227         struct bnxt *bp = dev->data->dev_private;
4228         uint8_t index, dir_op;
4229         uint16_t type, ext, ordinal, attr;
4230         int rc;
4231
4232         rc = is_bnxt_in_error(bp);
4233         if (rc)
4234                 return rc;
4235
4236         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4237                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4238                     bp->pdev->addr.devid, bp->pdev->addr.function,
4239                     in_eeprom->offset, in_eeprom->length);
4240
4241         if (!BNXT_PF(bp)) {
4242                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
4243                 return -EINVAL;
4244         }
4245
4246         type = in_eeprom->magic >> 16;
4247
4248         if (type == 0xffff) { /* special value for directory operations */
4249                 index = in_eeprom->magic & 0xff;
4250                 dir_op = in_eeprom->magic >> 8;
4251                 if (index == 0)
4252                         return -EINVAL;
4253                 switch (dir_op) {
4254                 case 0x0e: /* erase */
4255                         if (in_eeprom->offset != ~in_eeprom->magic)
4256                                 return -EINVAL;
4257                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
4258                 default:
4259                         return -EINVAL;
4260                 }
4261         }
4262
4263         /* Create or re-write an NVM item: */
4264         if (bnxt_dir_type_is_executable(type) == true)
4265                 return -EOPNOTSUPP;
4266         ext = in_eeprom->magic & 0xffff;
4267         ordinal = in_eeprom->offset >> 16;
4268         attr = in_eeprom->offset & 0xffff;
4269
4270         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
4271                                      in_eeprom->data, in_eeprom->length);
4272 }
4273
4274 /*
4275  * Initialization
4276  */
4277
4278 static const struct eth_dev_ops bnxt_dev_ops = {
4279         .dev_infos_get = bnxt_dev_info_get_op,
4280         .dev_close = bnxt_dev_close_op,
4281         .dev_configure = bnxt_dev_configure_op,
4282         .dev_start = bnxt_dev_start_op,
4283         .dev_stop = bnxt_dev_stop_op,
4284         .dev_set_link_up = bnxt_dev_set_link_up_op,
4285         .dev_set_link_down = bnxt_dev_set_link_down_op,
4286         .stats_get = bnxt_stats_get_op,
4287         .stats_reset = bnxt_stats_reset_op,
4288         .rx_queue_setup = bnxt_rx_queue_setup_op,
4289         .rx_queue_release = bnxt_rx_queue_release_op,
4290         .tx_queue_setup = bnxt_tx_queue_setup_op,
4291         .tx_queue_release = bnxt_tx_queue_release_op,
4292         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4293         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4294         .reta_update = bnxt_reta_update_op,
4295         .reta_query = bnxt_reta_query_op,
4296         .rss_hash_update = bnxt_rss_hash_update_op,
4297         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4298         .link_update = bnxt_link_update_op,
4299         .promiscuous_enable = bnxt_promiscuous_enable_op,
4300         .promiscuous_disable = bnxt_promiscuous_disable_op,
4301         .allmulticast_enable = bnxt_allmulticast_enable_op,
4302         .allmulticast_disable = bnxt_allmulticast_disable_op,
4303         .mac_addr_add = bnxt_mac_addr_add_op,
4304         .mac_addr_remove = bnxt_mac_addr_remove_op,
4305         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4306         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4307         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4308         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4309         .vlan_filter_set = bnxt_vlan_filter_set_op,
4310         .vlan_offload_set = bnxt_vlan_offload_set_op,
4311         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4312         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4313         .mtu_set = bnxt_mtu_set_op,
4314         .mac_addr_set = bnxt_set_default_mac_addr_op,
4315         .xstats_get = bnxt_dev_xstats_get_op,
4316         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4317         .xstats_reset = bnxt_dev_xstats_reset_op,
4318         .fw_version_get = bnxt_fw_version_get,
4319         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4320         .rxq_info_get = bnxt_rxq_info_get_op,
4321         .txq_info_get = bnxt_txq_info_get_op,
4322         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4323         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4324         .dev_led_on = bnxt_dev_led_on_op,
4325         .dev_led_off = bnxt_dev_led_off_op,
4326         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4327         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4328         .rx_queue_start = bnxt_rx_queue_start,
4329         .rx_queue_stop = bnxt_rx_queue_stop,
4330         .tx_queue_start = bnxt_tx_queue_start,
4331         .tx_queue_stop = bnxt_tx_queue_stop,
4332         .filter_ctrl = bnxt_filter_ctrl_op,
4333         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4334         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4335         .get_eeprom           = bnxt_get_eeprom_op,
4336         .set_eeprom           = bnxt_set_eeprom_op,
4337         .timesync_enable      = bnxt_timesync_enable,
4338         .timesync_disable     = bnxt_timesync_disable,
4339         .timesync_read_time   = bnxt_timesync_read_time,
4340         .timesync_write_time   = bnxt_timesync_write_time,
4341         .timesync_adjust_time = bnxt_timesync_adjust_time,
4342         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4343         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4344 };
4345
4346 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4347 {
4348         uint32_t offset;
4349
4350         /* Only pre-map the reset GRC registers using window 3 */
4351         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4352                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4353
4354         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4355
4356         return offset;
4357 }
4358
4359 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4360 {
4361         struct bnxt_error_recovery_info *info = bp->recovery_info;
4362         uint32_t reg_base = 0xffffffff;
4363         int i;
4364
4365         /* Only pre-map the monitoring GRC registers using window 2 */
4366         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4367                 uint32_t reg = info->status_regs[i];
4368
4369                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4370                         continue;
4371
4372                 if (reg_base == 0xffffffff)
4373                         reg_base = reg & 0xfffff000;
4374                 if ((reg & 0xfffff000) != reg_base)
4375                         return -ERANGE;
4376
4377                 /* Use mask 0xffc as the Lower 2 bits indicates
4378                  * address space location
4379                  */
4380                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4381                                                 (reg & 0xffc);
4382         }
4383
4384         if (reg_base == 0xffffffff)
4385                 return 0;
4386
4387         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4388                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4389
4390         return 0;
4391 }
4392
4393 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4394 {
4395         struct bnxt_error_recovery_info *info = bp->recovery_info;
4396         uint32_t delay = info->delay_after_reset[index];
4397         uint32_t val = info->reset_reg_val[index];
4398         uint32_t reg = info->reset_reg[index];
4399         uint32_t type, offset;
4400
4401         type = BNXT_FW_STATUS_REG_TYPE(reg);
4402         offset = BNXT_FW_STATUS_REG_OFF(reg);
4403
4404         switch (type) {
4405         case BNXT_FW_STATUS_REG_TYPE_CFG:
4406                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4407                 break;
4408         case BNXT_FW_STATUS_REG_TYPE_GRC:
4409                 offset = bnxt_map_reset_regs(bp, offset);
4410                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4411                 break;
4412         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4413                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4414                 break;
4415         }
4416         /* wait on a specific interval of time until core reset is complete */
4417         if (delay)
4418                 rte_delay_ms(delay);
4419 }
4420
4421 static void bnxt_dev_cleanup(struct bnxt *bp)
4422 {
4423         bp->eth_dev->data->dev_link.link_status = 0;
4424         bp->link_info->link_up = 0;
4425         if (bp->eth_dev->data->dev_started)
4426                 bnxt_dev_stop_op(bp->eth_dev);
4427
4428         bnxt_uninit_resources(bp, true);
4429 }
4430
4431 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4432 {
4433         struct rte_eth_dev *dev = bp->eth_dev;
4434         struct rte_vlan_filter_conf *vfc;
4435         int vidx, vbit, rc;
4436         uint16_t vlan_id;
4437
4438         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4439                 vfc = &dev->data->vlan_filter_conf;
4440                 vidx = vlan_id / 64;
4441                 vbit = vlan_id % 64;
4442
4443                 /* Each bit corresponds to a VLAN id */
4444                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4445                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4446                         if (rc)
4447                                 return rc;
4448                 }
4449         }
4450
4451         return 0;
4452 }
4453
4454 static int bnxt_restore_mac_filters(struct bnxt *bp)
4455 {
4456         struct rte_eth_dev *dev = bp->eth_dev;
4457         struct rte_eth_dev_info dev_info;
4458         struct rte_ether_addr *addr;
4459         uint64_t pool_mask;
4460         uint32_t pool = 0;
4461         uint16_t i;
4462         int rc;
4463
4464         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4465                 return 0;
4466
4467         rc = bnxt_dev_info_get_op(dev, &dev_info);
4468         if (rc)
4469                 return rc;
4470
4471         /* replay MAC address configuration */
4472         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4473                 addr = &dev->data->mac_addrs[i];
4474
4475                 /* skip zero address */
4476                 if (rte_is_zero_ether_addr(addr))
4477                         continue;
4478
4479                 pool = 0;
4480                 pool_mask = dev->data->mac_pool_sel[i];
4481
4482                 do {
4483                         if (pool_mask & 1ULL) {
4484                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4485                                 if (rc)
4486                                         return rc;
4487                         }
4488                         pool_mask >>= 1;
4489                         pool++;
4490                 } while (pool_mask);
4491         }
4492
4493         return 0;
4494 }
4495
4496 static int bnxt_restore_filters(struct bnxt *bp)
4497 {
4498         struct rte_eth_dev *dev = bp->eth_dev;
4499         int ret = 0;
4500
4501         if (dev->data->all_multicast) {
4502                 ret = bnxt_allmulticast_enable_op(dev);
4503                 if (ret)
4504                         return ret;
4505         }
4506         if (dev->data->promiscuous) {
4507                 ret = bnxt_promiscuous_enable_op(dev);
4508                 if (ret)
4509                         return ret;
4510         }
4511
4512         ret = bnxt_restore_mac_filters(bp);
4513         if (ret)
4514                 return ret;
4515
4516         ret = bnxt_restore_vlan_filters(bp);
4517         /* TODO restore other filters as well */
4518         return ret;
4519 }
4520
4521 static void bnxt_dev_recover(void *arg)
4522 {
4523         struct bnxt *bp = arg;
4524         int timeout = bp->fw_reset_max_msecs;
4525         int rc = 0;
4526
4527         /* Clear Error flag so that device re-init should happen */
4528         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4529
4530         do {
4531                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4532                 if (rc == 0)
4533                         break;
4534                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4535                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4536         } while (rc && timeout);
4537
4538         if (rc) {
4539                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4540                 goto err;
4541         }
4542
4543         rc = bnxt_init_resources(bp, true);
4544         if (rc) {
4545                 PMD_DRV_LOG(ERR,
4546                             "Failed to initialize resources after reset\n");
4547                 goto err;
4548         }
4549         /* clear reset flag as the device is initialized now */
4550         bp->flags &= ~BNXT_FLAG_FW_RESET;
4551
4552         rc = bnxt_dev_start_op(bp->eth_dev);
4553         if (rc) {
4554                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4555                 goto err_start;
4556         }
4557
4558         rc = bnxt_restore_filters(bp);
4559         if (rc)
4560                 goto err_start;
4561
4562         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4563         return;
4564 err_start:
4565         bnxt_dev_stop_op(bp->eth_dev);
4566 err:
4567         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4568         bnxt_uninit_resources(bp, false);
4569         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4570 }
4571
4572 void bnxt_dev_reset_and_resume(void *arg)
4573 {
4574         struct bnxt *bp = arg;
4575         int rc;
4576
4577         bnxt_dev_cleanup(bp);
4578
4579         bnxt_wait_for_device_shutdown(bp);
4580
4581         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4582                                bnxt_dev_recover, (void *)bp);
4583         if (rc)
4584                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4585 }
4586
4587 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4588 {
4589         struct bnxt_error_recovery_info *info = bp->recovery_info;
4590         uint32_t reg = info->status_regs[index];
4591         uint32_t type, offset, val = 0;
4592
4593         type = BNXT_FW_STATUS_REG_TYPE(reg);
4594         offset = BNXT_FW_STATUS_REG_OFF(reg);
4595
4596         switch (type) {
4597         case BNXT_FW_STATUS_REG_TYPE_CFG:
4598                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4599                 break;
4600         case BNXT_FW_STATUS_REG_TYPE_GRC:
4601                 offset = info->mapped_status_regs[index];
4602                 /* FALLTHROUGH */
4603         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4604                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4605                                        offset));
4606                 break;
4607         }
4608
4609         return val;
4610 }
4611
4612 static int bnxt_fw_reset_all(struct bnxt *bp)
4613 {
4614         struct bnxt_error_recovery_info *info = bp->recovery_info;
4615         uint32_t i;
4616         int rc = 0;
4617
4618         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4619                 /* Reset through master function driver */
4620                 for (i = 0; i < info->reg_array_cnt; i++)
4621                         bnxt_write_fw_reset_reg(bp, i);
4622                 /* Wait for time specified by FW after triggering reset */
4623                 rte_delay_ms(info->master_func_wait_period_after_reset);
4624         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4625                 /* Reset with the help of Kong processor */
4626                 rc = bnxt_hwrm_fw_reset(bp);
4627                 if (rc)
4628                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4629         }
4630
4631         return rc;
4632 }
4633
4634 static void bnxt_fw_reset_cb(void *arg)
4635 {
4636         struct bnxt *bp = arg;
4637         struct bnxt_error_recovery_info *info = bp->recovery_info;
4638         int rc = 0;
4639
4640         /* Only Master function can do FW reset */
4641         if (bnxt_is_master_func(bp) &&
4642             bnxt_is_recovery_enabled(bp)) {
4643                 rc = bnxt_fw_reset_all(bp);
4644                 if (rc) {
4645                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4646                         return;
4647                 }
4648         }
4649
4650         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4651          * EXCEPTION_FATAL_ASYNC event to all the functions
4652          * (including MASTER FUNC). After receiving this Async, all the active
4653          * drivers should treat this case as FW initiated recovery
4654          */
4655         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4656                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4657                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4658
4659                 /* To recover from error */
4660                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4661                                   (void *)bp);
4662         }
4663 }
4664
4665 /* Driver should poll FW heartbeat, reset_counter with the frequency
4666  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4667  * When the driver detects heartbeat stop or change in reset_counter,
4668  * it has to trigger a reset to recover from the error condition.
4669  * A “master PF” is the function who will have the privilege to
4670  * initiate the chimp reset. The master PF will be elected by the
4671  * firmware and will be notified through async message.
4672  */
4673 static void bnxt_check_fw_health(void *arg)
4674 {
4675         struct bnxt *bp = arg;
4676         struct bnxt_error_recovery_info *info = bp->recovery_info;
4677         uint32_t val = 0, wait_msec;
4678
4679         if (!info || !bnxt_is_recovery_enabled(bp) ||
4680             is_bnxt_in_error(bp))
4681                 return;
4682
4683         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4684         if (val == info->last_heart_beat)
4685                 goto reset;
4686
4687         info->last_heart_beat = val;
4688
4689         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4690         if (val != info->last_reset_counter)
4691                 goto reset;
4692
4693         info->last_reset_counter = val;
4694
4695         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4696                           bnxt_check_fw_health, (void *)bp);
4697
4698         return;
4699 reset:
4700         /* Stop DMA to/from device */
4701         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4702         bp->flags |= BNXT_FLAG_FW_RESET;
4703
4704         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4705
4706         if (bnxt_is_master_func(bp))
4707                 wait_msec = info->master_func_wait_period;
4708         else
4709                 wait_msec = info->normal_func_wait_period;
4710
4711         rte_eal_alarm_set(US_PER_MS * wait_msec,
4712                           bnxt_fw_reset_cb, (void *)bp);
4713 }
4714
4715 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4716 {
4717         uint32_t polling_freq;
4718
4719         pthread_mutex_lock(&bp->health_check_lock);
4720
4721         if (!bnxt_is_recovery_enabled(bp))
4722                 goto done;
4723
4724         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4725                 goto done;
4726
4727         polling_freq = bp->recovery_info->driver_polling_freq;
4728
4729         rte_eal_alarm_set(US_PER_MS * polling_freq,
4730                           bnxt_check_fw_health, (void *)bp);
4731         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4732
4733 done:
4734         pthread_mutex_unlock(&bp->health_check_lock);
4735 }
4736
4737 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4738 {
4739         if (!bnxt_is_recovery_enabled(bp))
4740                 return;
4741
4742         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4743         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4744 }
4745
4746 static bool bnxt_vf_pciid(uint16_t device_id)
4747 {
4748         switch (device_id) {
4749         case BROADCOM_DEV_ID_57304_VF:
4750         case BROADCOM_DEV_ID_57406_VF:
4751         case BROADCOM_DEV_ID_5731X_VF:
4752         case BROADCOM_DEV_ID_5741X_VF:
4753         case BROADCOM_DEV_ID_57414_VF:
4754         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4755         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4756         case BROADCOM_DEV_ID_58802_VF:
4757         case BROADCOM_DEV_ID_57500_VF1:
4758         case BROADCOM_DEV_ID_57500_VF2:
4759                 /* FALLTHROUGH */
4760                 return true;
4761         default:
4762                 return false;
4763         }
4764 }
4765
4766 static bool bnxt_thor_device(uint16_t device_id)
4767 {
4768         switch (device_id) {
4769         case BROADCOM_DEV_ID_57508:
4770         case BROADCOM_DEV_ID_57504:
4771         case BROADCOM_DEV_ID_57502:
4772         case BROADCOM_DEV_ID_57508_MF1:
4773         case BROADCOM_DEV_ID_57504_MF1:
4774         case BROADCOM_DEV_ID_57502_MF1:
4775         case BROADCOM_DEV_ID_57508_MF2:
4776         case BROADCOM_DEV_ID_57504_MF2:
4777         case BROADCOM_DEV_ID_57502_MF2:
4778         case BROADCOM_DEV_ID_57500_VF1:
4779         case BROADCOM_DEV_ID_57500_VF2:
4780                 /* FALLTHROUGH */
4781                 return true;
4782         default:
4783                 return false;
4784         }
4785 }
4786
4787 bool bnxt_stratus_device(struct bnxt *bp)
4788 {
4789         uint16_t device_id = bp->pdev->id.device_id;
4790
4791         switch (device_id) {
4792         case BROADCOM_DEV_ID_STRATUS_NIC:
4793         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4794         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4795                 /* FALLTHROUGH */
4796                 return true;
4797         default:
4798                 return false;
4799         }
4800 }
4801
4802 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4803 {
4804         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4805         struct bnxt *bp = eth_dev->data->dev_private;
4806
4807         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4808         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4809         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4810         if (!bp->bar0 || !bp->doorbell_base) {
4811                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4812                 return -ENODEV;
4813         }
4814
4815         bp->eth_dev = eth_dev;
4816         bp->pdev = pci_dev;
4817
4818         return 0;
4819 }
4820
4821 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4822                                   struct bnxt_ctx_pg_info *ctx_pg,
4823                                   uint32_t mem_size,
4824                                   const char *suffix,
4825                                   uint16_t idx)
4826 {
4827         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4828         const struct rte_memzone *mz = NULL;
4829         char mz_name[RTE_MEMZONE_NAMESIZE];
4830         rte_iova_t mz_phys_addr;
4831         uint64_t valid_bits = 0;
4832         uint32_t sz;
4833         int i;
4834
4835         if (!mem_size)
4836                 return 0;
4837
4838         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4839                          BNXT_PAGE_SIZE;
4840         rmem->page_size = BNXT_PAGE_SIZE;
4841         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4842         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4843         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4844
4845         valid_bits = PTU_PTE_VALID;
4846
4847         if (rmem->nr_pages > 1) {
4848                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4849                          "bnxt_ctx_pg_tbl%s_%x_%d",
4850                          suffix, idx, bp->eth_dev->data->port_id);
4851                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4852                 mz = rte_memzone_lookup(mz_name);
4853                 if (!mz) {
4854                         mz = rte_memzone_reserve_aligned(mz_name,
4855                                                 rmem->nr_pages * 8,
4856                                                 SOCKET_ID_ANY,
4857                                                 RTE_MEMZONE_2MB |
4858                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4859                                                 RTE_MEMZONE_IOVA_CONTIG,
4860                                                 BNXT_PAGE_SIZE);
4861                         if (mz == NULL)
4862                                 return -ENOMEM;
4863                 }
4864
4865                 memset(mz->addr, 0, mz->len);
4866                 mz_phys_addr = mz->iova;
4867
4868                 rmem->pg_tbl = mz->addr;
4869                 rmem->pg_tbl_map = mz_phys_addr;
4870                 rmem->pg_tbl_mz = mz;
4871         }
4872
4873         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4874                  suffix, idx, bp->eth_dev->data->port_id);
4875         mz = rte_memzone_lookup(mz_name);
4876         if (!mz) {
4877                 mz = rte_memzone_reserve_aligned(mz_name,
4878                                                  mem_size,
4879                                                  SOCKET_ID_ANY,
4880                                                  RTE_MEMZONE_1GB |
4881                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4882                                                  RTE_MEMZONE_IOVA_CONTIG,
4883                                                  BNXT_PAGE_SIZE);
4884                 if (mz == NULL)
4885                         return -ENOMEM;
4886         }
4887
4888         memset(mz->addr, 0, mz->len);
4889         mz_phys_addr = mz->iova;
4890
4891         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4892                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4893                 rmem->dma_arr[i] = mz_phys_addr + sz;
4894
4895                 if (rmem->nr_pages > 1) {
4896                         if (i == rmem->nr_pages - 2 &&
4897                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4898                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4899                         else if (i == rmem->nr_pages - 1 &&
4900                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4901                                 valid_bits |= PTU_PTE_LAST;
4902
4903                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4904                                                            valid_bits);
4905                 }
4906         }
4907
4908         rmem->mz = mz;
4909         if (rmem->vmem_size)
4910                 rmem->vmem = (void **)mz->addr;
4911         rmem->dma_arr[0] = mz_phys_addr;
4912         return 0;
4913 }
4914
4915 static void bnxt_free_ctx_mem(struct bnxt *bp)
4916 {
4917         int i;
4918
4919         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4920                 return;
4921
4922         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4923         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4924         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4925         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4926         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4927         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4928         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4929         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4930         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4931         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4932         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4933
4934         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4935                 if (bp->ctx->tqm_mem[i])
4936                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4937         }
4938
4939         rte_free(bp->ctx);
4940         bp->ctx = NULL;
4941 }
4942
4943 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4944
4945 #define min_t(type, x, y) ({                    \
4946         type __min1 = (x);                      \
4947         type __min2 = (y);                      \
4948         __min1 < __min2 ? __min1 : __min2; })
4949
4950 #define max_t(type, x, y) ({                    \
4951         type __max1 = (x);                      \
4952         type __max2 = (y);                      \
4953         __max1 > __max2 ? __max1 : __max2; })
4954
4955 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4956
4957 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4958 {
4959         struct bnxt_ctx_pg_info *ctx_pg;
4960         struct bnxt_ctx_mem_info *ctx;
4961         uint32_t mem_size, ena, entries;
4962         uint32_t entries_sp, min;
4963         int i, rc;
4964
4965         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4966         if (rc) {
4967                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4968                 return rc;
4969         }
4970         ctx = bp->ctx;
4971         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4972                 return 0;
4973
4974         ctx_pg = &ctx->qp_mem;
4975         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4976         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4977         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4978         if (rc)
4979                 return rc;
4980
4981         ctx_pg = &ctx->srq_mem;
4982         ctx_pg->entries = ctx->srq_max_l2_entries;
4983         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4984         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4985         if (rc)
4986                 return rc;
4987
4988         ctx_pg = &ctx->cq_mem;
4989         ctx_pg->entries = ctx->cq_max_l2_entries;
4990         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4991         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4992         if (rc)
4993                 return rc;
4994
4995         ctx_pg = &ctx->vnic_mem;
4996         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4997                 ctx->vnic_max_ring_table_entries;
4998         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4999         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
5000         if (rc)
5001                 return rc;
5002
5003         ctx_pg = &ctx->stat_mem;
5004         ctx_pg->entries = ctx->stat_max_entries;
5005         mem_size = ctx->stat_entry_size * ctx_pg->entries;
5006         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
5007         if (rc)
5008                 return rc;
5009
5010         min = ctx->tqm_min_entries_per_ring;
5011
5012         entries_sp = ctx->qp_max_l2_entries +
5013                      ctx->vnic_max_vnic_entries +
5014                      2 * ctx->qp_min_qp1_entries + min;
5015         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
5016
5017         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
5018         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
5019         entries = clamp_t(uint32_t, entries, min,
5020                           ctx->tqm_max_entries_per_ring);
5021         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
5022                 ctx_pg = ctx->tqm_mem[i];
5023                 ctx_pg->entries = i ? entries : entries_sp;
5024                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
5025                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
5026                 if (rc)
5027                         return rc;
5028                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
5029         }
5030
5031         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
5032         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
5033         if (rc)
5034                 PMD_DRV_LOG(ERR,
5035                             "Failed to configure context mem: rc = %d\n", rc);
5036         else
5037                 ctx->flags |= BNXT_CTX_FLAG_INITED;
5038
5039         return rc;
5040 }
5041
5042 static int bnxt_alloc_stats_mem(struct bnxt *bp)
5043 {
5044         struct rte_pci_device *pci_dev = bp->pdev;
5045         char mz_name[RTE_MEMZONE_NAMESIZE];
5046         const struct rte_memzone *mz = NULL;
5047         uint32_t total_alloc_len;
5048         rte_iova_t mz_phys_addr;
5049
5050         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
5051                 return 0;
5052
5053         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5054                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5055                  pci_dev->addr.bus, pci_dev->addr.devid,
5056                  pci_dev->addr.function, "rx_port_stats");
5057         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5058         mz = rte_memzone_lookup(mz_name);
5059         total_alloc_len =
5060                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
5061                                        sizeof(struct rx_port_stats_ext) + 512);
5062         if (!mz) {
5063                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
5064                                          SOCKET_ID_ANY,
5065                                          RTE_MEMZONE_2MB |
5066                                          RTE_MEMZONE_SIZE_HINT_ONLY |
5067                                          RTE_MEMZONE_IOVA_CONTIG);
5068                 if (mz == NULL)
5069                         return -ENOMEM;
5070         }
5071         memset(mz->addr, 0, mz->len);
5072         mz_phys_addr = mz->iova;
5073
5074         bp->rx_mem_zone = (const void *)mz;
5075         bp->hw_rx_port_stats = mz->addr;
5076         bp->hw_rx_port_stats_map = mz_phys_addr;
5077
5078         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5079                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5080                  pci_dev->addr.bus, pci_dev->addr.devid,
5081                  pci_dev->addr.function, "tx_port_stats");
5082         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5083         mz = rte_memzone_lookup(mz_name);
5084         total_alloc_len =
5085                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
5086                                        sizeof(struct tx_port_stats_ext) + 512);
5087         if (!mz) {
5088                 mz = rte_memzone_reserve(mz_name,
5089                                          total_alloc_len,
5090                                          SOCKET_ID_ANY,
5091                                          RTE_MEMZONE_2MB |
5092                                          RTE_MEMZONE_SIZE_HINT_ONLY |
5093                                          RTE_MEMZONE_IOVA_CONTIG);
5094                 if (mz == NULL)
5095                         return -ENOMEM;
5096         }
5097         memset(mz->addr, 0, mz->len);
5098         mz_phys_addr = mz->iova;
5099
5100         bp->tx_mem_zone = (const void *)mz;
5101         bp->hw_tx_port_stats = mz->addr;
5102         bp->hw_tx_port_stats_map = mz_phys_addr;
5103         bp->flags |= BNXT_FLAG_PORT_STATS;
5104
5105         /* Display extended statistics if FW supports it */
5106         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
5107             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
5108             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
5109                 return 0;
5110
5111         bp->hw_rx_port_stats_ext = (void *)
5112                 ((uint8_t *)bp->hw_rx_port_stats +
5113                  sizeof(struct rx_port_stats));
5114         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
5115                 sizeof(struct rx_port_stats);
5116         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
5117
5118         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
5119             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
5120                 bp->hw_tx_port_stats_ext = (void *)
5121                         ((uint8_t *)bp->hw_tx_port_stats +
5122                          sizeof(struct tx_port_stats));
5123                 bp->hw_tx_port_stats_ext_map =
5124                         bp->hw_tx_port_stats_map +
5125                         sizeof(struct tx_port_stats);
5126                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
5127         }
5128
5129         return 0;
5130 }
5131
5132 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
5133 {
5134         struct bnxt *bp = eth_dev->data->dev_private;
5135         int rc = 0;
5136
5137         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
5138                                                RTE_ETHER_ADDR_LEN *
5139                                                bp->max_l2_ctx,
5140                                                0);
5141         if (eth_dev->data->mac_addrs == NULL) {
5142                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
5143                 return -ENOMEM;
5144         }
5145
5146         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
5147                 if (BNXT_PF(bp))
5148                         return -EINVAL;
5149
5150                 /* Generate a random MAC address, if none was assigned by PF */
5151                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5152                 bnxt_eth_hw_addr_random(bp->mac_addr);
5153                 PMD_DRV_LOG(INFO,
5154                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
5155                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5156                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5157
5158                 rc = bnxt_hwrm_set_mac(bp);
5159                 if (rc)
5160                         return rc;
5161         }
5162
5163         /* Copy the permanent MAC from the FUNC_QCAPS response */
5164         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5165
5166         return rc;
5167 }
5168
5169 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5170 {
5171         int rc = 0;
5172
5173         /* MAC is already configured in FW */
5174         if (BNXT_HAS_DFLT_MAC_SET(bp))
5175                 return 0;
5176
5177         /* Restore the old MAC configured */
5178         rc = bnxt_hwrm_set_mac(bp);
5179         if (rc)
5180                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5181
5182         return rc;
5183 }
5184
5185 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5186 {
5187         if (!BNXT_PF(bp))
5188                 return;
5189
5190 #define ALLOW_FUNC(x)   \
5191         { \
5192                 uint32_t arg = (x); \
5193                 bp->pf->vf_req_fwd[((arg) >> 5)] &= \
5194                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
5195         }
5196
5197         /* Forward all requests if firmware is new enough */
5198         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
5199              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
5200             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
5201                 memset(bp->pf->vf_req_fwd, 0xff, sizeof(bp->pf->vf_req_fwd));
5202         } else {
5203                 PMD_DRV_LOG(WARNING,
5204                             "Firmware too old for VF mailbox functionality\n");
5205                 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5206         }
5207
5208         /*
5209          * The following are used for driver cleanup. If we disallow these,
5210          * VF drivers can't clean up cleanly.
5211          */
5212         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
5213         ALLOW_FUNC(HWRM_VNIC_FREE);
5214         ALLOW_FUNC(HWRM_RING_FREE);
5215         ALLOW_FUNC(HWRM_RING_GRP_FREE);
5216         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
5217         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
5218         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
5219         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
5220         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
5221 }
5222
5223 uint16_t
5224 bnxt_get_svif(uint16_t port_id, bool func_svif,
5225               enum bnxt_ulp_intf_type type)
5226 {
5227         struct rte_eth_dev *eth_dev;
5228         struct bnxt *bp;
5229
5230         eth_dev = &rte_eth_devices[port_id];
5231         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5232                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5233                 if (!vfr)
5234                         return 0;
5235
5236                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5237                         return vfr->svif;
5238
5239                 eth_dev = vfr->parent_dev;
5240         }
5241
5242         bp = eth_dev->data->dev_private;
5243
5244         return func_svif ? bp->func_svif : bp->port_svif;
5245 }
5246
5247 uint16_t
5248 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5249 {
5250         struct rte_eth_dev *eth_dev;
5251         struct bnxt_vnic_info *vnic;
5252         struct bnxt *bp;
5253
5254         eth_dev = &rte_eth_devices[port];
5255         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5256                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5257                 if (!vfr)
5258                         return 0;
5259
5260                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5261                         return vfr->dflt_vnic_id;
5262
5263                 eth_dev = vfr->parent_dev;
5264         }
5265
5266         bp = eth_dev->data->dev_private;
5267
5268         vnic = BNXT_GET_DEFAULT_VNIC(bp);
5269
5270         return vnic->fw_vnic_id;
5271 }
5272
5273 uint16_t
5274 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5275 {
5276         struct rte_eth_dev *eth_dev;
5277         struct bnxt *bp;
5278
5279         eth_dev = &rte_eth_devices[port];
5280         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5281                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5282                 if (!vfr)
5283                         return 0;
5284
5285                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5286                         return vfr->fw_fid;
5287
5288                 eth_dev = vfr->parent_dev;
5289         }
5290
5291         bp = eth_dev->data->dev_private;
5292
5293         return bp->fw_fid;
5294 }
5295
5296 enum bnxt_ulp_intf_type
5297 bnxt_get_interface_type(uint16_t port)
5298 {
5299         struct rte_eth_dev *eth_dev;
5300         struct bnxt *bp;
5301
5302         eth_dev = &rte_eth_devices[port];
5303         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5304                 return BNXT_ULP_INTF_TYPE_VF_REP;
5305
5306         bp = eth_dev->data->dev_private;
5307         if (BNXT_PF(bp))
5308                 return BNXT_ULP_INTF_TYPE_PF;
5309         else if (BNXT_VF_IS_TRUSTED(bp))
5310                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5311         else if (BNXT_VF(bp))
5312                 return BNXT_ULP_INTF_TYPE_VF;
5313
5314         return BNXT_ULP_INTF_TYPE_INVALID;
5315 }
5316
5317 uint16_t
5318 bnxt_get_phy_port_id(uint16_t port_id)
5319 {
5320         struct bnxt_representor *vfr;
5321         struct rte_eth_dev *eth_dev;
5322         struct bnxt *bp;
5323
5324         eth_dev = &rte_eth_devices[port_id];
5325         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5326                 vfr = eth_dev->data->dev_private;
5327                 if (!vfr)
5328                         return 0;
5329
5330                 eth_dev = vfr->parent_dev;
5331         }
5332
5333         bp = eth_dev->data->dev_private;
5334
5335         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5336 }
5337
5338 uint16_t
5339 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5340 {
5341         struct rte_eth_dev *eth_dev;
5342         struct bnxt *bp;
5343
5344         eth_dev = &rte_eth_devices[port_id];
5345         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5346                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5347                 if (!vfr)
5348                         return 0;
5349
5350                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5351                         return vfr->fw_fid - 1;
5352
5353                 eth_dev = vfr->parent_dev;
5354         }
5355
5356         bp = eth_dev->data->dev_private;
5357
5358         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5359 }
5360
5361 uint16_t
5362 bnxt_get_vport(uint16_t port_id)
5363 {
5364         return (1 << bnxt_get_phy_port_id(port_id));
5365 }
5366
5367 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5368 {
5369         struct bnxt_error_recovery_info *info = bp->recovery_info;
5370
5371         if (info) {
5372                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5373                         memset(info, 0, sizeof(*info));
5374                 return;
5375         }
5376
5377         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5378                 return;
5379
5380         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5381                            sizeof(*info), 0);
5382         if (!info)
5383                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5384
5385         bp->recovery_info = info;
5386 }
5387
5388 static void bnxt_check_fw_status(struct bnxt *bp)
5389 {
5390         uint32_t fw_status;
5391
5392         if (!(bp->recovery_info &&
5393               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5394                 return;
5395
5396         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5397         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5398                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5399                             fw_status);
5400 }
5401
5402 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5403 {
5404         struct bnxt_error_recovery_info *info = bp->recovery_info;
5405         uint32_t status_loc;
5406         uint32_t sig_ver;
5407
5408         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5409                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5410         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5411                                    BNXT_GRCP_WINDOW_2_BASE +
5412                                    offsetof(struct hcomm_status,
5413                                             sig_ver)));
5414         /* If the signature is absent, then FW does not support this feature */
5415         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5416             HCOMM_STATUS_SIGNATURE_VAL)
5417                 return 0;
5418
5419         if (!info) {
5420                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5421                                    sizeof(*info), 0);
5422                 if (!info)
5423                         return -ENOMEM;
5424                 bp->recovery_info = info;
5425         } else {
5426                 memset(info, 0, sizeof(*info));
5427         }
5428
5429         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5430                                       BNXT_GRCP_WINDOW_2_BASE +
5431                                       offsetof(struct hcomm_status,
5432                                                fw_status_loc)));
5433
5434         /* Only pre-map the FW health status GRC register */
5435         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5436                 return 0;
5437
5438         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5439         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5440                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5441
5442         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5443                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5444
5445         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5446
5447         return 0;
5448 }
5449
5450 static int bnxt_init_fw(struct bnxt *bp)
5451 {
5452         uint16_t mtu;
5453         int rc = 0;
5454
5455         bp->fw_cap = 0;
5456
5457         rc = bnxt_map_hcomm_fw_status_reg(bp);
5458         if (rc)
5459                 return rc;
5460
5461         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5462         if (rc) {
5463                 bnxt_check_fw_status(bp);
5464                 return rc;
5465         }
5466
5467         rc = bnxt_hwrm_func_reset(bp);
5468         if (rc)
5469                 return -EIO;
5470
5471         rc = bnxt_hwrm_vnic_qcaps(bp);
5472         if (rc)
5473                 return rc;
5474
5475         rc = bnxt_hwrm_queue_qportcfg(bp);
5476         if (rc)
5477                 return rc;
5478
5479         /* Get the MAX capabilities for this function.
5480          * This function also allocates context memory for TQM rings and
5481          * informs the firmware about this allocated backing store memory.
5482          */
5483         rc = bnxt_hwrm_func_qcaps(bp);
5484         if (rc)
5485                 return rc;
5486
5487         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5488         if (rc)
5489                 return rc;
5490
5491         bnxt_hwrm_port_mac_qcfg(bp);
5492
5493         bnxt_hwrm_parent_pf_qcfg(bp);
5494
5495         bnxt_hwrm_port_phy_qcaps(bp);
5496
5497         bnxt_alloc_error_recovery_info(bp);
5498         /* Get the adapter error recovery support info */
5499         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5500         if (rc)
5501                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5502
5503         bnxt_hwrm_port_led_qcaps(bp);
5504
5505         return 0;
5506 }
5507
5508 static int
5509 bnxt_init_locks(struct bnxt *bp)
5510 {
5511         int err;
5512
5513         err = pthread_mutex_init(&bp->flow_lock, NULL);
5514         if (err) {
5515                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5516                 return err;
5517         }
5518
5519         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5520         if (err)
5521                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5522
5523         err = pthread_mutex_init(&bp->health_check_lock, NULL);
5524         if (err)
5525                 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5526         return err;
5527 }
5528
5529 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5530 {
5531         int rc = 0;
5532
5533         rc = bnxt_init_fw(bp);
5534         if (rc)
5535                 return rc;
5536
5537         if (!reconfig_dev) {
5538                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5539                 if (rc)
5540                         return rc;
5541         } else {
5542                 rc = bnxt_restore_dflt_mac(bp);
5543                 if (rc)
5544                         return rc;
5545         }
5546
5547         bnxt_config_vf_req_fwd(bp);
5548
5549         rc = bnxt_hwrm_func_driver_register(bp);
5550         if (rc) {
5551                 PMD_DRV_LOG(ERR, "Failed to register driver");
5552                 return -EBUSY;
5553         }
5554
5555         if (BNXT_PF(bp)) {
5556                 if (bp->pdev->max_vfs) {
5557                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5558                         if (rc) {
5559                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5560                                 return rc;
5561                         }
5562                 } else {
5563                         rc = bnxt_hwrm_allocate_pf_only(bp);
5564                         if (rc) {
5565                                 PMD_DRV_LOG(ERR,
5566                                             "Failed to allocate PF resources");
5567                                 return rc;
5568                         }
5569                 }
5570         }
5571
5572         rc = bnxt_alloc_mem(bp, reconfig_dev);
5573         if (rc)
5574                 return rc;
5575
5576         rc = bnxt_setup_int(bp);
5577         if (rc)
5578                 return rc;
5579
5580         rc = bnxt_request_int(bp);
5581         if (rc)
5582                 return rc;
5583
5584         rc = bnxt_init_ctx_mem(bp);
5585         if (rc) {
5586                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5587                 return rc;
5588         }
5589
5590         rc = bnxt_init_locks(bp);
5591         if (rc)
5592                 return rc;
5593
5594         return 0;
5595 }
5596
5597 static int
5598 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5599                           const char *value, void *opaque_arg)
5600 {
5601         struct bnxt *bp = opaque_arg;
5602         unsigned long truflow;
5603         char *end = NULL;
5604
5605         if (!value || !opaque_arg) {
5606                 PMD_DRV_LOG(ERR,
5607                             "Invalid parameter passed to truflow devargs.\n");
5608                 return -EINVAL;
5609         }
5610
5611         truflow = strtoul(value, &end, 10);
5612         if (end == NULL || *end != '\0' ||
5613             (truflow == ULONG_MAX && errno == ERANGE)) {
5614                 PMD_DRV_LOG(ERR,
5615                             "Invalid parameter passed to truflow devargs.\n");
5616                 return -EINVAL;
5617         }
5618
5619         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5620                 PMD_DRV_LOG(ERR,
5621                             "Invalid value passed to truflow devargs.\n");
5622                 return -EINVAL;
5623         }
5624
5625         if (truflow) {
5626                 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5627                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5628         } else {
5629                 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
5630                 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
5631         }
5632
5633         return 0;
5634 }
5635
5636 static int
5637 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5638                              const char *value, void *opaque_arg)
5639 {
5640         struct bnxt *bp = opaque_arg;
5641         unsigned long flow_xstat;
5642         char *end = NULL;
5643
5644         if (!value || !opaque_arg) {
5645                 PMD_DRV_LOG(ERR,
5646                             "Invalid parameter passed to flow_xstat devarg.\n");
5647                 return -EINVAL;
5648         }
5649
5650         flow_xstat = strtoul(value, &end, 10);
5651         if (end == NULL || *end != '\0' ||
5652             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5653                 PMD_DRV_LOG(ERR,
5654                             "Invalid parameter passed to flow_xstat devarg.\n");
5655                 return -EINVAL;
5656         }
5657
5658         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5659                 PMD_DRV_LOG(ERR,
5660                             "Invalid value passed to flow_xstat devarg.\n");
5661                 return -EINVAL;
5662         }
5663
5664         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5665         if (BNXT_FLOW_XSTATS_EN(bp))
5666                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5667
5668         return 0;
5669 }
5670
5671 static int
5672 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5673                                         const char *value, void *opaque_arg)
5674 {
5675         struct bnxt *bp = opaque_arg;
5676         unsigned long max_num_kflows;
5677         char *end = NULL;
5678
5679         if (!value || !opaque_arg) {
5680                 PMD_DRV_LOG(ERR,
5681                         "Invalid parameter passed to max_num_kflows devarg.\n");
5682                 return -EINVAL;
5683         }
5684
5685         max_num_kflows = strtoul(value, &end, 10);
5686         if (end == NULL || *end != '\0' ||
5687                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5688                 PMD_DRV_LOG(ERR,
5689                         "Invalid parameter passed to max_num_kflows devarg.\n");
5690                 return -EINVAL;
5691         }
5692
5693         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5694                 PMD_DRV_LOG(ERR,
5695                         "Invalid value passed to max_num_kflows devarg.\n");
5696                 return -EINVAL;
5697         }
5698
5699         bp->max_num_kflows = max_num_kflows;
5700         if (bp->max_num_kflows)
5701                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5702                                 max_num_kflows);
5703
5704         return 0;
5705 }
5706
5707 static int
5708 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5709                             const char *value, void *opaque_arg)
5710 {
5711         struct bnxt_representor *vfr_bp = opaque_arg;
5712         unsigned long rep_is_pf;
5713         char *end = NULL;
5714
5715         if (!value || !opaque_arg) {
5716                 PMD_DRV_LOG(ERR,
5717                             "Invalid parameter passed to rep_is_pf devargs.\n");
5718                 return -EINVAL;
5719         }
5720
5721         rep_is_pf = strtoul(value, &end, 10);
5722         if (end == NULL || *end != '\0' ||
5723             (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5724                 PMD_DRV_LOG(ERR,
5725                             "Invalid parameter passed to rep_is_pf devargs.\n");
5726                 return -EINVAL;
5727         }
5728
5729         if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5730                 PMD_DRV_LOG(ERR,
5731                             "Invalid value passed to rep_is_pf devargs.\n");
5732                 return -EINVAL;
5733         }
5734
5735         vfr_bp->flags |= rep_is_pf;
5736         if (BNXT_REP_PF(vfr_bp))
5737                 PMD_DRV_LOG(INFO, "PF representor\n");
5738         else
5739                 PMD_DRV_LOG(INFO, "VF representor\n");
5740
5741         return 0;
5742 }
5743
5744 static int
5745 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5746                                const char *value, void *opaque_arg)
5747 {
5748         struct bnxt_representor *vfr_bp = opaque_arg;
5749         unsigned long rep_based_pf;
5750         char *end = NULL;
5751
5752         if (!value || !opaque_arg) {
5753                 PMD_DRV_LOG(ERR,
5754                             "Invalid parameter passed to rep_based_pf "
5755                             "devargs.\n");
5756                 return -EINVAL;
5757         }
5758
5759         rep_based_pf = strtoul(value, &end, 10);
5760         if (end == NULL || *end != '\0' ||
5761             (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5762                 PMD_DRV_LOG(ERR,
5763                             "Invalid parameter passed to rep_based_pf "
5764                             "devargs.\n");
5765                 return -EINVAL;
5766         }
5767
5768         if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5769                 PMD_DRV_LOG(ERR,
5770                             "Invalid value passed to rep_based_pf devargs.\n");
5771                 return -EINVAL;
5772         }
5773
5774         vfr_bp->rep_based_pf = rep_based_pf;
5775         PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5776
5777         return 0;
5778 }
5779
5780 static int
5781 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5782                             const char *value, void *opaque_arg)
5783 {
5784         struct bnxt_representor *vfr_bp = opaque_arg;
5785         unsigned long rep_q_r2f;
5786         char *end = NULL;
5787
5788         if (!value || !opaque_arg) {
5789                 PMD_DRV_LOG(ERR,
5790                             "Invalid parameter passed to rep_q_r2f "
5791                             "devargs.\n");
5792                 return -EINVAL;
5793         }
5794
5795         rep_q_r2f = strtoul(value, &end, 10);
5796         if (end == NULL || *end != '\0' ||
5797             (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5798                 PMD_DRV_LOG(ERR,
5799                             "Invalid parameter passed to rep_q_r2f "
5800                             "devargs.\n");
5801                 return -EINVAL;
5802         }
5803
5804         if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5805                 PMD_DRV_LOG(ERR,
5806                             "Invalid value passed to rep_q_r2f devargs.\n");
5807                 return -EINVAL;
5808         }
5809
5810         vfr_bp->rep_q_r2f = rep_q_r2f;
5811         vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5812         PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5813
5814         return 0;
5815 }
5816
5817 static int
5818 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5819                             const char *value, void *opaque_arg)
5820 {
5821         struct bnxt_representor *vfr_bp = opaque_arg;
5822         unsigned long rep_q_f2r;
5823         char *end = NULL;
5824
5825         if (!value || !opaque_arg) {
5826                 PMD_DRV_LOG(ERR,
5827                             "Invalid parameter passed to rep_q_f2r "
5828                             "devargs.\n");
5829                 return -EINVAL;
5830         }
5831
5832         rep_q_f2r = strtoul(value, &end, 10);
5833         if (end == NULL || *end != '\0' ||
5834             (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5835                 PMD_DRV_LOG(ERR,
5836                             "Invalid parameter passed to rep_q_f2r "
5837                             "devargs.\n");
5838                 return -EINVAL;
5839         }
5840
5841         if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5842                 PMD_DRV_LOG(ERR,
5843                             "Invalid value passed to rep_q_f2r devargs.\n");
5844                 return -EINVAL;
5845         }
5846
5847         vfr_bp->rep_q_f2r = rep_q_f2r;
5848         vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5849         PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5850
5851         return 0;
5852 }
5853
5854 static int
5855 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5856                              const char *value, void *opaque_arg)
5857 {
5858         struct bnxt_representor *vfr_bp = opaque_arg;
5859         unsigned long rep_fc_r2f;
5860         char *end = NULL;
5861
5862         if (!value || !opaque_arg) {
5863                 PMD_DRV_LOG(ERR,
5864                             "Invalid parameter passed to rep_fc_r2f "
5865                             "devargs.\n");
5866                 return -EINVAL;
5867         }
5868
5869         rep_fc_r2f = strtoul(value, &end, 10);
5870         if (end == NULL || *end != '\0' ||
5871             (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5872                 PMD_DRV_LOG(ERR,
5873                             "Invalid parameter passed to rep_fc_r2f "
5874                             "devargs.\n");
5875                 return -EINVAL;
5876         }
5877
5878         if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5879                 PMD_DRV_LOG(ERR,
5880                             "Invalid value passed to rep_fc_r2f devargs.\n");
5881                 return -EINVAL;
5882         }
5883
5884         vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5885         vfr_bp->rep_fc_r2f = rep_fc_r2f;
5886         PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5887
5888         return 0;
5889 }
5890
5891 static int
5892 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5893                              const char *value, void *opaque_arg)
5894 {
5895         struct bnxt_representor *vfr_bp = opaque_arg;
5896         unsigned long rep_fc_f2r;
5897         char *end = NULL;
5898
5899         if (!value || !opaque_arg) {
5900                 PMD_DRV_LOG(ERR,
5901                             "Invalid parameter passed to rep_fc_f2r "
5902                             "devargs.\n");
5903                 return -EINVAL;
5904         }
5905
5906         rep_fc_f2r = strtoul(value, &end, 10);
5907         if (end == NULL || *end != '\0' ||
5908             (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5909                 PMD_DRV_LOG(ERR,
5910                             "Invalid parameter passed to rep_fc_f2r "
5911                             "devargs.\n");
5912                 return -EINVAL;
5913         }
5914
5915         if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5916                 PMD_DRV_LOG(ERR,
5917                             "Invalid value passed to rep_fc_f2r devargs.\n");
5918                 return -EINVAL;
5919         }
5920
5921         vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5922         vfr_bp->rep_fc_f2r = rep_fc_f2r;
5923         PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5924
5925         return 0;
5926 }
5927
5928 static void
5929 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5930 {
5931         struct rte_kvargs *kvlist;
5932
5933         if (devargs == NULL)
5934                 return;
5935
5936         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5937         if (kvlist == NULL)
5938                 return;
5939
5940         /*
5941          * Handler for "truflow" devarg.
5942          * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1"
5943          */
5944         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5945                            bnxt_parse_devarg_truflow, bp);
5946
5947         /*
5948          * Handler for "flow_xstat" devarg.
5949          * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1"
5950          */
5951         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5952                            bnxt_parse_devarg_flow_xstat, bp);
5953
5954         /*
5955          * Handler for "max_num_kflows" devarg.
5956          * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32"
5957          */
5958         rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5959                            bnxt_parse_devarg_max_num_kflows, bp);
5960
5961         rte_kvargs_free(kvlist);
5962 }
5963
5964 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5965 {
5966         int rc = 0;
5967
5968         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5969                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5970                 if (rc)
5971                         PMD_DRV_LOG(ERR,
5972                                     "Failed to alloc switch domain: %d\n", rc);
5973                 else
5974                         PMD_DRV_LOG(INFO,
5975                                     "Switch domain allocated %d\n",
5976                                     bp->switch_domain_id);
5977         }
5978
5979         return rc;
5980 }
5981
5982 static int
5983 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5984 {
5985         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5986         static int version_printed;
5987         struct bnxt *bp;
5988         int rc;
5989
5990         if (version_printed++ == 0)
5991                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5992
5993         eth_dev->dev_ops = &bnxt_dev_ops;
5994         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5995         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5996         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5997         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5998         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5999
6000         /*
6001          * For secondary processes, we don't initialise any further
6002          * as primary has already done this work.
6003          */
6004         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6005                 return 0;
6006
6007         rte_eth_copy_pci_info(eth_dev, pci_dev);
6008
6009         bp = eth_dev->data->dev_private;
6010
6011         /* Parse dev arguments passed on when starting the DPDK application. */
6012         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
6013
6014         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
6015
6016         if (bnxt_vf_pciid(pci_dev->id.device_id))
6017                 bp->flags |= BNXT_FLAG_VF;
6018
6019         if (bnxt_thor_device(pci_dev->id.device_id))
6020                 bp->flags |= BNXT_FLAG_THOR_CHIP;
6021
6022         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
6023             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
6024             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
6025             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
6026                 bp->flags |= BNXT_FLAG_STINGRAY;
6027
6028         rc = bnxt_init_board(eth_dev);
6029         if (rc) {
6030                 PMD_DRV_LOG(ERR,
6031                             "Failed to initialize board rc: %x\n", rc);
6032                 return rc;
6033         }
6034
6035         rc = bnxt_alloc_pf_info(bp);
6036         if (rc)
6037                 goto error_free;
6038
6039         rc = bnxt_alloc_link_info(bp);
6040         if (rc)
6041                 goto error_free;
6042
6043         rc = bnxt_alloc_parent_info(bp);
6044         if (rc)
6045                 goto error_free;
6046
6047         rc = bnxt_alloc_hwrm_resources(bp);
6048         if (rc) {
6049                 PMD_DRV_LOG(ERR,
6050                             "Failed to allocate hwrm resource rc: %x\n", rc);
6051                 goto error_free;
6052         }
6053         rc = bnxt_alloc_leds_info(bp);
6054         if (rc)
6055                 goto error_free;
6056
6057         rc = bnxt_alloc_cos_queues(bp);
6058         if (rc)
6059                 goto error_free;
6060
6061         rc = bnxt_init_resources(bp, false);
6062         if (rc)
6063                 goto error_free;
6064
6065         rc = bnxt_alloc_stats_mem(bp);
6066         if (rc)
6067                 goto error_free;
6068
6069         bnxt_alloc_switch_domain(bp);
6070
6071         /* Pass the information to the rte_eth_dev_close() that it should also
6072          * release the private port resources.
6073          */
6074         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
6075
6076         PMD_DRV_LOG(INFO,
6077                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
6078                     pci_dev->mem_resource[0].phys_addr,
6079                     pci_dev->mem_resource[0].addr);
6080
6081         return 0;
6082
6083 error_free:
6084         bnxt_dev_uninit(eth_dev);
6085         return rc;
6086 }
6087
6088
6089 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
6090 {
6091         if (!ctx)
6092                 return;
6093
6094         if (ctx->va)
6095                 rte_free(ctx->va);
6096
6097         ctx->va = NULL;
6098         ctx->dma = RTE_BAD_IOVA;
6099         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
6100 }
6101
6102 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
6103 {
6104         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
6105                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6106                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
6107                                   bp->flow_stat->max_fc,
6108                                   false);
6109
6110         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
6111                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6112                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
6113                                   bp->flow_stat->max_fc,
6114                                   false);
6115
6116         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6117                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
6118         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6119
6120         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6121                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
6122         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6123
6124         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6125                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
6126         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6127
6128         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6129                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
6130         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6131 }
6132
6133 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
6134 {
6135         bnxt_unregister_fc_ctx_mem(bp);
6136
6137         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
6138         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
6139         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
6140         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
6141 }
6142
6143 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
6144 {
6145         if (BNXT_FLOW_XSTATS_EN(bp))
6146                 bnxt_uninit_fc_ctx_mem(bp);
6147 }
6148
6149 static void
6150 bnxt_free_error_recovery_info(struct bnxt *bp)
6151 {
6152         rte_free(bp->recovery_info);
6153         bp->recovery_info = NULL;
6154         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
6155 }
6156
6157 static void
6158 bnxt_uninit_locks(struct bnxt *bp)
6159 {
6160         pthread_mutex_destroy(&bp->flow_lock);
6161         pthread_mutex_destroy(&bp->def_cp_lock);
6162         pthread_mutex_destroy(&bp->health_check_lock);
6163         if (bp->rep_info) {
6164                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
6165                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
6166         }
6167 }
6168
6169 static int
6170 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
6171 {
6172         int rc;
6173
6174         bnxt_free_int(bp);
6175         bnxt_free_mem(bp, reconfig_dev);
6176         bnxt_hwrm_func_buf_unrgtr(bp);
6177         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
6178         bp->flags &= ~BNXT_FLAG_REGISTERED;
6179         bnxt_free_ctx_mem(bp);
6180         if (!reconfig_dev) {
6181                 bnxt_free_hwrm_resources(bp);
6182                 bnxt_free_error_recovery_info(bp);
6183         }
6184
6185         bnxt_uninit_ctx_mem(bp);
6186
6187         bnxt_uninit_locks(bp);
6188         bnxt_free_flow_stats_info(bp);
6189         bnxt_free_rep_info(bp);
6190         rte_free(bp->ptp_cfg);
6191         bp->ptp_cfg = NULL;
6192         return rc;
6193 }
6194
6195 static int
6196 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
6197 {
6198         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6199                 return -EPERM;
6200
6201         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
6202
6203         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
6204                 bnxt_dev_close_op(eth_dev);
6205
6206         return 0;
6207 }
6208
6209 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
6210 {
6211         struct bnxt *bp = eth_dev->data->dev_private;
6212         struct rte_eth_dev *vf_rep_eth_dev;
6213         int ret = 0, i;
6214
6215         if (!bp)
6216                 return -EINVAL;
6217
6218         for (i = 0; i < bp->num_reps; i++) {
6219                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
6220                 if (!vf_rep_eth_dev)
6221                         continue;
6222                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
6223                             vf_rep_eth_dev->data->port_id);
6224                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
6225         }
6226         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
6227                     eth_dev->data->port_id);
6228         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
6229
6230         return ret;
6231 }
6232
6233 static void bnxt_free_rep_info(struct bnxt *bp)
6234 {
6235         rte_free(bp->rep_info);
6236         bp->rep_info = NULL;
6237         rte_free(bp->cfa_code_map);
6238         bp->cfa_code_map = NULL;
6239 }
6240
6241 static int bnxt_init_rep_info(struct bnxt *bp)
6242 {
6243         int i = 0, rc;
6244
6245         if (bp->rep_info)
6246                 return 0;
6247
6248         bp->rep_info = rte_zmalloc("bnxt_rep_info",
6249                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
6250                                    0);
6251         if (!bp->rep_info) {
6252                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
6253                 return -ENOMEM;
6254         }
6255         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
6256                                        sizeof(*bp->cfa_code_map) *
6257                                        BNXT_MAX_CFA_CODE, 0);
6258         if (!bp->cfa_code_map) {
6259                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
6260                 bnxt_free_rep_info(bp);
6261                 return -ENOMEM;
6262         }
6263
6264         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
6265                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
6266
6267         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
6268         if (rc) {
6269                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
6270                 bnxt_free_rep_info(bp);
6271                 return rc;
6272         }
6273
6274         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
6275         if (rc) {
6276                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
6277                 bnxt_free_rep_info(bp);
6278                 return rc;
6279         }
6280
6281         return rc;
6282 }
6283
6284 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
6285                                struct rte_eth_devargs eth_da,
6286                                struct rte_eth_dev *backing_eth_dev,
6287                                const char *dev_args)
6288 {
6289         struct rte_eth_dev *vf_rep_eth_dev;
6290         char name[RTE_ETH_NAME_MAX_LEN];
6291         struct bnxt *backing_bp;
6292         uint16_t num_rep;
6293         int i, ret = 0;
6294         struct rte_kvargs *kvlist;
6295
6296         num_rep = eth_da.nb_representor_ports;
6297         if (num_rep > BNXT_MAX_VF_REPS) {
6298                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
6299                             num_rep, BNXT_MAX_VF_REPS);
6300                 return -EINVAL;
6301         }
6302
6303         if (num_rep >= RTE_MAX_ETHPORTS) {
6304                 PMD_DRV_LOG(ERR,
6305                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6306                             num_rep, RTE_MAX_ETHPORTS);
6307                 return -EINVAL;
6308         }
6309
6310         backing_bp = backing_eth_dev->data->dev_private;
6311
6312         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6313                 PMD_DRV_LOG(ERR,
6314                             "Not a PF or trusted VF. No Representor support\n");
6315                 /* Returning an error is not an option.
6316                  * Applications are not handling this correctly
6317                  */
6318                 return 0;
6319         }
6320
6321         if (bnxt_init_rep_info(backing_bp))
6322                 return 0;
6323
6324         for (i = 0; i < num_rep; i++) {
6325                 struct bnxt_representor representor = {
6326                         .vf_id = eth_da.representor_ports[i],
6327                         .switch_domain_id = backing_bp->switch_domain_id,
6328                         .parent_dev = backing_eth_dev
6329                 };
6330
6331                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6332                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6333                                     representor.vf_id, BNXT_MAX_VF_REPS);
6334                         continue;
6335                 }
6336
6337                 /* representor port net_bdf_port */
6338                 snprintf(name, sizeof(name), "net_%s_representor_%d",
6339                          pci_dev->device.name, eth_da.representor_ports[i]);
6340
6341                 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
6342                 if (kvlist) {
6343                         /*
6344                          * Handler for "rep_is_pf" devarg.
6345                          * Invoked as for ex: "-w 000:00:0d.0,
6346                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6347                          */
6348                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
6349                                            bnxt_parse_devarg_rep_is_pf,
6350                                            (void *)&representor);
6351                         /*
6352                          * Handler for "rep_based_pf" devarg.
6353                          * Invoked as for ex: "-w 000:00:0d.0,
6354                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6355                          */
6356                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_BASED_PF,
6357                                            bnxt_parse_devarg_rep_based_pf,
6358                                            (void *)&representor);
6359                         /*
6360                          * Handler for "rep_based_pf" devarg.
6361                          * Invoked as for ex: "-w 000:00:0d.0,
6362                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6363                          */
6364                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
6365                                            bnxt_parse_devarg_rep_q_r2f,
6366                                            (void *)&representor);
6367                         /*
6368                          * Handler for "rep_based_pf" devarg.
6369                          * Invoked as for ex: "-w 000:00:0d.0,
6370                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6371                          */
6372                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
6373                                            bnxt_parse_devarg_rep_q_f2r,
6374                                            (void *)&representor);
6375                         /*
6376                          * Handler for "rep_based_pf" devarg.
6377                          * Invoked as for ex: "-w 000:00:0d.0,
6378                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6379                          */
6380                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
6381                                            bnxt_parse_devarg_rep_fc_r2f,
6382                                            (void *)&representor);
6383                         /*
6384                          * Handler for "rep_based_pf" devarg.
6385                          * Invoked as for ex: "-w 000:00:0d.0,
6386                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6387                          */
6388                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
6389                                            bnxt_parse_devarg_rep_fc_f2r,
6390                                            (void *)&representor);
6391                 }
6392
6393                 ret = rte_eth_dev_create(&pci_dev->device, name,
6394                                          sizeof(struct bnxt_representor),
6395                                          NULL, NULL,
6396                                          bnxt_representor_init,
6397                                          &representor);
6398                 if (ret) {
6399                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6400                                     "representor %s.", name);
6401                         goto err;
6402                 }
6403
6404                 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6405                 if (!vf_rep_eth_dev) {
6406                         PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6407                                     " for VF-Rep: %s.", name);
6408                         ret = -ENODEV;
6409                         goto err;
6410                 }
6411
6412                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6413                             backing_eth_dev->data->port_id);
6414                 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6415                                                          vf_rep_eth_dev;
6416                 backing_bp->num_reps++;
6417
6418         }
6419
6420         return 0;
6421
6422 err:
6423         /* If num_rep > 1, then rollback already created
6424          * ports, since we'll be failing the probe anyway
6425          */
6426         if (num_rep > 1)
6427                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6428
6429         return ret;
6430 }
6431
6432 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6433                           struct rte_pci_device *pci_dev)
6434 {
6435         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6436         struct rte_eth_dev *backing_eth_dev;
6437         uint16_t num_rep;
6438         int ret = 0;
6439
6440         if (pci_dev->device.devargs) {
6441                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6442                                             &eth_da);
6443                 if (ret)
6444                         return ret;
6445         }
6446
6447         num_rep = eth_da.nb_representor_ports;
6448         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6449                     num_rep);
6450
6451         /* We could come here after first level of probe is already invoked
6452          * as part of an application bringup(OVS-DPDK vswitchd), so first check
6453          * for already allocated eth_dev for the backing device (PF/Trusted VF)
6454          */
6455         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6456         if (backing_eth_dev == NULL) {
6457                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6458                                          sizeof(struct bnxt),
6459                                          eth_dev_pci_specific_init, pci_dev,
6460                                          bnxt_dev_init, NULL);
6461
6462                 if (ret || !num_rep)
6463                         return ret;
6464
6465                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6466         }
6467         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6468                     backing_eth_dev->data->port_id);
6469         /* probe representor ports now */
6470         ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev,
6471                                   pci_dev->device.devargs->args);
6472
6473         return ret;
6474 }
6475
6476 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6477 {
6478         struct rte_eth_dev *eth_dev;
6479
6480         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6481         if (!eth_dev)
6482                 return 0; /* Invoked typically only by OVS-DPDK, by the
6483                            * time it comes here the eth_dev is already
6484                            * deleted by rte_eth_dev_close(), so returning
6485                            * +ve value will at least help in proper cleanup
6486                            */
6487
6488         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6489         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6490                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6491                         return rte_eth_dev_destroy(eth_dev,
6492                                                    bnxt_representor_uninit);
6493                 else
6494                         return rte_eth_dev_destroy(eth_dev,
6495                                                    bnxt_dev_uninit);
6496         } else {
6497                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6498         }
6499 }
6500
6501 static struct rte_pci_driver bnxt_rte_pmd = {
6502         .id_table = bnxt_pci_id_map,
6503         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6504                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6505                                                   * and OVS-DPDK
6506                                                   */
6507         .probe = bnxt_pci_probe,
6508         .remove = bnxt_pci_remove,
6509 };
6510
6511 static bool
6512 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6513 {
6514         if (strcmp(dev->device->driver->name, drv->driver.name))
6515                 return false;
6516
6517         return true;
6518 }
6519
6520 bool is_bnxt_supported(struct rte_eth_dev *dev)
6521 {
6522         return is_device_supported(dev, &bnxt_rte_pmd);
6523 }
6524
6525 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
6526 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6527 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6528 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");