1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2021 Broadcom
10 #include <ethdev_driver.h>
11 #include <ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
15 #include <rte_kvargs.h>
19 #include "bnxt_filter.h"
20 #include "bnxt_hwrm.h"
22 #include "bnxt_reps.h"
23 #include "bnxt_ring.h"
26 #include "bnxt_stats.h"
29 #include "bnxt_vnic.h"
30 #include "hsi_struct_def_dpdk.h"
31 #include "bnxt_nvm_defs.h"
32 #include "bnxt_tf_common.h"
33 #include "ulp_flow_db.h"
34 #include "rte_pmd_bnxt.h"
36 #define DRV_MODULE_NAME "bnxt"
37 static const char bnxt_version[] =
38 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
41 * The set of PCI devices this driver supports
43 static const struct rte_pci_id bnxt_pci_id_map[] = {
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
45 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
47 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
87 { .vendor_id = 0, /* sentinel */ },
90 #define BNXT_DEVARG_TRUFLOW "host-based-truflow"
91 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat"
92 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows"
93 #define BNXT_DEVARG_REPRESENTOR "representor"
94 #define BNXT_DEVARG_REP_BASED_PF "rep-based-pf"
95 #define BNXT_DEVARG_REP_IS_PF "rep-is-pf"
96 #define BNXT_DEVARG_REP_Q_R2F "rep-q-r2f"
97 #define BNXT_DEVARG_REP_Q_F2R "rep-q-f2r"
98 #define BNXT_DEVARG_REP_FC_R2F "rep-fc-r2f"
99 #define BNXT_DEVARG_REP_FC_F2R "rep-fc-f2r"
101 static const char *const bnxt_dev_args[] = {
102 BNXT_DEVARG_REPRESENTOR,
104 BNXT_DEVARG_FLOW_XSTAT,
105 BNXT_DEVARG_MAX_NUM_KFLOWS,
106 BNXT_DEVARG_REP_BASED_PF,
107 BNXT_DEVARG_REP_IS_PF,
108 BNXT_DEVARG_REP_Q_R2F,
109 BNXT_DEVARG_REP_Q_F2R,
110 BNXT_DEVARG_REP_FC_R2F,
111 BNXT_DEVARG_REP_FC_F2R,
116 * truflow == false to disable the feature
117 * truflow == true to enable the feature
119 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1)
122 * flow_xstat == false to disable the feature
123 * flow_xstat == true to enable the feature
125 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1)
128 * rep_is_pf == false to indicate VF representor
129 * rep_is_pf == true to indicate PF representor
131 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf) ((rep_is_pf) > 1)
134 * rep_based_pf == Physical index of the PF
136 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf) ((rep_based_pf) > 15)
138 * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
140 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f) ((rep_q_r2f) > 3)
143 * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
145 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r) ((rep_q_f2r) > 3)
148 * rep_fc_r2f == Flow control for the representor to endpoint direction
150 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f) ((rep_fc_r2f) > 1)
153 * rep_fc_f2r == Flow control for the endpoint to representor direction
155 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r) ((rep_fc_f2r) > 1)
157 int bnxt_cfa_code_dynfield_offset = -1;
160 * max_num_kflows must be >= 32
161 * and must be a power-of-2 supported value
162 * return: 1 -> invalid
165 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
167 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
172 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
173 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
174 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
175 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
176 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
177 static int bnxt_restore_vlan_filters(struct bnxt *bp);
178 static void bnxt_dev_recover(void *arg);
179 static void bnxt_free_error_recovery_info(struct bnxt *bp);
180 static void bnxt_free_rep_info(struct bnxt *bp);
182 int is_bnxt_in_error(struct bnxt *bp)
184 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
186 if (bp->flags & BNXT_FLAG_FW_RESET)
192 /***********************/
195 * High level utility functions
198 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
200 unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
201 BNXT_RSS_TBL_SIZE_P5);
203 if (!BNXT_CHIP_P5(bp))
206 return RTE_ALIGN_MUL_CEIL(num_rss_rings,
207 BNXT_RSS_ENTRIES_PER_CTX_P5) /
208 BNXT_RSS_ENTRIES_PER_CTX_P5;
211 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
213 if (!BNXT_CHIP_P5(bp))
214 return HW_HASH_INDEX_SIZE;
216 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
219 static void bnxt_free_parent_info(struct bnxt *bp)
221 rte_free(bp->parent);
224 static void bnxt_free_pf_info(struct bnxt *bp)
229 static void bnxt_free_link_info(struct bnxt *bp)
231 rte_free(bp->link_info);
234 static void bnxt_free_leds_info(struct bnxt *bp)
243 static void bnxt_free_flow_stats_info(struct bnxt *bp)
245 rte_free(bp->flow_stat);
246 bp->flow_stat = NULL;
249 static void bnxt_free_cos_queues(struct bnxt *bp)
251 rte_free(bp->rx_cos_queue);
252 rte_free(bp->tx_cos_queue);
255 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
257 bnxt_free_filter_mem(bp);
258 bnxt_free_vnic_attributes(bp);
259 bnxt_free_vnic_mem(bp);
261 /* tx/rx rings are configured as part of *_queue_setup callbacks.
262 * If the number of rings change across fw update,
263 * we don't have much choice except to warn the user.
267 bnxt_free_tx_rings(bp);
268 bnxt_free_rx_rings(bp);
270 bnxt_free_async_cp_ring(bp);
271 bnxt_free_rxtx_nq_ring(bp);
273 rte_free(bp->grp_info);
277 static int bnxt_alloc_parent_info(struct bnxt *bp)
279 bp->parent = rte_zmalloc("bnxt_parent_info",
280 sizeof(struct bnxt_parent_info), 0);
281 if (bp->parent == NULL)
287 static int bnxt_alloc_pf_info(struct bnxt *bp)
289 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
296 static int bnxt_alloc_link_info(struct bnxt *bp)
299 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
300 if (bp->link_info == NULL)
306 static int bnxt_alloc_leds_info(struct bnxt *bp)
311 bp->leds = rte_zmalloc("bnxt_leds",
312 BNXT_MAX_LED * sizeof(struct bnxt_led_info),
314 if (bp->leds == NULL)
320 static int bnxt_alloc_cos_queues(struct bnxt *bp)
323 rte_zmalloc("bnxt_rx_cosq",
324 BNXT_COS_QUEUE_COUNT *
325 sizeof(struct bnxt_cos_queue_info),
327 if (bp->rx_cos_queue == NULL)
331 rte_zmalloc("bnxt_tx_cosq",
332 BNXT_COS_QUEUE_COUNT *
333 sizeof(struct bnxt_cos_queue_info),
335 if (bp->tx_cos_queue == NULL)
341 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
343 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
344 sizeof(struct bnxt_flow_stat_info), 0);
345 if (bp->flow_stat == NULL)
351 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
355 rc = bnxt_alloc_ring_grps(bp);
359 rc = bnxt_alloc_async_ring_struct(bp);
363 rc = bnxt_alloc_vnic_mem(bp);
367 rc = bnxt_alloc_vnic_attributes(bp);
371 rc = bnxt_alloc_filter_mem(bp);
375 rc = bnxt_alloc_async_cp_ring(bp);
379 rc = bnxt_alloc_rxtx_nq_ring(bp);
383 if (BNXT_FLOW_XSTATS_EN(bp)) {
384 rc = bnxt_alloc_flow_stats_info(bp);
392 bnxt_free_mem(bp, reconfig);
396 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
398 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
399 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
400 uint64_t rx_offloads = dev_conf->rxmode.offloads;
401 struct bnxt_rx_queue *rxq;
405 rc = bnxt_vnic_grp_alloc(bp, vnic);
409 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
410 vnic_id, vnic, vnic->fw_grp_ids);
412 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
416 /* Alloc RSS context only if RSS mode is enabled */
417 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
418 int j, nr_ctxs = bnxt_rss_ctxts(bp);
420 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
421 PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
422 bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
424 "Only queues 0-%d will be in RSS table\n",
425 BNXT_RSS_TBL_SIZE_P5 - 1);
429 for (j = 0; j < nr_ctxs; j++) {
430 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
436 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
440 vnic->num_lb_ctxts = nr_ctxs;
444 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
445 * setting is not available at this time, it will not be
446 * configured correctly in the CFA.
448 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
449 vnic->vlan_strip = true;
451 vnic->vlan_strip = false;
453 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
457 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
461 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
462 rxq = bp->eth_dev->data->rx_queues[j];
465 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
466 j, rxq->vnic, rxq->vnic->fw_grp_ids);
468 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
469 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
471 vnic->rx_queue_cnt++;
474 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
476 rc = bnxt_vnic_rss_configure(bp, vnic);
480 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
482 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
483 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
485 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
489 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
494 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
498 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
499 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
504 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
505 " rx_fc_in_tbl.ctx_id = %d\n",
506 bp->flow_stat->rx_fc_in_tbl.va,
507 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
508 bp->flow_stat->rx_fc_in_tbl.ctx_id);
510 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
511 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
516 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
517 " rx_fc_out_tbl.ctx_id = %d\n",
518 bp->flow_stat->rx_fc_out_tbl.va,
519 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
520 bp->flow_stat->rx_fc_out_tbl.ctx_id);
522 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
523 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
528 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
529 " tx_fc_in_tbl.ctx_id = %d\n",
530 bp->flow_stat->tx_fc_in_tbl.va,
531 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
532 bp->flow_stat->tx_fc_in_tbl.ctx_id);
534 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
535 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
540 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
541 " tx_fc_out_tbl.ctx_id = %d\n",
542 bp->flow_stat->tx_fc_out_tbl.va,
543 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
544 bp->flow_stat->tx_fc_out_tbl.ctx_id);
546 memset(bp->flow_stat->rx_fc_out_tbl.va,
548 bp->flow_stat->rx_fc_out_tbl.size);
549 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
550 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
551 bp->flow_stat->rx_fc_out_tbl.ctx_id,
552 bp->flow_stat->max_fc,
557 memset(bp->flow_stat->tx_fc_out_tbl.va,
559 bp->flow_stat->tx_fc_out_tbl.size);
560 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
561 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
562 bp->flow_stat->tx_fc_out_tbl.ctx_id,
563 bp->flow_stat->max_fc,
569 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
570 struct bnxt_ctx_mem_buf_info *ctx)
575 ctx->va = rte_zmalloc(type, size, 0);
578 rte_mem_lock_page(ctx->va);
580 ctx->dma = rte_mem_virt2iova(ctx->va);
581 if (ctx->dma == RTE_BAD_IOVA)
587 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
589 struct rte_pci_device *pdev = bp->pdev;
590 char type[RTE_MEMZONE_NAMESIZE];
594 max_fc = bp->flow_stat->max_fc;
596 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
597 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
598 /* 4 bytes for each counter-id */
599 rc = bnxt_alloc_ctx_mem_buf(type,
601 &bp->flow_stat->rx_fc_in_tbl);
605 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
606 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
607 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
608 rc = bnxt_alloc_ctx_mem_buf(type,
610 &bp->flow_stat->rx_fc_out_tbl);
614 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
615 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
616 /* 4 bytes for each counter-id */
617 rc = bnxt_alloc_ctx_mem_buf(type,
619 &bp->flow_stat->tx_fc_in_tbl);
623 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
624 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
625 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
626 rc = bnxt_alloc_ctx_mem_buf(type,
628 &bp->flow_stat->tx_fc_out_tbl);
632 rc = bnxt_register_fc_ctx_mem(bp);
637 static int bnxt_init_ctx_mem(struct bnxt *bp)
641 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
642 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
643 !BNXT_FLOW_XSTATS_EN(bp))
646 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
650 rc = bnxt_init_fc_ctx_mem(bp);
655 static int bnxt_update_phy_setting(struct bnxt *bp)
657 struct rte_eth_link new;
660 rc = bnxt_get_hwrm_link_config(bp, &new);
662 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
667 * On BCM957508-N2100 adapters, FW will not allow any user other
668 * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
669 * always returns link up. Force phy update always in that case.
671 if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
672 rc = bnxt_set_hwrm_link_config(bp, true);
674 PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
682 static int bnxt_start_nic(struct bnxt *bp)
684 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
685 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
686 uint32_t intr_vector = 0;
687 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
688 uint32_t vec = BNXT_MISC_VEC_ID;
692 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
693 bp->eth_dev->data->dev_conf.rxmode.offloads |=
694 DEV_RX_OFFLOAD_JUMBO_FRAME;
695 bp->flags |= BNXT_FLAG_JUMBO;
697 bp->eth_dev->data->dev_conf.rxmode.offloads &=
698 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
699 bp->flags &= ~BNXT_FLAG_JUMBO;
702 /* THOR does not support ring groups.
703 * But we will use the array to save RSS context IDs.
705 if (BNXT_CHIP_P5(bp))
706 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
708 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
710 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
714 rc = bnxt_alloc_hwrm_rings(bp);
716 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
720 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
722 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
726 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
729 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
730 if (bp->rx_cos_queue[i].id != 0xff) {
731 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
735 "Num pools more than FW profile\n");
739 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
745 rc = bnxt_mq_rx_configure(bp);
747 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
752 rc = bnxt_setup_one_vnic(bp, 0);
755 /* VNIC configuration */
756 if (BNXT_RFS_NEEDS_VNIC(bp)) {
757 for (i = 1; i < bp->nr_vnics; i++) {
758 rc = bnxt_setup_one_vnic(bp, i);
764 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
767 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
771 /* check and configure queue intr-vector mapping */
772 if ((rte_intr_cap_multiple(intr_handle) ||
773 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
774 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
775 intr_vector = bp->eth_dev->data->nb_rx_queues;
776 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
777 if (intr_vector > bp->rx_cp_nr_rings) {
778 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
782 rc = rte_intr_efd_enable(intr_handle, intr_vector);
787 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
788 intr_handle->intr_vec =
789 rte_zmalloc("intr_vec",
790 bp->eth_dev->data->nb_rx_queues *
792 if (intr_handle->intr_vec == NULL) {
793 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
794 " intr_vec", bp->eth_dev->data->nb_rx_queues);
798 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
799 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
800 intr_handle->intr_vec, intr_handle->nb_efd,
801 intr_handle->max_intr);
802 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
804 intr_handle->intr_vec[queue_id] =
805 vec + BNXT_RX_VEC_START;
806 if (vec < base + intr_handle->nb_efd - 1)
811 /* enable uio/vfio intr/eventfd mapping */
812 rc = rte_intr_enable(intr_handle);
813 #ifndef RTE_EXEC_ENV_FREEBSD
814 /* In FreeBSD OS, nic_uio driver does not support interrupts */
819 rc = bnxt_update_phy_setting(bp);
823 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
825 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
830 rte_free(intr_handle->intr_vec);
832 rte_intr_efd_disable(intr_handle);
834 /* Some of the error status returned by FW may not be from errno.h */
841 static int bnxt_shutdown_nic(struct bnxt *bp)
843 bnxt_free_all_hwrm_resources(bp);
844 bnxt_free_all_filters(bp);
845 bnxt_free_all_vnics(bp);
850 * Device configuration and status function
853 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
855 uint32_t link_speed = bp->link_info->support_speeds;
856 uint32_t speed_capa = 0;
858 /* If PAM4 is configured, use PAM4 supported speed */
859 if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
860 link_speed = bp->link_info->support_pam4_speeds;
862 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
863 speed_capa |= ETH_LINK_SPEED_100M;
864 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
865 speed_capa |= ETH_LINK_SPEED_100M_HD;
866 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
867 speed_capa |= ETH_LINK_SPEED_1G;
868 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
869 speed_capa |= ETH_LINK_SPEED_2_5G;
870 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
871 speed_capa |= ETH_LINK_SPEED_10G;
872 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
873 speed_capa |= ETH_LINK_SPEED_20G;
874 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
875 speed_capa |= ETH_LINK_SPEED_25G;
876 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
877 speed_capa |= ETH_LINK_SPEED_40G;
878 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
879 speed_capa |= ETH_LINK_SPEED_50G;
880 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
881 speed_capa |= ETH_LINK_SPEED_100G;
882 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
883 speed_capa |= ETH_LINK_SPEED_50G;
884 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
885 speed_capa |= ETH_LINK_SPEED_100G;
886 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
887 speed_capa |= ETH_LINK_SPEED_200G;
889 if (bp->link_info->auto_mode ==
890 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
891 speed_capa |= ETH_LINK_SPEED_FIXED;
896 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
897 struct rte_eth_dev_info *dev_info)
899 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
900 struct bnxt *bp = eth_dev->data->dev_private;
901 uint16_t max_vnics, i, j, vpool, vrxq;
902 unsigned int max_rx_rings;
905 rc = is_bnxt_in_error(bp);
910 dev_info->max_mac_addrs = bp->max_l2_ctx;
911 dev_info->max_hash_mac_addrs = 0;
913 /* PF/VF specifics */
915 dev_info->max_vfs = pdev->max_vfs;
917 max_rx_rings = bnxt_max_rings(bp);
918 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
919 dev_info->max_rx_queues = max_rx_rings;
920 dev_info->max_tx_queues = max_rx_rings;
921 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
922 dev_info->hash_key_size = 40;
923 max_vnics = bp->max_vnics;
926 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
927 dev_info->max_mtu = BNXT_MAX_MTU;
929 /* Fast path specifics */
930 dev_info->min_rx_bufsize = 1;
931 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
933 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
934 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
935 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
936 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
937 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
938 dev_info->tx_queue_offload_capa;
939 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
941 dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
944 dev_info->default_rxconf = (struct rte_eth_rxconf) {
950 .rx_free_thresh = 32,
951 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
954 dev_info->default_txconf = (struct rte_eth_txconf) {
960 .tx_free_thresh = 32,
963 eth_dev->data->dev_conf.intr_conf.lsc = 1;
965 eth_dev->data->dev_conf.intr_conf.rxq = 1;
966 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
967 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
968 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
969 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
971 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
972 dev_info->switch_info.name = eth_dev->device->name;
973 dev_info->switch_info.domain_id = bp->switch_domain_id;
974 dev_info->switch_info.port_id =
975 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
976 BNXT_SWITCH_PORT_ID_TRUSTED_VF;
982 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
983 * need further investigation.
987 vpool = 64; /* ETH_64_POOLS */
988 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
989 for (i = 0; i < 4; vpool >>= 1, i++) {
990 if (max_vnics > vpool) {
991 for (j = 0; j < 5; vrxq >>= 1, j++) {
992 if (dev_info->max_rx_queues > vrxq) {
998 /* Not enough resources to support VMDq */
1002 /* Not enough resources to support VMDq */
1006 dev_info->max_vmdq_pools = vpool;
1007 dev_info->vmdq_queue_num = vrxq;
1009 dev_info->vmdq_pool_base = 0;
1010 dev_info->vmdq_queue_base = 0;
1015 /* Configure the device based on the configuration provided */
1016 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1018 struct bnxt *bp = eth_dev->data->dev_private;
1019 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1022 bp->rx_queues = (void *)eth_dev->data->rx_queues;
1023 bp->tx_queues = (void *)eth_dev->data->tx_queues;
1024 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1025 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1027 rc = is_bnxt_in_error(bp);
1031 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1032 rc = bnxt_hwrm_check_vf_rings(bp);
1034 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1038 /* If a resource has already been allocated - in this case
1039 * it is the async completion ring, free it. Reallocate it after
1040 * resource reservation. This will ensure the resource counts
1041 * are calculated correctly.
1044 pthread_mutex_lock(&bp->def_cp_lock);
1046 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1047 bnxt_disable_int(bp);
1048 bnxt_free_cp_ring(bp, bp->async_cp_ring);
1051 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1053 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1054 pthread_mutex_unlock(&bp->def_cp_lock);
1058 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1059 rc = bnxt_alloc_async_cp_ring(bp);
1061 pthread_mutex_unlock(&bp->def_cp_lock);
1064 bnxt_enable_int(bp);
1067 pthread_mutex_unlock(&bp->def_cp_lock);
1070 /* Inherit new configurations */
1071 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1072 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1073 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1074 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1075 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1077 goto resource_error;
1079 if (BNXT_HAS_RING_GRPS(bp) &&
1080 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1081 goto resource_error;
1083 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1084 bp->max_vnics < eth_dev->data->nb_rx_queues)
1085 goto resource_error;
1087 bp->rx_cp_nr_rings = bp->rx_nr_rings;
1088 bp->tx_cp_nr_rings = bp->tx_nr_rings;
1090 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1091 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1092 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1094 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1095 eth_dev->data->mtu =
1096 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1097 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1099 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1105 "Insufficient resources to support requested config\n");
1107 "Num Queues Requested: Tx %d, Rx %d\n",
1108 eth_dev->data->nb_tx_queues,
1109 eth_dev->data->nb_rx_queues);
1111 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1112 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1113 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1117 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1119 struct rte_eth_link *link = ð_dev->data->dev_link;
1121 if (link->link_status)
1122 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1123 eth_dev->data->port_id,
1124 (uint32_t)link->link_speed,
1125 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1126 ("full-duplex") : ("half-duplex\n"));
1128 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1129 eth_dev->data->port_id);
1133 * Determine whether the current configuration requires support for scattered
1134 * receive; return 1 if scattered receive is required and 0 if not.
1136 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1141 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1144 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO)
1147 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1148 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1150 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1151 RTE_PKTMBUF_HEADROOM);
1152 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1158 static eth_rx_burst_t
1159 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1161 struct bnxt *bp = eth_dev->data->dev_private;
1163 /* Disable vector mode RX for Stingray2 for now */
1164 if (BNXT_CHIP_SR2(bp)) {
1165 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1166 return bnxt_recv_pkts;
1169 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1170 #ifndef RTE_LIBRTE_IEEE1588
1172 * Vector mode receive can be enabled only if scatter rx is not
1173 * in use and rx offloads are limited to VLAN stripping and
1176 if (!eth_dev->data->scattered_rx &&
1177 !(eth_dev->data->dev_conf.rxmode.offloads &
1178 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1179 DEV_RX_OFFLOAD_KEEP_CRC |
1180 DEV_RX_OFFLOAD_JUMBO_FRAME |
1181 DEV_RX_OFFLOAD_IPV4_CKSUM |
1182 DEV_RX_OFFLOAD_UDP_CKSUM |
1183 DEV_RX_OFFLOAD_TCP_CKSUM |
1184 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1185 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1186 DEV_RX_OFFLOAD_RSS_HASH |
1187 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1188 !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp) &&
1189 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1190 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1191 eth_dev->data->port_id);
1192 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1193 return bnxt_recv_pkts_vec;
1195 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1196 eth_dev->data->port_id);
1198 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1199 eth_dev->data->port_id,
1200 eth_dev->data->scattered_rx,
1201 eth_dev->data->dev_conf.rxmode.offloads);
1204 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1205 return bnxt_recv_pkts;
1208 static eth_tx_burst_t
1209 bnxt_transmit_function(struct rte_eth_dev *eth_dev)
1211 struct bnxt *bp = eth_dev->data->dev_private;
1213 /* Disable vector mode TX for Stingray2 for now */
1214 if (BNXT_CHIP_SR2(bp))
1215 return bnxt_xmit_pkts;
1217 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1218 #ifndef RTE_LIBRTE_IEEE1588
1219 uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1222 * Vector mode transmit can be enabled only if not using scatter rx
1225 if (!eth_dev->data->scattered_rx &&
1226 !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
1227 !BNXT_TRUFLOW_EN(bp) &&
1228 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1229 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1230 eth_dev->data->port_id);
1231 return bnxt_xmit_pkts_vec;
1233 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1234 eth_dev->data->port_id);
1236 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1237 eth_dev->data->port_id,
1238 eth_dev->data->scattered_rx,
1242 return bnxt_xmit_pkts;
1245 static int bnxt_handle_if_change_status(struct bnxt *bp)
1249 /* Since fw has undergone a reset and lost all contexts,
1250 * set fatal flag to not issue hwrm during cleanup
1252 bp->flags |= BNXT_FLAG_FATAL_ERROR;
1253 bnxt_uninit_resources(bp, true);
1255 /* clear fatal flag so that re-init happens */
1256 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1257 rc = bnxt_init_resources(bp, true);
1259 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1264 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1266 struct bnxt *bp = eth_dev->data->dev_private;
1269 if (!BNXT_SINGLE_PF(bp))
1272 if (!bp->link_info->link_up)
1273 rc = bnxt_set_hwrm_link_config(bp, true);
1275 eth_dev->data->dev_link.link_status = 1;
1277 bnxt_print_link_info(eth_dev);
1281 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1283 struct bnxt *bp = eth_dev->data->dev_private;
1285 if (!BNXT_SINGLE_PF(bp))
1288 eth_dev->data->dev_link.link_status = 0;
1289 bnxt_set_hwrm_link_config(bp, false);
1290 bp->link_info->link_up = 0;
1295 static void bnxt_free_switch_domain(struct bnxt *bp)
1299 if (bp->switch_domain_id) {
1300 rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1302 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1303 bp->switch_domain_id, rc);
1307 static void bnxt_ptp_get_current_time(void *arg)
1309 struct bnxt *bp = arg;
1310 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1313 rc = is_bnxt_in_error(bp);
1320 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1321 &ptp->current_time);
1323 rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1325 PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n");
1326 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1330 static int bnxt_schedule_ptp_alarm(struct bnxt *bp)
1332 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1335 if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED)
1338 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1339 &ptp->current_time);
1341 rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1345 static void bnxt_cancel_ptp_alarm(struct bnxt *bp)
1347 if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) {
1348 rte_eal_alarm_cancel(bnxt_ptp_get_current_time, (void *)bp);
1349 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1353 static void bnxt_ptp_stop(struct bnxt *bp)
1355 bnxt_cancel_ptp_alarm(bp);
1356 bp->flags2 &= ~BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1359 static int bnxt_ptp_start(struct bnxt *bp)
1363 rc = bnxt_schedule_ptp_alarm(bp);
1365 PMD_DRV_LOG(ERR, "Failed to schedule PTP alarm\n");
1367 bp->flags2 |= BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1368 bp->flags2 |= BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1374 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev)
1376 struct bnxt *bp = eth_dev->data->dev_private;
1377 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1378 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1379 struct rte_eth_link link;
1382 eth_dev->data->dev_started = 0;
1383 eth_dev->data->scattered_rx = 0;
1385 /* Prevent crashes when queues are still in use */
1386 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1387 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1389 bnxt_disable_int(bp);
1391 /* disable uio/vfio intr/eventfd mapping */
1392 rte_intr_disable(intr_handle);
1394 /* Stop the child representors for this device */
1395 ret = bnxt_rep_stop_all(bp);
1399 /* delete the bnxt ULP port details */
1400 bnxt_ulp_port_deinit(bp);
1402 bnxt_cancel_fw_health_check(bp);
1404 if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1405 bnxt_cancel_ptp_alarm(bp);
1407 /* Do not bring link down during reset recovery */
1408 if (!is_bnxt_in_error(bp)) {
1409 bnxt_dev_set_link_down_op(eth_dev);
1410 /* Wait for link to be reset */
1411 if (BNXT_SINGLE_PF(bp))
1413 /* clear the recorded link status */
1414 memset(&link, 0, sizeof(link));
1415 rte_eth_linkstatus_set(eth_dev, &link);
1418 /* Clean queue intr-vector mapping */
1419 rte_intr_efd_disable(intr_handle);
1420 if (intr_handle->intr_vec != NULL) {
1421 rte_free(intr_handle->intr_vec);
1422 intr_handle->intr_vec = NULL;
1425 bnxt_hwrm_port_clr_stats(bp);
1426 bnxt_free_tx_mbufs(bp);
1427 bnxt_free_rx_mbufs(bp);
1428 /* Process any remaining notifications in default completion queue */
1429 bnxt_int_handler(eth_dev);
1430 bnxt_shutdown_nic(bp);
1431 bnxt_hwrm_if_change(bp, false);
1433 rte_free(bp->mark_table);
1434 bp->mark_table = NULL;
1436 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1437 bp->rx_cosq_cnt = 0;
1438 /* All filters are deleted on a port stop. */
1439 if (BNXT_FLOW_XSTATS_EN(bp))
1440 bp->flow_stat->flow_count = 0;
1445 /* Unload the driver, release resources */
1446 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1448 struct bnxt *bp = eth_dev->data->dev_private;
1450 pthread_mutex_lock(&bp->err_recovery_lock);
1451 if (bp->flags & BNXT_FLAG_FW_RESET) {
1453 "Adapter recovering from error..Please retry\n");
1454 pthread_mutex_unlock(&bp->err_recovery_lock);
1457 pthread_mutex_unlock(&bp->err_recovery_lock);
1459 return bnxt_dev_stop(eth_dev);
1462 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1464 struct bnxt *bp = eth_dev->data->dev_private;
1465 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1467 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1469 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1470 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1474 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1476 "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1477 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1480 rc = bnxt_hwrm_if_change(bp, true);
1481 if (rc == 0 || rc != -EAGAIN)
1484 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1485 } while (retry_cnt--);
1490 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1491 rc = bnxt_handle_if_change_status(bp);
1496 bnxt_enable_int(bp);
1498 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1500 rc = bnxt_start_nic(bp);
1504 eth_dev->data->dev_started = 1;
1506 bnxt_link_update_op(eth_dev, 1);
1508 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1509 vlan_mask |= ETH_VLAN_FILTER_MASK;
1510 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1511 vlan_mask |= ETH_VLAN_STRIP_MASK;
1512 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1516 /* Initialize bnxt ULP port details */
1517 rc = bnxt_ulp_port_init(bp);
1521 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1522 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1524 bnxt_schedule_fw_health_check(bp);
1526 if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1527 bnxt_schedule_ptp_alarm(bp);
1532 bnxt_dev_stop(eth_dev);
1537 bnxt_uninit_locks(struct bnxt *bp)
1539 pthread_mutex_destroy(&bp->flow_lock);
1540 pthread_mutex_destroy(&bp->def_cp_lock);
1541 pthread_mutex_destroy(&bp->health_check_lock);
1542 pthread_mutex_destroy(&bp->err_recovery_lock);
1544 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
1545 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
1549 static void bnxt_drv_uninit(struct bnxt *bp)
1551 bnxt_free_switch_domain(bp);
1552 bnxt_free_leds_info(bp);
1553 bnxt_free_cos_queues(bp);
1554 bnxt_free_link_info(bp);
1555 bnxt_free_pf_info(bp);
1556 bnxt_free_parent_info(bp);
1557 bnxt_uninit_locks(bp);
1559 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1560 bp->tx_mem_zone = NULL;
1561 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1562 bp->rx_mem_zone = NULL;
1564 bnxt_free_vf_info(bp);
1566 rte_free(bp->grp_info);
1567 bp->grp_info = NULL;
1570 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1572 struct bnxt *bp = eth_dev->data->dev_private;
1575 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1578 pthread_mutex_lock(&bp->err_recovery_lock);
1579 if (bp->flags & BNXT_FLAG_FW_RESET) {
1581 "Adapter recovering from error...Please retry\n");
1582 pthread_mutex_unlock(&bp->err_recovery_lock);
1585 pthread_mutex_unlock(&bp->err_recovery_lock);
1587 /* cancel the recovery handler before remove dev */
1588 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1589 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1590 bnxt_cancel_fc_thread(bp);
1592 if (eth_dev->data->dev_started)
1593 ret = bnxt_dev_stop(eth_dev);
1595 bnxt_uninit_resources(bp, false);
1597 bnxt_drv_uninit(bp);
1602 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1605 struct bnxt *bp = eth_dev->data->dev_private;
1606 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1607 struct bnxt_vnic_info *vnic;
1608 struct bnxt_filter_info *filter, *temp_filter;
1611 if (is_bnxt_in_error(bp))
1615 * Loop through all VNICs from the specified filter flow pools to
1616 * remove the corresponding MAC addr filter
1618 for (i = 0; i < bp->nr_vnics; i++) {
1619 if (!(pool_mask & (1ULL << i)))
1622 vnic = &bp->vnic_info[i];
1623 filter = STAILQ_FIRST(&vnic->filter);
1625 temp_filter = STAILQ_NEXT(filter, next);
1626 if (filter->mac_index == index) {
1627 STAILQ_REMOVE(&vnic->filter, filter,
1628 bnxt_filter_info, next);
1629 bnxt_hwrm_clear_l2_filter(bp, filter);
1630 bnxt_free_filter(bp, filter);
1632 filter = temp_filter;
1637 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1638 struct rte_ether_addr *mac_addr, uint32_t index,
1641 struct bnxt_filter_info *filter;
1644 /* Attach requested MAC address to the new l2_filter */
1645 STAILQ_FOREACH(filter, &vnic->filter, next) {
1646 if (filter->mac_index == index) {
1648 "MAC addr already existed for pool %d\n",
1654 filter = bnxt_alloc_filter(bp);
1656 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1660 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1661 * if the MAC that's been programmed now is a different one, then,
1662 * copy that addr to filter->l2_addr
1665 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1666 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1668 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1670 filter->mac_index = index;
1671 if (filter->mac_index == 0)
1672 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1674 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1676 bnxt_free_filter(bp, filter);
1682 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1683 struct rte_ether_addr *mac_addr,
1684 uint32_t index, uint32_t pool)
1686 struct bnxt *bp = eth_dev->data->dev_private;
1687 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1690 rc = is_bnxt_in_error(bp);
1694 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1695 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1700 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1704 /* Filter settings will get applied when port is started */
1705 if (!eth_dev->data->dev_started)
1708 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1713 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1716 struct bnxt *bp = eth_dev->data->dev_private;
1717 struct rte_eth_link new;
1718 int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1719 BNXT_MIN_LINK_WAIT_CNT;
1721 rc = is_bnxt_in_error(bp);
1725 memset(&new, 0, sizeof(new));
1727 /* Retrieve link info from hardware */
1728 rc = bnxt_get_hwrm_link_config(bp, &new);
1730 new.link_speed = ETH_LINK_SPEED_100M;
1731 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1733 "Failed to retrieve link rc = 0x%x!\n", rc);
1737 if (!wait_to_complete || new.link_status)
1740 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1743 /* Only single function PF can bring phy down.
1744 * When port is stopped, report link down for VF/MH/NPAR functions.
1746 if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1747 memset(&new, 0, sizeof(new));
1750 /* Timed out or success */
1751 if (new.link_status != eth_dev->data->dev_link.link_status ||
1752 new.link_speed != eth_dev->data->dev_link.link_speed) {
1753 rte_eth_linkstatus_set(eth_dev, &new);
1755 rte_eth_dev_callback_process(eth_dev,
1756 RTE_ETH_EVENT_INTR_LSC,
1759 bnxt_print_link_info(eth_dev);
1765 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1767 struct bnxt *bp = eth_dev->data->dev_private;
1768 struct bnxt_vnic_info *vnic;
1772 rc = is_bnxt_in_error(bp);
1776 /* Filter settings will get applied when port is started */
1777 if (!eth_dev->data->dev_started)
1780 if (bp->vnic_info == NULL)
1783 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1785 old_flags = vnic->flags;
1786 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1787 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1789 vnic->flags = old_flags;
1794 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1796 struct bnxt *bp = eth_dev->data->dev_private;
1797 struct bnxt_vnic_info *vnic;
1801 rc = is_bnxt_in_error(bp);
1805 /* Filter settings will get applied when port is started */
1806 if (!eth_dev->data->dev_started)
1809 if (bp->vnic_info == NULL)
1812 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1814 old_flags = vnic->flags;
1815 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1816 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1818 vnic->flags = old_flags;
1823 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1825 struct bnxt *bp = eth_dev->data->dev_private;
1826 struct bnxt_vnic_info *vnic;
1830 rc = is_bnxt_in_error(bp);
1834 /* Filter settings will get applied when port is started */
1835 if (!eth_dev->data->dev_started)
1838 if (bp->vnic_info == NULL)
1841 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1843 old_flags = vnic->flags;
1844 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1845 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1847 vnic->flags = old_flags;
1852 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1854 struct bnxt *bp = eth_dev->data->dev_private;
1855 struct bnxt_vnic_info *vnic;
1859 rc = is_bnxt_in_error(bp);
1863 /* Filter settings will get applied when port is started */
1864 if (!eth_dev->data->dev_started)
1867 if (bp->vnic_info == NULL)
1870 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1872 old_flags = vnic->flags;
1873 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1874 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1876 vnic->flags = old_flags;
1881 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1882 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1884 if (qid >= bp->rx_nr_rings)
1887 return bp->eth_dev->data->rx_queues[qid];
1890 /* Return rxq corresponding to a given rss table ring/group ID. */
1891 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1893 struct bnxt_rx_queue *rxq;
1896 if (!BNXT_HAS_RING_GRPS(bp)) {
1897 for (i = 0; i < bp->rx_nr_rings; i++) {
1898 rxq = bp->eth_dev->data->rx_queues[i];
1899 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1903 for (i = 0; i < bp->rx_nr_rings; i++) {
1904 if (bp->grp_info[i].fw_grp_id == fwr)
1909 return INVALID_HW_RING_ID;
1912 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1913 struct rte_eth_rss_reta_entry64 *reta_conf,
1916 struct bnxt *bp = eth_dev->data->dev_private;
1917 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1918 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1919 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1923 rc = is_bnxt_in_error(bp);
1927 if (!vnic->rss_table)
1930 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1933 if (reta_size != tbl_size) {
1934 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1935 "(%d) must equal the size supported by the hardware "
1936 "(%d)\n", reta_size, tbl_size);
1940 for (i = 0; i < reta_size; i++) {
1941 struct bnxt_rx_queue *rxq;
1943 idx = i / RTE_RETA_GROUP_SIZE;
1944 sft = i % RTE_RETA_GROUP_SIZE;
1946 if (!(reta_conf[idx].mask & (1ULL << sft)))
1949 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1951 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1955 if (BNXT_CHIP_P5(bp)) {
1956 vnic->rss_table[i * 2] =
1957 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1958 vnic->rss_table[i * 2 + 1] =
1959 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1961 vnic->rss_table[i] =
1962 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1966 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1970 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1971 struct rte_eth_rss_reta_entry64 *reta_conf,
1974 struct bnxt *bp = eth_dev->data->dev_private;
1975 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1976 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1977 uint16_t idx, sft, i;
1980 rc = is_bnxt_in_error(bp);
1984 /* Retrieve from the default VNIC */
1987 if (!vnic->rss_table)
1990 if (reta_size != tbl_size) {
1991 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1992 "(%d) must equal the size supported by the hardware "
1993 "(%d)\n", reta_size, tbl_size);
1997 for (idx = 0, i = 0; i < reta_size; i++) {
1998 idx = i / RTE_RETA_GROUP_SIZE;
1999 sft = i % RTE_RETA_GROUP_SIZE;
2001 if (reta_conf[idx].mask & (1ULL << sft)) {
2004 if (BNXT_CHIP_P5(bp))
2005 qid = bnxt_rss_to_qid(bp,
2006 vnic->rss_table[i * 2]);
2008 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
2010 if (qid == INVALID_HW_RING_ID) {
2011 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
2014 reta_conf[idx].reta[sft] = qid;
2021 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
2022 struct rte_eth_rss_conf *rss_conf)
2024 struct bnxt *bp = eth_dev->data->dev_private;
2025 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2026 struct bnxt_vnic_info *vnic;
2029 rc = is_bnxt_in_error(bp);
2034 * If RSS enablement were different than dev_configure,
2035 * then return -EINVAL
2037 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
2038 if (!rss_conf->rss_hf)
2039 PMD_DRV_LOG(ERR, "Hash type NONE\n");
2041 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
2045 bp->flags |= BNXT_FLAG_UPDATE_HASH;
2046 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf,
2050 /* Update the default RSS VNIC(s) */
2051 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2052 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
2054 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
2055 ETH_RSS_LEVEL(rss_conf->rss_hf));
2058 * If hashkey is not specified, use the previously configured
2061 if (!rss_conf->rss_key)
2064 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
2066 "Invalid hashkey length, should be 16 bytes\n");
2069 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
2072 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2076 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
2077 struct rte_eth_rss_conf *rss_conf)
2079 struct bnxt *bp = eth_dev->data->dev_private;
2080 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2082 uint32_t hash_types;
2084 rc = is_bnxt_in_error(bp);
2088 /* RSS configuration is the same for all VNICs */
2089 if (vnic && vnic->rss_hash_key) {
2090 if (rss_conf->rss_key) {
2091 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
2092 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
2093 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
2096 hash_types = vnic->hash_type;
2097 rss_conf->rss_hf = 0;
2098 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
2099 rss_conf->rss_hf |= ETH_RSS_IPV4;
2100 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
2102 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
2103 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2105 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
2107 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
2108 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2110 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
2112 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
2113 rss_conf->rss_hf |= ETH_RSS_IPV6;
2114 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
2116 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
2117 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2119 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
2121 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
2122 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2124 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2128 bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2132 "Unknown RSS config from firmware (%08x), RSS disabled",
2137 rss_conf->rss_hf = 0;
2142 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2143 struct rte_eth_fc_conf *fc_conf)
2145 struct bnxt *bp = dev->data->dev_private;
2146 struct rte_eth_link link_info;
2149 rc = is_bnxt_in_error(bp);
2153 rc = bnxt_get_hwrm_link_config(bp, &link_info);
2157 memset(fc_conf, 0, sizeof(*fc_conf));
2158 if (bp->link_info->auto_pause)
2159 fc_conf->autoneg = 1;
2160 switch (bp->link_info->pause) {
2162 fc_conf->mode = RTE_FC_NONE;
2164 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2165 fc_conf->mode = RTE_FC_TX_PAUSE;
2167 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2168 fc_conf->mode = RTE_FC_RX_PAUSE;
2170 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2171 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2172 fc_conf->mode = RTE_FC_FULL;
2178 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2179 struct rte_eth_fc_conf *fc_conf)
2181 struct bnxt *bp = dev->data->dev_private;
2184 rc = is_bnxt_in_error(bp);
2188 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2189 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2193 switch (fc_conf->mode) {
2195 bp->link_info->auto_pause = 0;
2196 bp->link_info->force_pause = 0;
2198 case RTE_FC_RX_PAUSE:
2199 if (fc_conf->autoneg) {
2200 bp->link_info->auto_pause =
2201 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2202 bp->link_info->force_pause = 0;
2204 bp->link_info->auto_pause = 0;
2205 bp->link_info->force_pause =
2206 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2209 case RTE_FC_TX_PAUSE:
2210 if (fc_conf->autoneg) {
2211 bp->link_info->auto_pause =
2212 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2213 bp->link_info->force_pause = 0;
2215 bp->link_info->auto_pause = 0;
2216 bp->link_info->force_pause =
2217 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2221 if (fc_conf->autoneg) {
2222 bp->link_info->auto_pause =
2223 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2224 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2225 bp->link_info->force_pause = 0;
2227 bp->link_info->auto_pause = 0;
2228 bp->link_info->force_pause =
2229 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2230 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2234 return bnxt_set_hwrm_link_config(bp, true);
2237 /* Add UDP tunneling port */
2239 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2240 struct rte_eth_udp_tunnel *udp_tunnel)
2242 struct bnxt *bp = eth_dev->data->dev_private;
2243 uint16_t tunnel_type = 0;
2246 rc = is_bnxt_in_error(bp);
2250 switch (udp_tunnel->prot_type) {
2251 case RTE_TUNNEL_TYPE_VXLAN:
2252 if (bp->vxlan_port_cnt) {
2253 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2254 udp_tunnel->udp_port);
2255 if (bp->vxlan_port != udp_tunnel->udp_port) {
2256 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2259 bp->vxlan_port_cnt++;
2263 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2264 bp->vxlan_port_cnt++;
2266 case RTE_TUNNEL_TYPE_GENEVE:
2267 if (bp->geneve_port_cnt) {
2268 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2269 udp_tunnel->udp_port);
2270 if (bp->geneve_port != udp_tunnel->udp_port) {
2271 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2274 bp->geneve_port_cnt++;
2278 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2279 bp->geneve_port_cnt++;
2282 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2285 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2291 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2292 struct rte_eth_udp_tunnel *udp_tunnel)
2294 struct bnxt *bp = eth_dev->data->dev_private;
2295 uint16_t tunnel_type = 0;
2299 rc = is_bnxt_in_error(bp);
2303 switch (udp_tunnel->prot_type) {
2304 case RTE_TUNNEL_TYPE_VXLAN:
2305 if (!bp->vxlan_port_cnt) {
2306 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2309 if (bp->vxlan_port != udp_tunnel->udp_port) {
2310 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2311 udp_tunnel->udp_port, bp->vxlan_port);
2314 if (--bp->vxlan_port_cnt)
2318 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2319 port = bp->vxlan_fw_dst_port_id;
2321 case RTE_TUNNEL_TYPE_GENEVE:
2322 if (!bp->geneve_port_cnt) {
2323 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2326 if (bp->geneve_port != udp_tunnel->udp_port) {
2327 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2328 udp_tunnel->udp_port, bp->geneve_port);
2331 if (--bp->geneve_port_cnt)
2335 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2336 port = bp->geneve_fw_dst_port_id;
2339 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2343 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2347 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2349 struct bnxt_filter_info *filter;
2350 struct bnxt_vnic_info *vnic;
2352 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2354 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2355 filter = STAILQ_FIRST(&vnic->filter);
2357 /* Search for this matching MAC+VLAN filter */
2358 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2359 /* Delete the filter */
2360 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2363 STAILQ_REMOVE(&vnic->filter, filter,
2364 bnxt_filter_info, next);
2365 bnxt_free_filter(bp, filter);
2367 "Deleted vlan filter for %d\n",
2371 filter = STAILQ_NEXT(filter, next);
2376 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2378 struct bnxt_filter_info *filter;
2379 struct bnxt_vnic_info *vnic;
2381 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2382 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2383 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2385 /* Implementation notes on the use of VNIC in this command:
2387 * By default, these filters belong to default vnic for the function.
2388 * Once these filters are set up, only destination VNIC can be modified.
2389 * If the destination VNIC is not specified in this command,
2390 * then the HWRM shall only create an l2 context id.
2393 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2394 filter = STAILQ_FIRST(&vnic->filter);
2395 /* Check if the VLAN has already been added */
2397 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2400 filter = STAILQ_NEXT(filter, next);
2403 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2404 * command to create MAC+VLAN filter with the right flags, enables set.
2406 filter = bnxt_alloc_filter(bp);
2409 "MAC/VLAN filter alloc failed\n");
2412 /* MAC + VLAN ID filter */
2413 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2414 * untagged packets are received
2416 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2417 * packets and only the programmed vlan's packets are received
2419 filter->l2_ivlan = vlan_id;
2420 filter->l2_ivlan_mask = 0x0FFF;
2421 filter->enables |= en;
2422 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2424 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2426 /* Free the newly allocated filter as we were
2427 * not able to create the filter in hardware.
2429 bnxt_free_filter(bp, filter);
2433 filter->mac_index = 0;
2434 /* Add this new filter to the list */
2436 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2438 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2441 "Added Vlan filter for %d\n", vlan_id);
2445 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2446 uint16_t vlan_id, int on)
2448 struct bnxt *bp = eth_dev->data->dev_private;
2451 rc = is_bnxt_in_error(bp);
2455 if (!eth_dev->data->dev_started) {
2456 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2460 /* These operations apply to ALL existing MAC/VLAN filters */
2462 return bnxt_add_vlan_filter(bp, vlan_id);
2464 return bnxt_del_vlan_filter(bp, vlan_id);
2467 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2468 struct bnxt_vnic_info *vnic)
2470 struct bnxt_filter_info *filter;
2473 filter = STAILQ_FIRST(&vnic->filter);
2475 if (filter->mac_index == 0 &&
2476 !memcmp(filter->l2_addr, bp->mac_addr,
2477 RTE_ETHER_ADDR_LEN)) {
2478 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2480 STAILQ_REMOVE(&vnic->filter, filter,
2481 bnxt_filter_info, next);
2482 bnxt_free_filter(bp, filter);
2486 filter = STAILQ_NEXT(filter, next);
2492 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2494 struct bnxt_vnic_info *vnic;
2498 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2499 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2500 /* Remove any VLAN filters programmed */
2501 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2502 bnxt_del_vlan_filter(bp, i);
2504 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2508 /* Default filter will allow packets that match the
2509 * dest mac. So, it has to be deleted, otherwise, we
2510 * will endup receiving vlan packets for which the
2511 * filter is not programmed, when hw-vlan-filter
2512 * configuration is ON
2514 bnxt_del_dflt_mac_filter(bp, vnic);
2515 /* This filter will allow only untagged packets */
2516 bnxt_add_vlan_filter(bp, 0);
2518 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2519 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2524 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2526 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2530 /* Destroy vnic filters and vnic */
2531 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2532 DEV_RX_OFFLOAD_VLAN_FILTER) {
2533 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2534 bnxt_del_vlan_filter(bp, i);
2536 bnxt_del_dflt_mac_filter(bp, vnic);
2538 rc = bnxt_hwrm_vnic_ctx_free(bp, vnic);
2542 rc = bnxt_hwrm_vnic_free(bp, vnic);
2546 rte_free(vnic->fw_grp_ids);
2547 vnic->fw_grp_ids = NULL;
2549 vnic->rx_queue_cnt = 0;
2555 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2557 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2560 /* Destroy, recreate and reconfigure the default vnic */
2561 rc = bnxt_free_one_vnic(bp, 0);
2565 /* default vnic 0 */
2566 rc = bnxt_setup_one_vnic(bp, 0);
2570 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2571 DEV_RX_OFFLOAD_VLAN_FILTER) {
2572 rc = bnxt_add_vlan_filter(bp, 0);
2575 rc = bnxt_restore_vlan_filters(bp);
2579 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2584 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2588 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2589 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2595 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2597 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2598 struct bnxt *bp = dev->data->dev_private;
2601 rc = is_bnxt_in_error(bp);
2605 /* Filter settings will get applied when port is started */
2606 if (!dev->data->dev_started)
2609 if (mask & ETH_VLAN_FILTER_MASK) {
2610 /* Enable or disable VLAN filtering */
2611 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2616 if (mask & ETH_VLAN_STRIP_MASK) {
2617 /* Enable or disable VLAN stripping */
2618 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2623 if (mask & ETH_VLAN_EXTEND_MASK) {
2624 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2625 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2627 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2634 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2637 struct bnxt *bp = dev->data->dev_private;
2638 int qinq = dev->data->dev_conf.rxmode.offloads &
2639 DEV_RX_OFFLOAD_VLAN_EXTEND;
2641 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2642 vlan_type != ETH_VLAN_TYPE_OUTER) {
2644 "Unsupported vlan type.");
2649 "QinQ not enabled. Needs to be ON as we can "
2650 "accelerate only outer vlan\n");
2654 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2656 case RTE_ETHER_TYPE_QINQ:
2658 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2660 case RTE_ETHER_TYPE_VLAN:
2662 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2664 case RTE_ETHER_TYPE_QINQ1:
2666 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2668 case RTE_ETHER_TYPE_QINQ2:
2670 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2672 case RTE_ETHER_TYPE_QINQ3:
2674 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2677 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2680 bp->outer_tpid_bd |= tpid;
2681 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2682 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2684 "Can accelerate only outer vlan in QinQ\n");
2692 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2693 struct rte_ether_addr *addr)
2695 struct bnxt *bp = dev->data->dev_private;
2696 /* Default Filter is tied to VNIC 0 */
2697 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2700 rc = is_bnxt_in_error(bp);
2704 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2707 if (rte_is_zero_ether_addr(addr))
2710 /* Filter settings will get applied when port is started */
2711 if (!dev->data->dev_started)
2714 /* Check if the requested MAC is already added */
2715 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2718 /* Destroy filter and re-create it */
2719 bnxt_del_dflt_mac_filter(bp, vnic);
2721 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2722 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2723 /* This filter will allow only untagged packets */
2724 rc = bnxt_add_vlan_filter(bp, 0);
2726 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2729 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2734 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2735 struct rte_ether_addr *mc_addr_set,
2736 uint32_t nb_mc_addr)
2738 struct bnxt *bp = eth_dev->data->dev_private;
2739 char *mc_addr_list = (char *)mc_addr_set;
2740 struct bnxt_vnic_info *vnic;
2741 uint32_t off = 0, i = 0;
2744 rc = is_bnxt_in_error(bp);
2748 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2750 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2751 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2755 /* TODO Check for Duplicate mcast addresses */
2756 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2757 for (i = 0; i < nb_mc_addr; i++) {
2758 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2759 RTE_ETHER_ADDR_LEN);
2760 off += RTE_ETHER_ADDR_LEN;
2763 vnic->mc_addr_cnt = i;
2764 if (vnic->mc_addr_cnt)
2765 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2767 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2770 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2774 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2776 struct bnxt *bp = dev->data->dev_private;
2777 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2778 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2779 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2780 uint8_t fw_rsvd = bp->fw_ver & 0xff;
2783 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2784 fw_major, fw_minor, fw_updt, fw_rsvd);
2786 ret += 1; /* add the size of '\0' */
2787 if (fw_size < (uint32_t)ret)
2794 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2795 struct rte_eth_rxq_info *qinfo)
2797 struct bnxt *bp = dev->data->dev_private;
2798 struct bnxt_rx_queue *rxq;
2800 if (is_bnxt_in_error(bp))
2803 rxq = dev->data->rx_queues[queue_id];
2805 qinfo->mp = rxq->mb_pool;
2806 qinfo->scattered_rx = dev->data->scattered_rx;
2807 qinfo->nb_desc = rxq->nb_rx_desc;
2809 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2810 qinfo->conf.rx_drop_en = rxq->drop_en;
2811 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2812 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2816 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2817 struct rte_eth_txq_info *qinfo)
2819 struct bnxt *bp = dev->data->dev_private;
2820 struct bnxt_tx_queue *txq;
2822 if (is_bnxt_in_error(bp))
2825 txq = dev->data->tx_queues[queue_id];
2827 qinfo->nb_desc = txq->nb_tx_desc;
2829 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2830 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2831 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2833 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2834 qinfo->conf.tx_rs_thresh = 0;
2835 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2836 qinfo->conf.offloads = txq->offloads;
2839 static const struct {
2840 eth_rx_burst_t pkt_burst;
2842 } bnxt_rx_burst_info[] = {
2843 {bnxt_recv_pkts, "Scalar"},
2844 #if defined(RTE_ARCH_X86)
2845 {bnxt_recv_pkts_vec, "Vector SSE"},
2846 #elif defined(RTE_ARCH_ARM64)
2847 {bnxt_recv_pkts_vec, "Vector Neon"},
2852 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2853 struct rte_eth_burst_mode *mode)
2855 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2858 for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2859 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2860 snprintf(mode->info, sizeof(mode->info), "%s",
2861 bnxt_rx_burst_info[i].info);
2869 static const struct {
2870 eth_tx_burst_t pkt_burst;
2872 } bnxt_tx_burst_info[] = {
2873 {bnxt_xmit_pkts, "Scalar"},
2874 #if defined(RTE_ARCH_X86)
2875 {bnxt_xmit_pkts_vec, "Vector SSE"},
2876 #elif defined(RTE_ARCH_ARM64)
2877 {bnxt_xmit_pkts_vec, "Vector Neon"},
2882 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2883 struct rte_eth_burst_mode *mode)
2885 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2888 for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2889 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2890 snprintf(mode->info, sizeof(mode->info), "%s",
2891 bnxt_tx_burst_info[i].info);
2899 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2901 struct bnxt *bp = eth_dev->data->dev_private;
2902 uint32_t new_pkt_size;
2906 rc = is_bnxt_in_error(bp);
2910 /* Exit if receive queues are not configured yet */
2911 if (!eth_dev->data->nb_rx_queues)
2914 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2915 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2918 * Disallow any MTU change that would require scattered receive support
2919 * if it is not already enabled.
2921 if (eth_dev->data->dev_started &&
2922 !eth_dev->data->scattered_rx &&
2924 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2926 "MTU change would require scattered rx support. ");
2927 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2931 if (new_mtu > RTE_ETHER_MTU) {
2932 bp->flags |= BNXT_FLAG_JUMBO;
2933 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2934 DEV_RX_OFFLOAD_JUMBO_FRAME;
2936 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2937 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2938 bp->flags &= ~BNXT_FLAG_JUMBO;
2941 /* Is there a change in mtu setting? */
2942 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2945 for (i = 0; i < bp->nr_vnics; i++) {
2946 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2949 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2950 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2954 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2955 size -= RTE_PKTMBUF_HEADROOM;
2957 if (size < new_mtu) {
2958 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2965 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2967 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2973 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2975 struct bnxt *bp = dev->data->dev_private;
2976 uint16_t vlan = bp->vlan;
2979 rc = is_bnxt_in_error(bp);
2983 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2985 "PVID cannot be modified for this function\n");
2988 bp->vlan = on ? pvid : 0;
2990 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2997 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2999 struct bnxt *bp = dev->data->dev_private;
3002 rc = is_bnxt_in_error(bp);
3006 return bnxt_hwrm_port_led_cfg(bp, true);
3010 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
3012 struct bnxt *bp = dev->data->dev_private;
3015 rc = is_bnxt_in_error(bp);
3019 return bnxt_hwrm_port_led_cfg(bp, false);
3023 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3025 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
3026 struct bnxt_cp_ring_info *cpr;
3027 uint32_t desc = 0, raw_cons;
3028 struct bnxt_rx_queue *rxq;
3029 struct rx_pkt_cmpl *rxcmp;
3032 rc = is_bnxt_in_error(bp);
3036 rxq = dev->data->rx_queues[rx_queue_id];
3038 raw_cons = cpr->cp_raw_cons;
3041 uint32_t agg_cnt, cons, cmpl_type;
3043 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3044 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3046 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3049 cmpl_type = CMP_TYPE(rxcmp);
3051 switch (cmpl_type) {
3052 case CMPL_BASE_TYPE_RX_L2:
3053 case CMPL_BASE_TYPE_RX_L2_V2:
3054 agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3055 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3059 case CMPL_BASE_TYPE_RX_TPA_END:
3060 if (BNXT_CHIP_P5(rxq->bp)) {
3061 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3063 p5_tpa_end = (void *)rxcmp;
3064 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3066 struct rx_tpa_end_cmpl *tpa_end;
3068 tpa_end = (void *)rxcmp;
3069 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3072 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3077 raw_cons += CMP_LEN(cmpl_type);
3085 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
3087 struct bnxt_rx_queue *rxq = rx_queue;
3088 struct bnxt_cp_ring_info *cpr;
3089 struct bnxt_rx_ring_info *rxr;
3090 uint32_t desc, raw_cons;
3091 struct bnxt *bp = rxq->bp;
3092 struct rx_pkt_cmpl *rxcmp;
3095 rc = is_bnxt_in_error(bp);
3099 if (offset >= rxq->nb_rx_desc)
3106 * For the vector receive case, the completion at the requested
3107 * offset can be indexed directly.
3109 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
3110 if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) {
3111 struct rx_pkt_cmpl *rxcmp;
3114 /* Check status of completion descriptor. */
3115 raw_cons = cpr->cp_raw_cons +
3116 offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2);
3117 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3118 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3120 if (CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3121 return RTE_ETH_RX_DESC_DONE;
3123 /* Check whether rx desc has an mbuf attached. */
3124 cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2);
3125 if (cons >= rxq->rxrearm_start &&
3126 cons < rxq->rxrearm_start + rxq->rxrearm_nb) {
3127 return RTE_ETH_RX_DESC_UNAVAIL;
3130 return RTE_ETH_RX_DESC_AVAIL;
3135 * For the non-vector receive case, scan the completion ring to
3136 * locate the completion descriptor for the requested offset.
3138 raw_cons = cpr->cp_raw_cons;
3141 uint32_t agg_cnt, cons, cmpl_type;
3143 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3144 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3146 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3149 cmpl_type = CMP_TYPE(rxcmp);
3151 switch (cmpl_type) {
3152 case CMPL_BASE_TYPE_RX_L2:
3153 case CMPL_BASE_TYPE_RX_L2_V2:
3154 if (desc == offset) {
3155 cons = rxcmp->opaque;
3156 if (rxr->rx_buf_ring[cons])
3157 return RTE_ETH_RX_DESC_DONE;
3159 return RTE_ETH_RX_DESC_UNAVAIL;
3161 agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3162 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3166 case CMPL_BASE_TYPE_RX_TPA_END:
3168 return RTE_ETH_RX_DESC_DONE;
3170 if (BNXT_CHIP_P5(rxq->bp)) {
3171 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3173 p5_tpa_end = (void *)rxcmp;
3174 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3176 struct rx_tpa_end_cmpl *tpa_end;
3178 tpa_end = (void *)rxcmp;
3179 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3182 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3187 raw_cons += CMP_LEN(cmpl_type);
3191 return RTE_ETH_RX_DESC_AVAIL;
3195 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
3197 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
3198 struct bnxt_tx_ring_info *txr;
3199 struct bnxt_cp_ring_info *cpr;
3200 struct rte_mbuf **tx_buf;
3201 struct tx_pkt_cmpl *txcmp;
3202 uint32_t cons, cp_cons;
3208 rc = is_bnxt_in_error(txq->bp);
3215 if (offset >= txq->nb_tx_desc)
3218 cons = RING_CMP(cpr->cp_ring_struct, offset);
3219 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3220 cp_cons = cpr->cp_raw_cons;
3222 if (cons > cp_cons) {
3223 if (CMPL_VALID(txcmp, cpr->valid))
3224 return RTE_ETH_TX_DESC_UNAVAIL;
3226 if (CMPL_VALID(txcmp, !cpr->valid))
3227 return RTE_ETH_TX_DESC_UNAVAIL;
3229 tx_buf = &txr->tx_buf_ring[cons];
3230 if (*tx_buf == NULL)
3231 return RTE_ETH_TX_DESC_DONE;
3233 return RTE_ETH_TX_DESC_FULL;
3237 bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
3238 const struct rte_flow_ops **ops)
3240 struct bnxt *bp = dev->data->dev_private;
3246 if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3247 struct bnxt_representor *vfr = dev->data->dev_private;
3248 bp = vfr->parent_dev->data->dev_private;
3249 /* parent is deleted while children are still valid */
3251 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error\n",
3252 dev->data->port_id);
3257 ret = is_bnxt_in_error(bp);
3261 /* PMD supports thread-safe flow operations. rte_flow API
3262 * functions can avoid mutex for multi-thread safety.
3264 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3266 if (BNXT_TRUFLOW_EN(bp))
3267 *ops = &bnxt_ulp_rte_flow_ops;
3269 *ops = &bnxt_flow_ops;
3274 static const uint32_t *
3275 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3277 static const uint32_t ptypes[] = {
3278 RTE_PTYPE_L2_ETHER_VLAN,
3279 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3280 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3284 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3285 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3286 RTE_PTYPE_INNER_L4_ICMP,
3287 RTE_PTYPE_INNER_L4_TCP,
3288 RTE_PTYPE_INNER_L4_UDP,
3292 if (!dev->rx_pkt_burst)
3298 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3301 uint32_t reg_base = *reg_arr & 0xfffff000;
3305 for (i = 0; i < count; i++) {
3306 if ((reg_arr[i] & 0xfffff000) != reg_base)
3309 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3310 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3314 static int bnxt_map_ptp_regs(struct bnxt *bp)
3316 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3320 reg_arr = ptp->rx_regs;
3321 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3325 reg_arr = ptp->tx_regs;
3326 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3330 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3331 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3333 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3334 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3339 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3341 rte_write32(0, (uint8_t *)bp->bar0 +
3342 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3343 rte_write32(0, (uint8_t *)bp->bar0 +
3344 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3347 static uint64_t bnxt_cc_read(struct bnxt *bp)
3351 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3352 BNXT_GRCPF_REG_SYNC_TIME));
3353 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3354 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3358 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3360 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3363 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3364 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3365 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3368 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3369 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3370 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3371 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3372 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3373 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3374 rte_read32((uint8_t *)bp->bar0 + ptp->tx_mapped_regs[BNXT_PTP_TX_SEQ]);
3379 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3381 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3382 struct bnxt_pf_info *pf = bp->pf;
3386 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3387 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3388 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3391 port_id = pf->port_id;
3392 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3393 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3395 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3396 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3397 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3398 /* bnxt_clr_rx_ts(bp); TBD */
3402 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3403 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3404 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3405 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3411 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3414 struct bnxt *bp = dev->data->dev_private;
3415 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3420 ns = rte_timespec_to_ns(ts);
3421 /* Set the timecounters to a new value. */
3423 ptp->tx_tstamp_tc.nsec = ns;
3424 ptp->rx_tstamp_tc.nsec = ns;
3430 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3432 struct bnxt *bp = dev->data->dev_private;
3433 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3434 uint64_t ns, systime_cycles = 0;
3440 if (BNXT_CHIP_P5(bp))
3441 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3444 systime_cycles = bnxt_cc_read(bp);
3446 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3447 *ts = rte_ns_to_timespec(ns);
3452 bnxt_timesync_enable(struct rte_eth_dev *dev)
3454 struct bnxt *bp = dev->data->dev_private;
3455 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3463 ptp->tx_tstamp_en = 1;
3464 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3466 rc = bnxt_hwrm_ptp_cfg(bp);
3470 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3471 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3472 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3474 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3475 ptp->tc.cc_shift = shift;
3476 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3478 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3479 ptp->rx_tstamp_tc.cc_shift = shift;
3480 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3482 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3483 ptp->tx_tstamp_tc.cc_shift = shift;
3484 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3486 if (!BNXT_CHIP_P5(bp))
3487 bnxt_map_ptp_regs(bp);
3489 rc = bnxt_ptp_start(bp);
3495 bnxt_timesync_disable(struct rte_eth_dev *dev)
3497 struct bnxt *bp = dev->data->dev_private;
3498 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3504 ptp->tx_tstamp_en = 0;
3507 bnxt_hwrm_ptp_cfg(bp);
3509 if (!BNXT_CHIP_P5(bp))
3510 bnxt_unmap_ptp_regs(bp);
3518 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3519 struct timespec *timestamp,
3520 uint32_t flags __rte_unused)
3522 struct bnxt *bp = dev->data->dev_private;
3523 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3524 uint64_t rx_tstamp_cycles = 0;
3530 if (BNXT_CHIP_P5(bp))
3531 rx_tstamp_cycles = ptp->rx_timestamp;
3533 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3535 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3536 *timestamp = rte_ns_to_timespec(ns);
3541 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3542 struct timespec *timestamp)
3544 struct bnxt *bp = dev->data->dev_private;
3545 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3546 uint64_t tx_tstamp_cycles = 0;
3553 if (BNXT_CHIP_P5(bp))
3554 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3557 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3559 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3560 *timestamp = rte_ns_to_timespec(ns);
3566 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3568 struct bnxt *bp = dev->data->dev_private;
3569 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3574 ptp->tc.nsec += delta;
3575 ptp->tx_tstamp_tc.nsec += delta;
3576 ptp->rx_tstamp_tc.nsec += delta;
3582 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3584 struct bnxt *bp = dev->data->dev_private;
3586 uint32_t dir_entries;
3587 uint32_t entry_length;
3589 rc = is_bnxt_in_error(bp);
3593 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3594 bp->pdev->addr.domain, bp->pdev->addr.bus,
3595 bp->pdev->addr.devid, bp->pdev->addr.function);
3597 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3601 return dir_entries * entry_length;
3605 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3606 struct rte_dev_eeprom_info *in_eeprom)
3608 struct bnxt *bp = dev->data->dev_private;
3613 rc = is_bnxt_in_error(bp);
3617 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3618 bp->pdev->addr.domain, bp->pdev->addr.bus,
3619 bp->pdev->addr.devid, bp->pdev->addr.function,
3620 in_eeprom->offset, in_eeprom->length);
3622 if (in_eeprom->offset == 0) /* special offset value to get directory */
3623 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3626 index = in_eeprom->offset >> 24;
3627 offset = in_eeprom->offset & 0xffffff;
3630 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3631 in_eeprom->length, in_eeprom->data);
3636 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3639 case BNX_DIR_TYPE_CHIMP_PATCH:
3640 case BNX_DIR_TYPE_BOOTCODE:
3641 case BNX_DIR_TYPE_BOOTCODE_2:
3642 case BNX_DIR_TYPE_APE_FW:
3643 case BNX_DIR_TYPE_APE_PATCH:
3644 case BNX_DIR_TYPE_KONG_FW:
3645 case BNX_DIR_TYPE_KONG_PATCH:
3646 case BNX_DIR_TYPE_BONO_FW:
3647 case BNX_DIR_TYPE_BONO_PATCH:
3655 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3658 case BNX_DIR_TYPE_AVS:
3659 case BNX_DIR_TYPE_EXP_ROM_MBA:
3660 case BNX_DIR_TYPE_PCIE:
3661 case BNX_DIR_TYPE_TSCF_UCODE:
3662 case BNX_DIR_TYPE_EXT_PHY:
3663 case BNX_DIR_TYPE_CCM:
3664 case BNX_DIR_TYPE_ISCSI_BOOT:
3665 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3666 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3674 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3676 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3677 bnxt_dir_type_is_other_exec_format(dir_type);
3681 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3682 struct rte_dev_eeprom_info *in_eeprom)
3684 struct bnxt *bp = dev->data->dev_private;
3685 uint8_t index, dir_op;
3686 uint16_t type, ext, ordinal, attr;
3689 rc = is_bnxt_in_error(bp);
3693 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3694 bp->pdev->addr.domain, bp->pdev->addr.bus,
3695 bp->pdev->addr.devid, bp->pdev->addr.function,
3696 in_eeprom->offset, in_eeprom->length);
3699 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3703 type = in_eeprom->magic >> 16;
3705 if (type == 0xffff) { /* special value for directory operations */
3706 index = in_eeprom->magic & 0xff;
3707 dir_op = in_eeprom->magic >> 8;
3711 case 0x0e: /* erase */
3712 if (in_eeprom->offset != ~in_eeprom->magic)
3714 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3720 /* Create or re-write an NVM item: */
3721 if (bnxt_dir_type_is_executable(type) == true)
3723 ext = in_eeprom->magic & 0xffff;
3724 ordinal = in_eeprom->offset >> 16;
3725 attr = in_eeprom->offset & 0xffff;
3727 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3728 in_eeprom->data, in_eeprom->length);
3735 static const struct eth_dev_ops bnxt_dev_ops = {
3736 .dev_infos_get = bnxt_dev_info_get_op,
3737 .dev_close = bnxt_dev_close_op,
3738 .dev_configure = bnxt_dev_configure_op,
3739 .dev_start = bnxt_dev_start_op,
3740 .dev_stop = bnxt_dev_stop_op,
3741 .dev_set_link_up = bnxt_dev_set_link_up_op,
3742 .dev_set_link_down = bnxt_dev_set_link_down_op,
3743 .stats_get = bnxt_stats_get_op,
3744 .stats_reset = bnxt_stats_reset_op,
3745 .rx_queue_setup = bnxt_rx_queue_setup_op,
3746 .rx_queue_release = bnxt_rx_queue_release_op,
3747 .tx_queue_setup = bnxt_tx_queue_setup_op,
3748 .tx_queue_release = bnxt_tx_queue_release_op,
3749 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3750 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3751 .reta_update = bnxt_reta_update_op,
3752 .reta_query = bnxt_reta_query_op,
3753 .rss_hash_update = bnxt_rss_hash_update_op,
3754 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3755 .link_update = bnxt_link_update_op,
3756 .promiscuous_enable = bnxt_promiscuous_enable_op,
3757 .promiscuous_disable = bnxt_promiscuous_disable_op,
3758 .allmulticast_enable = bnxt_allmulticast_enable_op,
3759 .allmulticast_disable = bnxt_allmulticast_disable_op,
3760 .mac_addr_add = bnxt_mac_addr_add_op,
3761 .mac_addr_remove = bnxt_mac_addr_remove_op,
3762 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3763 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3764 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3765 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3766 .vlan_filter_set = bnxt_vlan_filter_set_op,
3767 .vlan_offload_set = bnxt_vlan_offload_set_op,
3768 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3769 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3770 .mtu_set = bnxt_mtu_set_op,
3771 .mac_addr_set = bnxt_set_default_mac_addr_op,
3772 .xstats_get = bnxt_dev_xstats_get_op,
3773 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3774 .xstats_reset = bnxt_dev_xstats_reset_op,
3775 .fw_version_get = bnxt_fw_version_get,
3776 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3777 .rxq_info_get = bnxt_rxq_info_get_op,
3778 .txq_info_get = bnxt_txq_info_get_op,
3779 .rx_burst_mode_get = bnxt_rx_burst_mode_get,
3780 .tx_burst_mode_get = bnxt_tx_burst_mode_get,
3781 .dev_led_on = bnxt_dev_led_on_op,
3782 .dev_led_off = bnxt_dev_led_off_op,
3783 .rx_queue_start = bnxt_rx_queue_start,
3784 .rx_queue_stop = bnxt_rx_queue_stop,
3785 .tx_queue_start = bnxt_tx_queue_start,
3786 .tx_queue_stop = bnxt_tx_queue_stop,
3787 .flow_ops_get = bnxt_flow_ops_get_op,
3788 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3789 .get_eeprom_length = bnxt_get_eeprom_length_op,
3790 .get_eeprom = bnxt_get_eeprom_op,
3791 .set_eeprom = bnxt_set_eeprom_op,
3792 .timesync_enable = bnxt_timesync_enable,
3793 .timesync_disable = bnxt_timesync_disable,
3794 .timesync_read_time = bnxt_timesync_read_time,
3795 .timesync_write_time = bnxt_timesync_write_time,
3796 .timesync_adjust_time = bnxt_timesync_adjust_time,
3797 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3798 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3801 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3805 /* Only pre-map the reset GRC registers using window 3 */
3806 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3807 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3809 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3814 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3816 struct bnxt_error_recovery_info *info = bp->recovery_info;
3817 uint32_t reg_base = 0xffffffff;
3820 /* Only pre-map the monitoring GRC registers using window 2 */
3821 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3822 uint32_t reg = info->status_regs[i];
3824 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3827 if (reg_base == 0xffffffff)
3828 reg_base = reg & 0xfffff000;
3829 if ((reg & 0xfffff000) != reg_base)
3832 /* Use mask 0xffc as the Lower 2 bits indicates
3833 * address space location
3835 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3839 if (reg_base == 0xffffffff)
3842 rte_write32(reg_base, (uint8_t *)bp->bar0 +
3843 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3848 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3850 struct bnxt_error_recovery_info *info = bp->recovery_info;
3851 uint32_t delay = info->delay_after_reset[index];
3852 uint32_t val = info->reset_reg_val[index];
3853 uint32_t reg = info->reset_reg[index];
3854 uint32_t type, offset;
3857 type = BNXT_FW_STATUS_REG_TYPE(reg);
3858 offset = BNXT_FW_STATUS_REG_OFF(reg);
3861 case BNXT_FW_STATUS_REG_TYPE_CFG:
3862 ret = rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3864 PMD_DRV_LOG(ERR, "Failed to write %#x at PCI offset %#x",
3869 case BNXT_FW_STATUS_REG_TYPE_GRC:
3870 offset = bnxt_map_reset_regs(bp, offset);
3871 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3873 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3874 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3877 /* wait on a specific interval of time until core reset is complete */
3879 rte_delay_ms(delay);
3882 static void bnxt_dev_cleanup(struct bnxt *bp)
3884 bp->eth_dev->data->dev_link.link_status = 0;
3885 bp->link_info->link_up = 0;
3886 if (bp->eth_dev->data->dev_started)
3887 bnxt_dev_stop(bp->eth_dev);
3889 bnxt_uninit_resources(bp, true);
3893 bnxt_check_fw_reset_done(struct bnxt *bp)
3895 int timeout = bp->fw_reset_max_msecs;
3900 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
3902 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
3908 } while (timeout--);
3910 if (val == 0xffff) {
3911 PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n");
3918 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3920 struct rte_eth_dev *dev = bp->eth_dev;
3921 struct rte_vlan_filter_conf *vfc;
3925 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3926 vfc = &dev->data->vlan_filter_conf;
3927 vidx = vlan_id / 64;
3928 vbit = vlan_id % 64;
3930 /* Each bit corresponds to a VLAN id */
3931 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3932 rc = bnxt_add_vlan_filter(bp, vlan_id);
3941 static int bnxt_restore_mac_filters(struct bnxt *bp)
3943 struct rte_eth_dev *dev = bp->eth_dev;
3944 struct rte_eth_dev_info dev_info;
3945 struct rte_ether_addr *addr;
3951 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3954 rc = bnxt_dev_info_get_op(dev, &dev_info);
3958 /* replay MAC address configuration */
3959 for (i = 1; i < dev_info.max_mac_addrs; i++) {
3960 addr = &dev->data->mac_addrs[i];
3962 /* skip zero address */
3963 if (rte_is_zero_ether_addr(addr))
3967 pool_mask = dev->data->mac_pool_sel[i];
3970 if (pool_mask & 1ULL) {
3971 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3977 } while (pool_mask);
3983 static int bnxt_restore_filters(struct bnxt *bp)
3985 struct rte_eth_dev *dev = bp->eth_dev;
3988 if (dev->data->all_multicast) {
3989 ret = bnxt_allmulticast_enable_op(dev);
3993 if (dev->data->promiscuous) {
3994 ret = bnxt_promiscuous_enable_op(dev);
3999 ret = bnxt_restore_mac_filters(bp);
4003 ret = bnxt_restore_vlan_filters(bp);
4004 /* TODO restore other filters as well */
4008 static int bnxt_check_fw_ready(struct bnxt *bp)
4010 int timeout = bp->fw_reset_max_msecs;
4014 rc = bnxt_hwrm_poll_ver_get(bp);
4017 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4018 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4019 } while (rc && timeout > 0);
4022 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4027 static void bnxt_dev_recover(void *arg)
4029 struct bnxt *bp = arg;
4032 pthread_mutex_lock(&bp->err_recovery_lock);
4034 if (!bp->fw_reset_min_msecs) {
4035 rc = bnxt_check_fw_reset_done(bp);
4040 /* Clear Error flag so that device re-init should happen */
4041 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4043 rc = bnxt_check_fw_ready(bp);
4047 rc = bnxt_init_resources(bp, true);
4050 "Failed to initialize resources after reset\n");
4053 /* clear reset flag as the device is initialized now */
4054 bp->flags &= ~BNXT_FLAG_FW_RESET;
4056 rc = bnxt_dev_start_op(bp->eth_dev);
4058 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4062 rc = bnxt_restore_filters(bp);
4066 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4067 pthread_mutex_unlock(&bp->err_recovery_lock);
4071 bnxt_dev_stop(bp->eth_dev);
4073 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4074 bnxt_uninit_resources(bp, false);
4075 pthread_mutex_unlock(&bp->err_recovery_lock);
4076 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4079 void bnxt_dev_reset_and_resume(void *arg)
4081 struct bnxt *bp = arg;
4082 uint32_t us = US_PER_MS * bp->fw_reset_min_msecs;
4086 bnxt_dev_cleanup(bp);
4088 bnxt_wait_for_device_shutdown(bp);
4090 /* During some fatal firmware error conditions, the PCI config space
4091 * register 0x2e which normally contains the subsystem ID will become
4092 * 0xffff. This register will revert back to the normal value after
4093 * the chip has completed core reset. If we detect this condition,
4094 * we can poll this config register immediately for the value to revert.
4096 if (bp->flags & BNXT_FLAG_FATAL_ERROR) {
4097 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4099 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4102 if (val == 0xffff) {
4103 bp->fw_reset_min_msecs = 0;
4108 rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp);
4110 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4113 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4115 struct bnxt_error_recovery_info *info = bp->recovery_info;
4116 uint32_t reg = info->status_regs[index];
4117 uint32_t type, offset, val = 0;
4119 type = BNXT_FW_STATUS_REG_TYPE(reg);
4120 offset = BNXT_FW_STATUS_REG_OFF(reg);
4123 case BNXT_FW_STATUS_REG_TYPE_CFG:
4124 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4126 case BNXT_FW_STATUS_REG_TYPE_GRC:
4127 offset = info->mapped_status_regs[index];
4129 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4130 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4138 static int bnxt_fw_reset_all(struct bnxt *bp)
4140 struct bnxt_error_recovery_info *info = bp->recovery_info;
4144 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4145 /* Reset through master function driver */
4146 for (i = 0; i < info->reg_array_cnt; i++)
4147 bnxt_write_fw_reset_reg(bp, i);
4148 /* Wait for time specified by FW after triggering reset */
4149 rte_delay_ms(info->master_func_wait_period_after_reset);
4150 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4151 /* Reset with the help of Kong processor */
4152 rc = bnxt_hwrm_fw_reset(bp);
4154 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4160 static void bnxt_fw_reset_cb(void *arg)
4162 struct bnxt *bp = arg;
4163 struct bnxt_error_recovery_info *info = bp->recovery_info;
4166 /* Only Master function can do FW reset */
4167 if (bnxt_is_master_func(bp) &&
4168 bnxt_is_recovery_enabled(bp)) {
4169 rc = bnxt_fw_reset_all(bp);
4171 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4176 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4177 * EXCEPTION_FATAL_ASYNC event to all the functions
4178 * (including MASTER FUNC). After receiving this Async, all the active
4179 * drivers should treat this case as FW initiated recovery
4181 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4182 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4183 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4185 /* To recover from error */
4186 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4191 /* Driver should poll FW heartbeat, reset_counter with the frequency
4192 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4193 * When the driver detects heartbeat stop or change in reset_counter,
4194 * it has to trigger a reset to recover from the error condition.
4195 * A “master PF” is the function who will have the privilege to
4196 * initiate the chimp reset. The master PF will be elected by the
4197 * firmware and will be notified through async message.
4199 static void bnxt_check_fw_health(void *arg)
4201 struct bnxt *bp = arg;
4202 struct bnxt_error_recovery_info *info = bp->recovery_info;
4203 uint32_t val = 0, wait_msec;
4205 if (!info || !bnxt_is_recovery_enabled(bp) ||
4206 is_bnxt_in_error(bp))
4209 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4210 if (val == info->last_heart_beat)
4213 info->last_heart_beat = val;
4215 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4216 if (val != info->last_reset_counter)
4219 info->last_reset_counter = val;
4221 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4222 bnxt_check_fw_health, (void *)bp);
4226 /* Stop DMA to/from device */
4227 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4228 bp->flags |= BNXT_FLAG_FW_RESET;
4230 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4232 if (bnxt_is_master_func(bp))
4233 wait_msec = info->master_func_wait_period;
4235 wait_msec = info->normal_func_wait_period;
4237 rte_eal_alarm_set(US_PER_MS * wait_msec,
4238 bnxt_fw_reset_cb, (void *)bp);
4241 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4243 uint32_t polling_freq;
4245 pthread_mutex_lock(&bp->health_check_lock);
4247 if (!bnxt_is_recovery_enabled(bp))
4250 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4253 polling_freq = bp->recovery_info->driver_polling_freq;
4255 rte_eal_alarm_set(US_PER_MS * polling_freq,
4256 bnxt_check_fw_health, (void *)bp);
4257 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4260 pthread_mutex_unlock(&bp->health_check_lock);
4263 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4265 if (!bnxt_is_recovery_enabled(bp))
4268 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4269 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4272 static bool bnxt_vf_pciid(uint16_t device_id)
4274 switch (device_id) {
4275 case BROADCOM_DEV_ID_57304_VF:
4276 case BROADCOM_DEV_ID_57406_VF:
4277 case BROADCOM_DEV_ID_5731X_VF:
4278 case BROADCOM_DEV_ID_5741X_VF:
4279 case BROADCOM_DEV_ID_57414_VF:
4280 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4281 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4282 case BROADCOM_DEV_ID_58802_VF:
4283 case BROADCOM_DEV_ID_57500_VF1:
4284 case BROADCOM_DEV_ID_57500_VF2:
4285 case BROADCOM_DEV_ID_58818_VF:
4293 /* Phase 5 device */
4294 static bool bnxt_p5_device(uint16_t device_id)
4296 switch (device_id) {
4297 case BROADCOM_DEV_ID_57508:
4298 case BROADCOM_DEV_ID_57504:
4299 case BROADCOM_DEV_ID_57502:
4300 case BROADCOM_DEV_ID_57508_MF1:
4301 case BROADCOM_DEV_ID_57504_MF1:
4302 case BROADCOM_DEV_ID_57502_MF1:
4303 case BROADCOM_DEV_ID_57508_MF2:
4304 case BROADCOM_DEV_ID_57504_MF2:
4305 case BROADCOM_DEV_ID_57502_MF2:
4306 case BROADCOM_DEV_ID_57500_VF1:
4307 case BROADCOM_DEV_ID_57500_VF2:
4308 case BROADCOM_DEV_ID_58812:
4309 case BROADCOM_DEV_ID_58814:
4310 case BROADCOM_DEV_ID_58818:
4311 case BROADCOM_DEV_ID_58818_VF:
4319 bool bnxt_stratus_device(struct bnxt *bp)
4321 uint16_t device_id = bp->pdev->id.device_id;
4323 switch (device_id) {
4324 case BROADCOM_DEV_ID_STRATUS_NIC:
4325 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4326 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4334 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev)
4336 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4337 struct bnxt *bp = eth_dev->data->dev_private;
4339 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4340 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4341 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4342 if (!bp->bar0 || !bp->doorbell_base) {
4343 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4347 bp->eth_dev = eth_dev;
4353 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4354 struct bnxt_ctx_pg_info *ctx_pg,
4359 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4360 const struct rte_memzone *mz = NULL;
4361 char mz_name[RTE_MEMZONE_NAMESIZE];
4362 rte_iova_t mz_phys_addr;
4363 uint64_t valid_bits = 0;
4370 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4372 rmem->page_size = BNXT_PAGE_SIZE;
4373 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4374 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4375 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4377 valid_bits = PTU_PTE_VALID;
4379 if (rmem->nr_pages > 1) {
4380 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4381 "bnxt_ctx_pg_tbl%s_%x_%d",
4382 suffix, idx, bp->eth_dev->data->port_id);
4383 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4384 mz = rte_memzone_lookup(mz_name);
4386 mz = rte_memzone_reserve_aligned(mz_name,
4390 RTE_MEMZONE_SIZE_HINT_ONLY |
4391 RTE_MEMZONE_IOVA_CONTIG,
4397 memset(mz->addr, 0, mz->len);
4398 mz_phys_addr = mz->iova;
4400 rmem->pg_tbl = mz->addr;
4401 rmem->pg_tbl_map = mz_phys_addr;
4402 rmem->pg_tbl_mz = mz;
4405 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4406 suffix, idx, bp->eth_dev->data->port_id);
4407 mz = rte_memzone_lookup(mz_name);
4409 mz = rte_memzone_reserve_aligned(mz_name,
4413 RTE_MEMZONE_SIZE_HINT_ONLY |
4414 RTE_MEMZONE_IOVA_CONTIG,
4420 memset(mz->addr, 0, mz->len);
4421 mz_phys_addr = mz->iova;
4423 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4424 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4425 rmem->dma_arr[i] = mz_phys_addr + sz;
4427 if (rmem->nr_pages > 1) {
4428 if (i == rmem->nr_pages - 2 &&
4429 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4430 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4431 else if (i == rmem->nr_pages - 1 &&
4432 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4433 valid_bits |= PTU_PTE_LAST;
4435 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4441 if (rmem->vmem_size)
4442 rmem->vmem = (void **)mz->addr;
4443 rmem->dma_arr[0] = mz_phys_addr;
4447 static void bnxt_free_ctx_mem(struct bnxt *bp)
4451 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4454 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4455 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4456 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4457 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4458 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4459 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4460 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4461 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4462 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4463 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4464 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4466 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4467 if (bp->ctx->tqm_mem[i])
4468 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4475 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4477 #define min_t(type, x, y) ({ \
4478 type __min1 = (x); \
4479 type __min2 = (y); \
4480 __min1 < __min2 ? __min1 : __min2; })
4482 #define max_t(type, x, y) ({ \
4483 type __max1 = (x); \
4484 type __max2 = (y); \
4485 __max1 > __max2 ? __max1 : __max2; })
4487 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4489 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4491 struct bnxt_ctx_pg_info *ctx_pg;
4492 struct bnxt_ctx_mem_info *ctx;
4493 uint32_t mem_size, ena, entries;
4494 uint32_t entries_sp, min;
4497 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4499 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4503 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4506 ctx_pg = &ctx->qp_mem;
4507 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4508 if (ctx->qp_entry_size) {
4509 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4510 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4515 ctx_pg = &ctx->srq_mem;
4516 ctx_pg->entries = ctx->srq_max_l2_entries;
4517 if (ctx->srq_entry_size) {
4518 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4519 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4524 ctx_pg = &ctx->cq_mem;
4525 ctx_pg->entries = ctx->cq_max_l2_entries;
4526 if (ctx->cq_entry_size) {
4527 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4528 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4533 ctx_pg = &ctx->vnic_mem;
4534 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4535 ctx->vnic_max_ring_table_entries;
4536 if (ctx->vnic_entry_size) {
4537 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4538 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4543 ctx_pg = &ctx->stat_mem;
4544 ctx_pg->entries = ctx->stat_max_entries;
4545 if (ctx->stat_entry_size) {
4546 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4547 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4552 min = ctx->tqm_min_entries_per_ring;
4554 entries_sp = ctx->qp_max_l2_entries +
4555 ctx->vnic_max_vnic_entries +
4556 2 * ctx->qp_min_qp1_entries + min;
4557 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4559 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4560 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4561 entries = clamp_t(uint32_t, entries, min,
4562 ctx->tqm_max_entries_per_ring);
4563 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4564 /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7.
4565 * i > 8 is other ext rings.
4567 ctx_pg = ctx->tqm_mem[i];
4568 ctx_pg->entries = i ? entries : entries_sp;
4569 if (ctx->tqm_entry_size) {
4570 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4571 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size,
4576 if (i < BNXT_MAX_TQM_LEGACY_RINGS)
4577 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4579 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8;
4582 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4583 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4586 "Failed to configure context mem: rc = %d\n", rc);
4588 ctx->flags |= BNXT_CTX_FLAG_INITED;
4593 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4595 struct rte_pci_device *pci_dev = bp->pdev;
4596 char mz_name[RTE_MEMZONE_NAMESIZE];
4597 const struct rte_memzone *mz = NULL;
4598 uint32_t total_alloc_len;
4599 rte_iova_t mz_phys_addr;
4601 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4604 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4605 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4606 pci_dev->addr.bus, pci_dev->addr.devid,
4607 pci_dev->addr.function, "rx_port_stats");
4608 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4609 mz = rte_memzone_lookup(mz_name);
4611 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4612 sizeof(struct rx_port_stats_ext) + 512);
4614 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4617 RTE_MEMZONE_SIZE_HINT_ONLY |
4618 RTE_MEMZONE_IOVA_CONTIG);
4622 memset(mz->addr, 0, mz->len);
4623 mz_phys_addr = mz->iova;
4625 bp->rx_mem_zone = (const void *)mz;
4626 bp->hw_rx_port_stats = mz->addr;
4627 bp->hw_rx_port_stats_map = mz_phys_addr;
4629 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4630 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4631 pci_dev->addr.bus, pci_dev->addr.devid,
4632 pci_dev->addr.function, "tx_port_stats");
4633 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4634 mz = rte_memzone_lookup(mz_name);
4636 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4637 sizeof(struct tx_port_stats_ext) + 512);
4639 mz = rte_memzone_reserve(mz_name,
4643 RTE_MEMZONE_SIZE_HINT_ONLY |
4644 RTE_MEMZONE_IOVA_CONTIG);
4648 memset(mz->addr, 0, mz->len);
4649 mz_phys_addr = mz->iova;
4651 bp->tx_mem_zone = (const void *)mz;
4652 bp->hw_tx_port_stats = mz->addr;
4653 bp->hw_tx_port_stats_map = mz_phys_addr;
4654 bp->flags |= BNXT_FLAG_PORT_STATS;
4656 /* Display extended statistics if FW supports it */
4657 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4658 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4659 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4662 bp->hw_rx_port_stats_ext = (void *)
4663 ((uint8_t *)bp->hw_rx_port_stats +
4664 sizeof(struct rx_port_stats));
4665 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4666 sizeof(struct rx_port_stats);
4667 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4669 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4670 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4671 bp->hw_tx_port_stats_ext = (void *)
4672 ((uint8_t *)bp->hw_tx_port_stats +
4673 sizeof(struct tx_port_stats));
4674 bp->hw_tx_port_stats_ext_map =
4675 bp->hw_tx_port_stats_map +
4676 sizeof(struct tx_port_stats);
4677 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4683 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4685 struct bnxt *bp = eth_dev->data->dev_private;
4688 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4689 RTE_ETHER_ADDR_LEN *
4692 if (eth_dev->data->mac_addrs == NULL) {
4693 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4697 if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4701 /* Generate a random MAC address, if none was assigned by PF */
4702 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4703 bnxt_eth_hw_addr_random(bp->mac_addr);
4705 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4706 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4707 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4709 rc = bnxt_hwrm_set_mac(bp);
4714 /* Copy the permanent MAC from the FUNC_QCAPS response */
4715 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4720 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4724 /* MAC is already configured in FW */
4725 if (BNXT_HAS_DFLT_MAC_SET(bp))
4728 /* Restore the old MAC configured */
4729 rc = bnxt_hwrm_set_mac(bp);
4731 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4736 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4741 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
4743 if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
4744 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
4745 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
4746 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
4747 BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
4748 BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
4752 bnxt_get_svif(uint16_t port_id, bool func_svif,
4753 enum bnxt_ulp_intf_type type)
4755 struct rte_eth_dev *eth_dev;
4758 eth_dev = &rte_eth_devices[port_id];
4759 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4760 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4764 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4767 eth_dev = vfr->parent_dev;
4770 bp = eth_dev->data->dev_private;
4772 return func_svif ? bp->func_svif : bp->port_svif;
4776 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
4778 struct rte_eth_dev *eth_dev;
4779 struct bnxt_vnic_info *vnic;
4782 eth_dev = &rte_eth_devices[port];
4783 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4784 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4788 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4789 return vfr->dflt_vnic_id;
4791 eth_dev = vfr->parent_dev;
4794 bp = eth_dev->data->dev_private;
4796 vnic = BNXT_GET_DEFAULT_VNIC(bp);
4798 return vnic->fw_vnic_id;
4802 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
4804 struct rte_eth_dev *eth_dev;
4807 eth_dev = &rte_eth_devices[port];
4808 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4809 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4813 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4816 eth_dev = vfr->parent_dev;
4819 bp = eth_dev->data->dev_private;
4824 enum bnxt_ulp_intf_type
4825 bnxt_get_interface_type(uint16_t port)
4827 struct rte_eth_dev *eth_dev;
4830 eth_dev = &rte_eth_devices[port];
4831 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
4832 return BNXT_ULP_INTF_TYPE_VF_REP;
4834 bp = eth_dev->data->dev_private;
4836 return BNXT_ULP_INTF_TYPE_PF;
4837 else if (BNXT_VF_IS_TRUSTED(bp))
4838 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
4839 else if (BNXT_VF(bp))
4840 return BNXT_ULP_INTF_TYPE_VF;
4842 return BNXT_ULP_INTF_TYPE_INVALID;
4846 bnxt_get_phy_port_id(uint16_t port_id)
4848 struct bnxt_representor *vfr;
4849 struct rte_eth_dev *eth_dev;
4852 eth_dev = &rte_eth_devices[port_id];
4853 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4854 vfr = eth_dev->data->dev_private;
4858 eth_dev = vfr->parent_dev;
4861 bp = eth_dev->data->dev_private;
4863 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
4867 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
4869 struct rte_eth_dev *eth_dev;
4872 eth_dev = &rte_eth_devices[port_id];
4873 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4874 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4878 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4879 return vfr->fw_fid - 1;
4881 eth_dev = vfr->parent_dev;
4884 bp = eth_dev->data->dev_private;
4886 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
4890 bnxt_get_vport(uint16_t port_id)
4892 return (1 << bnxt_get_phy_port_id(port_id));
4895 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
4897 struct bnxt_error_recovery_info *info = bp->recovery_info;
4900 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
4901 memset(info, 0, sizeof(*info));
4905 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4908 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4911 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4913 bp->recovery_info = info;
4916 static void bnxt_check_fw_status(struct bnxt *bp)
4920 if (!(bp->recovery_info &&
4921 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
4924 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
4925 if (fw_status != BNXT_FW_STATUS_HEALTHY)
4926 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
4930 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
4932 struct bnxt_error_recovery_info *info = bp->recovery_info;
4933 uint32_t status_loc;
4936 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
4937 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4938 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4939 BNXT_GRCP_WINDOW_2_BASE +
4940 offsetof(struct hcomm_status,
4942 /* If the signature is absent, then FW does not support this feature */
4943 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
4944 HCOMM_STATUS_SIGNATURE_VAL)
4948 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4952 bp->recovery_info = info;
4954 memset(info, 0, sizeof(*info));
4957 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4958 BNXT_GRCP_WINDOW_2_BASE +
4959 offsetof(struct hcomm_status,
4962 /* Only pre-map the FW health status GRC register */
4963 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
4966 info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
4967 info->mapped_status_regs[BNXT_FW_STATUS_REG] =
4968 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
4970 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
4971 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4973 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
4978 /* This function gets the FW version along with the
4979 * capabilities(MAX and current) of the function, vnic,
4980 * error recovery, phy and other chip related info
4982 static int bnxt_get_config(struct bnxt *bp)
4989 rc = bnxt_map_hcomm_fw_status_reg(bp);
4993 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
4995 bnxt_check_fw_status(bp);
4999 rc = bnxt_hwrm_func_reset(bp);
5003 rc = bnxt_hwrm_vnic_qcaps(bp);
5007 rc = bnxt_hwrm_queue_qportcfg(bp);
5011 /* Get the MAX capabilities for this function.
5012 * This function also allocates context memory for TQM rings and
5013 * informs the firmware about this allocated backing store memory.
5015 rc = bnxt_hwrm_func_qcaps(bp);
5019 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5023 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5027 bnxt_hwrm_port_mac_qcfg(bp);
5029 bnxt_hwrm_parent_pf_qcfg(bp);
5031 bnxt_hwrm_port_phy_qcaps(bp);
5033 bnxt_alloc_error_recovery_info(bp);
5034 /* Get the adapter error recovery support info */
5035 rc = bnxt_hwrm_error_recovery_qcfg(bp);
5037 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5039 bnxt_hwrm_port_led_qcaps(bp);
5045 bnxt_init_locks(struct bnxt *bp)
5049 err = pthread_mutex_init(&bp->flow_lock, NULL);
5051 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5055 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5057 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5061 err = pthread_mutex_init(&bp->health_check_lock, NULL);
5063 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5067 err = pthread_mutex_init(&bp->err_recovery_lock, NULL);
5069 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n");
5074 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5078 rc = bnxt_get_config(bp);
5082 if (!reconfig_dev) {
5083 rc = bnxt_setup_mac_addr(bp->eth_dev);
5087 rc = bnxt_restore_dflt_mac(bp);
5092 bnxt_config_vf_req_fwd(bp);
5094 rc = bnxt_hwrm_func_driver_register(bp);
5096 PMD_DRV_LOG(ERR, "Failed to register driver");
5101 if (bp->pdev->max_vfs) {
5102 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5104 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5108 rc = bnxt_hwrm_allocate_pf_only(bp);
5111 "Failed to allocate PF resources");
5117 rc = bnxt_alloc_mem(bp, reconfig_dev);
5121 rc = bnxt_setup_int(bp);
5125 rc = bnxt_request_int(bp);
5129 rc = bnxt_init_ctx_mem(bp);
5131 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5139 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5140 const char *value, void *opaque_arg)
5142 struct bnxt *bp = opaque_arg;
5143 unsigned long truflow;
5146 if (!value || !opaque_arg) {
5148 "Invalid parameter passed to truflow devargs.\n");
5152 truflow = strtoul(value, &end, 10);
5153 if (end == NULL || *end != '\0' ||
5154 (truflow == ULONG_MAX && errno == ERANGE)) {
5156 "Invalid parameter passed to truflow devargs.\n");
5160 if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5162 "Invalid value passed to truflow devargs.\n");
5167 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5168 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5170 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
5171 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
5178 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5179 const char *value, void *opaque_arg)
5181 struct bnxt *bp = opaque_arg;
5182 unsigned long flow_xstat;
5185 if (!value || !opaque_arg) {
5187 "Invalid parameter passed to flow_xstat devarg.\n");
5191 flow_xstat = strtoul(value, &end, 10);
5192 if (end == NULL || *end != '\0' ||
5193 (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5195 "Invalid parameter passed to flow_xstat devarg.\n");
5199 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5201 "Invalid value passed to flow_xstat devarg.\n");
5205 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5206 if (BNXT_FLOW_XSTATS_EN(bp))
5207 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5213 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5214 const char *value, void *opaque_arg)
5216 struct bnxt *bp = opaque_arg;
5217 unsigned long max_num_kflows;
5220 if (!value || !opaque_arg) {
5222 "Invalid parameter passed to max_num_kflows devarg.\n");
5226 max_num_kflows = strtoul(value, &end, 10);
5227 if (end == NULL || *end != '\0' ||
5228 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5230 "Invalid parameter passed to max_num_kflows devarg.\n");
5234 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5236 "Invalid value passed to max_num_kflows devarg.\n");
5240 bp->max_num_kflows = max_num_kflows;
5241 if (bp->max_num_kflows)
5242 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5249 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5250 const char *value, void *opaque_arg)
5252 struct bnxt_representor *vfr_bp = opaque_arg;
5253 unsigned long rep_is_pf;
5256 if (!value || !opaque_arg) {
5258 "Invalid parameter passed to rep_is_pf devargs.\n");
5262 rep_is_pf = strtoul(value, &end, 10);
5263 if (end == NULL || *end != '\0' ||
5264 (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5266 "Invalid parameter passed to rep_is_pf devargs.\n");
5270 if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5272 "Invalid value passed to rep_is_pf devargs.\n");
5276 vfr_bp->flags |= rep_is_pf;
5277 if (BNXT_REP_PF(vfr_bp))
5278 PMD_DRV_LOG(INFO, "PF representor\n");
5280 PMD_DRV_LOG(INFO, "VF representor\n");
5286 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5287 const char *value, void *opaque_arg)
5289 struct bnxt_representor *vfr_bp = opaque_arg;
5290 unsigned long rep_based_pf;
5293 if (!value || !opaque_arg) {
5295 "Invalid parameter passed to rep_based_pf "
5300 rep_based_pf = strtoul(value, &end, 10);
5301 if (end == NULL || *end != '\0' ||
5302 (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5304 "Invalid parameter passed to rep_based_pf "
5309 if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5311 "Invalid value passed to rep_based_pf devargs.\n");
5315 vfr_bp->rep_based_pf = rep_based_pf;
5316 vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
5318 PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5324 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5325 const char *value, void *opaque_arg)
5327 struct bnxt_representor *vfr_bp = opaque_arg;
5328 unsigned long rep_q_r2f;
5331 if (!value || !opaque_arg) {
5333 "Invalid parameter passed to rep_q_r2f "
5338 rep_q_r2f = strtoul(value, &end, 10);
5339 if (end == NULL || *end != '\0' ||
5340 (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5342 "Invalid parameter passed to rep_q_r2f "
5347 if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5349 "Invalid value passed to rep_q_r2f devargs.\n");
5353 vfr_bp->rep_q_r2f = rep_q_r2f;
5354 vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5355 PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5361 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5362 const char *value, void *opaque_arg)
5364 struct bnxt_representor *vfr_bp = opaque_arg;
5365 unsigned long rep_q_f2r;
5368 if (!value || !opaque_arg) {
5370 "Invalid parameter passed to rep_q_f2r "
5375 rep_q_f2r = strtoul(value, &end, 10);
5376 if (end == NULL || *end != '\0' ||
5377 (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5379 "Invalid parameter passed to rep_q_f2r "
5384 if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5386 "Invalid value passed to rep_q_f2r devargs.\n");
5390 vfr_bp->rep_q_f2r = rep_q_f2r;
5391 vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5392 PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5398 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5399 const char *value, void *opaque_arg)
5401 struct bnxt_representor *vfr_bp = opaque_arg;
5402 unsigned long rep_fc_r2f;
5405 if (!value || !opaque_arg) {
5407 "Invalid parameter passed to rep_fc_r2f "
5412 rep_fc_r2f = strtoul(value, &end, 10);
5413 if (end == NULL || *end != '\0' ||
5414 (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5416 "Invalid parameter passed to rep_fc_r2f "
5421 if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5423 "Invalid value passed to rep_fc_r2f devargs.\n");
5427 vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5428 vfr_bp->rep_fc_r2f = rep_fc_r2f;
5429 PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5435 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5436 const char *value, void *opaque_arg)
5438 struct bnxt_representor *vfr_bp = opaque_arg;
5439 unsigned long rep_fc_f2r;
5442 if (!value || !opaque_arg) {
5444 "Invalid parameter passed to rep_fc_f2r "
5449 rep_fc_f2r = strtoul(value, &end, 10);
5450 if (end == NULL || *end != '\0' ||
5451 (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5453 "Invalid parameter passed to rep_fc_f2r "
5458 if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5460 "Invalid value passed to rep_fc_f2r devargs.\n");
5464 vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5465 vfr_bp->rep_fc_f2r = rep_fc_f2r;
5466 PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5472 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5474 struct rte_kvargs *kvlist;
5477 if (devargs == NULL)
5480 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5485 * Handler for "truflow" devarg.
5486 * Invoked as for ex: "-a 0000:00:0d.0,host-based-truflow=1"
5488 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5489 bnxt_parse_devarg_truflow, bp);
5494 * Handler for "flow_xstat" devarg.
5495 * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5497 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5498 bnxt_parse_devarg_flow_xstat, bp);
5503 * Handler for "max_num_kflows" devarg.
5504 * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5506 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5507 bnxt_parse_devarg_max_num_kflows, bp);
5512 rte_kvargs_free(kvlist);
5516 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5520 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5521 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5524 "Failed to alloc switch domain: %d\n", rc);
5527 "Switch domain allocated %d\n",
5528 bp->switch_domain_id);
5534 /* Allocate and initialize various fields in bnxt struct that
5535 * need to be allocated/destroyed only once in the lifetime of the driver
5537 static int bnxt_drv_init(struct rte_eth_dev *eth_dev)
5539 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5540 struct bnxt *bp = eth_dev->data->dev_private;
5543 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5545 if (bnxt_vf_pciid(pci_dev->id.device_id))
5546 bp->flags |= BNXT_FLAG_VF;
5548 if (bnxt_p5_device(pci_dev->id.device_id))
5549 bp->flags |= BNXT_FLAG_CHIP_P5;
5551 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5552 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5553 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5554 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5555 bp->flags |= BNXT_FLAG_STINGRAY;
5557 if (BNXT_TRUFLOW_EN(bp)) {
5558 /* extra mbuf field is required to store CFA code from mark */
5559 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5560 .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5561 .size = sizeof(bnxt_cfa_code_dynfield_t),
5562 .align = __alignof__(bnxt_cfa_code_dynfield_t),
5564 bnxt_cfa_code_dynfield_offset =
5565 rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5566 if (bnxt_cfa_code_dynfield_offset < 0) {
5568 "Failed to register mbuf field for TruFlow mark\n");
5573 rc = bnxt_map_pci_bars(eth_dev);
5576 "Failed to initialize board rc: %x\n", rc);
5580 rc = bnxt_alloc_pf_info(bp);
5584 rc = bnxt_alloc_link_info(bp);
5588 rc = bnxt_alloc_parent_info(bp);
5592 rc = bnxt_alloc_hwrm_resources(bp);
5595 "Failed to allocate response buffer rc: %x\n", rc);
5598 rc = bnxt_alloc_leds_info(bp);
5602 rc = bnxt_alloc_cos_queues(bp);
5606 rc = bnxt_init_locks(bp);
5610 rc = bnxt_alloc_switch_domain(bp);
5618 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5620 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5621 static int version_printed;
5625 if (version_printed++ == 0)
5626 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5628 eth_dev->dev_ops = &bnxt_dev_ops;
5629 eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5630 eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5631 eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5632 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5633 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5636 * For secondary processes, we don't initialise any further
5637 * as primary has already done this work.
5639 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5642 rte_eth_copy_pci_info(eth_dev, pci_dev);
5643 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
5645 bp = eth_dev->data->dev_private;
5647 /* Parse dev arguments passed on when starting the DPDK application. */
5648 rc = bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5652 rc = bnxt_drv_init(eth_dev);
5656 rc = bnxt_init_resources(bp, false);
5660 rc = bnxt_alloc_stats_mem(bp);
5665 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5666 pci_dev->mem_resource[0].phys_addr,
5667 pci_dev->mem_resource[0].addr);
5672 bnxt_dev_uninit(eth_dev);
5677 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5686 ctx->dma = RTE_BAD_IOVA;
5687 ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5690 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5692 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5693 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5694 bp->flow_stat->rx_fc_out_tbl.ctx_id,
5695 bp->flow_stat->max_fc,
5698 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5699 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5700 bp->flow_stat->tx_fc_out_tbl.ctx_id,
5701 bp->flow_stat->max_fc,
5704 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5705 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5706 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5708 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5709 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5710 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5712 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5713 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5714 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5716 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5717 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5718 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5721 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5723 bnxt_unregister_fc_ctx_mem(bp);
5725 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5726 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5727 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5728 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5731 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5733 if (BNXT_FLOW_XSTATS_EN(bp))
5734 bnxt_uninit_fc_ctx_mem(bp);
5738 bnxt_free_error_recovery_info(struct bnxt *bp)
5740 rte_free(bp->recovery_info);
5741 bp->recovery_info = NULL;
5742 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5746 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5751 bnxt_free_mem(bp, reconfig_dev);
5753 bnxt_hwrm_func_buf_unrgtr(bp);
5754 rte_free(bp->pf->vf_req_buf);
5756 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5757 bp->flags &= ~BNXT_FLAG_REGISTERED;
5758 bnxt_free_ctx_mem(bp);
5759 if (!reconfig_dev) {
5760 bnxt_free_hwrm_resources(bp);
5761 bnxt_free_error_recovery_info(bp);
5764 bnxt_uninit_ctx_mem(bp);
5766 bnxt_free_flow_stats_info(bp);
5767 bnxt_free_rep_info(bp);
5768 rte_free(bp->ptp_cfg);
5774 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5776 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5779 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5781 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5782 bnxt_dev_close_op(eth_dev);
5787 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5789 struct bnxt *bp = eth_dev->data->dev_private;
5790 struct rte_eth_dev *vf_rep_eth_dev;
5796 for (i = 0; i < bp->num_reps; i++) {
5797 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5798 if (!vf_rep_eth_dev)
5800 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
5801 vf_rep_eth_dev->data->port_id);
5802 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
5804 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
5805 eth_dev->data->port_id);
5806 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5811 static void bnxt_free_rep_info(struct bnxt *bp)
5813 rte_free(bp->rep_info);
5814 bp->rep_info = NULL;
5815 rte_free(bp->cfa_code_map);
5816 bp->cfa_code_map = NULL;
5819 static int bnxt_init_rep_info(struct bnxt *bp)
5826 bp->rep_info = rte_zmalloc("bnxt_rep_info",
5827 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5829 if (!bp->rep_info) {
5830 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5833 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5834 sizeof(*bp->cfa_code_map) *
5835 BNXT_MAX_CFA_CODE, 0);
5836 if (!bp->cfa_code_map) {
5837 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5838 bnxt_free_rep_info(bp);
5842 for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5843 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5845 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5847 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5848 bnxt_free_rep_info(bp);
5852 rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
5854 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
5855 bnxt_free_rep_info(bp);
5862 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5863 struct rte_eth_devargs *eth_da,
5864 struct rte_eth_dev *backing_eth_dev,
5865 const char *dev_args)
5867 struct rte_eth_dev *vf_rep_eth_dev;
5868 char name[RTE_ETH_NAME_MAX_LEN];
5869 struct bnxt *backing_bp;
5872 struct rte_kvargs *kvlist = NULL;
5874 if (eth_da->type == RTE_ETH_REPRESENTOR_NONE)
5876 if (eth_da->type != RTE_ETH_REPRESENTOR_VF) {
5877 PMD_DRV_LOG(ERR, "unsupported representor type %d\n",
5881 num_rep = eth_da->nb_representor_ports;
5882 if (num_rep > BNXT_MAX_VF_REPS) {
5883 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5884 num_rep, BNXT_MAX_VF_REPS);
5888 if (num_rep >= RTE_MAX_ETHPORTS) {
5890 "nb_representor_ports = %d > %d MAX ETHPORTS\n",
5891 num_rep, RTE_MAX_ETHPORTS);
5895 backing_bp = backing_eth_dev->data->dev_private;
5897 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
5899 "Not a PF or trusted VF. No Representor support\n");
5900 /* Returning an error is not an option.
5901 * Applications are not handling this correctly
5906 if (bnxt_init_rep_info(backing_bp))
5909 for (i = 0; i < num_rep; i++) {
5910 struct bnxt_representor representor = {
5911 .vf_id = eth_da->representor_ports[i],
5912 .switch_domain_id = backing_bp->switch_domain_id,
5913 .parent_dev = backing_eth_dev
5916 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
5917 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
5918 representor.vf_id, BNXT_MAX_VF_REPS);
5922 /* representor port net_bdf_port */
5923 snprintf(name, sizeof(name), "net_%s_representor_%d",
5924 pci_dev->device.name, eth_da->representor_ports[i]);
5926 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
5929 * Handler for "rep_is_pf" devarg.
5930 * Invoked as for ex: "-a 000:00:0d.0,
5931 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5933 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
5934 bnxt_parse_devarg_rep_is_pf,
5935 (void *)&representor);
5941 * Handler for "rep_based_pf" devarg.
5942 * Invoked as for ex: "-a 000:00:0d.0,
5943 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5945 ret = rte_kvargs_process(kvlist,
5946 BNXT_DEVARG_REP_BASED_PF,
5947 bnxt_parse_devarg_rep_based_pf,
5948 (void *)&representor);
5954 * Handler for "rep_based_pf" devarg.
5955 * Invoked as for ex: "-a 000:00:0d.0,
5956 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5958 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
5959 bnxt_parse_devarg_rep_q_r2f,
5960 (void *)&representor);
5966 * Handler for "rep_based_pf" devarg.
5967 * Invoked as for ex: "-a 000:00:0d.0,
5968 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5970 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
5971 bnxt_parse_devarg_rep_q_f2r,
5972 (void *)&representor);
5978 * Handler for "rep_based_pf" devarg.
5979 * Invoked as for ex: "-a 000:00:0d.0,
5980 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5982 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
5983 bnxt_parse_devarg_rep_fc_r2f,
5984 (void *)&representor);
5990 * Handler for "rep_based_pf" devarg.
5991 * Invoked as for ex: "-a 000:00:0d.0,
5992 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5994 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
5995 bnxt_parse_devarg_rep_fc_f2r,
5996 (void *)&representor);
6003 ret = rte_eth_dev_create(&pci_dev->device, name,
6004 sizeof(struct bnxt_representor),
6006 bnxt_representor_init,
6009 PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6010 "representor %s.", name);
6014 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6015 if (!vf_rep_eth_dev) {
6016 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6017 " for VF-Rep: %s.", name);
6022 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6023 backing_eth_dev->data->port_id);
6024 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6026 backing_bp->num_reps++;
6030 rte_kvargs_free(kvlist);
6034 /* If num_rep > 1, then rollback already created
6035 * ports, since we'll be failing the probe anyway
6038 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6040 rte_kvargs_free(kvlist);
6045 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6046 struct rte_pci_device *pci_dev)
6048 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6049 struct rte_eth_dev *backing_eth_dev;
6053 if (pci_dev->device.devargs) {
6054 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6060 num_rep = eth_da.nb_representor_ports;
6061 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6064 /* We could come here after first level of probe is already invoked
6065 * as part of an application bringup(OVS-DPDK vswitchd), so first check
6066 * for already allocated eth_dev for the backing device (PF/Trusted VF)
6068 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6069 if (backing_eth_dev == NULL) {
6070 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6071 sizeof(struct bnxt),
6072 eth_dev_pci_specific_init, pci_dev,
6073 bnxt_dev_init, NULL);
6075 if (ret || !num_rep)
6078 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6080 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6081 backing_eth_dev->data->port_id);
6086 /* probe representor ports now */
6087 ret = bnxt_rep_port_probe(pci_dev, ð_da, backing_eth_dev,
6088 pci_dev->device.devargs->args);
6093 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6095 struct rte_eth_dev *eth_dev;
6097 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6099 return 0; /* Invoked typically only by OVS-DPDK, by the
6100 * time it comes here the eth_dev is already
6101 * deleted by rte_eth_dev_close(), so returning
6102 * +ve value will at least help in proper cleanup
6105 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6106 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6107 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6108 return rte_eth_dev_destroy(eth_dev,
6109 bnxt_representor_uninit);
6111 return rte_eth_dev_destroy(eth_dev,
6114 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6118 static struct rte_pci_driver bnxt_rte_pmd = {
6119 .id_table = bnxt_pci_id_map,
6120 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6121 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6124 .probe = bnxt_pci_probe,
6125 .remove = bnxt_pci_remove,
6129 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6131 if (strcmp(dev->device->driver->name, drv->driver.name))
6137 bool is_bnxt_supported(struct rte_eth_dev *dev)
6139 return is_device_supported(dev, &bnxt_rte_pmd);
6142 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
6143 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6144 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6145 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");