4 * Copyright(c) Broadcom Limited.
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8 * modification, are permitted provided that the following conditions
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 #include <rte_ethdev.h>
39 #include <rte_malloc.h>
40 #include <rte_cycles.h>
44 #include "bnxt_filter.h"
45 #include "bnxt_hwrm.h"
46 #include "bnxt_ring.h"
49 #include "bnxt_stats.h"
52 #include "bnxt_vnic.h"
53 #include "hsi_struct_def_dpdk.h"
55 #define DRV_MODULE_NAME "bnxt"
56 static const char bnxt_version[] =
57 "Broadcom Cumulus driver " DRV_MODULE_NAME "\n";
59 #define PCI_VENDOR_ID_BROADCOM 0x14E4
61 #define BROADCOM_DEV_ID_57301 0x16c8
62 #define BROADCOM_DEV_ID_57302 0x16c9
63 #define BROADCOM_DEV_ID_57304_PF 0x16ca
64 #define BROADCOM_DEV_ID_57304_VF 0x16cb
65 #define BROADCOM_DEV_ID_57402 0x16d0
66 #define BROADCOM_DEV_ID_57404 0x16d1
67 #define BROADCOM_DEV_ID_57406_PF 0x16d2
68 #define BROADCOM_DEV_ID_57406_VF 0x16d3
69 #define BROADCOM_DEV_ID_57406_MF 0x16d4
70 #define BROADCOM_DEV_ID_57314 0x16df
72 static struct rte_pci_id bnxt_pci_id_map[] = {
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
83 { .vendor_id = 0, /* sentinel */ },
86 #define BNXT_ETH_RSS_SUPPORT ( \
88 ETH_RSS_NONFRAG_IPV4_TCP | \
89 ETH_RSS_NONFRAG_IPV4_UDP | \
91 ETH_RSS_NONFRAG_IPV6_TCP | \
92 ETH_RSS_NONFRAG_IPV6_UDP)
94 /***********************/
97 * High level utility functions
100 static void bnxt_free_mem(struct bnxt *bp)
102 bnxt_free_filter_mem(bp);
103 bnxt_free_vnic_attributes(bp);
104 bnxt_free_vnic_mem(bp);
107 bnxt_free_tx_rings(bp);
108 bnxt_free_rx_rings(bp);
109 bnxt_free_def_cp_ring(bp);
112 static int bnxt_alloc_mem(struct bnxt *bp)
116 /* Default completion ring */
117 rc = bnxt_init_def_ring_struct(bp, SOCKET_ID_ANY);
121 rc = bnxt_alloc_rings(bp, 0, NULL, NULL,
122 bp->def_cp_ring, "def_cp");
126 rc = bnxt_alloc_vnic_mem(bp);
130 rc = bnxt_alloc_vnic_attributes(bp);
134 rc = bnxt_alloc_filter_mem(bp);
145 static int bnxt_init_chip(struct bnxt *bp)
147 unsigned int i, rss_idx, fw_idx;
150 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
152 RTE_LOG(ERR, PMD, "HWRM stat ctx alloc failure rc: %x\n", rc);
156 rc = bnxt_alloc_hwrm_rings(bp);
158 RTE_LOG(ERR, PMD, "HWRM ring alloc failure rc: %x\n", rc);
162 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
164 RTE_LOG(ERR, PMD, "HWRM ring grp alloc failure: %x\n", rc);
168 rc = bnxt_mq_rx_configure(bp);
170 RTE_LOG(ERR, PMD, "MQ mode configure failure rc: %x\n", rc);
174 /* VNIC configuration */
175 for (i = 0; i < bp->nr_vnics; i++) {
176 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
178 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
180 RTE_LOG(ERR, PMD, "HWRM vnic alloc failure rc: %x\n",
185 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
188 "HWRM vnic ctx alloc failure rc: %x\n", rc);
192 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
194 RTE_LOG(ERR, PMD, "HWRM vnic cfg failure rc: %x\n", rc);
198 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
200 RTE_LOG(ERR, PMD, "HWRM vnic filter failure rc: %x\n",
204 if (vnic->rss_table && vnic->hash_type) {
206 * Fill the RSS hash & redirection table with
207 * ring group ids for all VNICs
209 for (rss_idx = 0, fw_idx = 0;
210 rss_idx < HW_HASH_INDEX_SIZE;
211 rss_idx++, fw_idx++) {
212 if (vnic->fw_grp_ids[fw_idx] ==
215 vnic->rss_table[rss_idx] =
216 vnic->fw_grp_ids[fw_idx];
218 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
221 "HWRM vnic set RSS failure rc: %x\n",
227 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0]);
230 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
237 bnxt_free_all_hwrm_resources(bp);
242 static int bnxt_shutdown_nic(struct bnxt *bp)
244 bnxt_free_all_hwrm_resources(bp);
245 bnxt_free_all_filters(bp);
246 bnxt_free_all_vnics(bp);
250 static int bnxt_init_nic(struct bnxt *bp)
254 bnxt_init_ring_grps(bp);
256 bnxt_init_filters(bp);
258 rc = bnxt_init_chip(bp);
266 * Device configuration and status function
269 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
270 struct rte_eth_dev_info *dev_info)
272 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
273 uint16_t max_vnics, i, j, vpool, vrxq;
276 dev_info->max_mac_addrs = MAX_NUM_MAC_ADDR;
277 dev_info->max_hash_mac_addrs = 0;
279 /* PF/VF specifics */
281 dev_info->max_rx_queues = bp->pf.max_rx_rings;
282 dev_info->max_tx_queues = bp->pf.max_tx_rings;
283 dev_info->max_vfs = bp->pf.active_vfs;
284 dev_info->reta_size = bp->pf.max_rsscos_ctx;
285 max_vnics = bp->pf.max_vnics;
287 dev_info->max_rx_queues = bp->vf.max_rx_rings;
288 dev_info->max_tx_queues = bp->vf.max_tx_rings;
289 dev_info->reta_size = bp->vf.max_rsscos_ctx;
290 max_vnics = bp->vf.max_vnics;
293 /* Fast path specifics */
294 dev_info->min_rx_bufsize = 1;
295 dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
297 dev_info->rx_offload_capa = 0;
298 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM |
299 DEV_TX_OFFLOAD_TCP_CKSUM |
300 DEV_TX_OFFLOAD_UDP_CKSUM |
301 DEV_TX_OFFLOAD_TCP_TSO;
304 dev_info->default_rxconf = (struct rte_eth_rxconf) {
310 .rx_free_thresh = 32,
314 dev_info->default_txconf = (struct rte_eth_txconf) {
320 .tx_free_thresh = 32,
322 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
323 ETH_TXQ_FLAGS_NOOFFLOADS,
328 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
329 * need further investigation.
333 vpool = 64; /* ETH_64_POOLS */
334 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
335 for (i = 0; i < 4; vpool >>= 1, i++) {
336 if (max_vnics > vpool) {
337 for (j = 0; j < 5; vrxq >>= 1, j++) {
338 if (dev_info->max_rx_queues > vrxq) {
344 /* Not enough resources to support VMDq */
348 /* Not enough resources to support VMDq */
352 dev_info->max_vmdq_pools = vpool;
353 dev_info->vmdq_queue_num = vrxq;
355 dev_info->vmdq_pool_base = 0;
356 dev_info->vmdq_queue_base = 0;
359 /* Configure the device based on the configuration provided */
360 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
362 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
365 bp->rx_queues = (void *)eth_dev->data->rx_queues;
366 bp->tx_queues = (void *)eth_dev->data->tx_queues;
368 /* Inherit new configurations */
369 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
370 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
371 bp->rx_cp_nr_rings = bp->rx_nr_rings;
372 bp->tx_cp_nr_rings = bp->tx_nr_rings;
374 if (eth_dev->data->dev_conf.rxmode.jumbo_frame)
376 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
377 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE;
378 rc = bnxt_set_hwrm_link_config(bp, true);
382 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
384 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
387 rc = bnxt_hwrm_func_reset(bp);
389 RTE_LOG(ERR, PMD, "hwrm chip reset failure rc: %x\n", rc);
394 rc = bnxt_alloc_mem(bp);
398 rc = bnxt_init_nic(bp);
405 bnxt_shutdown_nic(bp);
406 bnxt_free_tx_mbufs(bp);
407 bnxt_free_rx_mbufs(bp);
412 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
414 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
416 eth_dev->data->dev_link.link_status = 1;
417 bnxt_set_hwrm_link_config(bp, true);
421 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
423 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
425 eth_dev->data->dev_link.link_status = 0;
426 bnxt_set_hwrm_link_config(bp, false);
430 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
432 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
434 bnxt_free_tx_mbufs(bp);
435 bnxt_free_rx_mbufs(bp);
437 rte_free(eth_dev->data->mac_addrs);
440 /* Unload the driver, release resources */
441 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
443 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
445 if (bp->eth_dev->data->dev_started) {
446 /* TBD: STOP HW queues DMA */
447 eth_dev->data->dev_link.link_status = 0;
449 bnxt_shutdown_nic(bp);
452 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
455 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
456 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
457 struct bnxt_vnic_info *vnic;
458 struct bnxt_filter_info *filter, *temp_filter;
462 * Loop through all VNICs from the specified filter flow pools to
463 * remove the corresponding MAC addr filter
465 for (i = 0; i < MAX_FF_POOLS; i++) {
466 if (!(pool_mask & (1 << i)))
469 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
470 filter = STAILQ_FIRST(&vnic->filter);
472 temp_filter = STAILQ_NEXT(filter, next);
473 if (filter->mac_index == index) {
474 STAILQ_REMOVE(&vnic->filter, filter,
475 bnxt_filter_info, next);
476 bnxt_hwrm_clear_filter(bp, filter);
477 filter->mac_index = INVALID_MAC_INDEX;
478 memset(&filter->l2_addr, 0,
481 &bp->free_filter_list,
484 filter = temp_filter;
490 static void bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
491 struct ether_addr *mac_addr,
492 uint32_t index, uint32_t pool)
494 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
495 struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]);
496 struct bnxt_filter_info *filter;
499 RTE_LOG(ERR, PMD, "VNIC not found for pool %d!\n", pool);
502 /* Attach requested MAC address to the new l2_filter */
503 STAILQ_FOREACH(filter, &vnic->filter, next) {
504 if (filter->mac_index == index) {
506 "MAC addr already existed for pool %d\n", pool);
510 filter = bnxt_alloc_filter(bp);
512 RTE_LOG(ERR, PMD, "L2 filter alloc failed\n");
515 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
516 filter->mac_index = index;
517 memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
518 bnxt_hwrm_set_filter(bp, vnic, filter);
521 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
522 int wait_to_complete)
525 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
526 struct rte_eth_link new;
527 unsigned int cnt = BNXT_LINK_WAIT_CNT;
529 memset(&new, 0, sizeof(new));
531 /* Retrieve link info from hardware */
532 rc = bnxt_get_hwrm_link_config(bp, &new);
534 new.link_speed = ETH_LINK_SPEED_100M;
535 new.link_duplex = ETH_LINK_FULL_DUPLEX;
537 "Failed to retrieve link rc = 0x%x!", rc);
540 if (!wait_to_complete)
543 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
545 } while (!new.link_status && cnt--);
547 /* Timed out or success */
548 if (new.link_status) {
549 /* Update only if success */
550 eth_dev->data->dev_link.link_duplex = new.link_duplex;
551 eth_dev->data->dev_link.link_speed = new.link_speed;
553 eth_dev->data->dev_link.link_status = new.link_status;
558 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
560 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
561 struct bnxt_vnic_info *vnic;
563 if (bp->vnic_info == NULL)
566 vnic = &bp->vnic_info[0];
568 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
569 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
572 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
574 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
575 struct bnxt_vnic_info *vnic;
577 if (bp->vnic_info == NULL)
580 vnic = &bp->vnic_info[0];
582 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
583 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
586 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
588 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
589 struct bnxt_vnic_info *vnic;
591 if (bp->vnic_info == NULL)
594 vnic = &bp->vnic_info[0];
596 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
597 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
600 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
602 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
603 struct bnxt_vnic_info *vnic;
605 if (bp->vnic_info == NULL)
608 vnic = &bp->vnic_info[0];
610 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
611 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
614 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
615 struct rte_eth_rss_reta_entry64 *reta_conf,
618 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
619 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
620 struct bnxt_vnic_info *vnic;
623 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
626 if (reta_size != HW_HASH_INDEX_SIZE) {
627 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
628 "(%d) must equal the size supported by the hardware "
629 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
632 /* Update the RSS VNIC(s) */
633 for (i = 0; i < MAX_FF_POOLS; i++) {
634 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
635 memcpy(vnic->rss_table, reta_conf, reta_size);
637 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
643 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
644 struct rte_eth_rss_reta_entry64 *reta_conf,
647 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
648 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
650 /* Retrieve from the default VNIC */
653 if (!vnic->rss_table)
656 if (reta_size != HW_HASH_INDEX_SIZE) {
657 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
658 "(%d) must equal the size supported by the hardware "
659 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
662 /* EW - need to revisit here copying from u64 to u16 */
663 memcpy(reta_conf, vnic->rss_table, reta_size);
668 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
669 struct rte_eth_rss_conf *rss_conf)
671 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
672 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
673 struct bnxt_vnic_info *vnic;
674 uint16_t hash_type = 0;
678 * If RSS enablement were different than dev_configure,
679 * then return -EINVAL
681 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
682 if (!rss_conf->rss_hf)
685 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
688 if (rss_conf->rss_hf & ETH_RSS_IPV4)
689 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
690 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
691 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
692 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
693 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
694 if (rss_conf->rss_hf & ETH_RSS_IPV6)
695 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
696 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
697 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
698 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
699 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
701 /* Update the RSS VNIC(s) */
702 for (i = 0; i < MAX_FF_POOLS; i++) {
703 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
704 vnic->hash_type = hash_type;
707 * Use the supplied key if the key length is
708 * acceptable and the rss_key is not NULL
710 if (rss_conf->rss_key &&
711 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
712 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
713 rss_conf->rss_key_len);
715 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
721 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
722 struct rte_eth_rss_conf *rss_conf)
724 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
725 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
729 /* RSS configuration is the same for all VNICs */
730 if (vnic && vnic->rss_hash_key) {
731 if (rss_conf->rss_key) {
732 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
733 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
734 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
737 hash_types = vnic->hash_type;
738 rss_conf->rss_hf = 0;
739 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
740 rss_conf->rss_hf |= ETH_RSS_IPV4;
741 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
743 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
744 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
746 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
748 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
749 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
751 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
753 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
754 rss_conf->rss_hf |= ETH_RSS_IPV6;
755 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
757 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
758 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
760 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
762 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
763 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
765 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
769 "Unknwon RSS config from firmware (%08x), RSS disabled",
774 rss_conf->rss_hf = 0;
779 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
780 struct rte_eth_fc_conf *fc_conf __rte_unused)
782 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
783 struct rte_eth_link link_info;
786 rc = bnxt_get_hwrm_link_config(bp, &link_info);
790 memset(fc_conf, 0, sizeof(*fc_conf));
791 if (bp->link_info.auto_pause)
792 fc_conf->autoneg = 1;
793 switch (bp->link_info.pause) {
795 fc_conf->mode = RTE_FC_NONE;
797 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
798 fc_conf->mode = RTE_FC_TX_PAUSE;
800 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
801 fc_conf->mode = RTE_FC_RX_PAUSE;
803 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
804 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
805 fc_conf->mode = RTE_FC_FULL;
811 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
812 struct rte_eth_fc_conf *fc_conf)
814 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
816 switch (fc_conf->mode) {
818 bp->link_info.auto_pause = 0;
819 bp->link_info.force_pause = 0;
821 case RTE_FC_RX_PAUSE:
822 if (fc_conf->autoneg) {
823 bp->link_info.auto_pause =
824 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
825 bp->link_info.force_pause = 0;
827 bp->link_info.auto_pause = 0;
828 bp->link_info.force_pause =
829 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
832 case RTE_FC_TX_PAUSE:
833 if (fc_conf->autoneg) {
834 bp->link_info.auto_pause =
835 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
836 bp->link_info.force_pause = 0;
838 bp->link_info.auto_pause = 0;
839 bp->link_info.force_pause =
840 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
844 if (fc_conf->autoneg) {
845 bp->link_info.auto_pause =
846 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
847 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
848 bp->link_info.force_pause = 0;
850 bp->link_info.auto_pause = 0;
851 bp->link_info.force_pause =
852 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
853 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
857 return bnxt_set_hwrm_link_config(bp, true);
864 static struct eth_dev_ops bnxt_dev_ops = {
865 .dev_infos_get = bnxt_dev_info_get_op,
866 .dev_close = bnxt_dev_close_op,
867 .dev_configure = bnxt_dev_configure_op,
868 .dev_start = bnxt_dev_start_op,
869 .dev_stop = bnxt_dev_stop_op,
870 .dev_set_link_up = bnxt_dev_set_link_up_op,
871 .dev_set_link_down = bnxt_dev_set_link_down_op,
872 .stats_get = bnxt_stats_get_op,
873 .stats_reset = bnxt_stats_reset_op,
874 .rx_queue_setup = bnxt_rx_queue_setup_op,
875 .rx_queue_release = bnxt_rx_queue_release_op,
876 .tx_queue_setup = bnxt_tx_queue_setup_op,
877 .tx_queue_release = bnxt_tx_queue_release_op,
878 .reta_update = bnxt_reta_update_op,
879 .reta_query = bnxt_reta_query_op,
880 .rss_hash_update = bnxt_rss_hash_update_op,
881 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
882 .link_update = bnxt_link_update_op,
883 .promiscuous_enable = bnxt_promiscuous_enable_op,
884 .promiscuous_disable = bnxt_promiscuous_disable_op,
885 .allmulticast_enable = bnxt_allmulticast_enable_op,
886 .allmulticast_disable = bnxt_allmulticast_disable_op,
887 .mac_addr_add = bnxt_mac_addr_add_op,
888 .mac_addr_remove = bnxt_mac_addr_remove_op,
889 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
890 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
893 static bool bnxt_vf_pciid(uint16_t id)
895 if (id == BROADCOM_DEV_ID_57304_VF ||
896 id == BROADCOM_DEV_ID_57406_VF)
901 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
904 struct bnxt *bp = eth_dev->data->dev_private;
906 /* enable device (incl. PCI PM wakeup), and bus-mastering */
907 if (!eth_dev->pci_dev->mem_resource[0].addr) {
909 "Cannot find PCI device base address, aborting\n");
911 goto init_err_disable;
914 bp->eth_dev = eth_dev;
915 bp->pdev = eth_dev->pci_dev;
917 bp->bar0 = (void *)eth_dev->pci_dev->mem_resource[0].addr;
919 RTE_LOG(ERR, PMD, "Cannot map device registers, aborting\n");
921 goto init_err_release;
935 bnxt_dev_init(struct rte_eth_dev *eth_dev)
937 static int version_printed;
941 if (version_printed++ == 0)
942 RTE_LOG(INFO, PMD, "%s", bnxt_version);
944 if (eth_dev->pci_dev->addr.function >= 2 &&
945 eth_dev->pci_dev->addr.function < 4) {
946 RTE_LOG(ERR, PMD, "Function not enabled %x:\n",
947 eth_dev->pci_dev->addr.function);
952 rte_eth_copy_pci_info(eth_dev, eth_dev->pci_dev);
953 bp = eth_dev->data->dev_private;
955 if (bnxt_vf_pciid(eth_dev->pci_dev->id.device_id))
956 bp->flags |= BNXT_FLAG_VF;
958 rc = bnxt_init_board(eth_dev);
961 "Board initialization failed rc: %x\n", rc);
964 eth_dev->dev_ops = &bnxt_dev_ops;
965 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
966 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
968 rc = bnxt_alloc_hwrm_resources(bp);
971 "hwrm resource allocation failure rc: %x\n", rc);
974 rc = bnxt_hwrm_ver_get(bp);
977 bnxt_hwrm_queue_qportcfg(bp);
979 /* Get the MAX capabilities for this function */
980 rc = bnxt_hwrm_func_qcaps(bp);
982 RTE_LOG(ERR, PMD, "hwrm query capability failure rc: %x\n", rc);
985 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
986 ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR, 0);
987 if (eth_dev->data->mac_addrs == NULL) {
989 "Failed to alloc %u bytes needed to store MAC addr tbl",
990 ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR);
994 /* Copy the permanent MAC from the qcap response address now. */
996 memcpy(bp->mac_addr, bp->pf.mac_addr, sizeof(bp->mac_addr));
998 memcpy(bp->mac_addr, bp->vf.mac_addr, sizeof(bp->mac_addr));
999 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
1000 bp->grp_info = rte_zmalloc("bnxt_grp_info",
1001 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
1002 if (!bp->grp_info) {
1004 "Failed to alloc %zu bytes needed to store group info table\n",
1005 sizeof(*bp->grp_info) * bp->max_ring_grps);
1010 rc = bnxt_hwrm_func_driver_register(bp, 0,
1014 "Failed to register driver");
1020 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
1021 eth_dev->pci_dev->mem_resource[0].phys_addr,
1022 eth_dev->pci_dev->mem_resource[0].addr);
1027 eth_dev->driver->eth_dev_uninit(eth_dev);
1033 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) {
1034 struct bnxt *bp = eth_dev->data->dev_private;
1037 if (eth_dev->data->mac_addrs)
1038 rte_free(eth_dev->data->mac_addrs);
1040 rte_free(bp->grp_info);
1041 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
1042 bnxt_free_hwrm_resources(bp);
1046 static struct eth_driver bnxt_rte_pmd = {
1048 .name = "rte_" DRV_MODULE_NAME "_pmd",
1049 .id_table = bnxt_pci_id_map,
1050 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1051 .probe = rte_eth_dev_pci_probe,
1052 .remove = rte_eth_dev_pci_remove
1054 .eth_dev_init = bnxt_dev_init,
1055 .eth_dev_uninit = bnxt_dev_uninit,
1056 .dev_private_size = sizeof(struct bnxt),
1059 DRIVER_REGISTER_PCI(net_bnxt, bnxt_rte_pmd.pci_drv);
1060 DRIVER_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);