1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
18 #include "bnxt_filter.h"
19 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_stats.h"
27 #include "bnxt_vnic.h"
28 #include "hsi_struct_def_dpdk.h"
29 #include "bnxt_nvm_defs.h"
30 #include "bnxt_util.h"
32 #define DRV_MODULE_NAME "bnxt"
33 static const char bnxt_version[] =
34 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
35 int bnxt_logtype_driver;
37 #define PCI_VENDOR_ID_BROADCOM 0x14E4
39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
40 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
41 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
42 #define BROADCOM_DEV_ID_57414_VF 0x16c1
43 #define BROADCOM_DEV_ID_57301 0x16c8
44 #define BROADCOM_DEV_ID_57302 0x16c9
45 #define BROADCOM_DEV_ID_57304_PF 0x16ca
46 #define BROADCOM_DEV_ID_57304_VF 0x16cb
47 #define BROADCOM_DEV_ID_57417_MF 0x16cc
48 #define BROADCOM_DEV_ID_NS2 0x16cd
49 #define BROADCOM_DEV_ID_57311 0x16ce
50 #define BROADCOM_DEV_ID_57312 0x16cf
51 #define BROADCOM_DEV_ID_57402 0x16d0
52 #define BROADCOM_DEV_ID_57404 0x16d1
53 #define BROADCOM_DEV_ID_57406_PF 0x16d2
54 #define BROADCOM_DEV_ID_57406_VF 0x16d3
55 #define BROADCOM_DEV_ID_57402_MF 0x16d4
56 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
57 #define BROADCOM_DEV_ID_57412 0x16d6
58 #define BROADCOM_DEV_ID_57414 0x16d7
59 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
60 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
61 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
62 #define BROADCOM_DEV_ID_57412_MF 0x16de
63 #define BROADCOM_DEV_ID_57314 0x16df
64 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
65 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
66 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
67 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
68 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
69 #define BROADCOM_DEV_ID_57404_MF 0x16e7
70 #define BROADCOM_DEV_ID_57406_MF 0x16e8
71 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
72 #define BROADCOM_DEV_ID_57407_MF 0x16ea
73 #define BROADCOM_DEV_ID_57414_MF 0x16ec
74 #define BROADCOM_DEV_ID_57416_MF 0x16ee
75 #define BROADCOM_DEV_ID_57508 0x1750
76 #define BROADCOM_DEV_ID_57504 0x1751
77 #define BROADCOM_DEV_ID_57502 0x1752
78 #define BROADCOM_DEV_ID_57500_VF1 0x1806
79 #define BROADCOM_DEV_ID_57500_VF2 0x1807
80 #define BROADCOM_DEV_ID_58802 0xd802
81 #define BROADCOM_DEV_ID_58804 0xd804
82 #define BROADCOM_DEV_ID_58808 0x16f0
83 #define BROADCOM_DEV_ID_58802_VF 0xd800
85 static const struct rte_pci_id bnxt_pci_id_map[] = {
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
87 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
89 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
98 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
122 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
123 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
124 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
125 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
126 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
127 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
128 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
129 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
130 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
131 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
132 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
133 { .vendor_id = 0, /* sentinel */ },
136 #define BNXT_ETH_RSS_SUPPORT ( \
138 ETH_RSS_NONFRAG_IPV4_TCP | \
139 ETH_RSS_NONFRAG_IPV4_UDP | \
141 ETH_RSS_NONFRAG_IPV6_TCP | \
142 ETH_RSS_NONFRAG_IPV6_UDP)
144 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
145 DEV_TX_OFFLOAD_IPV4_CKSUM | \
146 DEV_TX_OFFLOAD_TCP_CKSUM | \
147 DEV_TX_OFFLOAD_UDP_CKSUM | \
148 DEV_TX_OFFLOAD_TCP_TSO | \
149 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
150 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
151 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
152 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
153 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
154 DEV_TX_OFFLOAD_QINQ_INSERT | \
155 DEV_TX_OFFLOAD_MULTI_SEGS)
157 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
158 DEV_RX_OFFLOAD_VLAN_STRIP | \
159 DEV_RX_OFFLOAD_IPV4_CKSUM | \
160 DEV_RX_OFFLOAD_UDP_CKSUM | \
161 DEV_RX_OFFLOAD_TCP_CKSUM | \
162 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
163 DEV_RX_OFFLOAD_JUMBO_FRAME | \
164 DEV_RX_OFFLOAD_KEEP_CRC | \
165 DEV_RX_OFFLOAD_VLAN_EXTEND | \
166 DEV_RX_OFFLOAD_TCP_LRO)
168 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
169 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
170 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
171 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
172 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
173 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
174 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
176 int is_bnxt_in_error(struct bnxt *bp)
178 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
180 if (bp->flags & BNXT_FLAG_FW_RESET)
186 /***********************/
189 * High level utility functions
192 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
194 if (!BNXT_CHIP_THOR(bp))
197 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
198 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
199 BNXT_RSS_ENTRIES_PER_CTX_THOR;
202 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
204 if (!BNXT_CHIP_THOR(bp))
205 return HW_HASH_INDEX_SIZE;
207 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
210 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
212 bnxt_free_filter_mem(bp);
213 bnxt_free_vnic_attributes(bp);
214 bnxt_free_vnic_mem(bp);
216 /* tx/rx rings are configured as part of *_queue_setup callbacks.
217 * If the number of rings change across fw update,
218 * we don't have much choice except to warn the user.
222 bnxt_free_tx_rings(bp);
223 bnxt_free_rx_rings(bp);
225 bnxt_free_async_cp_ring(bp);
228 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
232 rc = bnxt_alloc_ring_grps(bp);
236 rc = bnxt_alloc_async_ring_struct(bp);
240 rc = bnxt_alloc_vnic_mem(bp);
244 rc = bnxt_alloc_vnic_attributes(bp);
248 rc = bnxt_alloc_filter_mem(bp);
252 rc = bnxt_alloc_async_cp_ring(bp);
259 bnxt_free_mem(bp, reconfig);
263 static int bnxt_init_chip(struct bnxt *bp)
265 struct bnxt_rx_queue *rxq;
266 struct rte_eth_link new;
267 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
268 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
269 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
270 uint64_t rx_offloads = dev_conf->rxmode.offloads;
271 uint32_t intr_vector = 0;
272 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
273 uint32_t vec = BNXT_MISC_VEC_ID;
277 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
278 bp->eth_dev->data->dev_conf.rxmode.offloads |=
279 DEV_RX_OFFLOAD_JUMBO_FRAME;
280 bp->flags |= BNXT_FLAG_JUMBO;
282 bp->eth_dev->data->dev_conf.rxmode.offloads &=
283 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
284 bp->flags &= ~BNXT_FLAG_JUMBO;
287 /* THOR does not support ring groups.
288 * But we will use the array to save RSS context IDs.
290 if (BNXT_CHIP_THOR(bp))
291 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
293 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
295 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
299 rc = bnxt_alloc_hwrm_rings(bp);
301 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
305 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
307 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
311 rc = bnxt_mq_rx_configure(bp);
313 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
317 /* VNIC configuration */
318 for (i = 0; i < bp->nr_vnics; i++) {
319 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
320 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
322 rc = bnxt_vnic_grp_alloc(bp, vnic);
326 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
327 i, vnic, vnic->fw_grp_ids);
329 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
331 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
336 /* Alloc RSS context only if RSS mode is enabled */
337 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
338 int j, nr_ctxs = bnxt_rss_ctxts(bp);
341 for (j = 0; j < nr_ctxs; j++) {
342 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
348 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
352 vnic->num_lb_ctxts = nr_ctxs;
356 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
357 * setting is not available at this time, it will not be
358 * configured correctly in the CFA.
360 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
361 vnic->vlan_strip = true;
363 vnic->vlan_strip = false;
365 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
367 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
372 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
375 "HWRM vnic %d filter failure rc: %x\n",
380 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
381 rxq = bp->eth_dev->data->rx_queues[j];
384 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
385 j, rxq->vnic, rxq->vnic->fw_grp_ids);
387 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
388 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
391 rc = bnxt_vnic_rss_configure(bp, vnic);
394 "HWRM vnic set RSS failure rc: %x\n", rc);
398 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
400 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
401 DEV_RX_OFFLOAD_TCP_LRO)
402 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
404 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
406 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
409 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
413 /* check and configure queue intr-vector mapping */
414 if ((rte_intr_cap_multiple(intr_handle) ||
415 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
416 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
417 intr_vector = bp->eth_dev->data->nb_rx_queues;
418 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
419 if (intr_vector > bp->rx_cp_nr_rings) {
420 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
424 rc = rte_intr_efd_enable(intr_handle, intr_vector);
429 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
430 intr_handle->intr_vec =
431 rte_zmalloc("intr_vec",
432 bp->eth_dev->data->nb_rx_queues *
434 if (intr_handle->intr_vec == NULL) {
435 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
436 " intr_vec", bp->eth_dev->data->nb_rx_queues);
440 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
441 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
442 intr_handle->intr_vec, intr_handle->nb_efd,
443 intr_handle->max_intr);
444 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
446 intr_handle->intr_vec[queue_id] =
447 vec + BNXT_RX_VEC_START;
448 if (vec < base + intr_handle->nb_efd - 1)
453 /* enable uio/vfio intr/eventfd mapping */
454 rc = rte_intr_enable(intr_handle);
458 rc = bnxt_get_hwrm_link_config(bp, &new);
460 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
464 if (!bp->link_info.link_up) {
465 rc = bnxt_set_hwrm_link_config(bp, true);
468 "HWRM link config failure rc: %x\n", rc);
472 bnxt_print_link_info(bp->eth_dev);
477 rte_free(intr_handle->intr_vec);
479 rte_intr_efd_disable(intr_handle);
481 /* Some of the error status returned by FW may not be from errno.h */
488 static int bnxt_shutdown_nic(struct bnxt *bp)
490 bnxt_free_all_hwrm_resources(bp);
491 bnxt_free_all_filters(bp);
492 bnxt_free_all_vnics(bp);
496 static int bnxt_init_nic(struct bnxt *bp)
500 if (BNXT_HAS_RING_GRPS(bp)) {
501 rc = bnxt_init_ring_grps(bp);
507 bnxt_init_filters(bp);
513 * Device configuration and status function
516 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
517 struct rte_eth_dev_info *dev_info)
519 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
520 struct bnxt *bp = eth_dev->data->dev_private;
521 uint16_t max_vnics, i, j, vpool, vrxq;
522 unsigned int max_rx_rings;
525 rc = is_bnxt_in_error(bp);
530 dev_info->max_mac_addrs = bp->max_l2_ctx;
531 dev_info->max_hash_mac_addrs = 0;
533 /* PF/VF specifics */
535 dev_info->max_vfs = pdev->max_vfs;
537 max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
538 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
539 dev_info->max_rx_queues = max_rx_rings;
540 dev_info->max_tx_queues = max_rx_rings;
541 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
542 dev_info->hash_key_size = 40;
543 max_vnics = bp->max_vnics;
546 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
547 dev_info->max_mtu = BNXT_MAX_MTU;
549 /* Fast path specifics */
550 dev_info->min_rx_bufsize = 1;
551 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
553 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
554 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
555 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
556 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
557 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
560 dev_info->default_rxconf = (struct rte_eth_rxconf) {
566 .rx_free_thresh = 32,
567 /* If no descriptors available, pkts are dropped by default */
571 dev_info->default_txconf = (struct rte_eth_txconf) {
577 .tx_free_thresh = 32,
580 eth_dev->data->dev_conf.intr_conf.lsc = 1;
582 eth_dev->data->dev_conf.intr_conf.rxq = 1;
583 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
584 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
585 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
586 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
591 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
592 * need further investigation.
596 vpool = 64; /* ETH_64_POOLS */
597 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
598 for (i = 0; i < 4; vpool >>= 1, i++) {
599 if (max_vnics > vpool) {
600 for (j = 0; j < 5; vrxq >>= 1, j++) {
601 if (dev_info->max_rx_queues > vrxq) {
607 /* Not enough resources to support VMDq */
611 /* Not enough resources to support VMDq */
615 dev_info->max_vmdq_pools = vpool;
616 dev_info->vmdq_queue_num = vrxq;
618 dev_info->vmdq_pool_base = 0;
619 dev_info->vmdq_queue_base = 0;
624 /* Configure the device based on the configuration provided */
625 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
627 struct bnxt *bp = eth_dev->data->dev_private;
628 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
631 bp->rx_queues = (void *)eth_dev->data->rx_queues;
632 bp->tx_queues = (void *)eth_dev->data->tx_queues;
633 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
634 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
636 rc = is_bnxt_in_error(bp);
640 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
641 rc = bnxt_hwrm_check_vf_rings(bp);
643 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
647 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
649 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
653 /* legacy driver needs to get updated values */
654 rc = bnxt_hwrm_func_qcaps(bp);
656 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
661 /* Inherit new configurations */
662 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
663 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
664 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
665 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
666 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
670 if (BNXT_HAS_RING_GRPS(bp) &&
671 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
674 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
675 bp->max_vnics < eth_dev->data->nb_rx_queues)
678 bp->rx_cp_nr_rings = bp->rx_nr_rings;
679 bp->tx_cp_nr_rings = bp->tx_nr_rings;
681 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
683 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
684 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
686 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
692 "Insufficient resources to support requested config\n");
694 "Num Queues Requested: Tx %d, Rx %d\n",
695 eth_dev->data->nb_tx_queues,
696 eth_dev->data->nb_rx_queues);
698 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
699 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
700 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
704 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
706 struct rte_eth_link *link = ð_dev->data->dev_link;
708 if (link->link_status)
709 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
710 eth_dev->data->port_id,
711 (uint32_t)link->link_speed,
712 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
713 ("full-duplex") : ("half-duplex\n"));
715 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
716 eth_dev->data->port_id);
720 * Determine whether the current configuration requires support for scattered
721 * receive; return 1 if scattered receive is required and 0 if not.
723 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
728 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
729 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
731 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
732 RTE_PKTMBUF_HEADROOM);
733 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
739 static eth_rx_burst_t
740 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
743 #ifndef RTE_LIBRTE_IEEE1588
745 * Vector mode receive can be enabled only if scatter rx is not
746 * in use and rx offloads are limited to VLAN stripping and
749 if (!eth_dev->data->scattered_rx &&
750 !(eth_dev->data->dev_conf.rxmode.offloads &
751 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
752 DEV_RX_OFFLOAD_KEEP_CRC |
753 DEV_RX_OFFLOAD_JUMBO_FRAME |
754 DEV_RX_OFFLOAD_IPV4_CKSUM |
755 DEV_RX_OFFLOAD_UDP_CKSUM |
756 DEV_RX_OFFLOAD_TCP_CKSUM |
757 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
758 DEV_RX_OFFLOAD_VLAN_FILTER))) {
759 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
760 eth_dev->data->port_id);
761 return bnxt_recv_pkts_vec;
763 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
764 eth_dev->data->port_id);
766 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
767 eth_dev->data->port_id,
768 eth_dev->data->scattered_rx,
769 eth_dev->data->dev_conf.rxmode.offloads);
772 return bnxt_recv_pkts;
775 static eth_tx_burst_t
776 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
779 #ifndef RTE_LIBRTE_IEEE1588
781 * Vector mode transmit can be enabled only if not using scatter rx
784 if (!eth_dev->data->scattered_rx &&
785 !eth_dev->data->dev_conf.txmode.offloads) {
786 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
787 eth_dev->data->port_id);
788 return bnxt_xmit_pkts_vec;
790 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
791 eth_dev->data->port_id);
793 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
794 eth_dev->data->port_id,
795 eth_dev->data->scattered_rx,
796 eth_dev->data->dev_conf.txmode.offloads);
799 return bnxt_xmit_pkts;
802 static int bnxt_handle_if_change_status(struct bnxt *bp)
806 /* Since fw has undergone a reset and lost all contexts,
807 * set fatal flag to not issue hwrm during cleanup
809 bp->flags |= BNXT_FLAG_FATAL_ERROR;
810 bnxt_uninit_resources(bp, true);
812 /* clear fatal flag so that re-init happens */
813 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
814 rc = bnxt_init_resources(bp, true);
816 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
821 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
823 struct bnxt *bp = eth_dev->data->dev_private;
824 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
828 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
830 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
831 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
835 rc = bnxt_hwrm_if_change(bp, 1);
837 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
838 rc = bnxt_handle_if_change_status(bp);
844 rc = bnxt_init_chip(bp);
848 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
850 bnxt_link_update_op(eth_dev, 1);
852 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
853 vlan_mask |= ETH_VLAN_FILTER_MASK;
854 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
855 vlan_mask |= ETH_VLAN_STRIP_MASK;
856 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
860 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
861 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
863 bp->flags |= BNXT_FLAG_INIT_DONE;
864 eth_dev->data->dev_started = 1;
866 bnxt_schedule_fw_health_check(bp);
870 bnxt_hwrm_if_change(bp, 0);
871 bnxt_shutdown_nic(bp);
872 bnxt_free_tx_mbufs(bp);
873 bnxt_free_rx_mbufs(bp);
877 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
879 struct bnxt *bp = eth_dev->data->dev_private;
882 if (!bp->link_info.link_up)
883 rc = bnxt_set_hwrm_link_config(bp, true);
885 eth_dev->data->dev_link.link_status = 1;
887 bnxt_print_link_info(eth_dev);
891 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
893 struct bnxt *bp = eth_dev->data->dev_private;
895 eth_dev->data->dev_link.link_status = 0;
896 bnxt_set_hwrm_link_config(bp, false);
897 bp->link_info.link_up = 0;
902 /* Unload the driver, release resources */
903 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
905 struct bnxt *bp = eth_dev->data->dev_private;
906 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
907 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
909 eth_dev->data->dev_started = 0;
910 /* Prevent crashes when queues are still in use */
911 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
912 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
914 bnxt_disable_int(bp);
916 /* disable uio/vfio intr/eventfd mapping */
917 rte_intr_disable(intr_handle);
919 bnxt_cancel_fw_health_check(bp);
921 bp->flags &= ~BNXT_FLAG_INIT_DONE;
922 if (bp->eth_dev->data->dev_started) {
923 /* TBD: STOP HW queues DMA */
924 eth_dev->data->dev_link.link_status = 0;
926 bnxt_dev_set_link_down_op(eth_dev);
927 /* Wait for link to be reset and the async notification to process. */
928 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL * 2);
930 /* Clean queue intr-vector mapping */
931 rte_intr_efd_disable(intr_handle);
932 if (intr_handle->intr_vec != NULL) {
933 rte_free(intr_handle->intr_vec);
934 intr_handle->intr_vec = NULL;
937 bnxt_hwrm_port_clr_stats(bp);
938 bnxt_free_tx_mbufs(bp);
939 bnxt_free_rx_mbufs(bp);
940 /* Process any remaining notifications in default completion queue */
941 bnxt_int_handler(eth_dev);
942 bnxt_shutdown_nic(bp);
943 bnxt_hwrm_if_change(bp, 0);
947 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
949 struct bnxt *bp = eth_dev->data->dev_private;
951 if (bp->dev_stopped == 0)
952 bnxt_dev_stop_op(eth_dev);
954 if (eth_dev->data->mac_addrs != NULL) {
955 rte_free(eth_dev->data->mac_addrs);
956 eth_dev->data->mac_addrs = NULL;
958 if (bp->grp_info != NULL) {
959 rte_free(bp->grp_info);
963 bnxt_dev_uninit(eth_dev);
966 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
969 struct bnxt *bp = eth_dev->data->dev_private;
970 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
971 struct bnxt_vnic_info *vnic;
972 struct bnxt_filter_info *filter, *temp_filter;
975 if (is_bnxt_in_error(bp))
979 * Loop through all VNICs from the specified filter flow pools to
980 * remove the corresponding MAC addr filter
982 for (i = 0; i < bp->nr_vnics; i++) {
983 if (!(pool_mask & (1ULL << i)))
986 vnic = &bp->vnic_info[i];
987 filter = STAILQ_FIRST(&vnic->filter);
989 temp_filter = STAILQ_NEXT(filter, next);
990 if (filter->mac_index == index) {
991 STAILQ_REMOVE(&vnic->filter, filter,
992 bnxt_filter_info, next);
993 bnxt_hwrm_clear_l2_filter(bp, filter);
994 filter->mac_index = INVALID_MAC_INDEX;
995 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
996 STAILQ_INSERT_TAIL(&bp->free_filter_list,
999 filter = temp_filter;
1004 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1005 struct rte_ether_addr *mac_addr,
1006 uint32_t index, uint32_t pool)
1008 struct bnxt *bp = eth_dev->data->dev_private;
1009 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1010 struct bnxt_filter_info *filter;
1013 rc = is_bnxt_in_error(bp);
1017 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1018 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1023 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1026 /* Attach requested MAC address to the new l2_filter */
1027 STAILQ_FOREACH(filter, &vnic->filter, next) {
1028 if (filter->mac_index == index) {
1030 "MAC addr already existed for pool %d\n", pool);
1034 filter = bnxt_alloc_filter(bp);
1036 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1040 filter->mac_index = index;
1041 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1043 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1045 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1047 filter->mac_index = INVALID_MAC_INDEX;
1048 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1049 bnxt_free_filter(bp, filter);
1055 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1058 struct bnxt *bp = eth_dev->data->dev_private;
1059 struct rte_eth_link new;
1060 unsigned int cnt = BNXT_LINK_WAIT_CNT;
1062 rc = is_bnxt_in_error(bp);
1066 memset(&new, 0, sizeof(new));
1068 /* Retrieve link info from hardware */
1069 rc = bnxt_get_hwrm_link_config(bp, &new);
1071 new.link_speed = ETH_LINK_SPEED_100M;
1072 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1074 "Failed to retrieve link rc = 0x%x!\n", rc);
1078 if (!wait_to_complete || new.link_status)
1081 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1085 /* Timed out or success */
1086 if (new.link_status != eth_dev->data->dev_link.link_status ||
1087 new.link_speed != eth_dev->data->dev_link.link_speed) {
1088 rte_eth_linkstatus_set(eth_dev, &new);
1090 _rte_eth_dev_callback_process(eth_dev,
1091 RTE_ETH_EVENT_INTR_LSC,
1094 bnxt_print_link_info(eth_dev);
1100 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1102 struct bnxt *bp = eth_dev->data->dev_private;
1103 struct bnxt_vnic_info *vnic;
1107 rc = is_bnxt_in_error(bp);
1111 if (bp->vnic_info == NULL)
1114 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1116 old_flags = vnic->flags;
1117 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1118 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1120 vnic->flags = old_flags;
1125 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1127 struct bnxt *bp = eth_dev->data->dev_private;
1128 struct bnxt_vnic_info *vnic;
1132 rc = is_bnxt_in_error(bp);
1136 if (bp->vnic_info == NULL)
1139 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1141 old_flags = vnic->flags;
1142 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1143 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1145 vnic->flags = old_flags;
1150 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1152 struct bnxt *bp = eth_dev->data->dev_private;
1153 struct bnxt_vnic_info *vnic;
1157 rc = is_bnxt_in_error(bp);
1161 if (bp->vnic_info == NULL)
1164 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1166 old_flags = vnic->flags;
1167 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1168 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1170 vnic->flags = old_flags;
1175 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1177 struct bnxt *bp = eth_dev->data->dev_private;
1178 struct bnxt_vnic_info *vnic;
1182 rc = is_bnxt_in_error(bp);
1186 if (bp->vnic_info == NULL)
1189 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1191 old_flags = vnic->flags;
1192 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1193 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1195 vnic->flags = old_flags;
1200 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1201 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1203 if (qid >= bp->rx_nr_rings)
1206 return bp->eth_dev->data->rx_queues[qid];
1209 /* Return rxq corresponding to a given rss table ring/group ID. */
1210 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1212 struct bnxt_rx_queue *rxq;
1215 if (!BNXT_HAS_RING_GRPS(bp)) {
1216 for (i = 0; i < bp->rx_nr_rings; i++) {
1217 rxq = bp->eth_dev->data->rx_queues[i];
1218 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1222 for (i = 0; i < bp->rx_nr_rings; i++) {
1223 if (bp->grp_info[i].fw_grp_id == fwr)
1228 return INVALID_HW_RING_ID;
1231 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1232 struct rte_eth_rss_reta_entry64 *reta_conf,
1235 struct bnxt *bp = eth_dev->data->dev_private;
1236 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1237 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1238 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1242 rc = is_bnxt_in_error(bp);
1246 if (!vnic->rss_table)
1249 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1252 if (reta_size != tbl_size) {
1253 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1254 "(%d) must equal the size supported by the hardware "
1255 "(%d)\n", reta_size, tbl_size);
1259 for (i = 0; i < reta_size; i++) {
1260 struct bnxt_rx_queue *rxq;
1262 idx = i / RTE_RETA_GROUP_SIZE;
1263 sft = i % RTE_RETA_GROUP_SIZE;
1265 if (!(reta_conf[idx].mask & (1ULL << sft)))
1268 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1270 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1274 if (BNXT_CHIP_THOR(bp)) {
1275 vnic->rss_table[i * 2] =
1276 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1277 vnic->rss_table[i * 2 + 1] =
1278 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1280 vnic->rss_table[i] =
1281 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1284 vnic->rss_table[i] =
1285 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1288 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1292 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1293 struct rte_eth_rss_reta_entry64 *reta_conf,
1296 struct bnxt *bp = eth_dev->data->dev_private;
1297 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1298 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1299 uint16_t idx, sft, i;
1302 rc = is_bnxt_in_error(bp);
1306 /* Retrieve from the default VNIC */
1309 if (!vnic->rss_table)
1312 if (reta_size != tbl_size) {
1313 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1314 "(%d) must equal the size supported by the hardware "
1315 "(%d)\n", reta_size, tbl_size);
1319 for (idx = 0, i = 0; i < reta_size; i++) {
1320 idx = i / RTE_RETA_GROUP_SIZE;
1321 sft = i % RTE_RETA_GROUP_SIZE;
1323 if (reta_conf[idx].mask & (1ULL << sft)) {
1326 if (BNXT_CHIP_THOR(bp))
1327 qid = bnxt_rss_to_qid(bp,
1328 vnic->rss_table[i * 2]);
1330 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1332 if (qid == INVALID_HW_RING_ID) {
1333 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1336 reta_conf[idx].reta[sft] = qid;
1343 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1344 struct rte_eth_rss_conf *rss_conf)
1346 struct bnxt *bp = eth_dev->data->dev_private;
1347 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1348 struct bnxt_vnic_info *vnic;
1351 rc = is_bnxt_in_error(bp);
1356 * If RSS enablement were different than dev_configure,
1357 * then return -EINVAL
1359 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1360 if (!rss_conf->rss_hf)
1361 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1363 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1367 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1368 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1370 /* Update the default RSS VNIC(s) */
1371 vnic = &bp->vnic_info[0];
1372 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1375 * Use the supplied key if the key length is
1376 * acceptable and the rss_key is not NULL
1378 if (rss_conf->rss_key && rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1379 memcpy(vnic->rss_hash_key,
1381 rss_conf->rss_key_len);
1383 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1387 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1388 struct rte_eth_rss_conf *rss_conf)
1390 struct bnxt *bp = eth_dev->data->dev_private;
1391 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1393 uint32_t hash_types;
1395 rc = is_bnxt_in_error(bp);
1399 /* RSS configuration is the same for all VNICs */
1400 if (vnic && vnic->rss_hash_key) {
1401 if (rss_conf->rss_key) {
1402 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1403 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1404 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1407 hash_types = vnic->hash_type;
1408 rss_conf->rss_hf = 0;
1409 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1410 rss_conf->rss_hf |= ETH_RSS_IPV4;
1411 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1413 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1414 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1416 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1418 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1419 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1421 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1423 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1424 rss_conf->rss_hf |= ETH_RSS_IPV6;
1425 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1427 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1428 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1430 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1432 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1433 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1435 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1439 "Unknwon RSS config from firmware (%08x), RSS disabled",
1444 rss_conf->rss_hf = 0;
1449 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1450 struct rte_eth_fc_conf *fc_conf)
1452 struct bnxt *bp = dev->data->dev_private;
1453 struct rte_eth_link link_info;
1456 rc = is_bnxt_in_error(bp);
1460 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1464 memset(fc_conf, 0, sizeof(*fc_conf));
1465 if (bp->link_info.auto_pause)
1466 fc_conf->autoneg = 1;
1467 switch (bp->link_info.pause) {
1469 fc_conf->mode = RTE_FC_NONE;
1471 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1472 fc_conf->mode = RTE_FC_TX_PAUSE;
1474 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1475 fc_conf->mode = RTE_FC_RX_PAUSE;
1477 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1478 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1479 fc_conf->mode = RTE_FC_FULL;
1485 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1486 struct rte_eth_fc_conf *fc_conf)
1488 struct bnxt *bp = dev->data->dev_private;
1491 rc = is_bnxt_in_error(bp);
1495 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1496 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1500 switch (fc_conf->mode) {
1502 bp->link_info.auto_pause = 0;
1503 bp->link_info.force_pause = 0;
1505 case RTE_FC_RX_PAUSE:
1506 if (fc_conf->autoneg) {
1507 bp->link_info.auto_pause =
1508 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1509 bp->link_info.force_pause = 0;
1511 bp->link_info.auto_pause = 0;
1512 bp->link_info.force_pause =
1513 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1516 case RTE_FC_TX_PAUSE:
1517 if (fc_conf->autoneg) {
1518 bp->link_info.auto_pause =
1519 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1520 bp->link_info.force_pause = 0;
1522 bp->link_info.auto_pause = 0;
1523 bp->link_info.force_pause =
1524 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1528 if (fc_conf->autoneg) {
1529 bp->link_info.auto_pause =
1530 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1531 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1532 bp->link_info.force_pause = 0;
1534 bp->link_info.auto_pause = 0;
1535 bp->link_info.force_pause =
1536 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1537 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1541 return bnxt_set_hwrm_link_config(bp, true);
1544 /* Add UDP tunneling port */
1546 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1547 struct rte_eth_udp_tunnel *udp_tunnel)
1549 struct bnxt *bp = eth_dev->data->dev_private;
1550 uint16_t tunnel_type = 0;
1553 rc = is_bnxt_in_error(bp);
1557 switch (udp_tunnel->prot_type) {
1558 case RTE_TUNNEL_TYPE_VXLAN:
1559 if (bp->vxlan_port_cnt) {
1560 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1561 udp_tunnel->udp_port);
1562 if (bp->vxlan_port != udp_tunnel->udp_port) {
1563 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1566 bp->vxlan_port_cnt++;
1570 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1571 bp->vxlan_port_cnt++;
1573 case RTE_TUNNEL_TYPE_GENEVE:
1574 if (bp->geneve_port_cnt) {
1575 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1576 udp_tunnel->udp_port);
1577 if (bp->geneve_port != udp_tunnel->udp_port) {
1578 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1581 bp->geneve_port_cnt++;
1585 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1586 bp->geneve_port_cnt++;
1589 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1592 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1598 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1599 struct rte_eth_udp_tunnel *udp_tunnel)
1601 struct bnxt *bp = eth_dev->data->dev_private;
1602 uint16_t tunnel_type = 0;
1606 rc = is_bnxt_in_error(bp);
1610 switch (udp_tunnel->prot_type) {
1611 case RTE_TUNNEL_TYPE_VXLAN:
1612 if (!bp->vxlan_port_cnt) {
1613 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1616 if (bp->vxlan_port != udp_tunnel->udp_port) {
1617 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1618 udp_tunnel->udp_port, bp->vxlan_port);
1621 if (--bp->vxlan_port_cnt)
1625 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1626 port = bp->vxlan_fw_dst_port_id;
1628 case RTE_TUNNEL_TYPE_GENEVE:
1629 if (!bp->geneve_port_cnt) {
1630 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1633 if (bp->geneve_port != udp_tunnel->udp_port) {
1634 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1635 udp_tunnel->udp_port, bp->geneve_port);
1638 if (--bp->geneve_port_cnt)
1642 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1643 port = bp->geneve_fw_dst_port_id;
1646 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1650 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1653 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1656 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1657 bp->geneve_port = 0;
1662 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1664 struct bnxt_filter_info *filter;
1665 struct bnxt_vnic_info *vnic;
1667 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1669 /* if VLAN exists && VLAN matches vlan_id
1670 * remove the MAC+VLAN filter
1671 * add a new MAC only filter
1673 * VLAN filter doesn't exist, just skip and continue
1675 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1676 filter = STAILQ_FIRST(&vnic->filter);
1678 /* Search for this matching MAC+VLAN filter */
1679 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1680 !memcmp(filter->l2_addr,
1682 RTE_ETHER_ADDR_LEN)) {
1683 /* Delete the filter */
1684 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1687 STAILQ_REMOVE(&vnic->filter, filter,
1688 bnxt_filter_info, next);
1689 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1692 "Del Vlan filter for %d\n",
1696 filter = STAILQ_NEXT(filter, next);
1701 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1703 struct bnxt_filter_info *filter;
1704 struct bnxt_vnic_info *vnic;
1706 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1707 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1708 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1710 /* Implementation notes on the use of VNIC in this command:
1712 * By default, these filters belong to default vnic for the function.
1713 * Once these filters are set up, only destination VNIC can be modified.
1714 * If the destination VNIC is not specified in this command,
1715 * then the HWRM shall only create an l2 context id.
1718 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1719 filter = STAILQ_FIRST(&vnic->filter);
1720 /* Check if the VLAN has already been added */
1722 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1723 !memcmp(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN))
1726 filter = STAILQ_NEXT(filter, next);
1729 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1730 * command to create MAC+VLAN filter with the right flags, enables set.
1732 filter = bnxt_alloc_filter(bp);
1735 "MAC/VLAN filter alloc failed\n");
1738 /* MAC + VLAN ID filter */
1739 filter->l2_ivlan = vlan_id;
1740 filter->l2_ivlan_mask = 0x0FFF;
1741 filter->enables |= en;
1742 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1744 /* Free the newly allocated filter as we were
1745 * not able to create the filter in hardware.
1747 filter->fw_l2_filter_id = UINT64_MAX;
1748 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1752 /* Add this new filter to the list */
1753 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1755 "Added Vlan filter for %d\n", vlan_id);
1759 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1760 uint16_t vlan_id, int on)
1762 struct bnxt *bp = eth_dev->data->dev_private;
1765 rc = is_bnxt_in_error(bp);
1769 /* These operations apply to ALL existing MAC/VLAN filters */
1771 return bnxt_add_vlan_filter(bp, vlan_id);
1773 return bnxt_del_vlan_filter(bp, vlan_id);
1777 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1779 struct bnxt *bp = dev->data->dev_private;
1780 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1784 rc = is_bnxt_in_error(bp);
1788 if (mask & ETH_VLAN_FILTER_MASK) {
1789 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1790 /* Remove any VLAN filters programmed */
1791 for (i = 0; i < 4095; i++)
1792 bnxt_del_vlan_filter(bp, i);
1794 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1795 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1798 if (mask & ETH_VLAN_STRIP_MASK) {
1799 /* Enable or disable VLAN stripping */
1800 for (i = 0; i < bp->nr_vnics; i++) {
1801 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1802 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1803 vnic->vlan_strip = true;
1805 vnic->vlan_strip = false;
1806 bnxt_hwrm_vnic_cfg(bp, vnic);
1808 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1809 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1812 if (mask & ETH_VLAN_EXTEND_MASK) {
1813 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1814 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
1816 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
1823 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
1826 struct bnxt *bp = dev->data->dev_private;
1827 int qinq = dev->data->dev_conf.rxmode.offloads &
1828 DEV_RX_OFFLOAD_VLAN_EXTEND;
1830 if (vlan_type != ETH_VLAN_TYPE_INNER &&
1831 vlan_type != ETH_VLAN_TYPE_OUTER) {
1833 "Unsupported vlan type.");
1838 "QinQ not enabled. Needs to be ON as we can "
1839 "accelerate only outer vlan\n");
1843 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
1845 case RTE_ETHER_TYPE_QINQ:
1847 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
1849 case RTE_ETHER_TYPE_VLAN:
1851 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
1855 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
1859 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
1863 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
1866 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
1869 bp->outer_tpid_bd |= tpid;
1870 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
1871 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
1873 "Can accelerate only outer vlan in QinQ\n");
1881 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1882 struct rte_ether_addr *addr)
1884 struct bnxt *bp = dev->data->dev_private;
1885 /* Default Filter is tied to VNIC 0 */
1886 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1887 struct bnxt_filter_info *filter;
1890 rc = is_bnxt_in_error(bp);
1894 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1897 if (rte_is_zero_ether_addr(addr))
1900 STAILQ_FOREACH(filter, &vnic->filter, next) {
1901 /* Default Filter is at Index 0 */
1902 if (filter->mac_index != 0)
1905 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
1906 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1907 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1909 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1910 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1912 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1916 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
1917 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1925 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1926 struct rte_ether_addr *mc_addr_set,
1927 uint32_t nb_mc_addr)
1929 struct bnxt *bp = eth_dev->data->dev_private;
1930 char *mc_addr_list = (char *)mc_addr_set;
1931 struct bnxt_vnic_info *vnic;
1932 uint32_t off = 0, i = 0;
1935 rc = is_bnxt_in_error(bp);
1939 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1941 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1942 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1946 /* TODO Check for Duplicate mcast addresses */
1947 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1948 for (i = 0; i < nb_mc_addr; i++) {
1949 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1950 RTE_ETHER_ADDR_LEN);
1951 off += RTE_ETHER_ADDR_LEN;
1954 vnic->mc_addr_cnt = i;
1957 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1961 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1963 struct bnxt *bp = dev->data->dev_private;
1964 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1965 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1966 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1969 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1970 fw_major, fw_minor, fw_updt);
1972 ret += 1; /* add the size of '\0' */
1973 if (fw_size < (uint32_t)ret)
1980 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1981 struct rte_eth_rxq_info *qinfo)
1983 struct bnxt_rx_queue *rxq;
1985 rxq = dev->data->rx_queues[queue_id];
1987 qinfo->mp = rxq->mb_pool;
1988 qinfo->scattered_rx = dev->data->scattered_rx;
1989 qinfo->nb_desc = rxq->nb_rx_desc;
1991 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1992 qinfo->conf.rx_drop_en = 0;
1993 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
1997 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1998 struct rte_eth_txq_info *qinfo)
2000 struct bnxt_tx_queue *txq;
2002 txq = dev->data->tx_queues[queue_id];
2004 qinfo->nb_desc = txq->nb_tx_desc;
2006 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2007 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2008 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2010 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2011 qinfo->conf.tx_rs_thresh = 0;
2012 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2015 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2017 struct bnxt *bp = eth_dev->data->dev_private;
2018 uint32_t new_pkt_size;
2022 rc = is_bnxt_in_error(bp);
2026 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2027 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2031 * If vector-mode tx/rx is active, disallow any MTU change that would
2032 * require scattered receive support.
2034 if (eth_dev->data->dev_started &&
2035 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2036 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2038 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2040 "MTU change would require scattered rx support. ");
2041 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2046 if (new_mtu > RTE_ETHER_MTU) {
2047 bp->flags |= BNXT_FLAG_JUMBO;
2048 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2049 DEV_RX_OFFLOAD_JUMBO_FRAME;
2051 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2052 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2053 bp->flags &= ~BNXT_FLAG_JUMBO;
2056 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2058 for (i = 0; i < bp->nr_vnics; i++) {
2059 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2062 vnic->mru = new_mtu + RTE_ETHER_HDR_LEN +
2063 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
2064 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2068 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2069 size -= RTE_PKTMBUF_HEADROOM;
2071 if (size < new_mtu) {
2072 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2078 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2084 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2086 struct bnxt *bp = dev->data->dev_private;
2087 uint16_t vlan = bp->vlan;
2090 rc = is_bnxt_in_error(bp);
2094 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2096 "PVID cannot be modified for this function\n");
2099 bp->vlan = on ? pvid : 0;
2101 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2108 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2110 struct bnxt *bp = dev->data->dev_private;
2113 rc = is_bnxt_in_error(bp);
2117 return bnxt_hwrm_port_led_cfg(bp, true);
2121 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2123 struct bnxt *bp = dev->data->dev_private;
2126 rc = is_bnxt_in_error(bp);
2130 return bnxt_hwrm_port_led_cfg(bp, false);
2134 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2136 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2137 uint32_t desc = 0, raw_cons = 0, cons;
2138 struct bnxt_cp_ring_info *cpr;
2139 struct bnxt_rx_queue *rxq;
2140 struct rx_pkt_cmpl *rxcmp;
2143 rc = is_bnxt_in_error(bp);
2147 rxq = dev->data->rx_queues[rx_queue_id];
2149 raw_cons = cpr->cp_raw_cons;
2152 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2153 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2154 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2156 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2168 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2170 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2171 struct bnxt_rx_ring_info *rxr;
2172 struct bnxt_cp_ring_info *cpr;
2173 struct bnxt_sw_rx_bd *rx_buf;
2174 struct rx_pkt_cmpl *rxcmp;
2175 uint32_t cons, cp_cons;
2181 rc = is_bnxt_in_error(rxq->bp);
2188 if (offset >= rxq->nb_rx_desc)
2191 cons = RING_CMP(cpr->cp_ring_struct, offset);
2192 cp_cons = cpr->cp_raw_cons;
2193 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2195 if (cons > cp_cons) {
2196 if (CMPL_VALID(rxcmp, cpr->valid))
2197 return RTE_ETH_RX_DESC_DONE;
2199 if (CMPL_VALID(rxcmp, !cpr->valid))
2200 return RTE_ETH_RX_DESC_DONE;
2202 rx_buf = &rxr->rx_buf_ring[cons];
2203 if (rx_buf->mbuf == NULL)
2204 return RTE_ETH_RX_DESC_UNAVAIL;
2207 return RTE_ETH_RX_DESC_AVAIL;
2211 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2213 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2214 struct bnxt_tx_ring_info *txr;
2215 struct bnxt_cp_ring_info *cpr;
2216 struct bnxt_sw_tx_bd *tx_buf;
2217 struct tx_pkt_cmpl *txcmp;
2218 uint32_t cons, cp_cons;
2224 rc = is_bnxt_in_error(txq->bp);
2231 if (offset >= txq->nb_tx_desc)
2234 cons = RING_CMP(cpr->cp_ring_struct, offset);
2235 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2236 cp_cons = cpr->cp_raw_cons;
2238 if (cons > cp_cons) {
2239 if (CMPL_VALID(txcmp, cpr->valid))
2240 return RTE_ETH_TX_DESC_UNAVAIL;
2242 if (CMPL_VALID(txcmp, !cpr->valid))
2243 return RTE_ETH_TX_DESC_UNAVAIL;
2245 tx_buf = &txr->tx_buf_ring[cons];
2246 if (tx_buf->mbuf == NULL)
2247 return RTE_ETH_TX_DESC_DONE;
2249 return RTE_ETH_TX_DESC_FULL;
2252 static struct bnxt_filter_info *
2253 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2254 struct rte_eth_ethertype_filter *efilter,
2255 struct bnxt_vnic_info *vnic0,
2256 struct bnxt_vnic_info *vnic,
2259 struct bnxt_filter_info *mfilter = NULL;
2263 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2264 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2265 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2266 " ethertype filter.", efilter->ether_type);
2270 if (efilter->queue >= bp->rx_nr_rings) {
2271 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2276 vnic0 = &bp->vnic_info[0];
2277 vnic = &bp->vnic_info[efilter->queue];
2279 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2284 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2285 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2286 if ((!memcmp(efilter->mac_addr.addr_bytes,
2287 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2289 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2290 mfilter->ethertype == efilter->ether_type)) {
2296 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2297 if ((!memcmp(efilter->mac_addr.addr_bytes,
2298 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2299 mfilter->ethertype == efilter->ether_type &&
2301 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2315 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2316 enum rte_filter_op filter_op,
2319 struct bnxt *bp = dev->data->dev_private;
2320 struct rte_eth_ethertype_filter *efilter =
2321 (struct rte_eth_ethertype_filter *)arg;
2322 struct bnxt_filter_info *bfilter, *filter1;
2323 struct bnxt_vnic_info *vnic, *vnic0;
2326 if (filter_op == RTE_ETH_FILTER_NOP)
2330 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2335 vnic0 = &bp->vnic_info[0];
2336 vnic = &bp->vnic_info[efilter->queue];
2338 switch (filter_op) {
2339 case RTE_ETH_FILTER_ADD:
2340 bnxt_match_and_validate_ether_filter(bp, efilter,
2345 bfilter = bnxt_get_unused_filter(bp);
2346 if (bfilter == NULL) {
2348 "Not enough resources for a new filter.\n");
2351 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2352 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2353 RTE_ETHER_ADDR_LEN);
2354 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2355 RTE_ETHER_ADDR_LEN);
2356 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2357 bfilter->ethertype = efilter->ether_type;
2358 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2360 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2361 if (filter1 == NULL) {
2366 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2367 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2369 bfilter->dst_id = vnic->fw_vnic_id;
2371 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2373 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2376 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2379 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2381 case RTE_ETH_FILTER_DELETE:
2382 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2384 if (ret == -EEXIST) {
2385 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2387 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2389 bnxt_free_filter(bp, filter1);
2390 } else if (ret == 0) {
2391 PMD_DRV_LOG(ERR, "No matching filter found\n");
2395 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2401 bnxt_free_filter(bp, bfilter);
2407 parse_ntuple_filter(struct bnxt *bp,
2408 struct rte_eth_ntuple_filter *nfilter,
2409 struct bnxt_filter_info *bfilter)
2413 if (nfilter->queue >= bp->rx_nr_rings) {
2414 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2418 switch (nfilter->dst_port_mask) {
2420 bfilter->dst_port_mask = -1;
2421 bfilter->dst_port = nfilter->dst_port;
2422 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2423 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2426 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2430 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2431 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2433 switch (nfilter->proto_mask) {
2435 if (nfilter->proto == 17) /* IPPROTO_UDP */
2436 bfilter->ip_protocol = 17;
2437 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2438 bfilter->ip_protocol = 6;
2441 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2444 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2448 switch (nfilter->dst_ip_mask) {
2450 bfilter->dst_ipaddr_mask[0] = -1;
2451 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2452 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2453 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2456 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2460 switch (nfilter->src_ip_mask) {
2462 bfilter->src_ipaddr_mask[0] = -1;
2463 bfilter->src_ipaddr[0] = nfilter->src_ip;
2464 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2465 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2468 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2472 switch (nfilter->src_port_mask) {
2474 bfilter->src_port_mask = -1;
2475 bfilter->src_port = nfilter->src_port;
2476 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2477 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2480 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2485 //nfilter->priority = (uint8_t)filter->priority;
2487 bfilter->enables = en;
2491 static struct bnxt_filter_info*
2492 bnxt_match_ntuple_filter(struct bnxt *bp,
2493 struct bnxt_filter_info *bfilter,
2494 struct bnxt_vnic_info **mvnic)
2496 struct bnxt_filter_info *mfilter = NULL;
2499 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2500 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2501 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2502 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2503 bfilter->src_ipaddr_mask[0] ==
2504 mfilter->src_ipaddr_mask[0] &&
2505 bfilter->src_port == mfilter->src_port &&
2506 bfilter->src_port_mask == mfilter->src_port_mask &&
2507 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2508 bfilter->dst_ipaddr_mask[0] ==
2509 mfilter->dst_ipaddr_mask[0] &&
2510 bfilter->dst_port == mfilter->dst_port &&
2511 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2512 bfilter->flags == mfilter->flags &&
2513 bfilter->enables == mfilter->enables) {
2524 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2525 struct rte_eth_ntuple_filter *nfilter,
2526 enum rte_filter_op filter_op)
2528 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2529 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2532 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2533 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2537 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2538 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2542 bfilter = bnxt_get_unused_filter(bp);
2543 if (bfilter == NULL) {
2545 "Not enough resources for a new filter.\n");
2548 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2552 vnic = &bp->vnic_info[nfilter->queue];
2553 vnic0 = &bp->vnic_info[0];
2554 filter1 = STAILQ_FIRST(&vnic0->filter);
2555 if (filter1 == NULL) {
2560 bfilter->dst_id = vnic->fw_vnic_id;
2561 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2563 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2564 bfilter->ethertype = 0x800;
2565 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2567 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2569 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2570 bfilter->dst_id == mfilter->dst_id) {
2571 PMD_DRV_LOG(ERR, "filter exists.\n");
2574 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2575 bfilter->dst_id != mfilter->dst_id) {
2576 mfilter->dst_id = vnic->fw_vnic_id;
2577 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2578 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2579 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2580 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2581 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2584 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2585 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2590 if (filter_op == RTE_ETH_FILTER_ADD) {
2591 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2592 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2595 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2597 if (mfilter == NULL) {
2598 /* This should not happen. But for Coverity! */
2602 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2604 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2605 bnxt_free_filter(bp, mfilter);
2606 mfilter->fw_l2_filter_id = -1;
2607 bnxt_free_filter(bp, bfilter);
2608 bfilter->fw_l2_filter_id = -1;
2613 bfilter->fw_l2_filter_id = -1;
2614 bnxt_free_filter(bp, bfilter);
2619 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2620 enum rte_filter_op filter_op,
2623 struct bnxt *bp = dev->data->dev_private;
2626 if (filter_op == RTE_ETH_FILTER_NOP)
2630 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2635 switch (filter_op) {
2636 case RTE_ETH_FILTER_ADD:
2637 ret = bnxt_cfg_ntuple_filter(bp,
2638 (struct rte_eth_ntuple_filter *)arg,
2641 case RTE_ETH_FILTER_DELETE:
2642 ret = bnxt_cfg_ntuple_filter(bp,
2643 (struct rte_eth_ntuple_filter *)arg,
2647 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2655 bnxt_parse_fdir_filter(struct bnxt *bp,
2656 struct rte_eth_fdir_filter *fdir,
2657 struct bnxt_filter_info *filter)
2659 enum rte_fdir_mode fdir_mode =
2660 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2661 struct bnxt_vnic_info *vnic0, *vnic;
2662 struct bnxt_filter_info *filter1;
2666 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2669 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2670 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2672 switch (fdir->input.flow_type) {
2673 case RTE_ETH_FLOW_IPV4:
2674 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2676 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2677 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2678 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2679 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2680 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2681 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2682 filter->ip_addr_type =
2683 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2684 filter->src_ipaddr_mask[0] = 0xffffffff;
2685 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2686 filter->dst_ipaddr_mask[0] = 0xffffffff;
2687 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2688 filter->ethertype = 0x800;
2689 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2691 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2692 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2693 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2694 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2695 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2696 filter->dst_port_mask = 0xffff;
2697 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2698 filter->src_port_mask = 0xffff;
2699 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2700 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2701 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2702 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2703 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2704 filter->ip_protocol = 6;
2705 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2706 filter->ip_addr_type =
2707 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2708 filter->src_ipaddr_mask[0] = 0xffffffff;
2709 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2710 filter->dst_ipaddr_mask[0] = 0xffffffff;
2711 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2712 filter->ethertype = 0x800;
2713 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2715 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2716 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2717 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2718 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2719 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2720 filter->dst_port_mask = 0xffff;
2721 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2722 filter->src_port_mask = 0xffff;
2723 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2724 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2725 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2726 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2727 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2728 filter->ip_protocol = 17;
2729 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2730 filter->ip_addr_type =
2731 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2732 filter->src_ipaddr_mask[0] = 0xffffffff;
2733 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2734 filter->dst_ipaddr_mask[0] = 0xffffffff;
2735 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2736 filter->ethertype = 0x800;
2737 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2739 case RTE_ETH_FLOW_IPV6:
2740 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2742 filter->ip_addr_type =
2743 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2744 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2745 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2746 rte_memcpy(filter->src_ipaddr,
2747 fdir->input.flow.ipv6_flow.src_ip, 16);
2748 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2749 rte_memcpy(filter->dst_ipaddr,
2750 fdir->input.flow.ipv6_flow.dst_ip, 16);
2751 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2752 memset(filter->dst_ipaddr_mask, 0xff, 16);
2753 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2754 memset(filter->src_ipaddr_mask, 0xff, 16);
2755 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2756 filter->ethertype = 0x86dd;
2757 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2759 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2760 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2761 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2762 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2763 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2764 filter->dst_port_mask = 0xffff;
2765 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2766 filter->src_port_mask = 0xffff;
2767 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2768 filter->ip_addr_type =
2769 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2770 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2771 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2772 rte_memcpy(filter->src_ipaddr,
2773 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2774 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2775 rte_memcpy(filter->dst_ipaddr,
2776 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2777 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2778 memset(filter->dst_ipaddr_mask, 0xff, 16);
2779 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2780 memset(filter->src_ipaddr_mask, 0xff, 16);
2781 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2782 filter->ethertype = 0x86dd;
2783 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2785 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2786 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2787 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2788 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2789 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2790 filter->dst_port_mask = 0xffff;
2791 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2792 filter->src_port_mask = 0xffff;
2793 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2794 filter->ip_addr_type =
2795 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2796 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2797 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2798 rte_memcpy(filter->src_ipaddr,
2799 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2800 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2801 rte_memcpy(filter->dst_ipaddr,
2802 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2803 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2804 memset(filter->dst_ipaddr_mask, 0xff, 16);
2805 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2806 memset(filter->src_ipaddr_mask, 0xff, 16);
2807 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2808 filter->ethertype = 0x86dd;
2809 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2811 case RTE_ETH_FLOW_L2_PAYLOAD:
2812 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2813 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2815 case RTE_ETH_FLOW_VXLAN:
2816 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2818 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2819 filter->tunnel_type =
2820 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2821 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2823 case RTE_ETH_FLOW_NVGRE:
2824 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2826 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2827 filter->tunnel_type =
2828 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2829 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2831 case RTE_ETH_FLOW_UNKNOWN:
2832 case RTE_ETH_FLOW_RAW:
2833 case RTE_ETH_FLOW_FRAG_IPV4:
2834 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2835 case RTE_ETH_FLOW_FRAG_IPV6:
2836 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2837 case RTE_ETH_FLOW_IPV6_EX:
2838 case RTE_ETH_FLOW_IPV6_TCP_EX:
2839 case RTE_ETH_FLOW_IPV6_UDP_EX:
2840 case RTE_ETH_FLOW_GENEVE:
2846 vnic0 = &bp->vnic_info[0];
2847 vnic = &bp->vnic_info[fdir->action.rx_queue];
2849 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2854 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2855 rte_memcpy(filter->dst_macaddr,
2856 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2857 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2860 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2861 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2862 filter1 = STAILQ_FIRST(&vnic0->filter);
2863 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2865 filter->dst_id = vnic->fw_vnic_id;
2866 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2867 if (filter->dst_macaddr[i] == 0x00)
2868 filter1 = STAILQ_FIRST(&vnic0->filter);
2870 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2873 if (filter1 == NULL)
2876 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2877 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2879 filter->enables = en;
2884 static struct bnxt_filter_info *
2885 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2886 struct bnxt_vnic_info **mvnic)
2888 struct bnxt_filter_info *mf = NULL;
2891 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2892 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2894 STAILQ_FOREACH(mf, &vnic->filter, next) {
2895 if (mf->filter_type == nf->filter_type &&
2896 mf->flags == nf->flags &&
2897 mf->src_port == nf->src_port &&
2898 mf->src_port_mask == nf->src_port_mask &&
2899 mf->dst_port == nf->dst_port &&
2900 mf->dst_port_mask == nf->dst_port_mask &&
2901 mf->ip_protocol == nf->ip_protocol &&
2902 mf->ip_addr_type == nf->ip_addr_type &&
2903 mf->ethertype == nf->ethertype &&
2904 mf->vni == nf->vni &&
2905 mf->tunnel_type == nf->tunnel_type &&
2906 mf->l2_ovlan == nf->l2_ovlan &&
2907 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2908 mf->l2_ivlan == nf->l2_ivlan &&
2909 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2910 !memcmp(mf->l2_addr, nf->l2_addr,
2911 RTE_ETHER_ADDR_LEN) &&
2912 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2913 RTE_ETHER_ADDR_LEN) &&
2914 !memcmp(mf->src_macaddr, nf->src_macaddr,
2915 RTE_ETHER_ADDR_LEN) &&
2916 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2917 RTE_ETHER_ADDR_LEN) &&
2918 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2919 sizeof(nf->src_ipaddr)) &&
2920 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2921 sizeof(nf->src_ipaddr_mask)) &&
2922 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2923 sizeof(nf->dst_ipaddr)) &&
2924 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2925 sizeof(nf->dst_ipaddr_mask))) {
2936 bnxt_fdir_filter(struct rte_eth_dev *dev,
2937 enum rte_filter_op filter_op,
2940 struct bnxt *bp = dev->data->dev_private;
2941 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
2942 struct bnxt_filter_info *filter, *match;
2943 struct bnxt_vnic_info *vnic, *mvnic;
2946 if (filter_op == RTE_ETH_FILTER_NOP)
2949 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2952 switch (filter_op) {
2953 case RTE_ETH_FILTER_ADD:
2954 case RTE_ETH_FILTER_DELETE:
2956 filter = bnxt_get_unused_filter(bp);
2957 if (filter == NULL) {
2959 "Not enough resources for a new flow.\n");
2963 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2966 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2968 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2969 vnic = &bp->vnic_info[0];
2971 vnic = &bp->vnic_info[fdir->action.rx_queue];
2973 match = bnxt_match_fdir(bp, filter, &mvnic);
2974 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2975 if (match->dst_id == vnic->fw_vnic_id) {
2976 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2980 match->dst_id = vnic->fw_vnic_id;
2981 ret = bnxt_hwrm_set_ntuple_filter(bp,
2984 STAILQ_REMOVE(&mvnic->filter, match,
2985 bnxt_filter_info, next);
2986 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2988 "Filter with matching pattern exist\n");
2990 "Updated it to new destination q\n");
2994 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2995 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3000 if (filter_op == RTE_ETH_FILTER_ADD) {
3001 ret = bnxt_hwrm_set_ntuple_filter(bp,
3006 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3008 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3009 STAILQ_REMOVE(&vnic->filter, match,
3010 bnxt_filter_info, next);
3011 bnxt_free_filter(bp, match);
3012 filter->fw_l2_filter_id = -1;
3013 bnxt_free_filter(bp, filter);
3016 case RTE_ETH_FILTER_FLUSH:
3017 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3018 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3020 STAILQ_FOREACH(filter, &vnic->filter, next) {
3021 if (filter->filter_type ==
3022 HWRM_CFA_NTUPLE_FILTER) {
3024 bnxt_hwrm_clear_ntuple_filter(bp,
3026 STAILQ_REMOVE(&vnic->filter, filter,
3027 bnxt_filter_info, next);
3032 case RTE_ETH_FILTER_UPDATE:
3033 case RTE_ETH_FILTER_STATS:
3034 case RTE_ETH_FILTER_INFO:
3035 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3038 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3045 filter->fw_l2_filter_id = -1;
3046 bnxt_free_filter(bp, filter);
3051 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
3052 enum rte_filter_type filter_type,
3053 enum rte_filter_op filter_op, void *arg)
3057 ret = is_bnxt_in_error(dev->data->dev_private);
3061 switch (filter_type) {
3062 case RTE_ETH_FILTER_TUNNEL:
3064 "filter type: %d: To be implemented\n", filter_type);
3066 case RTE_ETH_FILTER_FDIR:
3067 ret = bnxt_fdir_filter(dev, filter_op, arg);
3069 case RTE_ETH_FILTER_NTUPLE:
3070 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3072 case RTE_ETH_FILTER_ETHERTYPE:
3073 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3075 case RTE_ETH_FILTER_GENERIC:
3076 if (filter_op != RTE_ETH_FILTER_GET)
3078 *(const void **)arg = &bnxt_flow_ops;
3082 "Filter type (%d) not supported", filter_type);
3089 static const uint32_t *
3090 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3092 static const uint32_t ptypes[] = {
3093 RTE_PTYPE_L2_ETHER_VLAN,
3094 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3095 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3099 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3100 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3101 RTE_PTYPE_INNER_L4_ICMP,
3102 RTE_PTYPE_INNER_L4_TCP,
3103 RTE_PTYPE_INNER_L4_UDP,
3107 if (!dev->rx_pkt_burst)
3113 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3116 uint32_t reg_base = *reg_arr & 0xfffff000;
3120 for (i = 0; i < count; i++) {
3121 if ((reg_arr[i] & 0xfffff000) != reg_base)
3124 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3125 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3129 static int bnxt_map_ptp_regs(struct bnxt *bp)
3131 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3135 reg_arr = ptp->rx_regs;
3136 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3140 reg_arr = ptp->tx_regs;
3141 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3145 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3146 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3148 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3149 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3154 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3156 rte_write32(0, (uint8_t *)bp->bar0 +
3157 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3158 rte_write32(0, (uint8_t *)bp->bar0 +
3159 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3162 static uint64_t bnxt_cc_read(struct bnxt *bp)
3166 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3167 BNXT_GRCPF_REG_SYNC_TIME));
3168 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3169 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3173 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3175 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3178 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3179 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3180 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3183 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3184 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3185 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3186 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3187 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3188 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3193 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3195 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3196 struct bnxt_pf_info *pf = &bp->pf;
3203 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3204 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3205 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3208 port_id = pf->port_id;
3209 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3210 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3212 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3213 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3214 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3215 /* bnxt_clr_rx_ts(bp); TBD */
3219 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3220 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3221 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3222 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3228 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3231 struct bnxt *bp = dev->data->dev_private;
3232 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3237 ns = rte_timespec_to_ns(ts);
3238 /* Set the timecounters to a new value. */
3245 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3247 struct bnxt *bp = dev->data->dev_private;
3248 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3249 uint64_t ns, systime_cycles = 0;
3255 if (BNXT_CHIP_THOR(bp))
3256 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3259 systime_cycles = bnxt_cc_read(bp);
3261 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3262 *ts = rte_ns_to_timespec(ns);
3267 bnxt_timesync_enable(struct rte_eth_dev *dev)
3269 struct bnxt *bp = dev->data->dev_private;
3270 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3278 ptp->tx_tstamp_en = 1;
3279 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3281 rc = bnxt_hwrm_ptp_cfg(bp);
3285 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3286 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3287 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3289 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3290 ptp->tc.cc_shift = shift;
3291 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3293 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3294 ptp->rx_tstamp_tc.cc_shift = shift;
3295 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3297 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3298 ptp->tx_tstamp_tc.cc_shift = shift;
3299 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3301 if (!BNXT_CHIP_THOR(bp))
3302 bnxt_map_ptp_regs(bp);
3308 bnxt_timesync_disable(struct rte_eth_dev *dev)
3310 struct bnxt *bp = dev->data->dev_private;
3311 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3317 ptp->tx_tstamp_en = 0;
3320 bnxt_hwrm_ptp_cfg(bp);
3322 if (!BNXT_CHIP_THOR(bp))
3323 bnxt_unmap_ptp_regs(bp);
3329 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3330 struct timespec *timestamp,
3331 uint32_t flags __rte_unused)
3333 struct bnxt *bp = dev->data->dev_private;
3334 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3335 uint64_t rx_tstamp_cycles = 0;
3341 if (BNXT_CHIP_THOR(bp))
3342 rx_tstamp_cycles = ptp->rx_timestamp;
3344 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3346 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3347 *timestamp = rte_ns_to_timespec(ns);
3352 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3353 struct timespec *timestamp)
3355 struct bnxt *bp = dev->data->dev_private;
3356 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3357 uint64_t tx_tstamp_cycles = 0;
3364 if (BNXT_CHIP_THOR(bp))
3365 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3368 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3370 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3371 *timestamp = rte_ns_to_timespec(ns);
3377 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3379 struct bnxt *bp = dev->data->dev_private;
3380 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3385 ptp->tc.nsec += delta;
3391 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3393 struct bnxt *bp = dev->data->dev_private;
3395 uint32_t dir_entries;
3396 uint32_t entry_length;
3398 rc = is_bnxt_in_error(bp);
3402 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3403 bp->pdev->addr.domain, bp->pdev->addr.bus,
3404 bp->pdev->addr.devid, bp->pdev->addr.function);
3406 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3410 return dir_entries * entry_length;
3414 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3415 struct rte_dev_eeprom_info *in_eeprom)
3417 struct bnxt *bp = dev->data->dev_private;
3422 rc = is_bnxt_in_error(bp);
3426 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3427 "len = %d\n", bp->pdev->addr.domain,
3428 bp->pdev->addr.bus, bp->pdev->addr.devid,
3429 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3431 if (in_eeprom->offset == 0) /* special offset value to get directory */
3432 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3435 index = in_eeprom->offset >> 24;
3436 offset = in_eeprom->offset & 0xffffff;
3439 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3440 in_eeprom->length, in_eeprom->data);
3445 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3448 case BNX_DIR_TYPE_CHIMP_PATCH:
3449 case BNX_DIR_TYPE_BOOTCODE:
3450 case BNX_DIR_TYPE_BOOTCODE_2:
3451 case BNX_DIR_TYPE_APE_FW:
3452 case BNX_DIR_TYPE_APE_PATCH:
3453 case BNX_DIR_TYPE_KONG_FW:
3454 case BNX_DIR_TYPE_KONG_PATCH:
3455 case BNX_DIR_TYPE_BONO_FW:
3456 case BNX_DIR_TYPE_BONO_PATCH:
3464 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3467 case BNX_DIR_TYPE_AVS:
3468 case BNX_DIR_TYPE_EXP_ROM_MBA:
3469 case BNX_DIR_TYPE_PCIE:
3470 case BNX_DIR_TYPE_TSCF_UCODE:
3471 case BNX_DIR_TYPE_EXT_PHY:
3472 case BNX_DIR_TYPE_CCM:
3473 case BNX_DIR_TYPE_ISCSI_BOOT:
3474 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3475 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3483 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3485 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3486 bnxt_dir_type_is_other_exec_format(dir_type);
3490 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3491 struct rte_dev_eeprom_info *in_eeprom)
3493 struct bnxt *bp = dev->data->dev_private;
3494 uint8_t index, dir_op;
3495 uint16_t type, ext, ordinal, attr;
3498 rc = is_bnxt_in_error(bp);
3502 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3503 "len = %d\n", bp->pdev->addr.domain,
3504 bp->pdev->addr.bus, bp->pdev->addr.devid,
3505 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3508 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3512 type = in_eeprom->magic >> 16;
3514 if (type == 0xffff) { /* special value for directory operations */
3515 index = in_eeprom->magic & 0xff;
3516 dir_op = in_eeprom->magic >> 8;
3520 case 0x0e: /* erase */
3521 if (in_eeprom->offset != ~in_eeprom->magic)
3523 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3529 /* Create or re-write an NVM item: */
3530 if (bnxt_dir_type_is_executable(type) == true)
3532 ext = in_eeprom->magic & 0xffff;
3533 ordinal = in_eeprom->offset >> 16;
3534 attr = in_eeprom->offset & 0xffff;
3536 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3537 in_eeprom->data, in_eeprom->length);
3544 static const struct eth_dev_ops bnxt_dev_ops = {
3545 .dev_infos_get = bnxt_dev_info_get_op,
3546 .dev_close = bnxt_dev_close_op,
3547 .dev_configure = bnxt_dev_configure_op,
3548 .dev_start = bnxt_dev_start_op,
3549 .dev_stop = bnxt_dev_stop_op,
3550 .dev_set_link_up = bnxt_dev_set_link_up_op,
3551 .dev_set_link_down = bnxt_dev_set_link_down_op,
3552 .stats_get = bnxt_stats_get_op,
3553 .stats_reset = bnxt_stats_reset_op,
3554 .rx_queue_setup = bnxt_rx_queue_setup_op,
3555 .rx_queue_release = bnxt_rx_queue_release_op,
3556 .tx_queue_setup = bnxt_tx_queue_setup_op,
3557 .tx_queue_release = bnxt_tx_queue_release_op,
3558 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3559 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3560 .reta_update = bnxt_reta_update_op,
3561 .reta_query = bnxt_reta_query_op,
3562 .rss_hash_update = bnxt_rss_hash_update_op,
3563 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3564 .link_update = bnxt_link_update_op,
3565 .promiscuous_enable = bnxt_promiscuous_enable_op,
3566 .promiscuous_disable = bnxt_promiscuous_disable_op,
3567 .allmulticast_enable = bnxt_allmulticast_enable_op,
3568 .allmulticast_disable = bnxt_allmulticast_disable_op,
3569 .mac_addr_add = bnxt_mac_addr_add_op,
3570 .mac_addr_remove = bnxt_mac_addr_remove_op,
3571 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3572 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3573 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3574 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3575 .vlan_filter_set = bnxt_vlan_filter_set_op,
3576 .vlan_offload_set = bnxt_vlan_offload_set_op,
3577 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3578 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3579 .mtu_set = bnxt_mtu_set_op,
3580 .mac_addr_set = bnxt_set_default_mac_addr_op,
3581 .xstats_get = bnxt_dev_xstats_get_op,
3582 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3583 .xstats_reset = bnxt_dev_xstats_reset_op,
3584 .fw_version_get = bnxt_fw_version_get,
3585 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3586 .rxq_info_get = bnxt_rxq_info_get_op,
3587 .txq_info_get = bnxt_txq_info_get_op,
3588 .dev_led_on = bnxt_dev_led_on_op,
3589 .dev_led_off = bnxt_dev_led_off_op,
3590 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3591 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3592 .rx_queue_count = bnxt_rx_queue_count_op,
3593 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3594 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3595 .rx_queue_start = bnxt_rx_queue_start,
3596 .rx_queue_stop = bnxt_rx_queue_stop,
3597 .tx_queue_start = bnxt_tx_queue_start,
3598 .tx_queue_stop = bnxt_tx_queue_stop,
3599 .filter_ctrl = bnxt_filter_ctrl_op,
3600 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3601 .get_eeprom_length = bnxt_get_eeprom_length_op,
3602 .get_eeprom = bnxt_get_eeprom_op,
3603 .set_eeprom = bnxt_set_eeprom_op,
3604 .timesync_enable = bnxt_timesync_enable,
3605 .timesync_disable = bnxt_timesync_disable,
3606 .timesync_read_time = bnxt_timesync_read_time,
3607 .timesync_write_time = bnxt_timesync_write_time,
3608 .timesync_adjust_time = bnxt_timesync_adjust_time,
3609 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3610 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3613 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3617 /* Only pre-map the reset GRC registers using window 3 */
3618 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3619 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3621 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3626 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3628 struct bnxt_error_recovery_info *info = bp->recovery_info;
3629 uint32_t reg_base = 0xffffffff;
3632 /* Only pre-map the monitoring GRC registers using window 2 */
3633 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3634 uint32_t reg = info->status_regs[i];
3636 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3639 if (reg_base == 0xffffffff)
3640 reg_base = reg & 0xfffff000;
3641 if ((reg & 0xfffff000) != reg_base)
3644 /* Use mask 0xffc as the Lower 2 bits indicates
3645 * address space location
3647 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3651 if (reg_base == 0xffffffff)
3654 rte_write32(reg_base, (uint8_t *)bp->bar0 +
3655 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3660 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3662 struct bnxt_error_recovery_info *info = bp->recovery_info;
3663 uint32_t delay = info->delay_after_reset[index];
3664 uint32_t val = info->reset_reg_val[index];
3665 uint32_t reg = info->reset_reg[index];
3666 uint32_t type, offset;
3668 type = BNXT_FW_STATUS_REG_TYPE(reg);
3669 offset = BNXT_FW_STATUS_REG_OFF(reg);
3672 case BNXT_FW_STATUS_REG_TYPE_CFG:
3673 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3675 case BNXT_FW_STATUS_REG_TYPE_GRC:
3676 offset = bnxt_map_reset_regs(bp, offset);
3677 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3679 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3680 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3683 /* wait on a specific interval of time until core reset is complete */
3685 rte_delay_ms(delay);
3688 static void bnxt_dev_cleanup(struct bnxt *bp)
3690 bnxt_set_hwrm_link_config(bp, false);
3691 bp->link_info.link_up = 0;
3692 if (bp->dev_stopped == 0)
3693 bnxt_dev_stop_op(bp->eth_dev);
3695 bnxt_uninit_resources(bp, true);
3698 static int bnxt_restore_filters(struct bnxt *bp)
3700 struct rte_eth_dev *dev = bp->eth_dev;
3703 if (dev->data->all_multicast)
3704 ret = bnxt_allmulticast_enable_op(dev);
3705 if (dev->data->promiscuous)
3706 ret = bnxt_promiscuous_enable_op(dev);
3708 /* TODO restore other filters as well */
3712 static void bnxt_dev_recover(void *arg)
3714 struct bnxt *bp = arg;
3715 int timeout = bp->fw_reset_max_msecs;
3718 /* Clear Error flag so that device re-init should happen */
3719 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3722 rc = bnxt_hwrm_ver_get(bp);
3725 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3726 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3727 } while (rc && timeout);
3730 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3734 rc = bnxt_init_resources(bp, true);
3737 "Failed to initialize resources after reset\n");
3740 /* clear reset flag as the device is initialized now */
3741 bp->flags &= ~BNXT_FLAG_FW_RESET;
3743 rc = bnxt_dev_start_op(bp->eth_dev);
3745 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3749 rc = bnxt_restore_filters(bp);
3753 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3756 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3757 bnxt_uninit_resources(bp, false);
3758 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3761 void bnxt_dev_reset_and_resume(void *arg)
3763 struct bnxt *bp = arg;
3766 bnxt_dev_cleanup(bp);
3768 bnxt_wait_for_device_shutdown(bp);
3770 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3771 bnxt_dev_recover, (void *)bp);
3773 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3776 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3778 struct bnxt_error_recovery_info *info = bp->recovery_info;
3779 uint32_t reg = info->status_regs[index];
3780 uint32_t type, offset, val = 0;
3782 type = BNXT_FW_STATUS_REG_TYPE(reg);
3783 offset = BNXT_FW_STATUS_REG_OFF(reg);
3786 case BNXT_FW_STATUS_REG_TYPE_CFG:
3787 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3789 case BNXT_FW_STATUS_REG_TYPE_GRC:
3790 offset = info->mapped_status_regs[index];
3792 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3793 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3801 static int bnxt_fw_reset_all(struct bnxt *bp)
3803 struct bnxt_error_recovery_info *info = bp->recovery_info;
3807 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3808 /* Reset through master function driver */
3809 for (i = 0; i < info->reg_array_cnt; i++)
3810 bnxt_write_fw_reset_reg(bp, i);
3811 /* Wait for time specified by FW after triggering reset */
3812 rte_delay_ms(info->master_func_wait_period_after_reset);
3813 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3814 /* Reset with the help of Kong processor */
3815 rc = bnxt_hwrm_fw_reset(bp);
3817 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3823 static void bnxt_fw_reset_cb(void *arg)
3825 struct bnxt *bp = arg;
3826 struct bnxt_error_recovery_info *info = bp->recovery_info;
3829 /* Only Master function can do FW reset */
3830 if (bnxt_is_master_func(bp) &&
3831 bnxt_is_recovery_enabled(bp)) {
3832 rc = bnxt_fw_reset_all(bp);
3834 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3839 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3840 * EXCEPTION_FATAL_ASYNC event to all the functions
3841 * (including MASTER FUNC). After receiving this Async, all the active
3842 * drivers should treat this case as FW initiated recovery
3844 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3845 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3846 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3848 /* To recover from error */
3849 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3854 /* Driver should poll FW heartbeat, reset_counter with the frequency
3855 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3856 * When the driver detects heartbeat stop or change in reset_counter,
3857 * it has to trigger a reset to recover from the error condition.
3858 * A “master PF” is the function who will have the privilege to
3859 * initiate the chimp reset. The master PF will be elected by the
3860 * firmware and will be notified through async message.
3862 static void bnxt_check_fw_health(void *arg)
3864 struct bnxt *bp = arg;
3865 struct bnxt_error_recovery_info *info = bp->recovery_info;
3866 uint32_t val = 0, wait_msec;
3868 if (!info || !bnxt_is_recovery_enabled(bp) ||
3869 is_bnxt_in_error(bp))
3872 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3873 if (val == info->last_heart_beat)
3876 info->last_heart_beat = val;
3878 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3879 if (val != info->last_reset_counter)
3882 info->last_reset_counter = val;
3884 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3885 bnxt_check_fw_health, (void *)bp);
3889 /* Stop DMA to/from device */
3890 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3891 bp->flags |= BNXT_FLAG_FW_RESET;
3893 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
3895 if (bnxt_is_master_func(bp))
3896 wait_msec = info->master_func_wait_period;
3898 wait_msec = info->normal_func_wait_period;
3900 rte_eal_alarm_set(US_PER_MS * wait_msec,
3901 bnxt_fw_reset_cb, (void *)bp);
3904 void bnxt_schedule_fw_health_check(struct bnxt *bp)
3906 uint32_t polling_freq;
3908 if (!bnxt_is_recovery_enabled(bp))
3911 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
3914 polling_freq = bp->recovery_info->driver_polling_freq;
3916 rte_eal_alarm_set(US_PER_MS * polling_freq,
3917 bnxt_check_fw_health, (void *)bp);
3918 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3921 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
3923 if (!bnxt_is_recovery_enabled(bp))
3926 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
3927 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3930 static bool bnxt_vf_pciid(uint16_t id)
3932 if (id == BROADCOM_DEV_ID_57304_VF ||
3933 id == BROADCOM_DEV_ID_57406_VF ||
3934 id == BROADCOM_DEV_ID_5731X_VF ||
3935 id == BROADCOM_DEV_ID_5741X_VF ||
3936 id == BROADCOM_DEV_ID_57414_VF ||
3937 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3938 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3939 id == BROADCOM_DEV_ID_58802_VF ||
3940 id == BROADCOM_DEV_ID_57500_VF1 ||
3941 id == BROADCOM_DEV_ID_57500_VF2)
3946 bool bnxt_stratus_device(struct bnxt *bp)
3948 uint16_t id = bp->pdev->id.device_id;
3950 if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3951 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3952 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3957 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3959 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3960 struct bnxt *bp = eth_dev->data->dev_private;
3962 /* enable device (incl. PCI PM wakeup), and bus-mastering */
3963 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3964 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3965 if (!bp->bar0 || !bp->doorbell_base) {
3966 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
3970 bp->eth_dev = eth_dev;
3976 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
3977 struct bnxt_ctx_pg_info *ctx_pg,
3982 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
3983 const struct rte_memzone *mz = NULL;
3984 char mz_name[RTE_MEMZONE_NAMESIZE];
3985 rte_iova_t mz_phys_addr;
3986 uint64_t valid_bits = 0;
3993 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
3995 rmem->page_size = BNXT_PAGE_SIZE;
3996 rmem->pg_arr = ctx_pg->ctx_pg_arr;
3997 rmem->dma_arr = ctx_pg->ctx_dma_arr;
3998 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4000 valid_bits = PTU_PTE_VALID;
4002 if (rmem->nr_pages > 1) {
4003 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4004 "bnxt_ctx_pg_tbl%s_%x_%d",
4005 suffix, idx, bp->eth_dev->data->port_id);
4006 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4007 mz = rte_memzone_lookup(mz_name);
4009 mz = rte_memzone_reserve_aligned(mz_name,
4013 RTE_MEMZONE_SIZE_HINT_ONLY |
4014 RTE_MEMZONE_IOVA_CONTIG,
4020 memset(mz->addr, 0, mz->len);
4021 mz_phys_addr = mz->iova;
4022 if ((unsigned long)mz->addr == mz_phys_addr) {
4024 "physical address same as virtual\n");
4025 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4026 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4027 if (mz_phys_addr == RTE_BAD_IOVA) {
4029 "unable to map addr to phys memory\n");
4033 rte_mem_lock_page(((char *)mz->addr));
4035 rmem->pg_tbl = mz->addr;
4036 rmem->pg_tbl_map = mz_phys_addr;
4037 rmem->pg_tbl_mz = mz;
4040 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4041 suffix, idx, bp->eth_dev->data->port_id);
4042 mz = rte_memzone_lookup(mz_name);
4044 mz = rte_memzone_reserve_aligned(mz_name,
4048 RTE_MEMZONE_SIZE_HINT_ONLY |
4049 RTE_MEMZONE_IOVA_CONTIG,
4055 memset(mz->addr, 0, mz->len);
4056 mz_phys_addr = mz->iova;
4057 if ((unsigned long)mz->addr == mz_phys_addr) {
4059 "Memzone physical address same as virtual.\n");
4060 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4061 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
4062 rte_mem_lock_page(((char *)mz->addr) + sz);
4063 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4064 if (mz_phys_addr == RTE_BAD_IOVA) {
4066 "unable to map addr to phys memory\n");
4071 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4072 rte_mem_lock_page(((char *)mz->addr) + sz);
4073 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4074 rmem->dma_arr[i] = mz_phys_addr + sz;
4076 if (rmem->nr_pages > 1) {
4077 if (i == rmem->nr_pages - 2 &&
4078 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4079 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4080 else if (i == rmem->nr_pages - 1 &&
4081 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4082 valid_bits |= PTU_PTE_LAST;
4084 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4090 if (rmem->vmem_size)
4091 rmem->vmem = (void **)mz->addr;
4092 rmem->dma_arr[0] = mz_phys_addr;
4096 static void bnxt_free_ctx_mem(struct bnxt *bp)
4100 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4103 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4104 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4105 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4106 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4107 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4108 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4109 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4110 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4111 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4112 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4113 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4115 for (i = 0; i < BNXT_MAX_Q; i++) {
4116 if (bp->ctx->tqm_mem[i])
4117 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4124 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4126 #define min_t(type, x, y) ({ \
4127 type __min1 = (x); \
4128 type __min2 = (y); \
4129 __min1 < __min2 ? __min1 : __min2; })
4131 #define max_t(type, x, y) ({ \
4132 type __max1 = (x); \
4133 type __max2 = (y); \
4134 __max1 > __max2 ? __max1 : __max2; })
4136 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4138 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4140 struct bnxt_ctx_pg_info *ctx_pg;
4141 struct bnxt_ctx_mem_info *ctx;
4142 uint32_t mem_size, ena, entries;
4145 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4147 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4151 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4154 ctx_pg = &ctx->qp_mem;
4155 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4156 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4157 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4161 ctx_pg = &ctx->srq_mem;
4162 ctx_pg->entries = ctx->srq_max_l2_entries;
4163 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4164 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4168 ctx_pg = &ctx->cq_mem;
4169 ctx_pg->entries = ctx->cq_max_l2_entries;
4170 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4171 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4175 ctx_pg = &ctx->vnic_mem;
4176 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4177 ctx->vnic_max_ring_table_entries;
4178 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4179 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4183 ctx_pg = &ctx->stat_mem;
4184 ctx_pg->entries = ctx->stat_max_entries;
4185 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4186 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4190 entries = ctx->qp_max_l2_entries;
4191 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4192 entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4193 ctx->tqm_max_entries_per_ring);
4194 for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4195 ctx_pg = ctx->tqm_mem[i];
4196 /* use min tqm entries for now. */
4197 ctx_pg->entries = entries;
4198 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4199 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4202 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4205 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4206 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4209 "Failed to configure context mem: rc = %d\n", rc);
4211 ctx->flags |= BNXT_CTX_FLAG_INITED;
4216 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4218 struct rte_pci_device *pci_dev = bp->pdev;
4219 char mz_name[RTE_MEMZONE_NAMESIZE];
4220 const struct rte_memzone *mz = NULL;
4221 uint32_t total_alloc_len;
4222 rte_iova_t mz_phys_addr;
4224 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4227 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4228 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4229 pci_dev->addr.bus, pci_dev->addr.devid,
4230 pci_dev->addr.function, "rx_port_stats");
4231 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4232 mz = rte_memzone_lookup(mz_name);
4234 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4235 sizeof(struct rx_port_stats_ext) + 512);
4237 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4240 RTE_MEMZONE_SIZE_HINT_ONLY |
4241 RTE_MEMZONE_IOVA_CONTIG);
4245 memset(mz->addr, 0, mz->len);
4246 mz_phys_addr = mz->iova;
4247 if ((unsigned long)mz->addr == mz_phys_addr) {
4249 "Memzone physical address same as virtual.\n");
4251 "Using rte_mem_virt2iova()\n");
4252 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4253 if (mz_phys_addr == RTE_BAD_IOVA) {
4255 "Can't map address to physical memory\n");
4260 bp->rx_mem_zone = (const void *)mz;
4261 bp->hw_rx_port_stats = mz->addr;
4262 bp->hw_rx_port_stats_map = mz_phys_addr;
4264 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4265 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4266 pci_dev->addr.bus, pci_dev->addr.devid,
4267 pci_dev->addr.function, "tx_port_stats");
4268 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4269 mz = rte_memzone_lookup(mz_name);
4271 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4272 sizeof(struct tx_port_stats_ext) + 512);
4274 mz = rte_memzone_reserve(mz_name,
4278 RTE_MEMZONE_SIZE_HINT_ONLY |
4279 RTE_MEMZONE_IOVA_CONTIG);
4283 memset(mz->addr, 0, mz->len);
4284 mz_phys_addr = mz->iova;
4285 if ((unsigned long)mz->addr == mz_phys_addr) {
4287 "Memzone physical address same as virtual\n");
4288 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4289 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4290 if (mz_phys_addr == RTE_BAD_IOVA) {
4292 "Can't map address to physical memory\n");
4297 bp->tx_mem_zone = (const void *)mz;
4298 bp->hw_tx_port_stats = mz->addr;
4299 bp->hw_tx_port_stats_map = mz_phys_addr;
4300 bp->flags |= BNXT_FLAG_PORT_STATS;
4302 /* Display extended statistics if FW supports it */
4303 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4304 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4305 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4308 bp->hw_rx_port_stats_ext = (void *)
4309 ((uint8_t *)bp->hw_rx_port_stats +
4310 sizeof(struct rx_port_stats));
4311 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4312 sizeof(struct rx_port_stats);
4313 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4315 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4316 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4317 bp->hw_tx_port_stats_ext = (void *)
4318 ((uint8_t *)bp->hw_tx_port_stats +
4319 sizeof(struct tx_port_stats));
4320 bp->hw_tx_port_stats_ext_map =
4321 bp->hw_tx_port_stats_map +
4322 sizeof(struct tx_port_stats);
4323 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4329 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4331 struct bnxt *bp = eth_dev->data->dev_private;
4334 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4335 RTE_ETHER_ADDR_LEN *
4338 if (eth_dev->data->mac_addrs == NULL) {
4339 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4343 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4347 /* Generate a random MAC address, if none was assigned by PF */
4348 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4349 bnxt_eth_hw_addr_random(bp->mac_addr);
4351 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4352 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4353 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4355 rc = bnxt_hwrm_set_mac(bp);
4357 memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4358 RTE_ETHER_ADDR_LEN);
4362 /* Copy the permanent MAC from the FUNC_QCAPS response */
4363 memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4364 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4369 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4373 /* MAC is already configured in FW */
4374 if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4377 /* Restore the old MAC configured */
4378 rc = bnxt_hwrm_set_mac(bp);
4380 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4385 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4390 #define ALLOW_FUNC(x) \
4392 uint32_t arg = (x); \
4393 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4394 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4397 /* Forward all requests if firmware is new enough */
4398 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4399 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4400 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4401 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4403 PMD_DRV_LOG(WARNING,
4404 "Firmware too old for VF mailbox functionality\n");
4405 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4409 * The following are used for driver cleanup. If we disallow these,
4410 * VF drivers can't clean up cleanly.
4412 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4413 ALLOW_FUNC(HWRM_VNIC_FREE);
4414 ALLOW_FUNC(HWRM_RING_FREE);
4415 ALLOW_FUNC(HWRM_RING_GRP_FREE);
4416 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4417 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4418 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4419 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4420 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4423 static int bnxt_init_fw(struct bnxt *bp)
4428 rc = bnxt_hwrm_ver_get(bp);
4432 rc = bnxt_hwrm_func_reset(bp);
4436 rc = bnxt_hwrm_queue_qportcfg(bp);
4440 /* Get the MAX capabilities for this function */
4441 rc = bnxt_hwrm_func_qcaps(bp);
4445 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4449 /* Get the adapter error recovery support info */
4450 rc = bnxt_hwrm_error_recovery_qcfg(bp);
4452 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
4454 if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
4455 mtu != bp->eth_dev->data->mtu)
4456 bp->eth_dev->data->mtu = mtu;
4458 bnxt_hwrm_port_led_qcaps(bp);
4463 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4467 rc = bnxt_init_fw(bp);
4471 if (!reconfig_dev) {
4472 rc = bnxt_setup_mac_addr(bp->eth_dev);
4476 rc = bnxt_restore_dflt_mac(bp);
4481 bnxt_config_vf_req_fwd(bp);
4483 rc = bnxt_hwrm_func_driver_register(bp);
4485 PMD_DRV_LOG(ERR, "Failed to register driver");
4490 if (bp->pdev->max_vfs) {
4491 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4493 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4497 rc = bnxt_hwrm_allocate_pf_only(bp);
4500 "Failed to allocate PF resources");
4506 rc = bnxt_alloc_mem(bp, reconfig_dev);
4510 rc = bnxt_setup_int(bp);
4516 rc = bnxt_request_int(bp);
4524 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4526 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4527 static int version_printed;
4531 if (version_printed++ == 0)
4532 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4534 eth_dev->dev_ops = &bnxt_dev_ops;
4535 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4536 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4539 * For secondary processes, we don't initialise any further
4540 * as primary has already done this work.
4542 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4545 rte_eth_copy_pci_info(eth_dev, pci_dev);
4547 bp = eth_dev->data->dev_private;
4549 bp->dev_stopped = 1;
4551 if (bnxt_vf_pciid(pci_dev->id.device_id))
4552 bp->flags |= BNXT_FLAG_VF;
4554 if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
4555 pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
4556 pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
4557 pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 ||
4558 pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2)
4559 bp->flags |= BNXT_FLAG_THOR_CHIP;
4561 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4562 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4563 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4564 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4565 bp->flags |= BNXT_FLAG_STINGRAY;
4567 rc = bnxt_init_board(eth_dev);
4570 "Failed to initialize board rc: %x\n", rc);
4574 rc = bnxt_alloc_hwrm_resources(bp);
4577 "Failed to allocate hwrm resource rc: %x\n", rc);
4580 rc = bnxt_init_resources(bp, false);
4584 rc = bnxt_alloc_stats_mem(bp);
4589 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4590 pci_dev->mem_resource[0].phys_addr,
4591 pci_dev->mem_resource[0].addr);
4596 bnxt_dev_uninit(eth_dev);
4601 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4606 bnxt_free_mem(bp, reconfig_dev);
4607 bnxt_hwrm_func_buf_unrgtr(bp);
4608 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4609 bp->flags &= ~BNXT_FLAG_REGISTERED;
4610 bnxt_free_ctx_mem(bp);
4611 if (!reconfig_dev) {
4612 bnxt_free_hwrm_resources(bp);
4614 if (bp->recovery_info != NULL) {
4615 rte_free(bp->recovery_info);
4616 bp->recovery_info = NULL;
4620 rte_free(bp->ptp_cfg);
4626 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4628 struct bnxt *bp = eth_dev->data->dev_private;
4631 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4634 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4636 rc = bnxt_uninit_resources(bp, false);
4638 if (bp->grp_info != NULL) {
4639 rte_free(bp->grp_info);
4640 bp->grp_info = NULL;
4643 if (bp->tx_mem_zone) {
4644 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4645 bp->tx_mem_zone = NULL;
4648 if (bp->rx_mem_zone) {
4649 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4650 bp->rx_mem_zone = NULL;
4653 if (bp->dev_stopped == 0)
4654 bnxt_dev_close_op(eth_dev);
4656 rte_free(bp->pf.vf_info);
4657 eth_dev->dev_ops = NULL;
4658 eth_dev->rx_pkt_burst = NULL;
4659 eth_dev->tx_pkt_burst = NULL;
4664 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4665 struct rte_pci_device *pci_dev)
4667 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4671 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4673 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4674 return rte_eth_dev_pci_generic_remove(pci_dev,
4677 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4680 static struct rte_pci_driver bnxt_rte_pmd = {
4681 .id_table = bnxt_pci_id_map,
4682 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4683 .probe = bnxt_pci_probe,
4684 .remove = bnxt_pci_remove,
4688 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4690 if (strcmp(dev->device->driver->name, drv->driver.name))
4696 bool is_bnxt_supported(struct rte_eth_dev *dev)
4698 return is_device_supported(dev, &bnxt_rte_pmd);
4701 RTE_INIT(bnxt_init_log)
4703 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4704 if (bnxt_logtype_driver >= 0)
4705 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4708 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4709 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4710 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");