4 * Copyright(c) Broadcom Limited.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Broadcom Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 #include <rte_ethdev.h>
39 #include <rte_ethdev_pci.h>
40 #include <rte_malloc.h>
41 #include <rte_cycles.h>
45 #include "bnxt_filter.h"
46 #include "bnxt_hwrm.h"
48 #include "bnxt_ring.h"
51 #include "bnxt_stats.h"
54 #include "bnxt_vnic.h"
55 #include "hsi_struct_def_dpdk.h"
56 #include "bnxt_nvm_defs.h"
58 #define DRV_MODULE_NAME "bnxt"
59 static const char bnxt_version[] =
60 "Broadcom Cumulus driver " DRV_MODULE_NAME "\n";
62 #define PCI_VENDOR_ID_BROADCOM 0x14E4
64 #define BROADCOM_DEV_ID_STRATUS_NIC_VF 0x1609
65 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
66 #define BROADCOM_DEV_ID_57414_VF 0x16c1
67 #define BROADCOM_DEV_ID_57301 0x16c8
68 #define BROADCOM_DEV_ID_57302 0x16c9
69 #define BROADCOM_DEV_ID_57304_PF 0x16ca
70 #define BROADCOM_DEV_ID_57304_VF 0x16cb
71 #define BROADCOM_DEV_ID_57417_MF 0x16cc
72 #define BROADCOM_DEV_ID_NS2 0x16cd
73 #define BROADCOM_DEV_ID_57311 0x16ce
74 #define BROADCOM_DEV_ID_57312 0x16cf
75 #define BROADCOM_DEV_ID_57402 0x16d0
76 #define BROADCOM_DEV_ID_57404 0x16d1
77 #define BROADCOM_DEV_ID_57406_PF 0x16d2
78 #define BROADCOM_DEV_ID_57406_VF 0x16d3
79 #define BROADCOM_DEV_ID_57402_MF 0x16d4
80 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
81 #define BROADCOM_DEV_ID_57412 0x16d6
82 #define BROADCOM_DEV_ID_57414 0x16d7
83 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
84 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
85 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
86 #define BROADCOM_DEV_ID_57412_MF 0x16de
87 #define BROADCOM_DEV_ID_57314 0x16df
88 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
89 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
90 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
91 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
92 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
93 #define BROADCOM_DEV_ID_57404_MF 0x16e7
94 #define BROADCOM_DEV_ID_57406_MF 0x16e8
95 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
96 #define BROADCOM_DEV_ID_57407_MF 0x16ea
97 #define BROADCOM_DEV_ID_57414_MF 0x16ec
98 #define BROADCOM_DEV_ID_57416_MF 0x16ee
100 static const struct rte_pci_id bnxt_pci_id_map[] = {
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
102 BROADCOM_DEV_ID_STRATUS_NIC_VF) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
122 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
123 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
124 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
125 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
126 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
127 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
128 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
129 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
130 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
131 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
132 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
133 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
134 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
135 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
136 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
137 { .vendor_id = 0, /* sentinel */ },
140 #define BNXT_ETH_RSS_SUPPORT ( \
142 ETH_RSS_NONFRAG_IPV4_TCP | \
143 ETH_RSS_NONFRAG_IPV4_UDP | \
145 ETH_RSS_NONFRAG_IPV6_TCP | \
146 ETH_RSS_NONFRAG_IPV6_UDP)
148 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
150 /***********************/
153 * High level utility functions
156 static void bnxt_free_mem(struct bnxt *bp)
158 bnxt_free_filter_mem(bp);
159 bnxt_free_vnic_attributes(bp);
160 bnxt_free_vnic_mem(bp);
163 bnxt_free_tx_rings(bp);
164 bnxt_free_rx_rings(bp);
165 bnxt_free_def_cp_ring(bp);
168 static int bnxt_alloc_mem(struct bnxt *bp)
172 /* Default completion ring */
173 rc = bnxt_init_def_ring_struct(bp, SOCKET_ID_ANY);
177 rc = bnxt_alloc_rings(bp, 0, NULL, NULL,
178 bp->def_cp_ring, "def_cp");
182 rc = bnxt_alloc_vnic_mem(bp);
186 rc = bnxt_alloc_vnic_attributes(bp);
190 rc = bnxt_alloc_filter_mem(bp);
201 static int bnxt_init_chip(struct bnxt *bp)
203 unsigned int i, rss_idx, fw_idx;
204 struct rte_eth_link new;
205 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
206 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
207 uint32_t intr_vector = 0;
208 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
209 uint32_t vec = BNXT_MISC_VEC_ID;
212 /* disable uio/vfio intr/eventfd mapping */
213 rte_intr_disable(intr_handle);
215 if (bp->eth_dev->data->mtu > ETHER_MTU) {
216 bp->eth_dev->data->dev_conf.rxmode.jumbo_frame = 1;
217 bp->flags |= BNXT_FLAG_JUMBO;
219 bp->eth_dev->data->dev_conf.rxmode.jumbo_frame = 0;
220 bp->flags &= ~BNXT_FLAG_JUMBO;
223 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
225 RTE_LOG(ERR, PMD, "HWRM stat ctx alloc failure rc: %x\n", rc);
229 rc = bnxt_alloc_hwrm_rings(bp);
231 RTE_LOG(ERR, PMD, "HWRM ring alloc failure rc: %x\n", rc);
235 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
237 RTE_LOG(ERR, PMD, "HWRM ring grp alloc failure: %x\n", rc);
241 rc = bnxt_mq_rx_configure(bp);
243 RTE_LOG(ERR, PMD, "MQ mode configure failure rc: %x\n", rc);
247 /* VNIC configuration */
248 for (i = 0; i < bp->nr_vnics; i++) {
249 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
251 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
253 RTE_LOG(ERR, PMD, "HWRM vnic %d alloc failure rc: %x\n",
258 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
261 "HWRM vnic %d ctx alloc failure rc: %x\n",
266 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
268 RTE_LOG(ERR, PMD, "HWRM vnic %d cfg failure rc: %x\n",
273 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
276 "HWRM vnic %d filter failure rc: %x\n",
280 if (vnic->rss_table && vnic->hash_type) {
282 * Fill the RSS hash & redirection table with
283 * ring group ids for all VNICs
285 for (rss_idx = 0, fw_idx = 0;
286 rss_idx < HW_HASH_INDEX_SIZE;
287 rss_idx++, fw_idx++) {
288 if (vnic->fw_grp_ids[fw_idx] ==
291 vnic->rss_table[rss_idx] =
292 vnic->fw_grp_ids[fw_idx];
294 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
297 "HWRM vnic %d set RSS failure rc: %x\n",
303 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
305 if (bp->eth_dev->data->dev_conf.rxmode.enable_lro)
306 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
308 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
310 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
313 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
317 /* check and configure queue intr-vector mapping */
318 if ((rte_intr_cap_multiple(intr_handle) ||
319 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
320 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
321 intr_vector = bp->eth_dev->data->nb_rx_queues;
322 RTE_LOG(INFO, PMD, "%s(): intr_vector = %d\n", __func__,
324 if (intr_vector > bp->rx_cp_nr_rings) {
325 RTE_LOG(ERR, PMD, "At most %d intr queues supported",
329 if (rte_intr_efd_enable(intr_handle, intr_vector))
333 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
334 intr_handle->intr_vec =
335 rte_zmalloc("intr_vec",
336 bp->eth_dev->data->nb_rx_queues *
338 if (intr_handle->intr_vec == NULL) {
339 RTE_LOG(ERR, PMD, "Failed to allocate %d rx_queues"
340 " intr_vec", bp->eth_dev->data->nb_rx_queues);
343 RTE_LOG(DEBUG, PMD, "%s(): intr_handle->intr_vec = %p "
344 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
345 __func__, intr_handle->intr_vec, intr_handle->nb_efd,
346 intr_handle->max_intr);
349 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
351 intr_handle->intr_vec[queue_id] = vec;
352 if (vec < base + intr_handle->nb_efd - 1)
356 /* enable uio/vfio intr/eventfd mapping */
357 rte_intr_enable(intr_handle);
359 rc = bnxt_get_hwrm_link_config(bp, &new);
361 RTE_LOG(ERR, PMD, "HWRM Get link config failure rc: %x\n", rc);
365 if (!bp->link_info.link_up) {
366 rc = bnxt_set_hwrm_link_config(bp, true);
369 "HWRM link config failure rc: %x\n", rc);
377 bnxt_free_all_hwrm_resources(bp);
382 static int bnxt_shutdown_nic(struct bnxt *bp)
384 bnxt_free_all_hwrm_resources(bp);
385 bnxt_free_all_filters(bp);
386 bnxt_free_all_vnics(bp);
390 static int bnxt_init_nic(struct bnxt *bp)
394 bnxt_init_ring_grps(bp);
396 bnxt_init_filters(bp);
398 rc = bnxt_init_chip(bp);
406 * Device configuration and status function
409 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
410 struct rte_eth_dev_info *dev_info)
412 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
413 uint16_t max_vnics, i, j, vpool, vrxq;
414 unsigned int max_rx_rings;
416 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
419 dev_info->max_mac_addrs = bp->max_l2_ctx;
420 dev_info->max_hash_mac_addrs = 0;
422 /* PF/VF specifics */
424 dev_info->max_vfs = bp->pdev->max_vfs;
425 max_rx_rings = RTE_MIN(bp->max_vnics, RTE_MIN(bp->max_l2_ctx,
426 RTE_MIN(bp->max_rsscos_ctx,
428 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
429 dev_info->max_rx_queues = max_rx_rings;
430 dev_info->max_tx_queues = max_rx_rings;
431 dev_info->reta_size = bp->max_rsscos_ctx;
432 dev_info->hash_key_size = 40;
433 max_vnics = bp->max_vnics;
435 /* Fast path specifics */
436 dev_info->min_rx_bufsize = 1;
437 dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
439 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
440 DEV_RX_OFFLOAD_IPV4_CKSUM |
441 DEV_RX_OFFLOAD_UDP_CKSUM |
442 DEV_RX_OFFLOAD_TCP_CKSUM |
443 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
444 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
445 DEV_TX_OFFLOAD_IPV4_CKSUM |
446 DEV_TX_OFFLOAD_TCP_CKSUM |
447 DEV_TX_OFFLOAD_UDP_CKSUM |
448 DEV_TX_OFFLOAD_TCP_TSO |
449 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
450 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
451 DEV_TX_OFFLOAD_GRE_TNL_TSO |
452 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
453 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
456 dev_info->default_rxconf = (struct rte_eth_rxconf) {
462 .rx_free_thresh = 32,
466 dev_info->default_txconf = (struct rte_eth_txconf) {
472 .tx_free_thresh = 32,
474 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
475 ETH_TXQ_FLAGS_NOOFFLOADS,
477 eth_dev->data->dev_conf.intr_conf.lsc = 1;
479 eth_dev->data->dev_conf.intr_conf.rxq = 1;
484 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
485 * need further investigation.
489 vpool = 64; /* ETH_64_POOLS */
490 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
491 for (i = 0; i < 4; vpool >>= 1, i++) {
492 if (max_vnics > vpool) {
493 for (j = 0; j < 5; vrxq >>= 1, j++) {
494 if (dev_info->max_rx_queues > vrxq) {
500 /* Not enough resources to support VMDq */
504 /* Not enough resources to support VMDq */
508 dev_info->max_vmdq_pools = vpool;
509 dev_info->vmdq_queue_num = vrxq;
511 dev_info->vmdq_pool_base = 0;
512 dev_info->vmdq_queue_base = 0;
515 /* Configure the device based on the configuration provided */
516 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
518 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
520 bp->rx_queues = (void *)eth_dev->data->rx_queues;
521 bp->tx_queues = (void *)eth_dev->data->tx_queues;
523 /* Inherit new configurations */
524 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
525 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
526 bp->rx_cp_nr_rings = bp->rx_nr_rings;
527 bp->tx_cp_nr_rings = bp->tx_nr_rings;
529 if (eth_dev->data->dev_conf.rxmode.jumbo_frame)
531 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
532 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE;
537 rte_bnxt_atomic_write_link_status(struct rte_eth_dev *eth_dev,
538 struct rte_eth_link *link)
540 struct rte_eth_link *dst = ð_dev->data->dev_link;
541 struct rte_eth_link *src = link;
543 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
544 *(uint64_t *)src) == 0)
550 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
552 struct rte_eth_link *link = ð_dev->data->dev_link;
554 if (link->link_status)
555 RTE_LOG(INFO, PMD, "Port %d Link Up - speed %u Mbps - %s\n",
556 eth_dev->data->port_id,
557 (uint32_t)link->link_speed,
558 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
559 ("full-duplex") : ("half-duplex\n"));
561 RTE_LOG(INFO, PMD, "Port %d Link Down\n",
562 eth_dev->data->port_id);
565 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
567 bnxt_print_link_info(eth_dev);
571 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
573 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
577 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
579 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
580 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
584 rc = bnxt_init_nic(bp);
588 bnxt_link_update_op(eth_dev, 0);
590 if (eth_dev->data->dev_conf.rxmode.hw_vlan_filter)
591 vlan_mask |= ETH_VLAN_FILTER_MASK;
592 if (eth_dev->data->dev_conf.rxmode.hw_vlan_strip)
593 vlan_mask |= ETH_VLAN_STRIP_MASK;
594 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
601 bnxt_shutdown_nic(bp);
602 bnxt_free_tx_mbufs(bp);
603 bnxt_free_rx_mbufs(bp);
607 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
609 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
611 eth_dev->data->dev_link.link_status = 1;
612 bnxt_set_hwrm_link_config(bp, true);
616 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
618 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
620 eth_dev->data->dev_link.link_status = 0;
621 bnxt_set_hwrm_link_config(bp, false);
625 /* Unload the driver, release resources */
626 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
628 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
630 if (bp->eth_dev->data->dev_started) {
631 /* TBD: STOP HW queues DMA */
632 eth_dev->data->dev_link.link_status = 0;
634 bnxt_set_hwrm_link_config(bp, false);
635 bnxt_hwrm_port_clr_stats(bp);
636 bnxt_shutdown_nic(bp);
640 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
642 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
644 if (bp->dev_stopped == 0)
645 bnxt_dev_stop_op(eth_dev);
647 bnxt_free_tx_mbufs(bp);
648 bnxt_free_rx_mbufs(bp);
650 if (eth_dev->data->mac_addrs != NULL) {
651 rte_free(eth_dev->data->mac_addrs);
652 eth_dev->data->mac_addrs = NULL;
654 if (bp->grp_info != NULL) {
655 rte_free(bp->grp_info);
660 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
663 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
664 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
665 struct bnxt_vnic_info *vnic;
666 struct bnxt_filter_info *filter, *temp_filter;
667 uint32_t pool = RTE_MIN(MAX_FF_POOLS, ETH_64_POOLS);
671 * Loop through all VNICs from the specified filter flow pools to
672 * remove the corresponding MAC addr filter
674 for (i = 0; i < pool; i++) {
675 if (!(pool_mask & (1ULL << i)))
678 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
679 filter = STAILQ_FIRST(&vnic->filter);
681 temp_filter = STAILQ_NEXT(filter, next);
682 if (filter->mac_index == index) {
683 STAILQ_REMOVE(&vnic->filter, filter,
684 bnxt_filter_info, next);
685 bnxt_hwrm_clear_l2_filter(bp, filter);
686 filter->mac_index = INVALID_MAC_INDEX;
687 memset(&filter->l2_addr, 0,
690 &bp->free_filter_list,
693 filter = temp_filter;
699 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
700 struct ether_addr *mac_addr,
701 uint32_t index, uint32_t pool)
703 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
704 struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]);
705 struct bnxt_filter_info *filter;
708 RTE_LOG(ERR, PMD, "Cannot add MAC address to a VF interface\n");
713 RTE_LOG(ERR, PMD, "VNIC not found for pool %d!\n", pool);
716 /* Attach requested MAC address to the new l2_filter */
717 STAILQ_FOREACH(filter, &vnic->filter, next) {
718 if (filter->mac_index == index) {
720 "MAC addr already existed for pool %d\n", pool);
724 filter = bnxt_alloc_filter(bp);
726 RTE_LOG(ERR, PMD, "L2 filter alloc failed\n");
729 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
730 filter->mac_index = index;
731 memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
732 return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
735 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
738 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
739 struct rte_eth_link new;
740 unsigned int cnt = BNXT_LINK_WAIT_CNT;
742 memset(&new, 0, sizeof(new));
744 /* Retrieve link info from hardware */
745 rc = bnxt_get_hwrm_link_config(bp, &new);
747 new.link_speed = ETH_LINK_SPEED_100M;
748 new.link_duplex = ETH_LINK_FULL_DUPLEX;
750 "Failed to retrieve link rc = 0x%x!\n", rc);
753 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
755 if (!wait_to_complete)
757 } while (!new.link_status && cnt--);
760 /* Timed out or success */
761 if (new.link_status != eth_dev->data->dev_link.link_status ||
762 new.link_speed != eth_dev->data->dev_link.link_speed) {
763 rte_bnxt_atomic_write_link_status(eth_dev, &new);
764 bnxt_print_link_info(eth_dev);
770 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
772 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
773 struct bnxt_vnic_info *vnic;
775 if (bp->vnic_info == NULL)
778 vnic = &bp->vnic_info[0];
780 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
781 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
784 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
786 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
787 struct bnxt_vnic_info *vnic;
789 if (bp->vnic_info == NULL)
792 vnic = &bp->vnic_info[0];
794 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
795 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
798 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
800 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
801 struct bnxt_vnic_info *vnic;
803 if (bp->vnic_info == NULL)
806 vnic = &bp->vnic_info[0];
808 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
809 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
812 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
814 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
815 struct bnxt_vnic_info *vnic;
817 if (bp->vnic_info == NULL)
820 vnic = &bp->vnic_info[0];
822 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
823 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
826 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
827 struct rte_eth_rss_reta_entry64 *reta_conf,
830 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
831 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
832 struct bnxt_vnic_info *vnic;
835 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
838 if (reta_size != HW_HASH_INDEX_SIZE) {
839 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
840 "(%d) must equal the size supported by the hardware "
841 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
844 /* Update the RSS VNIC(s) */
845 for (i = 0; i < MAX_FF_POOLS; i++) {
846 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
847 memcpy(vnic->rss_table, reta_conf, reta_size);
849 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
855 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
856 struct rte_eth_rss_reta_entry64 *reta_conf,
859 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
860 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
861 struct rte_intr_handle *intr_handle
862 = &bp->pdev->intr_handle;
864 /* Retrieve from the default VNIC */
867 if (!vnic->rss_table)
870 if (reta_size != HW_HASH_INDEX_SIZE) {
871 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
872 "(%d) must equal the size supported by the hardware "
873 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
876 /* EW - need to revisit here copying from u64 to u16 */
877 memcpy(reta_conf, vnic->rss_table, reta_size);
879 if (rte_intr_allow_others(intr_handle)) {
880 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
881 bnxt_dev_lsc_intr_setup(eth_dev);
887 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
888 struct rte_eth_rss_conf *rss_conf)
890 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
891 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
892 struct bnxt_vnic_info *vnic;
893 uint16_t hash_type = 0;
897 * If RSS enablement were different than dev_configure,
898 * then return -EINVAL
900 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
901 if (!rss_conf->rss_hf)
902 RTE_LOG(ERR, PMD, "Hash type NONE\n");
904 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
908 bp->flags |= BNXT_FLAG_UPDATE_HASH;
909 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
911 if (rss_conf->rss_hf & ETH_RSS_IPV4)
912 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
913 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
914 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
915 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
916 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
917 if (rss_conf->rss_hf & ETH_RSS_IPV6)
918 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
919 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
920 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
921 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
922 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
924 /* Update the RSS VNIC(s) */
925 for (i = 0; i < MAX_FF_POOLS; i++) {
926 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
927 vnic->hash_type = hash_type;
930 * Use the supplied key if the key length is
931 * acceptable and the rss_key is not NULL
933 if (rss_conf->rss_key &&
934 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
935 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
936 rss_conf->rss_key_len);
938 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
944 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
945 struct rte_eth_rss_conf *rss_conf)
947 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
948 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
952 /* RSS configuration is the same for all VNICs */
953 if (vnic && vnic->rss_hash_key) {
954 if (rss_conf->rss_key) {
955 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
956 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
957 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
960 hash_types = vnic->hash_type;
961 rss_conf->rss_hf = 0;
962 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
963 rss_conf->rss_hf |= ETH_RSS_IPV4;
964 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
966 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
967 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
969 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
971 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
972 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
974 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
976 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
977 rss_conf->rss_hf |= ETH_RSS_IPV6;
978 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
980 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
981 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
983 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
985 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
986 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
988 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
992 "Unknwon RSS config from firmware (%08x), RSS disabled",
997 rss_conf->rss_hf = 0;
1002 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1003 struct rte_eth_fc_conf *fc_conf)
1005 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1006 struct rte_eth_link link_info;
1009 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1013 memset(fc_conf, 0, sizeof(*fc_conf));
1014 if (bp->link_info.auto_pause)
1015 fc_conf->autoneg = 1;
1016 switch (bp->link_info.pause) {
1018 fc_conf->mode = RTE_FC_NONE;
1020 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1021 fc_conf->mode = RTE_FC_TX_PAUSE;
1023 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1024 fc_conf->mode = RTE_FC_RX_PAUSE;
1026 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1027 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1028 fc_conf->mode = RTE_FC_FULL;
1034 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1035 struct rte_eth_fc_conf *fc_conf)
1037 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1039 if (BNXT_NPAR_PF(bp) || BNXT_VF(bp)) {
1040 RTE_LOG(ERR, PMD, "Flow Control Settings cannot be modified\n");
1044 switch (fc_conf->mode) {
1046 bp->link_info.auto_pause = 0;
1047 bp->link_info.force_pause = 0;
1049 case RTE_FC_RX_PAUSE:
1050 if (fc_conf->autoneg) {
1051 bp->link_info.auto_pause =
1052 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1053 bp->link_info.force_pause = 0;
1055 bp->link_info.auto_pause = 0;
1056 bp->link_info.force_pause =
1057 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1060 case RTE_FC_TX_PAUSE:
1061 if (fc_conf->autoneg) {
1062 bp->link_info.auto_pause =
1063 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1064 bp->link_info.force_pause = 0;
1066 bp->link_info.auto_pause = 0;
1067 bp->link_info.force_pause =
1068 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1072 if (fc_conf->autoneg) {
1073 bp->link_info.auto_pause =
1074 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1075 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1076 bp->link_info.force_pause = 0;
1078 bp->link_info.auto_pause = 0;
1079 bp->link_info.force_pause =
1080 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1081 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1085 return bnxt_set_hwrm_link_config(bp, true);
1088 /* Add UDP tunneling port */
1090 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1091 struct rte_eth_udp_tunnel *udp_tunnel)
1093 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1094 uint16_t tunnel_type = 0;
1097 switch (udp_tunnel->prot_type) {
1098 case RTE_TUNNEL_TYPE_VXLAN:
1099 if (bp->vxlan_port_cnt) {
1100 RTE_LOG(ERR, PMD, "Tunnel Port %d already programmed\n",
1101 udp_tunnel->udp_port);
1102 if (bp->vxlan_port != udp_tunnel->udp_port) {
1103 RTE_LOG(ERR, PMD, "Only one port allowed\n");
1106 bp->vxlan_port_cnt++;
1110 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1111 bp->vxlan_port_cnt++;
1113 case RTE_TUNNEL_TYPE_GENEVE:
1114 if (bp->geneve_port_cnt) {
1115 RTE_LOG(ERR, PMD, "Tunnel Port %d already programmed\n",
1116 udp_tunnel->udp_port);
1117 if (bp->geneve_port != udp_tunnel->udp_port) {
1118 RTE_LOG(ERR, PMD, "Only one port allowed\n");
1121 bp->geneve_port_cnt++;
1125 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1126 bp->geneve_port_cnt++;
1129 RTE_LOG(ERR, PMD, "Tunnel type is not supported\n");
1132 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1138 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1139 struct rte_eth_udp_tunnel *udp_tunnel)
1141 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1142 uint16_t tunnel_type = 0;
1146 switch (udp_tunnel->prot_type) {
1147 case RTE_TUNNEL_TYPE_VXLAN:
1148 if (!bp->vxlan_port_cnt) {
1149 RTE_LOG(ERR, PMD, "No Tunnel port configured yet\n");
1152 if (bp->vxlan_port != udp_tunnel->udp_port) {
1153 RTE_LOG(ERR, PMD, "Req Port: %d. Configured port: %d\n",
1154 udp_tunnel->udp_port, bp->vxlan_port);
1157 if (--bp->vxlan_port_cnt)
1161 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1162 port = bp->vxlan_fw_dst_port_id;
1164 case RTE_TUNNEL_TYPE_GENEVE:
1165 if (!bp->geneve_port_cnt) {
1166 RTE_LOG(ERR, PMD, "No Tunnel port configured yet\n");
1169 if (bp->geneve_port != udp_tunnel->udp_port) {
1170 RTE_LOG(ERR, PMD, "Req Port: %d. Configured port: %d\n",
1171 udp_tunnel->udp_port, bp->geneve_port);
1174 if (--bp->geneve_port_cnt)
1178 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1179 port = bp->geneve_fw_dst_port_id;
1182 RTE_LOG(ERR, PMD, "Tunnel type is not supported\n");
1186 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1189 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1192 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1193 bp->geneve_port = 0;
1198 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1200 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1201 struct bnxt_vnic_info *vnic;
1204 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1206 /* Cycle through all VNICs */
1207 for (i = 0; i < bp->nr_vnics; i++) {
1209 * For each VNIC and each associated filter(s)
1210 * if VLAN exists && VLAN matches vlan_id
1211 * remove the MAC+VLAN filter
1212 * add a new MAC only filter
1214 * VLAN filter doesn't exist, just skip and continue
1216 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1217 filter = STAILQ_FIRST(&vnic->filter);
1219 temp_filter = STAILQ_NEXT(filter, next);
1221 if (filter->enables & chk &&
1222 filter->l2_ovlan == vlan_id) {
1223 /* Must delete the filter */
1224 STAILQ_REMOVE(&vnic->filter, filter,
1225 bnxt_filter_info, next);
1226 bnxt_hwrm_clear_l2_filter(bp, filter);
1228 &bp->free_filter_list,
1232 * Need to examine to see if the MAC
1233 * filter already existed or not before
1234 * allocating a new one
1237 new_filter = bnxt_alloc_filter(bp);
1240 "MAC/VLAN filter alloc failed\n");
1244 STAILQ_INSERT_TAIL(&vnic->filter,
1246 /* Inherit MAC from previous filter */
1247 new_filter->mac_index =
1249 memcpy(new_filter->l2_addr,
1250 filter->l2_addr, ETHER_ADDR_LEN);
1251 /* MAC only filter */
1252 rc = bnxt_hwrm_set_l2_filter(bp,
1258 "Del Vlan filter for %d\n",
1261 filter = temp_filter;
1269 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1271 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1272 struct bnxt_vnic_info *vnic;
1275 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN |
1276 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK;
1277 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1279 /* Cycle through all VNICs */
1280 for (i = 0; i < bp->nr_vnics; i++) {
1282 * For each VNIC and each associated filter(s)
1284 * if VLAN matches vlan_id
1285 * VLAN filter already exists, just skip and continue
1287 * add a new MAC+VLAN filter
1289 * Remove the old MAC only filter
1290 * Add a new MAC+VLAN filter
1292 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1293 filter = STAILQ_FIRST(&vnic->filter);
1295 temp_filter = STAILQ_NEXT(filter, next);
1297 if (filter->enables & chk) {
1298 if (filter->l2_ovlan == vlan_id)
1301 /* Must delete the MAC filter */
1302 STAILQ_REMOVE(&vnic->filter, filter,
1303 bnxt_filter_info, next);
1304 bnxt_hwrm_clear_l2_filter(bp, filter);
1305 filter->l2_ovlan = 0;
1307 &bp->free_filter_list,
1310 new_filter = bnxt_alloc_filter(bp);
1313 "MAC/VLAN filter alloc failed\n");
1317 STAILQ_INSERT_TAIL(&vnic->filter, new_filter,
1319 /* Inherit MAC from the previous filter */
1320 new_filter->mac_index = filter->mac_index;
1321 memcpy(new_filter->l2_addr, filter->l2_addr,
1323 /* MAC + VLAN ID filter */
1324 new_filter->l2_ovlan = vlan_id;
1325 new_filter->l2_ovlan_mask = 0xF000;
1326 new_filter->enables |= en;
1327 rc = bnxt_hwrm_set_l2_filter(bp,
1333 "Added Vlan filter for %d\n", vlan_id);
1335 filter = temp_filter;
1343 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1344 uint16_t vlan_id, int on)
1346 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1348 /* These operations apply to ALL existing MAC/VLAN filters */
1350 return bnxt_add_vlan_filter(bp, vlan_id);
1352 return bnxt_del_vlan_filter(bp, vlan_id);
1356 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1358 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1361 if (mask & ETH_VLAN_FILTER_MASK) {
1362 if (!dev->data->dev_conf.rxmode.hw_vlan_filter) {
1363 /* Remove any VLAN filters programmed */
1364 for (i = 0; i < 4095; i++)
1365 bnxt_del_vlan_filter(bp, i);
1367 RTE_LOG(INFO, PMD, "VLAN Filtering: %d\n",
1368 dev->data->dev_conf.rxmode.hw_vlan_filter);
1371 if (mask & ETH_VLAN_STRIP_MASK) {
1372 /* Enable or disable VLAN stripping */
1373 for (i = 0; i < bp->nr_vnics; i++) {
1374 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1375 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1376 vnic->vlan_strip = true;
1378 vnic->vlan_strip = false;
1379 bnxt_hwrm_vnic_cfg(bp, vnic);
1381 RTE_LOG(INFO, PMD, "VLAN Strip Offload: %d\n",
1382 dev->data->dev_conf.rxmode.hw_vlan_strip);
1385 if (mask & ETH_VLAN_EXTEND_MASK)
1386 RTE_LOG(ERR, PMD, "Extend VLAN Not supported\n");
1392 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, struct ether_addr *addr)
1394 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1395 /* Default Filter is tied to VNIC 0 */
1396 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1397 struct bnxt_filter_info *filter;
1403 memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1404 memcpy(&dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
1406 STAILQ_FOREACH(filter, &vnic->filter, next) {
1407 /* Default Filter is at Index 0 */
1408 if (filter->mac_index != 0)
1410 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1413 memcpy(filter->l2_addr, bp->mac_addr, ETHER_ADDR_LEN);
1414 memset(filter->l2_addr_mask, 0xff, ETHER_ADDR_LEN);
1415 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1417 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1418 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1419 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1422 filter->mac_index = 0;
1423 RTE_LOG(DEBUG, PMD, "Set MAC addr\n");
1428 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1429 struct ether_addr *mc_addr_set,
1430 uint32_t nb_mc_addr)
1432 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1433 char *mc_addr_list = (char *)mc_addr_set;
1434 struct bnxt_vnic_info *vnic;
1435 uint32_t off = 0, i = 0;
1437 vnic = &bp->vnic_info[0];
1439 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1440 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1444 /* TODO Check for Duplicate mcast addresses */
1445 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1446 for (i = 0; i < nb_mc_addr; i++) {
1447 memcpy(vnic->mc_list + off, &mc_addr_list[i], ETHER_ADDR_LEN);
1448 off += ETHER_ADDR_LEN;
1451 vnic->mc_addr_cnt = i;
1454 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1458 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1460 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1461 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1462 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1463 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1466 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1467 fw_major, fw_minor, fw_updt);
1469 ret += 1; /* add the size of '\0' */
1470 if (fw_size < (uint32_t)ret)
1477 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1478 struct rte_eth_rxq_info *qinfo)
1480 struct bnxt_rx_queue *rxq;
1482 rxq = dev->data->rx_queues[queue_id];
1484 qinfo->mp = rxq->mb_pool;
1485 qinfo->scattered_rx = dev->data->scattered_rx;
1486 qinfo->nb_desc = rxq->nb_rx_desc;
1488 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1489 qinfo->conf.rx_drop_en = 0;
1490 qinfo->conf.rx_deferred_start = 0;
1494 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1495 struct rte_eth_txq_info *qinfo)
1497 struct bnxt_tx_queue *txq;
1499 txq = dev->data->tx_queues[queue_id];
1501 qinfo->nb_desc = txq->nb_tx_desc;
1503 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1504 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1505 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1507 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1508 qinfo->conf.tx_rs_thresh = 0;
1509 qinfo->conf.txq_flags = txq->txq_flags;
1510 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1513 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1515 struct bnxt *bp = eth_dev->data->dev_private;
1516 struct rte_eth_dev_info dev_info;
1517 uint32_t max_dev_mtu;
1521 bnxt_dev_info_get_op(eth_dev, &dev_info);
1522 max_dev_mtu = dev_info.max_rx_pktlen -
1523 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE * 2;
1525 if (new_mtu < ETHER_MIN_MTU || new_mtu > max_dev_mtu) {
1526 RTE_LOG(ERR, PMD, "MTU requested must be within (%d, %d)\n",
1527 ETHER_MIN_MTU, max_dev_mtu);
1532 if (new_mtu > ETHER_MTU) {
1533 bp->flags |= BNXT_FLAG_JUMBO;
1534 eth_dev->data->dev_conf.rxmode.jumbo_frame = 1;
1536 eth_dev->data->dev_conf.rxmode.jumbo_frame = 0;
1537 bp->flags &= ~BNXT_FLAG_JUMBO;
1540 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len =
1541 new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1543 eth_dev->data->mtu = new_mtu;
1544 RTE_LOG(INFO, PMD, "New MTU is %d\n", eth_dev->data->mtu);
1546 for (i = 0; i < bp->nr_vnics; i++) {
1547 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1549 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1550 ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1551 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1555 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1564 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1566 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1567 uint16_t vlan = bp->vlan;
1570 if (BNXT_NPAR_PF(bp) || BNXT_VF(bp)) {
1572 "PVID cannot be modified for this function\n");
1575 bp->vlan = on ? pvid : 0;
1577 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1584 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1586 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1588 return bnxt_hwrm_port_led_cfg(bp, true);
1592 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1594 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1596 return bnxt_hwrm_port_led_cfg(bp, false);
1600 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1602 uint32_t desc = 0, raw_cons = 0, cons;
1603 struct bnxt_cp_ring_info *cpr;
1604 struct bnxt_rx_queue *rxq;
1605 struct rx_pkt_cmpl *rxcmp;
1610 rxq = dev->data->rx_queues[rx_queue_id];
1614 while (raw_cons < rxq->nb_rx_desc) {
1615 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1616 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1618 if (!CMPL_VALID(rxcmp, valid))
1620 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1621 cmp_type = CMP_TYPE(rxcmp);
1622 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1623 cmp = (rte_le_to_cpu_32(
1624 ((struct rx_tpa_end_cmpl *)
1625 (rxcmp))->agg_bufs_v1) &
1626 RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1627 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1629 } else if (cmp_type == 0x11) {
1631 cmp = (rxcmp->agg_bufs_v1 &
1632 RX_PKT_CMPL_AGG_BUFS_MASK) >>
1633 RX_PKT_CMPL_AGG_BUFS_SFT;
1638 raw_cons += cmp ? cmp : 2;
1645 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1647 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1648 struct bnxt_rx_ring_info *rxr;
1649 struct bnxt_cp_ring_info *cpr;
1650 struct bnxt_sw_rx_bd *rx_buf;
1651 struct rx_pkt_cmpl *rxcmp;
1652 uint32_t cons, cp_cons;
1660 if (offset >= rxq->nb_rx_desc)
1663 cons = RING_CMP(cpr->cp_ring_struct, offset);
1664 cp_cons = cpr->cp_raw_cons;
1665 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1667 if (cons > cp_cons) {
1668 if (CMPL_VALID(rxcmp, cpr->valid))
1669 return RTE_ETH_RX_DESC_DONE;
1671 if (CMPL_VALID(rxcmp, !cpr->valid))
1672 return RTE_ETH_RX_DESC_DONE;
1674 rx_buf = &rxr->rx_buf_ring[cons];
1675 if (rx_buf->mbuf == NULL)
1676 return RTE_ETH_RX_DESC_UNAVAIL;
1679 return RTE_ETH_RX_DESC_AVAIL;
1683 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1685 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1686 struct bnxt_tx_ring_info *txr;
1687 struct bnxt_cp_ring_info *cpr;
1688 struct bnxt_sw_tx_bd *tx_buf;
1689 struct tx_pkt_cmpl *txcmp;
1690 uint32_t cons, cp_cons;
1698 if (offset >= txq->nb_tx_desc)
1701 cons = RING_CMP(cpr->cp_ring_struct, offset);
1702 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1703 cp_cons = cpr->cp_raw_cons;
1705 if (cons > cp_cons) {
1706 if (CMPL_VALID(txcmp, cpr->valid))
1707 return RTE_ETH_TX_DESC_UNAVAIL;
1709 if (CMPL_VALID(txcmp, !cpr->valid))
1710 return RTE_ETH_TX_DESC_UNAVAIL;
1712 tx_buf = &txr->tx_buf_ring[cons];
1713 if (tx_buf->mbuf == NULL)
1714 return RTE_ETH_TX_DESC_DONE;
1716 return RTE_ETH_TX_DESC_FULL;
1719 static struct bnxt_filter_info *
1720 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
1721 struct rte_eth_ethertype_filter *efilter,
1722 struct bnxt_vnic_info *vnic0,
1723 struct bnxt_vnic_info *vnic,
1726 struct bnxt_filter_info *mfilter = NULL;
1730 if (efilter->ether_type != ETHER_TYPE_IPv4 &&
1731 efilter->ether_type != ETHER_TYPE_IPv6) {
1732 RTE_LOG(ERR, PMD, "unsupported ether_type(0x%04x) in"
1733 " ethertype filter.", efilter->ether_type);
1737 if (efilter->queue >= bp->rx_nr_rings) {
1738 RTE_LOG(ERR, PMD, "Invalid queue %d\n", efilter->queue);
1743 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1744 vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1746 RTE_LOG(ERR, PMD, "Invalid queue %d\n", efilter->queue);
1751 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1752 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
1753 if ((!memcmp(efilter->mac_addr.addr_bytes,
1754 mfilter->l2_addr, ETHER_ADDR_LEN) &&
1756 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
1757 mfilter->ethertype == efilter->ether_type)) {
1763 STAILQ_FOREACH(mfilter, &vnic->filter, next)
1764 if ((!memcmp(efilter->mac_addr.addr_bytes,
1765 mfilter->l2_addr, ETHER_ADDR_LEN) &&
1766 mfilter->ethertype == efilter->ether_type &&
1768 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
1782 bnxt_ethertype_filter(struct rte_eth_dev *dev,
1783 enum rte_filter_op filter_op,
1786 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1787 struct rte_eth_ethertype_filter *efilter =
1788 (struct rte_eth_ethertype_filter *)arg;
1789 struct bnxt_filter_info *bfilter, *filter1;
1790 struct bnxt_vnic_info *vnic, *vnic0;
1793 if (filter_op == RTE_ETH_FILTER_NOP)
1797 RTE_LOG(ERR, PMD, "arg shouldn't be NULL for operation %u.",
1802 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1803 vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1805 switch (filter_op) {
1806 case RTE_ETH_FILTER_ADD:
1807 bnxt_match_and_validate_ether_filter(bp, efilter,
1812 bfilter = bnxt_get_unused_filter(bp);
1813 if (bfilter == NULL) {
1815 "Not enough resources for a new filter.\n");
1818 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
1819 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
1821 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
1823 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
1824 bfilter->ethertype = efilter->ether_type;
1825 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
1827 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
1828 if (filter1 == NULL) {
1833 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
1834 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
1836 bfilter->dst_id = vnic->fw_vnic_id;
1838 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1840 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
1843 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
1846 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
1848 case RTE_ETH_FILTER_DELETE:
1849 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
1851 if (ret == -EEXIST) {
1852 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
1854 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
1856 bnxt_free_filter(bp, filter1);
1857 } else if (ret == 0) {
1858 RTE_LOG(ERR, PMD, "No matching filter found\n");
1862 RTE_LOG(ERR, PMD, "unsupported operation %u.", filter_op);
1868 bnxt_free_filter(bp, bfilter);
1874 parse_ntuple_filter(struct bnxt *bp,
1875 struct rte_eth_ntuple_filter *nfilter,
1876 struct bnxt_filter_info *bfilter)
1880 if (nfilter->queue >= bp->rx_nr_rings) {
1881 RTE_LOG(ERR, PMD, "Invalid queue %d\n", nfilter->queue);
1885 switch (nfilter->dst_port_mask) {
1887 bfilter->dst_port_mask = -1;
1888 bfilter->dst_port = nfilter->dst_port;
1889 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
1890 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
1893 RTE_LOG(ERR, PMD, "invalid dst_port mask.");
1897 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
1898 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1900 switch (nfilter->proto_mask) {
1902 if (nfilter->proto == 17) /* IPPROTO_UDP */
1903 bfilter->ip_protocol = 17;
1904 else if (nfilter->proto == 6) /* IPPROTO_TCP */
1905 bfilter->ip_protocol = 6;
1908 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1911 RTE_LOG(ERR, PMD, "invalid protocol mask.");
1915 switch (nfilter->dst_ip_mask) {
1917 bfilter->dst_ipaddr_mask[0] = -1;
1918 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
1919 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
1920 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
1923 RTE_LOG(ERR, PMD, "invalid dst_ip mask.");
1927 switch (nfilter->src_ip_mask) {
1929 bfilter->src_ipaddr_mask[0] = -1;
1930 bfilter->src_ipaddr[0] = nfilter->src_ip;
1931 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
1932 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
1935 RTE_LOG(ERR, PMD, "invalid src_ip mask.");
1939 switch (nfilter->src_port_mask) {
1941 bfilter->src_port_mask = -1;
1942 bfilter->src_port = nfilter->src_port;
1943 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
1944 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
1947 RTE_LOG(ERR, PMD, "invalid src_port mask.");
1952 //nfilter->priority = (uint8_t)filter->priority;
1954 bfilter->enables = en;
1958 static struct bnxt_filter_info*
1959 bnxt_match_ntuple_filter(struct bnxt *bp,
1960 struct bnxt_filter_info *bfilter)
1962 struct bnxt_filter_info *mfilter = NULL;
1965 for (i = bp->nr_vnics - 1; i >= 0; i--) {
1966 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1967 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
1968 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
1969 bfilter->src_ipaddr_mask[0] ==
1970 mfilter->src_ipaddr_mask[0] &&
1971 bfilter->src_port == mfilter->src_port &&
1972 bfilter->src_port_mask == mfilter->src_port_mask &&
1973 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
1974 bfilter->dst_ipaddr_mask[0] ==
1975 mfilter->dst_ipaddr_mask[0] &&
1976 bfilter->dst_port == mfilter->dst_port &&
1977 bfilter->dst_port_mask == mfilter->dst_port_mask &&
1978 bfilter->flags == mfilter->flags &&
1979 bfilter->enables == mfilter->enables)
1987 bnxt_cfg_ntuple_filter(struct bnxt *bp,
1988 struct rte_eth_ntuple_filter *nfilter,
1989 enum rte_filter_op filter_op)
1991 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
1992 struct bnxt_vnic_info *vnic, *vnic0;
1995 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
1996 RTE_LOG(ERR, PMD, "only 5tuple is supported.");
2000 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2001 RTE_LOG(ERR, PMD, "Ntuple filter: TCP flags not supported\n");
2005 bfilter = bnxt_get_unused_filter(bp);
2006 if (bfilter == NULL) {
2008 "Not enough resources for a new filter.\n");
2011 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2015 vnic = STAILQ_FIRST(&bp->ff_pool[nfilter->queue]);
2016 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
2017 filter1 = STAILQ_FIRST(&vnic0->filter);
2018 if (filter1 == NULL) {
2023 bfilter->dst_id = vnic->fw_vnic_id;
2024 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2026 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2027 bfilter->ethertype = 0x800;
2028 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2030 mfilter = bnxt_match_ntuple_filter(bp, bfilter);
2032 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2033 RTE_LOG(ERR, PMD, "filter exists.");
2037 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2038 RTE_LOG(ERR, PMD, "filter doesn't exist.");
2043 if (filter_op == RTE_ETH_FILTER_ADD) {
2044 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2045 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2048 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2050 if (mfilter == NULL) {
2051 /* This should not happen. But for Coverity! */
2055 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2057 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info,
2059 bnxt_free_filter(bp, mfilter);
2060 bfilter->fw_l2_filter_id = -1;
2061 bnxt_free_filter(bp, bfilter);
2066 bfilter->fw_l2_filter_id = -1;
2067 bnxt_free_filter(bp, bfilter);
2072 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2073 enum rte_filter_op filter_op,
2076 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2079 if (filter_op == RTE_ETH_FILTER_NOP)
2083 RTE_LOG(ERR, PMD, "arg shouldn't be NULL for operation %u.",
2088 switch (filter_op) {
2089 case RTE_ETH_FILTER_ADD:
2090 ret = bnxt_cfg_ntuple_filter(bp,
2091 (struct rte_eth_ntuple_filter *)arg,
2094 case RTE_ETH_FILTER_DELETE:
2095 ret = bnxt_cfg_ntuple_filter(bp,
2096 (struct rte_eth_ntuple_filter *)arg,
2100 RTE_LOG(ERR, PMD, "unsupported operation %u.", filter_op);
2108 bnxt_parse_fdir_filter(struct bnxt *bp,
2109 struct rte_eth_fdir_filter *fdir,
2110 struct bnxt_filter_info *filter)
2112 enum rte_fdir_mode fdir_mode =
2113 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2114 struct bnxt_vnic_info *vnic0, *vnic;
2115 struct bnxt_filter_info *filter1;
2119 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2122 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2123 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2125 switch (fdir->input.flow_type) {
2126 case RTE_ETH_FLOW_IPV4:
2127 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2129 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2130 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2131 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2132 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2133 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2134 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2135 filter->ip_addr_type =
2136 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2137 filter->src_ipaddr_mask[0] = 0xffffffff;
2138 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2139 filter->dst_ipaddr_mask[0] = 0xffffffff;
2140 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2141 filter->ethertype = 0x800;
2142 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2144 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2145 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2146 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2147 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2148 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2149 filter->dst_port_mask = 0xffff;
2150 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2151 filter->src_port_mask = 0xffff;
2152 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2153 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2154 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2155 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2156 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2157 filter->ip_protocol = 6;
2158 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2159 filter->ip_addr_type =
2160 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2161 filter->src_ipaddr_mask[0] = 0xffffffff;
2162 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2163 filter->dst_ipaddr_mask[0] = 0xffffffff;
2164 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2165 filter->ethertype = 0x800;
2166 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2168 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2169 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2170 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2171 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2172 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2173 filter->dst_port_mask = 0xffff;
2174 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2175 filter->src_port_mask = 0xffff;
2176 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2177 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2178 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2179 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2180 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2181 filter->ip_protocol = 17;
2182 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2183 filter->ip_addr_type =
2184 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2185 filter->src_ipaddr_mask[0] = 0xffffffff;
2186 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2187 filter->dst_ipaddr_mask[0] = 0xffffffff;
2188 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2189 filter->ethertype = 0x800;
2190 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2192 case RTE_ETH_FLOW_IPV6:
2193 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2195 filter->ip_addr_type =
2196 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2197 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2198 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2199 rte_memcpy(filter->src_ipaddr,
2200 fdir->input.flow.ipv6_flow.src_ip, 16);
2201 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2202 rte_memcpy(filter->dst_ipaddr,
2203 fdir->input.flow.ipv6_flow.dst_ip, 16);
2204 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2205 memset(filter->dst_ipaddr_mask, 0xff, 16);
2206 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2207 memset(filter->src_ipaddr_mask, 0xff, 16);
2208 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2209 filter->ethertype = 0x86dd;
2210 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2212 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2213 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2214 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2215 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2216 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2217 filter->dst_port_mask = 0xffff;
2218 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2219 filter->src_port_mask = 0xffff;
2220 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2221 filter->ip_addr_type =
2222 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2223 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2224 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2225 rte_memcpy(filter->src_ipaddr,
2226 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2227 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2228 rte_memcpy(filter->dst_ipaddr,
2229 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2230 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2231 memset(filter->dst_ipaddr_mask, 0xff, 16);
2232 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2233 memset(filter->src_ipaddr_mask, 0xff, 16);
2234 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2235 filter->ethertype = 0x86dd;
2236 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2238 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2239 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2240 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2241 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2242 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2243 filter->dst_port_mask = 0xffff;
2244 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2245 filter->src_port_mask = 0xffff;
2246 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2247 filter->ip_addr_type =
2248 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2249 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2250 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2251 rte_memcpy(filter->src_ipaddr,
2252 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2253 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2254 rte_memcpy(filter->dst_ipaddr,
2255 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2256 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2257 memset(filter->dst_ipaddr_mask, 0xff, 16);
2258 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2259 memset(filter->src_ipaddr_mask, 0xff, 16);
2260 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2261 filter->ethertype = 0x86dd;
2262 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2264 case RTE_ETH_FLOW_L2_PAYLOAD:
2265 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2266 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2268 case RTE_ETH_FLOW_VXLAN:
2269 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2271 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2272 filter->tunnel_type =
2273 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2274 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2276 case RTE_ETH_FLOW_NVGRE:
2277 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2279 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2280 filter->tunnel_type =
2281 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2282 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2284 case RTE_ETH_FLOW_UNKNOWN:
2285 case RTE_ETH_FLOW_RAW:
2286 case RTE_ETH_FLOW_FRAG_IPV4:
2287 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2288 case RTE_ETH_FLOW_FRAG_IPV6:
2289 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2290 case RTE_ETH_FLOW_IPV6_EX:
2291 case RTE_ETH_FLOW_IPV6_TCP_EX:
2292 case RTE_ETH_FLOW_IPV6_UDP_EX:
2293 case RTE_ETH_FLOW_GENEVE:
2299 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
2300 vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]);
2302 RTE_LOG(ERR, PMD, "Invalid queue %d\n", fdir->action.rx_queue);
2307 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2308 rte_memcpy(filter->dst_macaddr,
2309 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2310 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2313 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2314 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2315 filter1 = STAILQ_FIRST(&vnic0->filter);
2316 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2318 filter->dst_id = vnic->fw_vnic_id;
2319 for (i = 0; i < ETHER_ADDR_LEN; i++)
2320 if (filter->dst_macaddr[i] == 0x00)
2321 filter1 = STAILQ_FIRST(&vnic0->filter);
2323 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2326 if (filter1 == NULL)
2329 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2330 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2332 filter->enables = en;
2337 static struct bnxt_filter_info *
2338 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf)
2340 struct bnxt_filter_info *mf = NULL;
2343 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2344 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2346 STAILQ_FOREACH(mf, &vnic->filter, next) {
2347 if (mf->filter_type == nf->filter_type &&
2348 mf->flags == nf->flags &&
2349 mf->src_port == nf->src_port &&
2350 mf->src_port_mask == nf->src_port_mask &&
2351 mf->dst_port == nf->dst_port &&
2352 mf->dst_port_mask == nf->dst_port_mask &&
2353 mf->ip_protocol == nf->ip_protocol &&
2354 mf->ip_addr_type == nf->ip_addr_type &&
2355 mf->ethertype == nf->ethertype &&
2356 mf->vni == nf->vni &&
2357 mf->tunnel_type == nf->tunnel_type &&
2358 mf->l2_ovlan == nf->l2_ovlan &&
2359 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2360 mf->l2_ivlan == nf->l2_ivlan &&
2361 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2362 !memcmp(mf->l2_addr, nf->l2_addr, ETHER_ADDR_LEN) &&
2363 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2365 !memcmp(mf->src_macaddr, nf->src_macaddr,
2367 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2369 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2370 sizeof(nf->src_ipaddr)) &&
2371 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2372 sizeof(nf->src_ipaddr_mask)) &&
2373 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2374 sizeof(nf->dst_ipaddr)) &&
2375 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2376 sizeof(nf->dst_ipaddr_mask)))
2384 bnxt_fdir_filter(struct rte_eth_dev *dev,
2385 enum rte_filter_op filter_op,
2388 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2389 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
2390 struct bnxt_filter_info *filter, *match;
2391 struct bnxt_vnic_info *vnic;
2394 if (filter_op == RTE_ETH_FILTER_NOP)
2397 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2400 switch (filter_op) {
2401 case RTE_ETH_FILTER_ADD:
2402 case RTE_ETH_FILTER_DELETE:
2404 filter = bnxt_get_unused_filter(bp);
2405 if (filter == NULL) {
2407 "Not enough resources for a new flow.\n");
2411 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2414 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2416 match = bnxt_match_fdir(bp, filter);
2417 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2418 RTE_LOG(ERR, PMD, "Flow already exists.\n");
2422 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2423 RTE_LOG(ERR, PMD, "Flow does not exist.\n");
2428 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2429 vnic = STAILQ_FIRST(&bp->ff_pool[0]);
2432 STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]);
2434 if (filter_op == RTE_ETH_FILTER_ADD) {
2435 ret = bnxt_hwrm_set_ntuple_filter(bp,
2440 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2442 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2443 STAILQ_REMOVE(&vnic->filter, match,
2444 bnxt_filter_info, next);
2445 bnxt_free_filter(bp, match);
2446 filter->fw_l2_filter_id = -1;
2447 bnxt_free_filter(bp, filter);
2450 case RTE_ETH_FILTER_FLUSH:
2451 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2452 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2454 STAILQ_FOREACH(filter, &vnic->filter, next) {
2455 if (filter->filter_type ==
2456 HWRM_CFA_NTUPLE_FILTER) {
2458 bnxt_hwrm_clear_ntuple_filter(bp,
2460 STAILQ_REMOVE(&vnic->filter, filter,
2461 bnxt_filter_info, next);
2466 case RTE_ETH_FILTER_UPDATE:
2467 case RTE_ETH_FILTER_STATS:
2468 case RTE_ETH_FILTER_INFO:
2470 RTE_LOG(ERR, PMD, "operation %u not implemented", filter_op);
2473 RTE_LOG(ERR, PMD, "unknown operation %u", filter_op);
2480 filter->fw_l2_filter_id = -1;
2481 bnxt_free_filter(bp, filter);
2486 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2487 enum rte_filter_type filter_type,
2488 enum rte_filter_op filter_op, void *arg)
2492 switch (filter_type) {
2493 case RTE_ETH_FILTER_TUNNEL:
2495 "filter type: %d: To be implemented\n", filter_type);
2497 case RTE_ETH_FILTER_FDIR:
2498 ret = bnxt_fdir_filter(dev, filter_op, arg);
2500 case RTE_ETH_FILTER_NTUPLE:
2501 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2503 case RTE_ETH_FILTER_ETHERTYPE:
2504 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2506 case RTE_ETH_FILTER_GENERIC:
2507 if (filter_op != RTE_ETH_FILTER_GET)
2509 *(const void **)arg = &bnxt_flow_ops;
2513 "Filter type (%d) not supported", filter_type);
2520 static const uint32_t *
2521 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2523 static const uint32_t ptypes[] = {
2524 RTE_PTYPE_L2_ETHER_VLAN,
2525 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2526 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2530 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2531 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2532 RTE_PTYPE_INNER_L4_ICMP,
2533 RTE_PTYPE_INNER_L4_TCP,
2534 RTE_PTYPE_INNER_L4_UDP,
2538 if (dev->rx_pkt_burst == bnxt_recv_pkts)
2546 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
2548 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2550 uint32_t dir_entries;
2551 uint32_t entry_length;
2553 RTE_LOG(INFO, PMD, "%s(): %04x:%02x:%02x:%02x\n",
2554 __func__, bp->pdev->addr.domain, bp->pdev->addr.bus,
2555 bp->pdev->addr.devid, bp->pdev->addr.function);
2557 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
2561 return dir_entries * entry_length;
2565 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
2566 struct rte_dev_eeprom_info *in_eeprom)
2568 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2572 RTE_LOG(INFO, PMD, "%s(): %04x:%02x:%02x:%02x in_eeprom->offset = %d "
2573 "len = %d\n", __func__, bp->pdev->addr.domain,
2574 bp->pdev->addr.bus, bp->pdev->addr.devid,
2575 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2577 if (in_eeprom->offset == 0) /* special offset value to get directory */
2578 return bnxt_get_nvram_directory(bp, in_eeprom->length,
2581 index = in_eeprom->offset >> 24;
2582 offset = in_eeprom->offset & 0xffffff;
2585 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
2586 in_eeprom->length, in_eeprom->data);
2591 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
2594 case BNX_DIR_TYPE_CHIMP_PATCH:
2595 case BNX_DIR_TYPE_BOOTCODE:
2596 case BNX_DIR_TYPE_BOOTCODE_2:
2597 case BNX_DIR_TYPE_APE_FW:
2598 case BNX_DIR_TYPE_APE_PATCH:
2599 case BNX_DIR_TYPE_KONG_FW:
2600 case BNX_DIR_TYPE_KONG_PATCH:
2601 case BNX_DIR_TYPE_BONO_FW:
2602 case BNX_DIR_TYPE_BONO_PATCH:
2609 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
2612 case BNX_DIR_TYPE_AVS:
2613 case BNX_DIR_TYPE_EXP_ROM_MBA:
2614 case BNX_DIR_TYPE_PCIE:
2615 case BNX_DIR_TYPE_TSCF_UCODE:
2616 case BNX_DIR_TYPE_EXT_PHY:
2617 case BNX_DIR_TYPE_CCM:
2618 case BNX_DIR_TYPE_ISCSI_BOOT:
2619 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
2620 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
2627 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
2629 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
2630 bnxt_dir_type_is_other_exec_format(dir_type);
2634 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
2635 struct rte_dev_eeprom_info *in_eeprom)
2637 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2638 uint8_t index, dir_op;
2639 uint16_t type, ext, ordinal, attr;
2641 RTE_LOG(INFO, PMD, "%s(): %04x:%02x:%02x:%02x in_eeprom->offset = %d "
2642 "len = %d\n", __func__, bp->pdev->addr.domain,
2643 bp->pdev->addr.bus, bp->pdev->addr.devid,
2644 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2647 RTE_LOG(ERR, PMD, "NVM write not supported from a VF\n");
2651 type = in_eeprom->magic >> 16;
2653 if (type == 0xffff) { /* special value for directory operations */
2654 index = in_eeprom->magic & 0xff;
2655 dir_op = in_eeprom->magic >> 8;
2659 case 0x0e: /* erase */
2660 if (in_eeprom->offset != ~in_eeprom->magic)
2662 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
2668 /* Create or re-write an NVM item: */
2669 if (bnxt_dir_type_is_executable(type) == true)
2671 ext = in_eeprom->magic & 0xffff;
2672 ordinal = in_eeprom->offset >> 16;
2673 attr = in_eeprom->offset & 0xffff;
2675 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
2676 in_eeprom->data, in_eeprom->length);
2684 static const struct eth_dev_ops bnxt_dev_ops = {
2685 .dev_infos_get = bnxt_dev_info_get_op,
2686 .dev_close = bnxt_dev_close_op,
2687 .dev_configure = bnxt_dev_configure_op,
2688 .dev_start = bnxt_dev_start_op,
2689 .dev_stop = bnxt_dev_stop_op,
2690 .dev_set_link_up = bnxt_dev_set_link_up_op,
2691 .dev_set_link_down = bnxt_dev_set_link_down_op,
2692 .stats_get = bnxt_stats_get_op,
2693 .stats_reset = bnxt_stats_reset_op,
2694 .rx_queue_setup = bnxt_rx_queue_setup_op,
2695 .rx_queue_release = bnxt_rx_queue_release_op,
2696 .tx_queue_setup = bnxt_tx_queue_setup_op,
2697 .tx_queue_release = bnxt_tx_queue_release_op,
2698 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
2699 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
2700 .reta_update = bnxt_reta_update_op,
2701 .reta_query = bnxt_reta_query_op,
2702 .rss_hash_update = bnxt_rss_hash_update_op,
2703 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
2704 .link_update = bnxt_link_update_op,
2705 .promiscuous_enable = bnxt_promiscuous_enable_op,
2706 .promiscuous_disable = bnxt_promiscuous_disable_op,
2707 .allmulticast_enable = bnxt_allmulticast_enable_op,
2708 .allmulticast_disable = bnxt_allmulticast_disable_op,
2709 .mac_addr_add = bnxt_mac_addr_add_op,
2710 .mac_addr_remove = bnxt_mac_addr_remove_op,
2711 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
2712 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
2713 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
2714 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
2715 .vlan_filter_set = bnxt_vlan_filter_set_op,
2716 .vlan_offload_set = bnxt_vlan_offload_set_op,
2717 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
2718 .mtu_set = bnxt_mtu_set_op,
2719 .mac_addr_set = bnxt_set_default_mac_addr_op,
2720 .xstats_get = bnxt_dev_xstats_get_op,
2721 .xstats_get_names = bnxt_dev_xstats_get_names_op,
2722 .xstats_reset = bnxt_dev_xstats_reset_op,
2723 .fw_version_get = bnxt_fw_version_get,
2724 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
2725 .rxq_info_get = bnxt_rxq_info_get_op,
2726 .txq_info_get = bnxt_txq_info_get_op,
2727 .dev_led_on = bnxt_dev_led_on_op,
2728 .dev_led_off = bnxt_dev_led_off_op,
2729 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
2730 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
2731 .rx_queue_count = bnxt_rx_queue_count_op,
2732 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
2733 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
2734 .filter_ctrl = bnxt_filter_ctrl_op,
2735 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
2736 .get_eeprom_length = bnxt_get_eeprom_length_op,
2737 .get_eeprom = bnxt_get_eeprom_op,
2738 .set_eeprom = bnxt_set_eeprom_op,
2741 static bool bnxt_vf_pciid(uint16_t id)
2743 if (id == BROADCOM_DEV_ID_57304_VF ||
2744 id == BROADCOM_DEV_ID_57406_VF ||
2745 id == BROADCOM_DEV_ID_5731X_VF ||
2746 id == BROADCOM_DEV_ID_5741X_VF ||
2747 id == BROADCOM_DEV_ID_57414_VF ||
2748 id == BROADCOM_DEV_ID_STRATUS_NIC_VF)
2753 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
2755 struct bnxt *bp = eth_dev->data->dev_private;
2756 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2759 /* enable device (incl. PCI PM wakeup), and bus-mastering */
2760 if (!pci_dev->mem_resource[0].addr) {
2762 "Cannot find PCI device base address, aborting\n");
2764 goto init_err_disable;
2767 bp->eth_dev = eth_dev;
2770 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
2772 RTE_LOG(ERR, PMD, "Cannot map device registers, aborting\n");
2774 goto init_err_release;
2787 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
2789 #define ALLOW_FUNC(x) \
2791 typeof(x) arg = (x); \
2792 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
2793 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
2796 bnxt_dev_init(struct rte_eth_dev *eth_dev)
2798 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2799 char mz_name[RTE_MEMZONE_NAMESIZE];
2800 const struct rte_memzone *mz = NULL;
2801 static int version_printed;
2802 uint32_t total_alloc_len;
2803 rte_iova_t mz_phys_addr;
2807 if (version_printed++ == 0)
2808 RTE_LOG(INFO, PMD, "%s\n", bnxt_version);
2810 rte_eth_copy_pci_info(eth_dev, pci_dev);
2812 bp = eth_dev->data->dev_private;
2814 rte_atomic64_init(&bp->rx_mbuf_alloc_fail);
2815 bp->dev_stopped = 1;
2817 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2820 if (bnxt_vf_pciid(pci_dev->id.device_id))
2821 bp->flags |= BNXT_FLAG_VF;
2823 rc = bnxt_init_board(eth_dev);
2826 "Board initialization failed rc: %x\n", rc);
2830 eth_dev->dev_ops = &bnxt_dev_ops;
2831 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2833 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
2834 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
2836 if (BNXT_PF(bp) && pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) {
2837 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
2838 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
2839 pci_dev->addr.bus, pci_dev->addr.devid,
2840 pci_dev->addr.function, "rx_port_stats");
2841 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
2842 mz = rte_memzone_lookup(mz_name);
2843 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
2844 sizeof(struct rx_port_stats) + 512);
2846 mz = rte_memzone_reserve(mz_name, total_alloc_len,
2849 RTE_MEMZONE_SIZE_HINT_ONLY);
2853 memset(mz->addr, 0, mz->len);
2854 mz_phys_addr = mz->iova;
2855 if ((unsigned long)mz->addr == mz_phys_addr) {
2856 RTE_LOG(WARNING, PMD,
2857 "Memzone physical address same as virtual.\n");
2858 RTE_LOG(WARNING, PMD,
2859 "Using rte_mem_virt2iova()\n");
2860 mz_phys_addr = rte_mem_virt2iova(mz->addr);
2861 if (mz_phys_addr == 0) {
2863 "unable to map address to physical memory\n");
2868 bp->rx_mem_zone = (const void *)mz;
2869 bp->hw_rx_port_stats = mz->addr;
2870 bp->hw_rx_port_stats_map = mz_phys_addr;
2872 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
2873 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
2874 pci_dev->addr.bus, pci_dev->addr.devid,
2875 pci_dev->addr.function, "tx_port_stats");
2876 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
2877 mz = rte_memzone_lookup(mz_name);
2878 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
2879 sizeof(struct tx_port_stats) + 512);
2881 mz = rte_memzone_reserve(mz_name, total_alloc_len,
2884 RTE_MEMZONE_SIZE_HINT_ONLY);
2888 memset(mz->addr, 0, mz->len);
2889 mz_phys_addr = mz->iova;
2890 if ((unsigned long)mz->addr == mz_phys_addr) {
2891 RTE_LOG(WARNING, PMD,
2892 "Memzone physical address same as virtual.\n");
2893 RTE_LOG(WARNING, PMD,
2894 "Using rte_mem_virt2iova()\n");
2895 mz_phys_addr = rte_mem_virt2iova(mz->addr);
2896 if (mz_phys_addr == 0) {
2898 "unable to map address to physical memory\n");
2903 bp->tx_mem_zone = (const void *)mz;
2904 bp->hw_tx_port_stats = mz->addr;
2905 bp->hw_tx_port_stats_map = mz_phys_addr;
2907 bp->flags |= BNXT_FLAG_PORT_STATS;
2910 rc = bnxt_alloc_hwrm_resources(bp);
2913 "hwrm resource allocation failure rc: %x\n", rc);
2916 rc = bnxt_hwrm_ver_get(bp);
2919 bnxt_hwrm_queue_qportcfg(bp);
2921 bnxt_hwrm_func_qcfg(bp);
2923 /* Get the MAX capabilities for this function */
2924 rc = bnxt_hwrm_func_qcaps(bp);
2926 RTE_LOG(ERR, PMD, "hwrm query capability failure rc: %x\n", rc);
2929 if (bp->max_tx_rings == 0) {
2930 RTE_LOG(ERR, PMD, "No TX rings available!\n");
2934 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
2935 ETHER_ADDR_LEN * bp->max_l2_ctx, 0);
2936 if (eth_dev->data->mac_addrs == NULL) {
2938 "Failed to alloc %u bytes needed to store MAC addr tbl",
2939 ETHER_ADDR_LEN * bp->max_l2_ctx);
2943 /* Copy the permanent MAC from the qcap response address now. */
2944 memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr));
2945 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
2946 bp->grp_info = rte_zmalloc("bnxt_grp_info",
2947 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
2948 if (!bp->grp_info) {
2950 "Failed to alloc %zu bytes needed to store group info table\n",
2951 sizeof(*bp->grp_info) * bp->max_ring_grps);
2956 /* Forward all requests if firmware is new enough */
2957 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
2958 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
2959 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
2960 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
2962 RTE_LOG(WARNING, PMD,
2963 "Firmware too old for VF mailbox functionality\n");
2964 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
2968 * The following are used for driver cleanup. If we disallow these,
2969 * VF drivers can't clean up cleanly.
2971 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
2972 ALLOW_FUNC(HWRM_VNIC_FREE);
2973 ALLOW_FUNC(HWRM_RING_FREE);
2974 ALLOW_FUNC(HWRM_RING_GRP_FREE);
2975 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
2976 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
2977 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
2978 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
2979 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
2980 rc = bnxt_hwrm_func_driver_register(bp);
2983 "Failed to register driver");
2989 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
2990 pci_dev->mem_resource[0].phys_addr,
2991 pci_dev->mem_resource[0].addr);
2993 rc = bnxt_hwrm_func_reset(bp);
2995 RTE_LOG(ERR, PMD, "hwrm chip reset failure rc: %x\n", rc);
3001 //if (bp->pf.active_vfs) {
3002 // TODO: Deallocate VF resources?
3004 if (bp->pdev->max_vfs) {
3005 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
3007 RTE_LOG(ERR, PMD, "Failed to allocate VFs\n");
3011 rc = bnxt_hwrm_allocate_pf_only(bp);
3014 "Failed to allocate PF resources\n");
3020 bnxt_hwrm_port_led_qcaps(bp);
3022 rc = bnxt_setup_int(bp);
3026 rc = bnxt_alloc_mem(bp);
3028 goto error_free_int;
3030 rc = bnxt_request_int(bp);
3032 goto error_free_int;
3034 rc = bnxt_alloc_def_cp_ring(bp);
3036 goto error_free_int;
3038 bnxt_enable_int(bp);
3043 bnxt_disable_int(bp);
3044 bnxt_free_def_cp_ring(bp);
3045 bnxt_hwrm_func_buf_unrgtr(bp);
3049 bnxt_dev_uninit(eth_dev);
3055 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) {
3056 struct bnxt *bp = eth_dev->data->dev_private;
3059 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3062 bnxt_disable_int(bp);
3065 if (eth_dev->data->mac_addrs != NULL) {
3066 rte_free(eth_dev->data->mac_addrs);
3067 eth_dev->data->mac_addrs = NULL;
3069 if (bp->grp_info != NULL) {
3070 rte_free(bp->grp_info);
3071 bp->grp_info = NULL;
3073 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
3074 bnxt_free_hwrm_resources(bp);
3075 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
3076 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
3077 if (bp->dev_stopped == 0)
3078 bnxt_dev_close_op(eth_dev);
3080 rte_free(bp->pf.vf_info);
3081 eth_dev->dev_ops = NULL;
3082 eth_dev->rx_pkt_burst = NULL;
3083 eth_dev->tx_pkt_burst = NULL;
3088 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3089 struct rte_pci_device *pci_dev)
3091 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
3095 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
3097 return rte_eth_dev_pci_generic_remove(pci_dev, bnxt_dev_uninit);
3100 static struct rte_pci_driver bnxt_rte_pmd = {
3101 .id_table = bnxt_pci_id_map,
3102 .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
3103 RTE_PCI_DRV_INTR_LSC,
3104 .probe = bnxt_pci_probe,
3105 .remove = bnxt_pci_remove,
3109 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
3111 if (strcmp(dev->device->driver->name, drv->driver.name))
3117 bool is_bnxt_supported(struct rte_eth_dev *dev)
3119 return is_device_supported(dev, &bnxt_rte_pmd);
3122 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
3123 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
3124 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");