1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
20 #include "bnxt_ring.h"
23 #include "bnxt_stats.h"
26 #include "bnxt_vnic.h"
27 #include "hsi_struct_def_dpdk.h"
28 #include "bnxt_nvm_defs.h"
30 #define DRV_MODULE_NAME "bnxt"
31 static const char bnxt_version[] =
32 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
33 int bnxt_logtype_driver;
36 * The set of PCI devices this driver supports
38 static const struct rte_pci_id bnxt_pci_id_map[] = {
39 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
40 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
41 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
42 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
43 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
45 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
47 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
92 { .vendor_id = 0, /* sentinel */ },
95 #define BNXT_ETH_RSS_SUPPORT ( \
97 ETH_RSS_NONFRAG_IPV4_TCP | \
98 ETH_RSS_NONFRAG_IPV4_UDP | \
100 ETH_RSS_NONFRAG_IPV6_TCP | \
101 ETH_RSS_NONFRAG_IPV6_UDP)
103 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
104 DEV_TX_OFFLOAD_IPV4_CKSUM | \
105 DEV_TX_OFFLOAD_TCP_CKSUM | \
106 DEV_TX_OFFLOAD_UDP_CKSUM | \
107 DEV_TX_OFFLOAD_TCP_TSO | \
108 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
109 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
110 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
111 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
112 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
113 DEV_TX_OFFLOAD_QINQ_INSERT | \
114 DEV_TX_OFFLOAD_MULTI_SEGS)
116 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
117 DEV_RX_OFFLOAD_VLAN_STRIP | \
118 DEV_RX_OFFLOAD_IPV4_CKSUM | \
119 DEV_RX_OFFLOAD_UDP_CKSUM | \
120 DEV_RX_OFFLOAD_TCP_CKSUM | \
121 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
122 DEV_RX_OFFLOAD_JUMBO_FRAME | \
123 DEV_RX_OFFLOAD_KEEP_CRC | \
124 DEV_RX_OFFLOAD_VLAN_EXTEND | \
125 DEV_RX_OFFLOAD_TCP_LRO | \
126 DEV_RX_OFFLOAD_SCATTER | \
127 DEV_RX_OFFLOAD_RSS_HASH)
129 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
130 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
131 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
132 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
133 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
134 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
136 int is_bnxt_in_error(struct bnxt *bp)
138 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
140 if (bp->flags & BNXT_FLAG_FW_RESET)
146 /***********************/
149 * High level utility functions
152 uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
154 if (!BNXT_CHIP_THOR(bp))
157 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
158 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
159 BNXT_RSS_ENTRIES_PER_CTX_THOR;
162 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
164 if (!BNXT_CHIP_THOR(bp))
165 return HW_HASH_INDEX_SIZE;
167 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
170 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
172 bnxt_free_filter_mem(bp);
173 bnxt_free_vnic_attributes(bp);
174 bnxt_free_vnic_mem(bp);
176 /* tx/rx rings are configured as part of *_queue_setup callbacks.
177 * If the number of rings change across fw update,
178 * we don't have much choice except to warn the user.
182 bnxt_free_tx_rings(bp);
183 bnxt_free_rx_rings(bp);
185 bnxt_free_async_cp_ring(bp);
186 bnxt_free_rxtx_nq_ring(bp);
188 rte_free(bp->grp_info);
192 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
196 rc = bnxt_alloc_ring_grps(bp);
200 rc = bnxt_alloc_async_ring_struct(bp);
204 rc = bnxt_alloc_vnic_mem(bp);
208 rc = bnxt_alloc_vnic_attributes(bp);
212 rc = bnxt_alloc_filter_mem(bp);
216 rc = bnxt_alloc_async_cp_ring(bp);
220 rc = bnxt_alloc_rxtx_nq_ring(bp);
227 bnxt_free_mem(bp, reconfig);
231 static int bnxt_init_chip(struct bnxt *bp)
233 struct bnxt_rx_queue *rxq;
234 struct rte_eth_link new;
235 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
236 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
237 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
238 uint64_t rx_offloads = dev_conf->rxmode.offloads;
239 uint32_t intr_vector = 0;
240 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
241 uint32_t vec = BNXT_MISC_VEC_ID;
245 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
246 bp->eth_dev->data->dev_conf.rxmode.offloads |=
247 DEV_RX_OFFLOAD_JUMBO_FRAME;
248 bp->flags |= BNXT_FLAG_JUMBO;
250 bp->eth_dev->data->dev_conf.rxmode.offloads &=
251 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
252 bp->flags &= ~BNXT_FLAG_JUMBO;
255 /* THOR does not support ring groups.
256 * But we will use the array to save RSS context IDs.
258 if (BNXT_CHIP_THOR(bp))
259 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
261 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
263 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
267 rc = bnxt_alloc_hwrm_rings(bp);
269 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
273 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
275 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
279 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
282 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
283 if (bp->rx_cos_queue[i].id != 0xff) {
284 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
288 "Num pools more than FW profile\n");
292 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
298 rc = bnxt_mq_rx_configure(bp);
300 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
304 /* VNIC configuration */
305 for (i = 0; i < bp->nr_vnics; i++) {
306 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
307 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
309 rc = bnxt_vnic_grp_alloc(bp, vnic);
313 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
314 i, vnic, vnic->fw_grp_ids);
316 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
318 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
323 /* Alloc RSS context only if RSS mode is enabled */
324 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
325 int j, nr_ctxs = bnxt_rss_ctxts(bp);
328 for (j = 0; j < nr_ctxs; j++) {
329 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
335 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
339 vnic->num_lb_ctxts = nr_ctxs;
343 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
344 * setting is not available at this time, it will not be
345 * configured correctly in the CFA.
347 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
348 vnic->vlan_strip = true;
350 vnic->vlan_strip = false;
352 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
354 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
359 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
362 "HWRM vnic %d filter failure rc: %x\n",
367 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
368 rxq = bp->eth_dev->data->rx_queues[j];
371 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
372 j, rxq->vnic, rxq->vnic->fw_grp_ids);
374 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
375 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
378 rc = bnxt_vnic_rss_configure(bp, vnic);
381 "HWRM vnic set RSS failure rc: %x\n", rc);
385 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
387 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
388 DEV_RX_OFFLOAD_TCP_LRO)
389 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
391 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
393 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
396 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
400 /* check and configure queue intr-vector mapping */
401 if ((rte_intr_cap_multiple(intr_handle) ||
402 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
403 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
404 intr_vector = bp->eth_dev->data->nb_rx_queues;
405 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
406 if (intr_vector > bp->rx_cp_nr_rings) {
407 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
411 rc = rte_intr_efd_enable(intr_handle, intr_vector);
416 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
417 intr_handle->intr_vec =
418 rte_zmalloc("intr_vec",
419 bp->eth_dev->data->nb_rx_queues *
421 if (intr_handle->intr_vec == NULL) {
422 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
423 " intr_vec", bp->eth_dev->data->nb_rx_queues);
427 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
428 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
429 intr_handle->intr_vec, intr_handle->nb_efd,
430 intr_handle->max_intr);
431 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
433 intr_handle->intr_vec[queue_id] =
434 vec + BNXT_RX_VEC_START;
435 if (vec < base + intr_handle->nb_efd - 1)
440 /* enable uio/vfio intr/eventfd mapping */
441 rc = rte_intr_enable(intr_handle);
445 rc = bnxt_get_hwrm_link_config(bp, &new);
447 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
451 if (!bp->link_info.link_up) {
452 rc = bnxt_set_hwrm_link_config(bp, true);
455 "HWRM link config failure rc: %x\n", rc);
459 bnxt_print_link_info(bp->eth_dev);
464 rte_free(intr_handle->intr_vec);
466 rte_intr_efd_disable(intr_handle);
468 /* Some of the error status returned by FW may not be from errno.h */
475 static int bnxt_shutdown_nic(struct bnxt *bp)
477 bnxt_free_all_hwrm_resources(bp);
478 bnxt_free_all_filters(bp);
479 bnxt_free_all_vnics(bp);
484 * Device configuration and status function
487 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
488 struct rte_eth_dev_info *dev_info)
490 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
491 struct bnxt *bp = eth_dev->data->dev_private;
492 uint16_t max_vnics, i, j, vpool, vrxq;
493 unsigned int max_rx_rings;
496 rc = is_bnxt_in_error(bp);
501 dev_info->max_mac_addrs = bp->max_l2_ctx;
502 dev_info->max_hash_mac_addrs = 0;
504 /* PF/VF specifics */
506 dev_info->max_vfs = pdev->max_vfs;
508 max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
509 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
510 dev_info->max_rx_queues = max_rx_rings;
511 dev_info->max_tx_queues = max_rx_rings;
512 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
513 dev_info->hash_key_size = 40;
514 max_vnics = bp->max_vnics;
517 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
518 dev_info->max_mtu = BNXT_MAX_MTU;
520 /* Fast path specifics */
521 dev_info->min_rx_bufsize = 1;
522 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
524 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
525 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
526 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
527 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
528 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
531 dev_info->default_rxconf = (struct rte_eth_rxconf) {
537 .rx_free_thresh = 32,
538 /* If no descriptors available, pkts are dropped by default */
542 dev_info->default_txconf = (struct rte_eth_txconf) {
548 .tx_free_thresh = 32,
551 eth_dev->data->dev_conf.intr_conf.lsc = 1;
553 eth_dev->data->dev_conf.intr_conf.rxq = 1;
554 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
555 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
556 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
557 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
562 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
563 * need further investigation.
567 vpool = 64; /* ETH_64_POOLS */
568 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
569 for (i = 0; i < 4; vpool >>= 1, i++) {
570 if (max_vnics > vpool) {
571 for (j = 0; j < 5; vrxq >>= 1, j++) {
572 if (dev_info->max_rx_queues > vrxq) {
578 /* Not enough resources to support VMDq */
582 /* Not enough resources to support VMDq */
586 dev_info->max_vmdq_pools = vpool;
587 dev_info->vmdq_queue_num = vrxq;
589 dev_info->vmdq_pool_base = 0;
590 dev_info->vmdq_queue_base = 0;
595 /* Configure the device based on the configuration provided */
596 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
598 struct bnxt *bp = eth_dev->data->dev_private;
599 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
602 bp->rx_queues = (void *)eth_dev->data->rx_queues;
603 bp->tx_queues = (void *)eth_dev->data->tx_queues;
604 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
605 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
607 rc = is_bnxt_in_error(bp);
611 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
612 rc = bnxt_hwrm_check_vf_rings(bp);
614 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
618 /* If a resource has already been allocated - in this case
619 * it is the async completion ring, free it. Reallocate it after
620 * resource reservation. This will ensure the resource counts
621 * are calculated correctly.
624 pthread_mutex_lock(&bp->def_cp_lock);
626 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
627 bnxt_disable_int(bp);
628 bnxt_free_cp_ring(bp, bp->async_cp_ring);
631 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
633 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
634 pthread_mutex_unlock(&bp->def_cp_lock);
638 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
639 rc = bnxt_alloc_async_cp_ring(bp);
641 pthread_mutex_unlock(&bp->def_cp_lock);
647 pthread_mutex_unlock(&bp->def_cp_lock);
649 /* legacy driver needs to get updated values */
650 rc = bnxt_hwrm_func_qcaps(bp);
652 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
657 /* Inherit new configurations */
658 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
659 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
660 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
661 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
662 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
666 if (BNXT_HAS_RING_GRPS(bp) &&
667 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
670 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
671 bp->max_vnics < eth_dev->data->nb_rx_queues)
674 bp->rx_cp_nr_rings = bp->rx_nr_rings;
675 bp->tx_cp_nr_rings = bp->tx_nr_rings;
677 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
678 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
680 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
682 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
683 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
685 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
691 "Insufficient resources to support requested config\n");
693 "Num Queues Requested: Tx %d, Rx %d\n",
694 eth_dev->data->nb_tx_queues,
695 eth_dev->data->nb_rx_queues);
697 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
698 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
699 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
703 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
705 struct rte_eth_link *link = ð_dev->data->dev_link;
707 if (link->link_status)
708 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
709 eth_dev->data->port_id,
710 (uint32_t)link->link_speed,
711 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
712 ("full-duplex") : ("half-duplex\n"));
714 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
715 eth_dev->data->port_id);
719 * Determine whether the current configuration requires support for scattered
720 * receive; return 1 if scattered receive is required and 0 if not.
722 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
727 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
730 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
731 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
733 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
734 RTE_PKTMBUF_HEADROOM);
735 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
741 static eth_rx_burst_t
742 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
745 #ifndef RTE_LIBRTE_IEEE1588
747 * Vector mode receive can be enabled only if scatter rx is not
748 * in use and rx offloads are limited to VLAN stripping and
751 if (!eth_dev->data->scattered_rx &&
752 !(eth_dev->data->dev_conf.rxmode.offloads &
753 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
754 DEV_RX_OFFLOAD_KEEP_CRC |
755 DEV_RX_OFFLOAD_JUMBO_FRAME |
756 DEV_RX_OFFLOAD_IPV4_CKSUM |
757 DEV_RX_OFFLOAD_UDP_CKSUM |
758 DEV_RX_OFFLOAD_TCP_CKSUM |
759 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
760 DEV_RX_OFFLOAD_VLAN_FILTER))) {
761 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
762 eth_dev->data->port_id);
763 return bnxt_recv_pkts_vec;
765 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
766 eth_dev->data->port_id);
768 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
769 eth_dev->data->port_id,
770 eth_dev->data->scattered_rx,
771 eth_dev->data->dev_conf.rxmode.offloads);
774 return bnxt_recv_pkts;
777 static eth_tx_burst_t
778 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
781 #ifndef RTE_LIBRTE_IEEE1588
783 * Vector mode transmit can be enabled only if not using scatter rx
786 if (!eth_dev->data->scattered_rx &&
787 !eth_dev->data->dev_conf.txmode.offloads) {
788 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
789 eth_dev->data->port_id);
790 return bnxt_xmit_pkts_vec;
792 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
793 eth_dev->data->port_id);
795 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
796 eth_dev->data->port_id,
797 eth_dev->data->scattered_rx,
798 eth_dev->data->dev_conf.txmode.offloads);
801 return bnxt_xmit_pkts;
804 static int bnxt_handle_if_change_status(struct bnxt *bp)
808 /* Since fw has undergone a reset and lost all contexts,
809 * set fatal flag to not issue hwrm during cleanup
811 bp->flags |= BNXT_FLAG_FATAL_ERROR;
812 bnxt_uninit_resources(bp, true);
814 /* clear fatal flag so that re-init happens */
815 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
816 rc = bnxt_init_resources(bp, true);
818 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
823 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
825 struct bnxt *bp = eth_dev->data->dev_private;
826 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
830 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
831 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
835 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
837 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
838 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
841 rc = bnxt_hwrm_if_change(bp, 1);
843 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
844 rc = bnxt_handle_if_change_status(bp);
851 rc = bnxt_init_chip(bp);
855 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
857 bnxt_link_update_op(eth_dev, 1);
859 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
860 vlan_mask |= ETH_VLAN_FILTER_MASK;
861 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
862 vlan_mask |= ETH_VLAN_STRIP_MASK;
863 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
867 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
868 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
870 bp->flags |= BNXT_FLAG_INIT_DONE;
871 eth_dev->data->dev_started = 1;
873 pthread_mutex_lock(&bp->def_cp_lock);
874 bnxt_schedule_fw_health_check(bp);
875 pthread_mutex_unlock(&bp->def_cp_lock);
879 bnxt_hwrm_if_change(bp, 0);
880 bnxt_shutdown_nic(bp);
881 bnxt_free_tx_mbufs(bp);
882 bnxt_free_rx_mbufs(bp);
886 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
888 struct bnxt *bp = eth_dev->data->dev_private;
891 if (!bp->link_info.link_up)
892 rc = bnxt_set_hwrm_link_config(bp, true);
894 eth_dev->data->dev_link.link_status = 1;
896 bnxt_print_link_info(eth_dev);
900 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
902 struct bnxt *bp = eth_dev->data->dev_private;
904 eth_dev->data->dev_link.link_status = 0;
905 bnxt_set_hwrm_link_config(bp, false);
906 bp->link_info.link_up = 0;
911 /* Unload the driver, release resources */
912 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
914 struct bnxt *bp = eth_dev->data->dev_private;
915 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
916 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
918 eth_dev->data->dev_started = 0;
919 /* Prevent crashes when queues are still in use */
920 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
921 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
923 bnxt_disable_int(bp);
925 /* disable uio/vfio intr/eventfd mapping */
926 rte_intr_disable(intr_handle);
928 bnxt_cancel_fw_health_check(bp);
930 bp->flags &= ~BNXT_FLAG_INIT_DONE;
931 if (bp->eth_dev->data->dev_started) {
932 /* TBD: STOP HW queues DMA */
933 eth_dev->data->dev_link.link_status = 0;
935 bnxt_dev_set_link_down_op(eth_dev);
937 /* Wait for link to be reset and the async notification to process.
938 * During reset recovery, there is no need to wait
940 if (!is_bnxt_in_error(bp))
941 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL * 2);
943 /* Clean queue intr-vector mapping */
944 rte_intr_efd_disable(intr_handle);
945 if (intr_handle->intr_vec != NULL) {
946 rte_free(intr_handle->intr_vec);
947 intr_handle->intr_vec = NULL;
950 bnxt_hwrm_port_clr_stats(bp);
951 bnxt_free_tx_mbufs(bp);
952 bnxt_free_rx_mbufs(bp);
953 /* Process any remaining notifications in default completion queue */
954 bnxt_int_handler(eth_dev);
955 bnxt_shutdown_nic(bp);
956 bnxt_hwrm_if_change(bp, 0);
961 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
963 struct bnxt *bp = eth_dev->data->dev_private;
965 if (bp->dev_stopped == 0)
966 bnxt_dev_stop_op(eth_dev);
968 if (eth_dev->data->mac_addrs != NULL) {
969 rte_free(eth_dev->data->mac_addrs);
970 eth_dev->data->mac_addrs = NULL;
972 if (bp->grp_info != NULL) {
973 rte_free(bp->grp_info);
977 bnxt_dev_uninit(eth_dev);
980 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
983 struct bnxt *bp = eth_dev->data->dev_private;
984 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
985 struct bnxt_vnic_info *vnic;
986 struct bnxt_filter_info *filter, *temp_filter;
989 if (is_bnxt_in_error(bp))
993 * Loop through all VNICs from the specified filter flow pools to
994 * remove the corresponding MAC addr filter
996 for (i = 0; i < bp->nr_vnics; i++) {
997 if (!(pool_mask & (1ULL << i)))
1000 vnic = &bp->vnic_info[i];
1001 filter = STAILQ_FIRST(&vnic->filter);
1003 temp_filter = STAILQ_NEXT(filter, next);
1004 if (filter->mac_index == index) {
1005 STAILQ_REMOVE(&vnic->filter, filter,
1006 bnxt_filter_info, next);
1007 bnxt_hwrm_clear_l2_filter(bp, filter);
1008 filter->mac_index = INVALID_MAC_INDEX;
1009 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1010 bnxt_free_filter(bp, filter);
1012 filter = temp_filter;
1017 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1018 struct rte_ether_addr *mac_addr, uint32_t index,
1021 struct bnxt_filter_info *filter;
1024 /* Attach requested MAC address to the new l2_filter */
1025 STAILQ_FOREACH(filter, &vnic->filter, next) {
1026 if (filter->mac_index == index) {
1028 "MAC addr already existed for pool %d\n",
1034 filter = bnxt_alloc_filter(bp);
1036 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1040 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1041 * if the MAC that's been programmed now is a different one, then,
1042 * copy that addr to filter->l2_addr
1045 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1046 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1048 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1050 filter->mac_index = index;
1051 if (filter->mac_index == 0)
1052 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1054 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1056 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1057 bnxt_free_filter(bp, filter);
1063 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1064 struct rte_ether_addr *mac_addr,
1065 uint32_t index, uint32_t pool)
1067 struct bnxt *bp = eth_dev->data->dev_private;
1068 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1071 rc = is_bnxt_in_error(bp);
1075 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1076 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1081 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1085 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1090 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1093 struct bnxt *bp = eth_dev->data->dev_private;
1094 struct rte_eth_link new;
1095 unsigned int cnt = BNXT_LINK_WAIT_CNT;
1097 rc = is_bnxt_in_error(bp);
1101 memset(&new, 0, sizeof(new));
1103 /* Retrieve link info from hardware */
1104 rc = bnxt_get_hwrm_link_config(bp, &new);
1106 new.link_speed = ETH_LINK_SPEED_100M;
1107 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1109 "Failed to retrieve link rc = 0x%x!\n", rc);
1113 if (!wait_to_complete || new.link_status)
1116 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1120 /* Timed out or success */
1121 if (new.link_status != eth_dev->data->dev_link.link_status ||
1122 new.link_speed != eth_dev->data->dev_link.link_speed) {
1123 rte_eth_linkstatus_set(eth_dev, &new);
1125 _rte_eth_dev_callback_process(eth_dev,
1126 RTE_ETH_EVENT_INTR_LSC,
1129 bnxt_print_link_info(eth_dev);
1135 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1137 struct bnxt *bp = eth_dev->data->dev_private;
1138 struct bnxt_vnic_info *vnic;
1142 rc = is_bnxt_in_error(bp);
1146 if (bp->vnic_info == NULL)
1149 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1151 old_flags = vnic->flags;
1152 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1153 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1155 vnic->flags = old_flags;
1160 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1162 struct bnxt *bp = eth_dev->data->dev_private;
1163 struct bnxt_vnic_info *vnic;
1167 rc = is_bnxt_in_error(bp);
1171 if (bp->vnic_info == NULL)
1174 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1176 old_flags = vnic->flags;
1177 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1178 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1180 vnic->flags = old_flags;
1185 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1187 struct bnxt *bp = eth_dev->data->dev_private;
1188 struct bnxt_vnic_info *vnic;
1192 rc = is_bnxt_in_error(bp);
1196 if (bp->vnic_info == NULL)
1199 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1201 old_flags = vnic->flags;
1202 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1203 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1205 vnic->flags = old_flags;
1210 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1212 struct bnxt *bp = eth_dev->data->dev_private;
1213 struct bnxt_vnic_info *vnic;
1217 rc = is_bnxt_in_error(bp);
1221 if (bp->vnic_info == NULL)
1224 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1226 old_flags = vnic->flags;
1227 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1228 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1230 vnic->flags = old_flags;
1235 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1236 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1238 if (qid >= bp->rx_nr_rings)
1241 return bp->eth_dev->data->rx_queues[qid];
1244 /* Return rxq corresponding to a given rss table ring/group ID. */
1245 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1247 struct bnxt_rx_queue *rxq;
1250 if (!BNXT_HAS_RING_GRPS(bp)) {
1251 for (i = 0; i < bp->rx_nr_rings; i++) {
1252 rxq = bp->eth_dev->data->rx_queues[i];
1253 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1257 for (i = 0; i < bp->rx_nr_rings; i++) {
1258 if (bp->grp_info[i].fw_grp_id == fwr)
1263 return INVALID_HW_RING_ID;
1266 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1267 struct rte_eth_rss_reta_entry64 *reta_conf,
1270 struct bnxt *bp = eth_dev->data->dev_private;
1271 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1272 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1273 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1277 rc = is_bnxt_in_error(bp);
1281 if (!vnic->rss_table)
1284 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1287 if (reta_size != tbl_size) {
1288 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1289 "(%d) must equal the size supported by the hardware "
1290 "(%d)\n", reta_size, tbl_size);
1294 for (i = 0; i < reta_size; i++) {
1295 struct bnxt_rx_queue *rxq;
1297 idx = i / RTE_RETA_GROUP_SIZE;
1298 sft = i % RTE_RETA_GROUP_SIZE;
1300 if (!(reta_conf[idx].mask & (1ULL << sft)))
1303 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1305 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1309 if (BNXT_CHIP_THOR(bp)) {
1310 vnic->rss_table[i * 2] =
1311 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1312 vnic->rss_table[i * 2 + 1] =
1313 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1315 vnic->rss_table[i] =
1316 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1320 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1324 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1325 struct rte_eth_rss_reta_entry64 *reta_conf,
1328 struct bnxt *bp = eth_dev->data->dev_private;
1329 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1330 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1331 uint16_t idx, sft, i;
1334 rc = is_bnxt_in_error(bp);
1338 /* Retrieve from the default VNIC */
1341 if (!vnic->rss_table)
1344 if (reta_size != tbl_size) {
1345 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1346 "(%d) must equal the size supported by the hardware "
1347 "(%d)\n", reta_size, tbl_size);
1351 for (idx = 0, i = 0; i < reta_size; i++) {
1352 idx = i / RTE_RETA_GROUP_SIZE;
1353 sft = i % RTE_RETA_GROUP_SIZE;
1355 if (reta_conf[idx].mask & (1ULL << sft)) {
1358 if (BNXT_CHIP_THOR(bp))
1359 qid = bnxt_rss_to_qid(bp,
1360 vnic->rss_table[i * 2]);
1362 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1364 if (qid == INVALID_HW_RING_ID) {
1365 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1368 reta_conf[idx].reta[sft] = qid;
1375 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1376 struct rte_eth_rss_conf *rss_conf)
1378 struct bnxt *bp = eth_dev->data->dev_private;
1379 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1380 struct bnxt_vnic_info *vnic;
1383 rc = is_bnxt_in_error(bp);
1388 * If RSS enablement were different than dev_configure,
1389 * then return -EINVAL
1391 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1392 if (!rss_conf->rss_hf)
1393 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1395 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1399 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1400 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1402 /* Update the default RSS VNIC(s) */
1403 vnic = &bp->vnic_info[0];
1404 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1407 * If hashkey is not specified, use the previously configured
1410 if (!rss_conf->rss_key)
1413 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1415 "Invalid hashkey length, should be 16 bytes\n");
1418 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1421 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1425 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1426 struct rte_eth_rss_conf *rss_conf)
1428 struct bnxt *bp = eth_dev->data->dev_private;
1429 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1431 uint32_t hash_types;
1433 rc = is_bnxt_in_error(bp);
1437 /* RSS configuration is the same for all VNICs */
1438 if (vnic && vnic->rss_hash_key) {
1439 if (rss_conf->rss_key) {
1440 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1441 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1442 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1445 hash_types = vnic->hash_type;
1446 rss_conf->rss_hf = 0;
1447 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1448 rss_conf->rss_hf |= ETH_RSS_IPV4;
1449 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1451 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1452 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1454 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1456 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1457 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1459 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1461 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1462 rss_conf->rss_hf |= ETH_RSS_IPV6;
1463 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1465 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1466 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1468 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1470 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1471 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1473 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1477 "Unknwon RSS config from firmware (%08x), RSS disabled",
1482 rss_conf->rss_hf = 0;
1487 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1488 struct rte_eth_fc_conf *fc_conf)
1490 struct bnxt *bp = dev->data->dev_private;
1491 struct rte_eth_link link_info;
1494 rc = is_bnxt_in_error(bp);
1498 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1502 memset(fc_conf, 0, sizeof(*fc_conf));
1503 if (bp->link_info.auto_pause)
1504 fc_conf->autoneg = 1;
1505 switch (bp->link_info.pause) {
1507 fc_conf->mode = RTE_FC_NONE;
1509 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1510 fc_conf->mode = RTE_FC_TX_PAUSE;
1512 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1513 fc_conf->mode = RTE_FC_RX_PAUSE;
1515 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1516 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1517 fc_conf->mode = RTE_FC_FULL;
1523 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1524 struct rte_eth_fc_conf *fc_conf)
1526 struct bnxt *bp = dev->data->dev_private;
1529 rc = is_bnxt_in_error(bp);
1533 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1534 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1538 switch (fc_conf->mode) {
1540 bp->link_info.auto_pause = 0;
1541 bp->link_info.force_pause = 0;
1543 case RTE_FC_RX_PAUSE:
1544 if (fc_conf->autoneg) {
1545 bp->link_info.auto_pause =
1546 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1547 bp->link_info.force_pause = 0;
1549 bp->link_info.auto_pause = 0;
1550 bp->link_info.force_pause =
1551 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1554 case RTE_FC_TX_PAUSE:
1555 if (fc_conf->autoneg) {
1556 bp->link_info.auto_pause =
1557 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1558 bp->link_info.force_pause = 0;
1560 bp->link_info.auto_pause = 0;
1561 bp->link_info.force_pause =
1562 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1566 if (fc_conf->autoneg) {
1567 bp->link_info.auto_pause =
1568 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1569 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1570 bp->link_info.force_pause = 0;
1572 bp->link_info.auto_pause = 0;
1573 bp->link_info.force_pause =
1574 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1575 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1579 return bnxt_set_hwrm_link_config(bp, true);
1582 /* Add UDP tunneling port */
1584 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1585 struct rte_eth_udp_tunnel *udp_tunnel)
1587 struct bnxt *bp = eth_dev->data->dev_private;
1588 uint16_t tunnel_type = 0;
1591 rc = is_bnxt_in_error(bp);
1595 switch (udp_tunnel->prot_type) {
1596 case RTE_TUNNEL_TYPE_VXLAN:
1597 if (bp->vxlan_port_cnt) {
1598 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1599 udp_tunnel->udp_port);
1600 if (bp->vxlan_port != udp_tunnel->udp_port) {
1601 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1604 bp->vxlan_port_cnt++;
1608 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1609 bp->vxlan_port_cnt++;
1611 case RTE_TUNNEL_TYPE_GENEVE:
1612 if (bp->geneve_port_cnt) {
1613 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1614 udp_tunnel->udp_port);
1615 if (bp->geneve_port != udp_tunnel->udp_port) {
1616 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1619 bp->geneve_port_cnt++;
1623 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1624 bp->geneve_port_cnt++;
1627 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1630 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1636 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1637 struct rte_eth_udp_tunnel *udp_tunnel)
1639 struct bnxt *bp = eth_dev->data->dev_private;
1640 uint16_t tunnel_type = 0;
1644 rc = is_bnxt_in_error(bp);
1648 switch (udp_tunnel->prot_type) {
1649 case RTE_TUNNEL_TYPE_VXLAN:
1650 if (!bp->vxlan_port_cnt) {
1651 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1654 if (bp->vxlan_port != udp_tunnel->udp_port) {
1655 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1656 udp_tunnel->udp_port, bp->vxlan_port);
1659 if (--bp->vxlan_port_cnt)
1663 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1664 port = bp->vxlan_fw_dst_port_id;
1666 case RTE_TUNNEL_TYPE_GENEVE:
1667 if (!bp->geneve_port_cnt) {
1668 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1671 if (bp->geneve_port != udp_tunnel->udp_port) {
1672 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1673 udp_tunnel->udp_port, bp->geneve_port);
1676 if (--bp->geneve_port_cnt)
1680 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1681 port = bp->geneve_fw_dst_port_id;
1684 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1688 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1691 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1694 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1695 bp->geneve_port = 0;
1700 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1702 struct bnxt_filter_info *filter;
1703 struct bnxt_vnic_info *vnic;
1705 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1707 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1708 filter = STAILQ_FIRST(&vnic->filter);
1710 /* Search for this matching MAC+VLAN filter */
1711 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
1712 /* Delete the filter */
1713 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1716 STAILQ_REMOVE(&vnic->filter, filter,
1717 bnxt_filter_info, next);
1718 bnxt_free_filter(bp, filter);
1720 "Deleted vlan filter for %d\n",
1724 filter = STAILQ_NEXT(filter, next);
1729 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1731 struct bnxt_filter_info *filter;
1732 struct bnxt_vnic_info *vnic;
1734 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1735 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1736 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1738 /* Implementation notes on the use of VNIC in this command:
1740 * By default, these filters belong to default vnic for the function.
1741 * Once these filters are set up, only destination VNIC can be modified.
1742 * If the destination VNIC is not specified in this command,
1743 * then the HWRM shall only create an l2 context id.
1746 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1747 filter = STAILQ_FIRST(&vnic->filter);
1748 /* Check if the VLAN has already been added */
1750 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
1753 filter = STAILQ_NEXT(filter, next);
1756 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1757 * command to create MAC+VLAN filter with the right flags, enables set.
1759 filter = bnxt_alloc_filter(bp);
1762 "MAC/VLAN filter alloc failed\n");
1765 /* MAC + VLAN ID filter */
1766 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1767 * untagged packets are received
1769 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
1770 * packets and only the programmed vlan's packets are received
1772 filter->l2_ivlan = vlan_id;
1773 filter->l2_ivlan_mask = 0x0FFF;
1774 filter->enables |= en;
1775 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1777 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1779 /* Free the newly allocated filter as we were
1780 * not able to create the filter in hardware.
1782 filter->fw_l2_filter_id = UINT64_MAX;
1783 bnxt_free_filter(bp, filter);
1787 filter->mac_index = 0;
1788 /* Add this new filter to the list */
1790 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1792 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1795 "Added Vlan filter for %d\n", vlan_id);
1799 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1800 uint16_t vlan_id, int on)
1802 struct bnxt *bp = eth_dev->data->dev_private;
1805 rc = is_bnxt_in_error(bp);
1809 /* These operations apply to ALL existing MAC/VLAN filters */
1811 return bnxt_add_vlan_filter(bp, vlan_id);
1813 return bnxt_del_vlan_filter(bp, vlan_id);
1816 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
1817 struct bnxt_vnic_info *vnic)
1819 struct bnxt_filter_info *filter;
1822 filter = STAILQ_FIRST(&vnic->filter);
1824 if (filter->mac_index == 0 &&
1825 !memcmp(filter->l2_addr, bp->mac_addr,
1826 RTE_ETHER_ADDR_LEN)) {
1827 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1829 STAILQ_REMOVE(&vnic->filter, filter,
1830 bnxt_filter_info, next);
1831 bnxt_free_filter(bp, filter);
1832 filter->fw_l2_filter_id = UINT64_MAX;
1836 filter = STAILQ_NEXT(filter, next);
1842 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1844 struct bnxt *bp = dev->data->dev_private;
1845 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1846 struct bnxt_vnic_info *vnic;
1850 rc = is_bnxt_in_error(bp);
1854 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1855 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1856 /* Remove any VLAN filters programmed */
1857 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1858 bnxt_del_vlan_filter(bp, i);
1860 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1864 /* Default filter will allow packets that match the
1865 * dest mac. So, it has to be deleted, otherwise, we
1866 * will endup receiving vlan packets for which the
1867 * filter is not programmed, when hw-vlan-filter
1868 * configuration is ON
1870 bnxt_del_dflt_mac_filter(bp, vnic);
1871 /* This filter will allow only untagged packets */
1872 bnxt_add_vlan_filter(bp, 0);
1874 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1875 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1877 if (mask & ETH_VLAN_STRIP_MASK) {
1878 /* Enable or disable VLAN stripping */
1879 for (i = 0; i < bp->nr_vnics; i++) {
1880 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1881 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1882 vnic->vlan_strip = true;
1884 vnic->vlan_strip = false;
1885 bnxt_hwrm_vnic_cfg(bp, vnic);
1887 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1888 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1891 if (mask & ETH_VLAN_EXTEND_MASK) {
1892 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1893 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
1895 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
1902 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
1905 struct bnxt *bp = dev->data->dev_private;
1906 int qinq = dev->data->dev_conf.rxmode.offloads &
1907 DEV_RX_OFFLOAD_VLAN_EXTEND;
1909 if (vlan_type != ETH_VLAN_TYPE_INNER &&
1910 vlan_type != ETH_VLAN_TYPE_OUTER) {
1912 "Unsupported vlan type.");
1917 "QinQ not enabled. Needs to be ON as we can "
1918 "accelerate only outer vlan\n");
1922 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
1924 case RTE_ETHER_TYPE_QINQ:
1926 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
1928 case RTE_ETHER_TYPE_VLAN:
1930 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
1934 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
1938 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
1942 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
1945 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
1948 bp->outer_tpid_bd |= tpid;
1949 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
1950 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
1952 "Can accelerate only outer vlan in QinQ\n");
1960 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1961 struct rte_ether_addr *addr)
1963 struct bnxt *bp = dev->data->dev_private;
1964 /* Default Filter is tied to VNIC 0 */
1965 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1966 struct bnxt_filter_info *filter;
1969 rc = is_bnxt_in_error(bp);
1973 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1976 if (rte_is_zero_ether_addr(addr))
1979 STAILQ_FOREACH(filter, &vnic->filter, next) {
1980 /* Default Filter is at Index 0 */
1981 if (filter->mac_index != 0)
1984 memcpy(filter->l2_addr, addr, RTE_ETHER_ADDR_LEN);
1985 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1986 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX |
1987 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1989 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1990 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1992 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1994 memcpy(filter->l2_addr, bp->mac_addr,
1995 RTE_ETHER_ADDR_LEN);
1999 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2000 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2008 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2009 struct rte_ether_addr *mc_addr_set,
2010 uint32_t nb_mc_addr)
2012 struct bnxt *bp = eth_dev->data->dev_private;
2013 char *mc_addr_list = (char *)mc_addr_set;
2014 struct bnxt_vnic_info *vnic;
2015 uint32_t off = 0, i = 0;
2018 rc = is_bnxt_in_error(bp);
2022 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2024 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2025 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2029 /* TODO Check for Duplicate mcast addresses */
2030 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2031 for (i = 0; i < nb_mc_addr; i++) {
2032 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2033 RTE_ETHER_ADDR_LEN);
2034 off += RTE_ETHER_ADDR_LEN;
2037 vnic->mc_addr_cnt = i;
2038 if (vnic->mc_addr_cnt)
2039 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2041 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2044 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2048 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2050 struct bnxt *bp = dev->data->dev_private;
2051 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2052 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2053 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2056 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2057 fw_major, fw_minor, fw_updt);
2059 ret += 1; /* add the size of '\0' */
2060 if (fw_size < (uint32_t)ret)
2067 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2068 struct rte_eth_rxq_info *qinfo)
2070 struct bnxt_rx_queue *rxq;
2072 rxq = dev->data->rx_queues[queue_id];
2074 qinfo->mp = rxq->mb_pool;
2075 qinfo->scattered_rx = dev->data->scattered_rx;
2076 qinfo->nb_desc = rxq->nb_rx_desc;
2078 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2079 qinfo->conf.rx_drop_en = 0;
2080 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2084 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2085 struct rte_eth_txq_info *qinfo)
2087 struct bnxt_tx_queue *txq;
2089 txq = dev->data->tx_queues[queue_id];
2091 qinfo->nb_desc = txq->nb_tx_desc;
2093 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2094 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2095 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2097 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2098 qinfo->conf.tx_rs_thresh = 0;
2099 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2102 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2104 struct bnxt *bp = eth_dev->data->dev_private;
2105 uint32_t new_pkt_size;
2109 rc = is_bnxt_in_error(bp);
2113 /* Exit if receive queues are not configured yet */
2114 if (!eth_dev->data->nb_rx_queues)
2117 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2118 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2122 * If vector-mode tx/rx is active, disallow any MTU change that would
2123 * require scattered receive support.
2125 if (eth_dev->data->dev_started &&
2126 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2127 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2129 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2131 "MTU change would require scattered rx support. ");
2132 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2137 if (new_mtu > RTE_ETHER_MTU) {
2138 bp->flags |= BNXT_FLAG_JUMBO;
2139 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2140 DEV_RX_OFFLOAD_JUMBO_FRAME;
2142 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2143 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2144 bp->flags &= ~BNXT_FLAG_JUMBO;
2147 /* Is there a change in mtu setting? */
2148 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2151 for (i = 0; i < bp->nr_vnics; i++) {
2152 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2155 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2156 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2160 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2161 size -= RTE_PKTMBUF_HEADROOM;
2163 if (size < new_mtu) {
2164 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2171 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2173 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2179 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2181 struct bnxt *bp = dev->data->dev_private;
2182 uint16_t vlan = bp->vlan;
2185 rc = is_bnxt_in_error(bp);
2189 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2191 "PVID cannot be modified for this function\n");
2194 bp->vlan = on ? pvid : 0;
2196 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2203 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2205 struct bnxt *bp = dev->data->dev_private;
2208 rc = is_bnxt_in_error(bp);
2212 return bnxt_hwrm_port_led_cfg(bp, true);
2216 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2218 struct bnxt *bp = dev->data->dev_private;
2221 rc = is_bnxt_in_error(bp);
2225 return bnxt_hwrm_port_led_cfg(bp, false);
2229 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2231 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2232 uint32_t desc = 0, raw_cons = 0, cons;
2233 struct bnxt_cp_ring_info *cpr;
2234 struct bnxt_rx_queue *rxq;
2235 struct rx_pkt_cmpl *rxcmp;
2238 rc = is_bnxt_in_error(bp);
2242 rxq = dev->data->rx_queues[rx_queue_id];
2244 raw_cons = cpr->cp_raw_cons;
2247 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2248 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2249 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2251 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2263 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2265 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2266 struct bnxt_rx_ring_info *rxr;
2267 struct bnxt_cp_ring_info *cpr;
2268 struct bnxt_sw_rx_bd *rx_buf;
2269 struct rx_pkt_cmpl *rxcmp;
2270 uint32_t cons, cp_cons;
2276 rc = is_bnxt_in_error(rxq->bp);
2283 if (offset >= rxq->nb_rx_desc)
2286 cons = RING_CMP(cpr->cp_ring_struct, offset);
2287 cp_cons = cpr->cp_raw_cons;
2288 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2290 if (cons > cp_cons) {
2291 if (CMPL_VALID(rxcmp, cpr->valid))
2292 return RTE_ETH_RX_DESC_DONE;
2294 if (CMPL_VALID(rxcmp, !cpr->valid))
2295 return RTE_ETH_RX_DESC_DONE;
2297 rx_buf = &rxr->rx_buf_ring[cons];
2298 if (rx_buf->mbuf == NULL)
2299 return RTE_ETH_RX_DESC_UNAVAIL;
2302 return RTE_ETH_RX_DESC_AVAIL;
2306 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2308 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2309 struct bnxt_tx_ring_info *txr;
2310 struct bnxt_cp_ring_info *cpr;
2311 struct bnxt_sw_tx_bd *tx_buf;
2312 struct tx_pkt_cmpl *txcmp;
2313 uint32_t cons, cp_cons;
2319 rc = is_bnxt_in_error(txq->bp);
2326 if (offset >= txq->nb_tx_desc)
2329 cons = RING_CMP(cpr->cp_ring_struct, offset);
2330 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2331 cp_cons = cpr->cp_raw_cons;
2333 if (cons > cp_cons) {
2334 if (CMPL_VALID(txcmp, cpr->valid))
2335 return RTE_ETH_TX_DESC_UNAVAIL;
2337 if (CMPL_VALID(txcmp, !cpr->valid))
2338 return RTE_ETH_TX_DESC_UNAVAIL;
2340 tx_buf = &txr->tx_buf_ring[cons];
2341 if (tx_buf->mbuf == NULL)
2342 return RTE_ETH_TX_DESC_DONE;
2344 return RTE_ETH_TX_DESC_FULL;
2347 static struct bnxt_filter_info *
2348 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2349 struct rte_eth_ethertype_filter *efilter,
2350 struct bnxt_vnic_info *vnic0,
2351 struct bnxt_vnic_info *vnic,
2354 struct bnxt_filter_info *mfilter = NULL;
2358 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2359 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2360 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2361 " ethertype filter.", efilter->ether_type);
2365 if (efilter->queue >= bp->rx_nr_rings) {
2366 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2371 vnic0 = &bp->vnic_info[0];
2372 vnic = &bp->vnic_info[efilter->queue];
2374 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2379 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2380 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2381 if ((!memcmp(efilter->mac_addr.addr_bytes,
2382 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2384 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2385 mfilter->ethertype == efilter->ether_type)) {
2391 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2392 if ((!memcmp(efilter->mac_addr.addr_bytes,
2393 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2394 mfilter->ethertype == efilter->ether_type &&
2396 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2410 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2411 enum rte_filter_op filter_op,
2414 struct bnxt *bp = dev->data->dev_private;
2415 struct rte_eth_ethertype_filter *efilter =
2416 (struct rte_eth_ethertype_filter *)arg;
2417 struct bnxt_filter_info *bfilter, *filter1;
2418 struct bnxt_vnic_info *vnic, *vnic0;
2421 if (filter_op == RTE_ETH_FILTER_NOP)
2425 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2430 vnic0 = &bp->vnic_info[0];
2431 vnic = &bp->vnic_info[efilter->queue];
2433 switch (filter_op) {
2434 case RTE_ETH_FILTER_ADD:
2435 bnxt_match_and_validate_ether_filter(bp, efilter,
2440 bfilter = bnxt_get_unused_filter(bp);
2441 if (bfilter == NULL) {
2443 "Not enough resources for a new filter.\n");
2446 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2447 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2448 RTE_ETHER_ADDR_LEN);
2449 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2450 RTE_ETHER_ADDR_LEN);
2451 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2452 bfilter->ethertype = efilter->ether_type;
2453 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2455 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2456 if (filter1 == NULL) {
2461 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2462 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2464 bfilter->dst_id = vnic->fw_vnic_id;
2466 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2468 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2471 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2474 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2476 case RTE_ETH_FILTER_DELETE:
2477 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2479 if (ret == -EEXIST) {
2480 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2482 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2484 bnxt_free_filter(bp, filter1);
2485 } else if (ret == 0) {
2486 PMD_DRV_LOG(ERR, "No matching filter found\n");
2490 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2496 bnxt_free_filter(bp, bfilter);
2502 parse_ntuple_filter(struct bnxt *bp,
2503 struct rte_eth_ntuple_filter *nfilter,
2504 struct bnxt_filter_info *bfilter)
2508 if (nfilter->queue >= bp->rx_nr_rings) {
2509 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2513 switch (nfilter->dst_port_mask) {
2515 bfilter->dst_port_mask = -1;
2516 bfilter->dst_port = nfilter->dst_port;
2517 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2518 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2521 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2525 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2526 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2528 switch (nfilter->proto_mask) {
2530 if (nfilter->proto == 17) /* IPPROTO_UDP */
2531 bfilter->ip_protocol = 17;
2532 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2533 bfilter->ip_protocol = 6;
2536 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2539 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2543 switch (nfilter->dst_ip_mask) {
2545 bfilter->dst_ipaddr_mask[0] = -1;
2546 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2547 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2548 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2551 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2555 switch (nfilter->src_ip_mask) {
2557 bfilter->src_ipaddr_mask[0] = -1;
2558 bfilter->src_ipaddr[0] = nfilter->src_ip;
2559 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2560 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2563 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2567 switch (nfilter->src_port_mask) {
2569 bfilter->src_port_mask = -1;
2570 bfilter->src_port = nfilter->src_port;
2571 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2572 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2575 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2579 bfilter->enables = en;
2583 static struct bnxt_filter_info*
2584 bnxt_match_ntuple_filter(struct bnxt *bp,
2585 struct bnxt_filter_info *bfilter,
2586 struct bnxt_vnic_info **mvnic)
2588 struct bnxt_filter_info *mfilter = NULL;
2591 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2592 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2593 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2594 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2595 bfilter->src_ipaddr_mask[0] ==
2596 mfilter->src_ipaddr_mask[0] &&
2597 bfilter->src_port == mfilter->src_port &&
2598 bfilter->src_port_mask == mfilter->src_port_mask &&
2599 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2600 bfilter->dst_ipaddr_mask[0] ==
2601 mfilter->dst_ipaddr_mask[0] &&
2602 bfilter->dst_port == mfilter->dst_port &&
2603 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2604 bfilter->flags == mfilter->flags &&
2605 bfilter->enables == mfilter->enables) {
2616 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2617 struct rte_eth_ntuple_filter *nfilter,
2618 enum rte_filter_op filter_op)
2620 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2621 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2624 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2625 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2629 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2630 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2634 bfilter = bnxt_get_unused_filter(bp);
2635 if (bfilter == NULL) {
2637 "Not enough resources for a new filter.\n");
2640 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2644 vnic = &bp->vnic_info[nfilter->queue];
2645 vnic0 = &bp->vnic_info[0];
2646 filter1 = STAILQ_FIRST(&vnic0->filter);
2647 if (filter1 == NULL) {
2652 bfilter->dst_id = vnic->fw_vnic_id;
2653 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2655 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2656 bfilter->ethertype = 0x800;
2657 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2659 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2661 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2662 bfilter->dst_id == mfilter->dst_id) {
2663 PMD_DRV_LOG(ERR, "filter exists.\n");
2666 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2667 bfilter->dst_id != mfilter->dst_id) {
2668 mfilter->dst_id = vnic->fw_vnic_id;
2669 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2670 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2671 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2672 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2673 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2676 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2677 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2682 if (filter_op == RTE_ETH_FILTER_ADD) {
2683 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2684 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2687 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2689 if (mfilter == NULL) {
2690 /* This should not happen. But for Coverity! */
2694 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2696 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2697 bnxt_free_filter(bp, mfilter);
2698 mfilter->fw_l2_filter_id = -1;
2699 bnxt_free_filter(bp, bfilter);
2700 bfilter->fw_l2_filter_id = -1;
2705 bfilter->fw_l2_filter_id = -1;
2706 bnxt_free_filter(bp, bfilter);
2711 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2712 enum rte_filter_op filter_op,
2715 struct bnxt *bp = dev->data->dev_private;
2718 if (filter_op == RTE_ETH_FILTER_NOP)
2722 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2727 switch (filter_op) {
2728 case RTE_ETH_FILTER_ADD:
2729 ret = bnxt_cfg_ntuple_filter(bp,
2730 (struct rte_eth_ntuple_filter *)arg,
2733 case RTE_ETH_FILTER_DELETE:
2734 ret = bnxt_cfg_ntuple_filter(bp,
2735 (struct rte_eth_ntuple_filter *)arg,
2739 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2747 bnxt_parse_fdir_filter(struct bnxt *bp,
2748 struct rte_eth_fdir_filter *fdir,
2749 struct bnxt_filter_info *filter)
2751 enum rte_fdir_mode fdir_mode =
2752 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2753 struct bnxt_vnic_info *vnic0, *vnic;
2754 struct bnxt_filter_info *filter1;
2758 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2761 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2762 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2764 switch (fdir->input.flow_type) {
2765 case RTE_ETH_FLOW_IPV4:
2766 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2768 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2769 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2770 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2771 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2772 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2773 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2774 filter->ip_addr_type =
2775 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2776 filter->src_ipaddr_mask[0] = 0xffffffff;
2777 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2778 filter->dst_ipaddr_mask[0] = 0xffffffff;
2779 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2780 filter->ethertype = 0x800;
2781 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2783 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2784 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2785 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2786 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2787 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2788 filter->dst_port_mask = 0xffff;
2789 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2790 filter->src_port_mask = 0xffff;
2791 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2792 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2793 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2794 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2795 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2796 filter->ip_protocol = 6;
2797 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2798 filter->ip_addr_type =
2799 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2800 filter->src_ipaddr_mask[0] = 0xffffffff;
2801 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2802 filter->dst_ipaddr_mask[0] = 0xffffffff;
2803 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2804 filter->ethertype = 0x800;
2805 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2807 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2808 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2809 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2810 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2811 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2812 filter->dst_port_mask = 0xffff;
2813 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2814 filter->src_port_mask = 0xffff;
2815 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2816 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2817 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2818 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2819 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2820 filter->ip_protocol = 17;
2821 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2822 filter->ip_addr_type =
2823 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2824 filter->src_ipaddr_mask[0] = 0xffffffff;
2825 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2826 filter->dst_ipaddr_mask[0] = 0xffffffff;
2827 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2828 filter->ethertype = 0x800;
2829 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2831 case RTE_ETH_FLOW_IPV6:
2832 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2834 filter->ip_addr_type =
2835 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2836 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2837 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2838 rte_memcpy(filter->src_ipaddr,
2839 fdir->input.flow.ipv6_flow.src_ip, 16);
2840 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2841 rte_memcpy(filter->dst_ipaddr,
2842 fdir->input.flow.ipv6_flow.dst_ip, 16);
2843 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2844 memset(filter->dst_ipaddr_mask, 0xff, 16);
2845 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2846 memset(filter->src_ipaddr_mask, 0xff, 16);
2847 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2848 filter->ethertype = 0x86dd;
2849 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2851 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2852 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2853 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2854 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2855 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2856 filter->dst_port_mask = 0xffff;
2857 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2858 filter->src_port_mask = 0xffff;
2859 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2860 filter->ip_addr_type =
2861 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2862 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2863 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2864 rte_memcpy(filter->src_ipaddr,
2865 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2866 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2867 rte_memcpy(filter->dst_ipaddr,
2868 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2869 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2870 memset(filter->dst_ipaddr_mask, 0xff, 16);
2871 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2872 memset(filter->src_ipaddr_mask, 0xff, 16);
2873 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2874 filter->ethertype = 0x86dd;
2875 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2877 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2878 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2879 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2880 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2881 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2882 filter->dst_port_mask = 0xffff;
2883 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2884 filter->src_port_mask = 0xffff;
2885 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2886 filter->ip_addr_type =
2887 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2888 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2889 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2890 rte_memcpy(filter->src_ipaddr,
2891 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2892 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2893 rte_memcpy(filter->dst_ipaddr,
2894 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2895 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2896 memset(filter->dst_ipaddr_mask, 0xff, 16);
2897 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2898 memset(filter->src_ipaddr_mask, 0xff, 16);
2899 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2900 filter->ethertype = 0x86dd;
2901 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2903 case RTE_ETH_FLOW_L2_PAYLOAD:
2904 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2905 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2907 case RTE_ETH_FLOW_VXLAN:
2908 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2910 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2911 filter->tunnel_type =
2912 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2913 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2915 case RTE_ETH_FLOW_NVGRE:
2916 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2918 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2919 filter->tunnel_type =
2920 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2921 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2923 case RTE_ETH_FLOW_UNKNOWN:
2924 case RTE_ETH_FLOW_RAW:
2925 case RTE_ETH_FLOW_FRAG_IPV4:
2926 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2927 case RTE_ETH_FLOW_FRAG_IPV6:
2928 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2929 case RTE_ETH_FLOW_IPV6_EX:
2930 case RTE_ETH_FLOW_IPV6_TCP_EX:
2931 case RTE_ETH_FLOW_IPV6_UDP_EX:
2932 case RTE_ETH_FLOW_GENEVE:
2938 vnic0 = &bp->vnic_info[0];
2939 vnic = &bp->vnic_info[fdir->action.rx_queue];
2941 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2945 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2946 rte_memcpy(filter->dst_macaddr,
2947 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2948 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2951 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2952 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2953 filter1 = STAILQ_FIRST(&vnic0->filter);
2954 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2956 filter->dst_id = vnic->fw_vnic_id;
2957 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2958 if (filter->dst_macaddr[i] == 0x00)
2959 filter1 = STAILQ_FIRST(&vnic0->filter);
2961 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2964 if (filter1 == NULL)
2967 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2968 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2970 filter->enables = en;
2975 static struct bnxt_filter_info *
2976 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2977 struct bnxt_vnic_info **mvnic)
2979 struct bnxt_filter_info *mf = NULL;
2982 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2983 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2985 STAILQ_FOREACH(mf, &vnic->filter, next) {
2986 if (mf->filter_type == nf->filter_type &&
2987 mf->flags == nf->flags &&
2988 mf->src_port == nf->src_port &&
2989 mf->src_port_mask == nf->src_port_mask &&
2990 mf->dst_port == nf->dst_port &&
2991 mf->dst_port_mask == nf->dst_port_mask &&
2992 mf->ip_protocol == nf->ip_protocol &&
2993 mf->ip_addr_type == nf->ip_addr_type &&
2994 mf->ethertype == nf->ethertype &&
2995 mf->vni == nf->vni &&
2996 mf->tunnel_type == nf->tunnel_type &&
2997 mf->l2_ovlan == nf->l2_ovlan &&
2998 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2999 mf->l2_ivlan == nf->l2_ivlan &&
3000 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3001 !memcmp(mf->l2_addr, nf->l2_addr,
3002 RTE_ETHER_ADDR_LEN) &&
3003 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3004 RTE_ETHER_ADDR_LEN) &&
3005 !memcmp(mf->src_macaddr, nf->src_macaddr,
3006 RTE_ETHER_ADDR_LEN) &&
3007 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3008 RTE_ETHER_ADDR_LEN) &&
3009 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3010 sizeof(nf->src_ipaddr)) &&
3011 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3012 sizeof(nf->src_ipaddr_mask)) &&
3013 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3014 sizeof(nf->dst_ipaddr)) &&
3015 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3016 sizeof(nf->dst_ipaddr_mask))) {
3027 bnxt_fdir_filter(struct rte_eth_dev *dev,
3028 enum rte_filter_op filter_op,
3031 struct bnxt *bp = dev->data->dev_private;
3032 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
3033 struct bnxt_filter_info *filter, *match;
3034 struct bnxt_vnic_info *vnic, *mvnic;
3037 if (filter_op == RTE_ETH_FILTER_NOP)
3040 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3043 switch (filter_op) {
3044 case RTE_ETH_FILTER_ADD:
3045 case RTE_ETH_FILTER_DELETE:
3047 filter = bnxt_get_unused_filter(bp);
3048 if (filter == NULL) {
3050 "Not enough resources for a new flow.\n");
3054 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3057 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3059 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3060 vnic = &bp->vnic_info[0];
3062 vnic = &bp->vnic_info[fdir->action.rx_queue];
3064 match = bnxt_match_fdir(bp, filter, &mvnic);
3065 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3066 if (match->dst_id == vnic->fw_vnic_id) {
3067 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3071 match->dst_id = vnic->fw_vnic_id;
3072 ret = bnxt_hwrm_set_ntuple_filter(bp,
3075 STAILQ_REMOVE(&mvnic->filter, match,
3076 bnxt_filter_info, next);
3077 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3079 "Filter with matching pattern exist\n");
3081 "Updated it to new destination q\n");
3085 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3086 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3091 if (filter_op == RTE_ETH_FILTER_ADD) {
3092 ret = bnxt_hwrm_set_ntuple_filter(bp,
3097 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3099 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3100 STAILQ_REMOVE(&vnic->filter, match,
3101 bnxt_filter_info, next);
3102 bnxt_free_filter(bp, match);
3103 filter->fw_l2_filter_id = -1;
3104 bnxt_free_filter(bp, filter);
3107 case RTE_ETH_FILTER_FLUSH:
3108 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3109 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3111 STAILQ_FOREACH(filter, &vnic->filter, next) {
3112 if (filter->filter_type ==
3113 HWRM_CFA_NTUPLE_FILTER) {
3115 bnxt_hwrm_clear_ntuple_filter(bp,
3117 STAILQ_REMOVE(&vnic->filter, filter,
3118 bnxt_filter_info, next);
3123 case RTE_ETH_FILTER_UPDATE:
3124 case RTE_ETH_FILTER_STATS:
3125 case RTE_ETH_FILTER_INFO:
3126 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3129 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3136 filter->fw_l2_filter_id = -1;
3137 bnxt_free_filter(bp, filter);
3142 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
3143 enum rte_filter_type filter_type,
3144 enum rte_filter_op filter_op, void *arg)
3148 ret = is_bnxt_in_error(dev->data->dev_private);
3152 switch (filter_type) {
3153 case RTE_ETH_FILTER_TUNNEL:
3155 "filter type: %d: To be implemented\n", filter_type);
3157 case RTE_ETH_FILTER_FDIR:
3158 ret = bnxt_fdir_filter(dev, filter_op, arg);
3160 case RTE_ETH_FILTER_NTUPLE:
3161 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3163 case RTE_ETH_FILTER_ETHERTYPE:
3164 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3166 case RTE_ETH_FILTER_GENERIC:
3167 if (filter_op != RTE_ETH_FILTER_GET)
3169 *(const void **)arg = &bnxt_flow_ops;
3173 "Filter type (%d) not supported", filter_type);
3180 static const uint32_t *
3181 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3183 static const uint32_t ptypes[] = {
3184 RTE_PTYPE_L2_ETHER_VLAN,
3185 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3186 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3190 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3191 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3192 RTE_PTYPE_INNER_L4_ICMP,
3193 RTE_PTYPE_INNER_L4_TCP,
3194 RTE_PTYPE_INNER_L4_UDP,
3198 if (!dev->rx_pkt_burst)
3204 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3207 uint32_t reg_base = *reg_arr & 0xfffff000;
3211 for (i = 0; i < count; i++) {
3212 if ((reg_arr[i] & 0xfffff000) != reg_base)
3215 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3216 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3220 static int bnxt_map_ptp_regs(struct bnxt *bp)
3222 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3226 reg_arr = ptp->rx_regs;
3227 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3231 reg_arr = ptp->tx_regs;
3232 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3236 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3237 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3239 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3240 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3245 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3247 rte_write32(0, (uint8_t *)bp->bar0 +
3248 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3249 rte_write32(0, (uint8_t *)bp->bar0 +
3250 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3253 static uint64_t bnxt_cc_read(struct bnxt *bp)
3257 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3258 BNXT_GRCPF_REG_SYNC_TIME));
3259 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3260 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3264 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3266 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3269 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3270 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3271 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3274 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3275 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3276 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3277 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3278 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3279 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3284 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3286 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3287 struct bnxt_pf_info *pf = &bp->pf;
3294 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3295 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3296 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3299 port_id = pf->port_id;
3300 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3301 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3303 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3304 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3305 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3306 /* bnxt_clr_rx_ts(bp); TBD */
3310 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3311 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3312 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3313 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3319 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3322 struct bnxt *bp = dev->data->dev_private;
3323 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3328 ns = rte_timespec_to_ns(ts);
3329 /* Set the timecounters to a new value. */
3336 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3338 struct bnxt *bp = dev->data->dev_private;
3339 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3340 uint64_t ns, systime_cycles = 0;
3346 if (BNXT_CHIP_THOR(bp))
3347 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3350 systime_cycles = bnxt_cc_read(bp);
3352 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3353 *ts = rte_ns_to_timespec(ns);
3358 bnxt_timesync_enable(struct rte_eth_dev *dev)
3360 struct bnxt *bp = dev->data->dev_private;
3361 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3369 ptp->tx_tstamp_en = 1;
3370 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3372 rc = bnxt_hwrm_ptp_cfg(bp);
3376 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3377 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3378 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3380 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3381 ptp->tc.cc_shift = shift;
3382 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3384 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3385 ptp->rx_tstamp_tc.cc_shift = shift;
3386 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3388 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3389 ptp->tx_tstamp_tc.cc_shift = shift;
3390 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3392 if (!BNXT_CHIP_THOR(bp))
3393 bnxt_map_ptp_regs(bp);
3399 bnxt_timesync_disable(struct rte_eth_dev *dev)
3401 struct bnxt *bp = dev->data->dev_private;
3402 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3408 ptp->tx_tstamp_en = 0;
3411 bnxt_hwrm_ptp_cfg(bp);
3413 if (!BNXT_CHIP_THOR(bp))
3414 bnxt_unmap_ptp_regs(bp);
3420 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3421 struct timespec *timestamp,
3422 uint32_t flags __rte_unused)
3424 struct bnxt *bp = dev->data->dev_private;
3425 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3426 uint64_t rx_tstamp_cycles = 0;
3432 if (BNXT_CHIP_THOR(bp))
3433 rx_tstamp_cycles = ptp->rx_timestamp;
3435 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3437 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3438 *timestamp = rte_ns_to_timespec(ns);
3443 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3444 struct timespec *timestamp)
3446 struct bnxt *bp = dev->data->dev_private;
3447 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3448 uint64_t tx_tstamp_cycles = 0;
3455 if (BNXT_CHIP_THOR(bp))
3456 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3459 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3461 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3462 *timestamp = rte_ns_to_timespec(ns);
3468 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3470 struct bnxt *bp = dev->data->dev_private;
3471 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3476 ptp->tc.nsec += delta;
3482 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3484 struct bnxt *bp = dev->data->dev_private;
3486 uint32_t dir_entries;
3487 uint32_t entry_length;
3489 rc = is_bnxt_in_error(bp);
3493 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3494 bp->pdev->addr.domain, bp->pdev->addr.bus,
3495 bp->pdev->addr.devid, bp->pdev->addr.function);
3497 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3501 return dir_entries * entry_length;
3505 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3506 struct rte_dev_eeprom_info *in_eeprom)
3508 struct bnxt *bp = dev->data->dev_private;
3513 rc = is_bnxt_in_error(bp);
3517 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3518 "len = %d\n", bp->pdev->addr.domain,
3519 bp->pdev->addr.bus, bp->pdev->addr.devid,
3520 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3522 if (in_eeprom->offset == 0) /* special offset value to get directory */
3523 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3526 index = in_eeprom->offset >> 24;
3527 offset = in_eeprom->offset & 0xffffff;
3530 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3531 in_eeprom->length, in_eeprom->data);
3536 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3539 case BNX_DIR_TYPE_CHIMP_PATCH:
3540 case BNX_DIR_TYPE_BOOTCODE:
3541 case BNX_DIR_TYPE_BOOTCODE_2:
3542 case BNX_DIR_TYPE_APE_FW:
3543 case BNX_DIR_TYPE_APE_PATCH:
3544 case BNX_DIR_TYPE_KONG_FW:
3545 case BNX_DIR_TYPE_KONG_PATCH:
3546 case BNX_DIR_TYPE_BONO_FW:
3547 case BNX_DIR_TYPE_BONO_PATCH:
3555 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3558 case BNX_DIR_TYPE_AVS:
3559 case BNX_DIR_TYPE_EXP_ROM_MBA:
3560 case BNX_DIR_TYPE_PCIE:
3561 case BNX_DIR_TYPE_TSCF_UCODE:
3562 case BNX_DIR_TYPE_EXT_PHY:
3563 case BNX_DIR_TYPE_CCM:
3564 case BNX_DIR_TYPE_ISCSI_BOOT:
3565 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3566 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3574 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3576 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3577 bnxt_dir_type_is_other_exec_format(dir_type);
3581 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3582 struct rte_dev_eeprom_info *in_eeprom)
3584 struct bnxt *bp = dev->data->dev_private;
3585 uint8_t index, dir_op;
3586 uint16_t type, ext, ordinal, attr;
3589 rc = is_bnxt_in_error(bp);
3593 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3594 "len = %d\n", bp->pdev->addr.domain,
3595 bp->pdev->addr.bus, bp->pdev->addr.devid,
3596 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3599 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3603 type = in_eeprom->magic >> 16;
3605 if (type == 0xffff) { /* special value for directory operations */
3606 index = in_eeprom->magic & 0xff;
3607 dir_op = in_eeprom->magic >> 8;
3611 case 0x0e: /* erase */
3612 if (in_eeprom->offset != ~in_eeprom->magic)
3614 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3620 /* Create or re-write an NVM item: */
3621 if (bnxt_dir_type_is_executable(type) == true)
3623 ext = in_eeprom->magic & 0xffff;
3624 ordinal = in_eeprom->offset >> 16;
3625 attr = in_eeprom->offset & 0xffff;
3627 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3628 in_eeprom->data, in_eeprom->length);
3635 static const struct eth_dev_ops bnxt_dev_ops = {
3636 .dev_infos_get = bnxt_dev_info_get_op,
3637 .dev_close = bnxt_dev_close_op,
3638 .dev_configure = bnxt_dev_configure_op,
3639 .dev_start = bnxt_dev_start_op,
3640 .dev_stop = bnxt_dev_stop_op,
3641 .dev_set_link_up = bnxt_dev_set_link_up_op,
3642 .dev_set_link_down = bnxt_dev_set_link_down_op,
3643 .stats_get = bnxt_stats_get_op,
3644 .stats_reset = bnxt_stats_reset_op,
3645 .rx_queue_setup = bnxt_rx_queue_setup_op,
3646 .rx_queue_release = bnxt_rx_queue_release_op,
3647 .tx_queue_setup = bnxt_tx_queue_setup_op,
3648 .tx_queue_release = bnxt_tx_queue_release_op,
3649 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3650 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3651 .reta_update = bnxt_reta_update_op,
3652 .reta_query = bnxt_reta_query_op,
3653 .rss_hash_update = bnxt_rss_hash_update_op,
3654 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3655 .link_update = bnxt_link_update_op,
3656 .promiscuous_enable = bnxt_promiscuous_enable_op,
3657 .promiscuous_disable = bnxt_promiscuous_disable_op,
3658 .allmulticast_enable = bnxt_allmulticast_enable_op,
3659 .allmulticast_disable = bnxt_allmulticast_disable_op,
3660 .mac_addr_add = bnxt_mac_addr_add_op,
3661 .mac_addr_remove = bnxt_mac_addr_remove_op,
3662 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3663 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3664 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3665 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3666 .vlan_filter_set = bnxt_vlan_filter_set_op,
3667 .vlan_offload_set = bnxt_vlan_offload_set_op,
3668 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3669 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3670 .mtu_set = bnxt_mtu_set_op,
3671 .mac_addr_set = bnxt_set_default_mac_addr_op,
3672 .xstats_get = bnxt_dev_xstats_get_op,
3673 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3674 .xstats_reset = bnxt_dev_xstats_reset_op,
3675 .fw_version_get = bnxt_fw_version_get,
3676 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3677 .rxq_info_get = bnxt_rxq_info_get_op,
3678 .txq_info_get = bnxt_txq_info_get_op,
3679 .dev_led_on = bnxt_dev_led_on_op,
3680 .dev_led_off = bnxt_dev_led_off_op,
3681 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3682 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3683 .rx_queue_count = bnxt_rx_queue_count_op,
3684 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3685 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3686 .rx_queue_start = bnxt_rx_queue_start,
3687 .rx_queue_stop = bnxt_rx_queue_stop,
3688 .tx_queue_start = bnxt_tx_queue_start,
3689 .tx_queue_stop = bnxt_tx_queue_stop,
3690 .filter_ctrl = bnxt_filter_ctrl_op,
3691 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3692 .get_eeprom_length = bnxt_get_eeprom_length_op,
3693 .get_eeprom = bnxt_get_eeprom_op,
3694 .set_eeprom = bnxt_set_eeprom_op,
3695 .timesync_enable = bnxt_timesync_enable,
3696 .timesync_disable = bnxt_timesync_disable,
3697 .timesync_read_time = bnxt_timesync_read_time,
3698 .timesync_write_time = bnxt_timesync_write_time,
3699 .timesync_adjust_time = bnxt_timesync_adjust_time,
3700 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3701 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3704 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3708 /* Only pre-map the reset GRC registers using window 3 */
3709 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3710 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3712 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3717 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3719 struct bnxt_error_recovery_info *info = bp->recovery_info;
3720 uint32_t reg_base = 0xffffffff;
3723 /* Only pre-map the monitoring GRC registers using window 2 */
3724 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3725 uint32_t reg = info->status_regs[i];
3727 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3730 if (reg_base == 0xffffffff)
3731 reg_base = reg & 0xfffff000;
3732 if ((reg & 0xfffff000) != reg_base)
3735 /* Use mask 0xffc as the Lower 2 bits indicates
3736 * address space location
3738 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3742 if (reg_base == 0xffffffff)
3745 rte_write32(reg_base, (uint8_t *)bp->bar0 +
3746 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3751 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3753 struct bnxt_error_recovery_info *info = bp->recovery_info;
3754 uint32_t delay = info->delay_after_reset[index];
3755 uint32_t val = info->reset_reg_val[index];
3756 uint32_t reg = info->reset_reg[index];
3757 uint32_t type, offset;
3759 type = BNXT_FW_STATUS_REG_TYPE(reg);
3760 offset = BNXT_FW_STATUS_REG_OFF(reg);
3763 case BNXT_FW_STATUS_REG_TYPE_CFG:
3764 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3766 case BNXT_FW_STATUS_REG_TYPE_GRC:
3767 offset = bnxt_map_reset_regs(bp, offset);
3768 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3770 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3771 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3774 /* wait on a specific interval of time until core reset is complete */
3776 rte_delay_ms(delay);
3779 static void bnxt_dev_cleanup(struct bnxt *bp)
3781 bnxt_set_hwrm_link_config(bp, false);
3782 bp->link_info.link_up = 0;
3783 if (bp->dev_stopped == 0)
3784 bnxt_dev_stop_op(bp->eth_dev);
3786 bnxt_uninit_resources(bp, true);
3789 static int bnxt_restore_filters(struct bnxt *bp)
3791 struct rte_eth_dev *dev = bp->eth_dev;
3794 if (dev->data->all_multicast)
3795 ret = bnxt_allmulticast_enable_op(dev);
3796 if (dev->data->promiscuous)
3797 ret = bnxt_promiscuous_enable_op(dev);
3799 /* TODO restore other filters as well */
3803 static void bnxt_dev_recover(void *arg)
3805 struct bnxt *bp = arg;
3806 int timeout = bp->fw_reset_max_msecs;
3809 /* Clear Error flag so that device re-init should happen */
3810 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3813 rc = bnxt_hwrm_ver_get(bp);
3816 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3817 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3818 } while (rc && timeout);
3821 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3825 rc = bnxt_init_resources(bp, true);
3828 "Failed to initialize resources after reset\n");
3831 /* clear reset flag as the device is initialized now */
3832 bp->flags &= ~BNXT_FLAG_FW_RESET;
3834 rc = bnxt_dev_start_op(bp->eth_dev);
3836 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3840 rc = bnxt_restore_filters(bp);
3844 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3847 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3848 bnxt_uninit_resources(bp, false);
3849 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3852 void bnxt_dev_reset_and_resume(void *arg)
3854 struct bnxt *bp = arg;
3857 bnxt_dev_cleanup(bp);
3859 bnxt_wait_for_device_shutdown(bp);
3861 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3862 bnxt_dev_recover, (void *)bp);
3864 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3867 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3869 struct bnxt_error_recovery_info *info = bp->recovery_info;
3870 uint32_t reg = info->status_regs[index];
3871 uint32_t type, offset, val = 0;
3873 type = BNXT_FW_STATUS_REG_TYPE(reg);
3874 offset = BNXT_FW_STATUS_REG_OFF(reg);
3877 case BNXT_FW_STATUS_REG_TYPE_CFG:
3878 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3880 case BNXT_FW_STATUS_REG_TYPE_GRC:
3881 offset = info->mapped_status_regs[index];
3883 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3884 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3892 static int bnxt_fw_reset_all(struct bnxt *bp)
3894 struct bnxt_error_recovery_info *info = bp->recovery_info;
3898 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3899 /* Reset through master function driver */
3900 for (i = 0; i < info->reg_array_cnt; i++)
3901 bnxt_write_fw_reset_reg(bp, i);
3902 /* Wait for time specified by FW after triggering reset */
3903 rte_delay_ms(info->master_func_wait_period_after_reset);
3904 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3905 /* Reset with the help of Kong processor */
3906 rc = bnxt_hwrm_fw_reset(bp);
3908 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3914 static void bnxt_fw_reset_cb(void *arg)
3916 struct bnxt *bp = arg;
3917 struct bnxt_error_recovery_info *info = bp->recovery_info;
3920 /* Only Master function can do FW reset */
3921 if (bnxt_is_master_func(bp) &&
3922 bnxt_is_recovery_enabled(bp)) {
3923 rc = bnxt_fw_reset_all(bp);
3925 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3930 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3931 * EXCEPTION_FATAL_ASYNC event to all the functions
3932 * (including MASTER FUNC). After receiving this Async, all the active
3933 * drivers should treat this case as FW initiated recovery
3935 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3936 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3937 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3939 /* To recover from error */
3940 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3945 /* Driver should poll FW heartbeat, reset_counter with the frequency
3946 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3947 * When the driver detects heartbeat stop or change in reset_counter,
3948 * it has to trigger a reset to recover from the error condition.
3949 * A “master PF” is the function who will have the privilege to
3950 * initiate the chimp reset. The master PF will be elected by the
3951 * firmware and will be notified through async message.
3953 static void bnxt_check_fw_health(void *arg)
3955 struct bnxt *bp = arg;
3956 struct bnxt_error_recovery_info *info = bp->recovery_info;
3957 uint32_t val = 0, wait_msec;
3959 if (!info || !bnxt_is_recovery_enabled(bp) ||
3960 is_bnxt_in_error(bp))
3963 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3964 if (val == info->last_heart_beat)
3967 info->last_heart_beat = val;
3969 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3970 if (val != info->last_reset_counter)
3973 info->last_reset_counter = val;
3975 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3976 bnxt_check_fw_health, (void *)bp);
3980 /* Stop DMA to/from device */
3981 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3982 bp->flags |= BNXT_FLAG_FW_RESET;
3984 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
3986 if (bnxt_is_master_func(bp))
3987 wait_msec = info->master_func_wait_period;
3989 wait_msec = info->normal_func_wait_period;
3991 rte_eal_alarm_set(US_PER_MS * wait_msec,
3992 bnxt_fw_reset_cb, (void *)bp);
3995 void bnxt_schedule_fw_health_check(struct bnxt *bp)
3997 uint32_t polling_freq;
3999 if (!bnxt_is_recovery_enabled(bp))
4002 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4005 polling_freq = bp->recovery_info->driver_polling_freq;
4007 rte_eal_alarm_set(US_PER_MS * polling_freq,
4008 bnxt_check_fw_health, (void *)bp);
4009 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4012 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4014 if (!bnxt_is_recovery_enabled(bp))
4017 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4018 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4021 static bool bnxt_vf_pciid(uint16_t id)
4023 if (id == BROADCOM_DEV_ID_57304_VF ||
4024 id == BROADCOM_DEV_ID_57406_VF ||
4025 id == BROADCOM_DEV_ID_5731X_VF ||
4026 id == BROADCOM_DEV_ID_5741X_VF ||
4027 id == BROADCOM_DEV_ID_57414_VF ||
4028 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
4029 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
4030 id == BROADCOM_DEV_ID_58802_VF ||
4031 id == BROADCOM_DEV_ID_57500_VF1 ||
4032 id == BROADCOM_DEV_ID_57500_VF2)
4037 static bool bnxt_thor_device(uint16_t id)
4039 if (id == BROADCOM_DEV_ID_57508 ||
4040 id == BROADCOM_DEV_ID_57504 ||
4041 id == BROADCOM_DEV_ID_57502 ||
4042 id == BROADCOM_DEV_ID_57508_MF1 ||
4043 id == BROADCOM_DEV_ID_57504_MF1 ||
4044 id == BROADCOM_DEV_ID_57502_MF1 ||
4045 id == BROADCOM_DEV_ID_57508_MF2 ||
4046 id == BROADCOM_DEV_ID_57504_MF2 ||
4047 id == BROADCOM_DEV_ID_57502_MF2 ||
4048 id == BROADCOM_DEV_ID_57500_VF1 ||
4049 id == BROADCOM_DEV_ID_57500_VF2)
4055 bool bnxt_stratus_device(struct bnxt *bp)
4057 uint16_t id = bp->pdev->id.device_id;
4059 if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
4060 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
4061 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
4066 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4068 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4069 struct bnxt *bp = eth_dev->data->dev_private;
4071 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4072 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4073 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4074 if (!bp->bar0 || !bp->doorbell_base) {
4075 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4079 bp->eth_dev = eth_dev;
4085 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
4086 struct bnxt_ctx_pg_info *ctx_pg,
4091 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4092 const struct rte_memzone *mz = NULL;
4093 char mz_name[RTE_MEMZONE_NAMESIZE];
4094 rte_iova_t mz_phys_addr;
4095 uint64_t valid_bits = 0;
4102 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4104 rmem->page_size = BNXT_PAGE_SIZE;
4105 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4106 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4107 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4109 valid_bits = PTU_PTE_VALID;
4111 if (rmem->nr_pages > 1) {
4112 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4113 "bnxt_ctx_pg_tbl%s_%x_%d",
4114 suffix, idx, bp->eth_dev->data->port_id);
4115 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4116 mz = rte_memzone_lookup(mz_name);
4118 mz = rte_memzone_reserve_aligned(mz_name,
4122 RTE_MEMZONE_SIZE_HINT_ONLY |
4123 RTE_MEMZONE_IOVA_CONTIG,
4129 memset(mz->addr, 0, mz->len);
4130 mz_phys_addr = mz->iova;
4131 if ((unsigned long)mz->addr == mz_phys_addr) {
4133 "physical address same as virtual\n");
4134 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4135 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4136 if (mz_phys_addr == RTE_BAD_IOVA) {
4138 "unable to map addr to phys memory\n");
4142 rte_mem_lock_page(((char *)mz->addr));
4144 rmem->pg_tbl = mz->addr;
4145 rmem->pg_tbl_map = mz_phys_addr;
4146 rmem->pg_tbl_mz = mz;
4149 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4150 suffix, idx, bp->eth_dev->data->port_id);
4151 mz = rte_memzone_lookup(mz_name);
4153 mz = rte_memzone_reserve_aligned(mz_name,
4157 RTE_MEMZONE_SIZE_HINT_ONLY |
4158 RTE_MEMZONE_IOVA_CONTIG,
4164 memset(mz->addr, 0, mz->len);
4165 mz_phys_addr = mz->iova;
4166 if ((unsigned long)mz->addr == mz_phys_addr) {
4168 "Memzone physical address same as virtual.\n");
4169 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4170 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
4171 rte_mem_lock_page(((char *)mz->addr) + sz);
4172 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4173 if (mz_phys_addr == RTE_BAD_IOVA) {
4175 "unable to map addr to phys memory\n");
4180 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4181 rte_mem_lock_page(((char *)mz->addr) + sz);
4182 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4183 rmem->dma_arr[i] = mz_phys_addr + sz;
4185 if (rmem->nr_pages > 1) {
4186 if (i == rmem->nr_pages - 2 &&
4187 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4188 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4189 else if (i == rmem->nr_pages - 1 &&
4190 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4191 valid_bits |= PTU_PTE_LAST;
4193 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4199 if (rmem->vmem_size)
4200 rmem->vmem = (void **)mz->addr;
4201 rmem->dma_arr[0] = mz_phys_addr;
4205 static void bnxt_free_ctx_mem(struct bnxt *bp)
4209 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4212 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4213 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4214 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4215 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4216 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4217 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4218 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4219 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4220 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4221 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4222 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4224 for (i = 0; i < BNXT_MAX_Q; i++) {
4225 if (bp->ctx->tqm_mem[i])
4226 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4233 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4235 #define min_t(type, x, y) ({ \
4236 type __min1 = (x); \
4237 type __min2 = (y); \
4238 __min1 < __min2 ? __min1 : __min2; })
4240 #define max_t(type, x, y) ({ \
4241 type __max1 = (x); \
4242 type __max2 = (y); \
4243 __max1 > __max2 ? __max1 : __max2; })
4245 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4247 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4249 struct bnxt_ctx_pg_info *ctx_pg;
4250 struct bnxt_ctx_mem_info *ctx;
4251 uint32_t mem_size, ena, entries;
4254 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4256 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4260 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4263 ctx_pg = &ctx->qp_mem;
4264 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4265 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4266 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4270 ctx_pg = &ctx->srq_mem;
4271 ctx_pg->entries = ctx->srq_max_l2_entries;
4272 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4273 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4277 ctx_pg = &ctx->cq_mem;
4278 ctx_pg->entries = ctx->cq_max_l2_entries;
4279 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4280 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4284 ctx_pg = &ctx->vnic_mem;
4285 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4286 ctx->vnic_max_ring_table_entries;
4287 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4288 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4292 ctx_pg = &ctx->stat_mem;
4293 ctx_pg->entries = ctx->stat_max_entries;
4294 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4295 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4299 entries = ctx->qp_max_l2_entries +
4300 ctx->vnic_max_vnic_entries +
4301 ctx->tqm_min_entries_per_ring;
4302 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4303 entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4304 ctx->tqm_max_entries_per_ring);
4305 for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4306 ctx_pg = ctx->tqm_mem[i];
4307 /* use min tqm entries for now. */
4308 ctx_pg->entries = entries;
4309 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4310 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4313 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4316 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4317 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4320 "Failed to configure context mem: rc = %d\n", rc);
4322 ctx->flags |= BNXT_CTX_FLAG_INITED;
4327 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4329 struct rte_pci_device *pci_dev = bp->pdev;
4330 char mz_name[RTE_MEMZONE_NAMESIZE];
4331 const struct rte_memzone *mz = NULL;
4332 uint32_t total_alloc_len;
4333 rte_iova_t mz_phys_addr;
4335 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4338 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4339 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4340 pci_dev->addr.bus, pci_dev->addr.devid,
4341 pci_dev->addr.function, "rx_port_stats");
4342 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4343 mz = rte_memzone_lookup(mz_name);
4345 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4346 sizeof(struct rx_port_stats_ext) + 512);
4348 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4351 RTE_MEMZONE_SIZE_HINT_ONLY |
4352 RTE_MEMZONE_IOVA_CONTIG);
4356 memset(mz->addr, 0, mz->len);
4357 mz_phys_addr = mz->iova;
4358 if ((unsigned long)mz->addr == mz_phys_addr) {
4360 "Memzone physical address same as virtual.\n");
4362 "Using rte_mem_virt2iova()\n");
4363 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4364 if (mz_phys_addr == RTE_BAD_IOVA) {
4366 "Can't map address to physical memory\n");
4371 bp->rx_mem_zone = (const void *)mz;
4372 bp->hw_rx_port_stats = mz->addr;
4373 bp->hw_rx_port_stats_map = mz_phys_addr;
4375 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4376 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4377 pci_dev->addr.bus, pci_dev->addr.devid,
4378 pci_dev->addr.function, "tx_port_stats");
4379 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4380 mz = rte_memzone_lookup(mz_name);
4382 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4383 sizeof(struct tx_port_stats_ext) + 512);
4385 mz = rte_memzone_reserve(mz_name,
4389 RTE_MEMZONE_SIZE_HINT_ONLY |
4390 RTE_MEMZONE_IOVA_CONTIG);
4394 memset(mz->addr, 0, mz->len);
4395 mz_phys_addr = mz->iova;
4396 if ((unsigned long)mz->addr == mz_phys_addr) {
4398 "Memzone physical address same as virtual\n");
4399 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4400 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4401 if (mz_phys_addr == RTE_BAD_IOVA) {
4403 "Can't map address to physical memory\n");
4408 bp->tx_mem_zone = (const void *)mz;
4409 bp->hw_tx_port_stats = mz->addr;
4410 bp->hw_tx_port_stats_map = mz_phys_addr;
4411 bp->flags |= BNXT_FLAG_PORT_STATS;
4413 /* Display extended statistics if FW supports it */
4414 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4415 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4416 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4419 bp->hw_rx_port_stats_ext = (void *)
4420 ((uint8_t *)bp->hw_rx_port_stats +
4421 sizeof(struct rx_port_stats));
4422 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4423 sizeof(struct rx_port_stats);
4424 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4426 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4427 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4428 bp->hw_tx_port_stats_ext = (void *)
4429 ((uint8_t *)bp->hw_tx_port_stats +
4430 sizeof(struct tx_port_stats));
4431 bp->hw_tx_port_stats_ext_map =
4432 bp->hw_tx_port_stats_map +
4433 sizeof(struct tx_port_stats);
4434 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4440 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4442 struct bnxt *bp = eth_dev->data->dev_private;
4445 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4446 RTE_ETHER_ADDR_LEN *
4449 if (eth_dev->data->mac_addrs == NULL) {
4450 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4454 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4458 /* Generate a random MAC address, if none was assigned by PF */
4459 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4460 bnxt_eth_hw_addr_random(bp->mac_addr);
4462 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4463 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4464 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4466 rc = bnxt_hwrm_set_mac(bp);
4468 memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4469 RTE_ETHER_ADDR_LEN);
4473 /* Copy the permanent MAC from the FUNC_QCAPS response */
4474 memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4475 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4480 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4484 /* MAC is already configured in FW */
4485 if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4488 /* Restore the old MAC configured */
4489 rc = bnxt_hwrm_set_mac(bp);
4491 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4496 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4501 #define ALLOW_FUNC(x) \
4503 uint32_t arg = (x); \
4504 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4505 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4508 /* Forward all requests if firmware is new enough */
4509 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4510 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4511 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4512 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4514 PMD_DRV_LOG(WARNING,
4515 "Firmware too old for VF mailbox functionality\n");
4516 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4520 * The following are used for driver cleanup. If we disallow these,
4521 * VF drivers can't clean up cleanly.
4523 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4524 ALLOW_FUNC(HWRM_VNIC_FREE);
4525 ALLOW_FUNC(HWRM_RING_FREE);
4526 ALLOW_FUNC(HWRM_RING_GRP_FREE);
4527 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4528 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4529 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4530 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4531 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4534 static int bnxt_init_fw(struct bnxt *bp)
4539 rc = bnxt_hwrm_ver_get(bp);
4543 rc = bnxt_hwrm_func_reset(bp);
4547 rc = bnxt_hwrm_vnic_qcaps(bp);
4551 rc = bnxt_hwrm_queue_qportcfg(bp);
4555 /* Get the MAX capabilities for this function.
4556 * This function also allocates context memory for TQM rings and
4557 * informs the firmware about this allocated backing store memory.
4559 rc = bnxt_hwrm_func_qcaps(bp);
4563 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4567 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4571 /* Get the adapter error recovery support info */
4572 rc = bnxt_hwrm_error_recovery_qcfg(bp);
4574 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
4576 if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
4577 mtu != bp->eth_dev->data->mtu)
4578 bp->eth_dev->data->mtu = mtu;
4580 bnxt_hwrm_port_led_qcaps(bp);
4586 bnxt_init_locks(struct bnxt *bp)
4590 err = pthread_mutex_init(&bp->flow_lock, NULL);
4592 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4596 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4598 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4602 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4606 rc = bnxt_init_fw(bp);
4610 if (!reconfig_dev) {
4611 rc = bnxt_setup_mac_addr(bp->eth_dev);
4615 rc = bnxt_restore_dflt_mac(bp);
4620 bnxt_config_vf_req_fwd(bp);
4622 rc = bnxt_hwrm_func_driver_register(bp);
4624 PMD_DRV_LOG(ERR, "Failed to register driver");
4629 if (bp->pdev->max_vfs) {
4630 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4632 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4636 rc = bnxt_hwrm_allocate_pf_only(bp);
4639 "Failed to allocate PF resources");
4645 rc = bnxt_alloc_mem(bp, reconfig_dev);
4649 rc = bnxt_setup_int(bp);
4653 rc = bnxt_request_int(bp);
4657 rc = bnxt_init_locks(bp);
4665 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4667 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4668 static int version_printed;
4672 if (version_printed++ == 0)
4673 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4675 eth_dev->dev_ops = &bnxt_dev_ops;
4676 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4677 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4680 * For secondary processes, we don't initialise any further
4681 * as primary has already done this work.
4683 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4686 rte_eth_copy_pci_info(eth_dev, pci_dev);
4688 bp = eth_dev->data->dev_private;
4690 bp->dev_stopped = 1;
4692 if (bnxt_vf_pciid(pci_dev->id.device_id))
4693 bp->flags |= BNXT_FLAG_VF;
4695 if (bnxt_thor_device(pci_dev->id.device_id))
4696 bp->flags |= BNXT_FLAG_THOR_CHIP;
4698 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4699 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4700 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4701 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4702 bp->flags |= BNXT_FLAG_STINGRAY;
4704 rc = bnxt_init_board(eth_dev);
4707 "Failed to initialize board rc: %x\n", rc);
4711 rc = bnxt_alloc_hwrm_resources(bp);
4714 "Failed to allocate hwrm resource rc: %x\n", rc);
4717 rc = bnxt_init_resources(bp, false);
4721 rc = bnxt_alloc_stats_mem(bp);
4726 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4727 pci_dev->mem_resource[0].phys_addr,
4728 pci_dev->mem_resource[0].addr);
4733 bnxt_dev_uninit(eth_dev);
4738 bnxt_uninit_locks(struct bnxt *bp)
4740 pthread_mutex_destroy(&bp->flow_lock);
4741 pthread_mutex_destroy(&bp->def_cp_lock);
4745 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4750 bnxt_free_mem(bp, reconfig_dev);
4751 bnxt_hwrm_func_buf_unrgtr(bp);
4752 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4753 bp->flags &= ~BNXT_FLAG_REGISTERED;
4754 bnxt_free_ctx_mem(bp);
4755 if (!reconfig_dev) {
4756 bnxt_free_hwrm_resources(bp);
4758 if (bp->recovery_info != NULL) {
4759 rte_free(bp->recovery_info);
4760 bp->recovery_info = NULL;
4764 bnxt_uninit_locks(bp);
4765 rte_free(bp->ptp_cfg);
4771 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4773 struct bnxt *bp = eth_dev->data->dev_private;
4776 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4779 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4781 rc = bnxt_uninit_resources(bp, false);
4783 if (bp->tx_mem_zone) {
4784 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4785 bp->tx_mem_zone = NULL;
4788 if (bp->rx_mem_zone) {
4789 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4790 bp->rx_mem_zone = NULL;
4793 if (bp->dev_stopped == 0)
4794 bnxt_dev_close_op(eth_dev);
4796 rte_free(bp->pf.vf_info);
4797 eth_dev->dev_ops = NULL;
4798 eth_dev->rx_pkt_burst = NULL;
4799 eth_dev->tx_pkt_burst = NULL;
4804 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4805 struct rte_pci_device *pci_dev)
4807 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4811 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4813 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4814 return rte_eth_dev_pci_generic_remove(pci_dev,
4817 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4820 static struct rte_pci_driver bnxt_rte_pmd = {
4821 .id_table = bnxt_pci_id_map,
4822 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4823 .probe = bnxt_pci_probe,
4824 .remove = bnxt_pci_remove,
4828 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4830 if (strcmp(dev->device->driver->name, drv->driver.name))
4836 bool is_bnxt_supported(struct rte_eth_dev *dev)
4838 return is_device_supported(dev, &bnxt_rte_pmd);
4841 RTE_INIT(bnxt_init_log)
4843 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4844 if (bnxt_logtype_driver >= 0)
4845 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4848 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4849 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4850 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");