1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
20 #include "bnxt_ring.h"
23 #include "bnxt_stats.h"
26 #include "bnxt_vnic.h"
27 #include "hsi_struct_def_dpdk.h"
28 #include "bnxt_nvm_defs.h"
29 #include "bnxt_util.h"
31 #define DRV_MODULE_NAME "bnxt"
32 static const char bnxt_version[] =
33 "Broadcom NetXtreme driver " DRV_MODULE_NAME "\n";
34 int bnxt_logtype_driver;
36 #define PCI_VENDOR_ID_BROADCOM 0x14E4
38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
40 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
41 #define BROADCOM_DEV_ID_57414_VF 0x16c1
42 #define BROADCOM_DEV_ID_57301 0x16c8
43 #define BROADCOM_DEV_ID_57302 0x16c9
44 #define BROADCOM_DEV_ID_57304_PF 0x16ca
45 #define BROADCOM_DEV_ID_57304_VF 0x16cb
46 #define BROADCOM_DEV_ID_57417_MF 0x16cc
47 #define BROADCOM_DEV_ID_NS2 0x16cd
48 #define BROADCOM_DEV_ID_57311 0x16ce
49 #define BROADCOM_DEV_ID_57312 0x16cf
50 #define BROADCOM_DEV_ID_57402 0x16d0
51 #define BROADCOM_DEV_ID_57404 0x16d1
52 #define BROADCOM_DEV_ID_57406_PF 0x16d2
53 #define BROADCOM_DEV_ID_57406_VF 0x16d3
54 #define BROADCOM_DEV_ID_57402_MF 0x16d4
55 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
56 #define BROADCOM_DEV_ID_57412 0x16d6
57 #define BROADCOM_DEV_ID_57414 0x16d7
58 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
59 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
60 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
61 #define BROADCOM_DEV_ID_57412_MF 0x16de
62 #define BROADCOM_DEV_ID_57314 0x16df
63 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
64 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
65 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
66 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
67 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
68 #define BROADCOM_DEV_ID_57404_MF 0x16e7
69 #define BROADCOM_DEV_ID_57406_MF 0x16e8
70 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
71 #define BROADCOM_DEV_ID_57407_MF 0x16ea
72 #define BROADCOM_DEV_ID_57414_MF 0x16ec
73 #define BROADCOM_DEV_ID_57416_MF 0x16ee
74 #define BROADCOM_DEV_ID_58802 0xd802
75 #define BROADCOM_DEV_ID_58804 0xd804
76 #define BROADCOM_DEV_ID_58808 0x16f0
77 #define BROADCOM_DEV_ID_58802_VF 0xd800
79 static const struct rte_pci_id bnxt_pci_id_map[] = {
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
81 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
83 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
98 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
122 { .vendor_id = 0, /* sentinel */ },
125 #define BNXT_ETH_RSS_SUPPORT ( \
127 ETH_RSS_NONFRAG_IPV4_TCP | \
128 ETH_RSS_NONFRAG_IPV4_UDP | \
130 ETH_RSS_NONFRAG_IPV6_TCP | \
131 ETH_RSS_NONFRAG_IPV6_UDP)
133 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
134 DEV_TX_OFFLOAD_IPV4_CKSUM | \
135 DEV_TX_OFFLOAD_TCP_CKSUM | \
136 DEV_TX_OFFLOAD_UDP_CKSUM | \
137 DEV_TX_OFFLOAD_TCP_TSO | \
138 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
139 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
140 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
141 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
142 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
143 DEV_TX_OFFLOAD_MULTI_SEGS)
145 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
146 DEV_RX_OFFLOAD_VLAN_STRIP | \
147 DEV_RX_OFFLOAD_IPV4_CKSUM | \
148 DEV_RX_OFFLOAD_UDP_CKSUM | \
149 DEV_RX_OFFLOAD_TCP_CKSUM | \
150 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
151 DEV_RX_OFFLOAD_JUMBO_FRAME | \
152 DEV_RX_OFFLOAD_CRC_STRIP | \
153 DEV_RX_OFFLOAD_KEEP_CRC | \
154 DEV_RX_OFFLOAD_TCP_LRO)
156 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
157 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
158 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
159 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
161 /***********************/
164 * High level utility functions
167 static void bnxt_free_mem(struct bnxt *bp)
169 bnxt_free_filter_mem(bp);
170 bnxt_free_vnic_attributes(bp);
171 bnxt_free_vnic_mem(bp);
174 bnxt_free_tx_rings(bp);
175 bnxt_free_rx_rings(bp);
178 static int bnxt_alloc_mem(struct bnxt *bp)
182 rc = bnxt_alloc_vnic_mem(bp);
186 rc = bnxt_alloc_vnic_attributes(bp);
190 rc = bnxt_alloc_filter_mem(bp);
201 static int bnxt_init_chip(struct bnxt *bp)
203 struct bnxt_rx_queue *rxq;
204 struct rte_eth_link new;
205 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
206 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
207 uint32_t intr_vector = 0;
208 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
209 uint32_t vec = BNXT_MISC_VEC_ID;
213 /* disable uio/vfio intr/eventfd mapping */
214 rte_intr_disable(intr_handle);
216 if (bp->eth_dev->data->mtu > ETHER_MTU) {
217 bp->eth_dev->data->dev_conf.rxmode.offloads |=
218 DEV_RX_OFFLOAD_JUMBO_FRAME;
219 bp->flags |= BNXT_FLAG_JUMBO;
221 bp->eth_dev->data->dev_conf.rxmode.offloads &=
222 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
223 bp->flags &= ~BNXT_FLAG_JUMBO;
226 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
228 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
232 rc = bnxt_alloc_hwrm_rings(bp);
234 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
238 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
240 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
244 rc = bnxt_mq_rx_configure(bp);
246 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
250 /* VNIC configuration */
251 for (i = 0; i < bp->nr_vnics; i++) {
252 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
253 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
255 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
257 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
262 /* Alloc RSS context only if RSS mode is enabled */
263 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
264 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
267 "HWRM vnic %d ctx alloc failure rc: %x\n",
273 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
275 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
280 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
283 "HWRM vnic %d filter failure rc: %x\n",
288 for (j = 0; j < bp->rx_nr_rings; j++) {
289 rxq = bp->eth_dev->data->rx_queues[j];
291 if (rxq->rx_deferred_start)
292 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
295 rc = bnxt_vnic_rss_configure(bp, vnic);
298 "HWRM vnic set RSS failure rc: %x\n", rc);
302 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
304 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
305 DEV_RX_OFFLOAD_TCP_LRO)
306 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
308 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
310 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
313 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
317 /* check and configure queue intr-vector mapping */
318 if ((rte_intr_cap_multiple(intr_handle) ||
319 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
320 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
321 intr_vector = bp->eth_dev->data->nb_rx_queues;
322 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
323 if (intr_vector > bp->rx_cp_nr_rings) {
324 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
328 if (rte_intr_efd_enable(intr_handle, intr_vector))
332 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
333 intr_handle->intr_vec =
334 rte_zmalloc("intr_vec",
335 bp->eth_dev->data->nb_rx_queues *
337 if (intr_handle->intr_vec == NULL) {
338 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
339 " intr_vec", bp->eth_dev->data->nb_rx_queues);
342 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
343 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
344 intr_handle->intr_vec, intr_handle->nb_efd,
345 intr_handle->max_intr);
348 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
350 intr_handle->intr_vec[queue_id] = vec;
351 if (vec < base + intr_handle->nb_efd - 1)
355 /* enable uio/vfio intr/eventfd mapping */
356 rte_intr_enable(intr_handle);
358 rc = bnxt_get_hwrm_link_config(bp, &new);
360 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
364 if (!bp->link_info.link_up) {
365 rc = bnxt_set_hwrm_link_config(bp, true);
368 "HWRM link config failure rc: %x\n", rc);
372 bnxt_print_link_info(bp->eth_dev);
377 bnxt_free_all_hwrm_resources(bp);
379 /* Some of the error status returned by FW may not be from errno.h */
386 static int bnxt_shutdown_nic(struct bnxt *bp)
388 bnxt_free_all_hwrm_resources(bp);
389 bnxt_free_all_filters(bp);
390 bnxt_free_all_vnics(bp);
394 static int bnxt_init_nic(struct bnxt *bp)
398 rc = bnxt_init_ring_grps(bp);
403 bnxt_init_filters(bp);
409 * Device configuration and status function
412 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
413 struct rte_eth_dev_info *dev_info)
415 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
416 uint16_t max_vnics, i, j, vpool, vrxq;
417 unsigned int max_rx_rings;
420 dev_info->max_mac_addrs = bp->max_l2_ctx;
421 dev_info->max_hash_mac_addrs = 0;
423 /* PF/VF specifics */
425 dev_info->max_vfs = bp->pdev->max_vfs;
426 max_rx_rings = RTE_MIN(bp->max_vnics, bp->max_stat_ctx);
427 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
428 dev_info->max_rx_queues = max_rx_rings;
429 dev_info->max_tx_queues = max_rx_rings;
430 dev_info->reta_size = bp->max_rsscos_ctx;
431 dev_info->hash_key_size = 40;
432 max_vnics = bp->max_vnics;
434 /* Fast path specifics */
435 dev_info->min_rx_bufsize = 1;
436 dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
439 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
440 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
441 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
442 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
443 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
446 dev_info->default_rxconf = (struct rte_eth_rxconf) {
452 .rx_free_thresh = 32,
453 /* If no descriptors available, pkts are dropped by default */
457 dev_info->default_txconf = (struct rte_eth_txconf) {
463 .tx_free_thresh = 32,
466 eth_dev->data->dev_conf.intr_conf.lsc = 1;
468 eth_dev->data->dev_conf.intr_conf.rxq = 1;
469 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
470 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
471 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
472 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
477 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
478 * need further investigation.
482 vpool = 64; /* ETH_64_POOLS */
483 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
484 for (i = 0; i < 4; vpool >>= 1, i++) {
485 if (max_vnics > vpool) {
486 for (j = 0; j < 5; vrxq >>= 1, j++) {
487 if (dev_info->max_rx_queues > vrxq) {
493 /* Not enough resources to support VMDq */
497 /* Not enough resources to support VMDq */
501 dev_info->max_vmdq_pools = vpool;
502 dev_info->vmdq_queue_num = vrxq;
504 dev_info->vmdq_pool_base = 0;
505 dev_info->vmdq_queue_base = 0;
508 /* Configure the device based on the configuration provided */
509 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
511 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
512 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
514 bp->rx_queues = (void *)eth_dev->data->rx_queues;
515 bp->tx_queues = (void *)eth_dev->data->tx_queues;
516 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
517 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
519 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
522 rc = bnxt_hwrm_func_reserve_vf_resc(bp);
524 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
528 /* legacy driver needs to get updated values */
529 rc = bnxt_hwrm_func_qcaps(bp);
531 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
536 /* Inherit new configurations */
537 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
538 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
539 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
541 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
543 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps) {
545 "Insufficient resources to support requested config\n");
547 "Num Queues Requested: Tx %d, Rx %d\n",
548 eth_dev->data->nb_tx_queues,
549 eth_dev->data->nb_rx_queues);
551 "Res available: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d\n",
552 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
553 bp->max_stat_ctx, bp->max_ring_grps);
557 bp->rx_cp_nr_rings = bp->rx_nr_rings;
558 bp->tx_cp_nr_rings = bp->tx_nr_rings;
560 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
562 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
563 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE *
565 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
570 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
572 struct rte_eth_link *link = ð_dev->data->dev_link;
574 if (link->link_status)
575 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
576 eth_dev->data->port_id,
577 (uint32_t)link->link_speed,
578 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
579 ("full-duplex") : ("half-duplex\n"));
581 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
582 eth_dev->data->port_id);
585 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
587 bnxt_print_link_info(eth_dev);
591 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
593 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
594 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
598 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
600 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
601 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
605 rc = bnxt_init_chip(bp);
609 bnxt_link_update_op(eth_dev, 1);
611 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
612 vlan_mask |= ETH_VLAN_FILTER_MASK;
613 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
614 vlan_mask |= ETH_VLAN_STRIP_MASK;
615 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
619 bp->flags |= BNXT_FLAG_INIT_DONE;
623 bnxt_shutdown_nic(bp);
624 bnxt_free_tx_mbufs(bp);
625 bnxt_free_rx_mbufs(bp);
629 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
631 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
634 if (!bp->link_info.link_up)
635 rc = bnxt_set_hwrm_link_config(bp, true);
637 eth_dev->data->dev_link.link_status = 1;
639 bnxt_print_link_info(eth_dev);
643 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
645 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
647 eth_dev->data->dev_link.link_status = 0;
648 bnxt_set_hwrm_link_config(bp, false);
649 bp->link_info.link_up = 0;
654 /* Unload the driver, release resources */
655 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
657 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
659 bp->flags &= ~BNXT_FLAG_INIT_DONE;
660 if (bp->eth_dev->data->dev_started) {
661 /* TBD: STOP HW queues DMA */
662 eth_dev->data->dev_link.link_status = 0;
664 bnxt_set_hwrm_link_config(bp, false);
665 bnxt_hwrm_port_clr_stats(bp);
666 bnxt_free_tx_mbufs(bp);
667 bnxt_free_rx_mbufs(bp);
668 bnxt_shutdown_nic(bp);
672 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
674 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
676 if (bp->dev_stopped == 0)
677 bnxt_dev_stop_op(eth_dev);
680 if (eth_dev->data->mac_addrs != NULL) {
681 rte_free(eth_dev->data->mac_addrs);
682 eth_dev->data->mac_addrs = NULL;
684 if (bp->grp_info != NULL) {
685 rte_free(bp->grp_info);
689 bnxt_dev_uninit(eth_dev);
692 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
695 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
696 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
697 struct bnxt_vnic_info *vnic;
698 struct bnxt_filter_info *filter, *temp_filter;
699 uint32_t pool = RTE_MIN(MAX_FF_POOLS, ETH_64_POOLS);
703 * Loop through all VNICs from the specified filter flow pools to
704 * remove the corresponding MAC addr filter
706 for (i = 0; i < pool; i++) {
707 if (!(pool_mask & (1ULL << i)))
710 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
711 filter = STAILQ_FIRST(&vnic->filter);
713 temp_filter = STAILQ_NEXT(filter, next);
714 if (filter->mac_index == index) {
715 STAILQ_REMOVE(&vnic->filter, filter,
716 bnxt_filter_info, next);
717 bnxt_hwrm_clear_l2_filter(bp, filter);
718 filter->mac_index = INVALID_MAC_INDEX;
719 memset(&filter->l2_addr, 0,
722 &bp->free_filter_list,
725 filter = temp_filter;
731 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
732 struct ether_addr *mac_addr,
733 uint32_t index, uint32_t pool)
735 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
736 struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]);
737 struct bnxt_filter_info *filter;
740 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
745 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
748 /* Attach requested MAC address to the new l2_filter */
749 STAILQ_FOREACH(filter, &vnic->filter, next) {
750 if (filter->mac_index == index) {
752 "MAC addr already existed for pool %d\n", pool);
756 filter = bnxt_alloc_filter(bp);
758 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
761 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
762 filter->mac_index = index;
763 memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
764 return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
767 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
770 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
771 struct rte_eth_link new;
772 unsigned int cnt = BNXT_LINK_WAIT_CNT;
774 memset(&new, 0, sizeof(new));
776 /* Retrieve link info from hardware */
777 rc = bnxt_get_hwrm_link_config(bp, &new);
779 new.link_speed = ETH_LINK_SPEED_100M;
780 new.link_duplex = ETH_LINK_FULL_DUPLEX;
782 "Failed to retrieve link rc = 0x%x!\n", rc);
785 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
787 if (!wait_to_complete)
789 } while (!new.link_status && cnt--);
792 /* Timed out or success */
793 if (new.link_status != eth_dev->data->dev_link.link_status ||
794 new.link_speed != eth_dev->data->dev_link.link_speed) {
795 memcpy(ð_dev->data->dev_link, &new,
796 sizeof(struct rte_eth_link));
798 _rte_eth_dev_callback_process(eth_dev,
799 RTE_ETH_EVENT_INTR_LSC,
802 bnxt_print_link_info(eth_dev);
808 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
810 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
811 struct bnxt_vnic_info *vnic;
813 if (bp->vnic_info == NULL)
816 vnic = &bp->vnic_info[0];
818 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
819 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
822 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
824 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
825 struct bnxt_vnic_info *vnic;
827 if (bp->vnic_info == NULL)
830 vnic = &bp->vnic_info[0];
832 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
833 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
836 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
838 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
839 struct bnxt_vnic_info *vnic;
841 if (bp->vnic_info == NULL)
844 vnic = &bp->vnic_info[0];
846 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
847 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
850 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
852 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
853 struct bnxt_vnic_info *vnic;
855 if (bp->vnic_info == NULL)
858 vnic = &bp->vnic_info[0];
860 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
861 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
864 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
865 struct rte_eth_rss_reta_entry64 *reta_conf,
868 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
869 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
870 struct bnxt_vnic_info *vnic;
873 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
876 if (reta_size != HW_HASH_INDEX_SIZE) {
877 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
878 "(%d) must equal the size supported by the hardware "
879 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
882 /* Update the RSS VNIC(s) */
883 for (i = 0; i < MAX_FF_POOLS; i++) {
884 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
885 memcpy(vnic->rss_table, reta_conf, reta_size);
887 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
893 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
894 struct rte_eth_rss_reta_entry64 *reta_conf,
897 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
898 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
899 struct rte_intr_handle *intr_handle
900 = &bp->pdev->intr_handle;
902 /* Retrieve from the default VNIC */
905 if (!vnic->rss_table)
908 if (reta_size != HW_HASH_INDEX_SIZE) {
909 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
910 "(%d) must equal the size supported by the hardware "
911 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
914 /* EW - need to revisit here copying from uint64_t to uint16_t */
915 memcpy(reta_conf, vnic->rss_table, reta_size);
917 if (rte_intr_allow_others(intr_handle)) {
918 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
919 bnxt_dev_lsc_intr_setup(eth_dev);
925 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
926 struct rte_eth_rss_conf *rss_conf)
928 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
929 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
930 struct bnxt_vnic_info *vnic;
931 uint16_t hash_type = 0;
935 * If RSS enablement were different than dev_configure,
936 * then return -EINVAL
938 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
939 if (!rss_conf->rss_hf)
940 PMD_DRV_LOG(ERR, "Hash type NONE\n");
942 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
946 bp->flags |= BNXT_FLAG_UPDATE_HASH;
947 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
949 if (rss_conf->rss_hf & ETH_RSS_IPV4)
950 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
951 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
952 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
953 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
954 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
955 if (rss_conf->rss_hf & ETH_RSS_IPV6)
956 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
957 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
958 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
959 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
960 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
962 /* Update the RSS VNIC(s) */
963 for (i = 0; i < MAX_FF_POOLS; i++) {
964 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
965 vnic->hash_type = hash_type;
968 * Use the supplied key if the key length is
969 * acceptable and the rss_key is not NULL
971 if (rss_conf->rss_key &&
972 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
973 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
974 rss_conf->rss_key_len);
976 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
982 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
983 struct rte_eth_rss_conf *rss_conf)
985 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
986 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
990 /* RSS configuration is the same for all VNICs */
991 if (vnic && vnic->rss_hash_key) {
992 if (rss_conf->rss_key) {
993 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
994 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
995 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
998 hash_types = vnic->hash_type;
999 rss_conf->rss_hf = 0;
1000 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1001 rss_conf->rss_hf |= ETH_RSS_IPV4;
1002 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1004 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1005 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1007 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1009 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1010 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1012 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1014 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1015 rss_conf->rss_hf |= ETH_RSS_IPV6;
1016 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1018 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1019 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1021 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1023 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1024 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1026 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1030 "Unknwon RSS config from firmware (%08x), RSS disabled",
1035 rss_conf->rss_hf = 0;
1040 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1041 struct rte_eth_fc_conf *fc_conf)
1043 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1044 struct rte_eth_link link_info;
1047 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1051 memset(fc_conf, 0, sizeof(*fc_conf));
1052 if (bp->link_info.auto_pause)
1053 fc_conf->autoneg = 1;
1054 switch (bp->link_info.pause) {
1056 fc_conf->mode = RTE_FC_NONE;
1058 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1059 fc_conf->mode = RTE_FC_TX_PAUSE;
1061 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1062 fc_conf->mode = RTE_FC_RX_PAUSE;
1064 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1065 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1066 fc_conf->mode = RTE_FC_FULL;
1072 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1073 struct rte_eth_fc_conf *fc_conf)
1075 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1077 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1078 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1082 switch (fc_conf->mode) {
1084 bp->link_info.auto_pause = 0;
1085 bp->link_info.force_pause = 0;
1087 case RTE_FC_RX_PAUSE:
1088 if (fc_conf->autoneg) {
1089 bp->link_info.auto_pause =
1090 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1091 bp->link_info.force_pause = 0;
1093 bp->link_info.auto_pause = 0;
1094 bp->link_info.force_pause =
1095 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1098 case RTE_FC_TX_PAUSE:
1099 if (fc_conf->autoneg) {
1100 bp->link_info.auto_pause =
1101 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1102 bp->link_info.force_pause = 0;
1104 bp->link_info.auto_pause = 0;
1105 bp->link_info.force_pause =
1106 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1110 if (fc_conf->autoneg) {
1111 bp->link_info.auto_pause =
1112 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1113 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1114 bp->link_info.force_pause = 0;
1116 bp->link_info.auto_pause = 0;
1117 bp->link_info.force_pause =
1118 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1119 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1123 return bnxt_set_hwrm_link_config(bp, true);
1126 /* Add UDP tunneling port */
1128 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1129 struct rte_eth_udp_tunnel *udp_tunnel)
1131 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1132 uint16_t tunnel_type = 0;
1135 switch (udp_tunnel->prot_type) {
1136 case RTE_TUNNEL_TYPE_VXLAN:
1137 if (bp->vxlan_port_cnt) {
1138 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1139 udp_tunnel->udp_port);
1140 if (bp->vxlan_port != udp_tunnel->udp_port) {
1141 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1144 bp->vxlan_port_cnt++;
1148 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1149 bp->vxlan_port_cnt++;
1151 case RTE_TUNNEL_TYPE_GENEVE:
1152 if (bp->geneve_port_cnt) {
1153 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1154 udp_tunnel->udp_port);
1155 if (bp->geneve_port != udp_tunnel->udp_port) {
1156 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1159 bp->geneve_port_cnt++;
1163 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1164 bp->geneve_port_cnt++;
1167 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1170 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1176 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1177 struct rte_eth_udp_tunnel *udp_tunnel)
1179 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1180 uint16_t tunnel_type = 0;
1184 switch (udp_tunnel->prot_type) {
1185 case RTE_TUNNEL_TYPE_VXLAN:
1186 if (!bp->vxlan_port_cnt) {
1187 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1190 if (bp->vxlan_port != udp_tunnel->udp_port) {
1191 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1192 udp_tunnel->udp_port, bp->vxlan_port);
1195 if (--bp->vxlan_port_cnt)
1199 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1200 port = bp->vxlan_fw_dst_port_id;
1202 case RTE_TUNNEL_TYPE_GENEVE:
1203 if (!bp->geneve_port_cnt) {
1204 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1207 if (bp->geneve_port != udp_tunnel->udp_port) {
1208 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1209 udp_tunnel->udp_port, bp->geneve_port);
1212 if (--bp->geneve_port_cnt)
1216 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1217 port = bp->geneve_fw_dst_port_id;
1220 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1224 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1227 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1230 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1231 bp->geneve_port = 0;
1236 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1238 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1239 struct bnxt_vnic_info *vnic;
1242 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1244 /* Cycle through all VNICs */
1245 for (i = 0; i < bp->nr_vnics; i++) {
1247 * For each VNIC and each associated filter(s)
1248 * if VLAN exists && VLAN matches vlan_id
1249 * remove the MAC+VLAN filter
1250 * add a new MAC only filter
1252 * VLAN filter doesn't exist, just skip and continue
1254 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1255 filter = STAILQ_FIRST(&vnic->filter);
1257 temp_filter = STAILQ_NEXT(filter, next);
1259 if (filter->enables & chk &&
1260 filter->l2_ovlan == vlan_id) {
1261 /* Must delete the filter */
1262 STAILQ_REMOVE(&vnic->filter, filter,
1263 bnxt_filter_info, next);
1264 bnxt_hwrm_clear_l2_filter(bp, filter);
1266 &bp->free_filter_list,
1270 * Need to examine to see if the MAC
1271 * filter already existed or not before
1272 * allocating a new one
1275 new_filter = bnxt_alloc_filter(bp);
1278 "MAC/VLAN filter alloc failed\n");
1282 STAILQ_INSERT_TAIL(&vnic->filter,
1284 /* Inherit MAC from previous filter */
1285 new_filter->mac_index =
1287 memcpy(new_filter->l2_addr,
1288 filter->l2_addr, ETHER_ADDR_LEN);
1289 /* MAC only filter */
1290 rc = bnxt_hwrm_set_l2_filter(bp,
1296 "Del Vlan filter for %d\n",
1299 filter = temp_filter;
1307 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1309 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1310 struct bnxt_vnic_info *vnic;
1313 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN |
1314 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK;
1315 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1317 /* Cycle through all VNICs */
1318 for (i = 0; i < bp->nr_vnics; i++) {
1320 * For each VNIC and each associated filter(s)
1322 * if VLAN matches vlan_id
1323 * VLAN filter already exists, just skip and continue
1325 * add a new MAC+VLAN filter
1327 * Remove the old MAC only filter
1328 * Add a new MAC+VLAN filter
1330 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1331 filter = STAILQ_FIRST(&vnic->filter);
1333 temp_filter = STAILQ_NEXT(filter, next);
1335 if (filter->enables & chk) {
1336 if (filter->l2_ovlan == vlan_id)
1339 /* Must delete the MAC filter */
1340 STAILQ_REMOVE(&vnic->filter, filter,
1341 bnxt_filter_info, next);
1342 bnxt_hwrm_clear_l2_filter(bp, filter);
1343 filter->l2_ovlan = 0;
1345 &bp->free_filter_list,
1348 new_filter = bnxt_alloc_filter(bp);
1351 "MAC/VLAN filter alloc failed\n");
1355 STAILQ_INSERT_TAIL(&vnic->filter, new_filter,
1357 /* Inherit MAC from the previous filter */
1358 new_filter->mac_index = filter->mac_index;
1359 memcpy(new_filter->l2_addr, filter->l2_addr,
1361 /* MAC + VLAN ID filter */
1362 new_filter->l2_ovlan = vlan_id;
1363 new_filter->l2_ovlan_mask = 0xF000;
1364 new_filter->enables |= en;
1365 rc = bnxt_hwrm_set_l2_filter(bp,
1371 "Added Vlan filter for %d\n", vlan_id);
1373 filter = temp_filter;
1381 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1382 uint16_t vlan_id, int on)
1384 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1386 /* These operations apply to ALL existing MAC/VLAN filters */
1388 return bnxt_add_vlan_filter(bp, vlan_id);
1390 return bnxt_del_vlan_filter(bp, vlan_id);
1394 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1396 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1397 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1400 if (mask & ETH_VLAN_FILTER_MASK) {
1401 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1402 /* Remove any VLAN filters programmed */
1403 for (i = 0; i < 4095; i++)
1404 bnxt_del_vlan_filter(bp, i);
1406 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1407 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1410 if (mask & ETH_VLAN_STRIP_MASK) {
1411 /* Enable or disable VLAN stripping */
1412 for (i = 0; i < bp->nr_vnics; i++) {
1413 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1414 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1415 vnic->vlan_strip = true;
1417 vnic->vlan_strip = false;
1418 bnxt_hwrm_vnic_cfg(bp, vnic);
1420 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1421 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1424 if (mask & ETH_VLAN_EXTEND_MASK)
1425 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1431 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, struct ether_addr *addr)
1433 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1434 /* Default Filter is tied to VNIC 0 */
1435 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1436 struct bnxt_filter_info *filter;
1442 memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1444 STAILQ_FOREACH(filter, &vnic->filter, next) {
1445 /* Default Filter is at Index 0 */
1446 if (filter->mac_index != 0)
1448 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1451 memcpy(filter->l2_addr, bp->mac_addr, ETHER_ADDR_LEN);
1452 memset(filter->l2_addr_mask, 0xff, ETHER_ADDR_LEN);
1453 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1455 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1456 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1457 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1460 filter->mac_index = 0;
1461 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1468 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1469 struct ether_addr *mc_addr_set,
1470 uint32_t nb_mc_addr)
1472 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1473 char *mc_addr_list = (char *)mc_addr_set;
1474 struct bnxt_vnic_info *vnic;
1475 uint32_t off = 0, i = 0;
1477 vnic = &bp->vnic_info[0];
1479 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1480 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1484 /* TODO Check for Duplicate mcast addresses */
1485 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1486 for (i = 0; i < nb_mc_addr; i++) {
1487 memcpy(vnic->mc_list + off, &mc_addr_list[i], ETHER_ADDR_LEN);
1488 off += ETHER_ADDR_LEN;
1491 vnic->mc_addr_cnt = i;
1494 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1498 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1500 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1501 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1502 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1503 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1506 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1507 fw_major, fw_minor, fw_updt);
1509 ret += 1; /* add the size of '\0' */
1510 if (fw_size < (uint32_t)ret)
1517 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1518 struct rte_eth_rxq_info *qinfo)
1520 struct bnxt_rx_queue *rxq;
1522 rxq = dev->data->rx_queues[queue_id];
1524 qinfo->mp = rxq->mb_pool;
1525 qinfo->scattered_rx = dev->data->scattered_rx;
1526 qinfo->nb_desc = rxq->nb_rx_desc;
1528 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1529 qinfo->conf.rx_drop_en = 0;
1530 qinfo->conf.rx_deferred_start = 0;
1534 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1535 struct rte_eth_txq_info *qinfo)
1537 struct bnxt_tx_queue *txq;
1539 txq = dev->data->tx_queues[queue_id];
1541 qinfo->nb_desc = txq->nb_tx_desc;
1543 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1544 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1545 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1547 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1548 qinfo->conf.tx_rs_thresh = 0;
1549 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1552 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1554 struct bnxt *bp = eth_dev->data->dev_private;
1555 struct rte_eth_dev_info dev_info;
1556 uint32_t max_dev_mtu;
1560 bnxt_dev_info_get_op(eth_dev, &dev_info);
1561 max_dev_mtu = dev_info.max_rx_pktlen -
1562 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE * 2;
1564 if (new_mtu < ETHER_MIN_MTU || new_mtu > max_dev_mtu) {
1565 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1566 ETHER_MIN_MTU, max_dev_mtu);
1571 if (new_mtu > ETHER_MTU) {
1572 bp->flags |= BNXT_FLAG_JUMBO;
1573 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1574 DEV_RX_OFFLOAD_JUMBO_FRAME;
1576 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1577 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1578 bp->flags &= ~BNXT_FLAG_JUMBO;
1581 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len =
1582 new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1584 eth_dev->data->mtu = new_mtu;
1585 PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1587 for (i = 0; i < bp->nr_vnics; i++) {
1588 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1591 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1592 ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1593 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1597 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1598 size -= RTE_PKTMBUF_HEADROOM;
1600 if (size < new_mtu) {
1601 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1611 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1613 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1614 uint16_t vlan = bp->vlan;
1617 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1619 "PVID cannot be modified for this function\n");
1622 bp->vlan = on ? pvid : 0;
1624 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1631 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1633 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1635 return bnxt_hwrm_port_led_cfg(bp, true);
1639 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1641 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1643 return bnxt_hwrm_port_led_cfg(bp, false);
1647 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1649 uint32_t desc = 0, raw_cons = 0, cons;
1650 struct bnxt_cp_ring_info *cpr;
1651 struct bnxt_rx_queue *rxq;
1652 struct rx_pkt_cmpl *rxcmp;
1657 rxq = dev->data->rx_queues[rx_queue_id];
1661 while (raw_cons < rxq->nb_rx_desc) {
1662 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1663 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1665 if (!CMPL_VALID(rxcmp, valid))
1667 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1668 cmp_type = CMP_TYPE(rxcmp);
1669 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1670 cmp = (rte_le_to_cpu_32(
1671 ((struct rx_tpa_end_cmpl *)
1672 (rxcmp))->agg_bufs_v1) &
1673 RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1674 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1676 } else if (cmp_type == 0x11) {
1678 cmp = (rxcmp->agg_bufs_v1 &
1679 RX_PKT_CMPL_AGG_BUFS_MASK) >>
1680 RX_PKT_CMPL_AGG_BUFS_SFT;
1685 raw_cons += cmp ? cmp : 2;
1692 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1694 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1695 struct bnxt_rx_ring_info *rxr;
1696 struct bnxt_cp_ring_info *cpr;
1697 struct bnxt_sw_rx_bd *rx_buf;
1698 struct rx_pkt_cmpl *rxcmp;
1699 uint32_t cons, cp_cons;
1707 if (offset >= rxq->nb_rx_desc)
1710 cons = RING_CMP(cpr->cp_ring_struct, offset);
1711 cp_cons = cpr->cp_raw_cons;
1712 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1714 if (cons > cp_cons) {
1715 if (CMPL_VALID(rxcmp, cpr->valid))
1716 return RTE_ETH_RX_DESC_DONE;
1718 if (CMPL_VALID(rxcmp, !cpr->valid))
1719 return RTE_ETH_RX_DESC_DONE;
1721 rx_buf = &rxr->rx_buf_ring[cons];
1722 if (rx_buf->mbuf == NULL)
1723 return RTE_ETH_RX_DESC_UNAVAIL;
1726 return RTE_ETH_RX_DESC_AVAIL;
1730 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1732 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1733 struct bnxt_tx_ring_info *txr;
1734 struct bnxt_cp_ring_info *cpr;
1735 struct bnxt_sw_tx_bd *tx_buf;
1736 struct tx_pkt_cmpl *txcmp;
1737 uint32_t cons, cp_cons;
1745 if (offset >= txq->nb_tx_desc)
1748 cons = RING_CMP(cpr->cp_ring_struct, offset);
1749 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1750 cp_cons = cpr->cp_raw_cons;
1752 if (cons > cp_cons) {
1753 if (CMPL_VALID(txcmp, cpr->valid))
1754 return RTE_ETH_TX_DESC_UNAVAIL;
1756 if (CMPL_VALID(txcmp, !cpr->valid))
1757 return RTE_ETH_TX_DESC_UNAVAIL;
1759 tx_buf = &txr->tx_buf_ring[cons];
1760 if (tx_buf->mbuf == NULL)
1761 return RTE_ETH_TX_DESC_DONE;
1763 return RTE_ETH_TX_DESC_FULL;
1766 static struct bnxt_filter_info *
1767 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
1768 struct rte_eth_ethertype_filter *efilter,
1769 struct bnxt_vnic_info *vnic0,
1770 struct bnxt_vnic_info *vnic,
1773 struct bnxt_filter_info *mfilter = NULL;
1777 if (efilter->ether_type == ETHER_TYPE_IPv4 ||
1778 efilter->ether_type == ETHER_TYPE_IPv6) {
1779 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
1780 " ethertype filter.", efilter->ether_type);
1784 if (efilter->queue >= bp->rx_nr_rings) {
1785 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1790 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1791 vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1793 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1798 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1799 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
1800 if ((!memcmp(efilter->mac_addr.addr_bytes,
1801 mfilter->l2_addr, ETHER_ADDR_LEN) &&
1803 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
1804 mfilter->ethertype == efilter->ether_type)) {
1810 STAILQ_FOREACH(mfilter, &vnic->filter, next)
1811 if ((!memcmp(efilter->mac_addr.addr_bytes,
1812 mfilter->l2_addr, ETHER_ADDR_LEN) &&
1813 mfilter->ethertype == efilter->ether_type &&
1815 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
1829 bnxt_ethertype_filter(struct rte_eth_dev *dev,
1830 enum rte_filter_op filter_op,
1833 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1834 struct rte_eth_ethertype_filter *efilter =
1835 (struct rte_eth_ethertype_filter *)arg;
1836 struct bnxt_filter_info *bfilter, *filter1;
1837 struct bnxt_vnic_info *vnic, *vnic0;
1840 if (filter_op == RTE_ETH_FILTER_NOP)
1844 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
1849 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1850 vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1852 switch (filter_op) {
1853 case RTE_ETH_FILTER_ADD:
1854 bnxt_match_and_validate_ether_filter(bp, efilter,
1859 bfilter = bnxt_get_unused_filter(bp);
1860 if (bfilter == NULL) {
1862 "Not enough resources for a new filter.\n");
1865 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
1866 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
1868 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
1870 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
1871 bfilter->ethertype = efilter->ether_type;
1872 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
1874 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
1875 if (filter1 == NULL) {
1880 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
1881 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
1883 bfilter->dst_id = vnic->fw_vnic_id;
1885 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1887 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
1890 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
1893 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
1895 case RTE_ETH_FILTER_DELETE:
1896 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
1898 if (ret == -EEXIST) {
1899 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
1901 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
1903 bnxt_free_filter(bp, filter1);
1904 } else if (ret == 0) {
1905 PMD_DRV_LOG(ERR, "No matching filter found\n");
1909 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
1915 bnxt_free_filter(bp, bfilter);
1921 parse_ntuple_filter(struct bnxt *bp,
1922 struct rte_eth_ntuple_filter *nfilter,
1923 struct bnxt_filter_info *bfilter)
1927 if (nfilter->queue >= bp->rx_nr_rings) {
1928 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
1932 switch (nfilter->dst_port_mask) {
1934 bfilter->dst_port_mask = -1;
1935 bfilter->dst_port = nfilter->dst_port;
1936 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
1937 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
1940 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
1944 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
1945 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1947 switch (nfilter->proto_mask) {
1949 if (nfilter->proto == 17) /* IPPROTO_UDP */
1950 bfilter->ip_protocol = 17;
1951 else if (nfilter->proto == 6) /* IPPROTO_TCP */
1952 bfilter->ip_protocol = 6;
1955 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1958 PMD_DRV_LOG(ERR, "invalid protocol mask.");
1962 switch (nfilter->dst_ip_mask) {
1964 bfilter->dst_ipaddr_mask[0] = -1;
1965 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
1966 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
1967 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
1970 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
1974 switch (nfilter->src_ip_mask) {
1976 bfilter->src_ipaddr_mask[0] = -1;
1977 bfilter->src_ipaddr[0] = nfilter->src_ip;
1978 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
1979 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
1982 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
1986 switch (nfilter->src_port_mask) {
1988 bfilter->src_port_mask = -1;
1989 bfilter->src_port = nfilter->src_port;
1990 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
1991 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
1994 PMD_DRV_LOG(ERR, "invalid src_port mask.");
1999 //nfilter->priority = (uint8_t)filter->priority;
2001 bfilter->enables = en;
2005 static struct bnxt_filter_info*
2006 bnxt_match_ntuple_filter(struct bnxt *bp,
2007 struct bnxt_filter_info *bfilter,
2008 struct bnxt_vnic_info **mvnic)
2010 struct bnxt_filter_info *mfilter = NULL;
2013 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2014 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2015 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2016 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2017 bfilter->src_ipaddr_mask[0] ==
2018 mfilter->src_ipaddr_mask[0] &&
2019 bfilter->src_port == mfilter->src_port &&
2020 bfilter->src_port_mask == mfilter->src_port_mask &&
2021 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2022 bfilter->dst_ipaddr_mask[0] ==
2023 mfilter->dst_ipaddr_mask[0] &&
2024 bfilter->dst_port == mfilter->dst_port &&
2025 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2026 bfilter->flags == mfilter->flags &&
2027 bfilter->enables == mfilter->enables) {
2038 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2039 struct rte_eth_ntuple_filter *nfilter,
2040 enum rte_filter_op filter_op)
2042 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2043 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2046 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2047 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2051 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2052 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2056 bfilter = bnxt_get_unused_filter(bp);
2057 if (bfilter == NULL) {
2059 "Not enough resources for a new filter.\n");
2062 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2066 vnic = STAILQ_FIRST(&bp->ff_pool[nfilter->queue]);
2067 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
2068 filter1 = STAILQ_FIRST(&vnic0->filter);
2069 if (filter1 == NULL) {
2074 bfilter->dst_id = vnic->fw_vnic_id;
2075 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2077 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2078 bfilter->ethertype = 0x800;
2079 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2081 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2083 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2084 bfilter->dst_id == mfilter->dst_id) {
2085 PMD_DRV_LOG(ERR, "filter exists.\n");
2088 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2089 bfilter->dst_id != mfilter->dst_id) {
2090 mfilter->dst_id = vnic->fw_vnic_id;
2091 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2092 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2093 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2094 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2095 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2098 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2099 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2104 if (filter_op == RTE_ETH_FILTER_ADD) {
2105 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2106 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2109 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2111 if (mfilter == NULL) {
2112 /* This should not happen. But for Coverity! */
2116 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2118 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2119 bnxt_free_filter(bp, mfilter);
2120 mfilter->fw_l2_filter_id = -1;
2121 bnxt_free_filter(bp, bfilter);
2122 bfilter->fw_l2_filter_id = -1;
2127 bfilter->fw_l2_filter_id = -1;
2128 bnxt_free_filter(bp, bfilter);
2133 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2134 enum rte_filter_op filter_op,
2137 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2140 if (filter_op == RTE_ETH_FILTER_NOP)
2144 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2149 switch (filter_op) {
2150 case RTE_ETH_FILTER_ADD:
2151 ret = bnxt_cfg_ntuple_filter(bp,
2152 (struct rte_eth_ntuple_filter *)arg,
2155 case RTE_ETH_FILTER_DELETE:
2156 ret = bnxt_cfg_ntuple_filter(bp,
2157 (struct rte_eth_ntuple_filter *)arg,
2161 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2169 bnxt_parse_fdir_filter(struct bnxt *bp,
2170 struct rte_eth_fdir_filter *fdir,
2171 struct bnxt_filter_info *filter)
2173 enum rte_fdir_mode fdir_mode =
2174 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2175 struct bnxt_vnic_info *vnic0, *vnic;
2176 struct bnxt_filter_info *filter1;
2180 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2183 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2184 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2186 switch (fdir->input.flow_type) {
2187 case RTE_ETH_FLOW_IPV4:
2188 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2190 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2191 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2192 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2193 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2194 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2195 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2196 filter->ip_addr_type =
2197 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2198 filter->src_ipaddr_mask[0] = 0xffffffff;
2199 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2200 filter->dst_ipaddr_mask[0] = 0xffffffff;
2201 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2202 filter->ethertype = 0x800;
2203 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2205 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2206 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2207 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2208 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2209 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2210 filter->dst_port_mask = 0xffff;
2211 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2212 filter->src_port_mask = 0xffff;
2213 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2214 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2215 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2216 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2217 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2218 filter->ip_protocol = 6;
2219 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2220 filter->ip_addr_type =
2221 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2222 filter->src_ipaddr_mask[0] = 0xffffffff;
2223 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2224 filter->dst_ipaddr_mask[0] = 0xffffffff;
2225 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2226 filter->ethertype = 0x800;
2227 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2229 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2230 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2231 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2232 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2233 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2234 filter->dst_port_mask = 0xffff;
2235 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2236 filter->src_port_mask = 0xffff;
2237 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2238 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2239 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2240 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2241 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2242 filter->ip_protocol = 17;
2243 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2244 filter->ip_addr_type =
2245 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2246 filter->src_ipaddr_mask[0] = 0xffffffff;
2247 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2248 filter->dst_ipaddr_mask[0] = 0xffffffff;
2249 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2250 filter->ethertype = 0x800;
2251 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2253 case RTE_ETH_FLOW_IPV6:
2254 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2256 filter->ip_addr_type =
2257 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2258 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2259 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2260 rte_memcpy(filter->src_ipaddr,
2261 fdir->input.flow.ipv6_flow.src_ip, 16);
2262 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2263 rte_memcpy(filter->dst_ipaddr,
2264 fdir->input.flow.ipv6_flow.dst_ip, 16);
2265 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2266 memset(filter->dst_ipaddr_mask, 0xff, 16);
2267 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2268 memset(filter->src_ipaddr_mask, 0xff, 16);
2269 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2270 filter->ethertype = 0x86dd;
2271 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2273 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2274 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2275 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2276 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2277 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2278 filter->dst_port_mask = 0xffff;
2279 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2280 filter->src_port_mask = 0xffff;
2281 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2282 filter->ip_addr_type =
2283 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2284 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2285 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2286 rte_memcpy(filter->src_ipaddr,
2287 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2288 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2289 rte_memcpy(filter->dst_ipaddr,
2290 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2291 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2292 memset(filter->dst_ipaddr_mask, 0xff, 16);
2293 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2294 memset(filter->src_ipaddr_mask, 0xff, 16);
2295 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2296 filter->ethertype = 0x86dd;
2297 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2299 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2300 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2301 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2302 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2303 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2304 filter->dst_port_mask = 0xffff;
2305 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2306 filter->src_port_mask = 0xffff;
2307 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2308 filter->ip_addr_type =
2309 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2310 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2311 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2312 rte_memcpy(filter->src_ipaddr,
2313 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2314 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2315 rte_memcpy(filter->dst_ipaddr,
2316 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2317 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2318 memset(filter->dst_ipaddr_mask, 0xff, 16);
2319 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2320 memset(filter->src_ipaddr_mask, 0xff, 16);
2321 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2322 filter->ethertype = 0x86dd;
2323 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2325 case RTE_ETH_FLOW_L2_PAYLOAD:
2326 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2327 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2329 case RTE_ETH_FLOW_VXLAN:
2330 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2332 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2333 filter->tunnel_type =
2334 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2335 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2337 case RTE_ETH_FLOW_NVGRE:
2338 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2340 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2341 filter->tunnel_type =
2342 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2343 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2345 case RTE_ETH_FLOW_UNKNOWN:
2346 case RTE_ETH_FLOW_RAW:
2347 case RTE_ETH_FLOW_FRAG_IPV4:
2348 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2349 case RTE_ETH_FLOW_FRAG_IPV6:
2350 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2351 case RTE_ETH_FLOW_IPV6_EX:
2352 case RTE_ETH_FLOW_IPV6_TCP_EX:
2353 case RTE_ETH_FLOW_IPV6_UDP_EX:
2354 case RTE_ETH_FLOW_GENEVE:
2360 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
2361 vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]);
2363 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2368 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2369 rte_memcpy(filter->dst_macaddr,
2370 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2371 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2374 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2375 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2376 filter1 = STAILQ_FIRST(&vnic0->filter);
2377 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2379 filter->dst_id = vnic->fw_vnic_id;
2380 for (i = 0; i < ETHER_ADDR_LEN; i++)
2381 if (filter->dst_macaddr[i] == 0x00)
2382 filter1 = STAILQ_FIRST(&vnic0->filter);
2384 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2387 if (filter1 == NULL)
2390 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2391 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2393 filter->enables = en;
2398 static struct bnxt_filter_info *
2399 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2400 struct bnxt_vnic_info **mvnic)
2402 struct bnxt_filter_info *mf = NULL;
2405 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2406 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2408 STAILQ_FOREACH(mf, &vnic->filter, next) {
2409 if (mf->filter_type == nf->filter_type &&
2410 mf->flags == nf->flags &&
2411 mf->src_port == nf->src_port &&
2412 mf->src_port_mask == nf->src_port_mask &&
2413 mf->dst_port == nf->dst_port &&
2414 mf->dst_port_mask == nf->dst_port_mask &&
2415 mf->ip_protocol == nf->ip_protocol &&
2416 mf->ip_addr_type == nf->ip_addr_type &&
2417 mf->ethertype == nf->ethertype &&
2418 mf->vni == nf->vni &&
2419 mf->tunnel_type == nf->tunnel_type &&
2420 mf->l2_ovlan == nf->l2_ovlan &&
2421 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2422 mf->l2_ivlan == nf->l2_ivlan &&
2423 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2424 !memcmp(mf->l2_addr, nf->l2_addr, ETHER_ADDR_LEN) &&
2425 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2427 !memcmp(mf->src_macaddr, nf->src_macaddr,
2429 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2431 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2432 sizeof(nf->src_ipaddr)) &&
2433 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2434 sizeof(nf->src_ipaddr_mask)) &&
2435 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2436 sizeof(nf->dst_ipaddr)) &&
2437 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2438 sizeof(nf->dst_ipaddr_mask))) {
2449 bnxt_fdir_filter(struct rte_eth_dev *dev,
2450 enum rte_filter_op filter_op,
2453 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2454 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
2455 struct bnxt_filter_info *filter, *match;
2456 struct bnxt_vnic_info *vnic, *mvnic;
2459 if (filter_op == RTE_ETH_FILTER_NOP)
2462 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2465 switch (filter_op) {
2466 case RTE_ETH_FILTER_ADD:
2467 case RTE_ETH_FILTER_DELETE:
2469 filter = bnxt_get_unused_filter(bp);
2470 if (filter == NULL) {
2472 "Not enough resources for a new flow.\n");
2476 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2479 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2481 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2482 vnic = STAILQ_FIRST(&bp->ff_pool[0]);
2484 vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]);
2486 match = bnxt_match_fdir(bp, filter, &mvnic);
2487 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2488 if (match->dst_id == vnic->fw_vnic_id) {
2489 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2493 match->dst_id = vnic->fw_vnic_id;
2494 ret = bnxt_hwrm_set_ntuple_filter(bp,
2497 STAILQ_REMOVE(&mvnic->filter, match,
2498 bnxt_filter_info, next);
2499 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2501 "Filter with matching pattern exist\n");
2503 "Updated it to new destination q\n");
2507 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2508 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2513 if (filter_op == RTE_ETH_FILTER_ADD) {
2514 ret = bnxt_hwrm_set_ntuple_filter(bp,
2519 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2521 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2522 STAILQ_REMOVE(&vnic->filter, match,
2523 bnxt_filter_info, next);
2524 bnxt_free_filter(bp, match);
2525 filter->fw_l2_filter_id = -1;
2526 bnxt_free_filter(bp, filter);
2529 case RTE_ETH_FILTER_FLUSH:
2530 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2531 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2533 STAILQ_FOREACH(filter, &vnic->filter, next) {
2534 if (filter->filter_type ==
2535 HWRM_CFA_NTUPLE_FILTER) {
2537 bnxt_hwrm_clear_ntuple_filter(bp,
2539 STAILQ_REMOVE(&vnic->filter, filter,
2540 bnxt_filter_info, next);
2545 case RTE_ETH_FILTER_UPDATE:
2546 case RTE_ETH_FILTER_STATS:
2547 case RTE_ETH_FILTER_INFO:
2548 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2551 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2558 filter->fw_l2_filter_id = -1;
2559 bnxt_free_filter(bp, filter);
2564 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2565 enum rte_filter_type filter_type,
2566 enum rte_filter_op filter_op, void *arg)
2570 switch (filter_type) {
2571 case RTE_ETH_FILTER_TUNNEL:
2573 "filter type: %d: To be implemented\n", filter_type);
2575 case RTE_ETH_FILTER_FDIR:
2576 ret = bnxt_fdir_filter(dev, filter_op, arg);
2578 case RTE_ETH_FILTER_NTUPLE:
2579 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2581 case RTE_ETH_FILTER_ETHERTYPE:
2582 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2584 case RTE_ETH_FILTER_GENERIC:
2585 if (filter_op != RTE_ETH_FILTER_GET)
2587 *(const void **)arg = &bnxt_flow_ops;
2591 "Filter type (%d) not supported", filter_type);
2598 static const uint32_t *
2599 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2601 static const uint32_t ptypes[] = {
2602 RTE_PTYPE_L2_ETHER_VLAN,
2603 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2604 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2608 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2609 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2610 RTE_PTYPE_INNER_L4_ICMP,
2611 RTE_PTYPE_INNER_L4_TCP,
2612 RTE_PTYPE_INNER_L4_UDP,
2616 if (dev->rx_pkt_burst == bnxt_recv_pkts)
2621 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2624 uint32_t reg_base = *reg_arr & 0xfffff000;
2628 for (i = 0; i < count; i++) {
2629 if ((reg_arr[i] & 0xfffff000) != reg_base)
2632 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2633 rte_cpu_to_le_32(rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off));
2637 static int bnxt_map_ptp_regs(struct bnxt *bp)
2639 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2643 reg_arr = ptp->rx_regs;
2644 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2648 reg_arr = ptp->tx_regs;
2649 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2653 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2654 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2656 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2657 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2662 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2664 rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +
2665 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16));
2666 rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +
2667 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20));
2670 static uint64_t bnxt_cc_read(struct bnxt *bp)
2674 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2675 BNXT_GRCPF_REG_SYNC_TIME));
2676 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2677 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2681 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2683 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2686 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2687 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2688 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2691 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2692 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2693 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2694 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2695 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2696 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2701 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2703 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2704 struct bnxt_pf_info *pf = &bp->pf;
2711 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2712 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2713 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2716 port_id = pf->port_id;
2717 rte_cpu_to_le_32(rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2718 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]));
2720 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2721 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2722 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
2723 /* bnxt_clr_rx_ts(bp); TBD */
2727 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2728 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
2729 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2730 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
2736 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
2739 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2740 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2745 ns = rte_timespec_to_ns(ts);
2746 /* Set the timecounters to a new value. */
2753 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
2755 uint64_t ns, systime_cycles;
2756 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2757 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2762 systime_cycles = bnxt_cc_read(bp);
2763 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
2764 *ts = rte_ns_to_timespec(ns);
2769 bnxt_timesync_enable(struct rte_eth_dev *dev)
2771 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2772 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2779 ptp->tx_tstamp_en = 1;
2780 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
2782 if (!bnxt_hwrm_ptp_cfg(bp))
2783 bnxt_map_ptp_regs(bp);
2785 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
2786 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2787 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2789 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2790 ptp->tc.cc_shift = shift;
2791 ptp->tc.nsec_mask = (1ULL << shift) - 1;
2793 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2794 ptp->rx_tstamp_tc.cc_shift = shift;
2795 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2797 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2798 ptp->tx_tstamp_tc.cc_shift = shift;
2799 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2805 bnxt_timesync_disable(struct rte_eth_dev *dev)
2807 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2808 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2814 ptp->tx_tstamp_en = 0;
2817 bnxt_hwrm_ptp_cfg(bp);
2819 bnxt_unmap_ptp_regs(bp);
2825 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
2826 struct timespec *timestamp,
2827 uint32_t flags __rte_unused)
2829 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2830 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2831 uint64_t rx_tstamp_cycles = 0;
2837 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
2838 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
2839 *timestamp = rte_ns_to_timespec(ns);
2844 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
2845 struct timespec *timestamp)
2847 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2848 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2849 uint64_t tx_tstamp_cycles = 0;
2855 bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
2856 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
2857 *timestamp = rte_ns_to_timespec(ns);
2863 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
2865 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2866 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2871 ptp->tc.nsec += delta;
2877 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
2879 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2881 uint32_t dir_entries;
2882 uint32_t entry_length;
2884 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
2885 bp->pdev->addr.domain, bp->pdev->addr.bus,
2886 bp->pdev->addr.devid, bp->pdev->addr.function);
2888 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
2892 return dir_entries * entry_length;
2896 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
2897 struct rte_dev_eeprom_info *in_eeprom)
2899 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2903 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
2904 "len = %d\n", bp->pdev->addr.domain,
2905 bp->pdev->addr.bus, bp->pdev->addr.devid,
2906 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2908 if (in_eeprom->offset == 0) /* special offset value to get directory */
2909 return bnxt_get_nvram_directory(bp, in_eeprom->length,
2912 index = in_eeprom->offset >> 24;
2913 offset = in_eeprom->offset & 0xffffff;
2916 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
2917 in_eeprom->length, in_eeprom->data);
2922 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
2925 case BNX_DIR_TYPE_CHIMP_PATCH:
2926 case BNX_DIR_TYPE_BOOTCODE:
2927 case BNX_DIR_TYPE_BOOTCODE_2:
2928 case BNX_DIR_TYPE_APE_FW:
2929 case BNX_DIR_TYPE_APE_PATCH:
2930 case BNX_DIR_TYPE_KONG_FW:
2931 case BNX_DIR_TYPE_KONG_PATCH:
2932 case BNX_DIR_TYPE_BONO_FW:
2933 case BNX_DIR_TYPE_BONO_PATCH:
2941 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
2944 case BNX_DIR_TYPE_AVS:
2945 case BNX_DIR_TYPE_EXP_ROM_MBA:
2946 case BNX_DIR_TYPE_PCIE:
2947 case BNX_DIR_TYPE_TSCF_UCODE:
2948 case BNX_DIR_TYPE_EXT_PHY:
2949 case BNX_DIR_TYPE_CCM:
2950 case BNX_DIR_TYPE_ISCSI_BOOT:
2951 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
2952 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
2960 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
2962 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
2963 bnxt_dir_type_is_other_exec_format(dir_type);
2967 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
2968 struct rte_dev_eeprom_info *in_eeprom)
2970 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2971 uint8_t index, dir_op;
2972 uint16_t type, ext, ordinal, attr;
2974 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
2975 "len = %d\n", bp->pdev->addr.domain,
2976 bp->pdev->addr.bus, bp->pdev->addr.devid,
2977 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2980 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
2984 type = in_eeprom->magic >> 16;
2986 if (type == 0xffff) { /* special value for directory operations */
2987 index = in_eeprom->magic & 0xff;
2988 dir_op = in_eeprom->magic >> 8;
2992 case 0x0e: /* erase */
2993 if (in_eeprom->offset != ~in_eeprom->magic)
2995 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3001 /* Create or re-write an NVM item: */
3002 if (bnxt_dir_type_is_executable(type) == true)
3004 ext = in_eeprom->magic & 0xffff;
3005 ordinal = in_eeprom->offset >> 16;
3006 attr = in_eeprom->offset & 0xffff;
3008 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3009 in_eeprom->data, in_eeprom->length);
3017 static const struct eth_dev_ops bnxt_dev_ops = {
3018 .dev_infos_get = bnxt_dev_info_get_op,
3019 .dev_close = bnxt_dev_close_op,
3020 .dev_configure = bnxt_dev_configure_op,
3021 .dev_start = bnxt_dev_start_op,
3022 .dev_stop = bnxt_dev_stop_op,
3023 .dev_set_link_up = bnxt_dev_set_link_up_op,
3024 .dev_set_link_down = bnxt_dev_set_link_down_op,
3025 .stats_get = bnxt_stats_get_op,
3026 .stats_reset = bnxt_stats_reset_op,
3027 .rx_queue_setup = bnxt_rx_queue_setup_op,
3028 .rx_queue_release = bnxt_rx_queue_release_op,
3029 .tx_queue_setup = bnxt_tx_queue_setup_op,
3030 .tx_queue_release = bnxt_tx_queue_release_op,
3031 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3032 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3033 .reta_update = bnxt_reta_update_op,
3034 .reta_query = bnxt_reta_query_op,
3035 .rss_hash_update = bnxt_rss_hash_update_op,
3036 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3037 .link_update = bnxt_link_update_op,
3038 .promiscuous_enable = bnxt_promiscuous_enable_op,
3039 .promiscuous_disable = bnxt_promiscuous_disable_op,
3040 .allmulticast_enable = bnxt_allmulticast_enable_op,
3041 .allmulticast_disable = bnxt_allmulticast_disable_op,
3042 .mac_addr_add = bnxt_mac_addr_add_op,
3043 .mac_addr_remove = bnxt_mac_addr_remove_op,
3044 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3045 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3046 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3047 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3048 .vlan_filter_set = bnxt_vlan_filter_set_op,
3049 .vlan_offload_set = bnxt_vlan_offload_set_op,
3050 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3051 .mtu_set = bnxt_mtu_set_op,
3052 .mac_addr_set = bnxt_set_default_mac_addr_op,
3053 .xstats_get = bnxt_dev_xstats_get_op,
3054 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3055 .xstats_reset = bnxt_dev_xstats_reset_op,
3056 .fw_version_get = bnxt_fw_version_get,
3057 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3058 .rxq_info_get = bnxt_rxq_info_get_op,
3059 .txq_info_get = bnxt_txq_info_get_op,
3060 .dev_led_on = bnxt_dev_led_on_op,
3061 .dev_led_off = bnxt_dev_led_off_op,
3062 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3063 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3064 .rx_queue_count = bnxt_rx_queue_count_op,
3065 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3066 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3067 .rx_queue_start = bnxt_rx_queue_start,
3068 .rx_queue_stop = bnxt_rx_queue_stop,
3069 .tx_queue_start = bnxt_tx_queue_start,
3070 .tx_queue_stop = bnxt_tx_queue_stop,
3071 .filter_ctrl = bnxt_filter_ctrl_op,
3072 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3073 .get_eeprom_length = bnxt_get_eeprom_length_op,
3074 .get_eeprom = bnxt_get_eeprom_op,
3075 .set_eeprom = bnxt_set_eeprom_op,
3076 .timesync_enable = bnxt_timesync_enable,
3077 .timesync_disable = bnxt_timesync_disable,
3078 .timesync_read_time = bnxt_timesync_read_time,
3079 .timesync_write_time = bnxt_timesync_write_time,
3080 .timesync_adjust_time = bnxt_timesync_adjust_time,
3081 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3082 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3085 static bool bnxt_vf_pciid(uint16_t id)
3087 if (id == BROADCOM_DEV_ID_57304_VF ||
3088 id == BROADCOM_DEV_ID_57406_VF ||
3089 id == BROADCOM_DEV_ID_5731X_VF ||
3090 id == BROADCOM_DEV_ID_5741X_VF ||
3091 id == BROADCOM_DEV_ID_57414_VF ||
3092 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3093 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3094 id == BROADCOM_DEV_ID_58802_VF)
3099 bool bnxt_stratus_device(struct bnxt *bp)
3101 uint16_t id = bp->pdev->id.device_id;
3103 if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3104 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3105 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3110 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3112 struct bnxt *bp = eth_dev->data->dev_private;
3113 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3116 /* enable device (incl. PCI PM wakeup), and bus-mastering */
3117 if (!pci_dev->mem_resource[0].addr) {
3119 "Cannot find PCI device base address, aborting\n");
3121 goto init_err_disable;
3124 bp->eth_dev = eth_dev;
3127 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3129 PMD_DRV_LOG(ERR, "Cannot map device registers, aborting\n");
3131 goto init_err_release;
3134 if (!pci_dev->mem_resource[2].addr) {
3136 "Cannot find PCI device BAR 2 address, aborting\n");
3138 goto init_err_release;
3140 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3148 if (bp->doorbell_base)
3149 bp->doorbell_base = NULL;
3157 #define ALLOW_FUNC(x) \
3159 typeof(x) arg = (x); \
3160 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3161 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3164 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3166 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3167 char mz_name[RTE_MEMZONE_NAMESIZE];
3168 const struct rte_memzone *mz = NULL;
3169 static int version_printed;
3170 uint32_t total_alloc_len;
3171 rte_iova_t mz_phys_addr;
3175 if (version_printed++ == 0)
3176 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
3178 rte_eth_copy_pci_info(eth_dev, pci_dev);
3180 bp = eth_dev->data->dev_private;
3182 bp->dev_stopped = 1;
3184 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3187 if (bnxt_vf_pciid(pci_dev->id.device_id))
3188 bp->flags |= BNXT_FLAG_VF;
3190 rc = bnxt_init_board(eth_dev);
3193 "Board initialization failed rc: %x\n", rc);
3197 eth_dev->dev_ops = &bnxt_dev_ops;
3198 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3199 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3200 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3203 if (pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) {
3204 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3205 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3206 pci_dev->addr.bus, pci_dev->addr.devid,
3207 pci_dev->addr.function, "rx_port_stats");
3208 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3209 mz = rte_memzone_lookup(mz_name);
3210 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3211 sizeof(struct rx_port_stats) + 512);
3213 mz = rte_memzone_reserve(mz_name, total_alloc_len,
3216 RTE_MEMZONE_SIZE_HINT_ONLY |
3217 RTE_MEMZONE_IOVA_CONTIG);
3221 memset(mz->addr, 0, mz->len);
3222 mz_phys_addr = mz->iova;
3223 if ((unsigned long)mz->addr == mz_phys_addr) {
3224 PMD_DRV_LOG(WARNING,
3225 "Memzone physical address same as virtual.\n");
3226 PMD_DRV_LOG(WARNING,
3227 "Using rte_mem_virt2iova()\n");
3228 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3229 if (mz_phys_addr == 0) {
3231 "unable to map address to physical memory\n");
3236 bp->rx_mem_zone = (const void *)mz;
3237 bp->hw_rx_port_stats = mz->addr;
3238 bp->hw_rx_port_stats_map = mz_phys_addr;
3240 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3241 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3242 pci_dev->addr.bus, pci_dev->addr.devid,
3243 pci_dev->addr.function, "tx_port_stats");
3244 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3245 mz = rte_memzone_lookup(mz_name);
3246 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3247 sizeof(struct tx_port_stats) + 512);
3249 mz = rte_memzone_reserve(mz_name,
3253 RTE_MEMZONE_SIZE_HINT_ONLY |
3254 RTE_MEMZONE_IOVA_CONTIG);
3258 memset(mz->addr, 0, mz->len);
3259 mz_phys_addr = mz->iova;
3260 if ((unsigned long)mz->addr == mz_phys_addr) {
3261 PMD_DRV_LOG(WARNING,
3262 "Memzone physical address same as virtual.\n");
3263 PMD_DRV_LOG(WARNING,
3264 "Using rte_mem_virt2iova()\n");
3265 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3266 if (mz_phys_addr == 0) {
3268 "unable to map address to physical memory\n");
3273 bp->tx_mem_zone = (const void *)mz;
3274 bp->hw_tx_port_stats = mz->addr;
3275 bp->hw_tx_port_stats_map = mz_phys_addr;
3277 bp->flags |= BNXT_FLAG_PORT_STATS;
3280 rc = bnxt_alloc_hwrm_resources(bp);
3283 "hwrm resource allocation failure rc: %x\n", rc);
3286 rc = bnxt_hwrm_ver_get(bp);
3289 rc = bnxt_hwrm_queue_qportcfg(bp);
3291 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n");
3295 rc = bnxt_hwrm_func_qcfg(bp);
3297 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n");
3301 /* Get the MAX capabilities for this function */
3302 rc = bnxt_hwrm_func_qcaps(bp);
3304 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc);
3307 if (bp->max_tx_rings == 0) {
3308 PMD_DRV_LOG(ERR, "No TX rings available!\n");
3312 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3313 ETHER_ADDR_LEN * bp->max_l2_ctx, 0);
3314 if (eth_dev->data->mac_addrs == NULL) {
3316 "Failed to alloc %u bytes needed to store MAC addr tbl",
3317 ETHER_ADDR_LEN * bp->max_l2_ctx);
3322 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, ETHER_ADDR_LEN)) {
3324 "Invalid MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
3325 bp->dflt_mac_addr[0], bp->dflt_mac_addr[1],
3326 bp->dflt_mac_addr[2], bp->dflt_mac_addr[3],
3327 bp->dflt_mac_addr[4], bp->dflt_mac_addr[5]);
3331 /* Copy the permanent MAC from the qcap response address now. */
3332 memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr));
3333 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
3335 if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3336 /* 1 ring is for default completion ring */
3337 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
3342 bp->grp_info = rte_zmalloc("bnxt_grp_info",
3343 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
3344 if (!bp->grp_info) {
3346 "Failed to alloc %zu bytes to store group info table\n",
3347 sizeof(*bp->grp_info) * bp->max_ring_grps);
3352 /* Forward all requests if firmware is new enough */
3353 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3354 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3355 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3356 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3358 PMD_DRV_LOG(WARNING,
3359 "Firmware too old for VF mailbox functionality\n");
3360 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3364 * The following are used for driver cleanup. If we disallow these,
3365 * VF drivers can't clean up cleanly.
3367 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3368 ALLOW_FUNC(HWRM_VNIC_FREE);
3369 ALLOW_FUNC(HWRM_RING_FREE);
3370 ALLOW_FUNC(HWRM_RING_GRP_FREE);
3371 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3372 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3373 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3374 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3375 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3376 rc = bnxt_hwrm_func_driver_register(bp);
3379 "Failed to register driver");
3385 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3386 pci_dev->mem_resource[0].phys_addr,
3387 pci_dev->mem_resource[0].addr);
3389 rc = bnxt_hwrm_func_reset(bp);
3391 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc);
3397 //if (bp->pf.active_vfs) {
3398 // TODO: Deallocate VF resources?
3400 if (bp->pdev->max_vfs) {
3401 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
3403 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
3407 rc = bnxt_hwrm_allocate_pf_only(bp);
3410 "Failed to allocate PF resources\n");
3416 bnxt_hwrm_port_led_qcaps(bp);
3418 rc = bnxt_setup_int(bp);
3422 rc = bnxt_alloc_mem(bp);
3424 goto error_free_int;
3426 rc = bnxt_request_int(bp);
3428 goto error_free_int;
3430 bnxt_enable_int(bp);
3436 bnxt_disable_int(bp);
3437 bnxt_hwrm_func_buf_unrgtr(bp);
3441 bnxt_dev_uninit(eth_dev);
3447 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
3449 struct bnxt *bp = eth_dev->data->dev_private;
3452 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3455 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
3456 bnxt_disable_int(bp);
3459 if (eth_dev->data->mac_addrs != NULL) {
3460 rte_free(eth_dev->data->mac_addrs);
3461 eth_dev->data->mac_addrs = NULL;
3463 if (bp->grp_info != NULL) {
3464 rte_free(bp->grp_info);
3465 bp->grp_info = NULL;
3467 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
3468 bnxt_free_hwrm_resources(bp);
3470 if (bp->tx_mem_zone) {
3471 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
3472 bp->tx_mem_zone = NULL;
3475 if (bp->rx_mem_zone) {
3476 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
3477 bp->rx_mem_zone = NULL;
3480 if (bp->dev_stopped == 0)
3481 bnxt_dev_close_op(eth_dev);
3483 rte_free(bp->pf.vf_info);
3484 eth_dev->dev_ops = NULL;
3485 eth_dev->rx_pkt_burst = NULL;
3486 eth_dev->tx_pkt_burst = NULL;
3491 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3492 struct rte_pci_device *pci_dev)
3494 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
3498 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
3500 return rte_eth_dev_pci_generic_remove(pci_dev, bnxt_dev_uninit);
3503 static struct rte_pci_driver bnxt_rte_pmd = {
3504 .id_table = bnxt_pci_id_map,
3505 .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
3506 RTE_PCI_DRV_INTR_LSC,
3507 .probe = bnxt_pci_probe,
3508 .remove = bnxt_pci_remove,
3512 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
3514 if (strcmp(dev->device->driver->name, drv->driver.name))
3520 bool is_bnxt_supported(struct rte_eth_dev *dev)
3522 return is_device_supported(dev, &bnxt_rte_pmd);
3525 RTE_INIT(bnxt_init_log);
3529 bnxt_logtype_driver = rte_log_register("pmd.bnxt.driver");
3530 if (bnxt_logtype_driver >= 0)
3531 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_INFO);
3534 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
3535 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
3536 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");