1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
15 #include <rte_kvargs.h>
18 #include "bnxt_filter.h"
19 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_stats.h"
27 #include "bnxt_vnic.h"
28 #include "hsi_struct_def_dpdk.h"
29 #include "bnxt_nvm_defs.h"
31 #define DRV_MODULE_NAME "bnxt"
32 static const char bnxt_version[] =
33 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
34 int bnxt_logtype_driver;
37 * The set of PCI devices this driver supports
39 static const struct rte_pci_id bnxt_pci_id_map[] = {
40 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
41 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
42 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
43 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
45 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
47 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
93 { .vendor_id = 0, /* sentinel */ },
96 #define BNXT_ETH_RSS_SUPPORT ( \
98 ETH_RSS_NONFRAG_IPV4_TCP | \
99 ETH_RSS_NONFRAG_IPV4_UDP | \
101 ETH_RSS_NONFRAG_IPV6_TCP | \
102 ETH_RSS_NONFRAG_IPV6_UDP)
104 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
105 DEV_TX_OFFLOAD_IPV4_CKSUM | \
106 DEV_TX_OFFLOAD_TCP_CKSUM | \
107 DEV_TX_OFFLOAD_UDP_CKSUM | \
108 DEV_TX_OFFLOAD_TCP_TSO | \
109 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
110 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
111 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
112 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
113 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
114 DEV_TX_OFFLOAD_QINQ_INSERT | \
115 DEV_TX_OFFLOAD_MULTI_SEGS)
117 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
118 DEV_RX_OFFLOAD_VLAN_STRIP | \
119 DEV_RX_OFFLOAD_IPV4_CKSUM | \
120 DEV_RX_OFFLOAD_UDP_CKSUM | \
121 DEV_RX_OFFLOAD_TCP_CKSUM | \
122 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
123 DEV_RX_OFFLOAD_JUMBO_FRAME | \
124 DEV_RX_OFFLOAD_KEEP_CRC | \
125 DEV_RX_OFFLOAD_VLAN_EXTEND | \
126 DEV_RX_OFFLOAD_TCP_LRO | \
127 DEV_RX_OFFLOAD_SCATTER | \
128 DEV_RX_OFFLOAD_RSS_HASH)
130 #define BNXT_DEVARG_TRUFLOW "host-based-truflow"
131 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat"
132 static const char *const bnxt_dev_args[] = {
134 BNXT_DEVARG_FLOW_XSTAT,
139 * truflow == false to disable the feature
140 * truflow == true to enable the feature
142 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1)
145 * flow_xstat == false to disable the feature
146 * flow_xstat == true to enable the feature
148 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1)
150 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
151 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
152 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
153 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
154 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
155 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
156 static int bnxt_restore_vlan_filters(struct bnxt *bp);
157 static void bnxt_dev_recover(void *arg);
158 static void bnxt_free_error_recovery_info(struct bnxt *bp);
160 int is_bnxt_in_error(struct bnxt *bp)
162 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
164 if (bp->flags & BNXT_FLAG_FW_RESET)
170 /***********************/
173 * High level utility functions
176 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
178 if (!BNXT_CHIP_THOR(bp))
181 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
182 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
183 BNXT_RSS_ENTRIES_PER_CTX_THOR;
186 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
188 if (!BNXT_CHIP_THOR(bp))
189 return HW_HASH_INDEX_SIZE;
191 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
194 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
196 bnxt_free_filter_mem(bp);
197 bnxt_free_vnic_attributes(bp);
198 bnxt_free_vnic_mem(bp);
200 /* tx/rx rings are configured as part of *_queue_setup callbacks.
201 * If the number of rings change across fw update,
202 * we don't have much choice except to warn the user.
206 bnxt_free_tx_rings(bp);
207 bnxt_free_rx_rings(bp);
209 bnxt_free_async_cp_ring(bp);
210 bnxt_free_rxtx_nq_ring(bp);
212 rte_free(bp->grp_info);
216 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
220 rc = bnxt_alloc_ring_grps(bp);
224 rc = bnxt_alloc_async_ring_struct(bp);
228 rc = bnxt_alloc_vnic_mem(bp);
232 rc = bnxt_alloc_vnic_attributes(bp);
236 rc = bnxt_alloc_filter_mem(bp);
240 rc = bnxt_alloc_async_cp_ring(bp);
244 rc = bnxt_alloc_rxtx_nq_ring(bp);
251 bnxt_free_mem(bp, reconfig);
255 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
257 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
258 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
259 uint64_t rx_offloads = dev_conf->rxmode.offloads;
260 struct bnxt_rx_queue *rxq;
264 rc = bnxt_vnic_grp_alloc(bp, vnic);
268 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
269 vnic_id, vnic, vnic->fw_grp_ids);
271 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
275 /* Alloc RSS context only if RSS mode is enabled */
276 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
277 int j, nr_ctxs = bnxt_rss_ctxts(bp);
280 for (j = 0; j < nr_ctxs; j++) {
281 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
287 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
291 vnic->num_lb_ctxts = nr_ctxs;
295 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
296 * setting is not available at this time, it will not be
297 * configured correctly in the CFA.
299 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
300 vnic->vlan_strip = true;
302 vnic->vlan_strip = false;
304 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
308 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
312 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
313 rxq = bp->eth_dev->data->rx_queues[j];
316 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
317 j, rxq->vnic, rxq->vnic->fw_grp_ids);
319 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
320 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
322 vnic->rx_queue_cnt++;
325 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
327 rc = bnxt_vnic_rss_configure(bp, vnic);
331 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
333 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
334 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
336 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
340 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
345 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
349 rc = bnxt_hwrm_ctx_rgtr(bp, bp->rx_fc_in_tbl.dma,
350 &bp->rx_fc_in_tbl.ctx_id);
355 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
356 " rx_fc_in_tbl.ctx_id = %d\n",
358 (void *)((uintptr_t)bp->rx_fc_in_tbl.dma),
359 bp->rx_fc_in_tbl.ctx_id);
361 rc = bnxt_hwrm_ctx_rgtr(bp, bp->rx_fc_out_tbl.dma,
362 &bp->rx_fc_out_tbl.ctx_id);
367 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
368 " rx_fc_out_tbl.ctx_id = %d\n",
369 bp->rx_fc_out_tbl.va,
370 (void *)((uintptr_t)bp->rx_fc_out_tbl.dma),
371 bp->rx_fc_out_tbl.ctx_id);
373 rc = bnxt_hwrm_ctx_rgtr(bp, bp->tx_fc_in_tbl.dma,
374 &bp->tx_fc_in_tbl.ctx_id);
379 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
380 " tx_fc_in_tbl.ctx_id = %d\n",
382 (void *)((uintptr_t)bp->tx_fc_in_tbl.dma),
383 bp->tx_fc_in_tbl.ctx_id);
385 rc = bnxt_hwrm_ctx_rgtr(bp, bp->tx_fc_out_tbl.dma,
386 &bp->tx_fc_out_tbl.ctx_id);
391 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
392 " tx_fc_out_tbl.ctx_id = %d\n",
393 bp->tx_fc_out_tbl.va,
394 (void *)((uintptr_t)bp->tx_fc_out_tbl.dma),
395 bp->tx_fc_out_tbl.ctx_id);
397 memset(bp->rx_fc_out_tbl.va, 0, bp->rx_fc_out_tbl.size);
398 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
399 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
400 bp->rx_fc_out_tbl.ctx_id,
406 memset(bp->tx_fc_out_tbl.va, 0, bp->tx_fc_out_tbl.size);
407 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
408 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
409 bp->tx_fc_out_tbl.ctx_id,
416 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
417 struct bnxt_ctx_mem_buf_info *ctx)
422 ctx->va = rte_zmalloc(type, size, 0);
425 rte_mem_lock_page(ctx->va);
427 ctx->dma = rte_mem_virt2iova(ctx->va);
428 if (ctx->dma == RTE_BAD_IOVA)
434 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
436 struct rte_pci_device *pdev = bp->pdev;
437 char type[RTE_MEMZONE_NAMESIZE];
443 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
444 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
445 /* 4 bytes for each counter-id */
446 rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 4, &bp->rx_fc_in_tbl);
450 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
451 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
452 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
453 rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 16, &bp->rx_fc_out_tbl);
457 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
458 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
459 /* 4 bytes for each counter-id */
460 rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 4, &bp->tx_fc_in_tbl);
464 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
465 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
466 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
467 rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 16, &bp->tx_fc_out_tbl);
471 rc = bnxt_register_fc_ctx_mem(bp);
476 static int bnxt_init_ctx_mem(struct bnxt *bp)
480 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
481 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)))
484 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->max_fc);
488 rc = bnxt_init_fc_ctx_mem(bp);
493 static int bnxt_init_chip(struct bnxt *bp)
495 struct rte_eth_link new;
496 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
497 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
498 uint32_t intr_vector = 0;
499 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
500 uint32_t vec = BNXT_MISC_VEC_ID;
504 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
505 bp->eth_dev->data->dev_conf.rxmode.offloads |=
506 DEV_RX_OFFLOAD_JUMBO_FRAME;
507 bp->flags |= BNXT_FLAG_JUMBO;
509 bp->eth_dev->data->dev_conf.rxmode.offloads &=
510 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
511 bp->flags &= ~BNXT_FLAG_JUMBO;
514 /* THOR does not support ring groups.
515 * But we will use the array to save RSS context IDs.
517 if (BNXT_CHIP_THOR(bp))
518 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
520 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
522 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
526 rc = bnxt_alloc_hwrm_rings(bp);
528 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
532 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
534 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
538 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
541 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
542 if (bp->rx_cos_queue[i].id != 0xff) {
543 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
547 "Num pools more than FW profile\n");
551 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
557 rc = bnxt_mq_rx_configure(bp);
559 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
563 /* VNIC configuration */
564 for (i = 0; i < bp->nr_vnics; i++) {
565 rc = bnxt_setup_one_vnic(bp, i);
570 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
573 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
577 /* check and configure queue intr-vector mapping */
578 if ((rte_intr_cap_multiple(intr_handle) ||
579 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
580 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
581 intr_vector = bp->eth_dev->data->nb_rx_queues;
582 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
583 if (intr_vector > bp->rx_cp_nr_rings) {
584 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
588 rc = rte_intr_efd_enable(intr_handle, intr_vector);
593 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
594 intr_handle->intr_vec =
595 rte_zmalloc("intr_vec",
596 bp->eth_dev->data->nb_rx_queues *
598 if (intr_handle->intr_vec == NULL) {
599 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
600 " intr_vec", bp->eth_dev->data->nb_rx_queues);
604 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
605 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
606 intr_handle->intr_vec, intr_handle->nb_efd,
607 intr_handle->max_intr);
608 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
610 intr_handle->intr_vec[queue_id] =
611 vec + BNXT_RX_VEC_START;
612 if (vec < base + intr_handle->nb_efd - 1)
617 /* enable uio/vfio intr/eventfd mapping */
618 rc = rte_intr_enable(intr_handle);
619 #ifndef RTE_EXEC_ENV_FREEBSD
620 /* In FreeBSD OS, nic_uio driver does not support interrupts */
625 rc = bnxt_get_hwrm_link_config(bp, &new);
627 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
631 if (!bp->link_info.link_up) {
632 rc = bnxt_set_hwrm_link_config(bp, true);
635 "HWRM link config failure rc: %x\n", rc);
639 bnxt_print_link_info(bp->eth_dev);
641 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
643 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
648 rte_free(intr_handle->intr_vec);
650 rte_intr_efd_disable(intr_handle);
652 /* Some of the error status returned by FW may not be from errno.h */
659 static int bnxt_shutdown_nic(struct bnxt *bp)
661 bnxt_free_all_hwrm_resources(bp);
662 bnxt_free_all_filters(bp);
663 bnxt_free_all_vnics(bp);
668 * Device configuration and status function
671 static uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
673 uint32_t link_speed = bp->link_info.support_speeds;
674 uint32_t speed_capa = 0;
676 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
677 speed_capa |= ETH_LINK_SPEED_100M;
678 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
679 speed_capa |= ETH_LINK_SPEED_100M_HD;
680 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
681 speed_capa |= ETH_LINK_SPEED_1G;
682 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
683 speed_capa |= ETH_LINK_SPEED_2_5G;
684 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
685 speed_capa |= ETH_LINK_SPEED_10G;
686 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
687 speed_capa |= ETH_LINK_SPEED_20G;
688 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
689 speed_capa |= ETH_LINK_SPEED_25G;
690 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
691 speed_capa |= ETH_LINK_SPEED_40G;
692 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
693 speed_capa |= ETH_LINK_SPEED_50G;
694 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
695 speed_capa |= ETH_LINK_SPEED_100G;
697 if (bp->link_info.auto_mode == HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
698 speed_capa |= ETH_LINK_SPEED_FIXED;
700 speed_capa |= ETH_LINK_SPEED_AUTONEG;
705 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
706 struct rte_eth_dev_info *dev_info)
708 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
709 struct bnxt *bp = eth_dev->data->dev_private;
710 uint16_t max_vnics, i, j, vpool, vrxq;
711 unsigned int max_rx_rings;
714 rc = is_bnxt_in_error(bp);
719 dev_info->max_mac_addrs = bp->max_l2_ctx;
720 dev_info->max_hash_mac_addrs = 0;
722 /* PF/VF specifics */
724 dev_info->max_vfs = pdev->max_vfs;
726 max_rx_rings = BNXT_MAX_RINGS(bp);
727 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
728 dev_info->max_rx_queues = max_rx_rings;
729 dev_info->max_tx_queues = max_rx_rings;
730 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
731 dev_info->hash_key_size = 40;
732 max_vnics = bp->max_vnics;
735 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
736 dev_info->max_mtu = BNXT_MAX_MTU;
738 /* Fast path specifics */
739 dev_info->min_rx_bufsize = 1;
740 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
742 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
743 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
744 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
745 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
746 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
748 dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
751 dev_info->default_rxconf = (struct rte_eth_rxconf) {
757 .rx_free_thresh = 32,
758 /* If no descriptors available, pkts are dropped by default */
762 dev_info->default_txconf = (struct rte_eth_txconf) {
768 .tx_free_thresh = 32,
771 eth_dev->data->dev_conf.intr_conf.lsc = 1;
773 eth_dev->data->dev_conf.intr_conf.rxq = 1;
774 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
775 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
776 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
777 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
782 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
783 * need further investigation.
787 vpool = 64; /* ETH_64_POOLS */
788 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
789 for (i = 0; i < 4; vpool >>= 1, i++) {
790 if (max_vnics > vpool) {
791 for (j = 0; j < 5; vrxq >>= 1, j++) {
792 if (dev_info->max_rx_queues > vrxq) {
798 /* Not enough resources to support VMDq */
802 /* Not enough resources to support VMDq */
806 dev_info->max_vmdq_pools = vpool;
807 dev_info->vmdq_queue_num = vrxq;
809 dev_info->vmdq_pool_base = 0;
810 dev_info->vmdq_queue_base = 0;
815 /* Configure the device based on the configuration provided */
816 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
818 struct bnxt *bp = eth_dev->data->dev_private;
819 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
822 bp->rx_queues = (void *)eth_dev->data->rx_queues;
823 bp->tx_queues = (void *)eth_dev->data->tx_queues;
824 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
825 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
827 rc = is_bnxt_in_error(bp);
831 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
832 rc = bnxt_hwrm_check_vf_rings(bp);
834 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
838 /* If a resource has already been allocated - in this case
839 * it is the async completion ring, free it. Reallocate it after
840 * resource reservation. This will ensure the resource counts
841 * are calculated correctly.
844 pthread_mutex_lock(&bp->def_cp_lock);
846 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
847 bnxt_disable_int(bp);
848 bnxt_free_cp_ring(bp, bp->async_cp_ring);
851 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
853 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
854 pthread_mutex_unlock(&bp->def_cp_lock);
858 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
859 rc = bnxt_alloc_async_cp_ring(bp);
861 pthread_mutex_unlock(&bp->def_cp_lock);
867 pthread_mutex_unlock(&bp->def_cp_lock);
869 /* legacy driver needs to get updated values */
870 rc = bnxt_hwrm_func_qcaps(bp);
872 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
877 /* Inherit new configurations */
878 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
879 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
880 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
881 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
882 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
886 if (BNXT_HAS_RING_GRPS(bp) &&
887 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
890 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
891 bp->max_vnics < eth_dev->data->nb_rx_queues)
894 bp->rx_cp_nr_rings = bp->rx_nr_rings;
895 bp->tx_cp_nr_rings = bp->tx_nr_rings;
897 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
898 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
899 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
901 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
903 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
904 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
906 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
912 "Insufficient resources to support requested config\n");
914 "Num Queues Requested: Tx %d, Rx %d\n",
915 eth_dev->data->nb_tx_queues,
916 eth_dev->data->nb_rx_queues);
918 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
919 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
920 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
924 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
926 struct rte_eth_link *link = ð_dev->data->dev_link;
928 if (link->link_status)
929 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
930 eth_dev->data->port_id,
931 (uint32_t)link->link_speed,
932 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
933 ("full-duplex") : ("half-duplex\n"));
935 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
936 eth_dev->data->port_id);
940 * Determine whether the current configuration requires support for scattered
941 * receive; return 1 if scattered receive is required and 0 if not.
943 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
948 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
951 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
952 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
954 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
955 RTE_PKTMBUF_HEADROOM);
956 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
962 static eth_rx_burst_t
963 bnxt_receive_function(struct rte_eth_dev *eth_dev)
965 struct bnxt *bp = eth_dev->data->dev_private;
968 #ifndef RTE_LIBRTE_IEEE1588
970 * Vector mode receive can be enabled only if scatter rx is not
971 * in use and rx offloads are limited to VLAN stripping and
974 if (!eth_dev->data->scattered_rx &&
975 !(eth_dev->data->dev_conf.rxmode.offloads &
976 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
977 DEV_RX_OFFLOAD_KEEP_CRC |
978 DEV_RX_OFFLOAD_JUMBO_FRAME |
979 DEV_RX_OFFLOAD_IPV4_CKSUM |
980 DEV_RX_OFFLOAD_UDP_CKSUM |
981 DEV_RX_OFFLOAD_TCP_CKSUM |
982 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
983 DEV_RX_OFFLOAD_RSS_HASH |
984 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
986 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
987 eth_dev->data->port_id);
988 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
989 return bnxt_recv_pkts_vec;
991 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
992 eth_dev->data->port_id);
994 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
995 eth_dev->data->port_id,
996 eth_dev->data->scattered_rx,
997 eth_dev->data->dev_conf.rxmode.offloads);
1000 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1001 return bnxt_recv_pkts;
1004 static eth_tx_burst_t
1005 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1008 #ifndef RTE_LIBRTE_IEEE1588
1010 * Vector mode transmit can be enabled only if not using scatter rx
1013 if (!eth_dev->data->scattered_rx &&
1014 !eth_dev->data->dev_conf.txmode.offloads) {
1015 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1016 eth_dev->data->port_id);
1017 return bnxt_xmit_pkts_vec;
1019 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1020 eth_dev->data->port_id);
1022 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1023 eth_dev->data->port_id,
1024 eth_dev->data->scattered_rx,
1025 eth_dev->data->dev_conf.txmode.offloads);
1028 return bnxt_xmit_pkts;
1031 static int bnxt_handle_if_change_status(struct bnxt *bp)
1035 /* Since fw has undergone a reset and lost all contexts,
1036 * set fatal flag to not issue hwrm during cleanup
1038 bp->flags |= BNXT_FLAG_FATAL_ERROR;
1039 bnxt_uninit_resources(bp, true);
1041 /* clear fatal flag so that re-init happens */
1042 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1043 rc = bnxt_init_resources(bp, true);
1045 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1050 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1052 struct bnxt *bp = eth_dev->data->dev_private;
1053 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1055 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1057 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1058 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1062 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1064 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1065 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1069 rc = bnxt_hwrm_if_change(bp, true);
1070 if (rc == 0 || rc != -EAGAIN)
1073 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1074 } while (retry_cnt--);
1079 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1080 rc = bnxt_handle_if_change_status(bp);
1085 bnxt_enable_int(bp);
1087 rc = bnxt_init_chip(bp);
1091 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1092 eth_dev->data->dev_started = 1;
1094 bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1096 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1097 vlan_mask |= ETH_VLAN_FILTER_MASK;
1098 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1099 vlan_mask |= ETH_VLAN_STRIP_MASK;
1100 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1104 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1105 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1107 pthread_mutex_lock(&bp->def_cp_lock);
1108 bnxt_schedule_fw_health_check(bp);
1109 pthread_mutex_unlock(&bp->def_cp_lock);
1117 bnxt_shutdown_nic(bp);
1118 bnxt_free_tx_mbufs(bp);
1119 bnxt_free_rx_mbufs(bp);
1120 bnxt_hwrm_if_change(bp, false);
1121 eth_dev->data->dev_started = 0;
1125 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1127 struct bnxt *bp = eth_dev->data->dev_private;
1130 if (!bp->link_info.link_up)
1131 rc = bnxt_set_hwrm_link_config(bp, true);
1133 eth_dev->data->dev_link.link_status = 1;
1135 bnxt_print_link_info(eth_dev);
1139 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1141 struct bnxt *bp = eth_dev->data->dev_private;
1143 eth_dev->data->dev_link.link_status = 0;
1144 bnxt_set_hwrm_link_config(bp, false);
1145 bp->link_info.link_up = 0;
1150 /* Unload the driver, release resources */
1151 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1153 struct bnxt *bp = eth_dev->data->dev_private;
1154 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1155 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1158 bnxt_ulp_deinit(bp);
1160 eth_dev->data->dev_started = 0;
1161 /* Prevent crashes when queues are still in use */
1162 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1163 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1165 bnxt_disable_int(bp);
1167 /* disable uio/vfio intr/eventfd mapping */
1168 rte_intr_disable(intr_handle);
1170 bnxt_cancel_fw_health_check(bp);
1172 bnxt_dev_set_link_down_op(eth_dev);
1174 /* Wait for link to be reset and the async notification to process.
1175 * During reset recovery, there is no need to wait and
1176 * VF/NPAR functions do not have privilege to change PHY config.
1178 if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1179 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1181 /* Clean queue intr-vector mapping */
1182 rte_intr_efd_disable(intr_handle);
1183 if (intr_handle->intr_vec != NULL) {
1184 rte_free(intr_handle->intr_vec);
1185 intr_handle->intr_vec = NULL;
1188 bnxt_hwrm_port_clr_stats(bp);
1189 bnxt_free_tx_mbufs(bp);
1190 bnxt_free_rx_mbufs(bp);
1191 /* Process any remaining notifications in default completion queue */
1192 bnxt_int_handler(eth_dev);
1193 bnxt_shutdown_nic(bp);
1194 bnxt_hwrm_if_change(bp, false);
1196 rte_free(bp->mark_table);
1197 bp->mark_table = NULL;
1199 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1200 bp->rx_cosq_cnt = 0;
1203 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1205 struct bnxt *bp = eth_dev->data->dev_private;
1207 /* cancel the recovery handler before remove dev */
1208 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1209 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1210 bnxt_cancel_fc_thread(bp);
1212 if (eth_dev->data->dev_started)
1213 bnxt_dev_stop_op(eth_dev);
1215 bnxt_uninit_resources(bp, false);
1217 eth_dev->dev_ops = NULL;
1218 eth_dev->rx_pkt_burst = NULL;
1219 eth_dev->tx_pkt_burst = NULL;
1221 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1222 bp->tx_mem_zone = NULL;
1223 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1224 bp->rx_mem_zone = NULL;
1226 rte_free(bp->pf.vf_info);
1227 bp->pf.vf_info = NULL;
1229 rte_free(bp->grp_info);
1230 bp->grp_info = NULL;
1233 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1236 struct bnxt *bp = eth_dev->data->dev_private;
1237 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1238 struct bnxt_vnic_info *vnic;
1239 struct bnxt_filter_info *filter, *temp_filter;
1242 if (is_bnxt_in_error(bp))
1246 * Loop through all VNICs from the specified filter flow pools to
1247 * remove the corresponding MAC addr filter
1249 for (i = 0; i < bp->nr_vnics; i++) {
1250 if (!(pool_mask & (1ULL << i)))
1253 vnic = &bp->vnic_info[i];
1254 filter = STAILQ_FIRST(&vnic->filter);
1256 temp_filter = STAILQ_NEXT(filter, next);
1257 if (filter->mac_index == index) {
1258 STAILQ_REMOVE(&vnic->filter, filter,
1259 bnxt_filter_info, next);
1260 bnxt_hwrm_clear_l2_filter(bp, filter);
1261 bnxt_free_filter(bp, filter);
1263 filter = temp_filter;
1268 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1269 struct rte_ether_addr *mac_addr, uint32_t index,
1272 struct bnxt_filter_info *filter;
1275 /* Attach requested MAC address to the new l2_filter */
1276 STAILQ_FOREACH(filter, &vnic->filter, next) {
1277 if (filter->mac_index == index) {
1279 "MAC addr already existed for pool %d\n",
1285 filter = bnxt_alloc_filter(bp);
1287 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1291 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1292 * if the MAC that's been programmed now is a different one, then,
1293 * copy that addr to filter->l2_addr
1296 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1297 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1299 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1301 filter->mac_index = index;
1302 if (filter->mac_index == 0)
1303 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1305 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1307 bnxt_free_filter(bp, filter);
1313 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1314 struct rte_ether_addr *mac_addr,
1315 uint32_t index, uint32_t pool)
1317 struct bnxt *bp = eth_dev->data->dev_private;
1318 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1321 rc = is_bnxt_in_error(bp);
1325 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1326 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1331 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1335 /* Filter settings will get applied when port is started */
1336 if (!eth_dev->data->dev_started)
1339 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1344 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1345 bool exp_link_status)
1348 struct bnxt *bp = eth_dev->data->dev_private;
1349 struct rte_eth_link new;
1350 int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1351 BNXT_LINK_DOWN_WAIT_CNT;
1353 rc = is_bnxt_in_error(bp);
1357 memset(&new, 0, sizeof(new));
1359 /* Retrieve link info from hardware */
1360 rc = bnxt_get_hwrm_link_config(bp, &new);
1362 new.link_speed = ETH_LINK_SPEED_100M;
1363 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1365 "Failed to retrieve link rc = 0x%x!\n", rc);
1369 if (!wait_to_complete || new.link_status == exp_link_status)
1372 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1376 /* Timed out or success */
1377 if (new.link_status != eth_dev->data->dev_link.link_status ||
1378 new.link_speed != eth_dev->data->dev_link.link_speed) {
1379 rte_eth_linkstatus_set(eth_dev, &new);
1381 _rte_eth_dev_callback_process(eth_dev,
1382 RTE_ETH_EVENT_INTR_LSC,
1385 bnxt_print_link_info(eth_dev);
1391 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1392 int wait_to_complete)
1394 return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1397 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1399 struct bnxt *bp = eth_dev->data->dev_private;
1400 struct bnxt_vnic_info *vnic;
1404 rc = is_bnxt_in_error(bp);
1408 /* Filter settings will get applied when port is started */
1409 if (!eth_dev->data->dev_started)
1412 if (bp->vnic_info == NULL)
1415 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1417 old_flags = vnic->flags;
1418 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1419 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1421 vnic->flags = old_flags;
1426 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1428 struct bnxt *bp = eth_dev->data->dev_private;
1429 struct bnxt_vnic_info *vnic;
1433 rc = is_bnxt_in_error(bp);
1437 /* Filter settings will get applied when port is started */
1438 if (!eth_dev->data->dev_started)
1441 if (bp->vnic_info == NULL)
1444 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1446 old_flags = vnic->flags;
1447 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1448 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1450 vnic->flags = old_flags;
1455 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1457 struct bnxt *bp = eth_dev->data->dev_private;
1458 struct bnxt_vnic_info *vnic;
1462 rc = is_bnxt_in_error(bp);
1466 /* Filter settings will get applied when port is started */
1467 if (!eth_dev->data->dev_started)
1470 if (bp->vnic_info == NULL)
1473 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1475 old_flags = vnic->flags;
1476 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1477 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1479 vnic->flags = old_flags;
1484 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1486 struct bnxt *bp = eth_dev->data->dev_private;
1487 struct bnxt_vnic_info *vnic;
1491 rc = is_bnxt_in_error(bp);
1495 /* Filter settings will get applied when port is started */
1496 if (!eth_dev->data->dev_started)
1499 if (bp->vnic_info == NULL)
1502 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1504 old_flags = vnic->flags;
1505 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1506 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1508 vnic->flags = old_flags;
1513 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1514 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1516 if (qid >= bp->rx_nr_rings)
1519 return bp->eth_dev->data->rx_queues[qid];
1522 /* Return rxq corresponding to a given rss table ring/group ID. */
1523 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1525 struct bnxt_rx_queue *rxq;
1528 if (!BNXT_HAS_RING_GRPS(bp)) {
1529 for (i = 0; i < bp->rx_nr_rings; i++) {
1530 rxq = bp->eth_dev->data->rx_queues[i];
1531 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1535 for (i = 0; i < bp->rx_nr_rings; i++) {
1536 if (bp->grp_info[i].fw_grp_id == fwr)
1541 return INVALID_HW_RING_ID;
1544 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1545 struct rte_eth_rss_reta_entry64 *reta_conf,
1548 struct bnxt *bp = eth_dev->data->dev_private;
1549 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1550 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1551 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1555 rc = is_bnxt_in_error(bp);
1559 if (!vnic->rss_table)
1562 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1565 if (reta_size != tbl_size) {
1566 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1567 "(%d) must equal the size supported by the hardware "
1568 "(%d)\n", reta_size, tbl_size);
1572 for (i = 0; i < reta_size; i++) {
1573 struct bnxt_rx_queue *rxq;
1575 idx = i / RTE_RETA_GROUP_SIZE;
1576 sft = i % RTE_RETA_GROUP_SIZE;
1578 if (!(reta_conf[idx].mask & (1ULL << sft)))
1581 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1583 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1587 if (BNXT_CHIP_THOR(bp)) {
1588 vnic->rss_table[i * 2] =
1589 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1590 vnic->rss_table[i * 2 + 1] =
1591 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1593 vnic->rss_table[i] =
1594 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1598 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1602 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1603 struct rte_eth_rss_reta_entry64 *reta_conf,
1606 struct bnxt *bp = eth_dev->data->dev_private;
1607 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1608 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1609 uint16_t idx, sft, i;
1612 rc = is_bnxt_in_error(bp);
1616 /* Retrieve from the default VNIC */
1619 if (!vnic->rss_table)
1622 if (reta_size != tbl_size) {
1623 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1624 "(%d) must equal the size supported by the hardware "
1625 "(%d)\n", reta_size, tbl_size);
1629 for (idx = 0, i = 0; i < reta_size; i++) {
1630 idx = i / RTE_RETA_GROUP_SIZE;
1631 sft = i % RTE_RETA_GROUP_SIZE;
1633 if (reta_conf[idx].mask & (1ULL << sft)) {
1636 if (BNXT_CHIP_THOR(bp))
1637 qid = bnxt_rss_to_qid(bp,
1638 vnic->rss_table[i * 2]);
1640 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1642 if (qid == INVALID_HW_RING_ID) {
1643 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1646 reta_conf[idx].reta[sft] = qid;
1653 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1654 struct rte_eth_rss_conf *rss_conf)
1656 struct bnxt *bp = eth_dev->data->dev_private;
1657 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1658 struct bnxt_vnic_info *vnic;
1661 rc = is_bnxt_in_error(bp);
1666 * If RSS enablement were different than dev_configure,
1667 * then return -EINVAL
1669 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1670 if (!rss_conf->rss_hf)
1671 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1673 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1677 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1678 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1680 /* Update the default RSS VNIC(s) */
1681 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1682 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1685 * If hashkey is not specified, use the previously configured
1688 if (!rss_conf->rss_key)
1691 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1693 "Invalid hashkey length, should be 16 bytes\n");
1696 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1699 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1703 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1704 struct rte_eth_rss_conf *rss_conf)
1706 struct bnxt *bp = eth_dev->data->dev_private;
1707 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1709 uint32_t hash_types;
1711 rc = is_bnxt_in_error(bp);
1715 /* RSS configuration is the same for all VNICs */
1716 if (vnic && vnic->rss_hash_key) {
1717 if (rss_conf->rss_key) {
1718 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1719 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1720 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1723 hash_types = vnic->hash_type;
1724 rss_conf->rss_hf = 0;
1725 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1726 rss_conf->rss_hf |= ETH_RSS_IPV4;
1727 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1729 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1730 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1732 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1734 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1735 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1737 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1739 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1740 rss_conf->rss_hf |= ETH_RSS_IPV6;
1741 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1743 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1744 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1746 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1748 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1749 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1751 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1755 "Unknown RSS config from firmware (%08x), RSS disabled",
1760 rss_conf->rss_hf = 0;
1765 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1766 struct rte_eth_fc_conf *fc_conf)
1768 struct bnxt *bp = dev->data->dev_private;
1769 struct rte_eth_link link_info;
1772 rc = is_bnxt_in_error(bp);
1776 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1780 memset(fc_conf, 0, sizeof(*fc_conf));
1781 if (bp->link_info.auto_pause)
1782 fc_conf->autoneg = 1;
1783 switch (bp->link_info.pause) {
1785 fc_conf->mode = RTE_FC_NONE;
1787 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1788 fc_conf->mode = RTE_FC_TX_PAUSE;
1790 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1791 fc_conf->mode = RTE_FC_RX_PAUSE;
1793 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1794 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1795 fc_conf->mode = RTE_FC_FULL;
1801 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1802 struct rte_eth_fc_conf *fc_conf)
1804 struct bnxt *bp = dev->data->dev_private;
1807 rc = is_bnxt_in_error(bp);
1811 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1812 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1816 switch (fc_conf->mode) {
1818 bp->link_info.auto_pause = 0;
1819 bp->link_info.force_pause = 0;
1821 case RTE_FC_RX_PAUSE:
1822 if (fc_conf->autoneg) {
1823 bp->link_info.auto_pause =
1824 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1825 bp->link_info.force_pause = 0;
1827 bp->link_info.auto_pause = 0;
1828 bp->link_info.force_pause =
1829 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1832 case RTE_FC_TX_PAUSE:
1833 if (fc_conf->autoneg) {
1834 bp->link_info.auto_pause =
1835 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1836 bp->link_info.force_pause = 0;
1838 bp->link_info.auto_pause = 0;
1839 bp->link_info.force_pause =
1840 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1844 if (fc_conf->autoneg) {
1845 bp->link_info.auto_pause =
1846 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1847 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1848 bp->link_info.force_pause = 0;
1850 bp->link_info.auto_pause = 0;
1851 bp->link_info.force_pause =
1852 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1853 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1857 return bnxt_set_hwrm_link_config(bp, true);
1860 /* Add UDP tunneling port */
1862 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1863 struct rte_eth_udp_tunnel *udp_tunnel)
1865 struct bnxt *bp = eth_dev->data->dev_private;
1866 uint16_t tunnel_type = 0;
1869 rc = is_bnxt_in_error(bp);
1873 switch (udp_tunnel->prot_type) {
1874 case RTE_TUNNEL_TYPE_VXLAN:
1875 if (bp->vxlan_port_cnt) {
1876 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1877 udp_tunnel->udp_port);
1878 if (bp->vxlan_port != udp_tunnel->udp_port) {
1879 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1882 bp->vxlan_port_cnt++;
1886 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1887 bp->vxlan_port_cnt++;
1889 case RTE_TUNNEL_TYPE_GENEVE:
1890 if (bp->geneve_port_cnt) {
1891 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1892 udp_tunnel->udp_port);
1893 if (bp->geneve_port != udp_tunnel->udp_port) {
1894 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1897 bp->geneve_port_cnt++;
1901 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1902 bp->geneve_port_cnt++;
1905 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1908 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1914 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1915 struct rte_eth_udp_tunnel *udp_tunnel)
1917 struct bnxt *bp = eth_dev->data->dev_private;
1918 uint16_t tunnel_type = 0;
1922 rc = is_bnxt_in_error(bp);
1926 switch (udp_tunnel->prot_type) {
1927 case RTE_TUNNEL_TYPE_VXLAN:
1928 if (!bp->vxlan_port_cnt) {
1929 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1932 if (bp->vxlan_port != udp_tunnel->udp_port) {
1933 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1934 udp_tunnel->udp_port, bp->vxlan_port);
1937 if (--bp->vxlan_port_cnt)
1941 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1942 port = bp->vxlan_fw_dst_port_id;
1944 case RTE_TUNNEL_TYPE_GENEVE:
1945 if (!bp->geneve_port_cnt) {
1946 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1949 if (bp->geneve_port != udp_tunnel->udp_port) {
1950 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1951 udp_tunnel->udp_port, bp->geneve_port);
1954 if (--bp->geneve_port_cnt)
1958 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1959 port = bp->geneve_fw_dst_port_id;
1962 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1966 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1969 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1972 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1973 bp->geneve_port = 0;
1978 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1980 struct bnxt_filter_info *filter;
1981 struct bnxt_vnic_info *vnic;
1983 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1985 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1986 filter = STAILQ_FIRST(&vnic->filter);
1988 /* Search for this matching MAC+VLAN filter */
1989 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
1990 /* Delete the filter */
1991 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1994 STAILQ_REMOVE(&vnic->filter, filter,
1995 bnxt_filter_info, next);
1996 bnxt_free_filter(bp, filter);
1998 "Deleted vlan filter for %d\n",
2002 filter = STAILQ_NEXT(filter, next);
2007 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2009 struct bnxt_filter_info *filter;
2010 struct bnxt_vnic_info *vnic;
2012 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2013 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2014 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2016 /* Implementation notes on the use of VNIC in this command:
2018 * By default, these filters belong to default vnic for the function.
2019 * Once these filters are set up, only destination VNIC can be modified.
2020 * If the destination VNIC is not specified in this command,
2021 * then the HWRM shall only create an l2 context id.
2024 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2025 filter = STAILQ_FIRST(&vnic->filter);
2026 /* Check if the VLAN has already been added */
2028 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2031 filter = STAILQ_NEXT(filter, next);
2034 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2035 * command to create MAC+VLAN filter with the right flags, enables set.
2037 filter = bnxt_alloc_filter(bp);
2040 "MAC/VLAN filter alloc failed\n");
2043 /* MAC + VLAN ID filter */
2044 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2045 * untagged packets are received
2047 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2048 * packets and only the programmed vlan's packets are received
2050 filter->l2_ivlan = vlan_id;
2051 filter->l2_ivlan_mask = 0x0FFF;
2052 filter->enables |= en;
2053 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2055 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2057 /* Free the newly allocated filter as we were
2058 * not able to create the filter in hardware.
2060 bnxt_free_filter(bp, filter);
2064 filter->mac_index = 0;
2065 /* Add this new filter to the list */
2067 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2069 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2072 "Added Vlan filter for %d\n", vlan_id);
2076 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2077 uint16_t vlan_id, int on)
2079 struct bnxt *bp = eth_dev->data->dev_private;
2082 rc = is_bnxt_in_error(bp);
2086 if (!eth_dev->data->dev_started) {
2087 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2091 /* These operations apply to ALL existing MAC/VLAN filters */
2093 return bnxt_add_vlan_filter(bp, vlan_id);
2095 return bnxt_del_vlan_filter(bp, vlan_id);
2098 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2099 struct bnxt_vnic_info *vnic)
2101 struct bnxt_filter_info *filter;
2104 filter = STAILQ_FIRST(&vnic->filter);
2106 if (filter->mac_index == 0 &&
2107 !memcmp(filter->l2_addr, bp->mac_addr,
2108 RTE_ETHER_ADDR_LEN)) {
2109 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2111 STAILQ_REMOVE(&vnic->filter, filter,
2112 bnxt_filter_info, next);
2113 bnxt_free_filter(bp, filter);
2117 filter = STAILQ_NEXT(filter, next);
2123 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2125 struct bnxt_vnic_info *vnic;
2129 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2130 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2131 /* Remove any VLAN filters programmed */
2132 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2133 bnxt_del_vlan_filter(bp, i);
2135 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2139 /* Default filter will allow packets that match the
2140 * dest mac. So, it has to be deleted, otherwise, we
2141 * will endup receiving vlan packets for which the
2142 * filter is not programmed, when hw-vlan-filter
2143 * configuration is ON
2145 bnxt_del_dflt_mac_filter(bp, vnic);
2146 /* This filter will allow only untagged packets */
2147 bnxt_add_vlan_filter(bp, 0);
2149 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2150 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2155 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2157 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2161 /* Destroy vnic filters and vnic */
2162 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2163 DEV_RX_OFFLOAD_VLAN_FILTER) {
2164 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2165 bnxt_del_vlan_filter(bp, i);
2167 bnxt_del_dflt_mac_filter(bp, vnic);
2169 rc = bnxt_hwrm_vnic_free(bp, vnic);
2173 rte_free(vnic->fw_grp_ids);
2174 vnic->fw_grp_ids = NULL;
2176 vnic->rx_queue_cnt = 0;
2182 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2184 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2187 /* Destroy, recreate and reconfigure the default vnic */
2188 rc = bnxt_free_one_vnic(bp, 0);
2192 /* default vnic 0 */
2193 rc = bnxt_setup_one_vnic(bp, 0);
2197 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2198 DEV_RX_OFFLOAD_VLAN_FILTER) {
2199 rc = bnxt_add_vlan_filter(bp, 0);
2202 rc = bnxt_restore_vlan_filters(bp);
2206 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2211 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2215 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2216 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2222 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2224 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2225 struct bnxt *bp = dev->data->dev_private;
2228 rc = is_bnxt_in_error(bp);
2232 /* Filter settings will get applied when port is started */
2233 if (!dev->data->dev_started)
2236 if (mask & ETH_VLAN_FILTER_MASK) {
2237 /* Enable or disable VLAN filtering */
2238 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2243 if (mask & ETH_VLAN_STRIP_MASK) {
2244 /* Enable or disable VLAN stripping */
2245 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2250 if (mask & ETH_VLAN_EXTEND_MASK) {
2251 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2252 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2254 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2261 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2264 struct bnxt *bp = dev->data->dev_private;
2265 int qinq = dev->data->dev_conf.rxmode.offloads &
2266 DEV_RX_OFFLOAD_VLAN_EXTEND;
2268 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2269 vlan_type != ETH_VLAN_TYPE_OUTER) {
2271 "Unsupported vlan type.");
2276 "QinQ not enabled. Needs to be ON as we can "
2277 "accelerate only outer vlan\n");
2281 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2283 case RTE_ETHER_TYPE_QINQ:
2285 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2287 case RTE_ETHER_TYPE_VLAN:
2289 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2293 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2297 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2301 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2304 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2307 bp->outer_tpid_bd |= tpid;
2308 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2309 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2311 "Can accelerate only outer vlan in QinQ\n");
2319 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2320 struct rte_ether_addr *addr)
2322 struct bnxt *bp = dev->data->dev_private;
2323 /* Default Filter is tied to VNIC 0 */
2324 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2327 rc = is_bnxt_in_error(bp);
2331 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2334 if (rte_is_zero_ether_addr(addr))
2337 /* Filter settings will get applied when port is started */
2338 if (!dev->data->dev_started)
2341 /* Check if the requested MAC is already added */
2342 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2345 /* Destroy filter and re-create it */
2346 bnxt_del_dflt_mac_filter(bp, vnic);
2348 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2349 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2350 /* This filter will allow only untagged packets */
2351 rc = bnxt_add_vlan_filter(bp, 0);
2353 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2356 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2361 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2362 struct rte_ether_addr *mc_addr_set,
2363 uint32_t nb_mc_addr)
2365 struct bnxt *bp = eth_dev->data->dev_private;
2366 char *mc_addr_list = (char *)mc_addr_set;
2367 struct bnxt_vnic_info *vnic;
2368 uint32_t off = 0, i = 0;
2371 rc = is_bnxt_in_error(bp);
2375 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2377 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2378 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2382 /* TODO Check for Duplicate mcast addresses */
2383 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2384 for (i = 0; i < nb_mc_addr; i++) {
2385 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2386 RTE_ETHER_ADDR_LEN);
2387 off += RTE_ETHER_ADDR_LEN;
2390 vnic->mc_addr_cnt = i;
2391 if (vnic->mc_addr_cnt)
2392 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2394 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2397 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2401 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2403 struct bnxt *bp = dev->data->dev_private;
2404 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2405 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2406 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2407 uint8_t fw_rsvd = bp->fw_ver & 0xff;
2410 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2411 fw_major, fw_minor, fw_updt, fw_rsvd);
2413 ret += 1; /* add the size of '\0' */
2414 if (fw_size < (uint32_t)ret)
2421 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2422 struct rte_eth_rxq_info *qinfo)
2424 struct bnxt *bp = dev->data->dev_private;
2425 struct bnxt_rx_queue *rxq;
2427 if (is_bnxt_in_error(bp))
2430 rxq = dev->data->rx_queues[queue_id];
2432 qinfo->mp = rxq->mb_pool;
2433 qinfo->scattered_rx = dev->data->scattered_rx;
2434 qinfo->nb_desc = rxq->nb_rx_desc;
2436 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2437 qinfo->conf.rx_drop_en = 0;
2438 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2442 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2443 struct rte_eth_txq_info *qinfo)
2445 struct bnxt *bp = dev->data->dev_private;
2446 struct bnxt_tx_queue *txq;
2448 if (is_bnxt_in_error(bp))
2451 txq = dev->data->tx_queues[queue_id];
2453 qinfo->nb_desc = txq->nb_tx_desc;
2455 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2456 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2457 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2459 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2460 qinfo->conf.tx_rs_thresh = 0;
2461 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2464 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2466 struct bnxt *bp = eth_dev->data->dev_private;
2467 uint32_t new_pkt_size;
2471 rc = is_bnxt_in_error(bp);
2475 /* Exit if receive queues are not configured yet */
2476 if (!eth_dev->data->nb_rx_queues)
2479 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2480 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2484 * If vector-mode tx/rx is active, disallow any MTU change that would
2485 * require scattered receive support.
2487 if (eth_dev->data->dev_started &&
2488 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2489 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2491 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2493 "MTU change would require scattered rx support. ");
2494 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2499 if (new_mtu > RTE_ETHER_MTU) {
2500 bp->flags |= BNXT_FLAG_JUMBO;
2501 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2502 DEV_RX_OFFLOAD_JUMBO_FRAME;
2504 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2505 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2506 bp->flags &= ~BNXT_FLAG_JUMBO;
2509 /* Is there a change in mtu setting? */
2510 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2513 for (i = 0; i < bp->nr_vnics; i++) {
2514 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2517 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2518 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2522 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2523 size -= RTE_PKTMBUF_HEADROOM;
2525 if (size < new_mtu) {
2526 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2533 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2535 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2541 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2543 struct bnxt *bp = dev->data->dev_private;
2544 uint16_t vlan = bp->vlan;
2547 rc = is_bnxt_in_error(bp);
2551 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2553 "PVID cannot be modified for this function\n");
2556 bp->vlan = on ? pvid : 0;
2558 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2565 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2567 struct bnxt *bp = dev->data->dev_private;
2570 rc = is_bnxt_in_error(bp);
2574 return bnxt_hwrm_port_led_cfg(bp, true);
2578 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2580 struct bnxt *bp = dev->data->dev_private;
2583 rc = is_bnxt_in_error(bp);
2587 return bnxt_hwrm_port_led_cfg(bp, false);
2591 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2593 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2594 uint32_t desc = 0, raw_cons = 0, cons;
2595 struct bnxt_cp_ring_info *cpr;
2596 struct bnxt_rx_queue *rxq;
2597 struct rx_pkt_cmpl *rxcmp;
2600 rc = is_bnxt_in_error(bp);
2604 rxq = dev->data->rx_queues[rx_queue_id];
2606 raw_cons = cpr->cp_raw_cons;
2609 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2610 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2611 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2613 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2625 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2627 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2628 struct bnxt_rx_ring_info *rxr;
2629 struct bnxt_cp_ring_info *cpr;
2630 struct bnxt_sw_rx_bd *rx_buf;
2631 struct rx_pkt_cmpl *rxcmp;
2632 uint32_t cons, cp_cons;
2638 rc = is_bnxt_in_error(rxq->bp);
2645 if (offset >= rxq->nb_rx_desc)
2648 cons = RING_CMP(cpr->cp_ring_struct, offset);
2649 cp_cons = cpr->cp_raw_cons;
2650 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2652 if (cons > cp_cons) {
2653 if (CMPL_VALID(rxcmp, cpr->valid))
2654 return RTE_ETH_RX_DESC_DONE;
2656 if (CMPL_VALID(rxcmp, !cpr->valid))
2657 return RTE_ETH_RX_DESC_DONE;
2659 rx_buf = &rxr->rx_buf_ring[cons];
2660 if (rx_buf->mbuf == NULL)
2661 return RTE_ETH_RX_DESC_UNAVAIL;
2664 return RTE_ETH_RX_DESC_AVAIL;
2668 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2670 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2671 struct bnxt_tx_ring_info *txr;
2672 struct bnxt_cp_ring_info *cpr;
2673 struct bnxt_sw_tx_bd *tx_buf;
2674 struct tx_pkt_cmpl *txcmp;
2675 uint32_t cons, cp_cons;
2681 rc = is_bnxt_in_error(txq->bp);
2688 if (offset >= txq->nb_tx_desc)
2691 cons = RING_CMP(cpr->cp_ring_struct, offset);
2692 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2693 cp_cons = cpr->cp_raw_cons;
2695 if (cons > cp_cons) {
2696 if (CMPL_VALID(txcmp, cpr->valid))
2697 return RTE_ETH_TX_DESC_UNAVAIL;
2699 if (CMPL_VALID(txcmp, !cpr->valid))
2700 return RTE_ETH_TX_DESC_UNAVAIL;
2702 tx_buf = &txr->tx_buf_ring[cons];
2703 if (tx_buf->mbuf == NULL)
2704 return RTE_ETH_TX_DESC_DONE;
2706 return RTE_ETH_TX_DESC_FULL;
2709 static struct bnxt_filter_info *
2710 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2711 struct rte_eth_ethertype_filter *efilter,
2712 struct bnxt_vnic_info *vnic0,
2713 struct bnxt_vnic_info *vnic,
2716 struct bnxt_filter_info *mfilter = NULL;
2720 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2721 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2722 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2723 " ethertype filter.", efilter->ether_type);
2727 if (efilter->queue >= bp->rx_nr_rings) {
2728 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2733 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2734 vnic = &bp->vnic_info[efilter->queue];
2736 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2741 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2742 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2743 if ((!memcmp(efilter->mac_addr.addr_bytes,
2744 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2746 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2747 mfilter->ethertype == efilter->ether_type)) {
2753 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2754 if ((!memcmp(efilter->mac_addr.addr_bytes,
2755 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2756 mfilter->ethertype == efilter->ether_type &&
2758 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2772 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2773 enum rte_filter_op filter_op,
2776 struct bnxt *bp = dev->data->dev_private;
2777 struct rte_eth_ethertype_filter *efilter =
2778 (struct rte_eth_ethertype_filter *)arg;
2779 struct bnxt_filter_info *bfilter, *filter1;
2780 struct bnxt_vnic_info *vnic, *vnic0;
2783 if (filter_op == RTE_ETH_FILTER_NOP)
2787 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2792 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2793 vnic = &bp->vnic_info[efilter->queue];
2795 switch (filter_op) {
2796 case RTE_ETH_FILTER_ADD:
2797 bnxt_match_and_validate_ether_filter(bp, efilter,
2802 bfilter = bnxt_get_unused_filter(bp);
2803 if (bfilter == NULL) {
2805 "Not enough resources for a new filter.\n");
2808 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2809 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2810 RTE_ETHER_ADDR_LEN);
2811 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2812 RTE_ETHER_ADDR_LEN);
2813 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2814 bfilter->ethertype = efilter->ether_type;
2815 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2817 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2818 if (filter1 == NULL) {
2823 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2824 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2826 bfilter->dst_id = vnic->fw_vnic_id;
2828 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2830 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2833 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2836 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2838 case RTE_ETH_FILTER_DELETE:
2839 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2841 if (ret == -EEXIST) {
2842 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2844 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2846 bnxt_free_filter(bp, filter1);
2847 } else if (ret == 0) {
2848 PMD_DRV_LOG(ERR, "No matching filter found\n");
2852 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2858 bnxt_free_filter(bp, bfilter);
2864 parse_ntuple_filter(struct bnxt *bp,
2865 struct rte_eth_ntuple_filter *nfilter,
2866 struct bnxt_filter_info *bfilter)
2870 if (nfilter->queue >= bp->rx_nr_rings) {
2871 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2875 switch (nfilter->dst_port_mask) {
2877 bfilter->dst_port_mask = -1;
2878 bfilter->dst_port = nfilter->dst_port;
2879 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2880 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2883 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2887 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2888 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2890 switch (nfilter->proto_mask) {
2892 if (nfilter->proto == 17) /* IPPROTO_UDP */
2893 bfilter->ip_protocol = 17;
2894 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2895 bfilter->ip_protocol = 6;
2898 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2901 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2905 switch (nfilter->dst_ip_mask) {
2907 bfilter->dst_ipaddr_mask[0] = -1;
2908 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2909 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2910 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2913 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2917 switch (nfilter->src_ip_mask) {
2919 bfilter->src_ipaddr_mask[0] = -1;
2920 bfilter->src_ipaddr[0] = nfilter->src_ip;
2921 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2922 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2925 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2929 switch (nfilter->src_port_mask) {
2931 bfilter->src_port_mask = -1;
2932 bfilter->src_port = nfilter->src_port;
2933 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2934 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2937 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2941 bfilter->enables = en;
2945 static struct bnxt_filter_info*
2946 bnxt_match_ntuple_filter(struct bnxt *bp,
2947 struct bnxt_filter_info *bfilter,
2948 struct bnxt_vnic_info **mvnic)
2950 struct bnxt_filter_info *mfilter = NULL;
2953 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2954 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2955 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2956 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2957 bfilter->src_ipaddr_mask[0] ==
2958 mfilter->src_ipaddr_mask[0] &&
2959 bfilter->src_port == mfilter->src_port &&
2960 bfilter->src_port_mask == mfilter->src_port_mask &&
2961 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2962 bfilter->dst_ipaddr_mask[0] ==
2963 mfilter->dst_ipaddr_mask[0] &&
2964 bfilter->dst_port == mfilter->dst_port &&
2965 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2966 bfilter->flags == mfilter->flags &&
2967 bfilter->enables == mfilter->enables) {
2978 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2979 struct rte_eth_ntuple_filter *nfilter,
2980 enum rte_filter_op filter_op)
2982 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2983 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2986 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2987 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2991 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2992 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2996 bfilter = bnxt_get_unused_filter(bp);
2997 if (bfilter == NULL) {
2999 "Not enough resources for a new filter.\n");
3002 ret = parse_ntuple_filter(bp, nfilter, bfilter);
3006 vnic = &bp->vnic_info[nfilter->queue];
3007 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3008 filter1 = STAILQ_FIRST(&vnic0->filter);
3009 if (filter1 == NULL) {
3014 bfilter->dst_id = vnic->fw_vnic_id;
3015 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3017 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3018 bfilter->ethertype = 0x800;
3019 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3021 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3023 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3024 bfilter->dst_id == mfilter->dst_id) {
3025 PMD_DRV_LOG(ERR, "filter exists.\n");
3028 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3029 bfilter->dst_id != mfilter->dst_id) {
3030 mfilter->dst_id = vnic->fw_vnic_id;
3031 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3032 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3033 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3034 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3035 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3038 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3039 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3044 if (filter_op == RTE_ETH_FILTER_ADD) {
3045 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3046 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3049 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3051 if (mfilter == NULL) {
3052 /* This should not happen. But for Coverity! */
3056 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3058 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3059 bnxt_free_filter(bp, mfilter);
3060 bnxt_free_filter(bp, bfilter);
3065 bnxt_free_filter(bp, bfilter);
3070 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3071 enum rte_filter_op filter_op,
3074 struct bnxt *bp = dev->data->dev_private;
3077 if (filter_op == RTE_ETH_FILTER_NOP)
3081 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3086 switch (filter_op) {
3087 case RTE_ETH_FILTER_ADD:
3088 ret = bnxt_cfg_ntuple_filter(bp,
3089 (struct rte_eth_ntuple_filter *)arg,
3092 case RTE_ETH_FILTER_DELETE:
3093 ret = bnxt_cfg_ntuple_filter(bp,
3094 (struct rte_eth_ntuple_filter *)arg,
3098 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3106 bnxt_parse_fdir_filter(struct bnxt *bp,
3107 struct rte_eth_fdir_filter *fdir,
3108 struct bnxt_filter_info *filter)
3110 enum rte_fdir_mode fdir_mode =
3111 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3112 struct bnxt_vnic_info *vnic0, *vnic;
3113 struct bnxt_filter_info *filter1;
3117 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3120 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3121 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3123 switch (fdir->input.flow_type) {
3124 case RTE_ETH_FLOW_IPV4:
3125 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3127 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3128 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3129 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3130 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3131 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3132 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3133 filter->ip_addr_type =
3134 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3135 filter->src_ipaddr_mask[0] = 0xffffffff;
3136 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3137 filter->dst_ipaddr_mask[0] = 0xffffffff;
3138 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3139 filter->ethertype = 0x800;
3140 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3142 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3143 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3144 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3145 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3146 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3147 filter->dst_port_mask = 0xffff;
3148 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3149 filter->src_port_mask = 0xffff;
3150 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3151 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3152 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3153 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3154 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3155 filter->ip_protocol = 6;
3156 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3157 filter->ip_addr_type =
3158 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3159 filter->src_ipaddr_mask[0] = 0xffffffff;
3160 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3161 filter->dst_ipaddr_mask[0] = 0xffffffff;
3162 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3163 filter->ethertype = 0x800;
3164 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3166 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3167 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3168 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3169 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3170 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3171 filter->dst_port_mask = 0xffff;
3172 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3173 filter->src_port_mask = 0xffff;
3174 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3175 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3176 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3177 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3178 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3179 filter->ip_protocol = 17;
3180 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3181 filter->ip_addr_type =
3182 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3183 filter->src_ipaddr_mask[0] = 0xffffffff;
3184 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3185 filter->dst_ipaddr_mask[0] = 0xffffffff;
3186 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3187 filter->ethertype = 0x800;
3188 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3190 case RTE_ETH_FLOW_IPV6:
3191 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3193 filter->ip_addr_type =
3194 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3195 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3196 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3197 rte_memcpy(filter->src_ipaddr,
3198 fdir->input.flow.ipv6_flow.src_ip, 16);
3199 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3200 rte_memcpy(filter->dst_ipaddr,
3201 fdir->input.flow.ipv6_flow.dst_ip, 16);
3202 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3203 memset(filter->dst_ipaddr_mask, 0xff, 16);
3204 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3205 memset(filter->src_ipaddr_mask, 0xff, 16);
3206 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3207 filter->ethertype = 0x86dd;
3208 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3210 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3211 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3212 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3213 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3214 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3215 filter->dst_port_mask = 0xffff;
3216 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3217 filter->src_port_mask = 0xffff;
3218 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3219 filter->ip_addr_type =
3220 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3221 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3222 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3223 rte_memcpy(filter->src_ipaddr,
3224 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3225 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3226 rte_memcpy(filter->dst_ipaddr,
3227 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3228 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3229 memset(filter->dst_ipaddr_mask, 0xff, 16);
3230 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3231 memset(filter->src_ipaddr_mask, 0xff, 16);
3232 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3233 filter->ethertype = 0x86dd;
3234 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3236 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3237 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3238 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3239 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3240 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3241 filter->dst_port_mask = 0xffff;
3242 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3243 filter->src_port_mask = 0xffff;
3244 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3245 filter->ip_addr_type =
3246 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3247 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3248 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3249 rte_memcpy(filter->src_ipaddr,
3250 fdir->input.flow.udp6_flow.ip.src_ip, 16);
3251 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3252 rte_memcpy(filter->dst_ipaddr,
3253 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3254 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3255 memset(filter->dst_ipaddr_mask, 0xff, 16);
3256 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3257 memset(filter->src_ipaddr_mask, 0xff, 16);
3258 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3259 filter->ethertype = 0x86dd;
3260 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3262 case RTE_ETH_FLOW_L2_PAYLOAD:
3263 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3264 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3266 case RTE_ETH_FLOW_VXLAN:
3267 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3269 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3270 filter->tunnel_type =
3271 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3272 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3274 case RTE_ETH_FLOW_NVGRE:
3275 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3277 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3278 filter->tunnel_type =
3279 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3280 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3282 case RTE_ETH_FLOW_UNKNOWN:
3283 case RTE_ETH_FLOW_RAW:
3284 case RTE_ETH_FLOW_FRAG_IPV4:
3285 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3286 case RTE_ETH_FLOW_FRAG_IPV6:
3287 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3288 case RTE_ETH_FLOW_IPV6_EX:
3289 case RTE_ETH_FLOW_IPV6_TCP_EX:
3290 case RTE_ETH_FLOW_IPV6_UDP_EX:
3291 case RTE_ETH_FLOW_GENEVE:
3297 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3298 vnic = &bp->vnic_info[fdir->action.rx_queue];
3300 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3304 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3305 rte_memcpy(filter->dst_macaddr,
3306 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3307 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3310 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3311 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3312 filter1 = STAILQ_FIRST(&vnic0->filter);
3313 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3315 filter->dst_id = vnic->fw_vnic_id;
3316 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3317 if (filter->dst_macaddr[i] == 0x00)
3318 filter1 = STAILQ_FIRST(&vnic0->filter);
3320 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3323 if (filter1 == NULL)
3326 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3327 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3329 filter->enables = en;
3334 static struct bnxt_filter_info *
3335 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3336 struct bnxt_vnic_info **mvnic)
3338 struct bnxt_filter_info *mf = NULL;
3341 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3342 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3344 STAILQ_FOREACH(mf, &vnic->filter, next) {
3345 if (mf->filter_type == nf->filter_type &&
3346 mf->flags == nf->flags &&
3347 mf->src_port == nf->src_port &&
3348 mf->src_port_mask == nf->src_port_mask &&
3349 mf->dst_port == nf->dst_port &&
3350 mf->dst_port_mask == nf->dst_port_mask &&
3351 mf->ip_protocol == nf->ip_protocol &&
3352 mf->ip_addr_type == nf->ip_addr_type &&
3353 mf->ethertype == nf->ethertype &&
3354 mf->vni == nf->vni &&
3355 mf->tunnel_type == nf->tunnel_type &&
3356 mf->l2_ovlan == nf->l2_ovlan &&
3357 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3358 mf->l2_ivlan == nf->l2_ivlan &&
3359 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3360 !memcmp(mf->l2_addr, nf->l2_addr,
3361 RTE_ETHER_ADDR_LEN) &&
3362 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3363 RTE_ETHER_ADDR_LEN) &&
3364 !memcmp(mf->src_macaddr, nf->src_macaddr,
3365 RTE_ETHER_ADDR_LEN) &&
3366 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3367 RTE_ETHER_ADDR_LEN) &&
3368 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3369 sizeof(nf->src_ipaddr)) &&
3370 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3371 sizeof(nf->src_ipaddr_mask)) &&
3372 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3373 sizeof(nf->dst_ipaddr)) &&
3374 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3375 sizeof(nf->dst_ipaddr_mask))) {
3386 bnxt_fdir_filter(struct rte_eth_dev *dev,
3387 enum rte_filter_op filter_op,
3390 struct bnxt *bp = dev->data->dev_private;
3391 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
3392 struct bnxt_filter_info *filter, *match;
3393 struct bnxt_vnic_info *vnic, *mvnic;
3396 if (filter_op == RTE_ETH_FILTER_NOP)
3399 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3402 switch (filter_op) {
3403 case RTE_ETH_FILTER_ADD:
3404 case RTE_ETH_FILTER_DELETE:
3406 filter = bnxt_get_unused_filter(bp);
3407 if (filter == NULL) {
3409 "Not enough resources for a new flow.\n");
3413 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3416 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3418 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3419 vnic = &bp->vnic_info[0];
3421 vnic = &bp->vnic_info[fdir->action.rx_queue];
3423 match = bnxt_match_fdir(bp, filter, &mvnic);
3424 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3425 if (match->dst_id == vnic->fw_vnic_id) {
3426 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3430 match->dst_id = vnic->fw_vnic_id;
3431 ret = bnxt_hwrm_set_ntuple_filter(bp,
3434 STAILQ_REMOVE(&mvnic->filter, match,
3435 bnxt_filter_info, next);
3436 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3438 "Filter with matching pattern exist\n");
3440 "Updated it to new destination q\n");
3444 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3445 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3450 if (filter_op == RTE_ETH_FILTER_ADD) {
3451 ret = bnxt_hwrm_set_ntuple_filter(bp,
3456 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3458 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3459 STAILQ_REMOVE(&vnic->filter, match,
3460 bnxt_filter_info, next);
3461 bnxt_free_filter(bp, match);
3462 bnxt_free_filter(bp, filter);
3465 case RTE_ETH_FILTER_FLUSH:
3466 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3467 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3469 STAILQ_FOREACH(filter, &vnic->filter, next) {
3470 if (filter->filter_type ==
3471 HWRM_CFA_NTUPLE_FILTER) {
3473 bnxt_hwrm_clear_ntuple_filter(bp,
3475 STAILQ_REMOVE(&vnic->filter, filter,
3476 bnxt_filter_info, next);
3481 case RTE_ETH_FILTER_UPDATE:
3482 case RTE_ETH_FILTER_STATS:
3483 case RTE_ETH_FILTER_INFO:
3484 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3487 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3494 bnxt_free_filter(bp, filter);
3499 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3500 enum rte_filter_type filter_type,
3501 enum rte_filter_op filter_op, void *arg)
3503 struct bnxt *bp = dev->data->dev_private;
3506 ret = is_bnxt_in_error(dev->data->dev_private);
3510 switch (filter_type) {
3511 case RTE_ETH_FILTER_TUNNEL:
3513 "filter type: %d: To be implemented\n", filter_type);
3515 case RTE_ETH_FILTER_FDIR:
3516 ret = bnxt_fdir_filter(dev, filter_op, arg);
3518 case RTE_ETH_FILTER_NTUPLE:
3519 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3521 case RTE_ETH_FILTER_ETHERTYPE:
3522 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3524 case RTE_ETH_FILTER_GENERIC:
3525 if (filter_op != RTE_ETH_FILTER_GET)
3528 *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3530 *(const void **)arg = &bnxt_flow_ops;
3534 "Filter type (%d) not supported", filter_type);
3541 static const uint32_t *
3542 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3544 static const uint32_t ptypes[] = {
3545 RTE_PTYPE_L2_ETHER_VLAN,
3546 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3547 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3551 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3552 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3553 RTE_PTYPE_INNER_L4_ICMP,
3554 RTE_PTYPE_INNER_L4_TCP,
3555 RTE_PTYPE_INNER_L4_UDP,
3559 if (!dev->rx_pkt_burst)
3565 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3568 uint32_t reg_base = *reg_arr & 0xfffff000;
3572 for (i = 0; i < count; i++) {
3573 if ((reg_arr[i] & 0xfffff000) != reg_base)
3576 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3577 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3581 static int bnxt_map_ptp_regs(struct bnxt *bp)
3583 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3587 reg_arr = ptp->rx_regs;
3588 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3592 reg_arr = ptp->tx_regs;
3593 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3597 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3598 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3600 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3601 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3606 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3608 rte_write32(0, (uint8_t *)bp->bar0 +
3609 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3610 rte_write32(0, (uint8_t *)bp->bar0 +
3611 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3614 static uint64_t bnxt_cc_read(struct bnxt *bp)
3618 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3619 BNXT_GRCPF_REG_SYNC_TIME));
3620 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3621 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3625 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3627 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3630 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3631 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3632 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3635 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3636 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3637 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3638 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3639 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3640 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3645 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3647 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3648 struct bnxt_pf_info *pf = &bp->pf;
3655 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3656 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3657 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3660 port_id = pf->port_id;
3661 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3662 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3664 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3665 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3666 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3667 /* bnxt_clr_rx_ts(bp); TBD */
3671 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3672 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3673 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3674 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3680 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3683 struct bnxt *bp = dev->data->dev_private;
3684 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3689 ns = rte_timespec_to_ns(ts);
3690 /* Set the timecounters to a new value. */
3697 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3699 struct bnxt *bp = dev->data->dev_private;
3700 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3701 uint64_t ns, systime_cycles = 0;
3707 if (BNXT_CHIP_THOR(bp))
3708 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3711 systime_cycles = bnxt_cc_read(bp);
3713 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3714 *ts = rte_ns_to_timespec(ns);
3719 bnxt_timesync_enable(struct rte_eth_dev *dev)
3721 struct bnxt *bp = dev->data->dev_private;
3722 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3730 ptp->tx_tstamp_en = 1;
3731 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3733 rc = bnxt_hwrm_ptp_cfg(bp);
3737 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3738 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3739 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3741 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3742 ptp->tc.cc_shift = shift;
3743 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3745 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3746 ptp->rx_tstamp_tc.cc_shift = shift;
3747 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3749 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3750 ptp->tx_tstamp_tc.cc_shift = shift;
3751 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3753 if (!BNXT_CHIP_THOR(bp))
3754 bnxt_map_ptp_regs(bp);
3760 bnxt_timesync_disable(struct rte_eth_dev *dev)
3762 struct bnxt *bp = dev->data->dev_private;
3763 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3769 ptp->tx_tstamp_en = 0;
3772 bnxt_hwrm_ptp_cfg(bp);
3774 if (!BNXT_CHIP_THOR(bp))
3775 bnxt_unmap_ptp_regs(bp);
3781 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3782 struct timespec *timestamp,
3783 uint32_t flags __rte_unused)
3785 struct bnxt *bp = dev->data->dev_private;
3786 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3787 uint64_t rx_tstamp_cycles = 0;
3793 if (BNXT_CHIP_THOR(bp))
3794 rx_tstamp_cycles = ptp->rx_timestamp;
3796 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3798 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3799 *timestamp = rte_ns_to_timespec(ns);
3804 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3805 struct timespec *timestamp)
3807 struct bnxt *bp = dev->data->dev_private;
3808 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3809 uint64_t tx_tstamp_cycles = 0;
3816 if (BNXT_CHIP_THOR(bp))
3817 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3820 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3822 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3823 *timestamp = rte_ns_to_timespec(ns);
3829 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3831 struct bnxt *bp = dev->data->dev_private;
3832 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3837 ptp->tc.nsec += delta;
3843 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3845 struct bnxt *bp = dev->data->dev_private;
3847 uint32_t dir_entries;
3848 uint32_t entry_length;
3850 rc = is_bnxt_in_error(bp);
3854 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3855 bp->pdev->addr.domain, bp->pdev->addr.bus,
3856 bp->pdev->addr.devid, bp->pdev->addr.function);
3858 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3862 return dir_entries * entry_length;
3866 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3867 struct rte_dev_eeprom_info *in_eeprom)
3869 struct bnxt *bp = dev->data->dev_private;
3874 rc = is_bnxt_in_error(bp);
3878 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3879 bp->pdev->addr.domain, bp->pdev->addr.bus,
3880 bp->pdev->addr.devid, bp->pdev->addr.function,
3881 in_eeprom->offset, in_eeprom->length);
3883 if (in_eeprom->offset == 0) /* special offset value to get directory */
3884 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3887 index = in_eeprom->offset >> 24;
3888 offset = in_eeprom->offset & 0xffffff;
3891 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3892 in_eeprom->length, in_eeprom->data);
3897 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3900 case BNX_DIR_TYPE_CHIMP_PATCH:
3901 case BNX_DIR_TYPE_BOOTCODE:
3902 case BNX_DIR_TYPE_BOOTCODE_2:
3903 case BNX_DIR_TYPE_APE_FW:
3904 case BNX_DIR_TYPE_APE_PATCH:
3905 case BNX_DIR_TYPE_KONG_FW:
3906 case BNX_DIR_TYPE_KONG_PATCH:
3907 case BNX_DIR_TYPE_BONO_FW:
3908 case BNX_DIR_TYPE_BONO_PATCH:
3916 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3919 case BNX_DIR_TYPE_AVS:
3920 case BNX_DIR_TYPE_EXP_ROM_MBA:
3921 case BNX_DIR_TYPE_PCIE:
3922 case BNX_DIR_TYPE_TSCF_UCODE:
3923 case BNX_DIR_TYPE_EXT_PHY:
3924 case BNX_DIR_TYPE_CCM:
3925 case BNX_DIR_TYPE_ISCSI_BOOT:
3926 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3927 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3935 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3937 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3938 bnxt_dir_type_is_other_exec_format(dir_type);
3942 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3943 struct rte_dev_eeprom_info *in_eeprom)
3945 struct bnxt *bp = dev->data->dev_private;
3946 uint8_t index, dir_op;
3947 uint16_t type, ext, ordinal, attr;
3950 rc = is_bnxt_in_error(bp);
3954 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3955 bp->pdev->addr.domain, bp->pdev->addr.bus,
3956 bp->pdev->addr.devid, bp->pdev->addr.function,
3957 in_eeprom->offset, in_eeprom->length);
3960 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3964 type = in_eeprom->magic >> 16;
3966 if (type == 0xffff) { /* special value for directory operations */
3967 index = in_eeprom->magic & 0xff;
3968 dir_op = in_eeprom->magic >> 8;
3972 case 0x0e: /* erase */
3973 if (in_eeprom->offset != ~in_eeprom->magic)
3975 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3981 /* Create or re-write an NVM item: */
3982 if (bnxt_dir_type_is_executable(type) == true)
3984 ext = in_eeprom->magic & 0xffff;
3985 ordinal = in_eeprom->offset >> 16;
3986 attr = in_eeprom->offset & 0xffff;
3988 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3989 in_eeprom->data, in_eeprom->length);
3996 static const struct eth_dev_ops bnxt_dev_ops = {
3997 .dev_infos_get = bnxt_dev_info_get_op,
3998 .dev_close = bnxt_dev_close_op,
3999 .dev_configure = bnxt_dev_configure_op,
4000 .dev_start = bnxt_dev_start_op,
4001 .dev_stop = bnxt_dev_stop_op,
4002 .dev_set_link_up = bnxt_dev_set_link_up_op,
4003 .dev_set_link_down = bnxt_dev_set_link_down_op,
4004 .stats_get = bnxt_stats_get_op,
4005 .stats_reset = bnxt_stats_reset_op,
4006 .rx_queue_setup = bnxt_rx_queue_setup_op,
4007 .rx_queue_release = bnxt_rx_queue_release_op,
4008 .tx_queue_setup = bnxt_tx_queue_setup_op,
4009 .tx_queue_release = bnxt_tx_queue_release_op,
4010 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4011 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4012 .reta_update = bnxt_reta_update_op,
4013 .reta_query = bnxt_reta_query_op,
4014 .rss_hash_update = bnxt_rss_hash_update_op,
4015 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4016 .link_update = bnxt_link_update_op,
4017 .promiscuous_enable = bnxt_promiscuous_enable_op,
4018 .promiscuous_disable = bnxt_promiscuous_disable_op,
4019 .allmulticast_enable = bnxt_allmulticast_enable_op,
4020 .allmulticast_disable = bnxt_allmulticast_disable_op,
4021 .mac_addr_add = bnxt_mac_addr_add_op,
4022 .mac_addr_remove = bnxt_mac_addr_remove_op,
4023 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4024 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4025 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
4026 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
4027 .vlan_filter_set = bnxt_vlan_filter_set_op,
4028 .vlan_offload_set = bnxt_vlan_offload_set_op,
4029 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4030 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4031 .mtu_set = bnxt_mtu_set_op,
4032 .mac_addr_set = bnxt_set_default_mac_addr_op,
4033 .xstats_get = bnxt_dev_xstats_get_op,
4034 .xstats_get_names = bnxt_dev_xstats_get_names_op,
4035 .xstats_reset = bnxt_dev_xstats_reset_op,
4036 .fw_version_get = bnxt_fw_version_get,
4037 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4038 .rxq_info_get = bnxt_rxq_info_get_op,
4039 .txq_info_get = bnxt_txq_info_get_op,
4040 .dev_led_on = bnxt_dev_led_on_op,
4041 .dev_led_off = bnxt_dev_led_off_op,
4042 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4043 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4044 .rx_queue_count = bnxt_rx_queue_count_op,
4045 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
4046 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
4047 .rx_queue_start = bnxt_rx_queue_start,
4048 .rx_queue_stop = bnxt_rx_queue_stop,
4049 .tx_queue_start = bnxt_tx_queue_start,
4050 .tx_queue_stop = bnxt_tx_queue_stop,
4051 .filter_ctrl = bnxt_filter_ctrl_op,
4052 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4053 .get_eeprom_length = bnxt_get_eeprom_length_op,
4054 .get_eeprom = bnxt_get_eeprom_op,
4055 .set_eeprom = bnxt_set_eeprom_op,
4056 .timesync_enable = bnxt_timesync_enable,
4057 .timesync_disable = bnxt_timesync_disable,
4058 .timesync_read_time = bnxt_timesync_read_time,
4059 .timesync_write_time = bnxt_timesync_write_time,
4060 .timesync_adjust_time = bnxt_timesync_adjust_time,
4061 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4062 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4065 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4069 /* Only pre-map the reset GRC registers using window 3 */
4070 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4071 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4073 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4078 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4080 struct bnxt_error_recovery_info *info = bp->recovery_info;
4081 uint32_t reg_base = 0xffffffff;
4084 /* Only pre-map the monitoring GRC registers using window 2 */
4085 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4086 uint32_t reg = info->status_regs[i];
4088 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4091 if (reg_base == 0xffffffff)
4092 reg_base = reg & 0xfffff000;
4093 if ((reg & 0xfffff000) != reg_base)
4096 /* Use mask 0xffc as the Lower 2 bits indicates
4097 * address space location
4099 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4103 if (reg_base == 0xffffffff)
4106 rte_write32(reg_base, (uint8_t *)bp->bar0 +
4107 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4112 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4114 struct bnxt_error_recovery_info *info = bp->recovery_info;
4115 uint32_t delay = info->delay_after_reset[index];
4116 uint32_t val = info->reset_reg_val[index];
4117 uint32_t reg = info->reset_reg[index];
4118 uint32_t type, offset;
4120 type = BNXT_FW_STATUS_REG_TYPE(reg);
4121 offset = BNXT_FW_STATUS_REG_OFF(reg);
4124 case BNXT_FW_STATUS_REG_TYPE_CFG:
4125 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4127 case BNXT_FW_STATUS_REG_TYPE_GRC:
4128 offset = bnxt_map_reset_regs(bp, offset);
4129 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4131 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4132 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4135 /* wait on a specific interval of time until core reset is complete */
4137 rte_delay_ms(delay);
4140 static void bnxt_dev_cleanup(struct bnxt *bp)
4142 bnxt_set_hwrm_link_config(bp, false);
4143 bp->link_info.link_up = 0;
4144 if (bp->eth_dev->data->dev_started)
4145 bnxt_dev_stop_op(bp->eth_dev);
4147 bnxt_uninit_resources(bp, true);
4150 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4152 struct rte_eth_dev *dev = bp->eth_dev;
4153 struct rte_vlan_filter_conf *vfc;
4157 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4158 vfc = &dev->data->vlan_filter_conf;
4159 vidx = vlan_id / 64;
4160 vbit = vlan_id % 64;
4162 /* Each bit corresponds to a VLAN id */
4163 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4164 rc = bnxt_add_vlan_filter(bp, vlan_id);
4173 static int bnxt_restore_mac_filters(struct bnxt *bp)
4175 struct rte_eth_dev *dev = bp->eth_dev;
4176 struct rte_eth_dev_info dev_info;
4177 struct rte_ether_addr *addr;
4183 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
4186 rc = bnxt_dev_info_get_op(dev, &dev_info);
4190 /* replay MAC address configuration */
4191 for (i = 1; i < dev_info.max_mac_addrs; i++) {
4192 addr = &dev->data->mac_addrs[i];
4194 /* skip zero address */
4195 if (rte_is_zero_ether_addr(addr))
4199 pool_mask = dev->data->mac_pool_sel[i];
4202 if (pool_mask & 1ULL) {
4203 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4209 } while (pool_mask);
4215 static int bnxt_restore_filters(struct bnxt *bp)
4217 struct rte_eth_dev *dev = bp->eth_dev;
4220 if (dev->data->all_multicast) {
4221 ret = bnxt_allmulticast_enable_op(dev);
4225 if (dev->data->promiscuous) {
4226 ret = bnxt_promiscuous_enable_op(dev);
4231 ret = bnxt_restore_mac_filters(bp);
4235 ret = bnxt_restore_vlan_filters(bp);
4236 /* TODO restore other filters as well */
4240 static void bnxt_dev_recover(void *arg)
4242 struct bnxt *bp = arg;
4243 int timeout = bp->fw_reset_max_msecs;
4246 /* Clear Error flag so that device re-init should happen */
4247 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4250 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4253 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4254 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4255 } while (rc && timeout);
4258 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4262 rc = bnxt_init_resources(bp, true);
4265 "Failed to initialize resources after reset\n");
4268 /* clear reset flag as the device is initialized now */
4269 bp->flags &= ~BNXT_FLAG_FW_RESET;
4271 rc = bnxt_dev_start_op(bp->eth_dev);
4273 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4277 rc = bnxt_restore_filters(bp);
4281 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4284 bnxt_dev_stop_op(bp->eth_dev);
4286 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4287 bnxt_uninit_resources(bp, false);
4288 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4291 void bnxt_dev_reset_and_resume(void *arg)
4293 struct bnxt *bp = arg;
4296 bnxt_dev_cleanup(bp);
4298 bnxt_wait_for_device_shutdown(bp);
4300 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4301 bnxt_dev_recover, (void *)bp);
4303 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4306 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4308 struct bnxt_error_recovery_info *info = bp->recovery_info;
4309 uint32_t reg = info->status_regs[index];
4310 uint32_t type, offset, val = 0;
4312 type = BNXT_FW_STATUS_REG_TYPE(reg);
4313 offset = BNXT_FW_STATUS_REG_OFF(reg);
4316 case BNXT_FW_STATUS_REG_TYPE_CFG:
4317 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4319 case BNXT_FW_STATUS_REG_TYPE_GRC:
4320 offset = info->mapped_status_regs[index];
4322 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4323 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4331 static int bnxt_fw_reset_all(struct bnxt *bp)
4333 struct bnxt_error_recovery_info *info = bp->recovery_info;
4337 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4338 /* Reset through master function driver */
4339 for (i = 0; i < info->reg_array_cnt; i++)
4340 bnxt_write_fw_reset_reg(bp, i);
4341 /* Wait for time specified by FW after triggering reset */
4342 rte_delay_ms(info->master_func_wait_period_after_reset);
4343 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4344 /* Reset with the help of Kong processor */
4345 rc = bnxt_hwrm_fw_reset(bp);
4347 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4353 static void bnxt_fw_reset_cb(void *arg)
4355 struct bnxt *bp = arg;
4356 struct bnxt_error_recovery_info *info = bp->recovery_info;
4359 /* Only Master function can do FW reset */
4360 if (bnxt_is_master_func(bp) &&
4361 bnxt_is_recovery_enabled(bp)) {
4362 rc = bnxt_fw_reset_all(bp);
4364 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4369 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4370 * EXCEPTION_FATAL_ASYNC event to all the functions
4371 * (including MASTER FUNC). After receiving this Async, all the active
4372 * drivers should treat this case as FW initiated recovery
4374 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4375 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4376 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4378 /* To recover from error */
4379 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4384 /* Driver should poll FW heartbeat, reset_counter with the frequency
4385 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4386 * When the driver detects heartbeat stop or change in reset_counter,
4387 * it has to trigger a reset to recover from the error condition.
4388 * A “master PF” is the function who will have the privilege to
4389 * initiate the chimp reset. The master PF will be elected by the
4390 * firmware and will be notified through async message.
4392 static void bnxt_check_fw_health(void *arg)
4394 struct bnxt *bp = arg;
4395 struct bnxt_error_recovery_info *info = bp->recovery_info;
4396 uint32_t val = 0, wait_msec;
4398 if (!info || !bnxt_is_recovery_enabled(bp) ||
4399 is_bnxt_in_error(bp))
4402 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4403 if (val == info->last_heart_beat)
4406 info->last_heart_beat = val;
4408 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4409 if (val != info->last_reset_counter)
4412 info->last_reset_counter = val;
4414 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4415 bnxt_check_fw_health, (void *)bp);
4419 /* Stop DMA to/from device */
4420 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4421 bp->flags |= BNXT_FLAG_FW_RESET;
4423 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4425 if (bnxt_is_master_func(bp))
4426 wait_msec = info->master_func_wait_period;
4428 wait_msec = info->normal_func_wait_period;
4430 rte_eal_alarm_set(US_PER_MS * wait_msec,
4431 bnxt_fw_reset_cb, (void *)bp);
4434 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4436 uint32_t polling_freq;
4438 if (!bnxt_is_recovery_enabled(bp))
4441 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4444 polling_freq = bp->recovery_info->driver_polling_freq;
4446 rte_eal_alarm_set(US_PER_MS * polling_freq,
4447 bnxt_check_fw_health, (void *)bp);
4448 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4451 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4453 if (!bnxt_is_recovery_enabled(bp))
4456 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4457 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4460 static bool bnxt_vf_pciid(uint16_t device_id)
4462 switch (device_id) {
4463 case BROADCOM_DEV_ID_57304_VF:
4464 case BROADCOM_DEV_ID_57406_VF:
4465 case BROADCOM_DEV_ID_5731X_VF:
4466 case BROADCOM_DEV_ID_5741X_VF:
4467 case BROADCOM_DEV_ID_57414_VF:
4468 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4469 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4470 case BROADCOM_DEV_ID_58802_VF:
4471 case BROADCOM_DEV_ID_57500_VF1:
4472 case BROADCOM_DEV_ID_57500_VF2:
4480 static bool bnxt_thor_device(uint16_t device_id)
4482 switch (device_id) {
4483 case BROADCOM_DEV_ID_57508:
4484 case BROADCOM_DEV_ID_57504:
4485 case BROADCOM_DEV_ID_57502:
4486 case BROADCOM_DEV_ID_57508_MF1:
4487 case BROADCOM_DEV_ID_57504_MF1:
4488 case BROADCOM_DEV_ID_57502_MF1:
4489 case BROADCOM_DEV_ID_57508_MF2:
4490 case BROADCOM_DEV_ID_57504_MF2:
4491 case BROADCOM_DEV_ID_57502_MF2:
4492 case BROADCOM_DEV_ID_57500_VF1:
4493 case BROADCOM_DEV_ID_57500_VF2:
4501 bool bnxt_stratus_device(struct bnxt *bp)
4503 uint16_t device_id = bp->pdev->id.device_id;
4505 switch (device_id) {
4506 case BROADCOM_DEV_ID_STRATUS_NIC:
4507 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4508 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4516 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4518 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4519 struct bnxt *bp = eth_dev->data->dev_private;
4521 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4522 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4523 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4524 if (!bp->bar0 || !bp->doorbell_base) {
4525 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4529 bp->eth_dev = eth_dev;
4535 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4536 struct bnxt_ctx_pg_info *ctx_pg,
4541 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4542 const struct rte_memzone *mz = NULL;
4543 char mz_name[RTE_MEMZONE_NAMESIZE];
4544 rte_iova_t mz_phys_addr;
4545 uint64_t valid_bits = 0;
4552 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4554 rmem->page_size = BNXT_PAGE_SIZE;
4555 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4556 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4557 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4559 valid_bits = PTU_PTE_VALID;
4561 if (rmem->nr_pages > 1) {
4562 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4563 "bnxt_ctx_pg_tbl%s_%x_%d",
4564 suffix, idx, bp->eth_dev->data->port_id);
4565 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4566 mz = rte_memzone_lookup(mz_name);
4568 mz = rte_memzone_reserve_aligned(mz_name,
4572 RTE_MEMZONE_SIZE_HINT_ONLY |
4573 RTE_MEMZONE_IOVA_CONTIG,
4579 memset(mz->addr, 0, mz->len);
4580 mz_phys_addr = mz->iova;
4582 rmem->pg_tbl = mz->addr;
4583 rmem->pg_tbl_map = mz_phys_addr;
4584 rmem->pg_tbl_mz = mz;
4587 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4588 suffix, idx, bp->eth_dev->data->port_id);
4589 mz = rte_memzone_lookup(mz_name);
4591 mz = rte_memzone_reserve_aligned(mz_name,
4595 RTE_MEMZONE_SIZE_HINT_ONLY |
4596 RTE_MEMZONE_IOVA_CONTIG,
4602 memset(mz->addr, 0, mz->len);
4603 mz_phys_addr = mz->iova;
4605 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4606 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4607 rmem->dma_arr[i] = mz_phys_addr + sz;
4609 if (rmem->nr_pages > 1) {
4610 if (i == rmem->nr_pages - 2 &&
4611 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4612 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4613 else if (i == rmem->nr_pages - 1 &&
4614 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4615 valid_bits |= PTU_PTE_LAST;
4617 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4623 if (rmem->vmem_size)
4624 rmem->vmem = (void **)mz->addr;
4625 rmem->dma_arr[0] = mz_phys_addr;
4629 static void bnxt_free_ctx_mem(struct bnxt *bp)
4633 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4636 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4637 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4638 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4639 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4640 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4641 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4642 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4643 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4644 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4645 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4646 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4648 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4649 if (bp->ctx->tqm_mem[i])
4650 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4657 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4659 #define min_t(type, x, y) ({ \
4660 type __min1 = (x); \
4661 type __min2 = (y); \
4662 __min1 < __min2 ? __min1 : __min2; })
4664 #define max_t(type, x, y) ({ \
4665 type __max1 = (x); \
4666 type __max2 = (y); \
4667 __max1 > __max2 ? __max1 : __max2; })
4669 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4671 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4673 struct bnxt_ctx_pg_info *ctx_pg;
4674 struct bnxt_ctx_mem_info *ctx;
4675 uint32_t mem_size, ena, entries;
4676 uint32_t entries_sp, min;
4679 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4681 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4685 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4688 ctx_pg = &ctx->qp_mem;
4689 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4690 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4691 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4695 ctx_pg = &ctx->srq_mem;
4696 ctx_pg->entries = ctx->srq_max_l2_entries;
4697 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4698 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4702 ctx_pg = &ctx->cq_mem;
4703 ctx_pg->entries = ctx->cq_max_l2_entries;
4704 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4705 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4709 ctx_pg = &ctx->vnic_mem;
4710 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4711 ctx->vnic_max_ring_table_entries;
4712 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4713 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4717 ctx_pg = &ctx->stat_mem;
4718 ctx_pg->entries = ctx->stat_max_entries;
4719 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4720 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4724 min = ctx->tqm_min_entries_per_ring;
4726 entries_sp = ctx->qp_max_l2_entries +
4727 ctx->vnic_max_vnic_entries +
4728 2 * ctx->qp_min_qp1_entries + min;
4729 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4731 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4732 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4733 entries = clamp_t(uint32_t, entries, min,
4734 ctx->tqm_max_entries_per_ring);
4735 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4736 ctx_pg = ctx->tqm_mem[i];
4737 ctx_pg->entries = i ? entries : entries_sp;
4738 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4739 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4742 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4745 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4746 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4749 "Failed to configure context mem: rc = %d\n", rc);
4751 ctx->flags |= BNXT_CTX_FLAG_INITED;
4756 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4758 struct rte_pci_device *pci_dev = bp->pdev;
4759 char mz_name[RTE_MEMZONE_NAMESIZE];
4760 const struct rte_memzone *mz = NULL;
4761 uint32_t total_alloc_len;
4762 rte_iova_t mz_phys_addr;
4764 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4767 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4768 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4769 pci_dev->addr.bus, pci_dev->addr.devid,
4770 pci_dev->addr.function, "rx_port_stats");
4771 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4772 mz = rte_memzone_lookup(mz_name);
4774 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4775 sizeof(struct rx_port_stats_ext) + 512);
4777 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4780 RTE_MEMZONE_SIZE_HINT_ONLY |
4781 RTE_MEMZONE_IOVA_CONTIG);
4785 memset(mz->addr, 0, mz->len);
4786 mz_phys_addr = mz->iova;
4788 bp->rx_mem_zone = (const void *)mz;
4789 bp->hw_rx_port_stats = mz->addr;
4790 bp->hw_rx_port_stats_map = mz_phys_addr;
4792 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4793 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4794 pci_dev->addr.bus, pci_dev->addr.devid,
4795 pci_dev->addr.function, "tx_port_stats");
4796 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4797 mz = rte_memzone_lookup(mz_name);
4799 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4800 sizeof(struct tx_port_stats_ext) + 512);
4802 mz = rte_memzone_reserve(mz_name,
4806 RTE_MEMZONE_SIZE_HINT_ONLY |
4807 RTE_MEMZONE_IOVA_CONTIG);
4811 memset(mz->addr, 0, mz->len);
4812 mz_phys_addr = mz->iova;
4814 bp->tx_mem_zone = (const void *)mz;
4815 bp->hw_tx_port_stats = mz->addr;
4816 bp->hw_tx_port_stats_map = mz_phys_addr;
4817 bp->flags |= BNXT_FLAG_PORT_STATS;
4819 /* Display extended statistics if FW supports it */
4820 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4821 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4822 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4825 bp->hw_rx_port_stats_ext = (void *)
4826 ((uint8_t *)bp->hw_rx_port_stats +
4827 sizeof(struct rx_port_stats));
4828 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4829 sizeof(struct rx_port_stats);
4830 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4832 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4833 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4834 bp->hw_tx_port_stats_ext = (void *)
4835 ((uint8_t *)bp->hw_tx_port_stats +
4836 sizeof(struct tx_port_stats));
4837 bp->hw_tx_port_stats_ext_map =
4838 bp->hw_tx_port_stats_map +
4839 sizeof(struct tx_port_stats);
4840 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4846 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4848 struct bnxt *bp = eth_dev->data->dev_private;
4851 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4852 RTE_ETHER_ADDR_LEN *
4855 if (eth_dev->data->mac_addrs == NULL) {
4856 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4860 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4864 /* Generate a random MAC address, if none was assigned by PF */
4865 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4866 bnxt_eth_hw_addr_random(bp->mac_addr);
4868 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4869 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4870 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4872 rc = bnxt_hwrm_set_mac(bp);
4874 memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4875 RTE_ETHER_ADDR_LEN);
4879 /* Copy the permanent MAC from the FUNC_QCAPS response */
4880 memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4881 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4886 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4890 /* MAC is already configured in FW */
4891 if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4894 /* Restore the old MAC configured */
4895 rc = bnxt_hwrm_set_mac(bp);
4897 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4902 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4907 #define ALLOW_FUNC(x) \
4909 uint32_t arg = (x); \
4910 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4911 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4914 /* Forward all requests if firmware is new enough */
4915 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4916 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4917 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4918 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4920 PMD_DRV_LOG(WARNING,
4921 "Firmware too old for VF mailbox functionality\n");
4922 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4926 * The following are used for driver cleanup. If we disallow these,
4927 * VF drivers can't clean up cleanly.
4929 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4930 ALLOW_FUNC(HWRM_VNIC_FREE);
4931 ALLOW_FUNC(HWRM_RING_FREE);
4932 ALLOW_FUNC(HWRM_RING_GRP_FREE);
4933 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4934 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4935 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4936 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4937 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4941 bnxt_get_svif(uint16_t port_id, bool func_svif)
4943 struct rte_eth_dev *eth_dev;
4946 eth_dev = &rte_eth_devices[port_id];
4947 bp = eth_dev->data->dev_private;
4949 return func_svif ? bp->func_svif : bp->port_svif;
4953 bnxt_get_vnic_id(uint16_t port)
4955 struct rte_eth_dev *eth_dev;
4956 struct bnxt_vnic_info *vnic;
4959 eth_dev = &rte_eth_devices[port];
4960 bp = eth_dev->data->dev_private;
4962 vnic = BNXT_GET_DEFAULT_VNIC(bp);
4964 return vnic->fw_vnic_id;
4968 bnxt_get_fw_func_id(uint16_t port)
4970 struct rte_eth_dev *eth_dev;
4973 eth_dev = &rte_eth_devices[port];
4974 bp = eth_dev->data->dev_private;
4979 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
4981 struct bnxt_error_recovery_info *info = bp->recovery_info;
4984 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
4985 memset(info, 0, sizeof(*info));
4989 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4992 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4995 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4997 bp->recovery_info = info;
5000 static void bnxt_check_fw_status(struct bnxt *bp)
5004 if (!(bp->recovery_info &&
5005 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5008 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5009 if (fw_status != BNXT_FW_STATUS_HEALTHY)
5010 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5014 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5016 struct bnxt_error_recovery_info *info = bp->recovery_info;
5017 uint32_t status_loc;
5020 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5021 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5022 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5023 BNXT_GRCP_WINDOW_2_BASE +
5024 offsetof(struct hcomm_status,
5026 /* If the signature is absent, then FW does not support this feature */
5027 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5028 HCOMM_STATUS_SIGNATURE_VAL)
5032 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5036 bp->recovery_info = info;
5038 memset(info, 0, sizeof(*info));
5041 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5042 BNXT_GRCP_WINDOW_2_BASE +
5043 offsetof(struct hcomm_status,
5046 /* Only pre-map the FW health status GRC register */
5047 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5050 info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5051 info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5052 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5054 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5055 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5057 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5062 static int bnxt_init_fw(struct bnxt *bp)
5069 rc = bnxt_map_hcomm_fw_status_reg(bp);
5073 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5075 bnxt_check_fw_status(bp);
5079 rc = bnxt_hwrm_func_reset(bp);
5083 rc = bnxt_hwrm_vnic_qcaps(bp);
5087 rc = bnxt_hwrm_queue_qportcfg(bp);
5091 /* Get the MAX capabilities for this function.
5092 * This function also allocates context memory for TQM rings and
5093 * informs the firmware about this allocated backing store memory.
5095 rc = bnxt_hwrm_func_qcaps(bp);
5099 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5103 bnxt_hwrm_port_mac_qcfg(bp);
5105 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5109 bnxt_alloc_error_recovery_info(bp);
5110 /* Get the adapter error recovery support info */
5111 rc = bnxt_hwrm_error_recovery_qcfg(bp);
5113 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5115 bnxt_hwrm_port_led_qcaps(bp);
5121 bnxt_init_locks(struct bnxt *bp)
5125 err = pthread_mutex_init(&bp->flow_lock, NULL);
5127 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5131 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5133 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5137 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5141 rc = bnxt_init_fw(bp);
5145 if (!reconfig_dev) {
5146 rc = bnxt_setup_mac_addr(bp->eth_dev);
5150 rc = bnxt_restore_dflt_mac(bp);
5155 bnxt_config_vf_req_fwd(bp);
5157 rc = bnxt_hwrm_func_driver_register(bp);
5159 PMD_DRV_LOG(ERR, "Failed to register driver");
5164 if (bp->pdev->max_vfs) {
5165 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5167 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5171 rc = bnxt_hwrm_allocate_pf_only(bp);
5174 "Failed to allocate PF resources");
5180 rc = bnxt_alloc_mem(bp, reconfig_dev);
5184 rc = bnxt_setup_int(bp);
5188 rc = bnxt_request_int(bp);
5192 rc = bnxt_init_ctx_mem(bp);
5194 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5198 rc = bnxt_init_locks(bp);
5206 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5207 const char *value, void *opaque_arg)
5209 struct bnxt *bp = opaque_arg;
5210 unsigned long truflow;
5213 if (!value || !opaque_arg) {
5215 "Invalid parameter passed to truflow devargs.\n");
5219 truflow = strtoul(value, &end, 10);
5220 if (end == NULL || *end != '\0' ||
5221 (truflow == ULONG_MAX && errno == ERANGE)) {
5223 "Invalid parameter passed to truflow devargs.\n");
5227 if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5229 "Invalid value passed to truflow devargs.\n");
5233 bp->truflow = truflow;
5235 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5241 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5242 const char *value, void *opaque_arg)
5244 struct bnxt *bp = opaque_arg;
5245 unsigned long flow_xstat;
5248 if (!value || !opaque_arg) {
5250 "Invalid parameter passed to flow_xstat devarg.\n");
5254 flow_xstat = strtoul(value, &end, 10);
5255 if (end == NULL || *end != '\0' ||
5256 (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5258 "Invalid parameter passed to flow_xstat devarg.\n");
5262 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5264 "Invalid value passed to flow_xstat devarg.\n");
5268 bp->flow_xstat = flow_xstat;
5270 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5276 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5278 struct rte_kvargs *kvlist;
5280 if (devargs == NULL)
5283 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5288 * Handler for "truflow" devarg.
5289 * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1”
5291 rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5292 bnxt_parse_devarg_truflow, bp);
5295 * Handler for "flow_xstat" devarg.
5296 * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1”
5298 rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5299 bnxt_parse_devarg_flow_xstat, bp);
5301 rte_kvargs_free(kvlist);
5305 bnxt_dev_init(struct rte_eth_dev *eth_dev)
5307 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5308 static int version_printed;
5312 if (version_printed++ == 0)
5313 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5315 eth_dev->dev_ops = &bnxt_dev_ops;
5316 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5317 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5320 * For secondary processes, we don't initialise any further
5321 * as primary has already done this work.
5323 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5326 rte_eth_copy_pci_info(eth_dev, pci_dev);
5328 bp = eth_dev->data->dev_private;
5330 /* Parse dev arguments passed on when starting the DPDK application. */
5331 bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5333 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5335 if (bnxt_vf_pciid(pci_dev->id.device_id))
5336 bp->flags |= BNXT_FLAG_VF;
5338 if (bnxt_thor_device(pci_dev->id.device_id))
5339 bp->flags |= BNXT_FLAG_THOR_CHIP;
5341 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5342 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5343 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5344 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5345 bp->flags |= BNXT_FLAG_STINGRAY;
5347 rc = bnxt_init_board(eth_dev);
5350 "Failed to initialize board rc: %x\n", rc);
5354 rc = bnxt_alloc_hwrm_resources(bp);
5357 "Failed to allocate hwrm resource rc: %x\n", rc);
5360 rc = bnxt_init_resources(bp, false);
5364 rc = bnxt_alloc_stats_mem(bp);
5368 /* Pass the information to the rte_eth_dev_close() that it should also
5369 * release the private port resources.
5371 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5374 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5375 pci_dev->mem_resource[0].phys_addr,
5376 pci_dev->mem_resource[0].addr);
5381 bnxt_dev_uninit(eth_dev);
5386 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5395 ctx->dma = RTE_BAD_IOVA;
5396 ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5399 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5401 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5402 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5403 bp->rx_fc_out_tbl.ctx_id,
5407 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5408 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5409 bp->tx_fc_out_tbl.ctx_id,
5413 if (bp->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5414 bnxt_hwrm_ctx_unrgtr(bp, bp->rx_fc_in_tbl.ctx_id);
5415 bp->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5417 if (bp->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5418 bnxt_hwrm_ctx_unrgtr(bp, bp->rx_fc_out_tbl.ctx_id);
5419 bp->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5421 if (bp->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5422 bnxt_hwrm_ctx_unrgtr(bp, bp->tx_fc_in_tbl.ctx_id);
5423 bp->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5425 if (bp->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5426 bnxt_hwrm_ctx_unrgtr(bp, bp->tx_fc_out_tbl.ctx_id);
5427 bp->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5430 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5432 bnxt_unregister_fc_ctx_mem(bp);
5434 bnxt_free_ctx_mem_buf(&bp->rx_fc_in_tbl);
5435 bnxt_free_ctx_mem_buf(&bp->rx_fc_out_tbl);
5436 bnxt_free_ctx_mem_buf(&bp->tx_fc_in_tbl);
5437 bnxt_free_ctx_mem_buf(&bp->tx_fc_out_tbl);
5440 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5442 bnxt_uninit_fc_ctx_mem(bp);
5446 bnxt_free_error_recovery_info(struct bnxt *bp)
5448 rte_free(bp->recovery_info);
5449 bp->recovery_info = NULL;
5450 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5454 bnxt_uninit_locks(struct bnxt *bp)
5456 pthread_mutex_destroy(&bp->flow_lock);
5457 pthread_mutex_destroy(&bp->def_cp_lock);
5461 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5466 bnxt_free_mem(bp, reconfig_dev);
5467 bnxt_hwrm_func_buf_unrgtr(bp);
5468 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5469 bp->flags &= ~BNXT_FLAG_REGISTERED;
5470 bnxt_free_ctx_mem(bp);
5471 if (!reconfig_dev) {
5472 bnxt_free_hwrm_resources(bp);
5473 bnxt_free_error_recovery_info(bp);
5476 bnxt_uninit_ctx_mem(bp);
5478 bnxt_uninit_locks(bp);
5479 rte_free(bp->ptp_cfg);
5485 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5487 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5490 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5492 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5493 bnxt_dev_close_op(eth_dev);
5498 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5499 struct rte_pci_device *pci_dev)
5501 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
5505 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5507 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
5508 return rte_eth_dev_pci_generic_remove(pci_dev,
5511 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5514 static struct rte_pci_driver bnxt_rte_pmd = {
5515 .id_table = bnxt_pci_id_map,
5516 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5517 .probe = bnxt_pci_probe,
5518 .remove = bnxt_pci_remove,
5522 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5524 if (strcmp(dev->device->driver->name, drv->driver.name))
5530 bool is_bnxt_supported(struct rte_eth_dev *dev)
5532 return is_device_supported(dev, &bnxt_rte_pmd);
5535 RTE_INIT(bnxt_init_log)
5537 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
5538 if (bnxt_logtype_driver >= 0)
5539 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
5542 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5543 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5544 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");