4 * Copyright(c) Broadcom Limited.
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8 * modification, are permitted provided that the following conditions
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14 * notice, this list of conditions and the following disclaimer in
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 #include <rte_ethdev.h>
39 #include <rte_malloc.h>
40 #include <rte_cycles.h>
44 #include "bnxt_filter.h"
45 #include "bnxt_hwrm.h"
47 #include "bnxt_ring.h"
50 #include "bnxt_stats.h"
53 #include "bnxt_vnic.h"
54 #include "hsi_struct_def_dpdk.h"
56 #define DRV_MODULE_NAME "bnxt"
57 static const char bnxt_version[] =
58 "Broadcom Cumulus driver " DRV_MODULE_NAME "\n";
60 #define PCI_VENDOR_ID_BROADCOM 0x14E4
62 #define BROADCOM_DEV_ID_57301 0x16c8
63 #define BROADCOM_DEV_ID_57302 0x16c9
64 #define BROADCOM_DEV_ID_57304_PF 0x16ca
65 #define BROADCOM_DEV_ID_57304_VF 0x16cb
66 #define BROADCOM_DEV_ID_NS2 0x16cd
67 #define BROADCOM_DEV_ID_57402 0x16d0
68 #define BROADCOM_DEV_ID_57404 0x16d1
69 #define BROADCOM_DEV_ID_57406_PF 0x16d2
70 #define BROADCOM_DEV_ID_57406_VF 0x16d3
71 #define BROADCOM_DEV_ID_57402_MF 0x16d4
72 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
73 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
74 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
75 #define BROADCOM_DEV_ID_57404_MF 0x16e7
76 #define BROADCOM_DEV_ID_57406_MF 0x16e8
77 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
78 #define BROADCOM_DEV_ID_57407_MF 0x16ea
80 static struct rte_pci_id bnxt_pci_id_map[] = {
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
98 { .vendor_id = 0, /* sentinel */ },
101 #define BNXT_ETH_RSS_SUPPORT ( \
103 ETH_RSS_NONFRAG_IPV4_TCP | \
104 ETH_RSS_NONFRAG_IPV4_UDP | \
106 ETH_RSS_NONFRAG_IPV6_TCP | \
107 ETH_RSS_NONFRAG_IPV6_UDP)
109 /***********************/
112 * High level utility functions
115 static void bnxt_free_mem(struct bnxt *bp)
117 bnxt_free_filter_mem(bp);
118 bnxt_free_vnic_attributes(bp);
119 bnxt_free_vnic_mem(bp);
122 bnxt_free_tx_rings(bp);
123 bnxt_free_rx_rings(bp);
124 bnxt_free_def_cp_ring(bp);
127 static int bnxt_alloc_mem(struct bnxt *bp)
131 /* Default completion ring */
132 rc = bnxt_init_def_ring_struct(bp, SOCKET_ID_ANY);
136 rc = bnxt_alloc_rings(bp, 0, NULL, NULL,
137 bp->def_cp_ring, "def_cp");
141 rc = bnxt_alloc_vnic_mem(bp);
145 rc = bnxt_alloc_vnic_attributes(bp);
149 rc = bnxt_alloc_filter_mem(bp);
160 static int bnxt_init_chip(struct bnxt *bp)
162 unsigned int i, rss_idx, fw_idx;
163 struct rte_eth_link new;
166 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
168 RTE_LOG(ERR, PMD, "HWRM stat ctx alloc failure rc: %x\n", rc);
172 rc = bnxt_alloc_hwrm_rings(bp);
174 RTE_LOG(ERR, PMD, "HWRM ring alloc failure rc: %x\n", rc);
178 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
180 RTE_LOG(ERR, PMD, "HWRM ring grp alloc failure: %x\n", rc);
184 rc = bnxt_mq_rx_configure(bp);
186 RTE_LOG(ERR, PMD, "MQ mode configure failure rc: %x\n", rc);
190 /* VNIC configuration */
191 for (i = 0; i < bp->nr_vnics; i++) {
192 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
194 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
196 RTE_LOG(ERR, PMD, "HWRM vnic alloc failure rc: %x\n",
201 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
204 "HWRM vnic ctx alloc failure rc: %x\n", rc);
208 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
210 RTE_LOG(ERR, PMD, "HWRM vnic cfg failure rc: %x\n", rc);
214 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
216 RTE_LOG(ERR, PMD, "HWRM vnic filter failure rc: %x\n",
220 if (vnic->rss_table && vnic->hash_type) {
222 * Fill the RSS hash & redirection table with
223 * ring group ids for all VNICs
225 for (rss_idx = 0, fw_idx = 0;
226 rss_idx < HW_HASH_INDEX_SIZE;
227 rss_idx++, fw_idx++) {
228 if (vnic->fw_grp_ids[fw_idx] ==
231 vnic->rss_table[rss_idx] =
232 vnic->fw_grp_ids[fw_idx];
234 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
237 "HWRM vnic set RSS failure rc: %x\n",
243 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0]);
246 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
250 rc = bnxt_get_hwrm_link_config(bp, &new);
252 RTE_LOG(ERR, PMD, "HWRM Get link config failure rc: %x\n", rc);
256 if (!bp->link_info.link_up) {
257 rc = bnxt_set_hwrm_link_config(bp, true);
260 "HWRM link config failure rc: %x\n", rc);
268 bnxt_free_all_hwrm_resources(bp);
273 static int bnxt_shutdown_nic(struct bnxt *bp)
275 bnxt_free_all_hwrm_resources(bp);
276 bnxt_free_all_filters(bp);
277 bnxt_free_all_vnics(bp);
281 static int bnxt_init_nic(struct bnxt *bp)
285 bnxt_init_ring_grps(bp);
287 bnxt_init_filters(bp);
289 rc = bnxt_init_chip(bp);
297 * Device configuration and status function
300 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
301 struct rte_eth_dev_info *dev_info)
303 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
304 uint16_t max_vnics, i, j, vpool, vrxq;
306 dev_info->pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
309 dev_info->max_mac_addrs = MAX_NUM_MAC_ADDR;
310 dev_info->max_hash_mac_addrs = 0;
312 /* PF/VF specifics */
314 dev_info->max_rx_queues = bp->pf.max_rx_rings;
315 dev_info->max_tx_queues = bp->pf.max_tx_rings;
316 dev_info->max_vfs = bp->pf.active_vfs;
317 dev_info->reta_size = bp->pf.max_rsscos_ctx;
318 max_vnics = bp->pf.max_vnics;
320 dev_info->max_rx_queues = bp->vf.max_rx_rings;
321 dev_info->max_tx_queues = bp->vf.max_tx_rings;
322 dev_info->reta_size = bp->vf.max_rsscos_ctx;
323 max_vnics = bp->vf.max_vnics;
326 /* Fast path specifics */
327 dev_info->min_rx_bufsize = 1;
328 dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
330 dev_info->rx_offload_capa = 0;
331 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM |
332 DEV_TX_OFFLOAD_TCP_CKSUM |
333 DEV_TX_OFFLOAD_UDP_CKSUM |
334 DEV_TX_OFFLOAD_TCP_TSO;
337 dev_info->default_rxconf = (struct rte_eth_rxconf) {
343 .rx_free_thresh = 32,
347 dev_info->default_txconf = (struct rte_eth_txconf) {
353 .tx_free_thresh = 32,
355 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
356 ETH_TXQ_FLAGS_NOOFFLOADS,
358 eth_dev->data->dev_conf.intr_conf.lsc = 1;
363 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
364 * need further investigation.
368 vpool = 64; /* ETH_64_POOLS */
369 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
370 for (i = 0; i < 4; vpool >>= 1, i++) {
371 if (max_vnics > vpool) {
372 for (j = 0; j < 5; vrxq >>= 1, j++) {
373 if (dev_info->max_rx_queues > vrxq) {
379 /* Not enough resources to support VMDq */
383 /* Not enough resources to support VMDq */
387 dev_info->max_vmdq_pools = vpool;
388 dev_info->vmdq_queue_num = vrxq;
390 dev_info->vmdq_pool_base = 0;
391 dev_info->vmdq_queue_base = 0;
394 /* Configure the device based on the configuration provided */
395 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
397 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
399 bp->rx_queues = (void *)eth_dev->data->rx_queues;
400 bp->tx_queues = (void *)eth_dev->data->tx_queues;
402 /* Inherit new configurations */
403 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
404 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
405 bp->rx_cp_nr_rings = bp->rx_nr_rings;
406 bp->tx_cp_nr_rings = bp->tx_nr_rings;
408 if (eth_dev->data->dev_conf.rxmode.jumbo_frame)
410 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
411 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE;
416 rte_bnxt_atomic_write_link_status(struct rte_eth_dev *eth_dev,
417 struct rte_eth_link *link)
419 struct rte_eth_link *dst = ð_dev->data->dev_link;
420 struct rte_eth_link *src = link;
422 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
423 *(uint64_t *)src) == 0)
429 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
431 struct rte_eth_link *link = ð_dev->data->dev_link;
433 if (link->link_status)
434 RTE_LOG(INFO, PMD, "Port %d Link Up - speed %u Mbps - %s\n",
435 (uint8_t)(eth_dev->data->port_id),
436 (uint32_t)link->link_speed,
437 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
438 ("full-duplex") : ("half-duplex\n"));
440 RTE_LOG(INFO, PMD, "Port %d Link Down\n",
441 (uint8_t)(eth_dev->data->port_id));
444 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
446 bnxt_print_link_info(eth_dev);
450 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
452 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
456 rc = bnxt_hwrm_func_reset(bp);
458 RTE_LOG(ERR, PMD, "hwrm chip reset failure rc: %x\n", rc);
463 rc = bnxt_setup_int(bp);
467 rc = bnxt_alloc_mem(bp);
471 rc = bnxt_request_int(bp);
475 rc = bnxt_init_nic(bp);
481 bnxt_link_update_op(eth_dev, 0);
485 bnxt_shutdown_nic(bp);
486 bnxt_disable_int(bp);
488 bnxt_free_tx_mbufs(bp);
489 bnxt_free_rx_mbufs(bp);
494 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
496 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
498 eth_dev->data->dev_link.link_status = 1;
499 bnxt_set_hwrm_link_config(bp, true);
503 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
505 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
507 eth_dev->data->dev_link.link_status = 0;
508 bnxt_set_hwrm_link_config(bp, false);
512 /* Unload the driver, release resources */
513 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
515 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
517 if (bp->eth_dev->data->dev_started) {
518 /* TBD: STOP HW queues DMA */
519 eth_dev->data->dev_link.link_status = 0;
521 bnxt_set_hwrm_link_config(bp, false);
522 bnxt_disable_int(bp);
524 bnxt_shutdown_nic(bp);
528 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
530 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
532 if (bp->dev_stopped == 0)
533 bnxt_dev_stop_op(eth_dev);
535 bnxt_free_tx_mbufs(bp);
536 bnxt_free_rx_mbufs(bp);
538 if (eth_dev->data->mac_addrs != NULL) {
539 rte_free(eth_dev->data->mac_addrs);
540 eth_dev->data->mac_addrs = NULL;
542 if (bp->grp_info != NULL) {
543 rte_free(bp->grp_info);
548 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
551 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
552 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
553 struct bnxt_vnic_info *vnic;
554 struct bnxt_filter_info *filter, *temp_filter;
558 * Loop through all VNICs from the specified filter flow pools to
559 * remove the corresponding MAC addr filter
561 for (i = 0; i < MAX_FF_POOLS; i++) {
562 if (!(pool_mask & (1ULL << i)))
565 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
566 filter = STAILQ_FIRST(&vnic->filter);
568 temp_filter = STAILQ_NEXT(filter, next);
569 if (filter->mac_index == index) {
570 STAILQ_REMOVE(&vnic->filter, filter,
571 bnxt_filter_info, next);
572 bnxt_hwrm_clear_filter(bp, filter);
573 filter->mac_index = INVALID_MAC_INDEX;
574 memset(&filter->l2_addr, 0,
577 &bp->free_filter_list,
580 filter = temp_filter;
586 static void bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
587 struct ether_addr *mac_addr,
588 uint32_t index, uint32_t pool)
590 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
591 struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]);
592 struct bnxt_filter_info *filter;
595 RTE_LOG(ERR, PMD, "Cannot add MAC address to a VF interface\n");
600 RTE_LOG(ERR, PMD, "VNIC not found for pool %d!\n", pool);
603 /* Attach requested MAC address to the new l2_filter */
604 STAILQ_FOREACH(filter, &vnic->filter, next) {
605 if (filter->mac_index == index) {
607 "MAC addr already existed for pool %d\n", pool);
611 filter = bnxt_alloc_filter(bp);
613 RTE_LOG(ERR, PMD, "L2 filter alloc failed\n");
616 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
617 filter->mac_index = index;
618 memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
619 bnxt_hwrm_set_filter(bp, vnic, filter);
622 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
625 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
626 struct rte_eth_link new;
627 unsigned int cnt = BNXT_LINK_WAIT_CNT;
629 memset(&new, 0, sizeof(new));
631 /* Retrieve link info from hardware */
632 rc = bnxt_get_hwrm_link_config(bp, &new);
634 new.link_speed = ETH_LINK_SPEED_100M;
635 new.link_duplex = ETH_LINK_FULL_DUPLEX;
637 "Failed to retrieve link rc = 0x%x!", rc);
640 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
642 if (!wait_to_complete)
644 } while (!new.link_status && cnt--);
647 /* Timed out or success */
648 if (new.link_status != eth_dev->data->dev_link.link_status ||
649 new.link_speed != eth_dev->data->dev_link.link_speed) {
650 rte_bnxt_atomic_write_link_status(eth_dev, &new);
651 bnxt_print_link_info(eth_dev);
657 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
659 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
660 struct bnxt_vnic_info *vnic;
662 if (bp->vnic_info == NULL)
665 vnic = &bp->vnic_info[0];
667 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
668 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
671 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
673 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
674 struct bnxt_vnic_info *vnic;
676 if (bp->vnic_info == NULL)
679 vnic = &bp->vnic_info[0];
681 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
682 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
685 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
687 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
688 struct bnxt_vnic_info *vnic;
690 if (bp->vnic_info == NULL)
693 vnic = &bp->vnic_info[0];
695 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
696 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
699 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
701 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
702 struct bnxt_vnic_info *vnic;
704 if (bp->vnic_info == NULL)
707 vnic = &bp->vnic_info[0];
709 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
710 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
713 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
714 struct rte_eth_rss_reta_entry64 *reta_conf,
717 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
718 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
719 struct bnxt_vnic_info *vnic;
722 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
725 if (reta_size != HW_HASH_INDEX_SIZE) {
726 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
727 "(%d) must equal the size supported by the hardware "
728 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
731 /* Update the RSS VNIC(s) */
732 for (i = 0; i < MAX_FF_POOLS; i++) {
733 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
734 memcpy(vnic->rss_table, reta_conf, reta_size);
736 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
742 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
743 struct rte_eth_rss_reta_entry64 *reta_conf,
746 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
747 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
748 struct rte_intr_handle *intr_handle
749 = &bp->pdev->intr_handle;
751 /* Retrieve from the default VNIC */
754 if (!vnic->rss_table)
757 if (reta_size != HW_HASH_INDEX_SIZE) {
758 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
759 "(%d) must equal the size supported by the hardware "
760 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
763 /* EW - need to revisit here copying from u64 to u16 */
764 memcpy(reta_conf, vnic->rss_table, reta_size);
766 if (rte_intr_allow_others(intr_handle)) {
767 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
768 bnxt_dev_lsc_intr_setup(eth_dev);
774 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
775 struct rte_eth_rss_conf *rss_conf)
777 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
778 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
779 struct bnxt_vnic_info *vnic;
780 uint16_t hash_type = 0;
784 * If RSS enablement were different than dev_configure,
785 * then return -EINVAL
787 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
788 if (!rss_conf->rss_hf)
791 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
794 if (rss_conf->rss_hf & ETH_RSS_IPV4)
795 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
796 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
797 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
798 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
799 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
800 if (rss_conf->rss_hf & ETH_RSS_IPV6)
801 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
802 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
803 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
804 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
805 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
807 /* Update the RSS VNIC(s) */
808 for (i = 0; i < MAX_FF_POOLS; i++) {
809 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
810 vnic->hash_type = hash_type;
813 * Use the supplied key if the key length is
814 * acceptable and the rss_key is not NULL
816 if (rss_conf->rss_key &&
817 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
818 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
819 rss_conf->rss_key_len);
821 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
827 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
828 struct rte_eth_rss_conf *rss_conf)
830 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
831 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
835 /* RSS configuration is the same for all VNICs */
836 if (vnic && vnic->rss_hash_key) {
837 if (rss_conf->rss_key) {
838 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
839 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
840 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
843 hash_types = vnic->hash_type;
844 rss_conf->rss_hf = 0;
845 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
846 rss_conf->rss_hf |= ETH_RSS_IPV4;
847 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
849 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
850 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
852 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
854 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
855 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
857 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
859 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
860 rss_conf->rss_hf |= ETH_RSS_IPV6;
861 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
863 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
864 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
866 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
868 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
869 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
871 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
875 "Unknwon RSS config from firmware (%08x), RSS disabled",
880 rss_conf->rss_hf = 0;
885 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
886 struct rte_eth_fc_conf *fc_conf __rte_unused)
888 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
889 struct rte_eth_link link_info;
892 rc = bnxt_get_hwrm_link_config(bp, &link_info);
896 memset(fc_conf, 0, sizeof(*fc_conf));
897 if (bp->link_info.auto_pause)
898 fc_conf->autoneg = 1;
899 switch (bp->link_info.pause) {
901 fc_conf->mode = RTE_FC_NONE;
903 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
904 fc_conf->mode = RTE_FC_TX_PAUSE;
906 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
907 fc_conf->mode = RTE_FC_RX_PAUSE;
909 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
910 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
911 fc_conf->mode = RTE_FC_FULL;
917 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
918 struct rte_eth_fc_conf *fc_conf)
920 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
922 if (BNXT_NPAR_PF(bp) || BNXT_VF(bp)) {
923 RTE_LOG(ERR, PMD, "Flow Control Settings cannot be modified\n");
927 switch (fc_conf->mode) {
929 bp->link_info.auto_pause = 0;
930 bp->link_info.force_pause = 0;
932 case RTE_FC_RX_PAUSE:
933 if (fc_conf->autoneg) {
934 bp->link_info.auto_pause =
935 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
936 bp->link_info.force_pause = 0;
938 bp->link_info.auto_pause = 0;
939 bp->link_info.force_pause =
940 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
943 case RTE_FC_TX_PAUSE:
944 if (fc_conf->autoneg) {
945 bp->link_info.auto_pause =
946 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
947 bp->link_info.force_pause = 0;
949 bp->link_info.auto_pause = 0;
950 bp->link_info.force_pause =
951 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
955 if (fc_conf->autoneg) {
956 bp->link_info.auto_pause =
957 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
958 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
959 bp->link_info.force_pause = 0;
961 bp->link_info.auto_pause = 0;
962 bp->link_info.force_pause =
963 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
964 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
968 return bnxt_set_hwrm_link_config(bp, true);
975 static struct eth_dev_ops bnxt_dev_ops = {
976 .dev_infos_get = bnxt_dev_info_get_op,
977 .dev_close = bnxt_dev_close_op,
978 .dev_configure = bnxt_dev_configure_op,
979 .dev_start = bnxt_dev_start_op,
980 .dev_stop = bnxt_dev_stop_op,
981 .dev_set_link_up = bnxt_dev_set_link_up_op,
982 .dev_set_link_down = bnxt_dev_set_link_down_op,
983 .stats_get = bnxt_stats_get_op,
984 .stats_reset = bnxt_stats_reset_op,
985 .rx_queue_setup = bnxt_rx_queue_setup_op,
986 .rx_queue_release = bnxt_rx_queue_release_op,
987 .tx_queue_setup = bnxt_tx_queue_setup_op,
988 .tx_queue_release = bnxt_tx_queue_release_op,
989 .reta_update = bnxt_reta_update_op,
990 .reta_query = bnxt_reta_query_op,
991 .rss_hash_update = bnxt_rss_hash_update_op,
992 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
993 .link_update = bnxt_link_update_op,
994 .promiscuous_enable = bnxt_promiscuous_enable_op,
995 .promiscuous_disable = bnxt_promiscuous_disable_op,
996 .allmulticast_enable = bnxt_allmulticast_enable_op,
997 .allmulticast_disable = bnxt_allmulticast_disable_op,
998 .mac_addr_add = bnxt_mac_addr_add_op,
999 .mac_addr_remove = bnxt_mac_addr_remove_op,
1000 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
1001 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
1004 static bool bnxt_vf_pciid(uint16_t id)
1006 if (id == BROADCOM_DEV_ID_57304_VF ||
1007 id == BROADCOM_DEV_ID_57406_VF ||
1008 id == BROADCOM_DEV_ID_5731X_VF ||
1009 id == BROADCOM_DEV_ID_5741X_VF)
1014 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
1016 struct bnxt *bp = eth_dev->data->dev_private;
1017 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1020 /* enable device (incl. PCI PM wakeup), and bus-mastering */
1021 if (!pci_dev->mem_resource[0].addr) {
1023 "Cannot find PCI device base address, aborting\n");
1025 goto init_err_disable;
1028 bp->eth_dev = eth_dev;
1031 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
1033 RTE_LOG(ERR, PMD, "Cannot map device registers, aborting\n");
1035 goto init_err_release;
1049 bnxt_dev_init(struct rte_eth_dev *eth_dev)
1051 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1052 static int version_printed;
1056 if (version_printed++ == 0)
1057 RTE_LOG(INFO, PMD, "%s", bnxt_version);
1059 rte_eth_copy_pci_info(eth_dev, pci_dev);
1060 eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1061 bp = eth_dev->data->dev_private;
1063 if (bnxt_vf_pciid(pci_dev->id.device_id))
1064 bp->flags |= BNXT_FLAG_VF;
1066 rc = bnxt_init_board(eth_dev);
1069 "Board initialization failed rc: %x\n", rc);
1072 eth_dev->dev_ops = &bnxt_dev_ops;
1073 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
1074 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
1076 rc = bnxt_alloc_hwrm_resources(bp);
1079 "hwrm resource allocation failure rc: %x\n", rc);
1082 rc = bnxt_hwrm_ver_get(bp);
1085 bnxt_hwrm_queue_qportcfg(bp);
1087 bnxt_hwrm_func_qcfg(bp);
1089 /* Get the MAX capabilities for this function */
1090 rc = bnxt_hwrm_func_qcaps(bp);
1092 RTE_LOG(ERR, PMD, "hwrm query capability failure rc: %x\n", rc);
1095 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
1096 ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR, 0);
1097 if (eth_dev->data->mac_addrs == NULL) {
1099 "Failed to alloc %u bytes needed to store MAC addr tbl",
1100 ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR);
1104 /* Copy the permanent MAC from the qcap response address now. */
1106 memcpy(bp->mac_addr, bp->pf.mac_addr, sizeof(bp->mac_addr));
1108 memcpy(bp->mac_addr, bp->vf.mac_addr, sizeof(bp->mac_addr));
1109 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
1110 bp->grp_info = rte_zmalloc("bnxt_grp_info",
1111 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
1112 if (!bp->grp_info) {
1114 "Failed to alloc %zu bytes needed to store group info table\n",
1115 sizeof(*bp->grp_info) * bp->max_ring_grps);
1120 rc = bnxt_hwrm_func_driver_register(bp, 0,
1124 "Failed to register driver");
1130 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
1131 pci_dev->mem_resource[0].phys_addr,
1132 pci_dev->mem_resource[0].addr);
1134 bp->dev_stopped = 0;
1139 eth_dev->driver->eth_dev_uninit(eth_dev);
1145 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) {
1146 struct bnxt *bp = eth_dev->data->dev_private;
1149 if (eth_dev->data->mac_addrs != NULL) {
1150 rte_free(eth_dev->data->mac_addrs);
1151 eth_dev->data->mac_addrs = NULL;
1153 if (bp->grp_info != NULL) {
1154 rte_free(bp->grp_info);
1155 bp->grp_info = NULL;
1157 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
1158 bnxt_free_hwrm_resources(bp);
1159 if (bp->dev_stopped == 0)
1160 bnxt_dev_close_op(eth_dev);
1161 eth_dev->dev_ops = NULL;
1162 eth_dev->rx_pkt_burst = NULL;
1163 eth_dev->tx_pkt_burst = NULL;
1168 static struct eth_driver bnxt_rte_pmd = {
1170 .id_table = bnxt_pci_id_map,
1171 .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
1172 RTE_PCI_DRV_INTR_LSC,
1173 .probe = rte_eth_dev_pci_probe,
1174 .remove = rte_eth_dev_pci_remove
1176 .eth_dev_init = bnxt_dev_init,
1177 .eth_dev_uninit = bnxt_dev_uninit,
1178 .dev_private_size = sizeof(struct bnxt),
1181 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd.pci_drv);
1182 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
1183 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio");