1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
15 #include <rte_kvargs.h>
19 #include "bnxt_filter.h"
20 #include "bnxt_hwrm.h"
22 #include "bnxt_reps.h"
23 #include "bnxt_ring.h"
26 #include "bnxt_stats.h"
29 #include "bnxt_vnic.h"
30 #include "hsi_struct_def_dpdk.h"
31 #include "bnxt_nvm_defs.h"
32 #include "bnxt_tf_common.h"
33 #include "ulp_flow_db.h"
34 #include "rte_pmd_bnxt.h"
36 #define DRV_MODULE_NAME "bnxt"
37 static const char bnxt_version[] =
38 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
41 * The set of PCI devices this driver supports
43 static const struct rte_pci_id bnxt_pci_id_map[] = {
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
45 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
47 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
87 { .vendor_id = 0, /* sentinel */ },
90 #define BNXT_DEVARG_TRUFLOW "host-based-truflow"
91 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat"
92 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows"
93 #define BNXT_DEVARG_REPRESENTOR "representor"
94 #define BNXT_DEVARG_REP_BASED_PF "rep-based-pf"
95 #define BNXT_DEVARG_REP_IS_PF "rep-is-pf"
96 #define BNXT_DEVARG_REP_Q_R2F "rep-q-r2f"
97 #define BNXT_DEVARG_REP_Q_F2R "rep-q-f2r"
98 #define BNXT_DEVARG_REP_FC_R2F "rep-fc-r2f"
99 #define BNXT_DEVARG_REP_FC_F2R "rep-fc-f2r"
101 static const char *const bnxt_dev_args[] = {
102 BNXT_DEVARG_REPRESENTOR,
104 BNXT_DEVARG_FLOW_XSTAT,
105 BNXT_DEVARG_MAX_NUM_KFLOWS,
106 BNXT_DEVARG_REP_BASED_PF,
107 BNXT_DEVARG_REP_IS_PF,
108 BNXT_DEVARG_REP_Q_R2F,
109 BNXT_DEVARG_REP_Q_F2R,
110 BNXT_DEVARG_REP_FC_R2F,
111 BNXT_DEVARG_REP_FC_F2R,
116 * truflow == false to disable the feature
117 * truflow == true to enable the feature
119 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1)
122 * flow_xstat == false to disable the feature
123 * flow_xstat == true to enable the feature
125 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1)
128 * rep_is_pf == false to indicate VF representor
129 * rep_is_pf == true to indicate PF representor
131 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf) ((rep_is_pf) > 1)
134 * rep_based_pf == Physical index of the PF
136 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf) ((rep_based_pf) > 15)
138 * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
140 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f) ((rep_q_r2f) > 3)
143 * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
145 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r) ((rep_q_f2r) > 3)
148 * rep_fc_r2f == Flow control for the representor to endpoint direction
150 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f) ((rep_fc_r2f) > 1)
153 * rep_fc_f2r == Flow control for the endpoint to representor direction
155 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r) ((rep_fc_f2r) > 1)
157 int bnxt_cfa_code_dynfield_offset = -1;
160 * max_num_kflows must be >= 32
161 * and must be a power-of-2 supported value
162 * return: 1 -> invalid
165 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
167 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
172 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
173 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
174 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
175 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
176 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
177 static int bnxt_restore_vlan_filters(struct bnxt *bp);
178 static void bnxt_dev_recover(void *arg);
179 static void bnxt_free_error_recovery_info(struct bnxt *bp);
180 static void bnxt_free_rep_info(struct bnxt *bp);
182 int is_bnxt_in_error(struct bnxt *bp)
184 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
186 if (bp->flags & BNXT_FLAG_FW_RESET)
192 /***********************/
195 * High level utility functions
198 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
200 unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
201 BNXT_RSS_TBL_SIZE_P5);
203 if (!BNXT_CHIP_P5(bp))
206 return RTE_ALIGN_MUL_CEIL(num_rss_rings,
207 BNXT_RSS_ENTRIES_PER_CTX_P5) /
208 BNXT_RSS_ENTRIES_PER_CTX_P5;
211 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
213 if (!BNXT_CHIP_P5(bp))
214 return HW_HASH_INDEX_SIZE;
216 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
219 static void bnxt_free_parent_info(struct bnxt *bp)
221 rte_free(bp->parent);
224 static void bnxt_free_pf_info(struct bnxt *bp)
229 static void bnxt_free_link_info(struct bnxt *bp)
231 rte_free(bp->link_info);
234 static void bnxt_free_leds_info(struct bnxt *bp)
243 static void bnxt_free_flow_stats_info(struct bnxt *bp)
245 rte_free(bp->flow_stat);
246 bp->flow_stat = NULL;
249 static void bnxt_free_cos_queues(struct bnxt *bp)
251 rte_free(bp->rx_cos_queue);
252 rte_free(bp->tx_cos_queue);
255 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
257 bnxt_free_filter_mem(bp);
258 bnxt_free_vnic_attributes(bp);
259 bnxt_free_vnic_mem(bp);
261 /* tx/rx rings are configured as part of *_queue_setup callbacks.
262 * If the number of rings change across fw update,
263 * we don't have much choice except to warn the user.
267 bnxt_free_tx_rings(bp);
268 bnxt_free_rx_rings(bp);
270 bnxt_free_async_cp_ring(bp);
271 bnxt_free_rxtx_nq_ring(bp);
273 rte_free(bp->grp_info);
277 static int bnxt_alloc_parent_info(struct bnxt *bp)
279 bp->parent = rte_zmalloc("bnxt_parent_info",
280 sizeof(struct bnxt_parent_info), 0);
281 if (bp->parent == NULL)
287 static int bnxt_alloc_pf_info(struct bnxt *bp)
289 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
296 static int bnxt_alloc_link_info(struct bnxt *bp)
299 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
300 if (bp->link_info == NULL)
306 static int bnxt_alloc_leds_info(struct bnxt *bp)
311 bp->leds = rte_zmalloc("bnxt_leds",
312 BNXT_MAX_LED * sizeof(struct bnxt_led_info),
314 if (bp->leds == NULL)
320 static int bnxt_alloc_cos_queues(struct bnxt *bp)
323 rte_zmalloc("bnxt_rx_cosq",
324 BNXT_COS_QUEUE_COUNT *
325 sizeof(struct bnxt_cos_queue_info),
327 if (bp->rx_cos_queue == NULL)
331 rte_zmalloc("bnxt_tx_cosq",
332 BNXT_COS_QUEUE_COUNT *
333 sizeof(struct bnxt_cos_queue_info),
335 if (bp->tx_cos_queue == NULL)
341 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
343 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
344 sizeof(struct bnxt_flow_stat_info), 0);
345 if (bp->flow_stat == NULL)
351 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
355 rc = bnxt_alloc_ring_grps(bp);
359 rc = bnxt_alloc_async_ring_struct(bp);
363 rc = bnxt_alloc_vnic_mem(bp);
367 rc = bnxt_alloc_vnic_attributes(bp);
371 rc = bnxt_alloc_filter_mem(bp);
375 rc = bnxt_alloc_async_cp_ring(bp);
379 rc = bnxt_alloc_rxtx_nq_ring(bp);
383 if (BNXT_FLOW_XSTATS_EN(bp)) {
384 rc = bnxt_alloc_flow_stats_info(bp);
392 bnxt_free_mem(bp, reconfig);
396 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
398 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
399 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
400 uint64_t rx_offloads = dev_conf->rxmode.offloads;
401 struct bnxt_rx_queue *rxq;
405 rc = bnxt_vnic_grp_alloc(bp, vnic);
409 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
410 vnic_id, vnic, vnic->fw_grp_ids);
412 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
416 /* Alloc RSS context only if RSS mode is enabled */
417 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
418 int j, nr_ctxs = bnxt_rss_ctxts(bp);
420 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
421 PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
422 bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
424 "Only queues 0-%d will be in RSS table\n",
425 BNXT_RSS_TBL_SIZE_P5 - 1);
429 for (j = 0; j < nr_ctxs; j++) {
430 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
436 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
440 vnic->num_lb_ctxts = nr_ctxs;
444 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
445 * setting is not available at this time, it will not be
446 * configured correctly in the CFA.
448 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
449 vnic->vlan_strip = true;
451 vnic->vlan_strip = false;
453 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
457 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
461 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
462 rxq = bp->eth_dev->data->rx_queues[j];
465 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
466 j, rxq->vnic, rxq->vnic->fw_grp_ids);
468 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
469 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
471 vnic->rx_queue_cnt++;
474 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
476 rc = bnxt_vnic_rss_configure(bp, vnic);
480 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
482 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
483 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
485 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
489 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
494 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
498 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
499 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
504 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
505 " rx_fc_in_tbl.ctx_id = %d\n",
506 bp->flow_stat->rx_fc_in_tbl.va,
507 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
508 bp->flow_stat->rx_fc_in_tbl.ctx_id);
510 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
511 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
516 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
517 " rx_fc_out_tbl.ctx_id = %d\n",
518 bp->flow_stat->rx_fc_out_tbl.va,
519 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
520 bp->flow_stat->rx_fc_out_tbl.ctx_id);
522 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
523 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
528 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
529 " tx_fc_in_tbl.ctx_id = %d\n",
530 bp->flow_stat->tx_fc_in_tbl.va,
531 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
532 bp->flow_stat->tx_fc_in_tbl.ctx_id);
534 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
535 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
540 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
541 " tx_fc_out_tbl.ctx_id = %d\n",
542 bp->flow_stat->tx_fc_out_tbl.va,
543 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
544 bp->flow_stat->tx_fc_out_tbl.ctx_id);
546 memset(bp->flow_stat->rx_fc_out_tbl.va,
548 bp->flow_stat->rx_fc_out_tbl.size);
549 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
550 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
551 bp->flow_stat->rx_fc_out_tbl.ctx_id,
552 bp->flow_stat->max_fc,
557 memset(bp->flow_stat->tx_fc_out_tbl.va,
559 bp->flow_stat->tx_fc_out_tbl.size);
560 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
561 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
562 bp->flow_stat->tx_fc_out_tbl.ctx_id,
563 bp->flow_stat->max_fc,
569 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
570 struct bnxt_ctx_mem_buf_info *ctx)
575 ctx->va = rte_zmalloc(type, size, 0);
578 rte_mem_lock_page(ctx->va);
580 ctx->dma = rte_mem_virt2iova(ctx->va);
581 if (ctx->dma == RTE_BAD_IOVA)
587 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
589 struct rte_pci_device *pdev = bp->pdev;
590 char type[RTE_MEMZONE_NAMESIZE];
594 max_fc = bp->flow_stat->max_fc;
596 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
597 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
598 /* 4 bytes for each counter-id */
599 rc = bnxt_alloc_ctx_mem_buf(type,
601 &bp->flow_stat->rx_fc_in_tbl);
605 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
606 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
607 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
608 rc = bnxt_alloc_ctx_mem_buf(type,
610 &bp->flow_stat->rx_fc_out_tbl);
614 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
615 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
616 /* 4 bytes for each counter-id */
617 rc = bnxt_alloc_ctx_mem_buf(type,
619 &bp->flow_stat->tx_fc_in_tbl);
623 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
624 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
625 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
626 rc = bnxt_alloc_ctx_mem_buf(type,
628 &bp->flow_stat->tx_fc_out_tbl);
632 rc = bnxt_register_fc_ctx_mem(bp);
637 static int bnxt_init_ctx_mem(struct bnxt *bp)
641 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
642 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
643 !BNXT_FLOW_XSTATS_EN(bp))
646 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
650 rc = bnxt_init_fc_ctx_mem(bp);
655 static int bnxt_update_phy_setting(struct bnxt *bp)
657 struct rte_eth_link new;
660 rc = bnxt_get_hwrm_link_config(bp, &new);
662 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
667 * On BCM957508-N2100 adapters, FW will not allow any user other
668 * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
669 * always returns link up. Force phy update always in that case.
671 if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
672 rc = bnxt_set_hwrm_link_config(bp, true);
674 PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
682 static int bnxt_init_chip(struct bnxt *bp)
684 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
685 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
686 uint32_t intr_vector = 0;
687 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
688 uint32_t vec = BNXT_MISC_VEC_ID;
692 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
693 bp->eth_dev->data->dev_conf.rxmode.offloads |=
694 DEV_RX_OFFLOAD_JUMBO_FRAME;
695 bp->flags |= BNXT_FLAG_JUMBO;
697 bp->eth_dev->data->dev_conf.rxmode.offloads &=
698 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
699 bp->flags &= ~BNXT_FLAG_JUMBO;
702 /* THOR does not support ring groups.
703 * But we will use the array to save RSS context IDs.
705 if (BNXT_CHIP_P5(bp))
706 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
708 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
710 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
714 rc = bnxt_alloc_hwrm_rings(bp);
716 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
720 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
722 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
726 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
729 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
730 if (bp->rx_cos_queue[i].id != 0xff) {
731 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
735 "Num pools more than FW profile\n");
739 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
745 rc = bnxt_mq_rx_configure(bp);
747 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
752 rc = bnxt_setup_one_vnic(bp, 0);
755 /* VNIC configuration */
756 if (BNXT_RFS_NEEDS_VNIC(bp)) {
757 for (i = 1; i < bp->nr_vnics; i++) {
758 rc = bnxt_setup_one_vnic(bp, i);
764 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
767 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
771 /* check and configure queue intr-vector mapping */
772 if ((rte_intr_cap_multiple(intr_handle) ||
773 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
774 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
775 intr_vector = bp->eth_dev->data->nb_rx_queues;
776 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
777 if (intr_vector > bp->rx_cp_nr_rings) {
778 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
782 rc = rte_intr_efd_enable(intr_handle, intr_vector);
787 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
788 intr_handle->intr_vec =
789 rte_zmalloc("intr_vec",
790 bp->eth_dev->data->nb_rx_queues *
792 if (intr_handle->intr_vec == NULL) {
793 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
794 " intr_vec", bp->eth_dev->data->nb_rx_queues);
798 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
799 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
800 intr_handle->intr_vec, intr_handle->nb_efd,
801 intr_handle->max_intr);
802 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
804 intr_handle->intr_vec[queue_id] =
805 vec + BNXT_RX_VEC_START;
806 if (vec < base + intr_handle->nb_efd - 1)
811 /* enable uio/vfio intr/eventfd mapping */
812 rc = rte_intr_enable(intr_handle);
813 #ifndef RTE_EXEC_ENV_FREEBSD
814 /* In FreeBSD OS, nic_uio driver does not support interrupts */
819 rc = bnxt_update_phy_setting(bp);
823 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
825 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
830 rte_free(intr_handle->intr_vec);
832 rte_intr_efd_disable(intr_handle);
834 /* Some of the error status returned by FW may not be from errno.h */
841 static int bnxt_shutdown_nic(struct bnxt *bp)
843 bnxt_free_all_hwrm_resources(bp);
844 bnxt_free_all_filters(bp);
845 bnxt_free_all_vnics(bp);
850 * Device configuration and status function
853 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
855 uint32_t link_speed = bp->link_info->support_speeds;
856 uint32_t speed_capa = 0;
858 /* If PAM4 is configured, use PAM4 supported speed */
859 if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
860 link_speed = bp->link_info->support_pam4_speeds;
862 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
863 speed_capa |= ETH_LINK_SPEED_100M;
864 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
865 speed_capa |= ETH_LINK_SPEED_100M_HD;
866 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
867 speed_capa |= ETH_LINK_SPEED_1G;
868 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
869 speed_capa |= ETH_LINK_SPEED_2_5G;
870 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
871 speed_capa |= ETH_LINK_SPEED_10G;
872 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
873 speed_capa |= ETH_LINK_SPEED_20G;
874 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
875 speed_capa |= ETH_LINK_SPEED_25G;
876 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
877 speed_capa |= ETH_LINK_SPEED_40G;
878 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
879 speed_capa |= ETH_LINK_SPEED_50G;
880 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
881 speed_capa |= ETH_LINK_SPEED_100G;
882 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
883 speed_capa |= ETH_LINK_SPEED_50G;
884 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
885 speed_capa |= ETH_LINK_SPEED_100G;
886 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
887 speed_capa |= ETH_LINK_SPEED_200G;
889 if (bp->link_info->auto_mode ==
890 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
891 speed_capa |= ETH_LINK_SPEED_FIXED;
893 speed_capa |= ETH_LINK_SPEED_AUTONEG;
898 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
899 struct rte_eth_dev_info *dev_info)
901 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
902 struct bnxt *bp = eth_dev->data->dev_private;
903 uint16_t max_vnics, i, j, vpool, vrxq;
904 unsigned int max_rx_rings;
907 rc = is_bnxt_in_error(bp);
912 dev_info->max_mac_addrs = bp->max_l2_ctx;
913 dev_info->max_hash_mac_addrs = 0;
915 /* PF/VF specifics */
917 dev_info->max_vfs = pdev->max_vfs;
919 max_rx_rings = bnxt_max_rings(bp);
920 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
921 dev_info->max_rx_queues = max_rx_rings;
922 dev_info->max_tx_queues = max_rx_rings;
923 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
924 dev_info->hash_key_size = 40;
925 max_vnics = bp->max_vnics;
928 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
929 dev_info->max_mtu = BNXT_MAX_MTU;
931 /* Fast path specifics */
932 dev_info->min_rx_bufsize = 1;
933 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
935 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
936 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
937 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
938 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
939 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
940 dev_info->tx_queue_offload_capa;
941 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
943 dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
946 dev_info->default_rxconf = (struct rte_eth_rxconf) {
952 .rx_free_thresh = 32,
953 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
956 dev_info->default_txconf = (struct rte_eth_txconf) {
962 .tx_free_thresh = 32,
965 eth_dev->data->dev_conf.intr_conf.lsc = 1;
967 eth_dev->data->dev_conf.intr_conf.rxq = 1;
968 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
969 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
970 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
971 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
973 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
974 dev_info->switch_info.name = eth_dev->device->name;
975 dev_info->switch_info.domain_id = bp->switch_domain_id;
976 dev_info->switch_info.port_id =
977 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
978 BNXT_SWITCH_PORT_ID_TRUSTED_VF;
984 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
985 * need further investigation.
989 vpool = 64; /* ETH_64_POOLS */
990 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
991 for (i = 0; i < 4; vpool >>= 1, i++) {
992 if (max_vnics > vpool) {
993 for (j = 0; j < 5; vrxq >>= 1, j++) {
994 if (dev_info->max_rx_queues > vrxq) {
1000 /* Not enough resources to support VMDq */
1004 /* Not enough resources to support VMDq */
1008 dev_info->max_vmdq_pools = vpool;
1009 dev_info->vmdq_queue_num = vrxq;
1011 dev_info->vmdq_pool_base = 0;
1012 dev_info->vmdq_queue_base = 0;
1017 /* Configure the device based on the configuration provided */
1018 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1020 struct bnxt *bp = eth_dev->data->dev_private;
1021 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1024 bp->rx_queues = (void *)eth_dev->data->rx_queues;
1025 bp->tx_queues = (void *)eth_dev->data->tx_queues;
1026 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1027 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1029 rc = is_bnxt_in_error(bp);
1033 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1034 rc = bnxt_hwrm_check_vf_rings(bp);
1036 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1040 /* If a resource has already been allocated - in this case
1041 * it is the async completion ring, free it. Reallocate it after
1042 * resource reservation. This will ensure the resource counts
1043 * are calculated correctly.
1046 pthread_mutex_lock(&bp->def_cp_lock);
1048 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1049 bnxt_disable_int(bp);
1050 bnxt_free_cp_ring(bp, bp->async_cp_ring);
1053 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1055 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1056 pthread_mutex_unlock(&bp->def_cp_lock);
1060 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1061 rc = bnxt_alloc_async_cp_ring(bp);
1063 pthread_mutex_unlock(&bp->def_cp_lock);
1066 bnxt_enable_int(bp);
1069 pthread_mutex_unlock(&bp->def_cp_lock);
1072 /* Inherit new configurations */
1073 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1074 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1075 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1076 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1077 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1079 goto resource_error;
1081 if (BNXT_HAS_RING_GRPS(bp) &&
1082 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1083 goto resource_error;
1085 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1086 bp->max_vnics < eth_dev->data->nb_rx_queues)
1087 goto resource_error;
1089 bp->rx_cp_nr_rings = bp->rx_nr_rings;
1090 bp->tx_cp_nr_rings = bp->tx_nr_rings;
1092 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1093 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1094 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1096 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1097 eth_dev->data->mtu =
1098 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1099 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1101 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1107 "Insufficient resources to support requested config\n");
1109 "Num Queues Requested: Tx %d, Rx %d\n",
1110 eth_dev->data->nb_tx_queues,
1111 eth_dev->data->nb_rx_queues);
1113 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1114 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1115 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1119 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1121 struct rte_eth_link *link = ð_dev->data->dev_link;
1123 if (link->link_status)
1124 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1125 eth_dev->data->port_id,
1126 (uint32_t)link->link_speed,
1127 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1128 ("full-duplex") : ("half-duplex\n"));
1130 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1131 eth_dev->data->port_id);
1135 * Determine whether the current configuration requires support for scattered
1136 * receive; return 1 if scattered receive is required and 0 if not.
1138 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1143 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1146 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1147 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1149 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1150 RTE_PKTMBUF_HEADROOM);
1151 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1157 static eth_rx_burst_t
1158 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1160 struct bnxt *bp = eth_dev->data->dev_private;
1162 /* Disable vector mode RX for Stingray2 for now */
1163 if (BNXT_CHIP_SR2(bp)) {
1164 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1165 return bnxt_recv_pkts;
1168 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1169 #ifndef RTE_LIBRTE_IEEE1588
1171 * Vector mode receive can be enabled only if scatter rx is not
1172 * in use and rx offloads are limited to VLAN stripping and
1175 if (!eth_dev->data->scattered_rx &&
1176 !(eth_dev->data->dev_conf.rxmode.offloads &
1177 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1178 DEV_RX_OFFLOAD_KEEP_CRC |
1179 DEV_RX_OFFLOAD_JUMBO_FRAME |
1180 DEV_RX_OFFLOAD_IPV4_CKSUM |
1181 DEV_RX_OFFLOAD_UDP_CKSUM |
1182 DEV_RX_OFFLOAD_TCP_CKSUM |
1183 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1184 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1185 DEV_RX_OFFLOAD_RSS_HASH |
1186 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1187 !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp) &&
1188 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1189 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1190 eth_dev->data->port_id);
1191 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1192 return bnxt_recv_pkts_vec;
1194 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1195 eth_dev->data->port_id);
1197 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1198 eth_dev->data->port_id,
1199 eth_dev->data->scattered_rx,
1200 eth_dev->data->dev_conf.rxmode.offloads);
1203 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1204 return bnxt_recv_pkts;
1207 static eth_tx_burst_t
1208 bnxt_transmit_function(struct rte_eth_dev *eth_dev)
1210 struct bnxt *bp = eth_dev->data->dev_private;
1212 /* Disable vector mode TX for Stingray2 for now */
1213 if (BNXT_CHIP_SR2(bp))
1214 return bnxt_xmit_pkts;
1216 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1217 #ifndef RTE_LIBRTE_IEEE1588
1218 uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1221 * Vector mode transmit can be enabled only if not using scatter rx
1224 if (!eth_dev->data->scattered_rx &&
1225 !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
1226 !BNXT_TRUFLOW_EN(bp) &&
1227 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1228 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1229 eth_dev->data->port_id);
1230 return bnxt_xmit_pkts_vec;
1232 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1233 eth_dev->data->port_id);
1235 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1236 eth_dev->data->port_id,
1237 eth_dev->data->scattered_rx,
1241 return bnxt_xmit_pkts;
1244 static int bnxt_handle_if_change_status(struct bnxt *bp)
1248 /* Since fw has undergone a reset and lost all contexts,
1249 * set fatal flag to not issue hwrm during cleanup
1251 bp->flags |= BNXT_FLAG_FATAL_ERROR;
1252 bnxt_uninit_resources(bp, true);
1254 /* clear fatal flag so that re-init happens */
1255 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1256 rc = bnxt_init_resources(bp, true);
1258 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1263 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1265 struct bnxt *bp = eth_dev->data->dev_private;
1266 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1268 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1270 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1271 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1275 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1277 "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1278 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1281 rc = bnxt_hwrm_if_change(bp, true);
1282 if (rc == 0 || rc != -EAGAIN)
1285 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1286 } while (retry_cnt--);
1291 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1292 rc = bnxt_handle_if_change_status(bp);
1297 bnxt_enable_int(bp);
1299 rc = bnxt_init_chip(bp);
1303 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1304 eth_dev->data->dev_started = 1;
1306 bnxt_link_update_op(eth_dev, 1);
1308 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1309 vlan_mask |= ETH_VLAN_FILTER_MASK;
1310 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1311 vlan_mask |= ETH_VLAN_STRIP_MASK;
1312 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1316 /* Initialize bnxt ULP port details */
1317 rc = bnxt_ulp_port_init(bp);
1321 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1322 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1324 bnxt_schedule_fw_health_check(bp);
1329 bnxt_shutdown_nic(bp);
1330 bnxt_free_tx_mbufs(bp);
1331 bnxt_free_rx_mbufs(bp);
1332 bnxt_hwrm_if_change(bp, false);
1333 eth_dev->data->dev_started = 0;
1337 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1339 struct bnxt *bp = eth_dev->data->dev_private;
1342 if (!bp->link_info->link_up)
1343 rc = bnxt_set_hwrm_link_config(bp, true);
1345 eth_dev->data->dev_link.link_status = 1;
1347 bnxt_print_link_info(eth_dev);
1351 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1353 struct bnxt *bp = eth_dev->data->dev_private;
1355 eth_dev->data->dev_link.link_status = 0;
1356 bnxt_set_hwrm_link_config(bp, false);
1357 bp->link_info->link_up = 0;
1362 static void bnxt_free_switch_domain(struct bnxt *bp)
1366 if (bp->switch_domain_id) {
1367 rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1369 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1370 bp->switch_domain_id, rc);
1374 /* Unload the driver, release resources */
1375 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1377 struct bnxt *bp = eth_dev->data->dev_private;
1378 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1379 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1380 struct rte_eth_link link;
1383 eth_dev->data->dev_started = 0;
1384 eth_dev->data->scattered_rx = 0;
1386 /* Prevent crashes when queues are still in use */
1387 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1388 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1390 bnxt_disable_int(bp);
1392 /* disable uio/vfio intr/eventfd mapping */
1393 rte_intr_disable(intr_handle);
1395 /* Stop the child representors for this device */
1396 ret = bnxt_rep_stop_all(bp);
1400 /* delete the bnxt ULP port details */
1401 bnxt_ulp_port_deinit(bp);
1403 bnxt_cancel_fw_health_check(bp);
1405 /* Do not bring link down during reset recovery */
1406 if (!is_bnxt_in_error(bp)) {
1407 bnxt_dev_set_link_down_op(eth_dev);
1408 /* Wait for link to be reset */
1409 if (BNXT_SINGLE_PF(bp))
1411 /* clear the recorded link status */
1412 memset(&link, 0, sizeof(link));
1413 rte_eth_linkstatus_set(eth_dev, &link);
1416 /* Clean queue intr-vector mapping */
1417 rte_intr_efd_disable(intr_handle);
1418 if (intr_handle->intr_vec != NULL) {
1419 rte_free(intr_handle->intr_vec);
1420 intr_handle->intr_vec = NULL;
1423 bnxt_hwrm_port_clr_stats(bp);
1424 bnxt_free_tx_mbufs(bp);
1425 bnxt_free_rx_mbufs(bp);
1426 /* Process any remaining notifications in default completion queue */
1427 bnxt_int_handler(eth_dev);
1428 bnxt_shutdown_nic(bp);
1429 bnxt_hwrm_if_change(bp, false);
1431 rte_free(bp->mark_table);
1432 bp->mark_table = NULL;
1434 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1435 bp->rx_cosq_cnt = 0;
1436 /* All filters are deleted on a port stop. */
1437 if (BNXT_FLOW_XSTATS_EN(bp))
1438 bp->flow_stat->flow_count = 0;
1443 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1445 struct bnxt *bp = eth_dev->data->dev_private;
1448 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1451 /* cancel the recovery handler before remove dev */
1452 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1453 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1454 bnxt_cancel_fc_thread(bp);
1456 if (eth_dev->data->dev_started)
1457 ret = bnxt_dev_stop_op(eth_dev);
1459 bnxt_free_switch_domain(bp);
1461 bnxt_uninit_resources(bp, false);
1463 bnxt_free_leds_info(bp);
1464 bnxt_free_cos_queues(bp);
1465 bnxt_free_link_info(bp);
1466 bnxt_free_pf_info(bp);
1467 bnxt_free_parent_info(bp);
1469 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1470 bp->tx_mem_zone = NULL;
1471 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1472 bp->rx_mem_zone = NULL;
1474 bnxt_hwrm_free_vf_info(bp);
1476 rte_free(bp->grp_info);
1477 bp->grp_info = NULL;
1482 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1485 struct bnxt *bp = eth_dev->data->dev_private;
1486 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1487 struct bnxt_vnic_info *vnic;
1488 struct bnxt_filter_info *filter, *temp_filter;
1491 if (is_bnxt_in_error(bp))
1495 * Loop through all VNICs from the specified filter flow pools to
1496 * remove the corresponding MAC addr filter
1498 for (i = 0; i < bp->nr_vnics; i++) {
1499 if (!(pool_mask & (1ULL << i)))
1502 vnic = &bp->vnic_info[i];
1503 filter = STAILQ_FIRST(&vnic->filter);
1505 temp_filter = STAILQ_NEXT(filter, next);
1506 if (filter->mac_index == index) {
1507 STAILQ_REMOVE(&vnic->filter, filter,
1508 bnxt_filter_info, next);
1509 bnxt_hwrm_clear_l2_filter(bp, filter);
1510 bnxt_free_filter(bp, filter);
1512 filter = temp_filter;
1517 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1518 struct rte_ether_addr *mac_addr, uint32_t index,
1521 struct bnxt_filter_info *filter;
1524 /* Attach requested MAC address to the new l2_filter */
1525 STAILQ_FOREACH(filter, &vnic->filter, next) {
1526 if (filter->mac_index == index) {
1528 "MAC addr already existed for pool %d\n",
1534 filter = bnxt_alloc_filter(bp);
1536 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1540 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1541 * if the MAC that's been programmed now is a different one, then,
1542 * copy that addr to filter->l2_addr
1545 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1546 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1548 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1550 filter->mac_index = index;
1551 if (filter->mac_index == 0)
1552 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1554 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1556 bnxt_free_filter(bp, filter);
1562 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1563 struct rte_ether_addr *mac_addr,
1564 uint32_t index, uint32_t pool)
1566 struct bnxt *bp = eth_dev->data->dev_private;
1567 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1570 rc = is_bnxt_in_error(bp);
1574 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1575 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1580 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1584 /* Filter settings will get applied when port is started */
1585 if (!eth_dev->data->dev_started)
1588 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1593 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1596 struct bnxt *bp = eth_dev->data->dev_private;
1597 struct rte_eth_link new;
1598 int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1599 BNXT_MIN_LINK_WAIT_CNT;
1601 rc = is_bnxt_in_error(bp);
1605 memset(&new, 0, sizeof(new));
1607 /* Retrieve link info from hardware */
1608 rc = bnxt_get_hwrm_link_config(bp, &new);
1610 new.link_speed = ETH_LINK_SPEED_100M;
1611 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1613 "Failed to retrieve link rc = 0x%x!\n", rc);
1617 if (!wait_to_complete || new.link_status)
1620 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1623 /* Only single function PF can bring phy down.
1624 * When port is stopped, report link down for VF/MH/NPAR functions.
1626 if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1627 memset(&new, 0, sizeof(new));
1630 /* Timed out or success */
1631 if (new.link_status != eth_dev->data->dev_link.link_status ||
1632 new.link_speed != eth_dev->data->dev_link.link_speed) {
1633 rte_eth_linkstatus_set(eth_dev, &new);
1635 rte_eth_dev_callback_process(eth_dev,
1636 RTE_ETH_EVENT_INTR_LSC,
1639 bnxt_print_link_info(eth_dev);
1645 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1647 struct bnxt *bp = eth_dev->data->dev_private;
1648 struct bnxt_vnic_info *vnic;
1652 rc = is_bnxt_in_error(bp);
1656 /* Filter settings will get applied when port is started */
1657 if (!eth_dev->data->dev_started)
1660 if (bp->vnic_info == NULL)
1663 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1665 old_flags = vnic->flags;
1666 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1667 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1669 vnic->flags = old_flags;
1674 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1676 struct bnxt *bp = eth_dev->data->dev_private;
1677 struct bnxt_vnic_info *vnic;
1681 rc = is_bnxt_in_error(bp);
1685 /* Filter settings will get applied when port is started */
1686 if (!eth_dev->data->dev_started)
1689 if (bp->vnic_info == NULL)
1692 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1694 old_flags = vnic->flags;
1695 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1696 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1698 vnic->flags = old_flags;
1703 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1705 struct bnxt *bp = eth_dev->data->dev_private;
1706 struct bnxt_vnic_info *vnic;
1710 rc = is_bnxt_in_error(bp);
1714 /* Filter settings will get applied when port is started */
1715 if (!eth_dev->data->dev_started)
1718 if (bp->vnic_info == NULL)
1721 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1723 old_flags = vnic->flags;
1724 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1725 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1727 vnic->flags = old_flags;
1732 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1734 struct bnxt *bp = eth_dev->data->dev_private;
1735 struct bnxt_vnic_info *vnic;
1739 rc = is_bnxt_in_error(bp);
1743 /* Filter settings will get applied when port is started */
1744 if (!eth_dev->data->dev_started)
1747 if (bp->vnic_info == NULL)
1750 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1752 old_flags = vnic->flags;
1753 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1754 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1756 vnic->flags = old_flags;
1761 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1762 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1764 if (qid >= bp->rx_nr_rings)
1767 return bp->eth_dev->data->rx_queues[qid];
1770 /* Return rxq corresponding to a given rss table ring/group ID. */
1771 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1773 struct bnxt_rx_queue *rxq;
1776 if (!BNXT_HAS_RING_GRPS(bp)) {
1777 for (i = 0; i < bp->rx_nr_rings; i++) {
1778 rxq = bp->eth_dev->data->rx_queues[i];
1779 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1783 for (i = 0; i < bp->rx_nr_rings; i++) {
1784 if (bp->grp_info[i].fw_grp_id == fwr)
1789 return INVALID_HW_RING_ID;
1792 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1793 struct rte_eth_rss_reta_entry64 *reta_conf,
1796 struct bnxt *bp = eth_dev->data->dev_private;
1797 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1798 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1799 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1803 rc = is_bnxt_in_error(bp);
1807 if (!vnic->rss_table)
1810 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1813 if (reta_size != tbl_size) {
1814 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1815 "(%d) must equal the size supported by the hardware "
1816 "(%d)\n", reta_size, tbl_size);
1820 for (i = 0; i < reta_size; i++) {
1821 struct bnxt_rx_queue *rxq;
1823 idx = i / RTE_RETA_GROUP_SIZE;
1824 sft = i % RTE_RETA_GROUP_SIZE;
1826 if (!(reta_conf[idx].mask & (1ULL << sft)))
1829 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1831 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1835 if (BNXT_CHIP_P5(bp)) {
1836 vnic->rss_table[i * 2] =
1837 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1838 vnic->rss_table[i * 2 + 1] =
1839 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1841 vnic->rss_table[i] =
1842 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1846 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1850 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1851 struct rte_eth_rss_reta_entry64 *reta_conf,
1854 struct bnxt *bp = eth_dev->data->dev_private;
1855 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1856 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1857 uint16_t idx, sft, i;
1860 rc = is_bnxt_in_error(bp);
1864 /* Retrieve from the default VNIC */
1867 if (!vnic->rss_table)
1870 if (reta_size != tbl_size) {
1871 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1872 "(%d) must equal the size supported by the hardware "
1873 "(%d)\n", reta_size, tbl_size);
1877 for (idx = 0, i = 0; i < reta_size; i++) {
1878 idx = i / RTE_RETA_GROUP_SIZE;
1879 sft = i % RTE_RETA_GROUP_SIZE;
1881 if (reta_conf[idx].mask & (1ULL << sft)) {
1884 if (BNXT_CHIP_P5(bp))
1885 qid = bnxt_rss_to_qid(bp,
1886 vnic->rss_table[i * 2]);
1888 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1890 if (qid == INVALID_HW_RING_ID) {
1891 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1894 reta_conf[idx].reta[sft] = qid;
1901 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1902 struct rte_eth_rss_conf *rss_conf)
1904 struct bnxt *bp = eth_dev->data->dev_private;
1905 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1906 struct bnxt_vnic_info *vnic;
1909 rc = is_bnxt_in_error(bp);
1914 * If RSS enablement were different than dev_configure,
1915 * then return -EINVAL
1917 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1918 if (!rss_conf->rss_hf)
1919 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1921 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1925 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1926 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf,
1930 /* Update the default RSS VNIC(s) */
1931 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1932 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1934 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
1935 ETH_RSS_LEVEL(rss_conf->rss_hf));
1938 * If hashkey is not specified, use the previously configured
1941 if (!rss_conf->rss_key)
1944 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1946 "Invalid hashkey length, should be 16 bytes\n");
1949 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1952 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1956 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1957 struct rte_eth_rss_conf *rss_conf)
1959 struct bnxt *bp = eth_dev->data->dev_private;
1960 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1962 uint32_t hash_types;
1964 rc = is_bnxt_in_error(bp);
1968 /* RSS configuration is the same for all VNICs */
1969 if (vnic && vnic->rss_hash_key) {
1970 if (rss_conf->rss_key) {
1971 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1972 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1973 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1976 hash_types = vnic->hash_type;
1977 rss_conf->rss_hf = 0;
1978 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1979 rss_conf->rss_hf |= ETH_RSS_IPV4;
1980 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1982 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1983 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1985 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1987 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1988 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1990 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1992 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1993 rss_conf->rss_hf |= ETH_RSS_IPV6;
1994 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1996 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1997 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1999 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
2001 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
2002 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2004 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2008 bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2012 "Unknown RSS config from firmware (%08x), RSS disabled",
2017 rss_conf->rss_hf = 0;
2022 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2023 struct rte_eth_fc_conf *fc_conf)
2025 struct bnxt *bp = dev->data->dev_private;
2026 struct rte_eth_link link_info;
2029 rc = is_bnxt_in_error(bp);
2033 rc = bnxt_get_hwrm_link_config(bp, &link_info);
2037 memset(fc_conf, 0, sizeof(*fc_conf));
2038 if (bp->link_info->auto_pause)
2039 fc_conf->autoneg = 1;
2040 switch (bp->link_info->pause) {
2042 fc_conf->mode = RTE_FC_NONE;
2044 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2045 fc_conf->mode = RTE_FC_TX_PAUSE;
2047 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2048 fc_conf->mode = RTE_FC_RX_PAUSE;
2050 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2051 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2052 fc_conf->mode = RTE_FC_FULL;
2058 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2059 struct rte_eth_fc_conf *fc_conf)
2061 struct bnxt *bp = dev->data->dev_private;
2064 rc = is_bnxt_in_error(bp);
2068 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2069 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2073 switch (fc_conf->mode) {
2075 bp->link_info->auto_pause = 0;
2076 bp->link_info->force_pause = 0;
2078 case RTE_FC_RX_PAUSE:
2079 if (fc_conf->autoneg) {
2080 bp->link_info->auto_pause =
2081 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2082 bp->link_info->force_pause = 0;
2084 bp->link_info->auto_pause = 0;
2085 bp->link_info->force_pause =
2086 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2089 case RTE_FC_TX_PAUSE:
2090 if (fc_conf->autoneg) {
2091 bp->link_info->auto_pause =
2092 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2093 bp->link_info->force_pause = 0;
2095 bp->link_info->auto_pause = 0;
2096 bp->link_info->force_pause =
2097 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2101 if (fc_conf->autoneg) {
2102 bp->link_info->auto_pause =
2103 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2104 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2105 bp->link_info->force_pause = 0;
2107 bp->link_info->auto_pause = 0;
2108 bp->link_info->force_pause =
2109 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2110 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2114 return bnxt_set_hwrm_link_config(bp, true);
2117 /* Add UDP tunneling port */
2119 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2120 struct rte_eth_udp_tunnel *udp_tunnel)
2122 struct bnxt *bp = eth_dev->data->dev_private;
2123 uint16_t tunnel_type = 0;
2126 rc = is_bnxt_in_error(bp);
2130 switch (udp_tunnel->prot_type) {
2131 case RTE_TUNNEL_TYPE_VXLAN:
2132 if (bp->vxlan_port_cnt) {
2133 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2134 udp_tunnel->udp_port);
2135 if (bp->vxlan_port != udp_tunnel->udp_port) {
2136 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2139 bp->vxlan_port_cnt++;
2143 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2144 bp->vxlan_port_cnt++;
2146 case RTE_TUNNEL_TYPE_GENEVE:
2147 if (bp->geneve_port_cnt) {
2148 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2149 udp_tunnel->udp_port);
2150 if (bp->geneve_port != udp_tunnel->udp_port) {
2151 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2154 bp->geneve_port_cnt++;
2158 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2159 bp->geneve_port_cnt++;
2162 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2165 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2171 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2172 struct rte_eth_udp_tunnel *udp_tunnel)
2174 struct bnxt *bp = eth_dev->data->dev_private;
2175 uint16_t tunnel_type = 0;
2179 rc = is_bnxt_in_error(bp);
2183 switch (udp_tunnel->prot_type) {
2184 case RTE_TUNNEL_TYPE_VXLAN:
2185 if (!bp->vxlan_port_cnt) {
2186 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2189 if (bp->vxlan_port != udp_tunnel->udp_port) {
2190 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2191 udp_tunnel->udp_port, bp->vxlan_port);
2194 if (--bp->vxlan_port_cnt)
2198 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2199 port = bp->vxlan_fw_dst_port_id;
2201 case RTE_TUNNEL_TYPE_GENEVE:
2202 if (!bp->geneve_port_cnt) {
2203 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2206 if (bp->geneve_port != udp_tunnel->udp_port) {
2207 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2208 udp_tunnel->udp_port, bp->geneve_port);
2211 if (--bp->geneve_port_cnt)
2215 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2216 port = bp->geneve_fw_dst_port_id;
2219 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2223 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2227 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2229 struct bnxt_filter_info *filter;
2230 struct bnxt_vnic_info *vnic;
2232 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2234 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2235 filter = STAILQ_FIRST(&vnic->filter);
2237 /* Search for this matching MAC+VLAN filter */
2238 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2239 /* Delete the filter */
2240 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2243 STAILQ_REMOVE(&vnic->filter, filter,
2244 bnxt_filter_info, next);
2245 bnxt_free_filter(bp, filter);
2247 "Deleted vlan filter for %d\n",
2251 filter = STAILQ_NEXT(filter, next);
2256 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2258 struct bnxt_filter_info *filter;
2259 struct bnxt_vnic_info *vnic;
2261 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2262 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2263 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2265 /* Implementation notes on the use of VNIC in this command:
2267 * By default, these filters belong to default vnic for the function.
2268 * Once these filters are set up, only destination VNIC can be modified.
2269 * If the destination VNIC is not specified in this command,
2270 * then the HWRM shall only create an l2 context id.
2273 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2274 filter = STAILQ_FIRST(&vnic->filter);
2275 /* Check if the VLAN has already been added */
2277 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2280 filter = STAILQ_NEXT(filter, next);
2283 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2284 * command to create MAC+VLAN filter with the right flags, enables set.
2286 filter = bnxt_alloc_filter(bp);
2289 "MAC/VLAN filter alloc failed\n");
2292 /* MAC + VLAN ID filter */
2293 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2294 * untagged packets are received
2296 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2297 * packets and only the programmed vlan's packets are received
2299 filter->l2_ivlan = vlan_id;
2300 filter->l2_ivlan_mask = 0x0FFF;
2301 filter->enables |= en;
2302 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2304 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2306 /* Free the newly allocated filter as we were
2307 * not able to create the filter in hardware.
2309 bnxt_free_filter(bp, filter);
2313 filter->mac_index = 0;
2314 /* Add this new filter to the list */
2316 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2318 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2321 "Added Vlan filter for %d\n", vlan_id);
2325 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2326 uint16_t vlan_id, int on)
2328 struct bnxt *bp = eth_dev->data->dev_private;
2331 rc = is_bnxt_in_error(bp);
2335 if (!eth_dev->data->dev_started) {
2336 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2340 /* These operations apply to ALL existing MAC/VLAN filters */
2342 return bnxt_add_vlan_filter(bp, vlan_id);
2344 return bnxt_del_vlan_filter(bp, vlan_id);
2347 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2348 struct bnxt_vnic_info *vnic)
2350 struct bnxt_filter_info *filter;
2353 filter = STAILQ_FIRST(&vnic->filter);
2355 if (filter->mac_index == 0 &&
2356 !memcmp(filter->l2_addr, bp->mac_addr,
2357 RTE_ETHER_ADDR_LEN)) {
2358 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2360 STAILQ_REMOVE(&vnic->filter, filter,
2361 bnxt_filter_info, next);
2362 bnxt_free_filter(bp, filter);
2366 filter = STAILQ_NEXT(filter, next);
2372 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2374 struct bnxt_vnic_info *vnic;
2378 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2379 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2380 /* Remove any VLAN filters programmed */
2381 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2382 bnxt_del_vlan_filter(bp, i);
2384 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2388 /* Default filter will allow packets that match the
2389 * dest mac. So, it has to be deleted, otherwise, we
2390 * will endup receiving vlan packets for which the
2391 * filter is not programmed, when hw-vlan-filter
2392 * configuration is ON
2394 bnxt_del_dflt_mac_filter(bp, vnic);
2395 /* This filter will allow only untagged packets */
2396 bnxt_add_vlan_filter(bp, 0);
2398 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2399 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2404 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2406 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2410 /* Destroy vnic filters and vnic */
2411 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2412 DEV_RX_OFFLOAD_VLAN_FILTER) {
2413 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2414 bnxt_del_vlan_filter(bp, i);
2416 bnxt_del_dflt_mac_filter(bp, vnic);
2418 rc = bnxt_hwrm_vnic_free(bp, vnic);
2422 rte_free(vnic->fw_grp_ids);
2423 vnic->fw_grp_ids = NULL;
2425 vnic->rx_queue_cnt = 0;
2431 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2433 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2436 /* Destroy, recreate and reconfigure the default vnic */
2437 rc = bnxt_free_one_vnic(bp, 0);
2441 /* default vnic 0 */
2442 rc = bnxt_setup_one_vnic(bp, 0);
2446 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2447 DEV_RX_OFFLOAD_VLAN_FILTER) {
2448 rc = bnxt_add_vlan_filter(bp, 0);
2451 rc = bnxt_restore_vlan_filters(bp);
2455 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2460 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2464 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2465 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2471 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2473 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2474 struct bnxt *bp = dev->data->dev_private;
2477 rc = is_bnxt_in_error(bp);
2481 /* Filter settings will get applied when port is started */
2482 if (!dev->data->dev_started)
2485 if (mask & ETH_VLAN_FILTER_MASK) {
2486 /* Enable or disable VLAN filtering */
2487 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2492 if (mask & ETH_VLAN_STRIP_MASK) {
2493 /* Enable or disable VLAN stripping */
2494 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2499 if (mask & ETH_VLAN_EXTEND_MASK) {
2500 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2501 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2503 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2510 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2513 struct bnxt *bp = dev->data->dev_private;
2514 int qinq = dev->data->dev_conf.rxmode.offloads &
2515 DEV_RX_OFFLOAD_VLAN_EXTEND;
2517 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2518 vlan_type != ETH_VLAN_TYPE_OUTER) {
2520 "Unsupported vlan type.");
2525 "QinQ not enabled. Needs to be ON as we can "
2526 "accelerate only outer vlan\n");
2530 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2532 case RTE_ETHER_TYPE_QINQ:
2534 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2536 case RTE_ETHER_TYPE_VLAN:
2538 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2540 case RTE_ETHER_TYPE_QINQ1:
2542 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2544 case RTE_ETHER_TYPE_QINQ2:
2546 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2548 case RTE_ETHER_TYPE_QINQ3:
2550 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2553 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2556 bp->outer_tpid_bd |= tpid;
2557 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2558 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2560 "Can accelerate only outer vlan in QinQ\n");
2568 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2569 struct rte_ether_addr *addr)
2571 struct bnxt *bp = dev->data->dev_private;
2572 /* Default Filter is tied to VNIC 0 */
2573 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2576 rc = is_bnxt_in_error(bp);
2580 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2583 if (rte_is_zero_ether_addr(addr))
2586 /* Filter settings will get applied when port is started */
2587 if (!dev->data->dev_started)
2590 /* Check if the requested MAC is already added */
2591 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2594 /* Destroy filter and re-create it */
2595 bnxt_del_dflt_mac_filter(bp, vnic);
2597 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2598 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2599 /* This filter will allow only untagged packets */
2600 rc = bnxt_add_vlan_filter(bp, 0);
2602 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2605 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2610 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2611 struct rte_ether_addr *mc_addr_set,
2612 uint32_t nb_mc_addr)
2614 struct bnxt *bp = eth_dev->data->dev_private;
2615 char *mc_addr_list = (char *)mc_addr_set;
2616 struct bnxt_vnic_info *vnic;
2617 uint32_t off = 0, i = 0;
2620 rc = is_bnxt_in_error(bp);
2624 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2626 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2627 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2631 /* TODO Check for Duplicate mcast addresses */
2632 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2633 for (i = 0; i < nb_mc_addr; i++) {
2634 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2635 RTE_ETHER_ADDR_LEN);
2636 off += RTE_ETHER_ADDR_LEN;
2639 vnic->mc_addr_cnt = i;
2640 if (vnic->mc_addr_cnt)
2641 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2643 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2646 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2650 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2652 struct bnxt *bp = dev->data->dev_private;
2653 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2654 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2655 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2656 uint8_t fw_rsvd = bp->fw_ver & 0xff;
2659 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2660 fw_major, fw_minor, fw_updt, fw_rsvd);
2662 ret += 1; /* add the size of '\0' */
2663 if (fw_size < (uint32_t)ret)
2670 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2671 struct rte_eth_rxq_info *qinfo)
2673 struct bnxt *bp = dev->data->dev_private;
2674 struct bnxt_rx_queue *rxq;
2676 if (is_bnxt_in_error(bp))
2679 rxq = dev->data->rx_queues[queue_id];
2681 qinfo->mp = rxq->mb_pool;
2682 qinfo->scattered_rx = dev->data->scattered_rx;
2683 qinfo->nb_desc = rxq->nb_rx_desc;
2685 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2686 qinfo->conf.rx_drop_en = rxq->drop_en;
2687 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2688 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2692 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2693 struct rte_eth_txq_info *qinfo)
2695 struct bnxt *bp = dev->data->dev_private;
2696 struct bnxt_tx_queue *txq;
2698 if (is_bnxt_in_error(bp))
2701 txq = dev->data->tx_queues[queue_id];
2703 qinfo->nb_desc = txq->nb_tx_desc;
2705 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2706 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2707 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2709 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2710 qinfo->conf.tx_rs_thresh = 0;
2711 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2712 qinfo->conf.offloads = txq->offloads;
2715 static const struct {
2716 eth_rx_burst_t pkt_burst;
2718 } bnxt_rx_burst_info[] = {
2719 {bnxt_recv_pkts, "Scalar"},
2720 #if defined(RTE_ARCH_X86)
2721 {bnxt_recv_pkts_vec, "Vector SSE"},
2722 #elif defined(RTE_ARCH_ARM64)
2723 {bnxt_recv_pkts_vec, "Vector Neon"},
2728 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2729 struct rte_eth_burst_mode *mode)
2731 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2734 for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2735 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2736 snprintf(mode->info, sizeof(mode->info), "%s",
2737 bnxt_rx_burst_info[i].info);
2745 static const struct {
2746 eth_tx_burst_t pkt_burst;
2748 } bnxt_tx_burst_info[] = {
2749 {bnxt_xmit_pkts, "Scalar"},
2750 #if defined(RTE_ARCH_X86)
2751 {bnxt_xmit_pkts_vec, "Vector SSE"},
2752 #elif defined(RTE_ARCH_ARM64)
2753 {bnxt_xmit_pkts_vec, "Vector Neon"},
2758 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2759 struct rte_eth_burst_mode *mode)
2761 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2764 for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2765 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2766 snprintf(mode->info, sizeof(mode->info), "%s",
2767 bnxt_tx_burst_info[i].info);
2775 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2777 struct bnxt *bp = eth_dev->data->dev_private;
2778 uint32_t new_pkt_size;
2782 rc = is_bnxt_in_error(bp);
2786 /* Exit if receive queues are not configured yet */
2787 if (!eth_dev->data->nb_rx_queues)
2790 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2791 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2794 * Disallow any MTU change that would require scattered receive support
2795 * if it is not already enabled.
2797 if (eth_dev->data->dev_started &&
2798 !eth_dev->data->scattered_rx &&
2800 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2802 "MTU change would require scattered rx support. ");
2803 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2807 if (new_mtu > RTE_ETHER_MTU) {
2808 bp->flags |= BNXT_FLAG_JUMBO;
2809 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2810 DEV_RX_OFFLOAD_JUMBO_FRAME;
2812 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2813 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2814 bp->flags &= ~BNXT_FLAG_JUMBO;
2817 /* Is there a change in mtu setting? */
2818 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2821 for (i = 0; i < bp->nr_vnics; i++) {
2822 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2825 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2826 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2830 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2831 size -= RTE_PKTMBUF_HEADROOM;
2833 if (size < new_mtu) {
2834 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2841 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2843 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2849 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2851 struct bnxt *bp = dev->data->dev_private;
2852 uint16_t vlan = bp->vlan;
2855 rc = is_bnxt_in_error(bp);
2859 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2861 "PVID cannot be modified for this function\n");
2864 bp->vlan = on ? pvid : 0;
2866 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2873 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2875 struct bnxt *bp = dev->data->dev_private;
2878 rc = is_bnxt_in_error(bp);
2882 return bnxt_hwrm_port_led_cfg(bp, true);
2886 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2888 struct bnxt *bp = dev->data->dev_private;
2891 rc = is_bnxt_in_error(bp);
2895 return bnxt_hwrm_port_led_cfg(bp, false);
2899 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2901 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2902 uint32_t desc = 0, raw_cons = 0, cons;
2903 struct bnxt_cp_ring_info *cpr;
2904 struct bnxt_rx_queue *rxq;
2905 struct rx_pkt_cmpl *rxcmp;
2908 rc = is_bnxt_in_error(bp);
2912 rxq = dev->data->rx_queues[rx_queue_id];
2914 raw_cons = cpr->cp_raw_cons;
2917 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2918 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2919 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2921 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2933 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2935 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2936 struct bnxt_rx_ring_info *rxr;
2937 struct bnxt_cp_ring_info *cpr;
2938 struct rte_mbuf *rx_buf;
2939 struct rx_pkt_cmpl *rxcmp;
2940 uint32_t cons, cp_cons;
2946 rc = is_bnxt_in_error(rxq->bp);
2953 if (offset >= rxq->nb_rx_desc)
2956 cons = RING_CMP(cpr->cp_ring_struct, offset);
2957 cp_cons = cpr->cp_raw_cons;
2958 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2960 if (cons > cp_cons) {
2961 if (CMPL_VALID(rxcmp, cpr->valid))
2962 return RTE_ETH_RX_DESC_DONE;
2964 if (CMPL_VALID(rxcmp, !cpr->valid))
2965 return RTE_ETH_RX_DESC_DONE;
2967 rx_buf = rxr->rx_buf_ring[cons];
2968 if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf)
2969 return RTE_ETH_RX_DESC_UNAVAIL;
2972 return RTE_ETH_RX_DESC_AVAIL;
2976 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2978 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2979 struct bnxt_tx_ring_info *txr;
2980 struct bnxt_cp_ring_info *cpr;
2981 struct bnxt_sw_tx_bd *tx_buf;
2982 struct tx_pkt_cmpl *txcmp;
2983 uint32_t cons, cp_cons;
2989 rc = is_bnxt_in_error(txq->bp);
2996 if (offset >= txq->nb_tx_desc)
2999 cons = RING_CMP(cpr->cp_ring_struct, offset);
3000 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3001 cp_cons = cpr->cp_raw_cons;
3003 if (cons > cp_cons) {
3004 if (CMPL_VALID(txcmp, cpr->valid))
3005 return RTE_ETH_TX_DESC_UNAVAIL;
3007 if (CMPL_VALID(txcmp, !cpr->valid))
3008 return RTE_ETH_TX_DESC_UNAVAIL;
3010 tx_buf = &txr->tx_buf_ring[cons];
3011 if (tx_buf->mbuf == NULL)
3012 return RTE_ETH_TX_DESC_DONE;
3014 return RTE_ETH_TX_DESC_FULL;
3018 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3019 enum rte_filter_type filter_type,
3020 enum rte_filter_op filter_op, void *arg)
3022 struct bnxt *bp = dev->data->dev_private;
3028 if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3029 struct bnxt_representor *vfr = dev->data->dev_private;
3030 bp = vfr->parent_dev->data->dev_private;
3031 /* parent is deleted while children are still valid */
3033 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n",
3041 ret = is_bnxt_in_error(bp);
3045 switch (filter_type) {
3046 case RTE_ETH_FILTER_GENERIC:
3047 if (filter_op != RTE_ETH_FILTER_GET)
3050 /* PMD supports thread-safe flow operations. rte_flow API
3051 * functions can avoid mutex for multi-thread safety.
3053 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3055 if (BNXT_TRUFLOW_EN(bp))
3056 *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3058 *(const void **)arg = &bnxt_flow_ops;
3062 "Filter type (%d) not supported", filter_type);
3069 static const uint32_t *
3070 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3072 static const uint32_t ptypes[] = {
3073 RTE_PTYPE_L2_ETHER_VLAN,
3074 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3075 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3079 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3080 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3081 RTE_PTYPE_INNER_L4_ICMP,
3082 RTE_PTYPE_INNER_L4_TCP,
3083 RTE_PTYPE_INNER_L4_UDP,
3087 if (!dev->rx_pkt_burst)
3093 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3096 uint32_t reg_base = *reg_arr & 0xfffff000;
3100 for (i = 0; i < count; i++) {
3101 if ((reg_arr[i] & 0xfffff000) != reg_base)
3104 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3105 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3109 static int bnxt_map_ptp_regs(struct bnxt *bp)
3111 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3115 reg_arr = ptp->rx_regs;
3116 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3120 reg_arr = ptp->tx_regs;
3121 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3125 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3126 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3128 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3129 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3134 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3136 rte_write32(0, (uint8_t *)bp->bar0 +
3137 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3138 rte_write32(0, (uint8_t *)bp->bar0 +
3139 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3142 static uint64_t bnxt_cc_read(struct bnxt *bp)
3146 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3147 BNXT_GRCPF_REG_SYNC_TIME));
3148 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3149 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3153 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3155 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3158 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3159 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3160 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3163 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3164 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3165 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3166 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3167 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3168 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3173 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3175 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3176 struct bnxt_pf_info *pf = bp->pf;
3183 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3184 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3185 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3188 port_id = pf->port_id;
3189 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3190 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3192 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3193 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3194 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3195 /* bnxt_clr_rx_ts(bp); TBD */
3199 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3200 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3201 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3202 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3208 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3211 struct bnxt *bp = dev->data->dev_private;
3212 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3217 ns = rte_timespec_to_ns(ts);
3218 /* Set the timecounters to a new value. */
3225 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3227 struct bnxt *bp = dev->data->dev_private;
3228 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3229 uint64_t ns, systime_cycles = 0;
3235 if (BNXT_CHIP_P5(bp))
3236 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3239 systime_cycles = bnxt_cc_read(bp);
3241 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3242 *ts = rte_ns_to_timespec(ns);
3247 bnxt_timesync_enable(struct rte_eth_dev *dev)
3249 struct bnxt *bp = dev->data->dev_private;
3250 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3258 ptp->tx_tstamp_en = 1;
3259 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3261 rc = bnxt_hwrm_ptp_cfg(bp);
3265 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3266 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3267 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3269 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3270 ptp->tc.cc_shift = shift;
3271 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3273 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3274 ptp->rx_tstamp_tc.cc_shift = shift;
3275 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3277 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3278 ptp->tx_tstamp_tc.cc_shift = shift;
3279 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3281 if (!BNXT_CHIP_P5(bp))
3282 bnxt_map_ptp_regs(bp);
3288 bnxt_timesync_disable(struct rte_eth_dev *dev)
3290 struct bnxt *bp = dev->data->dev_private;
3291 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3297 ptp->tx_tstamp_en = 0;
3300 bnxt_hwrm_ptp_cfg(bp);
3302 if (!BNXT_CHIP_P5(bp))
3303 bnxt_unmap_ptp_regs(bp);
3309 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3310 struct timespec *timestamp,
3311 uint32_t flags __rte_unused)
3313 struct bnxt *bp = dev->data->dev_private;
3314 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3315 uint64_t rx_tstamp_cycles = 0;
3321 if (BNXT_CHIP_P5(bp))
3322 rx_tstamp_cycles = ptp->rx_timestamp;
3324 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3326 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3327 *timestamp = rte_ns_to_timespec(ns);
3332 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3333 struct timespec *timestamp)
3335 struct bnxt *bp = dev->data->dev_private;
3336 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3337 uint64_t tx_tstamp_cycles = 0;
3344 if (BNXT_CHIP_P5(bp))
3345 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3348 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3350 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3351 *timestamp = rte_ns_to_timespec(ns);
3357 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3359 struct bnxt *bp = dev->data->dev_private;
3360 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3365 ptp->tc.nsec += delta;
3371 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3373 struct bnxt *bp = dev->data->dev_private;
3375 uint32_t dir_entries;
3376 uint32_t entry_length;
3378 rc = is_bnxt_in_error(bp);
3382 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3383 bp->pdev->addr.domain, bp->pdev->addr.bus,
3384 bp->pdev->addr.devid, bp->pdev->addr.function);
3386 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3390 return dir_entries * entry_length;
3394 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3395 struct rte_dev_eeprom_info *in_eeprom)
3397 struct bnxt *bp = dev->data->dev_private;
3402 rc = is_bnxt_in_error(bp);
3406 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3407 bp->pdev->addr.domain, bp->pdev->addr.bus,
3408 bp->pdev->addr.devid, bp->pdev->addr.function,
3409 in_eeprom->offset, in_eeprom->length);
3411 if (in_eeprom->offset == 0) /* special offset value to get directory */
3412 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3415 index = in_eeprom->offset >> 24;
3416 offset = in_eeprom->offset & 0xffffff;
3419 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3420 in_eeprom->length, in_eeprom->data);
3425 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3428 case BNX_DIR_TYPE_CHIMP_PATCH:
3429 case BNX_DIR_TYPE_BOOTCODE:
3430 case BNX_DIR_TYPE_BOOTCODE_2:
3431 case BNX_DIR_TYPE_APE_FW:
3432 case BNX_DIR_TYPE_APE_PATCH:
3433 case BNX_DIR_TYPE_KONG_FW:
3434 case BNX_DIR_TYPE_KONG_PATCH:
3435 case BNX_DIR_TYPE_BONO_FW:
3436 case BNX_DIR_TYPE_BONO_PATCH:
3444 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3447 case BNX_DIR_TYPE_AVS:
3448 case BNX_DIR_TYPE_EXP_ROM_MBA:
3449 case BNX_DIR_TYPE_PCIE:
3450 case BNX_DIR_TYPE_TSCF_UCODE:
3451 case BNX_DIR_TYPE_EXT_PHY:
3452 case BNX_DIR_TYPE_CCM:
3453 case BNX_DIR_TYPE_ISCSI_BOOT:
3454 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3455 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3463 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3465 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3466 bnxt_dir_type_is_other_exec_format(dir_type);
3470 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3471 struct rte_dev_eeprom_info *in_eeprom)
3473 struct bnxt *bp = dev->data->dev_private;
3474 uint8_t index, dir_op;
3475 uint16_t type, ext, ordinal, attr;
3478 rc = is_bnxt_in_error(bp);
3482 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3483 bp->pdev->addr.domain, bp->pdev->addr.bus,
3484 bp->pdev->addr.devid, bp->pdev->addr.function,
3485 in_eeprom->offset, in_eeprom->length);
3488 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3492 type = in_eeprom->magic >> 16;
3494 if (type == 0xffff) { /* special value for directory operations */
3495 index = in_eeprom->magic & 0xff;
3496 dir_op = in_eeprom->magic >> 8;
3500 case 0x0e: /* erase */
3501 if (in_eeprom->offset != ~in_eeprom->magic)
3503 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3509 /* Create or re-write an NVM item: */
3510 if (bnxt_dir_type_is_executable(type) == true)
3512 ext = in_eeprom->magic & 0xffff;
3513 ordinal = in_eeprom->offset >> 16;
3514 attr = in_eeprom->offset & 0xffff;
3516 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3517 in_eeprom->data, in_eeprom->length);
3524 static const struct eth_dev_ops bnxt_dev_ops = {
3525 .dev_infos_get = bnxt_dev_info_get_op,
3526 .dev_close = bnxt_dev_close_op,
3527 .dev_configure = bnxt_dev_configure_op,
3528 .dev_start = bnxt_dev_start_op,
3529 .dev_stop = bnxt_dev_stop_op,
3530 .dev_set_link_up = bnxt_dev_set_link_up_op,
3531 .dev_set_link_down = bnxt_dev_set_link_down_op,
3532 .stats_get = bnxt_stats_get_op,
3533 .stats_reset = bnxt_stats_reset_op,
3534 .rx_queue_setup = bnxt_rx_queue_setup_op,
3535 .rx_queue_release = bnxt_rx_queue_release_op,
3536 .tx_queue_setup = bnxt_tx_queue_setup_op,
3537 .tx_queue_release = bnxt_tx_queue_release_op,
3538 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3539 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3540 .reta_update = bnxt_reta_update_op,
3541 .reta_query = bnxt_reta_query_op,
3542 .rss_hash_update = bnxt_rss_hash_update_op,
3543 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3544 .link_update = bnxt_link_update_op,
3545 .promiscuous_enable = bnxt_promiscuous_enable_op,
3546 .promiscuous_disable = bnxt_promiscuous_disable_op,
3547 .allmulticast_enable = bnxt_allmulticast_enable_op,
3548 .allmulticast_disable = bnxt_allmulticast_disable_op,
3549 .mac_addr_add = bnxt_mac_addr_add_op,
3550 .mac_addr_remove = bnxt_mac_addr_remove_op,
3551 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3552 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3553 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3554 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3555 .vlan_filter_set = bnxt_vlan_filter_set_op,
3556 .vlan_offload_set = bnxt_vlan_offload_set_op,
3557 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3558 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3559 .mtu_set = bnxt_mtu_set_op,
3560 .mac_addr_set = bnxt_set_default_mac_addr_op,
3561 .xstats_get = bnxt_dev_xstats_get_op,
3562 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3563 .xstats_reset = bnxt_dev_xstats_reset_op,
3564 .fw_version_get = bnxt_fw_version_get,
3565 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3566 .rxq_info_get = bnxt_rxq_info_get_op,
3567 .txq_info_get = bnxt_txq_info_get_op,
3568 .rx_burst_mode_get = bnxt_rx_burst_mode_get,
3569 .tx_burst_mode_get = bnxt_tx_burst_mode_get,
3570 .dev_led_on = bnxt_dev_led_on_op,
3571 .dev_led_off = bnxt_dev_led_off_op,
3572 .rx_queue_start = bnxt_rx_queue_start,
3573 .rx_queue_stop = bnxt_rx_queue_stop,
3574 .tx_queue_start = bnxt_tx_queue_start,
3575 .tx_queue_stop = bnxt_tx_queue_stop,
3576 .filter_ctrl = bnxt_filter_ctrl_op,
3577 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3578 .get_eeprom_length = bnxt_get_eeprom_length_op,
3579 .get_eeprom = bnxt_get_eeprom_op,
3580 .set_eeprom = bnxt_set_eeprom_op,
3581 .timesync_enable = bnxt_timesync_enable,
3582 .timesync_disable = bnxt_timesync_disable,
3583 .timesync_read_time = bnxt_timesync_read_time,
3584 .timesync_write_time = bnxt_timesync_write_time,
3585 .timesync_adjust_time = bnxt_timesync_adjust_time,
3586 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3587 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3590 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3594 /* Only pre-map the reset GRC registers using window 3 */
3595 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3596 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3598 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3603 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3605 struct bnxt_error_recovery_info *info = bp->recovery_info;
3606 uint32_t reg_base = 0xffffffff;
3609 /* Only pre-map the monitoring GRC registers using window 2 */
3610 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3611 uint32_t reg = info->status_regs[i];
3613 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3616 if (reg_base == 0xffffffff)
3617 reg_base = reg & 0xfffff000;
3618 if ((reg & 0xfffff000) != reg_base)
3621 /* Use mask 0xffc as the Lower 2 bits indicates
3622 * address space location
3624 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3628 if (reg_base == 0xffffffff)
3631 rte_write32(reg_base, (uint8_t *)bp->bar0 +
3632 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3637 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3639 struct bnxt_error_recovery_info *info = bp->recovery_info;
3640 uint32_t delay = info->delay_after_reset[index];
3641 uint32_t val = info->reset_reg_val[index];
3642 uint32_t reg = info->reset_reg[index];
3643 uint32_t type, offset;
3645 type = BNXT_FW_STATUS_REG_TYPE(reg);
3646 offset = BNXT_FW_STATUS_REG_OFF(reg);
3649 case BNXT_FW_STATUS_REG_TYPE_CFG:
3650 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3652 case BNXT_FW_STATUS_REG_TYPE_GRC:
3653 offset = bnxt_map_reset_regs(bp, offset);
3654 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3656 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3657 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3660 /* wait on a specific interval of time until core reset is complete */
3662 rte_delay_ms(delay);
3665 static void bnxt_dev_cleanup(struct bnxt *bp)
3667 bp->eth_dev->data->dev_link.link_status = 0;
3668 bp->link_info->link_up = 0;
3669 if (bp->eth_dev->data->dev_started)
3670 bnxt_dev_stop_op(bp->eth_dev);
3672 bnxt_uninit_resources(bp, true);
3675 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3677 struct rte_eth_dev *dev = bp->eth_dev;
3678 struct rte_vlan_filter_conf *vfc;
3682 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3683 vfc = &dev->data->vlan_filter_conf;
3684 vidx = vlan_id / 64;
3685 vbit = vlan_id % 64;
3687 /* Each bit corresponds to a VLAN id */
3688 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3689 rc = bnxt_add_vlan_filter(bp, vlan_id);
3698 static int bnxt_restore_mac_filters(struct bnxt *bp)
3700 struct rte_eth_dev *dev = bp->eth_dev;
3701 struct rte_eth_dev_info dev_info;
3702 struct rte_ether_addr *addr;
3708 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3711 rc = bnxt_dev_info_get_op(dev, &dev_info);
3715 /* replay MAC address configuration */
3716 for (i = 1; i < dev_info.max_mac_addrs; i++) {
3717 addr = &dev->data->mac_addrs[i];
3719 /* skip zero address */
3720 if (rte_is_zero_ether_addr(addr))
3724 pool_mask = dev->data->mac_pool_sel[i];
3727 if (pool_mask & 1ULL) {
3728 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3734 } while (pool_mask);
3740 static int bnxt_restore_filters(struct bnxt *bp)
3742 struct rte_eth_dev *dev = bp->eth_dev;
3745 if (dev->data->all_multicast) {
3746 ret = bnxt_allmulticast_enable_op(dev);
3750 if (dev->data->promiscuous) {
3751 ret = bnxt_promiscuous_enable_op(dev);
3756 ret = bnxt_restore_mac_filters(bp);
3760 ret = bnxt_restore_vlan_filters(bp);
3761 /* TODO restore other filters as well */
3765 static void bnxt_dev_recover(void *arg)
3767 struct bnxt *bp = arg;
3768 int timeout = bp->fw_reset_max_msecs;
3771 /* Clear Error flag so that device re-init should happen */
3772 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3775 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
3778 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3779 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3780 } while (rc && timeout);
3783 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3787 rc = bnxt_init_resources(bp, true);
3790 "Failed to initialize resources after reset\n");
3793 /* clear reset flag as the device is initialized now */
3794 bp->flags &= ~BNXT_FLAG_FW_RESET;
3796 rc = bnxt_dev_start_op(bp->eth_dev);
3798 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3802 rc = bnxt_restore_filters(bp);
3806 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3809 bnxt_dev_stop_op(bp->eth_dev);
3811 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3812 bnxt_uninit_resources(bp, false);
3813 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3816 void bnxt_dev_reset_and_resume(void *arg)
3818 struct bnxt *bp = arg;
3821 bnxt_dev_cleanup(bp);
3823 bnxt_wait_for_device_shutdown(bp);
3825 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3826 bnxt_dev_recover, (void *)bp);
3828 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3831 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3833 struct bnxt_error_recovery_info *info = bp->recovery_info;
3834 uint32_t reg = info->status_regs[index];
3835 uint32_t type, offset, val = 0;
3837 type = BNXT_FW_STATUS_REG_TYPE(reg);
3838 offset = BNXT_FW_STATUS_REG_OFF(reg);
3841 case BNXT_FW_STATUS_REG_TYPE_CFG:
3842 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3844 case BNXT_FW_STATUS_REG_TYPE_GRC:
3845 offset = info->mapped_status_regs[index];
3847 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3848 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3856 static int bnxt_fw_reset_all(struct bnxt *bp)
3858 struct bnxt_error_recovery_info *info = bp->recovery_info;
3862 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3863 /* Reset through master function driver */
3864 for (i = 0; i < info->reg_array_cnt; i++)
3865 bnxt_write_fw_reset_reg(bp, i);
3866 /* Wait for time specified by FW after triggering reset */
3867 rte_delay_ms(info->master_func_wait_period_after_reset);
3868 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3869 /* Reset with the help of Kong processor */
3870 rc = bnxt_hwrm_fw_reset(bp);
3872 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3878 static void bnxt_fw_reset_cb(void *arg)
3880 struct bnxt *bp = arg;
3881 struct bnxt_error_recovery_info *info = bp->recovery_info;
3884 /* Only Master function can do FW reset */
3885 if (bnxt_is_master_func(bp) &&
3886 bnxt_is_recovery_enabled(bp)) {
3887 rc = bnxt_fw_reset_all(bp);
3889 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3894 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3895 * EXCEPTION_FATAL_ASYNC event to all the functions
3896 * (including MASTER FUNC). After receiving this Async, all the active
3897 * drivers should treat this case as FW initiated recovery
3899 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3900 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3901 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3903 /* To recover from error */
3904 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3909 /* Driver should poll FW heartbeat, reset_counter with the frequency
3910 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3911 * When the driver detects heartbeat stop or change in reset_counter,
3912 * it has to trigger a reset to recover from the error condition.
3913 * A “master PF” is the function who will have the privilege to
3914 * initiate the chimp reset. The master PF will be elected by the
3915 * firmware and will be notified through async message.
3917 static void bnxt_check_fw_health(void *arg)
3919 struct bnxt *bp = arg;
3920 struct bnxt_error_recovery_info *info = bp->recovery_info;
3921 uint32_t val = 0, wait_msec;
3923 if (!info || !bnxt_is_recovery_enabled(bp) ||
3924 is_bnxt_in_error(bp))
3927 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3928 if (val == info->last_heart_beat)
3931 info->last_heart_beat = val;
3933 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3934 if (val != info->last_reset_counter)
3937 info->last_reset_counter = val;
3939 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3940 bnxt_check_fw_health, (void *)bp);
3944 /* Stop DMA to/from device */
3945 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3946 bp->flags |= BNXT_FLAG_FW_RESET;
3948 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
3950 if (bnxt_is_master_func(bp))
3951 wait_msec = info->master_func_wait_period;
3953 wait_msec = info->normal_func_wait_period;
3955 rte_eal_alarm_set(US_PER_MS * wait_msec,
3956 bnxt_fw_reset_cb, (void *)bp);
3959 void bnxt_schedule_fw_health_check(struct bnxt *bp)
3961 uint32_t polling_freq;
3963 pthread_mutex_lock(&bp->health_check_lock);
3965 if (!bnxt_is_recovery_enabled(bp))
3968 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
3971 polling_freq = bp->recovery_info->driver_polling_freq;
3973 rte_eal_alarm_set(US_PER_MS * polling_freq,
3974 bnxt_check_fw_health, (void *)bp);
3975 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3978 pthread_mutex_unlock(&bp->health_check_lock);
3981 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
3983 if (!bnxt_is_recovery_enabled(bp))
3986 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
3987 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3990 static bool bnxt_vf_pciid(uint16_t device_id)
3992 switch (device_id) {
3993 case BROADCOM_DEV_ID_57304_VF:
3994 case BROADCOM_DEV_ID_57406_VF:
3995 case BROADCOM_DEV_ID_5731X_VF:
3996 case BROADCOM_DEV_ID_5741X_VF:
3997 case BROADCOM_DEV_ID_57414_VF:
3998 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
3999 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4000 case BROADCOM_DEV_ID_58802_VF:
4001 case BROADCOM_DEV_ID_57500_VF1:
4002 case BROADCOM_DEV_ID_57500_VF2:
4003 case BROADCOM_DEV_ID_58818_VF:
4011 /* Phase 5 device */
4012 static bool bnxt_p5_device(uint16_t device_id)
4014 switch (device_id) {
4015 case BROADCOM_DEV_ID_57508:
4016 case BROADCOM_DEV_ID_57504:
4017 case BROADCOM_DEV_ID_57502:
4018 case BROADCOM_DEV_ID_57508_MF1:
4019 case BROADCOM_DEV_ID_57504_MF1:
4020 case BROADCOM_DEV_ID_57502_MF1:
4021 case BROADCOM_DEV_ID_57508_MF2:
4022 case BROADCOM_DEV_ID_57504_MF2:
4023 case BROADCOM_DEV_ID_57502_MF2:
4024 case BROADCOM_DEV_ID_57500_VF1:
4025 case BROADCOM_DEV_ID_57500_VF2:
4026 case BROADCOM_DEV_ID_58812:
4027 case BROADCOM_DEV_ID_58814:
4028 case BROADCOM_DEV_ID_58818:
4029 case BROADCOM_DEV_ID_58818_VF:
4037 bool bnxt_stratus_device(struct bnxt *bp)
4039 uint16_t device_id = bp->pdev->id.device_id;
4041 switch (device_id) {
4042 case BROADCOM_DEV_ID_STRATUS_NIC:
4043 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4044 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4052 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4054 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4055 struct bnxt *bp = eth_dev->data->dev_private;
4057 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4058 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4059 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4060 if (!bp->bar0 || !bp->doorbell_base) {
4061 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4065 bp->eth_dev = eth_dev;
4071 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4072 struct bnxt_ctx_pg_info *ctx_pg,
4077 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4078 const struct rte_memzone *mz = NULL;
4079 char mz_name[RTE_MEMZONE_NAMESIZE];
4080 rte_iova_t mz_phys_addr;
4081 uint64_t valid_bits = 0;
4088 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4090 rmem->page_size = BNXT_PAGE_SIZE;
4091 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4092 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4093 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4095 valid_bits = PTU_PTE_VALID;
4097 if (rmem->nr_pages > 1) {
4098 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4099 "bnxt_ctx_pg_tbl%s_%x_%d",
4100 suffix, idx, bp->eth_dev->data->port_id);
4101 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4102 mz = rte_memzone_lookup(mz_name);
4104 mz = rte_memzone_reserve_aligned(mz_name,
4108 RTE_MEMZONE_SIZE_HINT_ONLY |
4109 RTE_MEMZONE_IOVA_CONTIG,
4115 memset(mz->addr, 0, mz->len);
4116 mz_phys_addr = mz->iova;
4118 rmem->pg_tbl = mz->addr;
4119 rmem->pg_tbl_map = mz_phys_addr;
4120 rmem->pg_tbl_mz = mz;
4123 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4124 suffix, idx, bp->eth_dev->data->port_id);
4125 mz = rte_memzone_lookup(mz_name);
4127 mz = rte_memzone_reserve_aligned(mz_name,
4131 RTE_MEMZONE_SIZE_HINT_ONLY |
4132 RTE_MEMZONE_IOVA_CONTIG,
4138 memset(mz->addr, 0, mz->len);
4139 mz_phys_addr = mz->iova;
4141 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4142 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4143 rmem->dma_arr[i] = mz_phys_addr + sz;
4145 if (rmem->nr_pages > 1) {
4146 if (i == rmem->nr_pages - 2 &&
4147 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4148 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4149 else if (i == rmem->nr_pages - 1 &&
4150 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4151 valid_bits |= PTU_PTE_LAST;
4153 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4159 if (rmem->vmem_size)
4160 rmem->vmem = (void **)mz->addr;
4161 rmem->dma_arr[0] = mz_phys_addr;
4165 static void bnxt_free_ctx_mem(struct bnxt *bp)
4169 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4172 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4173 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4174 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4175 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4176 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4177 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4178 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4179 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4180 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4181 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4182 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4184 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4185 if (bp->ctx->tqm_mem[i])
4186 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4193 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4195 #define min_t(type, x, y) ({ \
4196 type __min1 = (x); \
4197 type __min2 = (y); \
4198 __min1 < __min2 ? __min1 : __min2; })
4200 #define max_t(type, x, y) ({ \
4201 type __max1 = (x); \
4202 type __max2 = (y); \
4203 __max1 > __max2 ? __max1 : __max2; })
4205 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4207 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4209 struct bnxt_ctx_pg_info *ctx_pg;
4210 struct bnxt_ctx_mem_info *ctx;
4211 uint32_t mem_size, ena, entries;
4212 uint32_t entries_sp, min;
4215 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4217 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4221 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4224 ctx_pg = &ctx->qp_mem;
4225 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4226 if (ctx->qp_entry_size) {
4227 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4228 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4233 ctx_pg = &ctx->srq_mem;
4234 ctx_pg->entries = ctx->srq_max_l2_entries;
4235 if (ctx->srq_entry_size) {
4236 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4237 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4242 ctx_pg = &ctx->cq_mem;
4243 ctx_pg->entries = ctx->cq_max_l2_entries;
4244 if (ctx->cq_entry_size) {
4245 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4246 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4251 ctx_pg = &ctx->vnic_mem;
4252 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4253 ctx->vnic_max_ring_table_entries;
4254 if (ctx->vnic_entry_size) {
4255 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4256 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4261 ctx_pg = &ctx->stat_mem;
4262 ctx_pg->entries = ctx->stat_max_entries;
4263 if (ctx->stat_entry_size) {
4264 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4265 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4270 min = ctx->tqm_min_entries_per_ring;
4272 entries_sp = ctx->qp_max_l2_entries +
4273 ctx->vnic_max_vnic_entries +
4274 2 * ctx->qp_min_qp1_entries + min;
4275 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4277 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4278 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4279 entries = clamp_t(uint32_t, entries, min,
4280 ctx->tqm_max_entries_per_ring);
4281 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4282 ctx_pg = ctx->tqm_mem[i];
4283 ctx_pg->entries = i ? entries : entries_sp;
4284 if (ctx->tqm_entry_size) {
4285 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4286 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4290 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4293 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4294 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4297 "Failed to configure context mem: rc = %d\n", rc);
4299 ctx->flags |= BNXT_CTX_FLAG_INITED;
4304 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4306 struct rte_pci_device *pci_dev = bp->pdev;
4307 char mz_name[RTE_MEMZONE_NAMESIZE];
4308 const struct rte_memzone *mz = NULL;
4309 uint32_t total_alloc_len;
4310 rte_iova_t mz_phys_addr;
4312 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4315 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4316 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4317 pci_dev->addr.bus, pci_dev->addr.devid,
4318 pci_dev->addr.function, "rx_port_stats");
4319 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4320 mz = rte_memzone_lookup(mz_name);
4322 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4323 sizeof(struct rx_port_stats_ext) + 512);
4325 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4328 RTE_MEMZONE_SIZE_HINT_ONLY |
4329 RTE_MEMZONE_IOVA_CONTIG);
4333 memset(mz->addr, 0, mz->len);
4334 mz_phys_addr = mz->iova;
4336 bp->rx_mem_zone = (const void *)mz;
4337 bp->hw_rx_port_stats = mz->addr;
4338 bp->hw_rx_port_stats_map = mz_phys_addr;
4340 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4341 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4342 pci_dev->addr.bus, pci_dev->addr.devid,
4343 pci_dev->addr.function, "tx_port_stats");
4344 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4345 mz = rte_memzone_lookup(mz_name);
4347 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4348 sizeof(struct tx_port_stats_ext) + 512);
4350 mz = rte_memzone_reserve(mz_name,
4354 RTE_MEMZONE_SIZE_HINT_ONLY |
4355 RTE_MEMZONE_IOVA_CONTIG);
4359 memset(mz->addr, 0, mz->len);
4360 mz_phys_addr = mz->iova;
4362 bp->tx_mem_zone = (const void *)mz;
4363 bp->hw_tx_port_stats = mz->addr;
4364 bp->hw_tx_port_stats_map = mz_phys_addr;
4365 bp->flags |= BNXT_FLAG_PORT_STATS;
4367 /* Display extended statistics if FW supports it */
4368 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4369 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4370 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4373 bp->hw_rx_port_stats_ext = (void *)
4374 ((uint8_t *)bp->hw_rx_port_stats +
4375 sizeof(struct rx_port_stats));
4376 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4377 sizeof(struct rx_port_stats);
4378 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4380 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4381 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4382 bp->hw_tx_port_stats_ext = (void *)
4383 ((uint8_t *)bp->hw_tx_port_stats +
4384 sizeof(struct tx_port_stats));
4385 bp->hw_tx_port_stats_ext_map =
4386 bp->hw_tx_port_stats_map +
4387 sizeof(struct tx_port_stats);
4388 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4394 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4396 struct bnxt *bp = eth_dev->data->dev_private;
4399 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4400 RTE_ETHER_ADDR_LEN *
4403 if (eth_dev->data->mac_addrs == NULL) {
4404 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4408 if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4412 /* Generate a random MAC address, if none was assigned by PF */
4413 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4414 bnxt_eth_hw_addr_random(bp->mac_addr);
4416 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4417 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4418 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4420 rc = bnxt_hwrm_set_mac(bp);
4425 /* Copy the permanent MAC from the FUNC_QCAPS response */
4426 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4431 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4435 /* MAC is already configured in FW */
4436 if (BNXT_HAS_DFLT_MAC_SET(bp))
4439 /* Restore the old MAC configured */
4440 rc = bnxt_hwrm_set_mac(bp);
4442 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4447 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4452 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
4454 if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
4455 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
4456 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
4457 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
4458 BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
4459 BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
4463 bnxt_get_svif(uint16_t port_id, bool func_svif,
4464 enum bnxt_ulp_intf_type type)
4466 struct rte_eth_dev *eth_dev;
4469 eth_dev = &rte_eth_devices[port_id];
4470 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4471 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4475 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4478 eth_dev = vfr->parent_dev;
4481 bp = eth_dev->data->dev_private;
4483 return func_svif ? bp->func_svif : bp->port_svif;
4487 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
4489 struct rte_eth_dev *eth_dev;
4490 struct bnxt_vnic_info *vnic;
4493 eth_dev = &rte_eth_devices[port];
4494 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4495 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4499 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4500 return vfr->dflt_vnic_id;
4502 eth_dev = vfr->parent_dev;
4505 bp = eth_dev->data->dev_private;
4507 vnic = BNXT_GET_DEFAULT_VNIC(bp);
4509 return vnic->fw_vnic_id;
4513 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
4515 struct rte_eth_dev *eth_dev;
4518 eth_dev = &rte_eth_devices[port];
4519 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4520 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4524 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4527 eth_dev = vfr->parent_dev;
4530 bp = eth_dev->data->dev_private;
4535 enum bnxt_ulp_intf_type
4536 bnxt_get_interface_type(uint16_t port)
4538 struct rte_eth_dev *eth_dev;
4541 eth_dev = &rte_eth_devices[port];
4542 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
4543 return BNXT_ULP_INTF_TYPE_VF_REP;
4545 bp = eth_dev->data->dev_private;
4547 return BNXT_ULP_INTF_TYPE_PF;
4548 else if (BNXT_VF_IS_TRUSTED(bp))
4549 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
4550 else if (BNXT_VF(bp))
4551 return BNXT_ULP_INTF_TYPE_VF;
4553 return BNXT_ULP_INTF_TYPE_INVALID;
4557 bnxt_get_phy_port_id(uint16_t port_id)
4559 struct bnxt_representor *vfr;
4560 struct rte_eth_dev *eth_dev;
4563 eth_dev = &rte_eth_devices[port_id];
4564 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4565 vfr = eth_dev->data->dev_private;
4569 eth_dev = vfr->parent_dev;
4572 bp = eth_dev->data->dev_private;
4574 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
4578 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
4580 struct rte_eth_dev *eth_dev;
4583 eth_dev = &rte_eth_devices[port_id];
4584 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4585 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4589 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4590 return vfr->fw_fid - 1;
4592 eth_dev = vfr->parent_dev;
4595 bp = eth_dev->data->dev_private;
4597 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
4601 bnxt_get_vport(uint16_t port_id)
4603 return (1 << bnxt_get_phy_port_id(port_id));
4606 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
4608 struct bnxt_error_recovery_info *info = bp->recovery_info;
4611 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
4612 memset(info, 0, sizeof(*info));
4616 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4619 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4622 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4624 bp->recovery_info = info;
4627 static void bnxt_check_fw_status(struct bnxt *bp)
4631 if (!(bp->recovery_info &&
4632 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
4635 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
4636 if (fw_status != BNXT_FW_STATUS_HEALTHY)
4637 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
4641 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
4643 struct bnxt_error_recovery_info *info = bp->recovery_info;
4644 uint32_t status_loc;
4647 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
4648 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4649 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4650 BNXT_GRCP_WINDOW_2_BASE +
4651 offsetof(struct hcomm_status,
4653 /* If the signature is absent, then FW does not support this feature */
4654 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
4655 HCOMM_STATUS_SIGNATURE_VAL)
4659 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4663 bp->recovery_info = info;
4665 memset(info, 0, sizeof(*info));
4668 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4669 BNXT_GRCP_WINDOW_2_BASE +
4670 offsetof(struct hcomm_status,
4673 /* Only pre-map the FW health status GRC register */
4674 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
4677 info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
4678 info->mapped_status_regs[BNXT_FW_STATUS_REG] =
4679 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
4681 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
4682 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4684 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
4689 static int bnxt_init_fw(struct bnxt *bp)
4696 rc = bnxt_map_hcomm_fw_status_reg(bp);
4700 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
4702 bnxt_check_fw_status(bp);
4706 rc = bnxt_hwrm_func_reset(bp);
4710 rc = bnxt_hwrm_vnic_qcaps(bp);
4714 rc = bnxt_hwrm_queue_qportcfg(bp);
4718 /* Get the MAX capabilities for this function.
4719 * This function also allocates context memory for TQM rings and
4720 * informs the firmware about this allocated backing store memory.
4722 rc = bnxt_hwrm_func_qcaps(bp);
4726 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4730 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4734 bnxt_hwrm_port_mac_qcfg(bp);
4736 bnxt_hwrm_parent_pf_qcfg(bp);
4738 bnxt_hwrm_port_phy_qcaps(bp);
4740 bnxt_alloc_error_recovery_info(bp);
4741 /* Get the adapter error recovery support info */
4742 rc = bnxt_hwrm_error_recovery_qcfg(bp);
4744 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4746 bnxt_hwrm_port_led_qcaps(bp);
4752 bnxt_init_locks(struct bnxt *bp)
4756 err = pthread_mutex_init(&bp->flow_lock, NULL);
4758 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4762 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4764 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4768 err = pthread_mutex_init(&bp->health_check_lock, NULL);
4770 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
4774 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4778 rc = bnxt_init_fw(bp);
4782 if (!reconfig_dev) {
4783 rc = bnxt_setup_mac_addr(bp->eth_dev);
4787 rc = bnxt_restore_dflt_mac(bp);
4792 bnxt_config_vf_req_fwd(bp);
4794 rc = bnxt_hwrm_func_driver_register(bp);
4796 PMD_DRV_LOG(ERR, "Failed to register driver");
4801 if (bp->pdev->max_vfs) {
4802 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4804 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4808 rc = bnxt_hwrm_allocate_pf_only(bp);
4811 "Failed to allocate PF resources");
4817 rc = bnxt_alloc_mem(bp, reconfig_dev);
4821 rc = bnxt_setup_int(bp);
4825 rc = bnxt_request_int(bp);
4829 rc = bnxt_init_ctx_mem(bp);
4831 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
4835 rc = bnxt_init_locks(bp);
4843 bnxt_parse_devarg_truflow(__rte_unused const char *key,
4844 const char *value, void *opaque_arg)
4846 struct bnxt *bp = opaque_arg;
4847 unsigned long truflow;
4850 if (!value || !opaque_arg) {
4852 "Invalid parameter passed to truflow devargs.\n");
4856 truflow = strtoul(value, &end, 10);
4857 if (end == NULL || *end != '\0' ||
4858 (truflow == ULONG_MAX && errno == ERANGE)) {
4860 "Invalid parameter passed to truflow devargs.\n");
4864 if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
4866 "Invalid value passed to truflow devargs.\n");
4871 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
4872 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
4874 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
4875 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
4882 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
4883 const char *value, void *opaque_arg)
4885 struct bnxt *bp = opaque_arg;
4886 unsigned long flow_xstat;
4889 if (!value || !opaque_arg) {
4891 "Invalid parameter passed to flow_xstat devarg.\n");
4895 flow_xstat = strtoul(value, &end, 10);
4896 if (end == NULL || *end != '\0' ||
4897 (flow_xstat == ULONG_MAX && errno == ERANGE)) {
4899 "Invalid parameter passed to flow_xstat devarg.\n");
4903 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
4905 "Invalid value passed to flow_xstat devarg.\n");
4909 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
4910 if (BNXT_FLOW_XSTATS_EN(bp))
4911 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
4917 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
4918 const char *value, void *opaque_arg)
4920 struct bnxt *bp = opaque_arg;
4921 unsigned long max_num_kflows;
4924 if (!value || !opaque_arg) {
4926 "Invalid parameter passed to max_num_kflows devarg.\n");
4930 max_num_kflows = strtoul(value, &end, 10);
4931 if (end == NULL || *end != '\0' ||
4932 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
4934 "Invalid parameter passed to max_num_kflows devarg.\n");
4938 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
4940 "Invalid value passed to max_num_kflows devarg.\n");
4944 bp->max_num_kflows = max_num_kflows;
4945 if (bp->max_num_kflows)
4946 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
4953 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
4954 const char *value, void *opaque_arg)
4956 struct bnxt_representor *vfr_bp = opaque_arg;
4957 unsigned long rep_is_pf;
4960 if (!value || !opaque_arg) {
4962 "Invalid parameter passed to rep_is_pf devargs.\n");
4966 rep_is_pf = strtoul(value, &end, 10);
4967 if (end == NULL || *end != '\0' ||
4968 (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
4970 "Invalid parameter passed to rep_is_pf devargs.\n");
4974 if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
4976 "Invalid value passed to rep_is_pf devargs.\n");
4980 vfr_bp->flags |= rep_is_pf;
4981 if (BNXT_REP_PF(vfr_bp))
4982 PMD_DRV_LOG(INFO, "PF representor\n");
4984 PMD_DRV_LOG(INFO, "VF representor\n");
4990 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
4991 const char *value, void *opaque_arg)
4993 struct bnxt_representor *vfr_bp = opaque_arg;
4994 unsigned long rep_based_pf;
4997 if (!value || !opaque_arg) {
4999 "Invalid parameter passed to rep_based_pf "
5004 rep_based_pf = strtoul(value, &end, 10);
5005 if (end == NULL || *end != '\0' ||
5006 (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5008 "Invalid parameter passed to rep_based_pf "
5013 if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5015 "Invalid value passed to rep_based_pf devargs.\n");
5019 vfr_bp->rep_based_pf = rep_based_pf;
5020 vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
5022 PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5028 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5029 const char *value, void *opaque_arg)
5031 struct bnxt_representor *vfr_bp = opaque_arg;
5032 unsigned long rep_q_r2f;
5035 if (!value || !opaque_arg) {
5037 "Invalid parameter passed to rep_q_r2f "
5042 rep_q_r2f = strtoul(value, &end, 10);
5043 if (end == NULL || *end != '\0' ||
5044 (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5046 "Invalid parameter passed to rep_q_r2f "
5051 if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5053 "Invalid value passed to rep_q_r2f devargs.\n");
5057 vfr_bp->rep_q_r2f = rep_q_r2f;
5058 vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5059 PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5065 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5066 const char *value, void *opaque_arg)
5068 struct bnxt_representor *vfr_bp = opaque_arg;
5069 unsigned long rep_q_f2r;
5072 if (!value || !opaque_arg) {
5074 "Invalid parameter passed to rep_q_f2r "
5079 rep_q_f2r = strtoul(value, &end, 10);
5080 if (end == NULL || *end != '\0' ||
5081 (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5083 "Invalid parameter passed to rep_q_f2r "
5088 if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5090 "Invalid value passed to rep_q_f2r devargs.\n");
5094 vfr_bp->rep_q_f2r = rep_q_f2r;
5095 vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5096 PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5102 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5103 const char *value, void *opaque_arg)
5105 struct bnxt_representor *vfr_bp = opaque_arg;
5106 unsigned long rep_fc_r2f;
5109 if (!value || !opaque_arg) {
5111 "Invalid parameter passed to rep_fc_r2f "
5116 rep_fc_r2f = strtoul(value, &end, 10);
5117 if (end == NULL || *end != '\0' ||
5118 (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5120 "Invalid parameter passed to rep_fc_r2f "
5125 if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5127 "Invalid value passed to rep_fc_r2f devargs.\n");
5131 vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5132 vfr_bp->rep_fc_r2f = rep_fc_r2f;
5133 PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5139 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5140 const char *value, void *opaque_arg)
5142 struct bnxt_representor *vfr_bp = opaque_arg;
5143 unsigned long rep_fc_f2r;
5146 if (!value || !opaque_arg) {
5148 "Invalid parameter passed to rep_fc_f2r "
5153 rep_fc_f2r = strtoul(value, &end, 10);
5154 if (end == NULL || *end != '\0' ||
5155 (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5157 "Invalid parameter passed to rep_fc_f2r "
5162 if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5164 "Invalid value passed to rep_fc_f2r devargs.\n");
5168 vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5169 vfr_bp->rep_fc_f2r = rep_fc_f2r;
5170 PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5176 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5178 struct rte_kvargs *kvlist;
5180 if (devargs == NULL)
5183 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5188 * Handler for "truflow" devarg.
5189 * Invoked as for ex: "-a 0000:00:0d.0,host-based-truflow=1"
5191 rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5192 bnxt_parse_devarg_truflow, bp);
5195 * Handler for "flow_xstat" devarg.
5196 * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5198 rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5199 bnxt_parse_devarg_flow_xstat, bp);
5202 * Handler for "max_num_kflows" devarg.
5203 * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5205 rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5206 bnxt_parse_devarg_max_num_kflows, bp);
5208 rte_kvargs_free(kvlist);
5211 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5215 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5216 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5219 "Failed to alloc switch domain: %d\n", rc);
5222 "Switch domain allocated %d\n",
5223 bp->switch_domain_id);
5230 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5232 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5233 static int version_printed;
5237 if (version_printed++ == 0)
5238 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5240 eth_dev->dev_ops = &bnxt_dev_ops;
5241 eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5242 eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5243 eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5244 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5245 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5248 * For secondary processes, we don't initialise any further
5249 * as primary has already done this work.
5251 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5254 rte_eth_copy_pci_info(eth_dev, pci_dev);
5255 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
5257 bp = eth_dev->data->dev_private;
5259 /* Parse dev arguments passed on when starting the DPDK application. */
5260 bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5262 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5264 if (bnxt_vf_pciid(pci_dev->id.device_id))
5265 bp->flags |= BNXT_FLAG_VF;
5267 if (bnxt_p5_device(pci_dev->id.device_id))
5268 bp->flags |= BNXT_FLAG_CHIP_P5;
5270 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5271 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5272 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5273 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5274 bp->flags |= BNXT_FLAG_STINGRAY;
5276 if (BNXT_TRUFLOW_EN(bp)) {
5277 /* extra mbuf field is required to store CFA code from mark */
5278 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5279 .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5280 .size = sizeof(bnxt_cfa_code_dynfield_t),
5281 .align = __alignof__(bnxt_cfa_code_dynfield_t),
5283 bnxt_cfa_code_dynfield_offset =
5284 rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5285 if (bnxt_cfa_code_dynfield_offset < 0) {
5287 "Failed to register mbuf field for TruFlow mark\n");
5292 rc = bnxt_init_board(eth_dev);
5295 "Failed to initialize board rc: %x\n", rc);
5299 rc = bnxt_alloc_pf_info(bp);
5303 rc = bnxt_alloc_link_info(bp);
5307 rc = bnxt_alloc_parent_info(bp);
5311 rc = bnxt_alloc_hwrm_resources(bp);
5314 "Failed to allocate hwrm resource rc: %x\n", rc);
5317 rc = bnxt_alloc_leds_info(bp);
5321 rc = bnxt_alloc_cos_queues(bp);
5325 rc = bnxt_init_resources(bp, false);
5329 rc = bnxt_alloc_stats_mem(bp);
5333 bnxt_alloc_switch_domain(bp);
5336 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5337 pci_dev->mem_resource[0].phys_addr,
5338 pci_dev->mem_resource[0].addr);
5343 bnxt_dev_uninit(eth_dev);
5348 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5357 ctx->dma = RTE_BAD_IOVA;
5358 ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5361 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5363 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5364 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5365 bp->flow_stat->rx_fc_out_tbl.ctx_id,
5366 bp->flow_stat->max_fc,
5369 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5370 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5371 bp->flow_stat->tx_fc_out_tbl.ctx_id,
5372 bp->flow_stat->max_fc,
5375 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5376 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5377 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5379 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5380 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5381 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5383 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5384 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5385 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5387 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5388 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5389 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5392 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5394 bnxt_unregister_fc_ctx_mem(bp);
5396 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5397 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5398 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5399 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5402 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5404 if (BNXT_FLOW_XSTATS_EN(bp))
5405 bnxt_uninit_fc_ctx_mem(bp);
5409 bnxt_free_error_recovery_info(struct bnxt *bp)
5411 rte_free(bp->recovery_info);
5412 bp->recovery_info = NULL;
5413 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5417 bnxt_uninit_locks(struct bnxt *bp)
5419 pthread_mutex_destroy(&bp->flow_lock);
5420 pthread_mutex_destroy(&bp->def_cp_lock);
5421 pthread_mutex_destroy(&bp->health_check_lock);
5423 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
5424 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
5429 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5434 bnxt_free_mem(bp, reconfig_dev);
5436 bnxt_hwrm_func_buf_unrgtr(bp);
5437 rte_free(bp->pf->vf_req_buf);
5439 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5440 bp->flags &= ~BNXT_FLAG_REGISTERED;
5441 bnxt_free_ctx_mem(bp);
5442 if (!reconfig_dev) {
5443 bnxt_free_hwrm_resources(bp);
5444 bnxt_free_error_recovery_info(bp);
5447 bnxt_uninit_ctx_mem(bp);
5449 bnxt_uninit_locks(bp);
5450 bnxt_free_flow_stats_info(bp);
5451 bnxt_free_rep_info(bp);
5452 rte_free(bp->ptp_cfg);
5458 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5460 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5463 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5465 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5466 bnxt_dev_close_op(eth_dev);
5471 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5473 struct bnxt *bp = eth_dev->data->dev_private;
5474 struct rte_eth_dev *vf_rep_eth_dev;
5480 for (i = 0; i < bp->num_reps; i++) {
5481 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5482 if (!vf_rep_eth_dev)
5484 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
5485 vf_rep_eth_dev->data->port_id);
5486 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
5488 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
5489 eth_dev->data->port_id);
5490 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5495 static void bnxt_free_rep_info(struct bnxt *bp)
5497 rte_free(bp->rep_info);
5498 bp->rep_info = NULL;
5499 rte_free(bp->cfa_code_map);
5500 bp->cfa_code_map = NULL;
5503 static int bnxt_init_rep_info(struct bnxt *bp)
5510 bp->rep_info = rte_zmalloc("bnxt_rep_info",
5511 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5513 if (!bp->rep_info) {
5514 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5517 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5518 sizeof(*bp->cfa_code_map) *
5519 BNXT_MAX_CFA_CODE, 0);
5520 if (!bp->cfa_code_map) {
5521 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5522 bnxt_free_rep_info(bp);
5526 for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5527 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5529 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5531 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5532 bnxt_free_rep_info(bp);
5536 rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
5538 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
5539 bnxt_free_rep_info(bp);
5546 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5547 struct rte_eth_devargs *eth_da,
5548 struct rte_eth_dev *backing_eth_dev,
5549 const char *dev_args)
5551 struct rte_eth_dev *vf_rep_eth_dev;
5552 char name[RTE_ETH_NAME_MAX_LEN];
5553 struct bnxt *backing_bp;
5556 struct rte_kvargs *kvlist = NULL;
5558 num_rep = eth_da->nb_representor_ports;
5559 if (num_rep > BNXT_MAX_VF_REPS) {
5560 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5561 num_rep, BNXT_MAX_VF_REPS);
5565 if (num_rep >= RTE_MAX_ETHPORTS) {
5567 "nb_representor_ports = %d > %d MAX ETHPORTS\n",
5568 num_rep, RTE_MAX_ETHPORTS);
5572 backing_bp = backing_eth_dev->data->dev_private;
5574 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
5576 "Not a PF or trusted VF. No Representor support\n");
5577 /* Returning an error is not an option.
5578 * Applications are not handling this correctly
5583 if (bnxt_init_rep_info(backing_bp))
5586 for (i = 0; i < num_rep; i++) {
5587 struct bnxt_representor representor = {
5588 .vf_id = eth_da->representor_ports[i],
5589 .switch_domain_id = backing_bp->switch_domain_id,
5590 .parent_dev = backing_eth_dev
5593 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
5594 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
5595 representor.vf_id, BNXT_MAX_VF_REPS);
5599 /* representor port net_bdf_port */
5600 snprintf(name, sizeof(name), "net_%s_representor_%d",
5601 pci_dev->device.name, eth_da->representor_ports[i]);
5603 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
5606 * Handler for "rep_is_pf" devarg.
5607 * Invoked as for ex: "-a 000:00:0d.0,
5608 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5610 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
5611 bnxt_parse_devarg_rep_is_pf,
5612 (void *)&representor);
5618 * Handler for "rep_based_pf" devarg.
5619 * Invoked as for ex: "-a 000:00:0d.0,
5620 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5622 ret = rte_kvargs_process(kvlist,
5623 BNXT_DEVARG_REP_BASED_PF,
5624 bnxt_parse_devarg_rep_based_pf,
5625 (void *)&representor);
5631 * Handler for "rep_based_pf" devarg.
5632 * Invoked as for ex: "-a 000:00:0d.0,
5633 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5635 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
5636 bnxt_parse_devarg_rep_q_r2f,
5637 (void *)&representor);
5643 * Handler for "rep_based_pf" devarg.
5644 * Invoked as for ex: "-a 000:00:0d.0,
5645 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5647 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
5648 bnxt_parse_devarg_rep_q_f2r,
5649 (void *)&representor);
5655 * Handler for "rep_based_pf" devarg.
5656 * Invoked as for ex: "-a 000:00:0d.0,
5657 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5659 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
5660 bnxt_parse_devarg_rep_fc_r2f,
5661 (void *)&representor);
5667 * Handler for "rep_based_pf" devarg.
5668 * Invoked as for ex: "-a 000:00:0d.0,
5669 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5671 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
5672 bnxt_parse_devarg_rep_fc_f2r,
5673 (void *)&representor);
5680 ret = rte_eth_dev_create(&pci_dev->device, name,
5681 sizeof(struct bnxt_representor),
5683 bnxt_representor_init,
5686 PMD_DRV_LOG(ERR, "failed to create bnxt vf "
5687 "representor %s.", name);
5691 vf_rep_eth_dev = rte_eth_dev_allocated(name);
5692 if (!vf_rep_eth_dev) {
5693 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
5694 " for VF-Rep: %s.", name);
5699 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
5700 backing_eth_dev->data->port_id);
5701 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
5703 backing_bp->num_reps++;
5707 rte_kvargs_free(kvlist);
5711 /* If num_rep > 1, then rollback already created
5712 * ports, since we'll be failing the probe anyway
5715 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
5717 rte_kvargs_free(kvlist);
5722 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5723 struct rte_pci_device *pci_dev)
5725 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
5726 struct rte_eth_dev *backing_eth_dev;
5730 if (pci_dev->device.devargs) {
5731 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
5737 num_rep = eth_da.nb_representor_ports;
5738 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
5741 /* We could come here after first level of probe is already invoked
5742 * as part of an application bringup(OVS-DPDK vswitchd), so first check
5743 * for already allocated eth_dev for the backing device (PF/Trusted VF)
5745 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5746 if (backing_eth_dev == NULL) {
5747 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
5748 sizeof(struct bnxt),
5749 eth_dev_pci_specific_init, pci_dev,
5750 bnxt_dev_init, NULL);
5752 if (ret || !num_rep)
5755 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5757 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
5758 backing_eth_dev->data->port_id);
5763 /* probe representor ports now */
5764 ret = bnxt_rep_port_probe(pci_dev, ð_da, backing_eth_dev,
5765 pci_dev->device.devargs->args);
5770 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5772 struct rte_eth_dev *eth_dev;
5774 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5776 return 0; /* Invoked typically only by OVS-DPDK, by the
5777 * time it comes here the eth_dev is already
5778 * deleted by rte_eth_dev_close(), so returning
5779 * +ve value will at least help in proper cleanup
5782 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
5783 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
5784 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
5785 return rte_eth_dev_destroy(eth_dev,
5786 bnxt_representor_uninit);
5788 return rte_eth_dev_destroy(eth_dev,
5791 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5795 static struct rte_pci_driver bnxt_rte_pmd = {
5796 .id_table = bnxt_pci_id_map,
5797 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
5798 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
5801 .probe = bnxt_pci_probe,
5802 .remove = bnxt_pci_remove,
5806 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5808 if (strcmp(dev->device->driver->name, drv->driver.name))
5814 bool is_bnxt_supported(struct rte_eth_dev *dev)
5816 return is_device_supported(dev, &bnxt_rte_pmd);
5819 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
5820 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5821 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5822 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");