1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2021 Broadcom
10 #include <ethdev_driver.h>
11 #include <ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
15 #include <rte_kvargs.h>
19 #include "bnxt_filter.h"
20 #include "bnxt_hwrm.h"
22 #include "bnxt_reps.h"
23 #include "bnxt_ring.h"
26 #include "bnxt_stats.h"
29 #include "bnxt_vnic.h"
30 #include "hsi_struct_def_dpdk.h"
31 #include "bnxt_nvm_defs.h"
32 #include "bnxt_tf_common.h"
33 #include "ulp_flow_db.h"
34 #include "rte_pmd_bnxt.h"
36 #define DRV_MODULE_NAME "bnxt"
37 static const char bnxt_version[] =
38 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
41 * The set of PCI devices this driver supports
43 static const struct rte_pci_id bnxt_pci_id_map[] = {
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
45 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
47 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
87 { .vendor_id = 0, /* sentinel */ },
90 #define BNXT_DEVARG_ACCUM_STATS "accum-stats"
91 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat"
92 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows"
93 #define BNXT_DEVARG_REPRESENTOR "representor"
94 #define BNXT_DEVARG_REP_BASED_PF "rep-based-pf"
95 #define BNXT_DEVARG_REP_IS_PF "rep-is-pf"
96 #define BNXT_DEVARG_REP_Q_R2F "rep-q-r2f"
97 #define BNXT_DEVARG_REP_Q_F2R "rep-q-f2r"
98 #define BNXT_DEVARG_REP_FC_R2F "rep-fc-r2f"
99 #define BNXT_DEVARG_REP_FC_F2R "rep-fc-f2r"
100 #define BNXT_DEVARG_APP_ID "app-id"
102 static const char *const bnxt_dev_args[] = {
103 BNXT_DEVARG_REPRESENTOR,
104 BNXT_DEVARG_ACCUM_STATS,
105 BNXT_DEVARG_FLOW_XSTAT,
106 BNXT_DEVARG_MAX_NUM_KFLOWS,
107 BNXT_DEVARG_REP_BASED_PF,
108 BNXT_DEVARG_REP_IS_PF,
109 BNXT_DEVARG_REP_Q_R2F,
110 BNXT_DEVARG_REP_Q_F2R,
111 BNXT_DEVARG_REP_FC_R2F,
112 BNXT_DEVARG_REP_FC_F2R,
118 * accum-stats == false to disable flow counter accumulation
119 * accum-stats == true to enable flow counter accumulation
121 #define BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats) ((accum_stats) > 1)
124 * app-id = an non-negative 8-bit number
126 #define BNXT_DEVARG_APP_ID_INVALID(val) ((val) > 255)
129 * flow_xstat == false to disable the feature
130 * flow_xstat == true to enable the feature
132 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1)
135 * rep_is_pf == false to indicate VF representor
136 * rep_is_pf == true to indicate PF representor
138 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf) ((rep_is_pf) > 1)
141 * rep_based_pf == Physical index of the PF
143 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf) ((rep_based_pf) > 15)
145 * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
147 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f) ((rep_q_r2f) > 3)
150 * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
152 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r) ((rep_q_f2r) > 3)
155 * rep_fc_r2f == Flow control for the representor to endpoint direction
157 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f) ((rep_fc_r2f) > 1)
160 * rep_fc_f2r == Flow control for the endpoint to representor direction
162 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r) ((rep_fc_f2r) > 1)
164 int bnxt_cfa_code_dynfield_offset = -1;
167 * max_num_kflows must be >= 32
168 * and must be a power-of-2 supported value
169 * return: 1 -> invalid
172 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
174 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
179 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
180 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
181 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
182 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
183 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
184 static int bnxt_restore_vlan_filters(struct bnxt *bp);
185 static void bnxt_dev_recover(void *arg);
186 static void bnxt_free_error_recovery_info(struct bnxt *bp);
187 static void bnxt_free_rep_info(struct bnxt *bp);
189 int is_bnxt_in_error(struct bnxt *bp)
191 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
193 if (bp->flags & BNXT_FLAG_FW_RESET)
199 /***********************/
202 * High level utility functions
205 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
207 unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
208 BNXT_RSS_TBL_SIZE_P5);
210 if (!BNXT_CHIP_P5(bp))
213 return RTE_ALIGN_MUL_CEIL(num_rss_rings,
214 BNXT_RSS_ENTRIES_PER_CTX_P5) /
215 BNXT_RSS_ENTRIES_PER_CTX_P5;
218 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
220 if (!BNXT_CHIP_P5(bp))
221 return HW_HASH_INDEX_SIZE;
223 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
226 static void bnxt_free_parent_info(struct bnxt *bp)
228 rte_free(bp->parent);
232 static void bnxt_free_pf_info(struct bnxt *bp)
238 static void bnxt_free_link_info(struct bnxt *bp)
240 rte_free(bp->link_info);
241 bp->link_info = NULL;
244 static void bnxt_free_leds_info(struct bnxt *bp)
253 static void bnxt_free_flow_stats_info(struct bnxt *bp)
255 rte_free(bp->flow_stat);
256 bp->flow_stat = NULL;
259 static void bnxt_free_cos_queues(struct bnxt *bp)
261 rte_free(bp->rx_cos_queue);
262 bp->rx_cos_queue = NULL;
263 rte_free(bp->tx_cos_queue);
264 bp->tx_cos_queue = NULL;
267 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
269 bnxt_free_filter_mem(bp);
270 bnxt_free_vnic_attributes(bp);
271 bnxt_free_vnic_mem(bp);
273 /* tx/rx rings are configured as part of *_queue_setup callbacks.
274 * If the number of rings change across fw update,
275 * we don't have much choice except to warn the user.
279 bnxt_free_tx_rings(bp);
280 bnxt_free_rx_rings(bp);
282 bnxt_free_async_cp_ring(bp);
283 bnxt_free_rxtx_nq_ring(bp);
285 rte_free(bp->grp_info);
289 static int bnxt_alloc_parent_info(struct bnxt *bp)
291 bp->parent = rte_zmalloc("bnxt_parent_info",
292 sizeof(struct bnxt_parent_info), 0);
293 if (bp->parent == NULL)
299 static int bnxt_alloc_pf_info(struct bnxt *bp)
301 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
308 static int bnxt_alloc_link_info(struct bnxt *bp)
311 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
312 if (bp->link_info == NULL)
318 static int bnxt_alloc_leds_info(struct bnxt *bp)
323 bp->leds = rte_zmalloc("bnxt_leds",
324 BNXT_MAX_LED * sizeof(struct bnxt_led_info),
326 if (bp->leds == NULL)
332 static int bnxt_alloc_cos_queues(struct bnxt *bp)
335 rte_zmalloc("bnxt_rx_cosq",
336 BNXT_COS_QUEUE_COUNT *
337 sizeof(struct bnxt_cos_queue_info),
339 if (bp->rx_cos_queue == NULL)
343 rte_zmalloc("bnxt_tx_cosq",
344 BNXT_COS_QUEUE_COUNT *
345 sizeof(struct bnxt_cos_queue_info),
347 if (bp->tx_cos_queue == NULL)
353 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
355 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
356 sizeof(struct bnxt_flow_stat_info), 0);
357 if (bp->flow_stat == NULL)
363 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
367 rc = bnxt_alloc_ring_grps(bp);
371 rc = bnxt_alloc_async_ring_struct(bp);
375 rc = bnxt_alloc_vnic_mem(bp);
379 rc = bnxt_alloc_vnic_attributes(bp);
383 rc = bnxt_alloc_filter_mem(bp);
387 rc = bnxt_alloc_async_cp_ring(bp);
391 rc = bnxt_alloc_rxtx_nq_ring(bp);
395 if (BNXT_FLOW_XSTATS_EN(bp)) {
396 rc = bnxt_alloc_flow_stats_info(bp);
404 bnxt_free_mem(bp, reconfig);
408 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
410 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
411 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
412 uint64_t rx_offloads = dev_conf->rxmode.offloads;
413 struct bnxt_rx_queue *rxq;
417 rc = bnxt_vnic_grp_alloc(bp, vnic);
421 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
422 vnic_id, vnic, vnic->fw_grp_ids);
424 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
428 /* Alloc RSS context only if RSS mode is enabled */
429 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
430 int j, nr_ctxs = bnxt_rss_ctxts(bp);
432 /* RSS table size in Thor is 512.
433 * Cap max Rx rings to same value
435 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
436 PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
437 bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
442 for (j = 0; j < nr_ctxs; j++) {
443 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
449 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
453 vnic->num_lb_ctxts = nr_ctxs;
457 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
458 * setting is not available at this time, it will not be
459 * configured correctly in the CFA.
461 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
462 vnic->vlan_strip = true;
464 vnic->vlan_strip = false;
466 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
470 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
474 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
475 rxq = bp->eth_dev->data->rx_queues[j];
478 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
479 j, rxq->vnic, rxq->vnic->fw_grp_ids);
481 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
482 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
484 vnic->rx_queue_cnt++;
487 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
489 rc = bnxt_vnic_rss_configure(bp, vnic);
493 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
495 rc = bnxt_hwrm_vnic_tpa_cfg(bp, vnic,
496 (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) ?
503 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
508 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
512 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
513 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
518 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
519 " rx_fc_in_tbl.ctx_id = %d\n",
520 bp->flow_stat->rx_fc_in_tbl.va,
521 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
522 bp->flow_stat->rx_fc_in_tbl.ctx_id);
524 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
525 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
530 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
531 " rx_fc_out_tbl.ctx_id = %d\n",
532 bp->flow_stat->rx_fc_out_tbl.va,
533 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
534 bp->flow_stat->rx_fc_out_tbl.ctx_id);
536 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
537 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
542 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
543 " tx_fc_in_tbl.ctx_id = %d\n",
544 bp->flow_stat->tx_fc_in_tbl.va,
545 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
546 bp->flow_stat->tx_fc_in_tbl.ctx_id);
548 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
549 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
554 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
555 " tx_fc_out_tbl.ctx_id = %d\n",
556 bp->flow_stat->tx_fc_out_tbl.va,
557 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
558 bp->flow_stat->tx_fc_out_tbl.ctx_id);
560 memset(bp->flow_stat->rx_fc_out_tbl.va,
562 bp->flow_stat->rx_fc_out_tbl.size);
563 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
564 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
565 bp->flow_stat->rx_fc_out_tbl.ctx_id,
566 bp->flow_stat->max_fc,
571 memset(bp->flow_stat->tx_fc_out_tbl.va,
573 bp->flow_stat->tx_fc_out_tbl.size);
574 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
575 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
576 bp->flow_stat->tx_fc_out_tbl.ctx_id,
577 bp->flow_stat->max_fc,
583 static int bnxt_alloc_ctx_mem_buf(struct bnxt *bp, char *type, size_t size,
584 struct bnxt_ctx_mem_buf_info *ctx)
589 ctx->va = rte_zmalloc_socket(type, size, 0,
590 bp->eth_dev->device->numa_node);
593 rte_mem_lock_page(ctx->va);
595 ctx->dma = rte_mem_virt2iova(ctx->va);
596 if (ctx->dma == RTE_BAD_IOVA)
602 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
604 struct rte_pci_device *pdev = bp->pdev;
605 char type[RTE_MEMZONE_NAMESIZE];
609 max_fc = bp->flow_stat->max_fc;
611 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
612 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
613 /* 4 bytes for each counter-id */
614 rc = bnxt_alloc_ctx_mem_buf(bp, type,
616 &bp->flow_stat->rx_fc_in_tbl);
620 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
621 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
622 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
623 rc = bnxt_alloc_ctx_mem_buf(bp, type,
625 &bp->flow_stat->rx_fc_out_tbl);
629 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
630 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
631 /* 4 bytes for each counter-id */
632 rc = bnxt_alloc_ctx_mem_buf(bp, type,
634 &bp->flow_stat->tx_fc_in_tbl);
638 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
639 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
640 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
641 rc = bnxt_alloc_ctx_mem_buf(bp, type,
643 &bp->flow_stat->tx_fc_out_tbl);
647 rc = bnxt_register_fc_ctx_mem(bp);
652 static int bnxt_init_ctx_mem(struct bnxt *bp)
656 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
657 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
658 !BNXT_FLOW_XSTATS_EN(bp))
661 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
665 rc = bnxt_init_fc_ctx_mem(bp);
670 static int bnxt_update_phy_setting(struct bnxt *bp)
672 struct rte_eth_link new;
675 rc = bnxt_get_hwrm_link_config(bp, &new);
677 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
682 * On BCM957508-N2100 adapters, FW will not allow any user other
683 * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
684 * always returns link up. Force phy update always in that case.
686 if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
687 rc = bnxt_set_hwrm_link_config(bp, true);
689 PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
697 static void bnxt_free_prev_ring_stats(struct bnxt *bp)
699 rte_free(bp->prev_rx_ring_stats);
700 rte_free(bp->prev_tx_ring_stats);
702 bp->prev_rx_ring_stats = NULL;
703 bp->prev_tx_ring_stats = NULL;
706 static int bnxt_alloc_prev_ring_stats(struct bnxt *bp)
708 bp->prev_rx_ring_stats = rte_zmalloc("bnxt_prev_rx_ring_stats",
709 sizeof(struct bnxt_ring_stats) *
712 if (bp->prev_rx_ring_stats == NULL)
715 bp->prev_tx_ring_stats = rte_zmalloc("bnxt_prev_tx_ring_stats",
716 sizeof(struct bnxt_ring_stats) *
719 if (bp->prev_tx_ring_stats == NULL)
725 bnxt_free_prev_ring_stats(bp);
729 static int bnxt_start_nic(struct bnxt *bp)
731 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
732 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
733 uint32_t intr_vector = 0;
734 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
735 uint32_t vec = BNXT_MISC_VEC_ID;
739 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
740 bp->eth_dev->data->dev_conf.rxmode.offloads |=
741 DEV_RX_OFFLOAD_JUMBO_FRAME;
742 bp->flags |= BNXT_FLAG_JUMBO;
744 bp->eth_dev->data->dev_conf.rxmode.offloads &=
745 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
746 bp->flags &= ~BNXT_FLAG_JUMBO;
749 /* THOR does not support ring groups.
750 * But we will use the array to save RSS context IDs.
752 if (BNXT_CHIP_P5(bp))
753 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
755 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
757 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
761 rc = bnxt_alloc_hwrm_rings(bp);
763 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
767 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
769 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
773 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
776 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
777 if (bp->rx_cos_queue[i].id != 0xff) {
778 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
782 "Num pools more than FW profile\n");
786 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
792 rc = bnxt_mq_rx_configure(bp);
794 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
799 rc = bnxt_setup_one_vnic(bp, 0);
802 /* VNIC configuration */
803 if (BNXT_RFS_NEEDS_VNIC(bp)) {
804 for (i = 1; i < bp->nr_vnics; i++) {
805 rc = bnxt_setup_one_vnic(bp, i);
811 for (j = 0; j < bp->tx_nr_rings; j++) {
812 struct bnxt_tx_queue *txq = bp->tx_queues[j];
814 if (!txq->tx_deferred_start) {
815 bp->eth_dev->data->tx_queue_state[j] =
816 RTE_ETH_QUEUE_STATE_STARTED;
817 txq->tx_started = true;
821 for (j = 0; j < bp->rx_nr_rings; j++) {
822 struct bnxt_rx_queue *rxq = bp->rx_queues[j];
824 if (!rxq->rx_deferred_start) {
825 bp->eth_dev->data->rx_queue_state[j] =
826 RTE_ETH_QUEUE_STATE_STARTED;
827 rxq->rx_started = true;
831 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
834 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
838 /* check and configure queue intr-vector mapping */
839 if ((rte_intr_cap_multiple(intr_handle) ||
840 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
841 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
842 intr_vector = bp->eth_dev->data->nb_rx_queues;
843 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
844 if (intr_vector > bp->rx_cp_nr_rings) {
845 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
849 rc = rte_intr_efd_enable(intr_handle, intr_vector);
854 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
855 intr_handle->intr_vec =
856 rte_zmalloc("intr_vec",
857 bp->eth_dev->data->nb_rx_queues *
859 if (intr_handle->intr_vec == NULL) {
860 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
861 " intr_vec", bp->eth_dev->data->nb_rx_queues);
865 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
866 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
867 intr_handle->intr_vec, intr_handle->nb_efd,
868 intr_handle->max_intr);
869 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
871 intr_handle->intr_vec[queue_id] =
872 vec + BNXT_RX_VEC_START;
873 if (vec < base + intr_handle->nb_efd - 1)
878 /* enable uio/vfio intr/eventfd mapping */
879 rc = rte_intr_enable(intr_handle);
880 #ifndef RTE_EXEC_ENV_FREEBSD
881 /* In FreeBSD OS, nic_uio driver does not support interrupts */
886 rc = bnxt_update_phy_setting(bp);
890 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
892 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
897 /* Some of the error status returned by FW may not be from errno.h */
904 static int bnxt_shutdown_nic(struct bnxt *bp)
906 bnxt_free_all_hwrm_resources(bp);
907 bnxt_free_all_filters(bp);
908 bnxt_free_all_vnics(bp);
913 * Device configuration and status function
916 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
918 uint32_t link_speed = 0;
919 uint32_t speed_capa = 0;
921 if (bp->link_info == NULL)
924 link_speed = bp->link_info->support_speeds;
926 /* If PAM4 is configured, use PAM4 supported speed */
927 if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
928 link_speed = bp->link_info->support_pam4_speeds;
930 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
931 speed_capa |= ETH_LINK_SPEED_100M;
932 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
933 speed_capa |= ETH_LINK_SPEED_100M_HD;
934 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
935 speed_capa |= ETH_LINK_SPEED_1G;
936 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
937 speed_capa |= ETH_LINK_SPEED_2_5G;
938 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
939 speed_capa |= ETH_LINK_SPEED_10G;
940 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
941 speed_capa |= ETH_LINK_SPEED_20G;
942 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
943 speed_capa |= ETH_LINK_SPEED_25G;
944 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
945 speed_capa |= ETH_LINK_SPEED_40G;
946 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
947 speed_capa |= ETH_LINK_SPEED_50G;
948 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
949 speed_capa |= ETH_LINK_SPEED_100G;
950 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
951 speed_capa |= ETH_LINK_SPEED_50G;
952 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
953 speed_capa |= ETH_LINK_SPEED_100G;
954 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
955 speed_capa |= ETH_LINK_SPEED_200G;
957 if (bp->link_info->auto_mode ==
958 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
959 speed_capa |= ETH_LINK_SPEED_FIXED;
964 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
965 struct rte_eth_dev_info *dev_info)
967 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
968 struct bnxt *bp = eth_dev->data->dev_private;
969 uint16_t max_vnics, i, j, vpool, vrxq;
970 unsigned int max_rx_rings;
973 rc = is_bnxt_in_error(bp);
978 dev_info->max_mac_addrs = bp->max_l2_ctx;
979 dev_info->max_hash_mac_addrs = 0;
981 /* PF/VF specifics */
983 dev_info->max_vfs = pdev->max_vfs;
985 max_rx_rings = bnxt_max_rings(bp);
986 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
987 dev_info->max_rx_queues = max_rx_rings;
988 dev_info->max_tx_queues = max_rx_rings;
989 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
990 dev_info->hash_key_size = HW_HASH_KEY_SIZE;
991 max_vnics = bp->max_vnics;
994 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
995 dev_info->max_mtu = BNXT_MAX_MTU;
997 /* Fast path specifics */
998 dev_info->min_rx_bufsize = 1;
999 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
1001 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
1002 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
1003 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
1004 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_VLAN_RX_STRIP)
1005 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_VLAN_STRIP;
1006 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
1007 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
1008 dev_info->tx_queue_offload_capa;
1009 if (bp->fw_cap & BNXT_FW_CAP_VLAN_TX_INSERT)
1010 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_VLAN_INSERT;
1011 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
1013 dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
1014 dev_info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
1015 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
1017 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1023 .rx_free_thresh = 32,
1024 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
1027 dev_info->default_txconf = (struct rte_eth_txconf) {
1033 .tx_free_thresh = 32,
1036 eth_dev->data->dev_conf.intr_conf.lsc = 1;
1038 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
1039 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
1040 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
1041 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
1043 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
1044 dev_info->switch_info.name = eth_dev->device->name;
1045 dev_info->switch_info.domain_id = bp->switch_domain_id;
1046 dev_info->switch_info.port_id =
1047 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
1048 BNXT_SWITCH_PORT_ID_TRUSTED_VF;
1052 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
1053 * need further investigation.
1056 /* VMDq resources */
1057 vpool = 64; /* ETH_64_POOLS */
1058 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
1059 for (i = 0; i < 4; vpool >>= 1, i++) {
1060 if (max_vnics > vpool) {
1061 for (j = 0; j < 5; vrxq >>= 1, j++) {
1062 if (dev_info->max_rx_queues > vrxq) {
1068 /* Not enough resources to support VMDq */
1072 /* Not enough resources to support VMDq */
1076 dev_info->max_vmdq_pools = vpool;
1077 dev_info->vmdq_queue_num = vrxq;
1079 dev_info->vmdq_pool_base = 0;
1080 dev_info->vmdq_queue_base = 0;
1085 /* Configure the device based on the configuration provided */
1086 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1088 struct bnxt *bp = eth_dev->data->dev_private;
1089 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1092 bp->rx_queues = (void *)eth_dev->data->rx_queues;
1093 bp->tx_queues = (void *)eth_dev->data->tx_queues;
1094 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1095 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1097 rc = is_bnxt_in_error(bp);
1101 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1102 rc = bnxt_hwrm_check_vf_rings(bp);
1104 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1108 /* If a resource has already been allocated - in this case
1109 * it is the async completion ring, free it. Reallocate it after
1110 * resource reservation. This will ensure the resource counts
1111 * are calculated correctly.
1114 pthread_mutex_lock(&bp->def_cp_lock);
1116 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1117 bnxt_disable_int(bp);
1118 bnxt_free_cp_ring(bp, bp->async_cp_ring);
1121 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1123 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1124 pthread_mutex_unlock(&bp->def_cp_lock);
1128 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1129 rc = bnxt_alloc_async_cp_ring(bp);
1131 pthread_mutex_unlock(&bp->def_cp_lock);
1134 bnxt_enable_int(bp);
1137 pthread_mutex_unlock(&bp->def_cp_lock);
1140 /* Inherit new configurations */
1141 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1142 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1143 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1144 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1145 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1147 goto resource_error;
1149 if (BNXT_HAS_RING_GRPS(bp) &&
1150 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1151 goto resource_error;
1153 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1154 bp->max_vnics < eth_dev->data->nb_rx_queues)
1155 goto resource_error;
1157 bp->rx_cp_nr_rings = bp->rx_nr_rings;
1158 bp->tx_cp_nr_rings = bp->tx_nr_rings;
1160 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1161 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1162 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1164 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1170 "Insufficient resources to support requested config\n");
1172 "Num Queues Requested: Tx %d, Rx %d\n",
1173 eth_dev->data->nb_tx_queues,
1174 eth_dev->data->nb_rx_queues);
1176 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1177 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1178 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1182 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1184 struct rte_eth_link *link = ð_dev->data->dev_link;
1186 if (link->link_status)
1187 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1188 eth_dev->data->port_id,
1189 (uint32_t)link->link_speed,
1190 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1191 ("full-duplex") : ("half-duplex\n"));
1193 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1194 eth_dev->data->port_id);
1198 * Determine whether the current configuration requires support for scattered
1199 * receive; return 1 if scattered receive is required and 0 if not.
1201 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1203 uint32_t overhead = BNXT_MAX_PKT_LEN - BNXT_MAX_MTU;
1207 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1210 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO)
1213 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1214 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1216 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1217 RTE_PKTMBUF_HEADROOM);
1218 if (eth_dev->data->mtu + overhead > buf_size)
1224 static eth_rx_burst_t
1225 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1227 struct bnxt *bp = eth_dev->data->dev_private;
1229 /* Disable vector mode RX for Stingray2 for now */
1230 if (BNXT_CHIP_SR2(bp)) {
1231 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1232 return bnxt_recv_pkts;
1235 #if (defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)) && \
1236 !defined(RTE_LIBRTE_IEEE1588)
1238 /* Vector mode receive cannot be enabled if scattered rx is in use. */
1239 if (eth_dev->data->scattered_rx)
1243 * Vector mode receive cannot be enabled if Truflow is enabled or if
1244 * asynchronous completions and receive completions can be placed in
1245 * the same completion ring.
1247 if (BNXT_TRUFLOW_EN(bp) || !BNXT_NUM_ASYNC_CPR(bp))
1251 * Vector mode receive cannot be enabled if any receive offloads outside
1252 * a limited subset have been enabled.
1254 if (eth_dev->data->dev_conf.rxmode.offloads &
1255 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1256 DEV_RX_OFFLOAD_KEEP_CRC |
1257 DEV_RX_OFFLOAD_JUMBO_FRAME |
1258 DEV_RX_OFFLOAD_IPV4_CKSUM |
1259 DEV_RX_OFFLOAD_UDP_CKSUM |
1260 DEV_RX_OFFLOAD_TCP_CKSUM |
1261 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1262 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1263 DEV_RX_OFFLOAD_RSS_HASH |
1264 DEV_RX_OFFLOAD_VLAN_FILTER))
1267 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1268 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1269 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1271 "Using AVX2 vector mode receive for port %d\n",
1272 eth_dev->data->port_id);
1273 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1274 return bnxt_recv_pkts_vec_avx2;
1277 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1279 "Using SSE vector mode receive for port %d\n",
1280 eth_dev->data->port_id);
1281 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1282 return bnxt_recv_pkts_vec;
1286 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1287 eth_dev->data->port_id);
1289 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1290 eth_dev->data->port_id,
1291 eth_dev->data->scattered_rx,
1292 eth_dev->data->dev_conf.rxmode.offloads);
1294 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1295 return bnxt_recv_pkts;
1298 static eth_tx_burst_t
1299 bnxt_transmit_function(struct rte_eth_dev *eth_dev)
1301 struct bnxt *bp = eth_dev->data->dev_private;
1303 /* Disable vector mode TX for Stingray2 for now */
1304 if (BNXT_CHIP_SR2(bp))
1305 return bnxt_xmit_pkts;
1307 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) && \
1308 !defined(RTE_LIBRTE_IEEE1588)
1309 uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1312 * Vector mode transmit can be enabled only if not using scatter rx
1315 if (eth_dev->data->scattered_rx ||
1316 (offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) ||
1317 BNXT_TRUFLOW_EN(bp))
1320 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1321 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1322 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1324 "Using AVX2 vector mode transmit for port %d\n",
1325 eth_dev->data->port_id);
1326 return bnxt_xmit_pkts_vec_avx2;
1329 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1331 "Using SSE vector mode transmit for port %d\n",
1332 eth_dev->data->port_id);
1333 return bnxt_xmit_pkts_vec;
1337 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1338 eth_dev->data->port_id);
1340 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1341 eth_dev->data->port_id,
1342 eth_dev->data->scattered_rx,
1345 return bnxt_xmit_pkts;
1348 static int bnxt_handle_if_change_status(struct bnxt *bp)
1352 /* Since fw has undergone a reset and lost all contexts,
1353 * set fatal flag to not issue hwrm during cleanup
1355 bp->flags |= BNXT_FLAG_FATAL_ERROR;
1356 bnxt_uninit_resources(bp, true);
1358 /* clear fatal flag so that re-init happens */
1359 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1360 rc = bnxt_init_resources(bp, true);
1362 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1367 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1369 struct bnxt *bp = eth_dev->data->dev_private;
1372 if (!BNXT_SINGLE_PF(bp))
1375 if (!bp->link_info->link_up)
1376 rc = bnxt_set_hwrm_link_config(bp, true);
1378 eth_dev->data->dev_link.link_status = 1;
1380 bnxt_print_link_info(eth_dev);
1384 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1386 struct bnxt *bp = eth_dev->data->dev_private;
1388 if (!BNXT_SINGLE_PF(bp))
1391 eth_dev->data->dev_link.link_status = 0;
1392 bnxt_set_hwrm_link_config(bp, false);
1393 bp->link_info->link_up = 0;
1398 static void bnxt_free_switch_domain(struct bnxt *bp)
1402 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)))
1405 rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1407 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1408 bp->switch_domain_id, rc);
1411 static void bnxt_ptp_get_current_time(void *arg)
1413 struct bnxt *bp = arg;
1414 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1417 rc = is_bnxt_in_error(bp);
1424 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1425 &ptp->current_time);
1427 rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1429 PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n");
1430 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1434 static int bnxt_schedule_ptp_alarm(struct bnxt *bp)
1436 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1439 if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED)
1442 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1443 &ptp->current_time);
1445 rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1449 static void bnxt_cancel_ptp_alarm(struct bnxt *bp)
1451 if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) {
1452 rte_eal_alarm_cancel(bnxt_ptp_get_current_time, (void *)bp);
1453 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1457 static void bnxt_ptp_stop(struct bnxt *bp)
1459 bnxt_cancel_ptp_alarm(bp);
1460 bp->flags2 &= ~BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1463 static int bnxt_ptp_start(struct bnxt *bp)
1467 rc = bnxt_schedule_ptp_alarm(bp);
1469 PMD_DRV_LOG(ERR, "Failed to schedule PTP alarm\n");
1471 bp->flags2 |= BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1472 bp->flags2 |= BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1478 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev)
1480 struct bnxt *bp = eth_dev->data->dev_private;
1481 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1482 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1483 struct rte_eth_link link;
1486 eth_dev->data->dev_started = 0;
1487 eth_dev->data->scattered_rx = 0;
1489 /* Prevent crashes when queues are still in use */
1490 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1491 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1493 bnxt_disable_int(bp);
1495 /* disable uio/vfio intr/eventfd mapping */
1496 rte_intr_disable(intr_handle);
1498 /* Stop the child representors for this device */
1499 ret = bnxt_rep_stop_all(bp);
1503 /* delete the bnxt ULP port details */
1504 bnxt_ulp_port_deinit(bp);
1506 bnxt_cancel_fw_health_check(bp);
1508 if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1509 bnxt_cancel_ptp_alarm(bp);
1511 /* Do not bring link down during reset recovery */
1512 if (!is_bnxt_in_error(bp)) {
1513 bnxt_dev_set_link_down_op(eth_dev);
1514 /* Wait for link to be reset */
1515 if (BNXT_SINGLE_PF(bp))
1517 /* clear the recorded link status */
1518 memset(&link, 0, sizeof(link));
1519 rte_eth_linkstatus_set(eth_dev, &link);
1522 /* Clean queue intr-vector mapping */
1523 rte_intr_efd_disable(intr_handle);
1524 if (intr_handle->intr_vec != NULL) {
1525 rte_free(intr_handle->intr_vec);
1526 intr_handle->intr_vec = NULL;
1529 bnxt_hwrm_port_clr_stats(bp);
1530 bnxt_free_tx_mbufs(bp);
1531 bnxt_free_rx_mbufs(bp);
1532 /* Process any remaining notifications in default completion queue */
1533 bnxt_int_handler(eth_dev);
1534 bnxt_shutdown_nic(bp);
1535 bnxt_hwrm_if_change(bp, false);
1537 bnxt_free_prev_ring_stats(bp);
1538 rte_free(bp->mark_table);
1539 bp->mark_table = NULL;
1541 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1542 bp->rx_cosq_cnt = 0;
1543 /* All filters are deleted on a port stop. */
1544 if (BNXT_FLOW_XSTATS_EN(bp))
1545 bp->flow_stat->flow_count = 0;
1550 /* Unload the driver, release resources */
1551 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1553 struct bnxt *bp = eth_dev->data->dev_private;
1555 pthread_mutex_lock(&bp->err_recovery_lock);
1556 if (bp->flags & BNXT_FLAG_FW_RESET) {
1558 "Adapter recovering from error..Please retry\n");
1559 pthread_mutex_unlock(&bp->err_recovery_lock);
1562 pthread_mutex_unlock(&bp->err_recovery_lock);
1564 return bnxt_dev_stop(eth_dev);
1567 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1569 struct bnxt *bp = eth_dev->data->dev_private;
1570 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1572 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1574 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1575 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1579 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1581 "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1582 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1585 rc = bnxt_hwrm_if_change(bp, true);
1586 if (rc == 0 || rc != -EAGAIN)
1589 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1590 } while (retry_cnt--);
1595 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1596 rc = bnxt_handle_if_change_status(bp);
1601 bnxt_enable_int(bp);
1603 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1605 rc = bnxt_start_nic(bp);
1609 rc = bnxt_alloc_prev_ring_stats(bp);
1613 eth_dev->data->dev_started = 1;
1615 bnxt_link_update_op(eth_dev, 1);
1617 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1618 vlan_mask |= ETH_VLAN_FILTER_MASK;
1619 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1620 vlan_mask |= ETH_VLAN_STRIP_MASK;
1621 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1625 /* Initialize bnxt ULP port details */
1626 rc = bnxt_ulp_port_init(bp);
1630 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1631 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1633 bnxt_schedule_fw_health_check(bp);
1635 if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1636 bnxt_schedule_ptp_alarm(bp);
1641 bnxt_dev_stop(eth_dev);
1646 bnxt_uninit_locks(struct bnxt *bp)
1648 pthread_mutex_destroy(&bp->flow_lock);
1649 pthread_mutex_destroy(&bp->def_cp_lock);
1650 pthread_mutex_destroy(&bp->health_check_lock);
1651 pthread_mutex_destroy(&bp->err_recovery_lock);
1653 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
1654 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
1658 static void bnxt_drv_uninit(struct bnxt *bp)
1660 bnxt_free_leds_info(bp);
1661 bnxt_free_cos_queues(bp);
1662 bnxt_free_link_info(bp);
1663 bnxt_free_parent_info(bp);
1664 bnxt_uninit_locks(bp);
1666 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1667 bp->tx_mem_zone = NULL;
1668 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1669 bp->rx_mem_zone = NULL;
1671 bnxt_free_vf_info(bp);
1672 bnxt_free_pf_info(bp);
1674 rte_free(bp->grp_info);
1675 bp->grp_info = NULL;
1678 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1680 struct bnxt *bp = eth_dev->data->dev_private;
1683 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1686 pthread_mutex_lock(&bp->err_recovery_lock);
1687 if (bp->flags & BNXT_FLAG_FW_RESET) {
1689 "Adapter recovering from error...Please retry\n");
1690 pthread_mutex_unlock(&bp->err_recovery_lock);
1693 pthread_mutex_unlock(&bp->err_recovery_lock);
1695 /* cancel the recovery handler before remove dev */
1696 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1697 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1698 bnxt_cancel_fc_thread(bp);
1700 if (eth_dev->data->dev_started)
1701 ret = bnxt_dev_stop(eth_dev);
1703 bnxt_uninit_resources(bp, false);
1705 bnxt_drv_uninit(bp);
1710 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1713 struct bnxt *bp = eth_dev->data->dev_private;
1714 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1715 struct bnxt_vnic_info *vnic;
1716 struct bnxt_filter_info *filter, *temp_filter;
1719 if (is_bnxt_in_error(bp))
1723 * Loop through all VNICs from the specified filter flow pools to
1724 * remove the corresponding MAC addr filter
1726 for (i = 0; i < bp->nr_vnics; i++) {
1727 if (!(pool_mask & (1ULL << i)))
1730 vnic = &bp->vnic_info[i];
1731 filter = STAILQ_FIRST(&vnic->filter);
1733 temp_filter = STAILQ_NEXT(filter, next);
1734 if (filter->mac_index == index) {
1735 STAILQ_REMOVE(&vnic->filter, filter,
1736 bnxt_filter_info, next);
1737 bnxt_hwrm_clear_l2_filter(bp, filter);
1738 bnxt_free_filter(bp, filter);
1740 filter = temp_filter;
1745 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1746 struct rte_ether_addr *mac_addr, uint32_t index,
1749 struct bnxt_filter_info *filter;
1752 /* Attach requested MAC address to the new l2_filter */
1753 STAILQ_FOREACH(filter, &vnic->filter, next) {
1754 if (filter->mac_index == index) {
1756 "MAC addr already existed for pool %d\n",
1762 filter = bnxt_alloc_filter(bp);
1764 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1768 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1769 * if the MAC that's been programmed now is a different one, then,
1770 * copy that addr to filter->l2_addr
1773 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1774 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1776 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1778 filter->mac_index = index;
1779 if (filter->mac_index == 0)
1780 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1782 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1784 bnxt_free_filter(bp, filter);
1790 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1791 struct rte_ether_addr *mac_addr,
1792 uint32_t index, uint32_t pool)
1794 struct bnxt *bp = eth_dev->data->dev_private;
1795 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1798 rc = is_bnxt_in_error(bp);
1802 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1803 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1808 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1812 /* Filter settings will get applied when port is started */
1813 if (!eth_dev->data->dev_started)
1816 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1821 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1824 struct bnxt *bp = eth_dev->data->dev_private;
1825 struct rte_eth_link new;
1826 int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1827 BNXT_MIN_LINK_WAIT_CNT;
1829 rc = is_bnxt_in_error(bp);
1833 memset(&new, 0, sizeof(new));
1835 if (bp->link_info == NULL)
1839 /* Retrieve link info from hardware */
1840 rc = bnxt_get_hwrm_link_config(bp, &new);
1842 new.link_speed = ETH_LINK_SPEED_100M;
1843 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1845 "Failed to retrieve link rc = 0x%x!\n", rc);
1849 if (!wait_to_complete || new.link_status)
1852 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1855 /* Only single function PF can bring phy down.
1856 * When port is stopped, report link down for VF/MH/NPAR functions.
1858 if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1859 memset(&new, 0, sizeof(new));
1862 /* Timed out or success */
1863 if (new.link_status != eth_dev->data->dev_link.link_status ||
1864 new.link_speed != eth_dev->data->dev_link.link_speed) {
1865 rte_eth_linkstatus_set(eth_dev, &new);
1866 bnxt_print_link_info(eth_dev);
1872 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1874 struct bnxt *bp = eth_dev->data->dev_private;
1875 struct bnxt_vnic_info *vnic;
1879 rc = is_bnxt_in_error(bp);
1883 /* Filter settings will get applied when port is started */
1884 if (!eth_dev->data->dev_started)
1887 if (bp->vnic_info == NULL)
1890 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1892 old_flags = vnic->flags;
1893 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1894 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1896 vnic->flags = old_flags;
1901 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1903 struct bnxt *bp = eth_dev->data->dev_private;
1904 struct bnxt_vnic_info *vnic;
1908 rc = is_bnxt_in_error(bp);
1912 /* Filter settings will get applied when port is started */
1913 if (!eth_dev->data->dev_started)
1916 if (bp->vnic_info == NULL)
1919 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1921 old_flags = vnic->flags;
1922 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1923 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1925 vnic->flags = old_flags;
1930 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1932 struct bnxt *bp = eth_dev->data->dev_private;
1933 struct bnxt_vnic_info *vnic;
1937 rc = is_bnxt_in_error(bp);
1941 /* Filter settings will get applied when port is started */
1942 if (!eth_dev->data->dev_started)
1945 if (bp->vnic_info == NULL)
1948 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1950 old_flags = vnic->flags;
1951 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1952 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1954 vnic->flags = old_flags;
1959 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1961 struct bnxt *bp = eth_dev->data->dev_private;
1962 struct bnxt_vnic_info *vnic;
1966 rc = is_bnxt_in_error(bp);
1970 /* Filter settings will get applied when port is started */
1971 if (!eth_dev->data->dev_started)
1974 if (bp->vnic_info == NULL)
1977 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1979 old_flags = vnic->flags;
1980 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1981 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1983 vnic->flags = old_flags;
1988 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1989 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1991 if (qid >= bp->rx_nr_rings)
1994 return bp->eth_dev->data->rx_queues[qid];
1997 /* Return rxq corresponding to a given rss table ring/group ID. */
1998 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
2000 struct bnxt_rx_queue *rxq;
2003 if (!BNXT_HAS_RING_GRPS(bp)) {
2004 for (i = 0; i < bp->rx_nr_rings; i++) {
2005 rxq = bp->eth_dev->data->rx_queues[i];
2006 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
2010 for (i = 0; i < bp->rx_nr_rings; i++) {
2011 if (bp->grp_info[i].fw_grp_id == fwr)
2016 return INVALID_HW_RING_ID;
2019 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
2020 struct rte_eth_rss_reta_entry64 *reta_conf,
2023 struct bnxt *bp = eth_dev->data->dev_private;
2024 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2025 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2026 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
2030 rc = is_bnxt_in_error(bp);
2034 if (!vnic->rss_table)
2037 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
2040 if (reta_size != tbl_size) {
2041 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2042 "(%d) must equal the size supported by the hardware "
2043 "(%d)\n", reta_size, tbl_size);
2047 for (i = 0; i < reta_size; i++) {
2048 struct bnxt_rx_queue *rxq;
2050 idx = i / RTE_RETA_GROUP_SIZE;
2051 sft = i % RTE_RETA_GROUP_SIZE;
2053 if (!(reta_conf[idx].mask & (1ULL << sft)))
2056 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
2058 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
2062 if (BNXT_CHIP_P5(bp)) {
2063 vnic->rss_table[i * 2] =
2064 rxq->rx_ring->rx_ring_struct->fw_ring_id;
2065 vnic->rss_table[i * 2 + 1] =
2066 rxq->cp_ring->cp_ring_struct->fw_ring_id;
2068 vnic->rss_table[i] =
2069 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
2073 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2077 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
2078 struct rte_eth_rss_reta_entry64 *reta_conf,
2081 struct bnxt *bp = eth_dev->data->dev_private;
2082 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2083 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
2084 uint16_t idx, sft, i;
2087 rc = is_bnxt_in_error(bp);
2093 if (!vnic->rss_table)
2096 if (reta_size != tbl_size) {
2097 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2098 "(%d) must equal the size supported by the hardware "
2099 "(%d)\n", reta_size, tbl_size);
2103 for (idx = 0, i = 0; i < reta_size; i++) {
2104 idx = i / RTE_RETA_GROUP_SIZE;
2105 sft = i % RTE_RETA_GROUP_SIZE;
2107 if (reta_conf[idx].mask & (1ULL << sft)) {
2110 if (BNXT_CHIP_P5(bp))
2111 qid = bnxt_rss_to_qid(bp,
2112 vnic->rss_table[i * 2]);
2114 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
2116 if (qid == INVALID_HW_RING_ID) {
2117 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
2120 reta_conf[idx].reta[sft] = qid;
2127 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
2128 struct rte_eth_rss_conf *rss_conf)
2130 struct bnxt *bp = eth_dev->data->dev_private;
2131 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2132 struct bnxt_vnic_info *vnic;
2135 rc = is_bnxt_in_error(bp);
2140 * If RSS enablement were different than dev_configure,
2141 * then return -EINVAL
2143 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
2144 if (!rss_conf->rss_hf)
2145 PMD_DRV_LOG(ERR, "Hash type NONE\n");
2147 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
2151 bp->flags |= BNXT_FLAG_UPDATE_HASH;
2152 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf,
2156 /* Update the default RSS VNIC(s) */
2157 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2158 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
2160 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
2161 ETH_RSS_LEVEL(rss_conf->rss_hf));
2164 * If hashkey is not specified, use the previously configured
2167 if (!rss_conf->rss_key)
2170 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
2172 "Invalid hashkey length, should be %d bytes\n",
2176 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
2179 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2183 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
2184 struct rte_eth_rss_conf *rss_conf)
2186 struct bnxt *bp = eth_dev->data->dev_private;
2187 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2189 uint32_t hash_types;
2191 rc = is_bnxt_in_error(bp);
2195 /* RSS configuration is the same for all VNICs */
2196 if (vnic && vnic->rss_hash_key) {
2197 if (rss_conf->rss_key) {
2198 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
2199 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
2200 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
2203 hash_types = vnic->hash_type;
2204 rss_conf->rss_hf = 0;
2205 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
2206 rss_conf->rss_hf |= ETH_RSS_IPV4;
2207 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
2209 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
2210 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2212 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
2214 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
2215 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2217 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
2219 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
2220 rss_conf->rss_hf |= ETH_RSS_IPV6;
2221 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
2223 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
2224 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2226 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
2228 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
2229 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2231 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2235 bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2239 "Unknown RSS config from firmware (%08x), RSS disabled",
2244 rss_conf->rss_hf = 0;
2249 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2250 struct rte_eth_fc_conf *fc_conf)
2252 struct bnxt *bp = dev->data->dev_private;
2253 struct rte_eth_link link_info;
2256 rc = is_bnxt_in_error(bp);
2260 rc = bnxt_get_hwrm_link_config(bp, &link_info);
2264 memset(fc_conf, 0, sizeof(*fc_conf));
2265 if (bp->link_info->auto_pause)
2266 fc_conf->autoneg = 1;
2267 switch (bp->link_info->pause) {
2269 fc_conf->mode = RTE_FC_NONE;
2271 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2272 fc_conf->mode = RTE_FC_TX_PAUSE;
2274 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2275 fc_conf->mode = RTE_FC_RX_PAUSE;
2277 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2278 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2279 fc_conf->mode = RTE_FC_FULL;
2285 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2286 struct rte_eth_fc_conf *fc_conf)
2288 struct bnxt *bp = dev->data->dev_private;
2291 rc = is_bnxt_in_error(bp);
2295 if (!BNXT_SINGLE_PF(bp)) {
2297 "Flow Control Settings cannot be modified on VF or on shared PF\n");
2301 switch (fc_conf->mode) {
2303 bp->link_info->auto_pause = 0;
2304 bp->link_info->force_pause = 0;
2306 case RTE_FC_RX_PAUSE:
2307 if (fc_conf->autoneg) {
2308 bp->link_info->auto_pause =
2309 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2310 bp->link_info->force_pause = 0;
2312 bp->link_info->auto_pause = 0;
2313 bp->link_info->force_pause =
2314 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2317 case RTE_FC_TX_PAUSE:
2318 if (fc_conf->autoneg) {
2319 bp->link_info->auto_pause =
2320 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2321 bp->link_info->force_pause = 0;
2323 bp->link_info->auto_pause = 0;
2324 bp->link_info->force_pause =
2325 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2329 if (fc_conf->autoneg) {
2330 bp->link_info->auto_pause =
2331 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2332 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2333 bp->link_info->force_pause = 0;
2335 bp->link_info->auto_pause = 0;
2336 bp->link_info->force_pause =
2337 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2338 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2342 return bnxt_set_hwrm_link_config(bp, true);
2345 /* Add UDP tunneling port */
2347 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2348 struct rte_eth_udp_tunnel *udp_tunnel)
2350 struct bnxt *bp = eth_dev->data->dev_private;
2351 uint16_t tunnel_type = 0;
2354 rc = is_bnxt_in_error(bp);
2358 switch (udp_tunnel->prot_type) {
2359 case RTE_TUNNEL_TYPE_VXLAN:
2360 if (bp->vxlan_port_cnt) {
2361 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2362 udp_tunnel->udp_port);
2363 if (bp->vxlan_port != udp_tunnel->udp_port) {
2364 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2367 bp->vxlan_port_cnt++;
2371 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2373 case RTE_TUNNEL_TYPE_GENEVE:
2374 if (bp->geneve_port_cnt) {
2375 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2376 udp_tunnel->udp_port);
2377 if (bp->geneve_port != udp_tunnel->udp_port) {
2378 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2381 bp->geneve_port_cnt++;
2385 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2388 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2391 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2398 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN)
2399 bp->vxlan_port_cnt++;
2402 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE)
2403 bp->geneve_port_cnt++;
2409 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2410 struct rte_eth_udp_tunnel *udp_tunnel)
2412 struct bnxt *bp = eth_dev->data->dev_private;
2413 uint16_t tunnel_type = 0;
2417 rc = is_bnxt_in_error(bp);
2421 switch (udp_tunnel->prot_type) {
2422 case RTE_TUNNEL_TYPE_VXLAN:
2423 if (!bp->vxlan_port_cnt) {
2424 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2427 if (bp->vxlan_port != udp_tunnel->udp_port) {
2428 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2429 udp_tunnel->udp_port, bp->vxlan_port);
2432 if (--bp->vxlan_port_cnt)
2436 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2437 port = bp->vxlan_fw_dst_port_id;
2439 case RTE_TUNNEL_TYPE_GENEVE:
2440 if (!bp->geneve_port_cnt) {
2441 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2444 if (bp->geneve_port != udp_tunnel->udp_port) {
2445 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2446 udp_tunnel->udp_port, bp->geneve_port);
2449 if (--bp->geneve_port_cnt)
2453 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2454 port = bp->geneve_fw_dst_port_id;
2457 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2461 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2465 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2467 struct bnxt_filter_info *filter;
2468 struct bnxt_vnic_info *vnic;
2470 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2472 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2473 filter = STAILQ_FIRST(&vnic->filter);
2475 /* Search for this matching MAC+VLAN filter */
2476 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2477 /* Delete the filter */
2478 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2481 STAILQ_REMOVE(&vnic->filter, filter,
2482 bnxt_filter_info, next);
2483 bnxt_free_filter(bp, filter);
2485 "Deleted vlan filter for %d\n",
2489 filter = STAILQ_NEXT(filter, next);
2494 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2496 struct bnxt_filter_info *filter;
2497 struct bnxt_vnic_info *vnic;
2499 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2500 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2501 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2503 /* Implementation notes on the use of VNIC in this command:
2505 * By default, these filters belong to default vnic for the function.
2506 * Once these filters are set up, only destination VNIC can be modified.
2507 * If the destination VNIC is not specified in this command,
2508 * then the HWRM shall only create an l2 context id.
2511 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2512 filter = STAILQ_FIRST(&vnic->filter);
2513 /* Check if the VLAN has already been added */
2515 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2518 filter = STAILQ_NEXT(filter, next);
2521 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2522 * command to create MAC+VLAN filter with the right flags, enables set.
2524 filter = bnxt_alloc_filter(bp);
2527 "MAC/VLAN filter alloc failed\n");
2530 /* MAC + VLAN ID filter */
2531 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2532 * untagged packets are received
2534 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2535 * packets and only the programmed vlan's packets are received
2537 filter->l2_ivlan = vlan_id;
2538 filter->l2_ivlan_mask = 0x0FFF;
2539 filter->enables |= en;
2540 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2542 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2544 /* Free the newly allocated filter as we were
2545 * not able to create the filter in hardware.
2547 bnxt_free_filter(bp, filter);
2551 filter->mac_index = 0;
2552 /* Add this new filter to the list */
2554 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2556 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2559 "Added Vlan filter for %d\n", vlan_id);
2563 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2564 uint16_t vlan_id, int on)
2566 struct bnxt *bp = eth_dev->data->dev_private;
2569 rc = is_bnxt_in_error(bp);
2573 if (!eth_dev->data->dev_started) {
2574 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2578 /* These operations apply to ALL existing MAC/VLAN filters */
2580 return bnxt_add_vlan_filter(bp, vlan_id);
2582 return bnxt_del_vlan_filter(bp, vlan_id);
2585 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2586 struct bnxt_vnic_info *vnic)
2588 struct bnxt_filter_info *filter;
2591 filter = STAILQ_FIRST(&vnic->filter);
2593 if (filter->mac_index == 0 &&
2594 !memcmp(filter->l2_addr, bp->mac_addr,
2595 RTE_ETHER_ADDR_LEN)) {
2596 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2598 STAILQ_REMOVE(&vnic->filter, filter,
2599 bnxt_filter_info, next);
2600 bnxt_free_filter(bp, filter);
2604 filter = STAILQ_NEXT(filter, next);
2610 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2612 struct bnxt_vnic_info *vnic;
2616 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2617 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2618 /* Remove any VLAN filters programmed */
2619 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2620 bnxt_del_vlan_filter(bp, i);
2622 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2626 /* Default filter will allow packets that match the
2627 * dest mac. So, it has to be deleted, otherwise, we
2628 * will endup receiving vlan packets for which the
2629 * filter is not programmed, when hw-vlan-filter
2630 * configuration is ON
2632 bnxt_del_dflt_mac_filter(bp, vnic);
2633 /* This filter will allow only untagged packets */
2634 bnxt_add_vlan_filter(bp, 0);
2636 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2637 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2642 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2644 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2648 /* Destroy vnic filters and vnic */
2649 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2650 DEV_RX_OFFLOAD_VLAN_FILTER) {
2651 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2652 bnxt_del_vlan_filter(bp, i);
2654 bnxt_del_dflt_mac_filter(bp, vnic);
2656 rc = bnxt_hwrm_vnic_ctx_free(bp, vnic);
2660 rc = bnxt_hwrm_vnic_free(bp, vnic);
2664 rte_free(vnic->fw_grp_ids);
2665 vnic->fw_grp_ids = NULL;
2667 vnic->rx_queue_cnt = 0;
2673 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2675 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2678 /* Destroy, recreate and reconfigure the default vnic */
2679 rc = bnxt_free_one_vnic(bp, 0);
2683 /* default vnic 0 */
2684 rc = bnxt_setup_one_vnic(bp, 0);
2688 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2689 DEV_RX_OFFLOAD_VLAN_FILTER) {
2690 rc = bnxt_add_vlan_filter(bp, 0);
2693 rc = bnxt_restore_vlan_filters(bp);
2697 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2702 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2706 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2707 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2713 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2715 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2716 struct bnxt *bp = dev->data->dev_private;
2719 rc = is_bnxt_in_error(bp);
2723 /* Filter settings will get applied when port is started */
2724 if (!dev->data->dev_started)
2727 if (mask & ETH_VLAN_FILTER_MASK) {
2728 /* Enable or disable VLAN filtering */
2729 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2734 if (mask & ETH_VLAN_STRIP_MASK) {
2735 /* Enable or disable VLAN stripping */
2736 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2741 if (mask & ETH_VLAN_EXTEND_MASK) {
2742 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2743 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2745 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2752 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2755 struct bnxt *bp = dev->data->dev_private;
2756 int qinq = dev->data->dev_conf.rxmode.offloads &
2757 DEV_RX_OFFLOAD_VLAN_EXTEND;
2759 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2760 vlan_type != ETH_VLAN_TYPE_OUTER) {
2762 "Unsupported vlan type.");
2767 "QinQ not enabled. Needs to be ON as we can "
2768 "accelerate only outer vlan\n");
2772 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2774 case RTE_ETHER_TYPE_QINQ:
2776 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2778 case RTE_ETHER_TYPE_VLAN:
2780 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2782 case RTE_ETHER_TYPE_QINQ1:
2784 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2786 case RTE_ETHER_TYPE_QINQ2:
2788 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2790 case RTE_ETHER_TYPE_QINQ3:
2792 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2795 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2798 bp->outer_tpid_bd |= tpid;
2799 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2800 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2802 "Can accelerate only outer vlan in QinQ\n");
2810 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2811 struct rte_ether_addr *addr)
2813 struct bnxt *bp = dev->data->dev_private;
2814 /* Default Filter is tied to VNIC 0 */
2815 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2818 rc = is_bnxt_in_error(bp);
2822 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2825 if (rte_is_zero_ether_addr(addr))
2828 /* Filter settings will get applied when port is started */
2829 if (!dev->data->dev_started)
2832 /* Check if the requested MAC is already added */
2833 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2836 /* Destroy filter and re-create it */
2837 bnxt_del_dflt_mac_filter(bp, vnic);
2839 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2840 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2841 /* This filter will allow only untagged packets */
2842 rc = bnxt_add_vlan_filter(bp, 0);
2844 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2847 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2852 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2853 struct rte_ether_addr *mc_addr_set,
2854 uint32_t nb_mc_addr)
2856 struct bnxt *bp = eth_dev->data->dev_private;
2857 char *mc_addr_list = (char *)mc_addr_set;
2858 struct bnxt_vnic_info *vnic;
2859 uint32_t off = 0, i = 0;
2862 rc = is_bnxt_in_error(bp);
2866 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2868 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2869 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2873 /* TODO Check for Duplicate mcast addresses */
2874 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2875 for (i = 0; i < nb_mc_addr; i++) {
2876 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2877 RTE_ETHER_ADDR_LEN);
2878 off += RTE_ETHER_ADDR_LEN;
2881 vnic->mc_addr_cnt = i;
2882 if (vnic->mc_addr_cnt)
2883 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2885 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2888 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2892 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2894 struct bnxt *bp = dev->data->dev_private;
2895 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2896 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2897 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2898 uint8_t fw_rsvd = bp->fw_ver & 0xff;
2901 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2902 fw_major, fw_minor, fw_updt, fw_rsvd);
2906 ret += 1; /* add the size of '\0' */
2907 if (fw_size < (size_t)ret)
2914 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2915 struct rte_eth_rxq_info *qinfo)
2917 struct bnxt *bp = dev->data->dev_private;
2918 struct bnxt_rx_queue *rxq;
2920 if (is_bnxt_in_error(bp))
2923 rxq = dev->data->rx_queues[queue_id];
2925 qinfo->mp = rxq->mb_pool;
2926 qinfo->scattered_rx = dev->data->scattered_rx;
2927 qinfo->nb_desc = rxq->nb_rx_desc;
2929 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2930 qinfo->conf.rx_drop_en = rxq->drop_en;
2931 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2932 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2936 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2937 struct rte_eth_txq_info *qinfo)
2939 struct bnxt *bp = dev->data->dev_private;
2940 struct bnxt_tx_queue *txq;
2942 if (is_bnxt_in_error(bp))
2945 txq = dev->data->tx_queues[queue_id];
2947 qinfo->nb_desc = txq->nb_tx_desc;
2949 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2950 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2951 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2953 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2954 qinfo->conf.tx_rs_thresh = 0;
2955 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2956 qinfo->conf.offloads = txq->offloads;
2959 static const struct {
2960 eth_rx_burst_t pkt_burst;
2962 } bnxt_rx_burst_info[] = {
2963 {bnxt_recv_pkts, "Scalar"},
2964 #if defined(RTE_ARCH_X86)
2965 {bnxt_recv_pkts_vec, "Vector SSE"},
2967 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2968 {bnxt_recv_pkts_vec_avx2, "Vector AVX2"},
2970 #if defined(RTE_ARCH_ARM64)
2971 {bnxt_recv_pkts_vec, "Vector Neon"},
2976 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2977 struct rte_eth_burst_mode *mode)
2979 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2982 for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2983 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2984 snprintf(mode->info, sizeof(mode->info), "%s",
2985 bnxt_rx_burst_info[i].info);
2993 static const struct {
2994 eth_tx_burst_t pkt_burst;
2996 } bnxt_tx_burst_info[] = {
2997 {bnxt_xmit_pkts, "Scalar"},
2998 #if defined(RTE_ARCH_X86)
2999 {bnxt_xmit_pkts_vec, "Vector SSE"},
3001 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
3002 {bnxt_xmit_pkts_vec_avx2, "Vector AVX2"},
3004 #if defined(RTE_ARCH_ARM64)
3005 {bnxt_xmit_pkts_vec, "Vector Neon"},
3010 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3011 struct rte_eth_burst_mode *mode)
3013 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3016 for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
3017 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
3018 snprintf(mode->info, sizeof(mode->info), "%s",
3019 bnxt_tx_burst_info[i].info);
3027 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
3029 uint32_t overhead = BNXT_MAX_PKT_LEN - BNXT_MAX_MTU;
3030 struct bnxt *bp = eth_dev->data->dev_private;
3031 uint32_t new_pkt_size;
3035 rc = is_bnxt_in_error(bp);
3039 /* Exit if receive queues are not configured yet */
3040 if (!eth_dev->data->nb_rx_queues)
3043 new_pkt_size = new_mtu + overhead;
3046 * Disallow any MTU change that would require scattered receive support
3047 * if it is not already enabled.
3049 if (eth_dev->data->dev_started &&
3050 !eth_dev->data->scattered_rx &&
3052 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
3054 "MTU change would require scattered rx support. ");
3055 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
3059 if (new_mtu > RTE_ETHER_MTU)
3060 bp->flags |= BNXT_FLAG_JUMBO;
3062 bp->flags &= ~BNXT_FLAG_JUMBO;
3064 /* Is there a change in mtu setting? */
3065 if (eth_dev->data->mtu == new_mtu)
3068 for (i = 0; i < bp->nr_vnics; i++) {
3069 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3072 vnic->mru = BNXT_VNIC_MRU(new_mtu);
3073 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
3077 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
3078 size -= RTE_PKTMBUF_HEADROOM;
3080 if (size < new_mtu) {
3081 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
3087 if (bnxt_hwrm_config_host_mtu(bp))
3088 PMD_DRV_LOG(WARNING, "Failed to configure host MTU\n");
3090 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
3096 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
3098 struct bnxt *bp = dev->data->dev_private;
3099 uint16_t vlan = bp->vlan;
3102 rc = is_bnxt_in_error(bp);
3106 if (!BNXT_SINGLE_PF(bp)) {
3107 PMD_DRV_LOG(ERR, "PVID cannot be modified on VF or on shared PF\n");
3110 bp->vlan = on ? pvid : 0;
3112 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
3119 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
3121 struct bnxt *bp = dev->data->dev_private;
3124 rc = is_bnxt_in_error(bp);
3128 return bnxt_hwrm_port_led_cfg(bp, true);
3132 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
3134 struct bnxt *bp = dev->data->dev_private;
3137 rc = is_bnxt_in_error(bp);
3141 return bnxt_hwrm_port_led_cfg(bp, false);
3145 bnxt_rx_queue_count_op(void *rx_queue)
3148 struct bnxt_cp_ring_info *cpr;
3149 uint32_t desc = 0, raw_cons, cp_ring_size;
3150 struct bnxt_rx_queue *rxq;
3151 struct rx_pkt_cmpl *rxcmp;
3157 rc = is_bnxt_in_error(bp);
3162 raw_cons = cpr->cp_raw_cons;
3163 cp_ring_size = cpr->cp_ring_struct->ring_size;
3166 uint32_t agg_cnt, cons, cmpl_type;
3168 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3169 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3171 if (!bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size))
3174 cmpl_type = CMP_TYPE(rxcmp);
3176 switch (cmpl_type) {
3177 case CMPL_BASE_TYPE_RX_L2:
3178 case CMPL_BASE_TYPE_RX_L2_V2:
3179 agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3180 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3184 case CMPL_BASE_TYPE_RX_TPA_END:
3185 if (BNXT_CHIP_P5(rxq->bp)) {
3186 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3188 p5_tpa_end = (void *)rxcmp;
3189 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3191 struct rx_tpa_end_cmpl *tpa_end;
3193 tpa_end = (void *)rxcmp;
3194 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3197 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3202 raw_cons += CMP_LEN(cmpl_type);
3210 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
3212 struct bnxt_rx_queue *rxq = rx_queue;
3213 struct bnxt_cp_ring_info *cpr;
3214 struct bnxt_rx_ring_info *rxr;
3215 uint32_t desc, raw_cons, cp_ring_size;
3216 struct bnxt *bp = rxq->bp;
3217 struct rx_pkt_cmpl *rxcmp;
3220 rc = is_bnxt_in_error(bp);
3224 if (offset >= rxq->nb_rx_desc)
3229 cp_ring_size = cpr->cp_ring_struct->ring_size;
3232 * For the vector receive case, the completion at the requested
3233 * offset can be indexed directly.
3235 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
3236 if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) {
3237 struct rx_pkt_cmpl *rxcmp;
3240 /* Check status of completion descriptor. */
3241 raw_cons = cpr->cp_raw_cons +
3242 offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2);
3243 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3244 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3246 if (bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size))
3247 return RTE_ETH_RX_DESC_DONE;
3249 /* Check whether rx desc has an mbuf attached. */
3250 cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2);
3251 if (cons >= rxq->rxrearm_start &&
3252 cons < rxq->rxrearm_start + rxq->rxrearm_nb) {
3253 return RTE_ETH_RX_DESC_UNAVAIL;
3256 return RTE_ETH_RX_DESC_AVAIL;
3261 * For the non-vector receive case, scan the completion ring to
3262 * locate the completion descriptor for the requested offset.
3264 raw_cons = cpr->cp_raw_cons;
3267 uint32_t agg_cnt, cons, cmpl_type;
3269 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3270 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3272 if (!bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size))
3275 cmpl_type = CMP_TYPE(rxcmp);
3277 switch (cmpl_type) {
3278 case CMPL_BASE_TYPE_RX_L2:
3279 case CMPL_BASE_TYPE_RX_L2_V2:
3280 if (desc == offset) {
3281 cons = rxcmp->opaque;
3282 if (rxr->rx_buf_ring[cons])
3283 return RTE_ETH_RX_DESC_DONE;
3285 return RTE_ETH_RX_DESC_UNAVAIL;
3287 agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3288 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3292 case CMPL_BASE_TYPE_RX_TPA_END:
3294 return RTE_ETH_RX_DESC_DONE;
3296 if (BNXT_CHIP_P5(rxq->bp)) {
3297 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3299 p5_tpa_end = (void *)rxcmp;
3300 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3302 struct rx_tpa_end_cmpl *tpa_end;
3304 tpa_end = (void *)rxcmp;
3305 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3308 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3313 raw_cons += CMP_LEN(cmpl_type);
3317 return RTE_ETH_RX_DESC_AVAIL;
3321 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
3323 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
3324 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
3325 uint32_t ring_mask, raw_cons, nb_tx_pkts = 0;
3326 struct cmpl_base *cp_desc_ring;
3329 rc = is_bnxt_in_error(txq->bp);
3333 if (offset >= txq->nb_tx_desc)
3336 /* Return "desc done" if descriptor is available for use. */
3337 if (bnxt_tx_bds_in_hw(txq) <= offset)
3338 return RTE_ETH_TX_DESC_DONE;
3340 raw_cons = cpr->cp_raw_cons;
3341 cp_desc_ring = cpr->cp_desc_ring;
3342 ring_mask = cpr->cp_ring_struct->ring_mask;
3344 /* Check to see if hw has posted a completion for the descriptor. */
3346 struct tx_cmpl *txcmp;
3349 cons = RING_CMPL(ring_mask, raw_cons);
3350 txcmp = (struct tx_cmpl *)&cp_desc_ring[cons];
3352 if (!bnxt_cpr_cmp_valid(txcmp, raw_cons, ring_mask + 1))
3355 if (CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2)
3356 nb_tx_pkts += rte_le_to_cpu_32(txcmp->opaque);
3358 if (nb_tx_pkts > offset)
3359 return RTE_ETH_TX_DESC_DONE;
3361 raw_cons = NEXT_RAW_CMP(raw_cons);
3364 /* Descriptor is pending transmit, not yet completed by hardware. */
3365 return RTE_ETH_TX_DESC_FULL;
3369 bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
3370 const struct rte_flow_ops **ops)
3372 struct bnxt *bp = dev->data->dev_private;
3378 if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3379 struct bnxt_representor *vfr = dev->data->dev_private;
3380 bp = vfr->parent_dev->data->dev_private;
3381 /* parent is deleted while children are still valid */
3383 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error\n",
3384 dev->data->port_id);
3389 ret = is_bnxt_in_error(bp);
3393 /* PMD supports thread-safe flow operations. rte_flow API
3394 * functions can avoid mutex for multi-thread safety.
3396 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3398 if (BNXT_TRUFLOW_EN(bp))
3399 *ops = &bnxt_ulp_rte_flow_ops;
3401 *ops = &bnxt_flow_ops;
3406 static const uint32_t *
3407 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3409 static const uint32_t ptypes[] = {
3410 RTE_PTYPE_L2_ETHER_VLAN,
3411 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3412 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3416 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3417 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3418 RTE_PTYPE_INNER_L4_ICMP,
3419 RTE_PTYPE_INNER_L4_TCP,
3420 RTE_PTYPE_INNER_L4_UDP,
3424 if (!dev->rx_pkt_burst)
3430 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3433 uint32_t reg_base = *reg_arr & 0xfffff000;
3437 for (i = 0; i < count; i++) {
3438 if ((reg_arr[i] & 0xfffff000) != reg_base)
3441 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3442 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3446 static int bnxt_map_ptp_regs(struct bnxt *bp)
3448 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3452 reg_arr = ptp->rx_regs;
3453 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3457 reg_arr = ptp->tx_regs;
3458 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3462 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3463 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3465 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3466 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3471 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3473 rte_write32(0, (uint8_t *)bp->bar0 +
3474 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3475 rte_write32(0, (uint8_t *)bp->bar0 +
3476 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3479 static uint64_t bnxt_cc_read(struct bnxt *bp)
3483 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3484 BNXT_GRCPF_REG_SYNC_TIME));
3485 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3486 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3490 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3492 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3495 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3496 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3497 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3500 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3501 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3502 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3503 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3504 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3505 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3506 rte_read32((uint8_t *)bp->bar0 + ptp->tx_mapped_regs[BNXT_PTP_TX_SEQ]);
3511 static int bnxt_clr_rx_ts(struct bnxt *bp, uint64_t *last_ts)
3513 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3514 struct bnxt_pf_info *pf = bp->pf;
3519 if (!ptp || (bp->flags & BNXT_FLAG_CHIP_P5))
3522 port_id = pf->port_id;
3523 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3524 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3525 while ((fifo & BNXT_PTP_RX_FIFO_PENDING) && (i < BNXT_PTP_RX_PND_CNT)) {
3526 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3527 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3528 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3529 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3530 *last_ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3531 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3532 *last_ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3533 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3537 if (i >= BNXT_PTP_RX_PND_CNT)
3543 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3545 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3546 struct bnxt_pf_info *pf = bp->pf;
3550 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3551 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3552 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3555 port_id = pf->port_id;
3556 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3557 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3559 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3560 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3561 if (fifo & BNXT_PTP_RX_FIFO_PENDING)
3562 return bnxt_clr_rx_ts(bp, ts);
3564 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3565 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3566 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3567 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3573 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3576 struct bnxt *bp = dev->data->dev_private;
3577 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3582 ns = rte_timespec_to_ns(ts);
3583 /* Set the timecounters to a new value. */
3585 ptp->tx_tstamp_tc.nsec = ns;
3586 ptp->rx_tstamp_tc.nsec = ns;
3592 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3594 struct bnxt *bp = dev->data->dev_private;
3595 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3596 uint64_t ns, systime_cycles = 0;
3602 if (BNXT_CHIP_P5(bp))
3603 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3606 systime_cycles = bnxt_cc_read(bp);
3608 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3609 *ts = rte_ns_to_timespec(ns);
3614 bnxt_timesync_enable(struct rte_eth_dev *dev)
3616 struct bnxt *bp = dev->data->dev_private;
3617 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3625 ptp->tx_tstamp_en = 1;
3626 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3628 rc = bnxt_hwrm_ptp_cfg(bp);
3632 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3633 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3634 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3636 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3637 ptp->tc.cc_shift = shift;
3638 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3640 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3641 ptp->rx_tstamp_tc.cc_shift = shift;
3642 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3644 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3645 ptp->tx_tstamp_tc.cc_shift = shift;
3646 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3648 if (!BNXT_CHIP_P5(bp))
3649 bnxt_map_ptp_regs(bp);
3651 rc = bnxt_ptp_start(bp);
3657 bnxt_timesync_disable(struct rte_eth_dev *dev)
3659 struct bnxt *bp = dev->data->dev_private;
3660 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3666 ptp->tx_tstamp_en = 0;
3669 bnxt_hwrm_ptp_cfg(bp);
3671 if (!BNXT_CHIP_P5(bp))
3672 bnxt_unmap_ptp_regs(bp);
3680 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3681 struct timespec *timestamp,
3682 uint32_t flags __rte_unused)
3684 struct bnxt *bp = dev->data->dev_private;
3685 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3686 uint64_t rx_tstamp_cycles = 0;
3692 if (BNXT_CHIP_P5(bp))
3693 rx_tstamp_cycles = ptp->rx_timestamp;
3695 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3697 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3698 *timestamp = rte_ns_to_timespec(ns);
3703 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3704 struct timespec *timestamp)
3706 struct bnxt *bp = dev->data->dev_private;
3707 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3708 uint64_t tx_tstamp_cycles = 0;
3715 if (BNXT_CHIP_P5(bp))
3716 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3719 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3721 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3722 *timestamp = rte_ns_to_timespec(ns);
3728 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3730 struct bnxt *bp = dev->data->dev_private;
3731 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3736 ptp->tc.nsec += delta;
3737 ptp->tx_tstamp_tc.nsec += delta;
3738 ptp->rx_tstamp_tc.nsec += delta;
3744 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3746 struct bnxt *bp = dev->data->dev_private;
3748 uint32_t dir_entries;
3749 uint32_t entry_length;
3751 rc = is_bnxt_in_error(bp);
3755 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3756 bp->pdev->addr.domain, bp->pdev->addr.bus,
3757 bp->pdev->addr.devid, bp->pdev->addr.function);
3759 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3763 return dir_entries * entry_length;
3767 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3768 struct rte_dev_eeprom_info *in_eeprom)
3770 struct bnxt *bp = dev->data->dev_private;
3775 rc = is_bnxt_in_error(bp);
3779 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3780 bp->pdev->addr.domain, bp->pdev->addr.bus,
3781 bp->pdev->addr.devid, bp->pdev->addr.function,
3782 in_eeprom->offset, in_eeprom->length);
3784 if (in_eeprom->offset == 0) /* special offset value to get directory */
3785 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3788 index = in_eeprom->offset >> 24;
3789 offset = in_eeprom->offset & 0xffffff;
3792 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3793 in_eeprom->length, in_eeprom->data);
3798 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3801 case BNX_DIR_TYPE_CHIMP_PATCH:
3802 case BNX_DIR_TYPE_BOOTCODE:
3803 case BNX_DIR_TYPE_BOOTCODE_2:
3804 case BNX_DIR_TYPE_APE_FW:
3805 case BNX_DIR_TYPE_APE_PATCH:
3806 case BNX_DIR_TYPE_KONG_FW:
3807 case BNX_DIR_TYPE_KONG_PATCH:
3808 case BNX_DIR_TYPE_BONO_FW:
3809 case BNX_DIR_TYPE_BONO_PATCH:
3817 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3820 case BNX_DIR_TYPE_AVS:
3821 case BNX_DIR_TYPE_EXP_ROM_MBA:
3822 case BNX_DIR_TYPE_PCIE:
3823 case BNX_DIR_TYPE_TSCF_UCODE:
3824 case BNX_DIR_TYPE_EXT_PHY:
3825 case BNX_DIR_TYPE_CCM:
3826 case BNX_DIR_TYPE_ISCSI_BOOT:
3827 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3828 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3836 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3838 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3839 bnxt_dir_type_is_other_exec_format(dir_type);
3843 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3844 struct rte_dev_eeprom_info *in_eeprom)
3846 struct bnxt *bp = dev->data->dev_private;
3847 uint8_t index, dir_op;
3848 uint16_t type, ext, ordinal, attr;
3851 rc = is_bnxt_in_error(bp);
3855 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3856 bp->pdev->addr.domain, bp->pdev->addr.bus,
3857 bp->pdev->addr.devid, bp->pdev->addr.function,
3858 in_eeprom->offset, in_eeprom->length);
3861 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3865 type = in_eeprom->magic >> 16;
3867 if (type == 0xffff) { /* special value for directory operations */
3868 index = in_eeprom->magic & 0xff;
3869 dir_op = in_eeprom->magic >> 8;
3873 case 0x0e: /* erase */
3874 if (in_eeprom->offset != ~in_eeprom->magic)
3876 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3882 /* Create or re-write an NVM item: */
3883 if (bnxt_dir_type_is_executable(type) == true)
3885 ext = in_eeprom->magic & 0xffff;
3886 ordinal = in_eeprom->offset >> 16;
3887 attr = in_eeprom->offset & 0xffff;
3889 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3890 in_eeprom->data, in_eeprom->length);
3893 static int bnxt_get_module_info(struct rte_eth_dev *dev,
3894 struct rte_eth_dev_module_info *modinfo)
3896 uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1];
3897 struct bnxt *bp = dev->data->dev_private;
3900 /* No point in going further if phy status indicates
3901 * module is not inserted or if it is powered down or
3902 * if it is of type 10GBase-T
3904 if (bp->link_info->module_status >
3905 HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG) {
3906 PMD_DRV_LOG(NOTICE, "Port %u : Module is not inserted or is powered down\n",
3907 dev->data->port_id);
3911 /* This feature is not supported in older firmware versions */
3912 if (bp->hwrm_spec_code < 0x10202) {
3913 PMD_DRV_LOG(NOTICE, "Port %u : Feature is not supported in older firmware\n",
3914 dev->data->port_id);
3918 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
3919 SFF_DIAG_SUPPORT_OFFSET + 1,
3925 switch (module_info[0]) {
3926 case SFF_MODULE_ID_SFP:
3927 modinfo->type = RTE_ETH_MODULE_SFF_8472;
3928 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
3929 if (module_info[SFF_DIAG_SUPPORT_OFFSET] == 0)
3930 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN;
3932 case SFF_MODULE_ID_QSFP:
3933 case SFF_MODULE_ID_QSFP_PLUS:
3934 modinfo->type = RTE_ETH_MODULE_SFF_8436;
3935 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN;
3937 case SFF_MODULE_ID_QSFP28:
3938 modinfo->type = RTE_ETH_MODULE_SFF_8636;
3939 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
3940 if (module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK)
3941 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_LEN;
3944 PMD_DRV_LOG(NOTICE, "Port %u : Unsupported module\n", dev->data->port_id);
3948 PMD_DRV_LOG(INFO, "Port %u : modinfo->type = %d modinfo->eeprom_len = %d\n",
3949 dev->data->port_id, modinfo->type, modinfo->eeprom_len);
3954 static int bnxt_get_module_eeprom(struct rte_eth_dev *dev,
3955 struct rte_dev_eeprom_info *info)
3957 uint8_t pg_addr[5] = { I2C_DEV_ADDR_A0, I2C_DEV_ADDR_A0 };
3958 uint32_t offset = info->offset, length = info->length;
3959 uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1];
3960 struct bnxt *bp = dev->data->dev_private;
3961 uint8_t *data = info->data;
3962 uint8_t page = offset >> 7;
3963 uint8_t max_pages = 2;
3967 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
3968 SFF_DIAG_SUPPORT_OFFSET + 1,
3973 switch (module_info[0]) {
3974 case SFF_MODULE_ID_SFP:
3975 module_info[SFF_DIAG_SUPPORT_OFFSET] = 0;
3976 if (module_info[SFF_DIAG_SUPPORT_OFFSET]) {
3977 pg_addr[2] = I2C_DEV_ADDR_A2;
3978 pg_addr[3] = I2C_DEV_ADDR_A2;
3982 case SFF_MODULE_ID_QSFP28:
3983 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0,
3984 SFF8636_OPT_PAGES_OFFSET,
3989 if (opt_pages & SFF8636_PAGE1_MASK) {
3990 pg_addr[2] = I2C_DEV_ADDR_A0;
3993 if (opt_pages & SFF8636_PAGE2_MASK) {
3994 pg_addr[3] = I2C_DEV_ADDR_A0;
3997 if (~module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK) {
3998 pg_addr[4] = I2C_DEV_ADDR_A0;
4006 memset(data, 0, length);
4009 while (length && page < max_pages) {
4010 uint8_t raw_page = page ? page - 1 : 0;
4013 if (pg_addr[page] == I2C_DEV_ADDR_A2)
4017 chunk = RTE_MIN(length, 256 - offset);
4019 if (pg_addr[page]) {
4020 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, pg_addr[page],
4030 page += 1 + (chunk > 128);
4033 return length ? -EINVAL : 0;
4040 static const struct eth_dev_ops bnxt_dev_ops = {
4041 .dev_infos_get = bnxt_dev_info_get_op,
4042 .dev_close = bnxt_dev_close_op,
4043 .dev_configure = bnxt_dev_configure_op,
4044 .dev_start = bnxt_dev_start_op,
4045 .dev_stop = bnxt_dev_stop_op,
4046 .dev_set_link_up = bnxt_dev_set_link_up_op,
4047 .dev_set_link_down = bnxt_dev_set_link_down_op,
4048 .stats_get = bnxt_stats_get_op,
4049 .stats_reset = bnxt_stats_reset_op,
4050 .rx_queue_setup = bnxt_rx_queue_setup_op,
4051 .rx_queue_release = bnxt_rx_queue_release_op,
4052 .tx_queue_setup = bnxt_tx_queue_setup_op,
4053 .tx_queue_release = bnxt_tx_queue_release_op,
4054 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4055 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4056 .reta_update = bnxt_reta_update_op,
4057 .reta_query = bnxt_reta_query_op,
4058 .rss_hash_update = bnxt_rss_hash_update_op,
4059 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4060 .link_update = bnxt_link_update_op,
4061 .promiscuous_enable = bnxt_promiscuous_enable_op,
4062 .promiscuous_disable = bnxt_promiscuous_disable_op,
4063 .allmulticast_enable = bnxt_allmulticast_enable_op,
4064 .allmulticast_disable = bnxt_allmulticast_disable_op,
4065 .mac_addr_add = bnxt_mac_addr_add_op,
4066 .mac_addr_remove = bnxt_mac_addr_remove_op,
4067 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4068 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4069 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
4070 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
4071 .vlan_filter_set = bnxt_vlan_filter_set_op,
4072 .vlan_offload_set = bnxt_vlan_offload_set_op,
4073 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4074 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4075 .mtu_set = bnxt_mtu_set_op,
4076 .mac_addr_set = bnxt_set_default_mac_addr_op,
4077 .xstats_get = bnxt_dev_xstats_get_op,
4078 .xstats_get_names = bnxt_dev_xstats_get_names_op,
4079 .xstats_reset = bnxt_dev_xstats_reset_op,
4080 .fw_version_get = bnxt_fw_version_get,
4081 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4082 .rxq_info_get = bnxt_rxq_info_get_op,
4083 .txq_info_get = bnxt_txq_info_get_op,
4084 .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4085 .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4086 .dev_led_on = bnxt_dev_led_on_op,
4087 .dev_led_off = bnxt_dev_led_off_op,
4088 .rx_queue_start = bnxt_rx_queue_start,
4089 .rx_queue_stop = bnxt_rx_queue_stop,
4090 .tx_queue_start = bnxt_tx_queue_start,
4091 .tx_queue_stop = bnxt_tx_queue_stop,
4092 .flow_ops_get = bnxt_flow_ops_get_op,
4093 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4094 .get_eeprom_length = bnxt_get_eeprom_length_op,
4095 .get_eeprom = bnxt_get_eeprom_op,
4096 .set_eeprom = bnxt_set_eeprom_op,
4097 .get_module_info = bnxt_get_module_info,
4098 .get_module_eeprom = bnxt_get_module_eeprom,
4099 .timesync_enable = bnxt_timesync_enable,
4100 .timesync_disable = bnxt_timesync_disable,
4101 .timesync_read_time = bnxt_timesync_read_time,
4102 .timesync_write_time = bnxt_timesync_write_time,
4103 .timesync_adjust_time = bnxt_timesync_adjust_time,
4104 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4105 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4108 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4112 /* Only pre-map the reset GRC registers using window 3 */
4113 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4114 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4116 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4121 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4123 struct bnxt_error_recovery_info *info = bp->recovery_info;
4124 uint32_t reg_base = 0xffffffff;
4127 /* Only pre-map the monitoring GRC registers using window 2 */
4128 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4129 uint32_t reg = info->status_regs[i];
4131 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4134 if (reg_base == 0xffffffff)
4135 reg_base = reg & 0xfffff000;
4136 if ((reg & 0xfffff000) != reg_base)
4139 /* Use mask 0xffc as the Lower 2 bits indicates
4140 * address space location
4142 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4146 if (reg_base == 0xffffffff)
4149 rte_write32(reg_base, (uint8_t *)bp->bar0 +
4150 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4155 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4157 struct bnxt_error_recovery_info *info = bp->recovery_info;
4158 uint32_t delay = info->delay_after_reset[index];
4159 uint32_t val = info->reset_reg_val[index];
4160 uint32_t reg = info->reset_reg[index];
4161 uint32_t type, offset;
4164 type = BNXT_FW_STATUS_REG_TYPE(reg);
4165 offset = BNXT_FW_STATUS_REG_OFF(reg);
4168 case BNXT_FW_STATUS_REG_TYPE_CFG:
4169 ret = rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4171 PMD_DRV_LOG(ERR, "Failed to write %#x at PCI offset %#x",
4176 case BNXT_FW_STATUS_REG_TYPE_GRC:
4177 offset = bnxt_map_reset_regs(bp, offset);
4178 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4180 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4181 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4184 /* wait on a specific interval of time until core reset is complete */
4186 rte_delay_ms(delay);
4189 static void bnxt_dev_cleanup(struct bnxt *bp)
4191 bp->eth_dev->data->dev_link.link_status = 0;
4192 bp->link_info->link_up = 0;
4193 if (bp->eth_dev->data->dev_started)
4194 bnxt_dev_stop(bp->eth_dev);
4196 bnxt_uninit_resources(bp, true);
4200 bnxt_check_fw_reset_done(struct bnxt *bp)
4202 int timeout = bp->fw_reset_max_msecs;
4207 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4209 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4215 } while (timeout--);
4217 if (val == 0xffff) {
4218 PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n");
4225 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4227 struct rte_eth_dev *dev = bp->eth_dev;
4228 struct rte_vlan_filter_conf *vfc;
4232 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4233 vfc = &dev->data->vlan_filter_conf;
4234 vidx = vlan_id / 64;
4235 vbit = vlan_id % 64;
4237 /* Each bit corresponds to a VLAN id */
4238 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4239 rc = bnxt_add_vlan_filter(bp, vlan_id);
4248 static int bnxt_restore_mac_filters(struct bnxt *bp)
4250 struct rte_eth_dev *dev = bp->eth_dev;
4251 struct rte_eth_dev_info dev_info;
4252 struct rte_ether_addr *addr;
4258 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4261 rc = bnxt_dev_info_get_op(dev, &dev_info);
4265 /* replay MAC address configuration */
4266 for (i = 1; i < dev_info.max_mac_addrs; i++) {
4267 addr = &dev->data->mac_addrs[i];
4269 /* skip zero address */
4270 if (rte_is_zero_ether_addr(addr))
4274 pool_mask = dev->data->mac_pool_sel[i];
4277 if (pool_mask & 1ULL) {
4278 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4284 } while (pool_mask);
4290 static int bnxt_restore_filters(struct bnxt *bp)
4292 struct rte_eth_dev *dev = bp->eth_dev;
4295 if (dev->data->all_multicast) {
4296 ret = bnxt_allmulticast_enable_op(dev);
4300 if (dev->data->promiscuous) {
4301 ret = bnxt_promiscuous_enable_op(dev);
4306 ret = bnxt_restore_mac_filters(bp);
4310 ret = bnxt_restore_vlan_filters(bp);
4311 /* TODO restore other filters as well */
4315 static int bnxt_check_fw_ready(struct bnxt *bp)
4317 int timeout = bp->fw_reset_max_msecs;
4321 rc = bnxt_hwrm_poll_ver_get(bp);
4324 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4325 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4326 } while (rc && timeout > 0);
4329 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4334 static void bnxt_dev_recover(void *arg)
4336 struct bnxt *bp = arg;
4339 pthread_mutex_lock(&bp->err_recovery_lock);
4341 if (!bp->fw_reset_min_msecs) {
4342 rc = bnxt_check_fw_reset_done(bp);
4347 /* Clear Error flag so that device re-init should happen */
4348 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4350 rc = bnxt_check_fw_ready(bp);
4354 rc = bnxt_init_resources(bp, true);
4357 "Failed to initialize resources after reset\n");
4360 /* clear reset flag as the device is initialized now */
4361 bp->flags &= ~BNXT_FLAG_FW_RESET;
4363 rc = bnxt_dev_start_op(bp->eth_dev);
4365 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4369 rc = bnxt_restore_filters(bp);
4373 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4374 pthread_mutex_unlock(&bp->err_recovery_lock);
4378 bnxt_dev_stop(bp->eth_dev);
4380 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4381 bnxt_uninit_resources(bp, false);
4382 if (bp->eth_dev->data->dev_conf.intr_conf.rmv)
4383 rte_eth_dev_callback_process(bp->eth_dev,
4384 RTE_ETH_EVENT_INTR_RMV,
4386 pthread_mutex_unlock(&bp->err_recovery_lock);
4387 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4390 void bnxt_dev_reset_and_resume(void *arg)
4392 struct bnxt *bp = arg;
4393 uint32_t us = US_PER_MS * bp->fw_reset_min_msecs;
4397 bnxt_dev_cleanup(bp);
4399 bnxt_wait_for_device_shutdown(bp);
4401 /* During some fatal firmware error conditions, the PCI config space
4402 * register 0x2e which normally contains the subsystem ID will become
4403 * 0xffff. This register will revert back to the normal value after
4404 * the chip has completed core reset. If we detect this condition,
4405 * we can poll this config register immediately for the value to revert.
4407 if (bp->flags & BNXT_FLAG_FATAL_ERROR) {
4408 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4410 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4413 if (val == 0xffff) {
4414 bp->fw_reset_min_msecs = 0;
4419 rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp);
4421 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4424 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4426 struct bnxt_error_recovery_info *info = bp->recovery_info;
4427 uint32_t reg = info->status_regs[index];
4428 uint32_t type, offset, val = 0;
4431 type = BNXT_FW_STATUS_REG_TYPE(reg);
4432 offset = BNXT_FW_STATUS_REG_OFF(reg);
4435 case BNXT_FW_STATUS_REG_TYPE_CFG:
4436 ret = rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4438 PMD_DRV_LOG(ERR, "Failed to read PCI offset %#x",
4441 case BNXT_FW_STATUS_REG_TYPE_GRC:
4442 offset = info->mapped_status_regs[index];
4444 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4445 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4453 static int bnxt_fw_reset_all(struct bnxt *bp)
4455 struct bnxt_error_recovery_info *info = bp->recovery_info;
4459 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4460 /* Reset through primary function driver */
4461 for (i = 0; i < info->reg_array_cnt; i++)
4462 bnxt_write_fw_reset_reg(bp, i);
4463 /* Wait for time specified by FW after triggering reset */
4464 rte_delay_ms(info->primary_func_wait_period_after_reset);
4465 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4466 /* Reset with the help of Kong processor */
4467 rc = bnxt_hwrm_fw_reset(bp);
4469 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4475 static void bnxt_fw_reset_cb(void *arg)
4477 struct bnxt *bp = arg;
4478 struct bnxt_error_recovery_info *info = bp->recovery_info;
4481 /* Only Primary function can do FW reset */
4482 if (bnxt_is_primary_func(bp) &&
4483 bnxt_is_recovery_enabled(bp)) {
4484 rc = bnxt_fw_reset_all(bp);
4486 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4491 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4492 * EXCEPTION_FATAL_ASYNC event to all the functions
4493 * (including MASTER FUNC). After receiving this Async, all the active
4494 * drivers should treat this case as FW initiated recovery
4496 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4497 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4498 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4500 /* To recover from error */
4501 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4506 /* Driver should poll FW heartbeat, reset_counter with the frequency
4507 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4508 * When the driver detects heartbeat stop or change in reset_counter,
4509 * it has to trigger a reset to recover from the error condition.
4510 * A “primary function” is the function who will have the privilege to
4511 * initiate the chimp reset. The primary function will be elected by the
4512 * firmware and will be notified through async message.
4514 static void bnxt_check_fw_health(void *arg)
4516 struct bnxt *bp = arg;
4517 struct bnxt_error_recovery_info *info = bp->recovery_info;
4518 uint32_t val = 0, wait_msec;
4520 if (!info || !bnxt_is_recovery_enabled(bp) ||
4521 is_bnxt_in_error(bp))
4524 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4525 if (val == info->last_heart_beat)
4528 info->last_heart_beat = val;
4530 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4531 if (val != info->last_reset_counter)
4534 info->last_reset_counter = val;
4536 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4537 bnxt_check_fw_health, (void *)bp);
4541 /* Stop DMA to/from device */
4542 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4543 bp->flags |= BNXT_FLAG_FW_RESET;
4547 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4549 if (bnxt_is_primary_func(bp))
4550 wait_msec = info->primary_func_wait_period;
4552 wait_msec = info->normal_func_wait_period;
4554 rte_eal_alarm_set(US_PER_MS * wait_msec,
4555 bnxt_fw_reset_cb, (void *)bp);
4558 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4560 uint32_t polling_freq;
4562 pthread_mutex_lock(&bp->health_check_lock);
4564 if (!bnxt_is_recovery_enabled(bp))
4567 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4570 polling_freq = bp->recovery_info->driver_polling_freq;
4572 rte_eal_alarm_set(US_PER_MS * polling_freq,
4573 bnxt_check_fw_health, (void *)bp);
4574 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4577 pthread_mutex_unlock(&bp->health_check_lock);
4580 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4582 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4583 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4586 static bool bnxt_vf_pciid(uint16_t device_id)
4588 switch (device_id) {
4589 case BROADCOM_DEV_ID_57304_VF:
4590 case BROADCOM_DEV_ID_57406_VF:
4591 case BROADCOM_DEV_ID_5731X_VF:
4592 case BROADCOM_DEV_ID_5741X_VF:
4593 case BROADCOM_DEV_ID_57414_VF:
4594 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4595 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4596 case BROADCOM_DEV_ID_58802_VF:
4597 case BROADCOM_DEV_ID_57500_VF1:
4598 case BROADCOM_DEV_ID_57500_VF2:
4599 case BROADCOM_DEV_ID_58818_VF:
4607 /* Phase 5 device */
4608 static bool bnxt_p5_device(uint16_t device_id)
4610 switch (device_id) {
4611 case BROADCOM_DEV_ID_57508:
4612 case BROADCOM_DEV_ID_57504:
4613 case BROADCOM_DEV_ID_57502:
4614 case BROADCOM_DEV_ID_57508_MF1:
4615 case BROADCOM_DEV_ID_57504_MF1:
4616 case BROADCOM_DEV_ID_57502_MF1:
4617 case BROADCOM_DEV_ID_57508_MF2:
4618 case BROADCOM_DEV_ID_57504_MF2:
4619 case BROADCOM_DEV_ID_57502_MF2:
4620 case BROADCOM_DEV_ID_57500_VF1:
4621 case BROADCOM_DEV_ID_57500_VF2:
4622 case BROADCOM_DEV_ID_58812:
4623 case BROADCOM_DEV_ID_58814:
4624 case BROADCOM_DEV_ID_58818:
4625 case BROADCOM_DEV_ID_58818_VF:
4633 bool bnxt_stratus_device(struct bnxt *bp)
4635 uint16_t device_id = bp->pdev->id.device_id;
4637 switch (device_id) {
4638 case BROADCOM_DEV_ID_STRATUS_NIC:
4639 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4640 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4648 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev)
4650 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4651 struct bnxt *bp = eth_dev->data->dev_private;
4653 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4654 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4655 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4656 if (!bp->bar0 || !bp->doorbell_base) {
4657 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4661 bp->eth_dev = eth_dev;
4667 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4668 struct bnxt_ctx_pg_info *ctx_pg,
4673 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4674 const struct rte_memzone *mz = NULL;
4675 char mz_name[RTE_MEMZONE_NAMESIZE];
4676 rte_iova_t mz_phys_addr;
4677 uint64_t valid_bits = 0;
4684 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4686 rmem->page_size = BNXT_PAGE_SIZE;
4687 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4688 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4689 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4691 valid_bits = PTU_PTE_VALID;
4693 if (rmem->nr_pages > 1) {
4694 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4695 "bnxt_ctx_pg_tbl%s_%x_%d",
4696 suffix, idx, bp->eth_dev->data->port_id);
4697 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4698 mz = rte_memzone_lookup(mz_name);
4700 mz = rte_memzone_reserve_aligned(mz_name,
4702 bp->eth_dev->device->numa_node,
4704 RTE_MEMZONE_SIZE_HINT_ONLY |
4705 RTE_MEMZONE_IOVA_CONTIG,
4711 memset(mz->addr, 0, mz->len);
4712 mz_phys_addr = mz->iova;
4714 rmem->pg_tbl = mz->addr;
4715 rmem->pg_tbl_map = mz_phys_addr;
4716 rmem->pg_tbl_mz = mz;
4719 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4720 suffix, idx, bp->eth_dev->data->port_id);
4721 mz = rte_memzone_lookup(mz_name);
4723 mz = rte_memzone_reserve_aligned(mz_name,
4725 bp->eth_dev->device->numa_node,
4727 RTE_MEMZONE_SIZE_HINT_ONLY |
4728 RTE_MEMZONE_IOVA_CONTIG,
4734 memset(mz->addr, 0, mz->len);
4735 mz_phys_addr = mz->iova;
4737 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4738 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4739 rmem->dma_arr[i] = mz_phys_addr + sz;
4741 if (rmem->nr_pages > 1) {
4742 if (i == rmem->nr_pages - 2 &&
4743 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4744 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4745 else if (i == rmem->nr_pages - 1 &&
4746 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4747 valid_bits |= PTU_PTE_LAST;
4749 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4755 if (rmem->vmem_size)
4756 rmem->vmem = (void **)mz->addr;
4757 rmem->dma_arr[0] = mz_phys_addr;
4761 static void bnxt_free_ctx_mem(struct bnxt *bp)
4765 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4768 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4769 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4770 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4771 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4772 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4773 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4774 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4775 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4776 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4777 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4778 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4780 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4781 if (bp->ctx->tqm_mem[i])
4782 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4789 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4791 #define min_t(type, x, y) ({ \
4792 type __min1 = (x); \
4793 type __min2 = (y); \
4794 __min1 < __min2 ? __min1 : __min2; })
4796 #define max_t(type, x, y) ({ \
4797 type __max1 = (x); \
4798 type __max2 = (y); \
4799 __max1 > __max2 ? __max1 : __max2; })
4801 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4803 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4805 struct bnxt_ctx_pg_info *ctx_pg;
4806 struct bnxt_ctx_mem_info *ctx;
4807 uint32_t mem_size, ena, entries;
4808 uint32_t entries_sp, min;
4811 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4813 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4817 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4820 ctx_pg = &ctx->qp_mem;
4821 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4822 if (ctx->qp_entry_size) {
4823 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4824 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4829 ctx_pg = &ctx->srq_mem;
4830 ctx_pg->entries = ctx->srq_max_l2_entries;
4831 if (ctx->srq_entry_size) {
4832 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4833 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4838 ctx_pg = &ctx->cq_mem;
4839 ctx_pg->entries = ctx->cq_max_l2_entries;
4840 if (ctx->cq_entry_size) {
4841 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4842 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4847 ctx_pg = &ctx->vnic_mem;
4848 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4849 ctx->vnic_max_ring_table_entries;
4850 if (ctx->vnic_entry_size) {
4851 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4852 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4857 ctx_pg = &ctx->stat_mem;
4858 ctx_pg->entries = ctx->stat_max_entries;
4859 if (ctx->stat_entry_size) {
4860 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4861 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4866 min = ctx->tqm_min_entries_per_ring;
4868 entries_sp = ctx->qp_max_l2_entries +
4869 ctx->vnic_max_vnic_entries +
4870 2 * ctx->qp_min_qp1_entries + min;
4871 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4873 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4874 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4875 entries = clamp_t(uint32_t, entries, min,
4876 ctx->tqm_max_entries_per_ring);
4877 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4878 /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7.
4879 * i > 8 is other ext rings.
4881 ctx_pg = ctx->tqm_mem[i];
4882 ctx_pg->entries = i ? entries : entries_sp;
4883 if (ctx->tqm_entry_size) {
4884 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4885 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size,
4890 if (i < BNXT_MAX_TQM_LEGACY_RINGS)
4891 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4893 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8;
4896 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4897 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4900 "Failed to configure context mem: rc = %d\n", rc);
4902 ctx->flags |= BNXT_CTX_FLAG_INITED;
4907 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4909 struct rte_pci_device *pci_dev = bp->pdev;
4910 char mz_name[RTE_MEMZONE_NAMESIZE];
4911 const struct rte_memzone *mz = NULL;
4912 uint32_t total_alloc_len;
4913 rte_iova_t mz_phys_addr;
4915 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4918 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4919 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4920 pci_dev->addr.bus, pci_dev->addr.devid,
4921 pci_dev->addr.function, "rx_port_stats");
4922 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4923 mz = rte_memzone_lookup(mz_name);
4925 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4926 sizeof(struct rx_port_stats_ext) + 512);
4928 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4931 RTE_MEMZONE_SIZE_HINT_ONLY |
4932 RTE_MEMZONE_IOVA_CONTIG);
4936 memset(mz->addr, 0, mz->len);
4937 mz_phys_addr = mz->iova;
4939 bp->rx_mem_zone = (const void *)mz;
4940 bp->hw_rx_port_stats = mz->addr;
4941 bp->hw_rx_port_stats_map = mz_phys_addr;
4943 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4944 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4945 pci_dev->addr.bus, pci_dev->addr.devid,
4946 pci_dev->addr.function, "tx_port_stats");
4947 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4948 mz = rte_memzone_lookup(mz_name);
4950 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4951 sizeof(struct tx_port_stats_ext) + 512);
4953 mz = rte_memzone_reserve(mz_name,
4957 RTE_MEMZONE_SIZE_HINT_ONLY |
4958 RTE_MEMZONE_IOVA_CONTIG);
4962 memset(mz->addr, 0, mz->len);
4963 mz_phys_addr = mz->iova;
4965 bp->tx_mem_zone = (const void *)mz;
4966 bp->hw_tx_port_stats = mz->addr;
4967 bp->hw_tx_port_stats_map = mz_phys_addr;
4968 bp->flags |= BNXT_FLAG_PORT_STATS;
4970 /* Display extended statistics if FW supports it */
4971 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4972 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4973 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4976 bp->hw_rx_port_stats_ext = (void *)
4977 ((uint8_t *)bp->hw_rx_port_stats +
4978 sizeof(struct rx_port_stats));
4979 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4980 sizeof(struct rx_port_stats);
4981 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4983 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4984 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4985 bp->hw_tx_port_stats_ext = (void *)
4986 ((uint8_t *)bp->hw_tx_port_stats +
4987 sizeof(struct tx_port_stats));
4988 bp->hw_tx_port_stats_ext_map =
4989 bp->hw_tx_port_stats_map +
4990 sizeof(struct tx_port_stats);
4991 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4997 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4999 struct bnxt *bp = eth_dev->data->dev_private;
5002 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
5003 RTE_ETHER_ADDR_LEN *
5006 if (eth_dev->data->mac_addrs == NULL) {
5007 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
5011 if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
5015 /* Generate a random MAC address, if none was assigned by PF */
5016 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5017 bnxt_eth_hw_addr_random(bp->mac_addr);
5019 "Assign random MAC:" RTE_ETHER_ADDR_PRT_FMT "\n",
5020 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5021 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5023 rc = bnxt_hwrm_set_mac(bp);
5028 /* Copy the permanent MAC from the FUNC_QCAPS response */
5029 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5034 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5038 /* MAC is already configured in FW */
5039 if (BNXT_HAS_DFLT_MAC_SET(bp))
5042 /* Restore the old MAC configured */
5043 rc = bnxt_hwrm_set_mac(bp);
5045 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5050 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5055 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5057 if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
5058 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
5059 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
5060 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
5061 BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
5062 BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
5066 bnxt_get_bp(uint16_t port)
5069 struct rte_eth_dev *dev;
5071 if (!rte_eth_dev_is_valid_port(port)) {
5072 PMD_DRV_LOG(ERR, "Invalid port %d\n", port);
5076 dev = &rte_eth_devices[port];
5077 if (!is_bnxt_supported(dev)) {
5078 PMD_DRV_LOG(ERR, "Device %d not supported\n", port);
5082 bp = (struct bnxt *)dev->data->dev_private;
5083 if (!BNXT_TRUFLOW_EN(bp)) {
5084 PMD_DRV_LOG(ERR, "TRUFLOW not enabled\n");
5092 bnxt_get_svif(uint16_t port_id, bool func_svif,
5093 enum bnxt_ulp_intf_type type)
5095 struct rte_eth_dev *eth_dev;
5098 eth_dev = &rte_eth_devices[port_id];
5099 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5100 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5104 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5107 eth_dev = vfr->parent_dev;
5110 bp = eth_dev->data->dev_private;
5112 return func_svif ? bp->func_svif : bp->port_svif;
5116 bnxt_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type,
5117 uint8_t *mac, uint8_t *parent_mac)
5119 struct rte_eth_dev *eth_dev;
5122 if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF &&
5123 type != BNXT_ULP_INTF_TYPE_PF)
5126 eth_dev = &rte_eth_devices[port];
5127 bp = eth_dev->data->dev_private;
5128 memcpy(mac, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5130 if (type == BNXT_ULP_INTF_TYPE_TRUSTED_VF)
5131 memcpy(parent_mac, bp->parent->mac_addr, RTE_ETHER_ADDR_LEN);
5135 bnxt_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5137 struct rte_eth_dev *eth_dev;
5140 if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF)
5143 eth_dev = &rte_eth_devices[port];
5144 bp = eth_dev->data->dev_private;
5146 return bp->parent->vnic;
5149 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5151 struct rte_eth_dev *eth_dev;
5152 struct bnxt_vnic_info *vnic;
5155 eth_dev = &rte_eth_devices[port];
5156 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5157 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5161 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5162 return vfr->dflt_vnic_id;
5164 eth_dev = vfr->parent_dev;
5167 bp = eth_dev->data->dev_private;
5169 vnic = BNXT_GET_DEFAULT_VNIC(bp);
5171 return vnic->fw_vnic_id;
5175 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5177 struct rte_eth_dev *eth_dev;
5180 eth_dev = &rte_eth_devices[port];
5181 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5182 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5186 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5189 eth_dev = vfr->parent_dev;
5192 bp = eth_dev->data->dev_private;
5197 enum bnxt_ulp_intf_type
5198 bnxt_get_interface_type(uint16_t port)
5200 struct rte_eth_dev *eth_dev;
5203 eth_dev = &rte_eth_devices[port];
5204 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5205 return BNXT_ULP_INTF_TYPE_VF_REP;
5207 bp = eth_dev->data->dev_private;
5209 return BNXT_ULP_INTF_TYPE_PF;
5210 else if (BNXT_VF_IS_TRUSTED(bp))
5211 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5212 else if (BNXT_VF(bp))
5213 return BNXT_ULP_INTF_TYPE_VF;
5215 return BNXT_ULP_INTF_TYPE_INVALID;
5219 bnxt_get_phy_port_id(uint16_t port_id)
5221 struct bnxt_representor *vfr;
5222 struct rte_eth_dev *eth_dev;
5225 eth_dev = &rte_eth_devices[port_id];
5226 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5227 vfr = eth_dev->data->dev_private;
5231 eth_dev = vfr->parent_dev;
5234 bp = eth_dev->data->dev_private;
5236 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5240 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5242 struct rte_eth_dev *eth_dev;
5245 eth_dev = &rte_eth_devices[port_id];
5246 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5247 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5251 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5252 return vfr->fw_fid - 1;
5254 eth_dev = vfr->parent_dev;
5257 bp = eth_dev->data->dev_private;
5259 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5263 bnxt_get_vport(uint16_t port_id)
5265 return (1 << bnxt_get_phy_port_id(port_id));
5268 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5270 struct bnxt_error_recovery_info *info = bp->recovery_info;
5273 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5274 memset(info, 0, sizeof(*info));
5278 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5281 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5284 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5286 bp->recovery_info = info;
5289 static void bnxt_check_fw_status(struct bnxt *bp)
5293 if (!(bp->recovery_info &&
5294 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5297 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5298 if (fw_status != BNXT_FW_STATUS_HEALTHY)
5299 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5303 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5305 struct bnxt_error_recovery_info *info = bp->recovery_info;
5306 uint32_t status_loc;
5309 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5310 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5311 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5312 BNXT_GRCP_WINDOW_2_BASE +
5313 offsetof(struct hcomm_status,
5315 /* If the signature is absent, then FW does not support this feature */
5316 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5317 HCOMM_STATUS_SIGNATURE_VAL)
5321 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5325 bp->recovery_info = info;
5327 memset(info, 0, sizeof(*info));
5330 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5331 BNXT_GRCP_WINDOW_2_BASE +
5332 offsetof(struct hcomm_status,
5335 /* Only pre-map the FW health status GRC register */
5336 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5339 info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5340 info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5341 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5343 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5344 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5346 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5351 /* This function gets the FW version along with the
5352 * capabilities(MAX and current) of the function, vnic,
5353 * error recovery, phy and other chip related info
5355 static int bnxt_get_config(struct bnxt *bp)
5362 rc = bnxt_map_hcomm_fw_status_reg(bp);
5366 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5368 bnxt_check_fw_status(bp);
5372 rc = bnxt_hwrm_func_reset(bp);
5376 rc = bnxt_hwrm_vnic_qcaps(bp);
5380 rc = bnxt_hwrm_queue_qportcfg(bp);
5384 /* Get the MAX capabilities for this function.
5385 * This function also allocates context memory for TQM rings and
5386 * informs the firmware about this allocated backing store memory.
5388 rc = bnxt_hwrm_func_qcaps(bp);
5392 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5396 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5400 bnxt_hwrm_port_mac_qcfg(bp);
5402 bnxt_hwrm_parent_pf_qcfg(bp);
5404 bnxt_hwrm_port_phy_qcaps(bp);
5406 bnxt_alloc_error_recovery_info(bp);
5407 /* Get the adapter error recovery support info */
5408 rc = bnxt_hwrm_error_recovery_qcfg(bp);
5410 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5412 bnxt_hwrm_port_led_qcaps(bp);
5418 bnxt_init_locks(struct bnxt *bp)
5422 err = pthread_mutex_init(&bp->flow_lock, NULL);
5424 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5428 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5430 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5434 err = pthread_mutex_init(&bp->health_check_lock, NULL);
5436 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5440 err = pthread_mutex_init(&bp->err_recovery_lock, NULL);
5442 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n");
5447 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5451 rc = bnxt_get_config(bp);
5455 if (!reconfig_dev) {
5456 rc = bnxt_setup_mac_addr(bp->eth_dev);
5460 rc = bnxt_restore_dflt_mac(bp);
5465 bnxt_config_vf_req_fwd(bp);
5467 rc = bnxt_hwrm_func_driver_register(bp);
5469 PMD_DRV_LOG(ERR, "Failed to register driver");
5474 if (bp->pdev->max_vfs) {
5475 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5477 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5481 rc = bnxt_hwrm_allocate_pf_only(bp);
5484 "Failed to allocate PF resources");
5490 rc = bnxt_alloc_mem(bp, reconfig_dev);
5494 rc = bnxt_setup_int(bp);
5498 rc = bnxt_request_int(bp);
5502 rc = bnxt_init_ctx_mem(bp);
5504 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5512 bnxt_parse_devarg_accum_stats(__rte_unused const char *key,
5513 const char *value, void *opaque_arg)
5515 struct bnxt *bp = opaque_arg;
5516 unsigned long accum_stats;
5519 if (!value || !opaque_arg) {
5521 "Invalid parameter passed to accum-stats devargs.\n");
5525 accum_stats = strtoul(value, &end, 10);
5526 if (end == NULL || *end != '\0' ||
5527 (accum_stats == ULONG_MAX && errno == ERANGE)) {
5529 "Invalid parameter passed to accum-stats devargs.\n");
5533 if (BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats)) {
5535 "Invalid value passed to accum-stats devargs.\n");
5540 bp->flags2 |= BNXT_FLAGS2_ACCUM_STATS_EN;
5541 PMD_DRV_LOG(INFO, "Host-based accum-stats feature enabled.\n");
5543 bp->flags2 &= ~BNXT_FLAGS2_ACCUM_STATS_EN;
5544 PMD_DRV_LOG(INFO, "Host-based accum-stats feature disabled.\n");
5551 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5552 const char *value, void *opaque_arg)
5554 struct bnxt *bp = opaque_arg;
5555 unsigned long flow_xstat;
5558 if (!value || !opaque_arg) {
5560 "Invalid parameter passed to flow_xstat devarg.\n");
5564 flow_xstat = strtoul(value, &end, 10);
5565 if (end == NULL || *end != '\0' ||
5566 (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5568 "Invalid parameter passed to flow_xstat devarg.\n");
5572 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5574 "Invalid value passed to flow_xstat devarg.\n");
5578 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5579 if (BNXT_FLOW_XSTATS_EN(bp))
5580 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5586 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5587 const char *value, void *opaque_arg)
5589 struct bnxt *bp = opaque_arg;
5590 unsigned long max_num_kflows;
5593 if (!value || !opaque_arg) {
5595 "Invalid parameter passed to max_num_kflows devarg.\n");
5599 max_num_kflows = strtoul(value, &end, 10);
5600 if (end == NULL || *end != '\0' ||
5601 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5603 "Invalid parameter passed to max_num_kflows devarg.\n");
5607 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5609 "Invalid value passed to max_num_kflows devarg.\n");
5613 bp->max_num_kflows = max_num_kflows;
5614 if (bp->max_num_kflows)
5615 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5622 bnxt_parse_devarg_app_id(__rte_unused const char *key,
5623 const char *value, void *opaque_arg)
5625 struct bnxt *bp = opaque_arg;
5626 unsigned long app_id;
5629 if (!value || !opaque_arg) {
5631 "Invalid parameter passed to app-id "
5636 app_id = strtoul(value, &end, 10);
5637 if (end == NULL || *end != '\0' ||
5638 (app_id == ULONG_MAX && errno == ERANGE)) {
5640 "Invalid parameter passed to app_id "
5645 if (BNXT_DEVARG_APP_ID_INVALID(app_id)) {
5646 PMD_DRV_LOG(ERR, "Invalid app-id(%d) devargs.\n",
5651 bp->app_id = app_id;
5652 PMD_DRV_LOG(INFO, "app-id=%d feature enabled.\n", (uint16_t)app_id);
5658 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5659 const char *value, void *opaque_arg)
5661 struct bnxt_representor *vfr_bp = opaque_arg;
5662 unsigned long rep_is_pf;
5665 if (!value || !opaque_arg) {
5667 "Invalid parameter passed to rep_is_pf devargs.\n");
5671 rep_is_pf = strtoul(value, &end, 10);
5672 if (end == NULL || *end != '\0' ||
5673 (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5675 "Invalid parameter passed to rep_is_pf devargs.\n");
5679 if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5681 "Invalid value passed to rep_is_pf devargs.\n");
5685 vfr_bp->flags |= rep_is_pf;
5686 if (BNXT_REP_PF(vfr_bp))
5687 PMD_DRV_LOG(INFO, "PF representor\n");
5689 PMD_DRV_LOG(INFO, "VF representor\n");
5695 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5696 const char *value, void *opaque_arg)
5698 struct bnxt_representor *vfr_bp = opaque_arg;
5699 unsigned long rep_based_pf;
5702 if (!value || !opaque_arg) {
5704 "Invalid parameter passed to rep_based_pf "
5709 rep_based_pf = strtoul(value, &end, 10);
5710 if (end == NULL || *end != '\0' ||
5711 (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5713 "Invalid parameter passed to rep_based_pf "
5718 if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5720 "Invalid value passed to rep_based_pf devargs.\n");
5724 vfr_bp->rep_based_pf = rep_based_pf;
5725 vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
5727 PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5733 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5734 const char *value, void *opaque_arg)
5736 struct bnxt_representor *vfr_bp = opaque_arg;
5737 unsigned long rep_q_r2f;
5740 if (!value || !opaque_arg) {
5742 "Invalid parameter passed to rep_q_r2f "
5747 rep_q_r2f = strtoul(value, &end, 10);
5748 if (end == NULL || *end != '\0' ||
5749 (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5751 "Invalid parameter passed to rep_q_r2f "
5756 if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5758 "Invalid value passed to rep_q_r2f devargs.\n");
5762 vfr_bp->rep_q_r2f = rep_q_r2f;
5763 vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5764 PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5770 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5771 const char *value, void *opaque_arg)
5773 struct bnxt_representor *vfr_bp = opaque_arg;
5774 unsigned long rep_q_f2r;
5777 if (!value || !opaque_arg) {
5779 "Invalid parameter passed to rep_q_f2r "
5784 rep_q_f2r = strtoul(value, &end, 10);
5785 if (end == NULL || *end != '\0' ||
5786 (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5788 "Invalid parameter passed to rep_q_f2r "
5793 if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5795 "Invalid value passed to rep_q_f2r devargs.\n");
5799 vfr_bp->rep_q_f2r = rep_q_f2r;
5800 vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5801 PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5807 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5808 const char *value, void *opaque_arg)
5810 struct bnxt_representor *vfr_bp = opaque_arg;
5811 unsigned long rep_fc_r2f;
5814 if (!value || !opaque_arg) {
5816 "Invalid parameter passed to rep_fc_r2f "
5821 rep_fc_r2f = strtoul(value, &end, 10);
5822 if (end == NULL || *end != '\0' ||
5823 (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5825 "Invalid parameter passed to rep_fc_r2f "
5830 if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5832 "Invalid value passed to rep_fc_r2f devargs.\n");
5836 vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5837 vfr_bp->rep_fc_r2f = rep_fc_r2f;
5838 PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5844 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5845 const char *value, void *opaque_arg)
5847 struct bnxt_representor *vfr_bp = opaque_arg;
5848 unsigned long rep_fc_f2r;
5851 if (!value || !opaque_arg) {
5853 "Invalid parameter passed to rep_fc_f2r "
5858 rep_fc_f2r = strtoul(value, &end, 10);
5859 if (end == NULL || *end != '\0' ||
5860 (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5862 "Invalid parameter passed to rep_fc_f2r "
5867 if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5869 "Invalid value passed to rep_fc_f2r devargs.\n");
5873 vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5874 vfr_bp->rep_fc_f2r = rep_fc_f2r;
5875 PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5881 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5883 struct rte_kvargs *kvlist;
5886 if (devargs == NULL)
5889 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5894 * Handler for "flow_xstat" devarg.
5895 * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5897 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5898 bnxt_parse_devarg_flow_xstat, bp);
5903 * Handler for "accum-stats" devarg.
5904 * Invoked as for ex: "-a 0000:00:0d.0,accum-stats=1"
5906 rte_kvargs_process(kvlist, BNXT_DEVARG_ACCUM_STATS,
5907 bnxt_parse_devarg_accum_stats, bp);
5909 * Handler for "max_num_kflows" devarg.
5910 * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5912 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5913 bnxt_parse_devarg_max_num_kflows, bp);
5919 * Handler for "app-id" devarg.
5920 * Invoked as for ex: "-a 000:00:0d.0,app-id=1"
5922 rte_kvargs_process(kvlist, BNXT_DEVARG_APP_ID,
5923 bnxt_parse_devarg_app_id, bp);
5925 rte_kvargs_free(kvlist);
5929 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5933 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5934 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5937 "Failed to alloc switch domain: %d\n", rc);
5940 "Switch domain allocated %d\n",
5941 bp->switch_domain_id);
5947 /* Allocate and initialize various fields in bnxt struct that
5948 * need to be allocated/destroyed only once in the lifetime of the driver
5950 static int bnxt_drv_init(struct rte_eth_dev *eth_dev)
5952 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5953 struct bnxt *bp = eth_dev->data->dev_private;
5956 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5958 if (bnxt_vf_pciid(pci_dev->id.device_id))
5959 bp->flags |= BNXT_FLAG_VF;
5961 if (bnxt_p5_device(pci_dev->id.device_id))
5962 bp->flags |= BNXT_FLAG_CHIP_P5;
5964 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5965 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5966 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5967 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5968 bp->flags |= BNXT_FLAG_STINGRAY;
5970 if (BNXT_TRUFLOW_EN(bp)) {
5971 /* extra mbuf field is required to store CFA code from mark */
5972 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5973 .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5974 .size = sizeof(bnxt_cfa_code_dynfield_t),
5975 .align = __alignof__(bnxt_cfa_code_dynfield_t),
5977 bnxt_cfa_code_dynfield_offset =
5978 rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5979 if (bnxt_cfa_code_dynfield_offset < 0) {
5981 "Failed to register mbuf field for TruFlow mark\n");
5986 rc = bnxt_map_pci_bars(eth_dev);
5989 "Failed to initialize board rc: %x\n", rc);
5993 rc = bnxt_alloc_pf_info(bp);
5997 rc = bnxt_alloc_link_info(bp);
6001 rc = bnxt_alloc_parent_info(bp);
6005 rc = bnxt_alloc_hwrm_resources(bp);
6008 "Failed to allocate response buffer rc: %x\n", rc);
6011 rc = bnxt_alloc_leds_info(bp);
6015 rc = bnxt_alloc_cos_queues(bp);
6019 rc = bnxt_init_locks(bp);
6023 rc = bnxt_alloc_switch_domain(bp);
6031 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
6033 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
6034 static int version_printed;
6038 if (version_printed++ == 0)
6039 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
6041 eth_dev->dev_ops = &bnxt_dev_ops;
6042 eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
6043 eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
6044 eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
6045 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
6046 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
6049 * For secondary processes, we don't initialise any further
6050 * as primary has already done this work.
6052 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6055 rte_eth_copy_pci_info(eth_dev, pci_dev);
6056 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
6058 bp = eth_dev->data->dev_private;
6060 /* Parse dev arguments passed on when starting the DPDK application. */
6061 rc = bnxt_parse_dev_args(bp, pci_dev->device.devargs);
6065 rc = bnxt_drv_init(eth_dev);
6069 rc = bnxt_init_resources(bp, false);
6073 rc = bnxt_alloc_stats_mem(bp);
6078 "Found %s device at mem %" PRIX64 ", node addr %pM\n",
6080 pci_dev->mem_resource[0].phys_addr,
6081 pci_dev->mem_resource[0].addr);
6086 bnxt_dev_uninit(eth_dev);
6091 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
6100 ctx->dma = RTE_BAD_IOVA;
6101 ctx->ctx_id = BNXT_CTX_VAL_INVAL;
6104 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
6106 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
6107 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6108 bp->flow_stat->rx_fc_out_tbl.ctx_id,
6109 bp->flow_stat->max_fc,
6112 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
6113 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6114 bp->flow_stat->tx_fc_out_tbl.ctx_id,
6115 bp->flow_stat->max_fc,
6118 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6119 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
6120 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6122 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6123 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
6124 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6126 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6127 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
6128 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6130 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6131 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
6132 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6135 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
6137 bnxt_unregister_fc_ctx_mem(bp);
6139 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
6140 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
6141 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
6142 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
6145 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
6147 if (BNXT_FLOW_XSTATS_EN(bp))
6148 bnxt_uninit_fc_ctx_mem(bp);
6152 bnxt_free_error_recovery_info(struct bnxt *bp)
6154 rte_free(bp->recovery_info);
6155 bp->recovery_info = NULL;
6156 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
6160 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
6165 bnxt_free_mem(bp, reconfig_dev);
6167 bnxt_hwrm_func_buf_unrgtr(bp);
6168 if (bp->pf != NULL) {
6169 rte_free(bp->pf->vf_req_buf);
6170 bp->pf->vf_req_buf = NULL;
6173 rc = bnxt_hwrm_func_driver_unregister(bp);
6174 bp->flags &= ~BNXT_FLAG_REGISTERED;
6175 bnxt_free_ctx_mem(bp);
6176 if (!reconfig_dev) {
6177 bnxt_free_hwrm_resources(bp);
6178 bnxt_free_error_recovery_info(bp);
6181 bnxt_uninit_ctx_mem(bp);
6183 bnxt_free_flow_stats_info(bp);
6184 if (bp->rep_info != NULL)
6185 bnxt_free_switch_domain(bp);
6186 bnxt_free_rep_info(bp);
6187 rte_free(bp->ptp_cfg);
6193 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
6195 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6198 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
6200 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
6201 bnxt_dev_close_op(eth_dev);
6206 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
6208 struct bnxt *bp = eth_dev->data->dev_private;
6209 struct rte_eth_dev *vf_rep_eth_dev;
6215 for (i = 0; i < bp->num_reps; i++) {
6216 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
6217 if (!vf_rep_eth_dev)
6219 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
6220 vf_rep_eth_dev->data->port_id);
6221 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
6223 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
6224 eth_dev->data->port_id);
6225 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
6230 static void bnxt_free_rep_info(struct bnxt *bp)
6232 rte_free(bp->rep_info);
6233 bp->rep_info = NULL;
6234 rte_free(bp->cfa_code_map);
6235 bp->cfa_code_map = NULL;
6238 static int bnxt_init_rep_info(struct bnxt *bp)
6245 bp->rep_info = rte_zmalloc("bnxt_rep_info",
6246 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
6248 if (!bp->rep_info) {
6249 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
6252 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
6253 sizeof(*bp->cfa_code_map) *
6254 BNXT_MAX_CFA_CODE, 0);
6255 if (!bp->cfa_code_map) {
6256 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
6257 bnxt_free_rep_info(bp);
6261 for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
6262 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
6264 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
6266 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
6267 bnxt_free_rep_info(bp);
6271 rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
6273 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
6274 bnxt_free_rep_info(bp);
6281 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
6282 struct rte_eth_devargs *eth_da,
6283 struct rte_eth_dev *backing_eth_dev,
6284 const char *dev_args)
6286 struct rte_eth_dev *vf_rep_eth_dev;
6287 char name[RTE_ETH_NAME_MAX_LEN];
6288 struct bnxt *backing_bp;
6291 struct rte_kvargs *kvlist = NULL;
6293 if (eth_da->type == RTE_ETH_REPRESENTOR_NONE)
6295 if (eth_da->type != RTE_ETH_REPRESENTOR_VF) {
6296 PMD_DRV_LOG(ERR, "unsupported representor type %d\n",
6300 num_rep = eth_da->nb_representor_ports;
6301 if (num_rep > BNXT_MAX_VF_REPS) {
6302 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
6303 num_rep, BNXT_MAX_VF_REPS);
6307 if (num_rep >= RTE_MAX_ETHPORTS) {
6309 "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6310 num_rep, RTE_MAX_ETHPORTS);
6314 backing_bp = backing_eth_dev->data->dev_private;
6316 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6318 "Not a PF or trusted VF. No Representor support\n");
6319 /* Returning an error is not an option.
6320 * Applications are not handling this correctly
6325 if (bnxt_init_rep_info(backing_bp))
6328 for (i = 0; i < num_rep; i++) {
6329 struct bnxt_representor representor = {
6330 .vf_id = eth_da->representor_ports[i],
6331 .switch_domain_id = backing_bp->switch_domain_id,
6332 .parent_dev = backing_eth_dev
6335 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6336 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6337 representor.vf_id, BNXT_MAX_VF_REPS);
6341 /* representor port net_bdf_port */
6342 snprintf(name, sizeof(name), "net_%s_representor_%d",
6343 pci_dev->device.name, eth_da->representor_ports[i]);
6345 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
6348 * Handler for "rep_is_pf" devarg.
6349 * Invoked as for ex: "-a 000:00:0d.0,
6350 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6352 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
6353 bnxt_parse_devarg_rep_is_pf,
6354 (void *)&representor);
6360 * Handler for "rep_based_pf" devarg.
6361 * Invoked as for ex: "-a 000:00:0d.0,
6362 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6364 ret = rte_kvargs_process(kvlist,
6365 BNXT_DEVARG_REP_BASED_PF,
6366 bnxt_parse_devarg_rep_based_pf,
6367 (void *)&representor);
6373 * Handler for "rep_based_pf" devarg.
6374 * Invoked as for ex: "-a 000:00:0d.0,
6375 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6377 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
6378 bnxt_parse_devarg_rep_q_r2f,
6379 (void *)&representor);
6385 * Handler for "rep_based_pf" devarg.
6386 * Invoked as for ex: "-a 000:00:0d.0,
6387 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6389 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
6390 bnxt_parse_devarg_rep_q_f2r,
6391 (void *)&representor);
6397 * Handler for "rep_based_pf" devarg.
6398 * Invoked as for ex: "-a 000:00:0d.0,
6399 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6401 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
6402 bnxt_parse_devarg_rep_fc_r2f,
6403 (void *)&representor);
6409 * Handler for "rep_based_pf" devarg.
6410 * Invoked as for ex: "-a 000:00:0d.0,
6411 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6413 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
6414 bnxt_parse_devarg_rep_fc_f2r,
6415 (void *)&representor);
6422 ret = rte_eth_dev_create(&pci_dev->device, name,
6423 sizeof(struct bnxt_representor),
6425 bnxt_representor_init,
6428 PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6429 "representor %s.", name);
6433 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6434 if (!vf_rep_eth_dev) {
6435 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6436 " for VF-Rep: %s.", name);
6441 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6442 backing_eth_dev->data->port_id);
6443 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6445 backing_bp->num_reps++;
6449 rte_kvargs_free(kvlist);
6453 /* If num_rep > 1, then rollback already created
6454 * ports, since we'll be failing the probe anyway
6457 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6459 rte_kvargs_free(kvlist);
6464 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6465 struct rte_pci_device *pci_dev)
6467 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6468 struct rte_eth_dev *backing_eth_dev;
6472 if (pci_dev->device.devargs) {
6473 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6479 num_rep = eth_da.nb_representor_ports;
6480 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6483 /* We could come here after first level of probe is already invoked
6484 * as part of an application bringup(OVS-DPDK vswitchd), so first check
6485 * for already allocated eth_dev for the backing device (PF/Trusted VF)
6487 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6488 if (backing_eth_dev == NULL) {
6489 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6490 sizeof(struct bnxt),
6491 eth_dev_pci_specific_init, pci_dev,
6492 bnxt_dev_init, NULL);
6494 if (ret || !num_rep)
6497 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6499 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6500 backing_eth_dev->data->port_id);
6505 /* probe representor ports now */
6506 ret = bnxt_rep_port_probe(pci_dev, ð_da, backing_eth_dev,
6507 pci_dev->device.devargs->args);
6512 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6514 struct rte_eth_dev *eth_dev;
6516 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6518 return 0; /* Invoked typically only by OVS-DPDK, by the
6519 * time it comes here the eth_dev is already
6520 * deleted by rte_eth_dev_close(), so returning
6521 * +ve value will at least help in proper cleanup
6524 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6525 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6526 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6527 return rte_eth_dev_destroy(eth_dev,
6528 bnxt_representor_uninit);
6530 return rte_eth_dev_destroy(eth_dev,
6533 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6537 static struct rte_pci_driver bnxt_rte_pmd = {
6538 .id_table = bnxt_pci_id_map,
6539 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6540 RTE_PCI_DRV_INTR_RMV |
6541 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6544 .probe = bnxt_pci_probe,
6545 .remove = bnxt_pci_remove,
6549 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6551 if (strcmp(dev->device->driver->name, drv->driver.name))
6557 bool is_bnxt_supported(struct rte_eth_dev *dev)
6559 return is_device_supported(dev, &bnxt_rte_pmd);
6562 RTE_LOG_REGISTER_SUFFIX(bnxt_logtype_driver, driver, NOTICE);
6563 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6564 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6565 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");