1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
15 #include <rte_kvargs.h>
19 #include "bnxt_filter.h"
20 #include "bnxt_hwrm.h"
22 #include "bnxt_reps.h"
23 #include "bnxt_ring.h"
26 #include "bnxt_stats.h"
29 #include "bnxt_vnic.h"
30 #include "hsi_struct_def_dpdk.h"
31 #include "bnxt_nvm_defs.h"
32 #include "bnxt_tf_common.h"
33 #include "ulp_flow_db.h"
34 #include "rte_pmd_bnxt.h"
36 #define DRV_MODULE_NAME "bnxt"
37 static const char bnxt_version[] =
38 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
41 * The set of PCI devices this driver supports
43 static const struct rte_pci_id bnxt_pci_id_map[] = {
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
45 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
47 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
97 { .vendor_id = 0, /* sentinel */ },
100 #define BNXT_DEVARG_TRUFLOW "host-based-truflow"
101 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat"
102 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows"
103 #define BNXT_DEVARG_REPRESENTOR "representor"
104 #define BNXT_DEVARG_REP_BASED_PF "rep-based-pf"
105 #define BNXT_DEVARG_REP_IS_PF "rep-is-pf"
106 #define BNXT_DEVARG_REP_Q_R2F "rep-q-r2f"
107 #define BNXT_DEVARG_REP_Q_F2R "rep-q-f2r"
108 #define BNXT_DEVARG_REP_FC_R2F "rep-fc-r2f"
109 #define BNXT_DEVARG_REP_FC_F2R "rep-fc-f2r"
111 static const char *const bnxt_dev_args[] = {
112 BNXT_DEVARG_REPRESENTOR,
114 BNXT_DEVARG_FLOW_XSTAT,
115 BNXT_DEVARG_MAX_NUM_KFLOWS,
116 BNXT_DEVARG_REP_BASED_PF,
117 BNXT_DEVARG_REP_IS_PF,
118 BNXT_DEVARG_REP_Q_R2F,
119 BNXT_DEVARG_REP_Q_F2R,
120 BNXT_DEVARG_REP_FC_R2F,
121 BNXT_DEVARG_REP_FC_F2R,
126 * truflow == false to disable the feature
127 * truflow == true to enable the feature
129 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1)
132 * flow_xstat == false to disable the feature
133 * flow_xstat == true to enable the feature
135 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1)
138 * rep_is_pf == false to indicate VF representor
139 * rep_is_pf == true to indicate PF representor
141 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf) ((rep_is_pf) > 1)
144 * rep_based_pf == Physical index of the PF
146 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf) ((rep_based_pf) > 15)
148 * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
150 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f) ((rep_q_r2f) > 3)
153 * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
155 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r) ((rep_q_f2r) > 3)
158 * rep_fc_r2f == Flow control for the representor to endpoint direction
160 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f) ((rep_fc_r2f) > 1)
163 * rep_fc_f2r == Flow control for the endpoint to representor direction
165 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r) ((rep_fc_f2r) > 1)
167 int bnxt_cfa_code_dynfield_offset = -1;
170 * max_num_kflows must be >= 32
171 * and must be a power-of-2 supported value
172 * return: 1 -> invalid
175 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
177 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
182 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
183 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
184 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
185 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
186 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
187 static int bnxt_restore_vlan_filters(struct bnxt *bp);
188 static void bnxt_dev_recover(void *arg);
189 static void bnxt_free_error_recovery_info(struct bnxt *bp);
190 static void bnxt_free_rep_info(struct bnxt *bp);
192 int is_bnxt_in_error(struct bnxt *bp)
194 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
196 if (bp->flags & BNXT_FLAG_FW_RESET)
202 /***********************/
205 * High level utility functions
208 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
210 if (!BNXT_CHIP_THOR(bp))
213 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
214 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
215 BNXT_RSS_ENTRIES_PER_CTX_THOR;
218 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
220 if (!BNXT_CHIP_THOR(bp))
221 return HW_HASH_INDEX_SIZE;
223 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
226 static void bnxt_free_parent_info(struct bnxt *bp)
228 rte_free(bp->parent);
231 static void bnxt_free_pf_info(struct bnxt *bp)
236 static void bnxt_free_link_info(struct bnxt *bp)
238 rte_free(bp->link_info);
241 static void bnxt_free_leds_info(struct bnxt *bp)
250 static void bnxt_free_flow_stats_info(struct bnxt *bp)
252 rte_free(bp->flow_stat);
253 bp->flow_stat = NULL;
256 static void bnxt_free_cos_queues(struct bnxt *bp)
258 rte_free(bp->rx_cos_queue);
259 rte_free(bp->tx_cos_queue);
262 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
264 bnxt_free_filter_mem(bp);
265 bnxt_free_vnic_attributes(bp);
266 bnxt_free_vnic_mem(bp);
268 /* tx/rx rings are configured as part of *_queue_setup callbacks.
269 * If the number of rings change across fw update,
270 * we don't have much choice except to warn the user.
274 bnxt_free_tx_rings(bp);
275 bnxt_free_rx_rings(bp);
277 bnxt_free_async_cp_ring(bp);
278 bnxt_free_rxtx_nq_ring(bp);
280 rte_free(bp->grp_info);
284 static int bnxt_alloc_parent_info(struct bnxt *bp)
286 bp->parent = rte_zmalloc("bnxt_parent_info",
287 sizeof(struct bnxt_parent_info), 0);
288 if (bp->parent == NULL)
294 static int bnxt_alloc_pf_info(struct bnxt *bp)
296 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
303 static int bnxt_alloc_link_info(struct bnxt *bp)
306 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
307 if (bp->link_info == NULL)
313 static int bnxt_alloc_leds_info(struct bnxt *bp)
318 bp->leds = rte_zmalloc("bnxt_leds",
319 BNXT_MAX_LED * sizeof(struct bnxt_led_info),
321 if (bp->leds == NULL)
327 static int bnxt_alloc_cos_queues(struct bnxt *bp)
330 rte_zmalloc("bnxt_rx_cosq",
331 BNXT_COS_QUEUE_COUNT *
332 sizeof(struct bnxt_cos_queue_info),
334 if (bp->rx_cos_queue == NULL)
338 rte_zmalloc("bnxt_tx_cosq",
339 BNXT_COS_QUEUE_COUNT *
340 sizeof(struct bnxt_cos_queue_info),
342 if (bp->tx_cos_queue == NULL)
348 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
350 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
351 sizeof(struct bnxt_flow_stat_info), 0);
352 if (bp->flow_stat == NULL)
358 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
362 rc = bnxt_alloc_ring_grps(bp);
366 rc = bnxt_alloc_async_ring_struct(bp);
370 rc = bnxt_alloc_vnic_mem(bp);
374 rc = bnxt_alloc_vnic_attributes(bp);
378 rc = bnxt_alloc_filter_mem(bp);
382 rc = bnxt_alloc_async_cp_ring(bp);
386 rc = bnxt_alloc_rxtx_nq_ring(bp);
390 if (BNXT_FLOW_XSTATS_EN(bp)) {
391 rc = bnxt_alloc_flow_stats_info(bp);
399 bnxt_free_mem(bp, reconfig);
403 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
405 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
406 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
407 uint64_t rx_offloads = dev_conf->rxmode.offloads;
408 struct bnxt_rx_queue *rxq;
412 rc = bnxt_vnic_grp_alloc(bp, vnic);
416 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
417 vnic_id, vnic, vnic->fw_grp_ids);
419 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
423 /* Alloc RSS context only if RSS mode is enabled */
424 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
425 int j, nr_ctxs = bnxt_rss_ctxts(bp);
428 for (j = 0; j < nr_ctxs; j++) {
429 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
435 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
439 vnic->num_lb_ctxts = nr_ctxs;
443 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
444 * setting is not available at this time, it will not be
445 * configured correctly in the CFA.
447 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
448 vnic->vlan_strip = true;
450 vnic->vlan_strip = false;
452 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
456 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
460 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
461 rxq = bp->eth_dev->data->rx_queues[j];
464 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
465 j, rxq->vnic, rxq->vnic->fw_grp_ids);
467 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
468 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
470 vnic->rx_queue_cnt++;
473 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
475 rc = bnxt_vnic_rss_configure(bp, vnic);
479 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
481 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
482 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
484 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
488 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
493 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
497 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
498 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
503 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
504 " rx_fc_in_tbl.ctx_id = %d\n",
505 bp->flow_stat->rx_fc_in_tbl.va,
506 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
507 bp->flow_stat->rx_fc_in_tbl.ctx_id);
509 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
510 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
515 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
516 " rx_fc_out_tbl.ctx_id = %d\n",
517 bp->flow_stat->rx_fc_out_tbl.va,
518 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
519 bp->flow_stat->rx_fc_out_tbl.ctx_id);
521 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
522 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
527 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
528 " tx_fc_in_tbl.ctx_id = %d\n",
529 bp->flow_stat->tx_fc_in_tbl.va,
530 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
531 bp->flow_stat->tx_fc_in_tbl.ctx_id);
533 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
534 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
539 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
540 " tx_fc_out_tbl.ctx_id = %d\n",
541 bp->flow_stat->tx_fc_out_tbl.va,
542 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
543 bp->flow_stat->tx_fc_out_tbl.ctx_id);
545 memset(bp->flow_stat->rx_fc_out_tbl.va,
547 bp->flow_stat->rx_fc_out_tbl.size);
548 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
549 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
550 bp->flow_stat->rx_fc_out_tbl.ctx_id,
551 bp->flow_stat->max_fc,
556 memset(bp->flow_stat->tx_fc_out_tbl.va,
558 bp->flow_stat->tx_fc_out_tbl.size);
559 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
560 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
561 bp->flow_stat->tx_fc_out_tbl.ctx_id,
562 bp->flow_stat->max_fc,
568 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
569 struct bnxt_ctx_mem_buf_info *ctx)
574 ctx->va = rte_zmalloc(type, size, 0);
577 rte_mem_lock_page(ctx->va);
579 ctx->dma = rte_mem_virt2iova(ctx->va);
580 if (ctx->dma == RTE_BAD_IOVA)
586 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
588 struct rte_pci_device *pdev = bp->pdev;
589 char type[RTE_MEMZONE_NAMESIZE];
593 max_fc = bp->flow_stat->max_fc;
595 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
596 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
597 /* 4 bytes for each counter-id */
598 rc = bnxt_alloc_ctx_mem_buf(type,
600 &bp->flow_stat->rx_fc_in_tbl);
604 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
605 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
606 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
607 rc = bnxt_alloc_ctx_mem_buf(type,
609 &bp->flow_stat->rx_fc_out_tbl);
613 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
614 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
615 /* 4 bytes for each counter-id */
616 rc = bnxt_alloc_ctx_mem_buf(type,
618 &bp->flow_stat->tx_fc_in_tbl);
622 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
623 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
624 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
625 rc = bnxt_alloc_ctx_mem_buf(type,
627 &bp->flow_stat->tx_fc_out_tbl);
631 rc = bnxt_register_fc_ctx_mem(bp);
636 static int bnxt_init_ctx_mem(struct bnxt *bp)
640 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
641 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
642 !BNXT_FLOW_XSTATS_EN(bp))
645 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
649 rc = bnxt_init_fc_ctx_mem(bp);
654 static int bnxt_update_phy_setting(struct bnxt *bp)
656 struct rte_eth_link new;
659 rc = bnxt_get_hwrm_link_config(bp, &new);
661 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
666 * On BCM957508-N2100 adapters, FW will not allow any user other
667 * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
668 * always returns link up. Force phy update always in that case.
670 if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
671 rc = bnxt_set_hwrm_link_config(bp, true);
673 PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
681 static int bnxt_init_chip(struct bnxt *bp)
683 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
684 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
685 uint32_t intr_vector = 0;
686 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
687 uint32_t vec = BNXT_MISC_VEC_ID;
691 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
692 bp->eth_dev->data->dev_conf.rxmode.offloads |=
693 DEV_RX_OFFLOAD_JUMBO_FRAME;
694 bp->flags |= BNXT_FLAG_JUMBO;
696 bp->eth_dev->data->dev_conf.rxmode.offloads &=
697 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
698 bp->flags &= ~BNXT_FLAG_JUMBO;
701 /* THOR does not support ring groups.
702 * But we will use the array to save RSS context IDs.
704 if (BNXT_CHIP_THOR(bp))
705 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
707 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
709 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
713 rc = bnxt_alloc_hwrm_rings(bp);
715 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
719 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
721 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
725 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
728 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
729 if (bp->rx_cos_queue[i].id != 0xff) {
730 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
734 "Num pools more than FW profile\n");
738 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
744 rc = bnxt_mq_rx_configure(bp);
746 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
750 /* VNIC configuration */
751 for (i = 0; i < bp->nr_vnics; i++) {
752 rc = bnxt_setup_one_vnic(bp, i);
757 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
760 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
764 /* check and configure queue intr-vector mapping */
765 if ((rte_intr_cap_multiple(intr_handle) ||
766 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
767 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
768 intr_vector = bp->eth_dev->data->nb_rx_queues;
769 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
770 if (intr_vector > bp->rx_cp_nr_rings) {
771 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
775 rc = rte_intr_efd_enable(intr_handle, intr_vector);
780 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
781 intr_handle->intr_vec =
782 rte_zmalloc("intr_vec",
783 bp->eth_dev->data->nb_rx_queues *
785 if (intr_handle->intr_vec == NULL) {
786 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
787 " intr_vec", bp->eth_dev->data->nb_rx_queues);
791 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
792 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
793 intr_handle->intr_vec, intr_handle->nb_efd,
794 intr_handle->max_intr);
795 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
797 intr_handle->intr_vec[queue_id] =
798 vec + BNXT_RX_VEC_START;
799 if (vec < base + intr_handle->nb_efd - 1)
804 /* enable uio/vfio intr/eventfd mapping */
805 rc = rte_intr_enable(intr_handle);
806 #ifndef RTE_EXEC_ENV_FREEBSD
807 /* In FreeBSD OS, nic_uio driver does not support interrupts */
812 rc = bnxt_update_phy_setting(bp);
816 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
818 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
823 rte_free(intr_handle->intr_vec);
825 rte_intr_efd_disable(intr_handle);
827 /* Some of the error status returned by FW may not be from errno.h */
834 static int bnxt_shutdown_nic(struct bnxt *bp)
836 bnxt_free_all_hwrm_resources(bp);
837 bnxt_free_all_filters(bp);
838 bnxt_free_all_vnics(bp);
843 * Device configuration and status function
846 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
848 uint32_t link_speed = bp->link_info->support_speeds;
849 uint32_t speed_capa = 0;
851 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
852 speed_capa |= ETH_LINK_SPEED_100M;
853 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
854 speed_capa |= ETH_LINK_SPEED_100M_HD;
855 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
856 speed_capa |= ETH_LINK_SPEED_1G;
857 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
858 speed_capa |= ETH_LINK_SPEED_2_5G;
859 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
860 speed_capa |= ETH_LINK_SPEED_10G;
861 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
862 speed_capa |= ETH_LINK_SPEED_20G;
863 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
864 speed_capa |= ETH_LINK_SPEED_25G;
865 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
866 speed_capa |= ETH_LINK_SPEED_40G;
867 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
868 speed_capa |= ETH_LINK_SPEED_50G;
869 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
870 speed_capa |= ETH_LINK_SPEED_100G;
871 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
872 speed_capa |= ETH_LINK_SPEED_50G;
873 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
874 speed_capa |= ETH_LINK_SPEED_100G;
875 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
876 speed_capa |= ETH_LINK_SPEED_200G;
878 if (bp->link_info->auto_mode ==
879 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
880 speed_capa |= ETH_LINK_SPEED_FIXED;
882 speed_capa |= ETH_LINK_SPEED_AUTONEG;
887 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
888 struct rte_eth_dev_info *dev_info)
890 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
891 struct bnxt *bp = eth_dev->data->dev_private;
892 uint16_t max_vnics, i, j, vpool, vrxq;
893 unsigned int max_rx_rings;
896 rc = is_bnxt_in_error(bp);
901 dev_info->max_mac_addrs = bp->max_l2_ctx;
902 dev_info->max_hash_mac_addrs = 0;
904 /* PF/VF specifics */
906 dev_info->max_vfs = pdev->max_vfs;
908 max_rx_rings = BNXT_MAX_RINGS(bp);
909 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
910 dev_info->max_rx_queues = max_rx_rings;
911 dev_info->max_tx_queues = max_rx_rings;
912 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
913 dev_info->hash_key_size = 40;
914 max_vnics = bp->max_vnics;
917 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
918 dev_info->max_mtu = BNXT_MAX_MTU;
920 /* Fast path specifics */
921 dev_info->min_rx_bufsize = 1;
922 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
924 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
925 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
926 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
927 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
928 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
929 dev_info->tx_queue_offload_capa;
930 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
932 dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
935 dev_info->default_rxconf = (struct rte_eth_rxconf) {
941 .rx_free_thresh = 32,
942 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
945 dev_info->default_txconf = (struct rte_eth_txconf) {
951 .tx_free_thresh = 32,
954 eth_dev->data->dev_conf.intr_conf.lsc = 1;
956 eth_dev->data->dev_conf.intr_conf.rxq = 1;
957 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
958 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
959 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
960 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
962 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
963 dev_info->switch_info.name = eth_dev->device->name;
964 dev_info->switch_info.domain_id = bp->switch_domain_id;
965 dev_info->switch_info.port_id =
966 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
967 BNXT_SWITCH_PORT_ID_TRUSTED_VF;
973 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
974 * need further investigation.
978 vpool = 64; /* ETH_64_POOLS */
979 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
980 for (i = 0; i < 4; vpool >>= 1, i++) {
981 if (max_vnics > vpool) {
982 for (j = 0; j < 5; vrxq >>= 1, j++) {
983 if (dev_info->max_rx_queues > vrxq) {
989 /* Not enough resources to support VMDq */
993 /* Not enough resources to support VMDq */
997 dev_info->max_vmdq_pools = vpool;
998 dev_info->vmdq_queue_num = vrxq;
1000 dev_info->vmdq_pool_base = 0;
1001 dev_info->vmdq_queue_base = 0;
1006 /* Configure the device based on the configuration provided */
1007 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1009 struct bnxt *bp = eth_dev->data->dev_private;
1010 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1013 bp->rx_queues = (void *)eth_dev->data->rx_queues;
1014 bp->tx_queues = (void *)eth_dev->data->tx_queues;
1015 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1016 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1018 rc = is_bnxt_in_error(bp);
1022 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1023 rc = bnxt_hwrm_check_vf_rings(bp);
1025 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1029 /* If a resource has already been allocated - in this case
1030 * it is the async completion ring, free it. Reallocate it after
1031 * resource reservation. This will ensure the resource counts
1032 * are calculated correctly.
1035 pthread_mutex_lock(&bp->def_cp_lock);
1037 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1038 bnxt_disable_int(bp);
1039 bnxt_free_cp_ring(bp, bp->async_cp_ring);
1042 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1044 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1045 pthread_mutex_unlock(&bp->def_cp_lock);
1049 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1050 rc = bnxt_alloc_async_cp_ring(bp);
1052 pthread_mutex_unlock(&bp->def_cp_lock);
1055 bnxt_enable_int(bp);
1058 pthread_mutex_unlock(&bp->def_cp_lock);
1060 /* legacy driver needs to get updated values */
1061 rc = bnxt_hwrm_func_qcaps(bp);
1063 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
1068 /* Inherit new configurations */
1069 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1070 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1071 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1072 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1073 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1075 goto resource_error;
1077 if (BNXT_HAS_RING_GRPS(bp) &&
1078 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1079 goto resource_error;
1081 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1082 bp->max_vnics < eth_dev->data->nb_rx_queues)
1083 goto resource_error;
1085 bp->rx_cp_nr_rings = bp->rx_nr_rings;
1086 bp->tx_cp_nr_rings = bp->tx_nr_rings;
1088 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1089 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1090 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1092 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1093 eth_dev->data->mtu =
1094 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1095 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1097 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1103 "Insufficient resources to support requested config\n");
1105 "Num Queues Requested: Tx %d, Rx %d\n",
1106 eth_dev->data->nb_tx_queues,
1107 eth_dev->data->nb_rx_queues);
1109 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1110 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1111 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1115 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1117 struct rte_eth_link *link = ð_dev->data->dev_link;
1119 if (link->link_status)
1120 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1121 eth_dev->data->port_id,
1122 (uint32_t)link->link_speed,
1123 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1124 ("full-duplex") : ("half-duplex\n"));
1126 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1127 eth_dev->data->port_id);
1131 * Determine whether the current configuration requires support for scattered
1132 * receive; return 1 if scattered receive is required and 0 if not.
1134 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1139 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1142 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1143 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1145 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1146 RTE_PKTMBUF_HEADROOM);
1147 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1153 static eth_rx_burst_t
1154 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1156 struct bnxt *bp = eth_dev->data->dev_private;
1158 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1159 #ifndef RTE_LIBRTE_IEEE1588
1161 * Vector mode receive can be enabled only if scatter rx is not
1162 * in use and rx offloads are limited to VLAN stripping and
1165 if (!eth_dev->data->scattered_rx &&
1166 !(eth_dev->data->dev_conf.rxmode.offloads &
1167 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1168 DEV_RX_OFFLOAD_KEEP_CRC |
1169 DEV_RX_OFFLOAD_JUMBO_FRAME |
1170 DEV_RX_OFFLOAD_IPV4_CKSUM |
1171 DEV_RX_OFFLOAD_UDP_CKSUM |
1172 DEV_RX_OFFLOAD_TCP_CKSUM |
1173 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1174 DEV_RX_OFFLOAD_RSS_HASH |
1175 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1176 !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp) &&
1177 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1178 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1179 eth_dev->data->port_id);
1180 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1181 return bnxt_recv_pkts_vec;
1183 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1184 eth_dev->data->port_id);
1186 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1187 eth_dev->data->port_id,
1188 eth_dev->data->scattered_rx,
1189 eth_dev->data->dev_conf.rxmode.offloads);
1192 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1193 return bnxt_recv_pkts;
1196 static eth_tx_burst_t
1197 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1199 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1200 #ifndef RTE_LIBRTE_IEEE1588
1201 uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1202 struct bnxt *bp = eth_dev->data->dev_private;
1205 * Vector mode transmit can be enabled only if not using scatter rx
1208 if (!eth_dev->data->scattered_rx &&
1209 !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
1210 !BNXT_TRUFLOW_EN(bp) &&
1211 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1212 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1213 eth_dev->data->port_id);
1214 return bnxt_xmit_pkts_vec;
1216 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1217 eth_dev->data->port_id);
1219 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1220 eth_dev->data->port_id,
1221 eth_dev->data->scattered_rx,
1225 return bnxt_xmit_pkts;
1228 static int bnxt_handle_if_change_status(struct bnxt *bp)
1232 /* Since fw has undergone a reset and lost all contexts,
1233 * set fatal flag to not issue hwrm during cleanup
1235 bp->flags |= BNXT_FLAG_FATAL_ERROR;
1236 bnxt_uninit_resources(bp, true);
1238 /* clear fatal flag so that re-init happens */
1239 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1240 rc = bnxt_init_resources(bp, true);
1242 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1247 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1249 struct bnxt *bp = eth_dev->data->dev_private;
1250 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1252 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1254 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1255 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1259 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1261 "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1262 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1266 rc = bnxt_hwrm_if_change(bp, true);
1267 if (rc == 0 || rc != -EAGAIN)
1270 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1271 } while (retry_cnt--);
1276 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1277 rc = bnxt_handle_if_change_status(bp);
1282 bnxt_enable_int(bp);
1284 rc = bnxt_init_chip(bp);
1288 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1289 eth_dev->data->dev_started = 1;
1291 bnxt_link_update_op(eth_dev, 1);
1293 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1294 vlan_mask |= ETH_VLAN_FILTER_MASK;
1295 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1296 vlan_mask |= ETH_VLAN_STRIP_MASK;
1297 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1301 /* Initialize bnxt ULP port details */
1302 rc = bnxt_ulp_port_init(bp);
1306 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1307 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1309 bnxt_schedule_fw_health_check(bp);
1314 bnxt_shutdown_nic(bp);
1315 bnxt_free_tx_mbufs(bp);
1316 bnxt_free_rx_mbufs(bp);
1317 bnxt_hwrm_if_change(bp, false);
1318 eth_dev->data->dev_started = 0;
1322 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1324 struct bnxt *bp = eth_dev->data->dev_private;
1327 if (!bp->link_info->link_up)
1328 rc = bnxt_set_hwrm_link_config(bp, true);
1330 eth_dev->data->dev_link.link_status = 1;
1332 bnxt_print_link_info(eth_dev);
1336 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1338 struct bnxt *bp = eth_dev->data->dev_private;
1340 eth_dev->data->dev_link.link_status = 0;
1341 bnxt_set_hwrm_link_config(bp, false);
1342 bp->link_info->link_up = 0;
1347 static void bnxt_free_switch_domain(struct bnxt *bp)
1351 if (bp->switch_domain_id) {
1352 rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1354 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1355 bp->switch_domain_id, rc);
1359 /* Unload the driver, release resources */
1360 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1362 struct bnxt *bp = eth_dev->data->dev_private;
1363 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1364 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1365 struct rte_eth_link link;
1368 eth_dev->data->dev_started = 0;
1369 eth_dev->data->scattered_rx = 0;
1371 /* Prevent crashes when queues are still in use */
1372 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1373 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1375 bnxt_disable_int(bp);
1377 /* disable uio/vfio intr/eventfd mapping */
1378 rte_intr_disable(intr_handle);
1380 /* Stop the child representors for this device */
1381 ret = bnxt_rep_stop_all(bp);
1385 /* delete the bnxt ULP port details */
1386 bnxt_ulp_port_deinit(bp);
1388 bnxt_cancel_fw_health_check(bp);
1390 /* Do not bring link down during reset recovery */
1391 if (!is_bnxt_in_error(bp)) {
1392 bnxt_dev_set_link_down_op(eth_dev);
1393 /* Wait for link to be reset */
1394 if (BNXT_SINGLE_PF(bp))
1396 /* clear the recorded link status */
1397 memset(&link, 0, sizeof(link));
1398 rte_eth_linkstatus_set(eth_dev, &link);
1401 /* Clean queue intr-vector mapping */
1402 rte_intr_efd_disable(intr_handle);
1403 if (intr_handle->intr_vec != NULL) {
1404 rte_free(intr_handle->intr_vec);
1405 intr_handle->intr_vec = NULL;
1408 bnxt_hwrm_port_clr_stats(bp);
1409 bnxt_free_tx_mbufs(bp);
1410 bnxt_free_rx_mbufs(bp);
1411 /* Process any remaining notifications in default completion queue */
1412 bnxt_int_handler(eth_dev);
1413 bnxt_shutdown_nic(bp);
1414 bnxt_hwrm_if_change(bp, false);
1416 rte_free(bp->mark_table);
1417 bp->mark_table = NULL;
1419 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1420 bp->rx_cosq_cnt = 0;
1421 /* All filters are deleted on a port stop. */
1422 if (BNXT_FLOW_XSTATS_EN(bp))
1423 bp->flow_stat->flow_count = 0;
1428 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1430 struct bnxt *bp = eth_dev->data->dev_private;
1433 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1436 /* cancel the recovery handler before remove dev */
1437 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1438 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1439 bnxt_cancel_fc_thread(bp);
1441 if (eth_dev->data->dev_started)
1442 ret = bnxt_dev_stop_op(eth_dev);
1444 bnxt_free_switch_domain(bp);
1446 bnxt_uninit_resources(bp, false);
1448 bnxt_free_leds_info(bp);
1449 bnxt_free_cos_queues(bp);
1450 bnxt_free_link_info(bp);
1451 bnxt_free_pf_info(bp);
1452 bnxt_free_parent_info(bp);
1454 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1455 bp->tx_mem_zone = NULL;
1456 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1457 bp->rx_mem_zone = NULL;
1459 bnxt_hwrm_free_vf_info(bp);
1461 rte_free(bp->grp_info);
1462 bp->grp_info = NULL;
1467 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1470 struct bnxt *bp = eth_dev->data->dev_private;
1471 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1472 struct bnxt_vnic_info *vnic;
1473 struct bnxt_filter_info *filter, *temp_filter;
1476 if (is_bnxt_in_error(bp))
1480 * Loop through all VNICs from the specified filter flow pools to
1481 * remove the corresponding MAC addr filter
1483 for (i = 0; i < bp->nr_vnics; i++) {
1484 if (!(pool_mask & (1ULL << i)))
1487 vnic = &bp->vnic_info[i];
1488 filter = STAILQ_FIRST(&vnic->filter);
1490 temp_filter = STAILQ_NEXT(filter, next);
1491 if (filter->mac_index == index) {
1492 STAILQ_REMOVE(&vnic->filter, filter,
1493 bnxt_filter_info, next);
1494 bnxt_hwrm_clear_l2_filter(bp, filter);
1495 bnxt_free_filter(bp, filter);
1497 filter = temp_filter;
1502 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1503 struct rte_ether_addr *mac_addr, uint32_t index,
1506 struct bnxt_filter_info *filter;
1509 /* Attach requested MAC address to the new l2_filter */
1510 STAILQ_FOREACH(filter, &vnic->filter, next) {
1511 if (filter->mac_index == index) {
1513 "MAC addr already existed for pool %d\n",
1519 filter = bnxt_alloc_filter(bp);
1521 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1525 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1526 * if the MAC that's been programmed now is a different one, then,
1527 * copy that addr to filter->l2_addr
1530 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1531 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1533 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1535 filter->mac_index = index;
1536 if (filter->mac_index == 0)
1537 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1539 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1541 bnxt_free_filter(bp, filter);
1547 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1548 struct rte_ether_addr *mac_addr,
1549 uint32_t index, uint32_t pool)
1551 struct bnxt *bp = eth_dev->data->dev_private;
1552 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1555 rc = is_bnxt_in_error(bp);
1559 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1560 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1565 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1569 /* Filter settings will get applied when port is started */
1570 if (!eth_dev->data->dev_started)
1573 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1578 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1581 struct bnxt *bp = eth_dev->data->dev_private;
1582 struct rte_eth_link new;
1583 int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1584 BNXT_MIN_LINK_WAIT_CNT;
1586 rc = is_bnxt_in_error(bp);
1590 memset(&new, 0, sizeof(new));
1592 /* Retrieve link info from hardware */
1593 rc = bnxt_get_hwrm_link_config(bp, &new);
1595 new.link_speed = ETH_LINK_SPEED_100M;
1596 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1598 "Failed to retrieve link rc = 0x%x!\n", rc);
1602 if (!wait_to_complete || new.link_status)
1605 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1608 /* Only single function PF can bring phy down.
1609 * When port is stopped, report link down for VF/MH/NPAR functions.
1611 if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1612 memset(&new, 0, sizeof(new));
1615 /* Timed out or success */
1616 if (new.link_status != eth_dev->data->dev_link.link_status ||
1617 new.link_speed != eth_dev->data->dev_link.link_speed) {
1618 rte_eth_linkstatus_set(eth_dev, &new);
1620 rte_eth_dev_callback_process(eth_dev,
1621 RTE_ETH_EVENT_INTR_LSC,
1624 bnxt_print_link_info(eth_dev);
1630 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1632 struct bnxt *bp = eth_dev->data->dev_private;
1633 struct bnxt_vnic_info *vnic;
1637 rc = is_bnxt_in_error(bp);
1641 /* Filter settings will get applied when port is started */
1642 if (!eth_dev->data->dev_started)
1645 if (bp->vnic_info == NULL)
1648 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1650 old_flags = vnic->flags;
1651 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1652 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1654 vnic->flags = old_flags;
1659 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1661 struct bnxt *bp = eth_dev->data->dev_private;
1662 struct bnxt_vnic_info *vnic;
1666 rc = is_bnxt_in_error(bp);
1670 /* Filter settings will get applied when port is started */
1671 if (!eth_dev->data->dev_started)
1674 if (bp->vnic_info == NULL)
1677 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1679 old_flags = vnic->flags;
1680 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1681 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1683 vnic->flags = old_flags;
1688 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1690 struct bnxt *bp = eth_dev->data->dev_private;
1691 struct bnxt_vnic_info *vnic;
1695 rc = is_bnxt_in_error(bp);
1699 /* Filter settings will get applied when port is started */
1700 if (!eth_dev->data->dev_started)
1703 if (bp->vnic_info == NULL)
1706 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1708 old_flags = vnic->flags;
1709 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1710 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1712 vnic->flags = old_flags;
1717 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1719 struct bnxt *bp = eth_dev->data->dev_private;
1720 struct bnxt_vnic_info *vnic;
1724 rc = is_bnxt_in_error(bp);
1728 /* Filter settings will get applied when port is started */
1729 if (!eth_dev->data->dev_started)
1732 if (bp->vnic_info == NULL)
1735 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1737 old_flags = vnic->flags;
1738 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1739 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1741 vnic->flags = old_flags;
1746 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1747 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1749 if (qid >= bp->rx_nr_rings)
1752 return bp->eth_dev->data->rx_queues[qid];
1755 /* Return rxq corresponding to a given rss table ring/group ID. */
1756 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1758 struct bnxt_rx_queue *rxq;
1761 if (!BNXT_HAS_RING_GRPS(bp)) {
1762 for (i = 0; i < bp->rx_nr_rings; i++) {
1763 rxq = bp->eth_dev->data->rx_queues[i];
1764 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1768 for (i = 0; i < bp->rx_nr_rings; i++) {
1769 if (bp->grp_info[i].fw_grp_id == fwr)
1774 return INVALID_HW_RING_ID;
1777 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1778 struct rte_eth_rss_reta_entry64 *reta_conf,
1781 struct bnxt *bp = eth_dev->data->dev_private;
1782 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1783 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1784 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1788 rc = is_bnxt_in_error(bp);
1792 if (!vnic->rss_table)
1795 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1798 if (reta_size != tbl_size) {
1799 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1800 "(%d) must equal the size supported by the hardware "
1801 "(%d)\n", reta_size, tbl_size);
1805 for (i = 0; i < reta_size; i++) {
1806 struct bnxt_rx_queue *rxq;
1808 idx = i / RTE_RETA_GROUP_SIZE;
1809 sft = i % RTE_RETA_GROUP_SIZE;
1811 if (!(reta_conf[idx].mask & (1ULL << sft)))
1814 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1816 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1820 if (BNXT_CHIP_THOR(bp)) {
1821 vnic->rss_table[i * 2] =
1822 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1823 vnic->rss_table[i * 2 + 1] =
1824 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1826 vnic->rss_table[i] =
1827 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1831 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1835 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1836 struct rte_eth_rss_reta_entry64 *reta_conf,
1839 struct bnxt *bp = eth_dev->data->dev_private;
1840 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1841 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1842 uint16_t idx, sft, i;
1845 rc = is_bnxt_in_error(bp);
1849 /* Retrieve from the default VNIC */
1852 if (!vnic->rss_table)
1855 if (reta_size != tbl_size) {
1856 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1857 "(%d) must equal the size supported by the hardware "
1858 "(%d)\n", reta_size, tbl_size);
1862 for (idx = 0, i = 0; i < reta_size; i++) {
1863 idx = i / RTE_RETA_GROUP_SIZE;
1864 sft = i % RTE_RETA_GROUP_SIZE;
1866 if (reta_conf[idx].mask & (1ULL << sft)) {
1869 if (BNXT_CHIP_THOR(bp))
1870 qid = bnxt_rss_to_qid(bp,
1871 vnic->rss_table[i * 2]);
1873 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1875 if (qid == INVALID_HW_RING_ID) {
1876 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1879 reta_conf[idx].reta[sft] = qid;
1886 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1887 struct rte_eth_rss_conf *rss_conf)
1889 struct bnxt *bp = eth_dev->data->dev_private;
1890 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1891 struct bnxt_vnic_info *vnic;
1894 rc = is_bnxt_in_error(bp);
1899 * If RSS enablement were different than dev_configure,
1900 * then return -EINVAL
1902 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1903 if (!rss_conf->rss_hf)
1904 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1906 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1910 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1911 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf,
1915 /* Update the default RSS VNIC(s) */
1916 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1917 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1919 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
1920 ETH_RSS_LEVEL(rss_conf->rss_hf));
1923 * If hashkey is not specified, use the previously configured
1926 if (!rss_conf->rss_key)
1929 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1931 "Invalid hashkey length, should be 16 bytes\n");
1934 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1937 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1941 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1942 struct rte_eth_rss_conf *rss_conf)
1944 struct bnxt *bp = eth_dev->data->dev_private;
1945 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1947 uint32_t hash_types;
1949 rc = is_bnxt_in_error(bp);
1953 /* RSS configuration is the same for all VNICs */
1954 if (vnic && vnic->rss_hash_key) {
1955 if (rss_conf->rss_key) {
1956 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1957 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1958 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1961 hash_types = vnic->hash_type;
1962 rss_conf->rss_hf = 0;
1963 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1964 rss_conf->rss_hf |= ETH_RSS_IPV4;
1965 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1967 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1968 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1970 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1972 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1973 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1975 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1977 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1978 rss_conf->rss_hf |= ETH_RSS_IPV6;
1979 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1981 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1982 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1984 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1986 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1987 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1989 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1993 bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
1997 "Unknown RSS config from firmware (%08x), RSS disabled",
2002 rss_conf->rss_hf = 0;
2007 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2008 struct rte_eth_fc_conf *fc_conf)
2010 struct bnxt *bp = dev->data->dev_private;
2011 struct rte_eth_link link_info;
2014 rc = is_bnxt_in_error(bp);
2018 rc = bnxt_get_hwrm_link_config(bp, &link_info);
2022 memset(fc_conf, 0, sizeof(*fc_conf));
2023 if (bp->link_info->auto_pause)
2024 fc_conf->autoneg = 1;
2025 switch (bp->link_info->pause) {
2027 fc_conf->mode = RTE_FC_NONE;
2029 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2030 fc_conf->mode = RTE_FC_TX_PAUSE;
2032 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2033 fc_conf->mode = RTE_FC_RX_PAUSE;
2035 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2036 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2037 fc_conf->mode = RTE_FC_FULL;
2043 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2044 struct rte_eth_fc_conf *fc_conf)
2046 struct bnxt *bp = dev->data->dev_private;
2049 rc = is_bnxt_in_error(bp);
2053 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2054 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2058 switch (fc_conf->mode) {
2060 bp->link_info->auto_pause = 0;
2061 bp->link_info->force_pause = 0;
2063 case RTE_FC_RX_PAUSE:
2064 if (fc_conf->autoneg) {
2065 bp->link_info->auto_pause =
2066 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2067 bp->link_info->force_pause = 0;
2069 bp->link_info->auto_pause = 0;
2070 bp->link_info->force_pause =
2071 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2074 case RTE_FC_TX_PAUSE:
2075 if (fc_conf->autoneg) {
2076 bp->link_info->auto_pause =
2077 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2078 bp->link_info->force_pause = 0;
2080 bp->link_info->auto_pause = 0;
2081 bp->link_info->force_pause =
2082 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2086 if (fc_conf->autoneg) {
2087 bp->link_info->auto_pause =
2088 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2089 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2090 bp->link_info->force_pause = 0;
2092 bp->link_info->auto_pause = 0;
2093 bp->link_info->force_pause =
2094 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2095 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2099 return bnxt_set_hwrm_link_config(bp, true);
2102 /* Add UDP tunneling port */
2104 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2105 struct rte_eth_udp_tunnel *udp_tunnel)
2107 struct bnxt *bp = eth_dev->data->dev_private;
2108 uint16_t tunnel_type = 0;
2111 rc = is_bnxt_in_error(bp);
2115 switch (udp_tunnel->prot_type) {
2116 case RTE_TUNNEL_TYPE_VXLAN:
2117 if (bp->vxlan_port_cnt) {
2118 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2119 udp_tunnel->udp_port);
2120 if (bp->vxlan_port != udp_tunnel->udp_port) {
2121 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2124 bp->vxlan_port_cnt++;
2128 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2129 bp->vxlan_port_cnt++;
2131 case RTE_TUNNEL_TYPE_GENEVE:
2132 if (bp->geneve_port_cnt) {
2133 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2134 udp_tunnel->udp_port);
2135 if (bp->geneve_port != udp_tunnel->udp_port) {
2136 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2139 bp->geneve_port_cnt++;
2143 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2144 bp->geneve_port_cnt++;
2147 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2150 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2156 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2157 struct rte_eth_udp_tunnel *udp_tunnel)
2159 struct bnxt *bp = eth_dev->data->dev_private;
2160 uint16_t tunnel_type = 0;
2164 rc = is_bnxt_in_error(bp);
2168 switch (udp_tunnel->prot_type) {
2169 case RTE_TUNNEL_TYPE_VXLAN:
2170 if (!bp->vxlan_port_cnt) {
2171 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2174 if (bp->vxlan_port != udp_tunnel->udp_port) {
2175 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2176 udp_tunnel->udp_port, bp->vxlan_port);
2179 if (--bp->vxlan_port_cnt)
2183 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2184 port = bp->vxlan_fw_dst_port_id;
2186 case RTE_TUNNEL_TYPE_GENEVE:
2187 if (!bp->geneve_port_cnt) {
2188 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2191 if (bp->geneve_port != udp_tunnel->udp_port) {
2192 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2193 udp_tunnel->udp_port, bp->geneve_port);
2196 if (--bp->geneve_port_cnt)
2200 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2201 port = bp->geneve_fw_dst_port_id;
2204 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2208 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2212 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2214 struct bnxt_filter_info *filter;
2215 struct bnxt_vnic_info *vnic;
2217 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2219 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2220 filter = STAILQ_FIRST(&vnic->filter);
2222 /* Search for this matching MAC+VLAN filter */
2223 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2224 /* Delete the filter */
2225 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2228 STAILQ_REMOVE(&vnic->filter, filter,
2229 bnxt_filter_info, next);
2230 bnxt_free_filter(bp, filter);
2232 "Deleted vlan filter for %d\n",
2236 filter = STAILQ_NEXT(filter, next);
2241 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2243 struct bnxt_filter_info *filter;
2244 struct bnxt_vnic_info *vnic;
2246 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2247 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2248 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2250 /* Implementation notes on the use of VNIC in this command:
2252 * By default, these filters belong to default vnic for the function.
2253 * Once these filters are set up, only destination VNIC can be modified.
2254 * If the destination VNIC is not specified in this command,
2255 * then the HWRM shall only create an l2 context id.
2258 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2259 filter = STAILQ_FIRST(&vnic->filter);
2260 /* Check if the VLAN has already been added */
2262 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2265 filter = STAILQ_NEXT(filter, next);
2268 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2269 * command to create MAC+VLAN filter with the right flags, enables set.
2271 filter = bnxt_alloc_filter(bp);
2274 "MAC/VLAN filter alloc failed\n");
2277 /* MAC + VLAN ID filter */
2278 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2279 * untagged packets are received
2281 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2282 * packets and only the programmed vlan's packets are received
2284 filter->l2_ivlan = vlan_id;
2285 filter->l2_ivlan_mask = 0x0FFF;
2286 filter->enables |= en;
2287 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2289 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2291 /* Free the newly allocated filter as we were
2292 * not able to create the filter in hardware.
2294 bnxt_free_filter(bp, filter);
2298 filter->mac_index = 0;
2299 /* Add this new filter to the list */
2301 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2303 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2306 "Added Vlan filter for %d\n", vlan_id);
2310 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2311 uint16_t vlan_id, int on)
2313 struct bnxt *bp = eth_dev->data->dev_private;
2316 rc = is_bnxt_in_error(bp);
2320 if (!eth_dev->data->dev_started) {
2321 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2325 /* These operations apply to ALL existing MAC/VLAN filters */
2327 return bnxt_add_vlan_filter(bp, vlan_id);
2329 return bnxt_del_vlan_filter(bp, vlan_id);
2332 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2333 struct bnxt_vnic_info *vnic)
2335 struct bnxt_filter_info *filter;
2338 filter = STAILQ_FIRST(&vnic->filter);
2340 if (filter->mac_index == 0 &&
2341 !memcmp(filter->l2_addr, bp->mac_addr,
2342 RTE_ETHER_ADDR_LEN)) {
2343 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2345 STAILQ_REMOVE(&vnic->filter, filter,
2346 bnxt_filter_info, next);
2347 bnxt_free_filter(bp, filter);
2351 filter = STAILQ_NEXT(filter, next);
2357 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2359 struct bnxt_vnic_info *vnic;
2363 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2364 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2365 /* Remove any VLAN filters programmed */
2366 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2367 bnxt_del_vlan_filter(bp, i);
2369 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2373 /* Default filter will allow packets that match the
2374 * dest mac. So, it has to be deleted, otherwise, we
2375 * will endup receiving vlan packets for which the
2376 * filter is not programmed, when hw-vlan-filter
2377 * configuration is ON
2379 bnxt_del_dflt_mac_filter(bp, vnic);
2380 /* This filter will allow only untagged packets */
2381 bnxt_add_vlan_filter(bp, 0);
2383 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2384 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2389 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2391 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2395 /* Destroy vnic filters and vnic */
2396 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2397 DEV_RX_OFFLOAD_VLAN_FILTER) {
2398 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2399 bnxt_del_vlan_filter(bp, i);
2401 bnxt_del_dflt_mac_filter(bp, vnic);
2403 rc = bnxt_hwrm_vnic_free(bp, vnic);
2407 rte_free(vnic->fw_grp_ids);
2408 vnic->fw_grp_ids = NULL;
2410 vnic->rx_queue_cnt = 0;
2416 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2418 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2421 /* Destroy, recreate and reconfigure the default vnic */
2422 rc = bnxt_free_one_vnic(bp, 0);
2426 /* default vnic 0 */
2427 rc = bnxt_setup_one_vnic(bp, 0);
2431 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2432 DEV_RX_OFFLOAD_VLAN_FILTER) {
2433 rc = bnxt_add_vlan_filter(bp, 0);
2436 rc = bnxt_restore_vlan_filters(bp);
2440 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2445 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2449 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2450 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2456 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2458 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2459 struct bnxt *bp = dev->data->dev_private;
2462 rc = is_bnxt_in_error(bp);
2466 /* Filter settings will get applied when port is started */
2467 if (!dev->data->dev_started)
2470 if (mask & ETH_VLAN_FILTER_MASK) {
2471 /* Enable or disable VLAN filtering */
2472 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2477 if (mask & ETH_VLAN_STRIP_MASK) {
2478 /* Enable or disable VLAN stripping */
2479 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2484 if (mask & ETH_VLAN_EXTEND_MASK) {
2485 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2486 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2488 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2495 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2498 struct bnxt *bp = dev->data->dev_private;
2499 int qinq = dev->data->dev_conf.rxmode.offloads &
2500 DEV_RX_OFFLOAD_VLAN_EXTEND;
2502 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2503 vlan_type != ETH_VLAN_TYPE_OUTER) {
2505 "Unsupported vlan type.");
2510 "QinQ not enabled. Needs to be ON as we can "
2511 "accelerate only outer vlan\n");
2515 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2517 case RTE_ETHER_TYPE_QINQ:
2519 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2521 case RTE_ETHER_TYPE_VLAN:
2523 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2525 case RTE_ETHER_TYPE_QINQ1:
2527 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2529 case RTE_ETHER_TYPE_QINQ2:
2531 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2533 case RTE_ETHER_TYPE_QINQ3:
2535 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2538 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2541 bp->outer_tpid_bd |= tpid;
2542 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2543 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2545 "Can accelerate only outer vlan in QinQ\n");
2553 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2554 struct rte_ether_addr *addr)
2556 struct bnxt *bp = dev->data->dev_private;
2557 /* Default Filter is tied to VNIC 0 */
2558 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2561 rc = is_bnxt_in_error(bp);
2565 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2568 if (rte_is_zero_ether_addr(addr))
2571 /* Filter settings will get applied when port is started */
2572 if (!dev->data->dev_started)
2575 /* Check if the requested MAC is already added */
2576 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2579 /* Destroy filter and re-create it */
2580 bnxt_del_dflt_mac_filter(bp, vnic);
2582 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2583 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2584 /* This filter will allow only untagged packets */
2585 rc = bnxt_add_vlan_filter(bp, 0);
2587 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2590 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2595 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2596 struct rte_ether_addr *mc_addr_set,
2597 uint32_t nb_mc_addr)
2599 struct bnxt *bp = eth_dev->data->dev_private;
2600 char *mc_addr_list = (char *)mc_addr_set;
2601 struct bnxt_vnic_info *vnic;
2602 uint32_t off = 0, i = 0;
2605 rc = is_bnxt_in_error(bp);
2609 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2611 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2612 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2616 /* TODO Check for Duplicate mcast addresses */
2617 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2618 for (i = 0; i < nb_mc_addr; i++) {
2619 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2620 RTE_ETHER_ADDR_LEN);
2621 off += RTE_ETHER_ADDR_LEN;
2624 vnic->mc_addr_cnt = i;
2625 if (vnic->mc_addr_cnt)
2626 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2628 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2631 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2635 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2637 struct bnxt *bp = dev->data->dev_private;
2638 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2639 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2640 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2641 uint8_t fw_rsvd = bp->fw_ver & 0xff;
2644 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2645 fw_major, fw_minor, fw_updt, fw_rsvd);
2647 ret += 1; /* add the size of '\0' */
2648 if (fw_size < (uint32_t)ret)
2655 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2656 struct rte_eth_rxq_info *qinfo)
2658 struct bnxt *bp = dev->data->dev_private;
2659 struct bnxt_rx_queue *rxq;
2661 if (is_bnxt_in_error(bp))
2664 rxq = dev->data->rx_queues[queue_id];
2666 qinfo->mp = rxq->mb_pool;
2667 qinfo->scattered_rx = dev->data->scattered_rx;
2668 qinfo->nb_desc = rxq->nb_rx_desc;
2670 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2671 qinfo->conf.rx_drop_en = rxq->drop_en;
2672 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2673 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2677 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2678 struct rte_eth_txq_info *qinfo)
2680 struct bnxt *bp = dev->data->dev_private;
2681 struct bnxt_tx_queue *txq;
2683 if (is_bnxt_in_error(bp))
2686 txq = dev->data->tx_queues[queue_id];
2688 qinfo->nb_desc = txq->nb_tx_desc;
2690 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2691 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2692 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2694 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2695 qinfo->conf.tx_rs_thresh = 0;
2696 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2697 qinfo->conf.offloads = txq->offloads;
2700 static const struct {
2701 eth_rx_burst_t pkt_burst;
2703 } bnxt_rx_burst_info[] = {
2704 {bnxt_recv_pkts, "Scalar"},
2705 #if defined(RTE_ARCH_X86)
2706 {bnxt_recv_pkts_vec, "Vector SSE"},
2707 #elif defined(RTE_ARCH_ARM64)
2708 {bnxt_recv_pkts_vec, "Vector Neon"},
2713 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2714 struct rte_eth_burst_mode *mode)
2716 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2719 for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2720 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2721 snprintf(mode->info, sizeof(mode->info), "%s",
2722 bnxt_rx_burst_info[i].info);
2730 static const struct {
2731 eth_tx_burst_t pkt_burst;
2733 } bnxt_tx_burst_info[] = {
2734 {bnxt_xmit_pkts, "Scalar"},
2735 #if defined(RTE_ARCH_X86)
2736 {bnxt_xmit_pkts_vec, "Vector SSE"},
2737 #elif defined(RTE_ARCH_ARM64)
2738 {bnxt_xmit_pkts_vec, "Vector Neon"},
2743 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2744 struct rte_eth_burst_mode *mode)
2746 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2749 for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2750 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2751 snprintf(mode->info, sizeof(mode->info), "%s",
2752 bnxt_tx_burst_info[i].info);
2760 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2762 struct bnxt *bp = eth_dev->data->dev_private;
2763 uint32_t new_pkt_size;
2767 rc = is_bnxt_in_error(bp);
2771 /* Exit if receive queues are not configured yet */
2772 if (!eth_dev->data->nb_rx_queues)
2775 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2776 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2779 * Disallow any MTU change that would require scattered receive support
2780 * if it is not already enabled.
2782 if (eth_dev->data->dev_started &&
2783 !eth_dev->data->scattered_rx &&
2785 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2787 "MTU change would require scattered rx support. ");
2788 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2792 if (new_mtu > RTE_ETHER_MTU) {
2793 bp->flags |= BNXT_FLAG_JUMBO;
2794 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2795 DEV_RX_OFFLOAD_JUMBO_FRAME;
2797 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2798 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2799 bp->flags &= ~BNXT_FLAG_JUMBO;
2802 /* Is there a change in mtu setting? */
2803 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2806 for (i = 0; i < bp->nr_vnics; i++) {
2807 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2810 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2811 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2815 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2816 size -= RTE_PKTMBUF_HEADROOM;
2818 if (size < new_mtu) {
2819 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2826 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2828 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2834 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2836 struct bnxt *bp = dev->data->dev_private;
2837 uint16_t vlan = bp->vlan;
2840 rc = is_bnxt_in_error(bp);
2844 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2846 "PVID cannot be modified for this function\n");
2849 bp->vlan = on ? pvid : 0;
2851 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2858 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2860 struct bnxt *bp = dev->data->dev_private;
2863 rc = is_bnxt_in_error(bp);
2867 return bnxt_hwrm_port_led_cfg(bp, true);
2871 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2873 struct bnxt *bp = dev->data->dev_private;
2876 rc = is_bnxt_in_error(bp);
2880 return bnxt_hwrm_port_led_cfg(bp, false);
2884 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2886 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2887 uint32_t desc = 0, raw_cons = 0, cons;
2888 struct bnxt_cp_ring_info *cpr;
2889 struct bnxt_rx_queue *rxq;
2890 struct rx_pkt_cmpl *rxcmp;
2893 rc = is_bnxt_in_error(bp);
2897 rxq = dev->data->rx_queues[rx_queue_id];
2899 raw_cons = cpr->cp_raw_cons;
2902 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2903 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2904 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2906 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2918 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2920 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2921 struct bnxt_rx_ring_info *rxr;
2922 struct bnxt_cp_ring_info *cpr;
2923 struct rte_mbuf *rx_buf;
2924 struct rx_pkt_cmpl *rxcmp;
2925 uint32_t cons, cp_cons;
2931 rc = is_bnxt_in_error(rxq->bp);
2938 if (offset >= rxq->nb_rx_desc)
2941 cons = RING_CMP(cpr->cp_ring_struct, offset);
2942 cp_cons = cpr->cp_raw_cons;
2943 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2945 if (cons > cp_cons) {
2946 if (CMPL_VALID(rxcmp, cpr->valid))
2947 return RTE_ETH_RX_DESC_DONE;
2949 if (CMPL_VALID(rxcmp, !cpr->valid))
2950 return RTE_ETH_RX_DESC_DONE;
2952 rx_buf = rxr->rx_buf_ring[cons];
2953 if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf)
2954 return RTE_ETH_RX_DESC_UNAVAIL;
2957 return RTE_ETH_RX_DESC_AVAIL;
2961 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2963 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2964 struct bnxt_tx_ring_info *txr;
2965 struct bnxt_cp_ring_info *cpr;
2966 struct bnxt_sw_tx_bd *tx_buf;
2967 struct tx_pkt_cmpl *txcmp;
2968 uint32_t cons, cp_cons;
2974 rc = is_bnxt_in_error(txq->bp);
2981 if (offset >= txq->nb_tx_desc)
2984 cons = RING_CMP(cpr->cp_ring_struct, offset);
2985 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2986 cp_cons = cpr->cp_raw_cons;
2988 if (cons > cp_cons) {
2989 if (CMPL_VALID(txcmp, cpr->valid))
2990 return RTE_ETH_TX_DESC_UNAVAIL;
2992 if (CMPL_VALID(txcmp, !cpr->valid))
2993 return RTE_ETH_TX_DESC_UNAVAIL;
2995 tx_buf = &txr->tx_buf_ring[cons];
2996 if (tx_buf->mbuf == NULL)
2997 return RTE_ETH_TX_DESC_DONE;
2999 return RTE_ETH_TX_DESC_FULL;
3003 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3004 enum rte_filter_type filter_type,
3005 enum rte_filter_op filter_op, void *arg)
3007 struct bnxt *bp = dev->data->dev_private;
3013 if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3014 struct bnxt_representor *vfr = dev->data->dev_private;
3015 bp = vfr->parent_dev->data->dev_private;
3016 /* parent is deleted while children are still valid */
3018 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n",
3026 ret = is_bnxt_in_error(bp);
3030 switch (filter_type) {
3031 case RTE_ETH_FILTER_GENERIC:
3032 if (filter_op != RTE_ETH_FILTER_GET)
3035 /* PMD supports thread-safe flow operations. rte_flow API
3036 * functions can avoid mutex for multi-thread safety.
3038 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3040 if (BNXT_TRUFLOW_EN(bp))
3041 *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3043 *(const void **)arg = &bnxt_flow_ops;
3047 "Filter type (%d) not supported", filter_type);
3054 static const uint32_t *
3055 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3057 static const uint32_t ptypes[] = {
3058 RTE_PTYPE_L2_ETHER_VLAN,
3059 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3060 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3064 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3065 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3066 RTE_PTYPE_INNER_L4_ICMP,
3067 RTE_PTYPE_INNER_L4_TCP,
3068 RTE_PTYPE_INNER_L4_UDP,
3072 if (!dev->rx_pkt_burst)
3078 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3081 uint32_t reg_base = *reg_arr & 0xfffff000;
3085 for (i = 0; i < count; i++) {
3086 if ((reg_arr[i] & 0xfffff000) != reg_base)
3089 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3090 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3094 static int bnxt_map_ptp_regs(struct bnxt *bp)
3096 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3100 reg_arr = ptp->rx_regs;
3101 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3105 reg_arr = ptp->tx_regs;
3106 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3110 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3111 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3113 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3114 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3119 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3121 rte_write32(0, (uint8_t *)bp->bar0 +
3122 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3123 rte_write32(0, (uint8_t *)bp->bar0 +
3124 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3127 static uint64_t bnxt_cc_read(struct bnxt *bp)
3131 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3132 BNXT_GRCPF_REG_SYNC_TIME));
3133 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3134 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3138 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3140 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3143 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3144 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3145 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3148 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3149 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3150 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3151 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3152 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3153 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3158 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3160 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3161 struct bnxt_pf_info *pf = bp->pf;
3168 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3169 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3170 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3173 port_id = pf->port_id;
3174 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3175 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3177 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3178 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3179 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3180 /* bnxt_clr_rx_ts(bp); TBD */
3184 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3185 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3186 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3187 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3193 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3196 struct bnxt *bp = dev->data->dev_private;
3197 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3202 ns = rte_timespec_to_ns(ts);
3203 /* Set the timecounters to a new value. */
3210 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3212 struct bnxt *bp = dev->data->dev_private;
3213 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3214 uint64_t ns, systime_cycles = 0;
3220 if (BNXT_CHIP_THOR(bp))
3221 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3224 systime_cycles = bnxt_cc_read(bp);
3226 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3227 *ts = rte_ns_to_timespec(ns);
3232 bnxt_timesync_enable(struct rte_eth_dev *dev)
3234 struct bnxt *bp = dev->data->dev_private;
3235 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3243 ptp->tx_tstamp_en = 1;
3244 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3246 rc = bnxt_hwrm_ptp_cfg(bp);
3250 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3251 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3252 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3254 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3255 ptp->tc.cc_shift = shift;
3256 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3258 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3259 ptp->rx_tstamp_tc.cc_shift = shift;
3260 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3262 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3263 ptp->tx_tstamp_tc.cc_shift = shift;
3264 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3266 if (!BNXT_CHIP_THOR(bp))
3267 bnxt_map_ptp_regs(bp);
3273 bnxt_timesync_disable(struct rte_eth_dev *dev)
3275 struct bnxt *bp = dev->data->dev_private;
3276 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3282 ptp->tx_tstamp_en = 0;
3285 bnxt_hwrm_ptp_cfg(bp);
3287 if (!BNXT_CHIP_THOR(bp))
3288 bnxt_unmap_ptp_regs(bp);
3294 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3295 struct timespec *timestamp,
3296 uint32_t flags __rte_unused)
3298 struct bnxt *bp = dev->data->dev_private;
3299 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3300 uint64_t rx_tstamp_cycles = 0;
3306 if (BNXT_CHIP_THOR(bp))
3307 rx_tstamp_cycles = ptp->rx_timestamp;
3309 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3311 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3312 *timestamp = rte_ns_to_timespec(ns);
3317 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3318 struct timespec *timestamp)
3320 struct bnxt *bp = dev->data->dev_private;
3321 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3322 uint64_t tx_tstamp_cycles = 0;
3329 if (BNXT_CHIP_THOR(bp))
3330 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3333 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3335 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3336 *timestamp = rte_ns_to_timespec(ns);
3342 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3344 struct bnxt *bp = dev->data->dev_private;
3345 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3350 ptp->tc.nsec += delta;
3356 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3358 struct bnxt *bp = dev->data->dev_private;
3360 uint32_t dir_entries;
3361 uint32_t entry_length;
3363 rc = is_bnxt_in_error(bp);
3367 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3368 bp->pdev->addr.domain, bp->pdev->addr.bus,
3369 bp->pdev->addr.devid, bp->pdev->addr.function);
3371 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3375 return dir_entries * entry_length;
3379 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3380 struct rte_dev_eeprom_info *in_eeprom)
3382 struct bnxt *bp = dev->data->dev_private;
3387 rc = is_bnxt_in_error(bp);
3391 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3392 bp->pdev->addr.domain, bp->pdev->addr.bus,
3393 bp->pdev->addr.devid, bp->pdev->addr.function,
3394 in_eeprom->offset, in_eeprom->length);
3396 if (in_eeprom->offset == 0) /* special offset value to get directory */
3397 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3400 index = in_eeprom->offset >> 24;
3401 offset = in_eeprom->offset & 0xffffff;
3404 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3405 in_eeprom->length, in_eeprom->data);
3410 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3413 case BNX_DIR_TYPE_CHIMP_PATCH:
3414 case BNX_DIR_TYPE_BOOTCODE:
3415 case BNX_DIR_TYPE_BOOTCODE_2:
3416 case BNX_DIR_TYPE_APE_FW:
3417 case BNX_DIR_TYPE_APE_PATCH:
3418 case BNX_DIR_TYPE_KONG_FW:
3419 case BNX_DIR_TYPE_KONG_PATCH:
3420 case BNX_DIR_TYPE_BONO_FW:
3421 case BNX_DIR_TYPE_BONO_PATCH:
3429 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3432 case BNX_DIR_TYPE_AVS:
3433 case BNX_DIR_TYPE_EXP_ROM_MBA:
3434 case BNX_DIR_TYPE_PCIE:
3435 case BNX_DIR_TYPE_TSCF_UCODE:
3436 case BNX_DIR_TYPE_EXT_PHY:
3437 case BNX_DIR_TYPE_CCM:
3438 case BNX_DIR_TYPE_ISCSI_BOOT:
3439 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3440 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3448 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3450 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3451 bnxt_dir_type_is_other_exec_format(dir_type);
3455 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3456 struct rte_dev_eeprom_info *in_eeprom)
3458 struct bnxt *bp = dev->data->dev_private;
3459 uint8_t index, dir_op;
3460 uint16_t type, ext, ordinal, attr;
3463 rc = is_bnxt_in_error(bp);
3467 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3468 bp->pdev->addr.domain, bp->pdev->addr.bus,
3469 bp->pdev->addr.devid, bp->pdev->addr.function,
3470 in_eeprom->offset, in_eeprom->length);
3473 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3477 type = in_eeprom->magic >> 16;
3479 if (type == 0xffff) { /* special value for directory operations */
3480 index = in_eeprom->magic & 0xff;
3481 dir_op = in_eeprom->magic >> 8;
3485 case 0x0e: /* erase */
3486 if (in_eeprom->offset != ~in_eeprom->magic)
3488 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3494 /* Create or re-write an NVM item: */
3495 if (bnxt_dir_type_is_executable(type) == true)
3497 ext = in_eeprom->magic & 0xffff;
3498 ordinal = in_eeprom->offset >> 16;
3499 attr = in_eeprom->offset & 0xffff;
3501 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3502 in_eeprom->data, in_eeprom->length);
3509 static const struct eth_dev_ops bnxt_dev_ops = {
3510 .dev_infos_get = bnxt_dev_info_get_op,
3511 .dev_close = bnxt_dev_close_op,
3512 .dev_configure = bnxt_dev_configure_op,
3513 .dev_start = bnxt_dev_start_op,
3514 .dev_stop = bnxt_dev_stop_op,
3515 .dev_set_link_up = bnxt_dev_set_link_up_op,
3516 .dev_set_link_down = bnxt_dev_set_link_down_op,
3517 .stats_get = bnxt_stats_get_op,
3518 .stats_reset = bnxt_stats_reset_op,
3519 .rx_queue_setup = bnxt_rx_queue_setup_op,
3520 .rx_queue_release = bnxt_rx_queue_release_op,
3521 .tx_queue_setup = bnxt_tx_queue_setup_op,
3522 .tx_queue_release = bnxt_tx_queue_release_op,
3523 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3524 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3525 .reta_update = bnxt_reta_update_op,
3526 .reta_query = bnxt_reta_query_op,
3527 .rss_hash_update = bnxt_rss_hash_update_op,
3528 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3529 .link_update = bnxt_link_update_op,
3530 .promiscuous_enable = bnxt_promiscuous_enable_op,
3531 .promiscuous_disable = bnxt_promiscuous_disable_op,
3532 .allmulticast_enable = bnxt_allmulticast_enable_op,
3533 .allmulticast_disable = bnxt_allmulticast_disable_op,
3534 .mac_addr_add = bnxt_mac_addr_add_op,
3535 .mac_addr_remove = bnxt_mac_addr_remove_op,
3536 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3537 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3538 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3539 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3540 .vlan_filter_set = bnxt_vlan_filter_set_op,
3541 .vlan_offload_set = bnxt_vlan_offload_set_op,
3542 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3543 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3544 .mtu_set = bnxt_mtu_set_op,
3545 .mac_addr_set = bnxt_set_default_mac_addr_op,
3546 .xstats_get = bnxt_dev_xstats_get_op,
3547 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3548 .xstats_reset = bnxt_dev_xstats_reset_op,
3549 .fw_version_get = bnxt_fw_version_get,
3550 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3551 .rxq_info_get = bnxt_rxq_info_get_op,
3552 .txq_info_get = bnxt_txq_info_get_op,
3553 .rx_burst_mode_get = bnxt_rx_burst_mode_get,
3554 .tx_burst_mode_get = bnxt_tx_burst_mode_get,
3555 .dev_led_on = bnxt_dev_led_on_op,
3556 .dev_led_off = bnxt_dev_led_off_op,
3557 .rx_queue_start = bnxt_rx_queue_start,
3558 .rx_queue_stop = bnxt_rx_queue_stop,
3559 .tx_queue_start = bnxt_tx_queue_start,
3560 .tx_queue_stop = bnxt_tx_queue_stop,
3561 .filter_ctrl = bnxt_filter_ctrl_op,
3562 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3563 .get_eeprom_length = bnxt_get_eeprom_length_op,
3564 .get_eeprom = bnxt_get_eeprom_op,
3565 .set_eeprom = bnxt_set_eeprom_op,
3566 .timesync_enable = bnxt_timesync_enable,
3567 .timesync_disable = bnxt_timesync_disable,
3568 .timesync_read_time = bnxt_timesync_read_time,
3569 .timesync_write_time = bnxt_timesync_write_time,
3570 .timesync_adjust_time = bnxt_timesync_adjust_time,
3571 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3572 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3575 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3579 /* Only pre-map the reset GRC registers using window 3 */
3580 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3581 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3583 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3588 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3590 struct bnxt_error_recovery_info *info = bp->recovery_info;
3591 uint32_t reg_base = 0xffffffff;
3594 /* Only pre-map the monitoring GRC registers using window 2 */
3595 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3596 uint32_t reg = info->status_regs[i];
3598 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3601 if (reg_base == 0xffffffff)
3602 reg_base = reg & 0xfffff000;
3603 if ((reg & 0xfffff000) != reg_base)
3606 /* Use mask 0xffc as the Lower 2 bits indicates
3607 * address space location
3609 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3613 if (reg_base == 0xffffffff)
3616 rte_write32(reg_base, (uint8_t *)bp->bar0 +
3617 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3622 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3624 struct bnxt_error_recovery_info *info = bp->recovery_info;
3625 uint32_t delay = info->delay_after_reset[index];
3626 uint32_t val = info->reset_reg_val[index];
3627 uint32_t reg = info->reset_reg[index];
3628 uint32_t type, offset;
3630 type = BNXT_FW_STATUS_REG_TYPE(reg);
3631 offset = BNXT_FW_STATUS_REG_OFF(reg);
3634 case BNXT_FW_STATUS_REG_TYPE_CFG:
3635 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3637 case BNXT_FW_STATUS_REG_TYPE_GRC:
3638 offset = bnxt_map_reset_regs(bp, offset);
3639 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3641 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3642 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3645 /* wait on a specific interval of time until core reset is complete */
3647 rte_delay_ms(delay);
3650 static void bnxt_dev_cleanup(struct bnxt *bp)
3652 bp->eth_dev->data->dev_link.link_status = 0;
3653 bp->link_info->link_up = 0;
3654 if (bp->eth_dev->data->dev_started)
3655 bnxt_dev_stop_op(bp->eth_dev);
3657 bnxt_uninit_resources(bp, true);
3660 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3662 struct rte_eth_dev *dev = bp->eth_dev;
3663 struct rte_vlan_filter_conf *vfc;
3667 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3668 vfc = &dev->data->vlan_filter_conf;
3669 vidx = vlan_id / 64;
3670 vbit = vlan_id % 64;
3672 /* Each bit corresponds to a VLAN id */
3673 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3674 rc = bnxt_add_vlan_filter(bp, vlan_id);
3683 static int bnxt_restore_mac_filters(struct bnxt *bp)
3685 struct rte_eth_dev *dev = bp->eth_dev;
3686 struct rte_eth_dev_info dev_info;
3687 struct rte_ether_addr *addr;
3693 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3696 rc = bnxt_dev_info_get_op(dev, &dev_info);
3700 /* replay MAC address configuration */
3701 for (i = 1; i < dev_info.max_mac_addrs; i++) {
3702 addr = &dev->data->mac_addrs[i];
3704 /* skip zero address */
3705 if (rte_is_zero_ether_addr(addr))
3709 pool_mask = dev->data->mac_pool_sel[i];
3712 if (pool_mask & 1ULL) {
3713 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3719 } while (pool_mask);
3725 static int bnxt_restore_filters(struct bnxt *bp)
3727 struct rte_eth_dev *dev = bp->eth_dev;
3730 if (dev->data->all_multicast) {
3731 ret = bnxt_allmulticast_enable_op(dev);
3735 if (dev->data->promiscuous) {
3736 ret = bnxt_promiscuous_enable_op(dev);
3741 ret = bnxt_restore_mac_filters(bp);
3745 ret = bnxt_restore_vlan_filters(bp);
3746 /* TODO restore other filters as well */
3750 static void bnxt_dev_recover(void *arg)
3752 struct bnxt *bp = arg;
3753 int timeout = bp->fw_reset_max_msecs;
3756 /* Clear Error flag so that device re-init should happen */
3757 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3760 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
3763 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3764 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3765 } while (rc && timeout);
3768 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3772 rc = bnxt_init_resources(bp, true);
3775 "Failed to initialize resources after reset\n");
3778 /* clear reset flag as the device is initialized now */
3779 bp->flags &= ~BNXT_FLAG_FW_RESET;
3781 rc = bnxt_dev_start_op(bp->eth_dev);
3783 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3787 rc = bnxt_restore_filters(bp);
3791 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3794 bnxt_dev_stop_op(bp->eth_dev);
3796 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3797 bnxt_uninit_resources(bp, false);
3798 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3801 void bnxt_dev_reset_and_resume(void *arg)
3803 struct bnxt *bp = arg;
3806 bnxt_dev_cleanup(bp);
3808 bnxt_wait_for_device_shutdown(bp);
3810 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3811 bnxt_dev_recover, (void *)bp);
3813 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3816 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3818 struct bnxt_error_recovery_info *info = bp->recovery_info;
3819 uint32_t reg = info->status_regs[index];
3820 uint32_t type, offset, val = 0;
3822 type = BNXT_FW_STATUS_REG_TYPE(reg);
3823 offset = BNXT_FW_STATUS_REG_OFF(reg);
3826 case BNXT_FW_STATUS_REG_TYPE_CFG:
3827 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3829 case BNXT_FW_STATUS_REG_TYPE_GRC:
3830 offset = info->mapped_status_regs[index];
3832 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3833 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3841 static int bnxt_fw_reset_all(struct bnxt *bp)
3843 struct bnxt_error_recovery_info *info = bp->recovery_info;
3847 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3848 /* Reset through master function driver */
3849 for (i = 0; i < info->reg_array_cnt; i++)
3850 bnxt_write_fw_reset_reg(bp, i);
3851 /* Wait for time specified by FW after triggering reset */
3852 rte_delay_ms(info->master_func_wait_period_after_reset);
3853 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3854 /* Reset with the help of Kong processor */
3855 rc = bnxt_hwrm_fw_reset(bp);
3857 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3863 static void bnxt_fw_reset_cb(void *arg)
3865 struct bnxt *bp = arg;
3866 struct bnxt_error_recovery_info *info = bp->recovery_info;
3869 /* Only Master function can do FW reset */
3870 if (bnxt_is_master_func(bp) &&
3871 bnxt_is_recovery_enabled(bp)) {
3872 rc = bnxt_fw_reset_all(bp);
3874 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3879 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3880 * EXCEPTION_FATAL_ASYNC event to all the functions
3881 * (including MASTER FUNC). After receiving this Async, all the active
3882 * drivers should treat this case as FW initiated recovery
3884 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3885 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3886 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3888 /* To recover from error */
3889 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3894 /* Driver should poll FW heartbeat, reset_counter with the frequency
3895 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3896 * When the driver detects heartbeat stop or change in reset_counter,
3897 * it has to trigger a reset to recover from the error condition.
3898 * A “master PF” is the function who will have the privilege to
3899 * initiate the chimp reset. The master PF will be elected by the
3900 * firmware and will be notified through async message.
3902 static void bnxt_check_fw_health(void *arg)
3904 struct bnxt *bp = arg;
3905 struct bnxt_error_recovery_info *info = bp->recovery_info;
3906 uint32_t val = 0, wait_msec;
3908 if (!info || !bnxt_is_recovery_enabled(bp) ||
3909 is_bnxt_in_error(bp))
3912 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3913 if (val == info->last_heart_beat)
3916 info->last_heart_beat = val;
3918 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3919 if (val != info->last_reset_counter)
3922 info->last_reset_counter = val;
3924 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3925 bnxt_check_fw_health, (void *)bp);
3929 /* Stop DMA to/from device */
3930 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3931 bp->flags |= BNXT_FLAG_FW_RESET;
3933 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
3935 if (bnxt_is_master_func(bp))
3936 wait_msec = info->master_func_wait_period;
3938 wait_msec = info->normal_func_wait_period;
3940 rte_eal_alarm_set(US_PER_MS * wait_msec,
3941 bnxt_fw_reset_cb, (void *)bp);
3944 void bnxt_schedule_fw_health_check(struct bnxt *bp)
3946 uint32_t polling_freq;
3948 pthread_mutex_lock(&bp->health_check_lock);
3950 if (!bnxt_is_recovery_enabled(bp))
3953 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
3956 polling_freq = bp->recovery_info->driver_polling_freq;
3958 rte_eal_alarm_set(US_PER_MS * polling_freq,
3959 bnxt_check_fw_health, (void *)bp);
3960 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3963 pthread_mutex_unlock(&bp->health_check_lock);
3966 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
3968 if (!bnxt_is_recovery_enabled(bp))
3971 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
3972 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3975 static bool bnxt_vf_pciid(uint16_t device_id)
3977 switch (device_id) {
3978 case BROADCOM_DEV_ID_57304_VF:
3979 case BROADCOM_DEV_ID_57406_VF:
3980 case BROADCOM_DEV_ID_5731X_VF:
3981 case BROADCOM_DEV_ID_5741X_VF:
3982 case BROADCOM_DEV_ID_57414_VF:
3983 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
3984 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
3985 case BROADCOM_DEV_ID_58802_VF:
3986 case BROADCOM_DEV_ID_57500_VF1:
3987 case BROADCOM_DEV_ID_57500_VF2:
3995 static bool bnxt_thor_device(uint16_t device_id)
3997 switch (device_id) {
3998 case BROADCOM_DEV_ID_57508:
3999 case BROADCOM_DEV_ID_57504:
4000 case BROADCOM_DEV_ID_57502:
4001 case BROADCOM_DEV_ID_57508_MF1:
4002 case BROADCOM_DEV_ID_57504_MF1:
4003 case BROADCOM_DEV_ID_57502_MF1:
4004 case BROADCOM_DEV_ID_57508_MF2:
4005 case BROADCOM_DEV_ID_57504_MF2:
4006 case BROADCOM_DEV_ID_57502_MF2:
4007 case BROADCOM_DEV_ID_57500_VF1:
4008 case BROADCOM_DEV_ID_57500_VF2:
4016 bool bnxt_stratus_device(struct bnxt *bp)
4018 uint16_t device_id = bp->pdev->id.device_id;
4020 switch (device_id) {
4021 case BROADCOM_DEV_ID_STRATUS_NIC:
4022 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4023 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4031 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4033 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4034 struct bnxt *bp = eth_dev->data->dev_private;
4036 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4037 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4038 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4039 if (!bp->bar0 || !bp->doorbell_base) {
4040 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4044 bp->eth_dev = eth_dev;
4050 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4051 struct bnxt_ctx_pg_info *ctx_pg,
4056 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4057 const struct rte_memzone *mz = NULL;
4058 char mz_name[RTE_MEMZONE_NAMESIZE];
4059 rte_iova_t mz_phys_addr;
4060 uint64_t valid_bits = 0;
4067 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4069 rmem->page_size = BNXT_PAGE_SIZE;
4070 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4071 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4072 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4074 valid_bits = PTU_PTE_VALID;
4076 if (rmem->nr_pages > 1) {
4077 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4078 "bnxt_ctx_pg_tbl%s_%x_%d",
4079 suffix, idx, bp->eth_dev->data->port_id);
4080 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4081 mz = rte_memzone_lookup(mz_name);
4083 mz = rte_memzone_reserve_aligned(mz_name,
4087 RTE_MEMZONE_SIZE_HINT_ONLY |
4088 RTE_MEMZONE_IOVA_CONTIG,
4094 memset(mz->addr, 0, mz->len);
4095 mz_phys_addr = mz->iova;
4097 rmem->pg_tbl = mz->addr;
4098 rmem->pg_tbl_map = mz_phys_addr;
4099 rmem->pg_tbl_mz = mz;
4102 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4103 suffix, idx, bp->eth_dev->data->port_id);
4104 mz = rte_memzone_lookup(mz_name);
4106 mz = rte_memzone_reserve_aligned(mz_name,
4110 RTE_MEMZONE_SIZE_HINT_ONLY |
4111 RTE_MEMZONE_IOVA_CONTIG,
4117 memset(mz->addr, 0, mz->len);
4118 mz_phys_addr = mz->iova;
4120 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4121 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4122 rmem->dma_arr[i] = mz_phys_addr + sz;
4124 if (rmem->nr_pages > 1) {
4125 if (i == rmem->nr_pages - 2 &&
4126 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4127 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4128 else if (i == rmem->nr_pages - 1 &&
4129 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4130 valid_bits |= PTU_PTE_LAST;
4132 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4138 if (rmem->vmem_size)
4139 rmem->vmem = (void **)mz->addr;
4140 rmem->dma_arr[0] = mz_phys_addr;
4144 static void bnxt_free_ctx_mem(struct bnxt *bp)
4148 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4151 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4152 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4153 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4154 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4155 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4156 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4157 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4158 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4159 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4160 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4161 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4163 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4164 if (bp->ctx->tqm_mem[i])
4165 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4172 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4174 #define min_t(type, x, y) ({ \
4175 type __min1 = (x); \
4176 type __min2 = (y); \
4177 __min1 < __min2 ? __min1 : __min2; })
4179 #define max_t(type, x, y) ({ \
4180 type __max1 = (x); \
4181 type __max2 = (y); \
4182 __max1 > __max2 ? __max1 : __max2; })
4184 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4186 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4188 struct bnxt_ctx_pg_info *ctx_pg;
4189 struct bnxt_ctx_mem_info *ctx;
4190 uint32_t mem_size, ena, entries;
4191 uint32_t entries_sp, min;
4194 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4196 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4200 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4203 ctx_pg = &ctx->qp_mem;
4204 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4205 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4206 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4210 ctx_pg = &ctx->srq_mem;
4211 ctx_pg->entries = ctx->srq_max_l2_entries;
4212 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4213 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4217 ctx_pg = &ctx->cq_mem;
4218 ctx_pg->entries = ctx->cq_max_l2_entries;
4219 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4220 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4224 ctx_pg = &ctx->vnic_mem;
4225 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4226 ctx->vnic_max_ring_table_entries;
4227 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4228 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4232 ctx_pg = &ctx->stat_mem;
4233 ctx_pg->entries = ctx->stat_max_entries;
4234 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4235 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4239 min = ctx->tqm_min_entries_per_ring;
4241 entries_sp = ctx->qp_max_l2_entries +
4242 ctx->vnic_max_vnic_entries +
4243 2 * ctx->qp_min_qp1_entries + min;
4244 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4246 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4247 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4248 entries = clamp_t(uint32_t, entries, min,
4249 ctx->tqm_max_entries_per_ring);
4250 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4251 ctx_pg = ctx->tqm_mem[i];
4252 ctx_pg->entries = i ? entries : entries_sp;
4253 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4254 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4257 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4260 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4261 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4264 "Failed to configure context mem: rc = %d\n", rc);
4266 ctx->flags |= BNXT_CTX_FLAG_INITED;
4271 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4273 struct rte_pci_device *pci_dev = bp->pdev;
4274 char mz_name[RTE_MEMZONE_NAMESIZE];
4275 const struct rte_memzone *mz = NULL;
4276 uint32_t total_alloc_len;
4277 rte_iova_t mz_phys_addr;
4279 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4282 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4283 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4284 pci_dev->addr.bus, pci_dev->addr.devid,
4285 pci_dev->addr.function, "rx_port_stats");
4286 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4287 mz = rte_memzone_lookup(mz_name);
4289 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4290 sizeof(struct rx_port_stats_ext) + 512);
4292 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4295 RTE_MEMZONE_SIZE_HINT_ONLY |
4296 RTE_MEMZONE_IOVA_CONTIG);
4300 memset(mz->addr, 0, mz->len);
4301 mz_phys_addr = mz->iova;
4303 bp->rx_mem_zone = (const void *)mz;
4304 bp->hw_rx_port_stats = mz->addr;
4305 bp->hw_rx_port_stats_map = mz_phys_addr;
4307 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4308 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4309 pci_dev->addr.bus, pci_dev->addr.devid,
4310 pci_dev->addr.function, "tx_port_stats");
4311 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4312 mz = rte_memzone_lookup(mz_name);
4314 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4315 sizeof(struct tx_port_stats_ext) + 512);
4317 mz = rte_memzone_reserve(mz_name,
4321 RTE_MEMZONE_SIZE_HINT_ONLY |
4322 RTE_MEMZONE_IOVA_CONTIG);
4326 memset(mz->addr, 0, mz->len);
4327 mz_phys_addr = mz->iova;
4329 bp->tx_mem_zone = (const void *)mz;
4330 bp->hw_tx_port_stats = mz->addr;
4331 bp->hw_tx_port_stats_map = mz_phys_addr;
4332 bp->flags |= BNXT_FLAG_PORT_STATS;
4334 /* Display extended statistics if FW supports it */
4335 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4336 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4337 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4340 bp->hw_rx_port_stats_ext = (void *)
4341 ((uint8_t *)bp->hw_rx_port_stats +
4342 sizeof(struct rx_port_stats));
4343 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4344 sizeof(struct rx_port_stats);
4345 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4347 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4348 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4349 bp->hw_tx_port_stats_ext = (void *)
4350 ((uint8_t *)bp->hw_tx_port_stats +
4351 sizeof(struct tx_port_stats));
4352 bp->hw_tx_port_stats_ext_map =
4353 bp->hw_tx_port_stats_map +
4354 sizeof(struct tx_port_stats);
4355 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4361 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4363 struct bnxt *bp = eth_dev->data->dev_private;
4366 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4367 RTE_ETHER_ADDR_LEN *
4370 if (eth_dev->data->mac_addrs == NULL) {
4371 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4375 if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4379 /* Generate a random MAC address, if none was assigned by PF */
4380 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4381 bnxt_eth_hw_addr_random(bp->mac_addr);
4383 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4384 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4385 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4387 rc = bnxt_hwrm_set_mac(bp);
4392 /* Copy the permanent MAC from the FUNC_QCAPS response */
4393 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4398 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4402 /* MAC is already configured in FW */
4403 if (BNXT_HAS_DFLT_MAC_SET(bp))
4406 /* Restore the old MAC configured */
4407 rc = bnxt_hwrm_set_mac(bp);
4409 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4414 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4419 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
4421 if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
4422 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
4423 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
4424 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
4425 BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
4426 BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
4430 bnxt_get_svif(uint16_t port_id, bool func_svif,
4431 enum bnxt_ulp_intf_type type)
4433 struct rte_eth_dev *eth_dev;
4436 eth_dev = &rte_eth_devices[port_id];
4437 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4438 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4442 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4445 eth_dev = vfr->parent_dev;
4448 bp = eth_dev->data->dev_private;
4450 return func_svif ? bp->func_svif : bp->port_svif;
4454 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
4456 struct rte_eth_dev *eth_dev;
4457 struct bnxt_vnic_info *vnic;
4460 eth_dev = &rte_eth_devices[port];
4461 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4462 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4466 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4467 return vfr->dflt_vnic_id;
4469 eth_dev = vfr->parent_dev;
4472 bp = eth_dev->data->dev_private;
4474 vnic = BNXT_GET_DEFAULT_VNIC(bp);
4476 return vnic->fw_vnic_id;
4480 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
4482 struct rte_eth_dev *eth_dev;
4485 eth_dev = &rte_eth_devices[port];
4486 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4487 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4491 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4494 eth_dev = vfr->parent_dev;
4497 bp = eth_dev->data->dev_private;
4502 enum bnxt_ulp_intf_type
4503 bnxt_get_interface_type(uint16_t port)
4505 struct rte_eth_dev *eth_dev;
4508 eth_dev = &rte_eth_devices[port];
4509 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
4510 return BNXT_ULP_INTF_TYPE_VF_REP;
4512 bp = eth_dev->data->dev_private;
4514 return BNXT_ULP_INTF_TYPE_PF;
4515 else if (BNXT_VF_IS_TRUSTED(bp))
4516 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
4517 else if (BNXT_VF(bp))
4518 return BNXT_ULP_INTF_TYPE_VF;
4520 return BNXT_ULP_INTF_TYPE_INVALID;
4524 bnxt_get_phy_port_id(uint16_t port_id)
4526 struct bnxt_representor *vfr;
4527 struct rte_eth_dev *eth_dev;
4530 eth_dev = &rte_eth_devices[port_id];
4531 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4532 vfr = eth_dev->data->dev_private;
4536 eth_dev = vfr->parent_dev;
4539 bp = eth_dev->data->dev_private;
4541 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
4545 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
4547 struct rte_eth_dev *eth_dev;
4550 eth_dev = &rte_eth_devices[port_id];
4551 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4552 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4556 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4557 return vfr->fw_fid - 1;
4559 eth_dev = vfr->parent_dev;
4562 bp = eth_dev->data->dev_private;
4564 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
4568 bnxt_get_vport(uint16_t port_id)
4570 return (1 << bnxt_get_phy_port_id(port_id));
4573 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
4575 struct bnxt_error_recovery_info *info = bp->recovery_info;
4578 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
4579 memset(info, 0, sizeof(*info));
4583 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4586 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4589 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4591 bp->recovery_info = info;
4594 static void bnxt_check_fw_status(struct bnxt *bp)
4598 if (!(bp->recovery_info &&
4599 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
4602 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
4603 if (fw_status != BNXT_FW_STATUS_HEALTHY)
4604 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
4608 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
4610 struct bnxt_error_recovery_info *info = bp->recovery_info;
4611 uint32_t status_loc;
4614 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
4615 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4616 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4617 BNXT_GRCP_WINDOW_2_BASE +
4618 offsetof(struct hcomm_status,
4620 /* If the signature is absent, then FW does not support this feature */
4621 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
4622 HCOMM_STATUS_SIGNATURE_VAL)
4626 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4630 bp->recovery_info = info;
4632 memset(info, 0, sizeof(*info));
4635 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4636 BNXT_GRCP_WINDOW_2_BASE +
4637 offsetof(struct hcomm_status,
4640 /* Only pre-map the FW health status GRC register */
4641 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
4644 info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
4645 info->mapped_status_regs[BNXT_FW_STATUS_REG] =
4646 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
4648 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
4649 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4651 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
4656 static int bnxt_init_fw(struct bnxt *bp)
4663 rc = bnxt_map_hcomm_fw_status_reg(bp);
4667 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
4669 bnxt_check_fw_status(bp);
4673 rc = bnxt_hwrm_func_reset(bp);
4677 rc = bnxt_hwrm_vnic_qcaps(bp);
4681 rc = bnxt_hwrm_queue_qportcfg(bp);
4685 /* Get the MAX capabilities for this function.
4686 * This function also allocates context memory for TQM rings and
4687 * informs the firmware about this allocated backing store memory.
4689 rc = bnxt_hwrm_func_qcaps(bp);
4693 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4697 bnxt_hwrm_port_mac_qcfg(bp);
4699 bnxt_hwrm_parent_pf_qcfg(bp);
4701 bnxt_hwrm_port_phy_qcaps(bp);
4703 bnxt_alloc_error_recovery_info(bp);
4704 /* Get the adapter error recovery support info */
4705 rc = bnxt_hwrm_error_recovery_qcfg(bp);
4707 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4709 bnxt_hwrm_port_led_qcaps(bp);
4715 bnxt_init_locks(struct bnxt *bp)
4719 err = pthread_mutex_init(&bp->flow_lock, NULL);
4721 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4725 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4727 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4729 err = pthread_mutex_init(&bp->health_check_lock, NULL);
4731 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
4735 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4739 rc = bnxt_init_fw(bp);
4743 if (!reconfig_dev) {
4744 rc = bnxt_setup_mac_addr(bp->eth_dev);
4748 rc = bnxt_restore_dflt_mac(bp);
4753 bnxt_config_vf_req_fwd(bp);
4755 rc = bnxt_hwrm_func_driver_register(bp);
4757 PMD_DRV_LOG(ERR, "Failed to register driver");
4762 if (bp->pdev->max_vfs) {
4763 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4765 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4769 rc = bnxt_hwrm_allocate_pf_only(bp);
4772 "Failed to allocate PF resources");
4778 rc = bnxt_alloc_mem(bp, reconfig_dev);
4782 rc = bnxt_setup_int(bp);
4786 rc = bnxt_request_int(bp);
4790 rc = bnxt_init_ctx_mem(bp);
4792 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
4796 rc = bnxt_init_locks(bp);
4804 bnxt_parse_devarg_truflow(__rte_unused const char *key,
4805 const char *value, void *opaque_arg)
4807 struct bnxt *bp = opaque_arg;
4808 unsigned long truflow;
4811 if (!value || !opaque_arg) {
4813 "Invalid parameter passed to truflow devargs.\n");
4817 truflow = strtoul(value, &end, 10);
4818 if (end == NULL || *end != '\0' ||
4819 (truflow == ULONG_MAX && errno == ERANGE)) {
4821 "Invalid parameter passed to truflow devargs.\n");
4825 if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
4827 "Invalid value passed to truflow devargs.\n");
4832 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
4833 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
4835 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
4836 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
4843 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
4844 const char *value, void *opaque_arg)
4846 struct bnxt *bp = opaque_arg;
4847 unsigned long flow_xstat;
4850 if (!value || !opaque_arg) {
4852 "Invalid parameter passed to flow_xstat devarg.\n");
4856 flow_xstat = strtoul(value, &end, 10);
4857 if (end == NULL || *end != '\0' ||
4858 (flow_xstat == ULONG_MAX && errno == ERANGE)) {
4860 "Invalid parameter passed to flow_xstat devarg.\n");
4864 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
4866 "Invalid value passed to flow_xstat devarg.\n");
4870 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
4871 if (BNXT_FLOW_XSTATS_EN(bp))
4872 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
4878 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
4879 const char *value, void *opaque_arg)
4881 struct bnxt *bp = opaque_arg;
4882 unsigned long max_num_kflows;
4885 if (!value || !opaque_arg) {
4887 "Invalid parameter passed to max_num_kflows devarg.\n");
4891 max_num_kflows = strtoul(value, &end, 10);
4892 if (end == NULL || *end != '\0' ||
4893 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
4895 "Invalid parameter passed to max_num_kflows devarg.\n");
4899 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
4901 "Invalid value passed to max_num_kflows devarg.\n");
4905 bp->max_num_kflows = max_num_kflows;
4906 if (bp->max_num_kflows)
4907 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
4914 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
4915 const char *value, void *opaque_arg)
4917 struct bnxt_representor *vfr_bp = opaque_arg;
4918 unsigned long rep_is_pf;
4921 if (!value || !opaque_arg) {
4923 "Invalid parameter passed to rep_is_pf devargs.\n");
4927 rep_is_pf = strtoul(value, &end, 10);
4928 if (end == NULL || *end != '\0' ||
4929 (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
4931 "Invalid parameter passed to rep_is_pf devargs.\n");
4935 if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
4937 "Invalid value passed to rep_is_pf devargs.\n");
4941 vfr_bp->flags |= rep_is_pf;
4942 if (BNXT_REP_PF(vfr_bp))
4943 PMD_DRV_LOG(INFO, "PF representor\n");
4945 PMD_DRV_LOG(INFO, "VF representor\n");
4951 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
4952 const char *value, void *opaque_arg)
4954 struct bnxt_representor *vfr_bp = opaque_arg;
4955 unsigned long rep_based_pf;
4958 if (!value || !opaque_arg) {
4960 "Invalid parameter passed to rep_based_pf "
4965 rep_based_pf = strtoul(value, &end, 10);
4966 if (end == NULL || *end != '\0' ||
4967 (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
4969 "Invalid parameter passed to rep_based_pf "
4974 if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
4976 "Invalid value passed to rep_based_pf devargs.\n");
4980 vfr_bp->rep_based_pf = rep_based_pf;
4981 vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
4983 PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
4989 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
4990 const char *value, void *opaque_arg)
4992 struct bnxt_representor *vfr_bp = opaque_arg;
4993 unsigned long rep_q_r2f;
4996 if (!value || !opaque_arg) {
4998 "Invalid parameter passed to rep_q_r2f "
5003 rep_q_r2f = strtoul(value, &end, 10);
5004 if (end == NULL || *end != '\0' ||
5005 (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5007 "Invalid parameter passed to rep_q_r2f "
5012 if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5014 "Invalid value passed to rep_q_r2f devargs.\n");
5018 vfr_bp->rep_q_r2f = rep_q_r2f;
5019 vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5020 PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5026 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5027 const char *value, void *opaque_arg)
5029 struct bnxt_representor *vfr_bp = opaque_arg;
5030 unsigned long rep_q_f2r;
5033 if (!value || !opaque_arg) {
5035 "Invalid parameter passed to rep_q_f2r "
5040 rep_q_f2r = strtoul(value, &end, 10);
5041 if (end == NULL || *end != '\0' ||
5042 (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5044 "Invalid parameter passed to rep_q_f2r "
5049 if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5051 "Invalid value passed to rep_q_f2r devargs.\n");
5055 vfr_bp->rep_q_f2r = rep_q_f2r;
5056 vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5057 PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5063 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5064 const char *value, void *opaque_arg)
5066 struct bnxt_representor *vfr_bp = opaque_arg;
5067 unsigned long rep_fc_r2f;
5070 if (!value || !opaque_arg) {
5072 "Invalid parameter passed to rep_fc_r2f "
5077 rep_fc_r2f = strtoul(value, &end, 10);
5078 if (end == NULL || *end != '\0' ||
5079 (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5081 "Invalid parameter passed to rep_fc_r2f "
5086 if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5088 "Invalid value passed to rep_fc_r2f devargs.\n");
5092 vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5093 vfr_bp->rep_fc_r2f = rep_fc_r2f;
5094 PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5100 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5101 const char *value, void *opaque_arg)
5103 struct bnxt_representor *vfr_bp = opaque_arg;
5104 unsigned long rep_fc_f2r;
5107 if (!value || !opaque_arg) {
5109 "Invalid parameter passed to rep_fc_f2r "
5114 rep_fc_f2r = strtoul(value, &end, 10);
5115 if (end == NULL || *end != '\0' ||
5116 (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5118 "Invalid parameter passed to rep_fc_f2r "
5123 if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5125 "Invalid value passed to rep_fc_f2r devargs.\n");
5129 vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5130 vfr_bp->rep_fc_f2r = rep_fc_f2r;
5131 PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5137 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5139 struct rte_kvargs *kvlist;
5141 if (devargs == NULL)
5144 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5149 * Handler for "truflow" devarg.
5150 * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1"
5152 rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5153 bnxt_parse_devarg_truflow, bp);
5156 * Handler for "flow_xstat" devarg.
5157 * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1"
5159 rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5160 bnxt_parse_devarg_flow_xstat, bp);
5163 * Handler for "max_num_kflows" devarg.
5164 * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32"
5166 rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5167 bnxt_parse_devarg_max_num_kflows, bp);
5169 rte_kvargs_free(kvlist);
5172 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5176 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5177 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5180 "Failed to alloc switch domain: %d\n", rc);
5183 "Switch domain allocated %d\n",
5184 bp->switch_domain_id);
5191 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5193 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5194 static int version_printed;
5198 if (version_printed++ == 0)
5199 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5201 eth_dev->dev_ops = &bnxt_dev_ops;
5202 eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5203 eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5204 eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5205 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5206 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5209 * For secondary processes, we don't initialise any further
5210 * as primary has already done this work.
5212 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5215 rte_eth_copy_pci_info(eth_dev, pci_dev);
5216 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
5218 bp = eth_dev->data->dev_private;
5220 /* Parse dev arguments passed on when starting the DPDK application. */
5221 bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5223 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5225 if (bnxt_vf_pciid(pci_dev->id.device_id))
5226 bp->flags |= BNXT_FLAG_VF;
5228 if (bnxt_thor_device(pci_dev->id.device_id))
5229 bp->flags |= BNXT_FLAG_THOR_CHIP;
5231 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5232 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5233 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5234 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5235 bp->flags |= BNXT_FLAG_STINGRAY;
5237 if (BNXT_TRUFLOW_EN(bp)) {
5238 /* extra mbuf field is required to store CFA code from mark */
5239 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5240 .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5241 .size = sizeof(bnxt_cfa_code_dynfield_t),
5242 .align = __alignof__(bnxt_cfa_code_dynfield_t),
5244 bnxt_cfa_code_dynfield_offset =
5245 rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5246 if (bnxt_cfa_code_dynfield_offset < 0) {
5248 "Failed to register mbuf field for TruFlow mark\n");
5253 rc = bnxt_init_board(eth_dev);
5256 "Failed to initialize board rc: %x\n", rc);
5260 rc = bnxt_alloc_pf_info(bp);
5264 rc = bnxt_alloc_link_info(bp);
5268 rc = bnxt_alloc_parent_info(bp);
5272 rc = bnxt_alloc_hwrm_resources(bp);
5275 "Failed to allocate hwrm resource rc: %x\n", rc);
5278 rc = bnxt_alloc_leds_info(bp);
5282 rc = bnxt_alloc_cos_queues(bp);
5286 rc = bnxt_init_resources(bp, false);
5290 rc = bnxt_alloc_stats_mem(bp);
5294 bnxt_alloc_switch_domain(bp);
5297 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5298 pci_dev->mem_resource[0].phys_addr,
5299 pci_dev->mem_resource[0].addr);
5304 bnxt_dev_uninit(eth_dev);
5309 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5318 ctx->dma = RTE_BAD_IOVA;
5319 ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5322 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5324 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5325 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5326 bp->flow_stat->rx_fc_out_tbl.ctx_id,
5327 bp->flow_stat->max_fc,
5330 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5331 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5332 bp->flow_stat->tx_fc_out_tbl.ctx_id,
5333 bp->flow_stat->max_fc,
5336 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5337 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5338 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5340 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5341 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5342 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5344 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5345 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5346 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5348 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5349 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5350 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5353 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5355 bnxt_unregister_fc_ctx_mem(bp);
5357 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5358 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5359 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5360 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5363 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5365 if (BNXT_FLOW_XSTATS_EN(bp))
5366 bnxt_uninit_fc_ctx_mem(bp);
5370 bnxt_free_error_recovery_info(struct bnxt *bp)
5372 rte_free(bp->recovery_info);
5373 bp->recovery_info = NULL;
5374 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5378 bnxt_uninit_locks(struct bnxt *bp)
5380 pthread_mutex_destroy(&bp->flow_lock);
5381 pthread_mutex_destroy(&bp->def_cp_lock);
5382 pthread_mutex_destroy(&bp->health_check_lock);
5384 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
5385 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
5390 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5395 bnxt_free_mem(bp, reconfig_dev);
5397 bnxt_hwrm_func_buf_unrgtr(bp);
5398 rte_free(bp->pf->vf_req_buf);
5400 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5401 bp->flags &= ~BNXT_FLAG_REGISTERED;
5402 bnxt_free_ctx_mem(bp);
5403 if (!reconfig_dev) {
5404 bnxt_free_hwrm_resources(bp);
5405 bnxt_free_error_recovery_info(bp);
5408 bnxt_uninit_ctx_mem(bp);
5410 bnxt_uninit_locks(bp);
5411 bnxt_free_flow_stats_info(bp);
5412 bnxt_free_rep_info(bp);
5413 rte_free(bp->ptp_cfg);
5419 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5421 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5424 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5426 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5427 bnxt_dev_close_op(eth_dev);
5432 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5434 struct bnxt *bp = eth_dev->data->dev_private;
5435 struct rte_eth_dev *vf_rep_eth_dev;
5441 for (i = 0; i < bp->num_reps; i++) {
5442 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5443 if (!vf_rep_eth_dev)
5445 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
5446 vf_rep_eth_dev->data->port_id);
5447 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
5449 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
5450 eth_dev->data->port_id);
5451 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5456 static void bnxt_free_rep_info(struct bnxt *bp)
5458 rte_free(bp->rep_info);
5459 bp->rep_info = NULL;
5460 rte_free(bp->cfa_code_map);
5461 bp->cfa_code_map = NULL;
5464 static int bnxt_init_rep_info(struct bnxt *bp)
5471 bp->rep_info = rte_zmalloc("bnxt_rep_info",
5472 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5474 if (!bp->rep_info) {
5475 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5478 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5479 sizeof(*bp->cfa_code_map) *
5480 BNXT_MAX_CFA_CODE, 0);
5481 if (!bp->cfa_code_map) {
5482 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5483 bnxt_free_rep_info(bp);
5487 for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5488 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5490 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5492 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5493 bnxt_free_rep_info(bp);
5497 rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
5499 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
5500 bnxt_free_rep_info(bp);
5507 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5508 struct rte_eth_devargs eth_da,
5509 struct rte_eth_dev *backing_eth_dev,
5510 const char *dev_args)
5512 struct rte_eth_dev *vf_rep_eth_dev;
5513 char name[RTE_ETH_NAME_MAX_LEN];
5514 struct bnxt *backing_bp;
5517 struct rte_kvargs *kvlist = NULL;
5519 num_rep = eth_da.nb_representor_ports;
5520 if (num_rep > BNXT_MAX_VF_REPS) {
5521 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5522 num_rep, BNXT_MAX_VF_REPS);
5526 if (num_rep >= RTE_MAX_ETHPORTS) {
5528 "nb_representor_ports = %d > %d MAX ETHPORTS\n",
5529 num_rep, RTE_MAX_ETHPORTS);
5533 backing_bp = backing_eth_dev->data->dev_private;
5535 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
5537 "Not a PF or trusted VF. No Representor support\n");
5538 /* Returning an error is not an option.
5539 * Applications are not handling this correctly
5544 if (bnxt_init_rep_info(backing_bp))
5547 for (i = 0; i < num_rep; i++) {
5548 struct bnxt_representor representor = {
5549 .vf_id = eth_da.representor_ports[i],
5550 .switch_domain_id = backing_bp->switch_domain_id,
5551 .parent_dev = backing_eth_dev
5554 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
5555 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
5556 representor.vf_id, BNXT_MAX_VF_REPS);
5560 /* representor port net_bdf_port */
5561 snprintf(name, sizeof(name), "net_%s_representor_%d",
5562 pci_dev->device.name, eth_da.representor_ports[i]);
5564 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
5567 * Handler for "rep_is_pf" devarg.
5568 * Invoked as for ex: "-w 000:00:0d.0,
5569 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5571 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
5572 bnxt_parse_devarg_rep_is_pf,
5573 (void *)&representor);
5579 * Handler for "rep_based_pf" devarg.
5580 * Invoked as for ex: "-w 000:00:0d.0,
5581 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5583 ret = rte_kvargs_process(kvlist,
5584 BNXT_DEVARG_REP_BASED_PF,
5585 bnxt_parse_devarg_rep_based_pf,
5586 (void *)&representor);
5592 * Handler for "rep_based_pf" devarg.
5593 * Invoked as for ex: "-w 000:00:0d.0,
5594 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5596 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
5597 bnxt_parse_devarg_rep_q_r2f,
5598 (void *)&representor);
5604 * Handler for "rep_based_pf" devarg.
5605 * Invoked as for ex: "-w 000:00:0d.0,
5606 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5608 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
5609 bnxt_parse_devarg_rep_q_f2r,
5610 (void *)&representor);
5616 * Handler for "rep_based_pf" devarg.
5617 * Invoked as for ex: "-w 000:00:0d.0,
5618 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5620 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
5621 bnxt_parse_devarg_rep_fc_r2f,
5622 (void *)&representor);
5628 * Handler for "rep_based_pf" devarg.
5629 * Invoked as for ex: "-w 000:00:0d.0,
5630 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5632 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
5633 bnxt_parse_devarg_rep_fc_f2r,
5634 (void *)&representor);
5641 ret = rte_eth_dev_create(&pci_dev->device, name,
5642 sizeof(struct bnxt_representor),
5644 bnxt_representor_init,
5647 PMD_DRV_LOG(ERR, "failed to create bnxt vf "
5648 "representor %s.", name);
5652 vf_rep_eth_dev = rte_eth_dev_allocated(name);
5653 if (!vf_rep_eth_dev) {
5654 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
5655 " for VF-Rep: %s.", name);
5660 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
5661 backing_eth_dev->data->port_id);
5662 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
5664 backing_bp->num_reps++;
5668 rte_kvargs_free(kvlist);
5672 /* If num_rep > 1, then rollback already created
5673 * ports, since we'll be failing the probe anyway
5676 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
5678 rte_kvargs_free(kvlist);
5683 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5684 struct rte_pci_device *pci_dev)
5686 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
5687 struct rte_eth_dev *backing_eth_dev;
5691 if (pci_dev->device.devargs) {
5692 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
5698 num_rep = eth_da.nb_representor_ports;
5699 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
5702 /* We could come here after first level of probe is already invoked
5703 * as part of an application bringup(OVS-DPDK vswitchd), so first check
5704 * for already allocated eth_dev for the backing device (PF/Trusted VF)
5706 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5707 if (backing_eth_dev == NULL) {
5708 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
5709 sizeof(struct bnxt),
5710 eth_dev_pci_specific_init, pci_dev,
5711 bnxt_dev_init, NULL);
5713 if (ret || !num_rep)
5716 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5718 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
5719 backing_eth_dev->data->port_id);
5724 /* probe representor ports now */
5725 ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev,
5726 pci_dev->device.devargs->args);
5731 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5733 struct rte_eth_dev *eth_dev;
5735 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5737 return 0; /* Invoked typically only by OVS-DPDK, by the
5738 * time it comes here the eth_dev is already
5739 * deleted by rte_eth_dev_close(), so returning
5740 * +ve value will at least help in proper cleanup
5743 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
5744 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
5745 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
5746 return rte_eth_dev_destroy(eth_dev,
5747 bnxt_representor_uninit);
5749 return rte_eth_dev_destroy(eth_dev,
5752 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5756 static struct rte_pci_driver bnxt_rte_pmd = {
5757 .id_table = bnxt_pci_id_map,
5758 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
5759 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
5762 .probe = bnxt_pci_probe,
5763 .remove = bnxt_pci_remove,
5767 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5769 if (strcmp(dev->device->driver->name, drv->driver.name))
5775 bool is_bnxt_supported(struct rte_eth_dev *dev)
5777 return is_device_supported(dev, &bnxt_rte_pmd);
5780 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
5781 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5782 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5783 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");