drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_irq.h"
  20 #include "bnxt_ring.h"
  21 #include "bnxt_rxq.h"
  22 #include "bnxt_rxr.h"
  23 #include "bnxt_stats.h"
  24 #include "bnxt_txq.h"
  25 #include "bnxt_txr.h"
  26 #include "bnxt_vnic.h"
  27 #include "hsi_struct_def_dpdk.h"
  28 #include "bnxt_nvm_defs.h"
  29 #include "bnxt_util.h"
  30
  31 #define DRV_MODULE_NAME         "bnxt"
  32 static const char bnxt_version[] =
  33         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  34 int bnxt_logtype_driver;
  35
  36 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  37
  38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  40 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
  41 #define BROADCOM_DEV_ID_57414_VF 0x16c1
  42 #define BROADCOM_DEV_ID_57301 0x16c8
  43 #define BROADCOM_DEV_ID_57302 0x16c9
  44 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  45 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  46 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  47 #define BROADCOM_DEV_ID_NS2 0x16cd
  48 #define BROADCOM_DEV_ID_57311 0x16ce
  49 #define BROADCOM_DEV_ID_57312 0x16cf
  50 #define BROADCOM_DEV_ID_57402 0x16d0
  51 #define BROADCOM_DEV_ID_57404 0x16d1
  52 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  53 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  54 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  55 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  56 #define BROADCOM_DEV_ID_57412 0x16d6
  57 #define BROADCOM_DEV_ID_57414 0x16d7
  58 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  59 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  60 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  61 #define BROADCOM_DEV_ID_57412_MF 0x16de
  62 #define BROADCOM_DEV_ID_57314 0x16df
  63 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  64 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  65 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  66 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  67 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  68 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  69 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  70 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  71 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  72 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  73 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  74 #define BROADCOM_DEV_ID_57508 0x1750
  75 #define BROADCOM_DEV_ID_57504 0x1751
  76 #define BROADCOM_DEV_ID_57502 0x1752
  77 #define BROADCOM_DEV_ID_57500_VF1 0x1806
  78 #define BROADCOM_DEV_ID_57500_VF2 0x1807
  79 #define BROADCOM_DEV_ID_58802 0xd802
  80 #define BROADCOM_DEV_ID_58804 0xd804
  81 #define BROADCOM_DEV_ID_58808 0x16f0
  82 #define BROADCOM_DEV_ID_58802_VF 0xd800
  83
  84 static const struct rte_pci_id bnxt_pci_id_map[] = {
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  86                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  88                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
 100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
 102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 119         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 121         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 122         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 123         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
 124         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
 125         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
 126         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
 127         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
 128         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
 129         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
 130         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
 131         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
 132         { .vendor_id = 0, /* sentinel */ },
 133 };
 134
 135 #define BNXT_ETH_RSS_SUPPORT (  \
 136         ETH_RSS_IPV4 |          \
 137         ETH_RSS_NONFRAG_IPV4_TCP |      \
 138         ETH_RSS_NONFRAG_IPV4_UDP |      \
 139         ETH_RSS_IPV6 |          \
 140         ETH_RSS_NONFRAG_IPV6_TCP |      \
 141         ETH_RSS_NONFRAG_IPV6_UDP)
 142
 143 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 144                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 145                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 146                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 147                                      DEV_TX_OFFLOAD_TCP_TSO | \
 148                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 149                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 150                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 151                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 152                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 153                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 154
 155 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 156                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 157                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 158                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 159                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 160                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 161                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 162                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 163                                      DEV_RX_OFFLOAD_TCP_LRO)
 164
 165 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 166 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 167 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 168 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 169
 170 int is_bnxt_in_error(struct bnxt *bp)
 171 {
 172         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 173                 return -EIO;
 174         if (bp->flags & BNXT_FLAG_FW_RESET)
 175                 return -EBUSY;
 176
 177         return 0;
 178 }
 179
 180 /***********************/
 181
 182 /*
 183  * High level utility functions
 184  */
 185
 186 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 187 {
 188         if (!BNXT_CHIP_THOR(bp))
 189                 return 1;
 190
 191         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 192                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 193                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 194 }
 195
 196 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 197 {
 198         if (!BNXT_CHIP_THOR(bp))
 199                 return HW_HASH_INDEX_SIZE;
 200
 201         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 202 }
 203
 204 static void bnxt_free_mem(struct bnxt *bp)
 205 {
 206         bnxt_free_filter_mem(bp);
 207         bnxt_free_vnic_attributes(bp);
 208         bnxt_free_vnic_mem(bp);
 209
 210         bnxt_free_stats(bp);
 211         bnxt_free_tx_rings(bp);
 212         bnxt_free_rx_rings(bp);
 213         bnxt_free_async_cp_ring(bp);
 214 }
 215
 216 static int bnxt_alloc_mem(struct bnxt *bp)
 217 {
 218         int rc;
 219
 220         rc = bnxt_alloc_ring_grps(bp);
 221         if (rc)
 222                 goto alloc_mem_err;
 223
 224         rc = bnxt_alloc_async_ring_struct(bp);
 225         if (rc)
 226                 goto alloc_mem_err;
 227
 228         rc = bnxt_alloc_vnic_mem(bp);
 229         if (rc)
 230                 goto alloc_mem_err;
 231
 232         rc = bnxt_alloc_vnic_attributes(bp);
 233         if (rc)
 234                 goto alloc_mem_err;
 235
 236         rc = bnxt_alloc_filter_mem(bp);
 237         if (rc)
 238                 goto alloc_mem_err;
 239
 240         rc = bnxt_alloc_async_cp_ring(bp);
 241         if (rc)
 242                 goto alloc_mem_err;
 243
 244         return 0;
 245
 246 alloc_mem_err:
 247         bnxt_free_mem(bp);
 248         return rc;
 249 }
 250
 251 static int bnxt_init_chip(struct bnxt *bp)
 252 {
 253         struct bnxt_rx_queue *rxq;
 254         struct rte_eth_link new;
 255         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 256         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 257         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 258         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 259         uint32_t intr_vector = 0;
 260         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 261         uint32_t vec = BNXT_MISC_VEC_ID;
 262         unsigned int i, j;
 263         int rc;
 264
 265         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 266                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 267                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 268                 bp->flags |= BNXT_FLAG_JUMBO;
 269         } else {
 270                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 271                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 272                 bp->flags &= ~BNXT_FLAG_JUMBO;
 273         }
 274
 275         /* THOR does not support ring groups.
 276          * But we will use the array to save RSS context IDs.
 277          */
 278         if (BNXT_CHIP_THOR(bp))
 279                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 280
 281         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 282         if (rc) {
 283                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 284                 goto err_out;
 285         }
 286
 287         rc = bnxt_alloc_hwrm_rings(bp);
 288         if (rc) {
 289                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 290                 goto err_out;
 291         }
 292
 293         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 294         if (rc) {
 295                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 296                 goto err_out;
 297         }
 298
 299         rc = bnxt_mq_rx_configure(bp);
 300         if (rc) {
 301                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 302                 goto err_out;
 303         }
 304
 305         /* VNIC configuration */
 306         for (i = 0; i < bp->nr_vnics; i++) {
 307                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 308                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 309                 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
 310
 311                 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
 312                 if (!vnic->fw_grp_ids) {
 313                         PMD_DRV_LOG(ERR,
 314                                     "Failed to alloc %d bytes for group ids\n",
 315                                     size);
 316                         rc = -ENOMEM;
 317                         goto err_out;
 318                 }
 319                 memset(vnic->fw_grp_ids, -1, size);
 320
 321                 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 322                             i, vnic, vnic->fw_grp_ids);
 323
 324                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 325                 if (rc) {
 326                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 327                                 i, rc);
 328                         goto err_out;
 329                 }
 330
 331                 /* Alloc RSS context only if RSS mode is enabled */
 332                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 333                         int j, nr_ctxs = bnxt_rss_ctxts(bp);
 334
 335                         rc = 0;
 336                         for (j = 0; j < nr_ctxs; j++) {
 337                                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 338                                 if (rc)
 339                                         break;
 340                         }
 341                         if (rc) {
 342                                 PMD_DRV_LOG(ERR,
 343                                   "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 344                                   i, j, rc);
 345                                 goto err_out;
 346                         }
 347                         vnic->num_lb_ctxts = nr_ctxs;
 348                 }
 349
 350                 /*
 351                  * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 352                  * setting is not available at this time, it will not be
 353                  * configured correctly in the CFA.
 354                  */
 355                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 356                         vnic->vlan_strip = true;
 357                 else
 358                         vnic->vlan_strip = false;
 359
 360                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 361                 if (rc) {
 362                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 363                                 i, rc);
 364                         goto err_out;
 365                 }
 366
 367                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 368                 if (rc) {
 369                         PMD_DRV_LOG(ERR,
 370                                 "HWRM vnic %d filter failure rc: %x\n",
 371                                 i, rc);
 372                         goto err_out;
 373                 }
 374
 375                 for (j = 0; j < bp->rx_nr_rings; j++) {
 376                         rxq = bp->eth_dev->data->rx_queues[j];
 377
 378                         PMD_DRV_LOG(DEBUG,
 379                                     "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 380                                     j, rxq->vnic, rxq->vnic->fw_grp_ids);
 381
 382                         if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 383                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 384                 }
 385
 386                 rc = bnxt_vnic_rss_configure(bp, vnic);
 387                 if (rc) {
 388                         PMD_DRV_LOG(ERR,
 389                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 390                         goto err_out;
 391                 }
 392
 393                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 394
 395                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 396                     DEV_RX_OFFLOAD_TCP_LRO)
 397                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 398                 else
 399                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 400         }
 401         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 402         if (rc) {
 403                 PMD_DRV_LOG(ERR,
 404                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 405                 goto err_out;
 406         }
 407
 408         /* check and configure queue intr-vector mapping */
 409         if ((rte_intr_cap_multiple(intr_handle) ||
 410              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 411             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 412                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 413                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 414                 if (intr_vector > bp->rx_cp_nr_rings) {
 415                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 416                                         bp->rx_cp_nr_rings);
 417                         return -ENOTSUP;
 418                 }
 419                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 420                 if (rc)
 421                         return rc;
 422         }
 423
 424         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 425                 intr_handle->intr_vec =
 426                         rte_zmalloc("intr_vec",
 427                                     bp->eth_dev->data->nb_rx_queues *
 428                                     sizeof(int), 0);
 429                 if (intr_handle->intr_vec == NULL) {
 430                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 431                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 432                         rc = -ENOMEM;
 433                         goto err_disable;
 434                 }
 435                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 436                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 437                          intr_handle->intr_vec, intr_handle->nb_efd,
 438                         intr_handle->max_intr);
 439                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 440                      queue_id++) {
 441                         intr_handle->intr_vec[queue_id] =
 442                                                         vec + BNXT_RX_VEC_START;
 443                         if (vec < base + intr_handle->nb_efd - 1)
 444                                 vec++;
 445                 }
 446         }
 447
 448         /* enable uio/vfio intr/eventfd mapping */
 449         rc = rte_intr_enable(intr_handle);
 450         if (rc)
 451                 goto err_free;
 452
 453         rc = bnxt_get_hwrm_link_config(bp, &new);
 454         if (rc) {
 455                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 456                 goto err_free;
 457         }
 458
 459         if (!bp->link_info.link_up) {
 460                 rc = bnxt_set_hwrm_link_config(bp, true);
 461                 if (rc) {
 462                         PMD_DRV_LOG(ERR,
 463                                 "HWRM link config failure rc: %x\n", rc);
 464                         goto err_free;
 465                 }
 466         }
 467         bnxt_print_link_info(bp->eth_dev);
 468
 469         return 0;
 470
 471 err_free:
 472         rte_free(intr_handle->intr_vec);
 473 err_disable:
 474         rte_intr_efd_disable(intr_handle);
 475 err_out:
 476         /* Some of the error status returned by FW may not be from errno.h */
 477         if (rc > 0)
 478                 rc = -EIO;
 479
 480         return rc;
 481 }
 482
 483 static int bnxt_shutdown_nic(struct bnxt *bp)
 484 {
 485         bnxt_free_all_hwrm_resources(bp);
 486         bnxt_free_all_filters(bp);
 487         bnxt_free_all_vnics(bp);
 488         return 0;
 489 }
 490
 491 static int bnxt_init_nic(struct bnxt *bp)
 492 {
 493         int rc;
 494
 495         if (BNXT_HAS_RING_GRPS(bp)) {
 496                 rc = bnxt_init_ring_grps(bp);
 497                 if (rc)
 498                         return rc;
 499         }
 500
 501         bnxt_init_vnics(bp);
 502         bnxt_init_filters(bp);
 503
 504         return 0;
 505 }
 506
 507 /*
 508  * Device configuration and status function
 509  */
 510
 511 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 512                                 struct rte_eth_dev_info *dev_info)
 513 {
 514         struct bnxt *bp = eth_dev->data->dev_private;
 515         uint16_t max_vnics, i, j, vpool, vrxq;
 516         unsigned int max_rx_rings;
 517         int rc;
 518
 519         rc = is_bnxt_in_error(bp);
 520         if (rc)
 521                 return rc;
 522
 523         /* MAC Specifics */
 524         dev_info->max_mac_addrs = bp->max_l2_ctx;
 525         dev_info->max_hash_mac_addrs = 0;
 526
 527         /* PF/VF specifics */
 528         if (BNXT_PF(bp))
 529                 dev_info->max_vfs = bp->pdev->max_vfs;
 530         max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
 531         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 532         dev_info->max_rx_queues = max_rx_rings;
 533         dev_info->max_tx_queues = max_rx_rings;
 534         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 535         dev_info->hash_key_size = 40;
 536         max_vnics = bp->max_vnics;
 537
 538         /* Fast path specifics */
 539         dev_info->min_rx_bufsize = 1;
 540         dev_info->max_rx_pktlen = BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +
 541                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
 542
 543         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 544         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 545                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 546         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 547         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 548
 549         /* *INDENT-OFF* */
 550         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 551                 .rx_thresh = {
 552                         .pthresh = 8,
 553                         .hthresh = 8,
 554                         .wthresh = 0,
 555                 },
 556                 .rx_free_thresh = 32,
 557                 /* If no descriptors available, pkts are dropped by default */
 558                 .rx_drop_en = 1,
 559         };
 560
 561         dev_info->default_txconf = (struct rte_eth_txconf) {
 562                 .tx_thresh = {
 563                         .pthresh = 32,
 564                         .hthresh = 0,
 565                         .wthresh = 0,
 566                 },
 567                 .tx_free_thresh = 32,
 568                 .tx_rs_thresh = 32,
 569         };
 570         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 571
 572         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 573         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 574         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 575         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 576         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 577
 578         /* *INDENT-ON* */
 579
 580         /*
 581          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 582          *       need further investigation.
 583          */
 584
 585         /* VMDq resources */
 586         vpool = 64; /* ETH_64_POOLS */
 587         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 588         for (i = 0; i < 4; vpool >>= 1, i++) {
 589                 if (max_vnics > vpool) {
 590                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 591                                 if (dev_info->max_rx_queues > vrxq) {
 592                                         if (vpool > vrxq)
 593                                                 vpool = vrxq;
 594                                         goto found;
 595                                 }
 596                         }
 597                         /* Not enough resources to support VMDq */
 598                         break;
 599                 }
 600         }
 601         /* Not enough resources to support VMDq */
 602         vpool = 0;
 603         vrxq = 0;
 604 found:
 605         dev_info->max_vmdq_pools = vpool;
 606         dev_info->vmdq_queue_num = vrxq;
 607
 608         dev_info->vmdq_pool_base = 0;
 609         dev_info->vmdq_queue_base = 0;
 610
 611         return 0;
 612 }
 613
 614 /* Configure the device based on the configuration provided */
 615 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 616 {
 617         struct bnxt *bp = eth_dev->data->dev_private;
 618         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 619         int rc;
 620
 621         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 622         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 623         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 624         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 625
 626         rc = is_bnxt_in_error(bp);
 627         if (rc)
 628                 return rc;
 629
 630         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 631                 rc = bnxt_hwrm_check_vf_rings(bp);
 632                 if (rc) {
 633                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 634                         return -ENOSPC;
 635                 }
 636
 637                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 638                 if (rc) {
 639                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 640                         return -ENOSPC;
 641                 }
 642         } else {
 643                 /* legacy driver needs to get updated values */
 644                 rc = bnxt_hwrm_func_qcaps(bp);
 645                 if (rc) {
 646                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 647                         return rc;
 648                 }
 649         }
 650
 651         /* Inherit new configurations */
 652         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 653             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 654             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 655                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 656             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 657             bp->max_stat_ctx)
 658                 goto resource_error;
 659
 660         if (BNXT_HAS_RING_GRPS(bp) &&
 661             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 662                 goto resource_error;
 663
 664         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 665             bp->max_vnics < eth_dev->data->nb_rx_queues)
 666                 goto resource_error;
 667
 668         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 669         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 670
 671         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 672                 eth_dev->data->mtu =
 673                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 674                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 675                         BNXT_NUM_VLANS;
 676                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 677         }
 678         return 0;
 679
 680 resource_error:
 681         PMD_DRV_LOG(ERR,
 682                     "Insufficient resources to support requested config\n");
 683         PMD_DRV_LOG(ERR,
 684                     "Num Queues Requested: Tx %d, Rx %d\n",
 685                     eth_dev->data->nb_tx_queues,
 686                     eth_dev->data->nb_rx_queues);
 687         PMD_DRV_LOG(ERR,
 688                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 689                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 690                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 691         return -ENOSPC;
 692 }
 693
 694 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 695 {
 696         struct rte_eth_link *link = &eth_dev->data->dev_link;
 697
 698         if (link->link_status)
 699                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 700                         eth_dev->data->port_id,
 701                         (uint32_t)link->link_speed,
 702                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 703                         ("full-duplex") : ("half-duplex\n"));
 704         else
 705                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 706                         eth_dev->data->port_id);
 707 }
 708
 709 /*
 710  * Determine whether the current configuration requires support for scattered
 711  * receive; return 1 if scattered receive is required and 0 if not.
 712  */
 713 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 714 {
 715         uint16_t buf_size;
 716         int i;
 717
 718         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 719                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 720
 721                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 722                                       RTE_PKTMBUF_HEADROOM);
 723                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 724                         return 1;
 725         }
 726         return 0;
 727 }
 728
 729 static eth_rx_burst_t
 730 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
 731 {
 732 #ifdef RTE_ARCH_X86
 733         /*
 734          * Vector mode receive can be enabled only if scatter rx is not
 735          * in use and rx offloads are limited to VLAN stripping and
 736          * CRC stripping.
 737          */
 738         if (!eth_dev->data->scattered_rx &&
 739             !(eth_dev->data->dev_conf.rxmode.offloads &
 740               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 741                 DEV_RX_OFFLOAD_KEEP_CRC |
 742                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 743                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 744                 DEV_RX_OFFLOAD_UDP_CKSUM |
 745                 DEV_RX_OFFLOAD_TCP_CKSUM |
 746                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 747                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 748                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 749                             eth_dev->data->port_id);
 750                 return bnxt_recv_pkts_vec;
 751         }
 752         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 753                     eth_dev->data->port_id);
 754         PMD_DRV_LOG(INFO,
 755                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 756                     eth_dev->data->port_id,
 757                     eth_dev->data->scattered_rx,
 758                     eth_dev->data->dev_conf.rxmode.offloads);
 759 #endif
 760         return bnxt_recv_pkts;
 761 }
 762
 763 static eth_tx_burst_t
 764 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 765 {
 766 #ifdef RTE_ARCH_X86
 767         /*
 768          * Vector mode transmit can be enabled only if not using scatter rx
 769          * or tx offloads.
 770          */
 771         if (!eth_dev->data->scattered_rx &&
 772             !eth_dev->data->dev_conf.txmode.offloads) {
 773                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 774                             eth_dev->data->port_id);
 775                 return bnxt_xmit_pkts_vec;
 776         }
 777         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 778                     eth_dev->data->port_id);
 779         PMD_DRV_LOG(INFO,
 780                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 781                     eth_dev->data->port_id,
 782                     eth_dev->data->scattered_rx,
 783                     eth_dev->data->dev_conf.txmode.offloads);
 784 #endif
 785         return bnxt_xmit_pkts;
 786 }
 787
 788 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 789 {
 790         struct bnxt *bp = eth_dev->data->dev_private;
 791         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 792         int vlan_mask = 0;
 793         int rc;
 794
 795         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 796                 PMD_DRV_LOG(ERR,
 797                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 798                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 799         }
 800
 801         rc = bnxt_init_chip(bp);
 802         if (rc)
 803                 goto error;
 804
 805         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 806
 807         bnxt_link_update_op(eth_dev, 1);
 808
 809         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 810                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 811         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 812                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 813         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 814         if (rc)
 815                 goto error;
 816
 817         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 818         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 819
 820         bnxt_enable_int(bp);
 821         bp->flags |= BNXT_FLAG_INIT_DONE;
 822         eth_dev->data->dev_started = 1;
 823         bp->dev_stopped = 0;
 824         return 0;
 825
 826 error:
 827         bnxt_shutdown_nic(bp);
 828         bnxt_free_tx_mbufs(bp);
 829         bnxt_free_rx_mbufs(bp);
 830         return rc;
 831 }
 832
 833 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 834 {
 835         struct bnxt *bp = eth_dev->data->dev_private;
 836         int rc = 0;
 837
 838         if (!bp->link_info.link_up)
 839                 rc = bnxt_set_hwrm_link_config(bp, true);
 840         if (!rc)
 841                 eth_dev->data->dev_link.link_status = 1;
 842
 843         bnxt_print_link_info(eth_dev);
 844         return 0;
 845 }
 846
 847 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 848 {
 849         struct bnxt *bp = eth_dev->data->dev_private;
 850
 851         eth_dev->data->dev_link.link_status = 0;
 852         bnxt_set_hwrm_link_config(bp, false);
 853         bp->link_info.link_up = 0;
 854
 855         return 0;
 856 }
 857
 858 /* Unload the driver, release resources */
 859 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 860 {
 861         struct bnxt *bp = eth_dev->data->dev_private;
 862         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 863         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 864
 865         eth_dev->data->dev_started = 0;
 866         /* Prevent crashes when queues are still in use */
 867         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
 868         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
 869
 870         bnxt_disable_int(bp);
 871
 872         /* disable uio/vfio intr/eventfd mapping */
 873         rte_intr_disable(intr_handle);
 874
 875         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 876         if (bp->eth_dev->data->dev_started) {
 877                 /* TBD: STOP HW queues DMA */
 878                 eth_dev->data->dev_link.link_status = 0;
 879         }
 880         bnxt_set_hwrm_link_config(bp, false);
 881
 882         /* Clean queue intr-vector mapping */
 883         rte_intr_efd_disable(intr_handle);
 884         if (intr_handle->intr_vec != NULL) {
 885                 rte_free(intr_handle->intr_vec);
 886                 intr_handle->intr_vec = NULL;
 887         }
 888
 889         bnxt_hwrm_port_clr_stats(bp);
 890         bnxt_free_tx_mbufs(bp);
 891         bnxt_free_rx_mbufs(bp);
 892         bnxt_shutdown_nic(bp);
 893         bp->dev_stopped = 1;
 894 }
 895
 896 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 897 {
 898         struct bnxt *bp = eth_dev->data->dev_private;
 899
 900         if (bp->dev_stopped == 0)
 901                 bnxt_dev_stop_op(eth_dev);
 902
 903         if (eth_dev->data->mac_addrs != NULL) {
 904                 rte_free(eth_dev->data->mac_addrs);
 905                 eth_dev->data->mac_addrs = NULL;
 906         }
 907         if (bp->grp_info != NULL) {
 908                 rte_free(bp->grp_info);
 909                 bp->grp_info = NULL;
 910         }
 911
 912         bnxt_dev_uninit(eth_dev);
 913 }
 914
 915 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 916                                     uint32_t index)
 917 {
 918         struct bnxt *bp = eth_dev->data->dev_private;
 919         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 920         struct bnxt_vnic_info *vnic;
 921         struct bnxt_filter_info *filter, *temp_filter;
 922         uint32_t i;
 923
 924         if (is_bnxt_in_error(bp))
 925                 return;
 926
 927         /*
 928          * Loop through all VNICs from the specified filter flow pools to
 929          * remove the corresponding MAC addr filter
 930          */
 931         for (i = 0; i < bp->nr_vnics; i++) {
 932                 if (!(pool_mask & (1ULL << i)))
 933                         continue;
 934
 935                 vnic = &bp->vnic_info[i];
 936                 filter = STAILQ_FIRST(&vnic->filter);
 937                 while (filter) {
 938                         temp_filter = STAILQ_NEXT(filter, next);
 939                         if (filter->mac_index == index) {
 940                                 STAILQ_REMOVE(&vnic->filter, filter,
 941                                                 bnxt_filter_info, next);
 942                                 bnxt_hwrm_clear_l2_filter(bp, filter);
 943                                 filter->mac_index = INVALID_MAC_INDEX;
 944                                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
 945                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
 946                                                    filter, next);
 947                         }
 948                         filter = temp_filter;
 949                 }
 950         }
 951 }
 952
 953 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
 954                                 struct rte_ether_addr *mac_addr,
 955                                 uint32_t index, uint32_t pool)
 956 {
 957         struct bnxt *bp = eth_dev->data->dev_private;
 958         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
 959         struct bnxt_filter_info *filter;
 960         int rc = 0;
 961
 962         rc = is_bnxt_in_error(bp);
 963         if (rc)
 964                 return rc;
 965
 966         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
 967                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
 968                 return -ENOTSUP;
 969         }
 970
 971         if (!vnic) {
 972                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
 973                 return -EINVAL;
 974         }
 975         /* Attach requested MAC address to the new l2_filter */
 976         STAILQ_FOREACH(filter, &vnic->filter, next) {
 977                 if (filter->mac_index == index) {
 978                         PMD_DRV_LOG(ERR,
 979                                 "MAC addr already existed for pool %d\n", pool);
 980                         return 0;
 981                 }
 982         }
 983         filter = bnxt_alloc_filter(bp);
 984         if (!filter) {
 985                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
 986                 return -ENODEV;
 987         }
 988
 989         filter->mac_index = index;
 990         memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
 991
 992         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
 993         if (!rc) {
 994                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
 995         } else {
 996                 filter->mac_index = INVALID_MAC_INDEX;
 997                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
 998                 bnxt_free_filter(bp, filter);
 999         }
1000
1001         return rc;
1002 }
1003
1004 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1005 {
1006         int rc = 0;
1007         struct bnxt *bp = eth_dev->data->dev_private;
1008         struct rte_eth_link new;
1009         unsigned int cnt = BNXT_LINK_WAIT_CNT;
1010
1011         rc = is_bnxt_in_error(bp);
1012         if (rc)
1013                 return rc;
1014
1015         memset(&new, 0, sizeof(new));
1016         do {
1017                 /* Retrieve link info from hardware */
1018                 rc = bnxt_get_hwrm_link_config(bp, &new);
1019                 if (rc) {
1020                         new.link_speed = ETH_LINK_SPEED_100M;
1021                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1022                         PMD_DRV_LOG(ERR,
1023                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1024                         goto out;
1025                 }
1026
1027                 if (!wait_to_complete || new.link_status)
1028                         break;
1029
1030                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1031         } while (cnt--);
1032
1033 out:
1034         /* Timed out or success */
1035         if (new.link_status != eth_dev->data->dev_link.link_status ||
1036         new.link_speed != eth_dev->data->dev_link.link_speed) {
1037                 memcpy(&eth_dev->data->dev_link, &new,
1038                         sizeof(struct rte_eth_link));
1039
1040                 _rte_eth_dev_callback_process(eth_dev,
1041                                               RTE_ETH_EVENT_INTR_LSC,
1042                                               NULL);
1043
1044                 bnxt_print_link_info(eth_dev);
1045         }
1046
1047         return rc;
1048 }
1049
1050 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1051 {
1052         struct bnxt *bp = eth_dev->data->dev_private;
1053         struct bnxt_vnic_info *vnic;
1054         uint32_t old_flags;
1055         int rc;
1056
1057         rc = is_bnxt_in_error(bp);
1058         if (rc)
1059                 return rc;
1060
1061         if (bp->vnic_info == NULL)
1062                 return 0;
1063
1064         vnic = &bp->vnic_info[0];
1065
1066         old_flags = vnic->flags;
1067         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1068         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1069         if (rc != 0)
1070                 vnic->flags = old_flags;
1071
1072         return rc;
1073 }
1074
1075 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1076 {
1077         struct bnxt *bp = eth_dev->data->dev_private;
1078         struct bnxt_vnic_info *vnic;
1079         uint32_t old_flags;
1080         int rc;
1081
1082         rc = is_bnxt_in_error(bp);
1083         if (rc)
1084                 return rc;
1085
1086         if (bp->vnic_info == NULL)
1087                 return 0;
1088
1089         vnic = &bp->vnic_info[0];
1090
1091         old_flags = vnic->flags;
1092         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1093         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1094         if (rc != 0)
1095                 vnic->flags = old_flags;
1096
1097         return rc;
1098 }
1099
1100 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1101 {
1102         struct bnxt *bp = eth_dev->data->dev_private;
1103         struct bnxt_vnic_info *vnic;
1104         uint32_t old_flags;
1105         int rc;
1106
1107         rc = is_bnxt_in_error(bp);
1108         if (rc)
1109                 return rc;
1110
1111         if (bp->vnic_info == NULL)
1112                 return 0;
1113
1114         vnic = &bp->vnic_info[0];
1115
1116         old_flags = vnic->flags;
1117         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1118         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1119         if (rc != 0)
1120                 vnic->flags = old_flags;
1121
1122         return rc;
1123 }
1124
1125 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1126 {
1127         struct bnxt *bp = eth_dev->data->dev_private;
1128         struct bnxt_vnic_info *vnic;
1129         uint32_t old_flags;
1130         int rc;
1131
1132         rc = is_bnxt_in_error(bp);
1133         if (rc)
1134                 return rc;
1135
1136         if (bp->vnic_info == NULL)
1137                 return 0;
1138
1139         vnic = &bp->vnic_info[0];
1140
1141         old_flags = vnic->flags;
1142         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1143         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1144         if (rc != 0)
1145                 vnic->flags = old_flags;
1146
1147         return rc;
1148 }
1149
1150 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1151 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1152 {
1153         if (qid >= bp->rx_nr_rings)
1154                 return NULL;
1155
1156         return bp->eth_dev->data->rx_queues[qid];
1157 }
1158
1159 /* Return rxq corresponding to a given rss table ring/group ID. */
1160 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1161 {
1162         struct bnxt_rx_queue *rxq;
1163         unsigned int i;
1164
1165         if (!BNXT_HAS_RING_GRPS(bp)) {
1166                 for (i = 0; i < bp->rx_nr_rings; i++) {
1167                         rxq = bp->eth_dev->data->rx_queues[i];
1168                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1169                                 return rxq->index;
1170                 }
1171         } else {
1172                 for (i = 0; i < bp->rx_nr_rings; i++) {
1173                         if (bp->grp_info[i].fw_grp_id == fwr)
1174                                 return i;
1175                 }
1176         }
1177
1178         return INVALID_HW_RING_ID;
1179 }
1180
1181 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1182                             struct rte_eth_rss_reta_entry64 *reta_conf,
1183                             uint16_t reta_size)
1184 {
1185         struct bnxt *bp = eth_dev->data->dev_private;
1186         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1187         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1188         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1189         uint16_t idx, sft;
1190         int i, rc;
1191
1192         rc = is_bnxt_in_error(bp);
1193         if (rc)
1194                 return rc;
1195
1196         if (!vnic->rss_table)
1197                 return -EINVAL;
1198
1199         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1200                 return -EINVAL;
1201
1202         if (reta_size != tbl_size) {
1203                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1204                         "(%d) must equal the size supported by the hardware "
1205                         "(%d)\n", reta_size, tbl_size);
1206                 return -EINVAL;
1207         }
1208
1209         for (i = 0; i < reta_size; i++) {
1210                 struct bnxt_rx_queue *rxq;
1211
1212                 idx = i / RTE_RETA_GROUP_SIZE;
1213                 sft = i % RTE_RETA_GROUP_SIZE;
1214
1215                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1216                         continue;
1217
1218                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1219                 if (!rxq) {
1220                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1221                         return -EINVAL;
1222                 }
1223
1224                 if (BNXT_CHIP_THOR(bp)) {
1225                         vnic->rss_table[i * 2] =
1226                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1227                         vnic->rss_table[i * 2 + 1] =
1228                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1229                 } else {
1230                         vnic->rss_table[i] =
1231                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1232                 }
1233
1234                 vnic->rss_table[i] =
1235                     vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1236         }
1237
1238         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1239         return 0;
1240 }
1241
1242 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1243                               struct rte_eth_rss_reta_entry64 *reta_conf,
1244                               uint16_t reta_size)
1245 {
1246         struct bnxt *bp = eth_dev->data->dev_private;
1247         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1248         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1249         uint16_t idx, sft, i;
1250         int rc;
1251
1252         rc = is_bnxt_in_error(bp);
1253         if (rc)
1254                 return rc;
1255
1256         /* Retrieve from the default VNIC */
1257         if (!vnic)
1258                 return -EINVAL;
1259         if (!vnic->rss_table)
1260                 return -EINVAL;
1261
1262         if (reta_size != tbl_size) {
1263                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1264                         "(%d) must equal the size supported by the hardware "
1265                         "(%d)\n", reta_size, tbl_size);
1266                 return -EINVAL;
1267         }
1268
1269         for (idx = 0, i = 0; i < reta_size; i++) {
1270                 idx = i / RTE_RETA_GROUP_SIZE;
1271                 sft = i % RTE_RETA_GROUP_SIZE;
1272
1273                 if (reta_conf[idx].mask & (1ULL << sft)) {
1274                         uint16_t qid;
1275
1276                         if (BNXT_CHIP_THOR(bp))
1277                                 qid = bnxt_rss_to_qid(bp,
1278                                                       vnic->rss_table[i * 2]);
1279                         else
1280                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1281
1282                         if (qid == INVALID_HW_RING_ID) {
1283                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1284                                 return -EINVAL;
1285                         }
1286                         reta_conf[idx].reta[sft] = qid;
1287                 }
1288         }
1289
1290         return 0;
1291 }
1292
1293 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1294                                    struct rte_eth_rss_conf *rss_conf)
1295 {
1296         struct bnxt *bp = eth_dev->data->dev_private;
1297         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1298         struct bnxt_vnic_info *vnic;
1299         uint16_t hash_type = 0;
1300         unsigned int i;
1301         int rc;
1302
1303         rc = is_bnxt_in_error(bp);
1304         if (rc)
1305                 return rc;
1306
1307         /*
1308          * If RSS enablement were different than dev_configure,
1309          * then return -EINVAL
1310          */
1311         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1312                 if (!rss_conf->rss_hf)
1313                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1314         } else {
1315                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1316                         return -EINVAL;
1317         }
1318
1319         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1320         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1321
1322         if (rss_conf->rss_hf & ETH_RSS_IPV4)
1323                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1324         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1325                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1326         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1327                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1328         if (rss_conf->rss_hf & ETH_RSS_IPV6)
1329                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1330         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1331                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1332         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1333                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1334
1335         /* Update the RSS VNIC(s) */
1336         for (i = 0; i < bp->nr_vnics; i++) {
1337                 vnic = &bp->vnic_info[i];
1338                 vnic->hash_type = hash_type;
1339
1340                 /*
1341                  * Use the supplied key if the key length is
1342                  * acceptable and the rss_key is not NULL
1343                  */
1344                 if (rss_conf->rss_key &&
1345                     rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1346                         memcpy(vnic->rss_hash_key, rss_conf->rss_key,
1347                                rss_conf->rss_key_len);
1348
1349                 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1350         }
1351         return 0;
1352 }
1353
1354 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1355                                      struct rte_eth_rss_conf *rss_conf)
1356 {
1357         struct bnxt *bp = eth_dev->data->dev_private;
1358         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1359         int len, rc;
1360         uint32_t hash_types;
1361
1362         rc = is_bnxt_in_error(bp);
1363         if (rc)
1364                 return rc;
1365
1366         /* RSS configuration is the same for all VNICs */
1367         if (vnic && vnic->rss_hash_key) {
1368                 if (rss_conf->rss_key) {
1369                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1370                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1371                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1372                 }
1373
1374                 hash_types = vnic->hash_type;
1375                 rss_conf->rss_hf = 0;
1376                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1377                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1378                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1379                 }
1380                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1381                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1382                         hash_types &=
1383                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1384                 }
1385                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1386                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1387                         hash_types &=
1388                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1389                 }
1390                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1391                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1392                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1393                 }
1394                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1395                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1396                         hash_types &=
1397                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1398                 }
1399                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1400                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1401                         hash_types &=
1402                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1403                 }
1404                 if (hash_types) {
1405                         PMD_DRV_LOG(ERR,
1406                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1407                                 vnic->hash_type);
1408                         return -ENOTSUP;
1409                 }
1410         } else {
1411                 rss_conf->rss_hf = 0;
1412         }
1413         return 0;
1414 }
1415
1416 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1417                                struct rte_eth_fc_conf *fc_conf)
1418 {
1419         struct bnxt *bp = dev->data->dev_private;
1420         struct rte_eth_link link_info;
1421         int rc;
1422
1423         rc = is_bnxt_in_error(bp);
1424         if (rc)
1425                 return rc;
1426
1427         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1428         if (rc)
1429                 return rc;
1430
1431         memset(fc_conf, 0, sizeof(*fc_conf));
1432         if (bp->link_info.auto_pause)
1433                 fc_conf->autoneg = 1;
1434         switch (bp->link_info.pause) {
1435         case 0:
1436                 fc_conf->mode = RTE_FC_NONE;
1437                 break;
1438         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1439                 fc_conf->mode = RTE_FC_TX_PAUSE;
1440                 break;
1441         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1442                 fc_conf->mode = RTE_FC_RX_PAUSE;
1443                 break;
1444         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1445                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1446                 fc_conf->mode = RTE_FC_FULL;
1447                 break;
1448         }
1449         return 0;
1450 }
1451
1452 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1453                                struct rte_eth_fc_conf *fc_conf)
1454 {
1455         struct bnxt *bp = dev->data->dev_private;
1456         int rc;
1457
1458         rc = is_bnxt_in_error(bp);
1459         if (rc)
1460                 return rc;
1461
1462         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1463                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1464                 return -ENOTSUP;
1465         }
1466
1467         switch (fc_conf->mode) {
1468         case RTE_FC_NONE:
1469                 bp->link_info.auto_pause = 0;
1470                 bp->link_info.force_pause = 0;
1471                 break;
1472         case RTE_FC_RX_PAUSE:
1473                 if (fc_conf->autoneg) {
1474                         bp->link_info.auto_pause =
1475                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1476                         bp->link_info.force_pause = 0;
1477                 } else {
1478                         bp->link_info.auto_pause = 0;
1479                         bp->link_info.force_pause =
1480                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1481                 }
1482                 break;
1483         case RTE_FC_TX_PAUSE:
1484                 if (fc_conf->autoneg) {
1485                         bp->link_info.auto_pause =
1486                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1487                         bp->link_info.force_pause = 0;
1488                 } else {
1489                         bp->link_info.auto_pause = 0;
1490                         bp->link_info.force_pause =
1491                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1492                 }
1493                 break;
1494         case RTE_FC_FULL:
1495                 if (fc_conf->autoneg) {
1496                         bp->link_info.auto_pause =
1497                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1498                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1499                         bp->link_info.force_pause = 0;
1500                 } else {
1501                         bp->link_info.auto_pause = 0;
1502                         bp->link_info.force_pause =
1503                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1504                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1505                 }
1506                 break;
1507         }
1508         return bnxt_set_hwrm_link_config(bp, true);
1509 }
1510
1511 /* Add UDP tunneling port */
1512 static int
1513 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1514                          struct rte_eth_udp_tunnel *udp_tunnel)
1515 {
1516         struct bnxt *bp = eth_dev->data->dev_private;
1517         uint16_t tunnel_type = 0;
1518         int rc = 0;
1519
1520         rc = is_bnxt_in_error(bp);
1521         if (rc)
1522                 return rc;
1523
1524         switch (udp_tunnel->prot_type) {
1525         case RTE_TUNNEL_TYPE_VXLAN:
1526                 if (bp->vxlan_port_cnt) {
1527                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1528                                 udp_tunnel->udp_port);
1529                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1530                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1531                                 return -ENOSPC;
1532                         }
1533                         bp->vxlan_port_cnt++;
1534                         return 0;
1535                 }
1536                 tunnel_type =
1537                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1538                 bp->vxlan_port_cnt++;
1539                 break;
1540         case RTE_TUNNEL_TYPE_GENEVE:
1541                 if (bp->geneve_port_cnt) {
1542                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1543                                 udp_tunnel->udp_port);
1544                         if (bp->geneve_port != udp_tunnel->udp_port) {
1545                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1546                                 return -ENOSPC;
1547                         }
1548                         bp->geneve_port_cnt++;
1549                         return 0;
1550                 }
1551                 tunnel_type =
1552                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1553                 bp->geneve_port_cnt++;
1554                 break;
1555         default:
1556                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1557                 return -ENOTSUP;
1558         }
1559         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1560                                              tunnel_type);
1561         return rc;
1562 }
1563
1564 static int
1565 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1566                          struct rte_eth_udp_tunnel *udp_tunnel)
1567 {
1568         struct bnxt *bp = eth_dev->data->dev_private;
1569         uint16_t tunnel_type = 0;
1570         uint16_t port = 0;
1571         int rc = 0;
1572
1573         rc = is_bnxt_in_error(bp);
1574         if (rc)
1575                 return rc;
1576
1577         switch (udp_tunnel->prot_type) {
1578         case RTE_TUNNEL_TYPE_VXLAN:
1579                 if (!bp->vxlan_port_cnt) {
1580                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1581                         return -EINVAL;
1582                 }
1583                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1584                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1585                                 udp_tunnel->udp_port, bp->vxlan_port);
1586                         return -EINVAL;
1587                 }
1588                 if (--bp->vxlan_port_cnt)
1589                         return 0;
1590
1591                 tunnel_type =
1592                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1593                 port = bp->vxlan_fw_dst_port_id;
1594                 break;
1595         case RTE_TUNNEL_TYPE_GENEVE:
1596                 if (!bp->geneve_port_cnt) {
1597                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1598                         return -EINVAL;
1599                 }
1600                 if (bp->geneve_port != udp_tunnel->udp_port) {
1601                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1602                                 udp_tunnel->udp_port, bp->geneve_port);
1603                         return -EINVAL;
1604                 }
1605                 if (--bp->geneve_port_cnt)
1606                         return 0;
1607
1608                 tunnel_type =
1609                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1610                 port = bp->geneve_fw_dst_port_id;
1611                 break;
1612         default:
1613                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1614                 return -ENOTSUP;
1615         }
1616
1617         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1618         if (!rc) {
1619                 if (tunnel_type ==
1620                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1621                         bp->vxlan_port = 0;
1622                 if (tunnel_type ==
1623                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1624                         bp->geneve_port = 0;
1625         }
1626         return rc;
1627 }
1628
1629 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1630 {
1631         struct bnxt_filter_info *filter;
1632         struct bnxt_vnic_info *vnic;
1633         int rc = 0;
1634         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1635
1636         /* if VLAN exists && VLAN matches vlan_id
1637          *      remove the MAC+VLAN filter
1638          *      add a new MAC only filter
1639          * else
1640          *      VLAN filter doesn't exist, just skip and continue
1641          */
1642         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1643         filter = STAILQ_FIRST(&vnic->filter);
1644         while (filter) {
1645                 /* Search for this matching MAC+VLAN filter */
1646                 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1647                     !memcmp(filter->l2_addr,
1648                             bp->mac_addr,
1649                             RTE_ETHER_ADDR_LEN)) {
1650                         /* Delete the filter */
1651                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1652                         if (rc)
1653                                 return rc;
1654                         STAILQ_REMOVE(&vnic->filter, filter,
1655                                       bnxt_filter_info, next);
1656                         STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1657
1658                         PMD_DRV_LOG(INFO,
1659                                     "Del Vlan filter for %d\n",
1660                                     vlan_id);
1661                         return rc;
1662                 }
1663                 filter = STAILQ_NEXT(filter, next);
1664         }
1665         return -ENOENT;
1666 }
1667
1668 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1669 {
1670         struct bnxt_filter_info *filter;
1671         struct bnxt_vnic_info *vnic;
1672         int rc = 0;
1673         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1674                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1675         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1676
1677         /* Implementation notes on the use of VNIC in this command:
1678          *
1679          * By default, these filters belong to default vnic for the function.
1680          * Once these filters are set up, only destination VNIC can be modified.
1681          * If the destination VNIC is not specified in this command,
1682          * then the HWRM shall only create an l2 context id.
1683          */
1684
1685         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1686         filter = STAILQ_FIRST(&vnic->filter);
1687         /* Check if the VLAN has already been added */
1688         while (filter) {
1689                 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1690                     !memcmp(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN))
1691                         return -EEXIST;
1692
1693                 filter = STAILQ_NEXT(filter, next);
1694         }
1695
1696         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1697          * command to create MAC+VLAN filter with the right flags, enables set.
1698          */
1699         filter = bnxt_alloc_filter(bp);
1700         if (!filter) {
1701                 PMD_DRV_LOG(ERR,
1702                             "MAC/VLAN filter alloc failed\n");
1703                 return -ENOMEM;
1704         }
1705         /* MAC + VLAN ID filter */
1706         filter->l2_ivlan = vlan_id;
1707         filter->l2_ivlan_mask = 0x0FFF;
1708         filter->enables |= en;
1709         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1710         if (rc) {
1711                 /* Free the newly allocated filter as we were
1712                  * not able to create the filter in hardware.
1713                  */
1714                 filter->fw_l2_filter_id = UINT64_MAX;
1715                 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1716                 return rc;
1717         }
1718
1719         /* Add this new filter to the list */
1720         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1721         PMD_DRV_LOG(INFO,
1722                     "Added Vlan filter for %d\n", vlan_id);
1723         return rc;
1724 }
1725
1726 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1727                 uint16_t vlan_id, int on)
1728 {
1729         struct bnxt *bp = eth_dev->data->dev_private;
1730         int rc;
1731
1732         rc = is_bnxt_in_error(bp);
1733         if (rc)
1734                 return rc;
1735
1736         /* These operations apply to ALL existing MAC/VLAN filters */
1737         if (on)
1738                 return bnxt_add_vlan_filter(bp, vlan_id);
1739         else
1740                 return bnxt_del_vlan_filter(bp, vlan_id);
1741 }
1742
1743 static int
1744 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1745 {
1746         struct bnxt *bp = dev->data->dev_private;
1747         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1748         unsigned int i;
1749         int rc;
1750
1751         rc = is_bnxt_in_error(bp);
1752         if (rc)
1753                 return rc;
1754
1755         if (mask & ETH_VLAN_FILTER_MASK) {
1756                 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1757                         /* Remove any VLAN filters programmed */
1758                         for (i = 0; i < 4095; i++)
1759                                 bnxt_del_vlan_filter(bp, i);
1760                 }
1761                 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1762                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1763         }
1764
1765         if (mask & ETH_VLAN_STRIP_MASK) {
1766                 /* Enable or disable VLAN stripping */
1767                 for (i = 0; i < bp->nr_vnics; i++) {
1768                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1769                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1770                                 vnic->vlan_strip = true;
1771                         else
1772                                 vnic->vlan_strip = false;
1773                         bnxt_hwrm_vnic_cfg(bp, vnic);
1774                 }
1775                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1776                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1777         }
1778
1779         if (mask & ETH_VLAN_EXTEND_MASK)
1780                 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1781
1782         return 0;
1783 }
1784
1785 static int
1786 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1787                         struct rte_ether_addr *addr)
1788 {
1789         struct bnxt *bp = dev->data->dev_private;
1790         /* Default Filter is tied to VNIC 0 */
1791         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1792         struct bnxt_filter_info *filter;
1793         int rc;
1794
1795         rc = is_bnxt_in_error(bp);
1796         if (rc)
1797                 return rc;
1798
1799         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1800                 return -EPERM;
1801
1802         if (rte_is_zero_ether_addr(addr))
1803                 return -EINVAL;
1804
1805         STAILQ_FOREACH(filter, &vnic->filter, next) {
1806                 /* Default Filter is at Index 0 */
1807                 if (filter->mac_index != 0)
1808                         continue;
1809
1810                 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
1811                 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1812                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1813                 filter->enables |=
1814                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1815                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1816
1817                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1818                 if (rc)
1819                         return rc;
1820
1821                 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
1822                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1823                 return 0;
1824         }
1825
1826         return 0;
1827 }
1828
1829 static int
1830 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1831                           struct rte_ether_addr *mc_addr_set,
1832                           uint32_t nb_mc_addr)
1833 {
1834         struct bnxt *bp = eth_dev->data->dev_private;
1835         char *mc_addr_list = (char *)mc_addr_set;
1836         struct bnxt_vnic_info *vnic;
1837         uint32_t off = 0, i = 0;
1838         int rc;
1839
1840         rc = is_bnxt_in_error(bp);
1841         if (rc)
1842                 return rc;
1843
1844         vnic = &bp->vnic_info[0];
1845
1846         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1847                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1848                 goto allmulti;
1849         }
1850
1851         /* TODO Check for Duplicate mcast addresses */
1852         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1853         for (i = 0; i < nb_mc_addr; i++) {
1854                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1855                         RTE_ETHER_ADDR_LEN);
1856                 off += RTE_ETHER_ADDR_LEN;
1857         }
1858
1859         vnic->mc_addr_cnt = i;
1860
1861 allmulti:
1862         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1863 }
1864
1865 static int
1866 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1867 {
1868         struct bnxt *bp = dev->data->dev_private;
1869         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1870         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1871         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1872         int ret;
1873
1874         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1875                         fw_major, fw_minor, fw_updt);
1876
1877         ret += 1; /* add the size of '\0' */
1878         if (fw_size < (uint32_t)ret)
1879                 return ret;
1880         else
1881                 return 0;
1882 }
1883
1884 static void
1885 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1886         struct rte_eth_rxq_info *qinfo)
1887 {
1888         struct bnxt_rx_queue *rxq;
1889
1890         rxq = dev->data->rx_queues[queue_id];
1891
1892         qinfo->mp = rxq->mb_pool;
1893         qinfo->scattered_rx = dev->data->scattered_rx;
1894         qinfo->nb_desc = rxq->nb_rx_desc;
1895
1896         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1897         qinfo->conf.rx_drop_en = 0;
1898         qinfo->conf.rx_deferred_start = 0;
1899 }
1900
1901 static void
1902 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1903         struct rte_eth_txq_info *qinfo)
1904 {
1905         struct bnxt_tx_queue *txq;
1906
1907         txq = dev->data->tx_queues[queue_id];
1908
1909         qinfo->nb_desc = txq->nb_tx_desc;
1910
1911         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1912         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1913         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1914
1915         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1916         qinfo->conf.tx_rs_thresh = 0;
1917         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1918 }
1919
1920 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1921 {
1922         struct bnxt *bp = eth_dev->data->dev_private;
1923         struct rte_eth_dev_info dev_info;
1924         uint32_t new_pkt_size;
1925         uint32_t rc = 0;
1926         uint32_t i;
1927
1928         rc = is_bnxt_in_error(bp);
1929         if (rc)
1930                 return rc;
1931
1932         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1933                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
1934
1935         rc = bnxt_dev_info_get_op(eth_dev, &dev_info);
1936         if (rc != 0) {
1937                 PMD_DRV_LOG(ERR, "Error during getting ethernet device info\n");
1938                 return rc;
1939         }
1940
1941         if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > BNXT_MAX_MTU) {
1942                 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1943                         RTE_ETHER_MIN_MTU, BNXT_MAX_MTU);
1944                 return -EINVAL;
1945         }
1946
1947 #ifdef RTE_ARCH_X86
1948         /*
1949          * If vector-mode tx/rx is active, disallow any MTU change that would
1950          * require scattered receive support.
1951          */
1952         if (eth_dev->data->dev_started &&
1953             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
1954              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
1955             (new_pkt_size >
1956              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
1957                 PMD_DRV_LOG(ERR,
1958                             "MTU change would require scattered rx support. ");
1959                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
1960                 return -EINVAL;
1961         }
1962 #endif
1963
1964         if (new_mtu > RTE_ETHER_MTU) {
1965                 bp->flags |= BNXT_FLAG_JUMBO;
1966                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1967                         DEV_RX_OFFLOAD_JUMBO_FRAME;
1968         } else {
1969                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1970                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1971                 bp->flags &= ~BNXT_FLAG_JUMBO;
1972         }
1973
1974         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
1975
1976         eth_dev->data->mtu = new_mtu;
1977         PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1978
1979         for (i = 0; i < bp->nr_vnics; i++) {
1980                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1981                 uint16_t size = 0;
1982
1983                 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1984                                         RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1985                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1986                 if (rc)
1987                         break;
1988
1989                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1990                 size -= RTE_PKTMBUF_HEADROOM;
1991
1992                 if (size < new_mtu) {
1993                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1994                         if (rc)
1995                                 return rc;
1996                 }
1997         }
1998
1999         return rc;
2000 }
2001
2002 static int
2003 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2004 {
2005         struct bnxt *bp = dev->data->dev_private;
2006         uint16_t vlan = bp->vlan;
2007         int rc;
2008
2009         rc = is_bnxt_in_error(bp);
2010         if (rc)
2011                 return rc;
2012
2013         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2014                 PMD_DRV_LOG(ERR,
2015                         "PVID cannot be modified for this function\n");
2016                 return -ENOTSUP;
2017         }
2018         bp->vlan = on ? pvid : 0;
2019
2020         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2021         if (rc)
2022                 bp->vlan = vlan;
2023         return rc;
2024 }
2025
2026 static int
2027 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2028 {
2029         struct bnxt *bp = dev->data->dev_private;
2030         int rc;
2031
2032         rc = is_bnxt_in_error(bp);
2033         if (rc)
2034                 return rc;
2035
2036         return bnxt_hwrm_port_led_cfg(bp, true);
2037 }
2038
2039 static int
2040 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2041 {
2042         struct bnxt *bp = dev->data->dev_private;
2043         int rc;
2044
2045         rc = is_bnxt_in_error(bp);
2046         if (rc)
2047                 return rc;
2048
2049         return bnxt_hwrm_port_led_cfg(bp, false);
2050 }
2051
2052 static uint32_t
2053 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2054 {
2055         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2056         uint32_t desc = 0, raw_cons = 0, cons;
2057         struct bnxt_cp_ring_info *cpr;
2058         struct bnxt_rx_queue *rxq;
2059         struct rx_pkt_cmpl *rxcmp;
2060         uint16_t cmp_type;
2061         uint8_t cmp = 1;
2062         bool valid;
2063         int rc;
2064
2065         rc = is_bnxt_in_error(bp);
2066         if (rc)
2067                 return rc;
2068
2069         rxq = dev->data->rx_queues[rx_queue_id];
2070         cpr = rxq->cp_ring;
2071         valid = cpr->valid;
2072
2073         while (raw_cons < rxq->nb_rx_desc) {
2074                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2075                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2076
2077                 if (!CMPL_VALID(rxcmp, valid))
2078                         goto nothing_to_do;
2079                 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
2080                 cmp_type = CMP_TYPE(rxcmp);
2081                 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
2082                         cmp = (rte_le_to_cpu_32(
2083                                         ((struct rx_tpa_end_cmpl *)
2084                                          (rxcmp))->agg_bufs_v1) &
2085                                RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
2086                                 RX_TPA_END_CMPL_AGG_BUFS_SFT;
2087                         desc++;
2088                 } else if (cmp_type == 0x11) {
2089                         desc++;
2090                         cmp = (rxcmp->agg_bufs_v1 &
2091                                    RX_PKT_CMPL_AGG_BUFS_MASK) >>
2092                                 RX_PKT_CMPL_AGG_BUFS_SFT;
2093                 } else {
2094                         cmp = 1;
2095                 }
2096 nothing_to_do:
2097                 raw_cons += cmp ? cmp : 2;
2098         }
2099
2100         return desc;
2101 }
2102
2103 static int
2104 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2105 {
2106         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2107         struct bnxt_rx_ring_info *rxr;
2108         struct bnxt_cp_ring_info *cpr;
2109         struct bnxt_sw_rx_bd *rx_buf;
2110         struct rx_pkt_cmpl *rxcmp;
2111         uint32_t cons, cp_cons;
2112         int rc;
2113
2114         if (!rxq)
2115                 return -EINVAL;
2116
2117         rc = is_bnxt_in_error(rxq->bp);
2118         if (rc)
2119                 return rc;
2120
2121         cpr = rxq->cp_ring;
2122         rxr = rxq->rx_ring;
2123
2124         if (offset >= rxq->nb_rx_desc)
2125                 return -EINVAL;
2126
2127         cons = RING_CMP(cpr->cp_ring_struct, offset);
2128         cp_cons = cpr->cp_raw_cons;
2129         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2130
2131         if (cons > cp_cons) {
2132                 if (CMPL_VALID(rxcmp, cpr->valid))
2133                         return RTE_ETH_RX_DESC_DONE;
2134         } else {
2135                 if (CMPL_VALID(rxcmp, !cpr->valid))
2136                         return RTE_ETH_RX_DESC_DONE;
2137         }
2138         rx_buf = &rxr->rx_buf_ring[cons];
2139         if (rx_buf->mbuf == NULL)
2140                 return RTE_ETH_RX_DESC_UNAVAIL;
2141
2142
2143         return RTE_ETH_RX_DESC_AVAIL;
2144 }
2145
2146 static int
2147 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2148 {
2149         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2150         struct bnxt_tx_ring_info *txr;
2151         struct bnxt_cp_ring_info *cpr;
2152         struct bnxt_sw_tx_bd *tx_buf;
2153         struct tx_pkt_cmpl *txcmp;
2154         uint32_t cons, cp_cons;
2155         int rc;
2156
2157         if (!txq)
2158                 return -EINVAL;
2159
2160         rc = is_bnxt_in_error(txq->bp);
2161         if (rc)
2162                 return rc;
2163
2164         cpr = txq->cp_ring;
2165         txr = txq->tx_ring;
2166
2167         if (offset >= txq->nb_tx_desc)
2168                 return -EINVAL;
2169
2170         cons = RING_CMP(cpr->cp_ring_struct, offset);
2171         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2172         cp_cons = cpr->cp_raw_cons;
2173
2174         if (cons > cp_cons) {
2175                 if (CMPL_VALID(txcmp, cpr->valid))
2176                         return RTE_ETH_TX_DESC_UNAVAIL;
2177         } else {
2178                 if (CMPL_VALID(txcmp, !cpr->valid))
2179                         return RTE_ETH_TX_DESC_UNAVAIL;
2180         }
2181         tx_buf = &txr->tx_buf_ring[cons];
2182         if (tx_buf->mbuf == NULL)
2183                 return RTE_ETH_TX_DESC_DONE;
2184
2185         return RTE_ETH_TX_DESC_FULL;
2186 }
2187
2188 static struct bnxt_filter_info *
2189 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2190                                 struct rte_eth_ethertype_filter *efilter,
2191                                 struct bnxt_vnic_info *vnic0,
2192                                 struct bnxt_vnic_info *vnic,
2193                                 int *ret)
2194 {
2195         struct bnxt_filter_info *mfilter = NULL;
2196         int match = 0;
2197         *ret = 0;
2198
2199         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2200                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2201                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2202                         " ethertype filter.", efilter->ether_type);
2203                 *ret = -EINVAL;
2204                 goto exit;
2205         }
2206         if (efilter->queue >= bp->rx_nr_rings) {
2207                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2208                 *ret = -EINVAL;
2209                 goto exit;
2210         }
2211
2212         vnic0 = &bp->vnic_info[0];
2213         vnic = &bp->vnic_info[efilter->queue];
2214         if (vnic == NULL) {
2215                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2216                 *ret = -EINVAL;
2217                 goto exit;
2218         }
2219
2220         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2221                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2222                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2223                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2224                              mfilter->flags ==
2225                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2226                              mfilter->ethertype == efilter->ether_type)) {
2227                                 match = 1;
2228                                 break;
2229                         }
2230                 }
2231         } else {
2232                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2233                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2234                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2235                              mfilter->ethertype == efilter->ether_type &&
2236                              mfilter->flags ==
2237                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2238                                 match = 1;
2239                                 break;
2240                         }
2241         }
2242
2243         if (match)
2244                 *ret = -EEXIST;
2245
2246 exit:
2247         return mfilter;
2248 }
2249
2250 static int
2251 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2252                         enum rte_filter_op filter_op,
2253                         void *arg)
2254 {
2255         struct bnxt *bp = dev->data->dev_private;
2256         struct rte_eth_ethertype_filter *efilter =
2257                         (struct rte_eth_ethertype_filter *)arg;
2258         struct bnxt_filter_info *bfilter, *filter1;
2259         struct bnxt_vnic_info *vnic, *vnic0;
2260         int ret;
2261
2262         if (filter_op == RTE_ETH_FILTER_NOP)
2263                 return 0;
2264
2265         if (arg == NULL) {
2266                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2267                             filter_op);
2268                 return -EINVAL;
2269         }
2270
2271         vnic0 = &bp->vnic_info[0];
2272         vnic = &bp->vnic_info[efilter->queue];
2273
2274         switch (filter_op) {
2275         case RTE_ETH_FILTER_ADD:
2276                 bnxt_match_and_validate_ether_filter(bp, efilter,
2277                                                         vnic0, vnic, &ret);
2278                 if (ret < 0)
2279                         return ret;
2280
2281                 bfilter = bnxt_get_unused_filter(bp);
2282                 if (bfilter == NULL) {
2283                         PMD_DRV_LOG(ERR,
2284                                 "Not enough resources for a new filter.\n");
2285                         return -ENOMEM;
2286                 }
2287                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2288                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2289                        RTE_ETHER_ADDR_LEN);
2290                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2291                        RTE_ETHER_ADDR_LEN);
2292                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2293                 bfilter->ethertype = efilter->ether_type;
2294                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2295
2296                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2297                 if (filter1 == NULL) {
2298                         ret = -EINVAL;
2299                         goto cleanup;
2300                 }
2301                 bfilter->enables |=
2302                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2303                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2304
2305                 bfilter->dst_id = vnic->fw_vnic_id;
2306
2307                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2308                         bfilter->flags =
2309                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2310                 }
2311
2312                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2313                 if (ret)
2314                         goto cleanup;
2315                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2316                 break;
2317         case RTE_ETH_FILTER_DELETE:
2318                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2319                                                         vnic0, vnic, &ret);
2320                 if (ret == -EEXIST) {
2321                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2322
2323                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2324                                       next);
2325                         bnxt_free_filter(bp, filter1);
2326                 } else if (ret == 0) {
2327                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2328                 }
2329                 break;
2330         default:
2331                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2332                 ret = -EINVAL;
2333                 goto error;
2334         }
2335         return ret;
2336 cleanup:
2337         bnxt_free_filter(bp, bfilter);
2338 error:
2339         return ret;
2340 }
2341
2342 static inline int
2343 parse_ntuple_filter(struct bnxt *bp,
2344                     struct rte_eth_ntuple_filter *nfilter,
2345                     struct bnxt_filter_info *bfilter)
2346 {
2347         uint32_t en = 0;
2348
2349         if (nfilter->queue >= bp->rx_nr_rings) {
2350                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2351                 return -EINVAL;
2352         }
2353
2354         switch (nfilter->dst_port_mask) {
2355         case UINT16_MAX:
2356                 bfilter->dst_port_mask = -1;
2357                 bfilter->dst_port = nfilter->dst_port;
2358                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2359                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2360                 break;
2361         default:
2362                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2363                 return -EINVAL;
2364         }
2365
2366         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2367         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2368
2369         switch (nfilter->proto_mask) {
2370         case UINT8_MAX:
2371                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2372                         bfilter->ip_protocol = 17;
2373                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2374                         bfilter->ip_protocol = 6;
2375                 else
2376                         return -EINVAL;
2377                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2378                 break;
2379         default:
2380                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2381                 return -EINVAL;
2382         }
2383
2384         switch (nfilter->dst_ip_mask) {
2385         case UINT32_MAX:
2386                 bfilter->dst_ipaddr_mask[0] = -1;
2387                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2388                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2389                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2390                 break;
2391         default:
2392                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2393                 return -EINVAL;
2394         }
2395
2396         switch (nfilter->src_ip_mask) {
2397         case UINT32_MAX:
2398                 bfilter->src_ipaddr_mask[0] = -1;
2399                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2400                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2401                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2402                 break;
2403         default:
2404                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2405                 return -EINVAL;
2406         }
2407
2408         switch (nfilter->src_port_mask) {
2409         case UINT16_MAX:
2410                 bfilter->src_port_mask = -1;
2411                 bfilter->src_port = nfilter->src_port;
2412                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2413                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2414                 break;
2415         default:
2416                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2417                 return -EINVAL;
2418         }
2419
2420         //TODO Priority
2421         //nfilter->priority = (uint8_t)filter->priority;
2422
2423         bfilter->enables = en;
2424         return 0;
2425 }
2426
2427 static struct bnxt_filter_info*
2428 bnxt_match_ntuple_filter(struct bnxt *bp,
2429                          struct bnxt_filter_info *bfilter,
2430                          struct bnxt_vnic_info **mvnic)
2431 {
2432         struct bnxt_filter_info *mfilter = NULL;
2433         int i;
2434
2435         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2436                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2437                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2438                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2439                             bfilter->src_ipaddr_mask[0] ==
2440                             mfilter->src_ipaddr_mask[0] &&
2441                             bfilter->src_port == mfilter->src_port &&
2442                             bfilter->src_port_mask == mfilter->src_port_mask &&
2443                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2444                             bfilter->dst_ipaddr_mask[0] ==
2445                             mfilter->dst_ipaddr_mask[0] &&
2446                             bfilter->dst_port == mfilter->dst_port &&
2447                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2448                             bfilter->flags == mfilter->flags &&
2449                             bfilter->enables == mfilter->enables) {
2450                                 if (mvnic)
2451                                         *mvnic = vnic;
2452                                 return mfilter;
2453                         }
2454                 }
2455         }
2456         return NULL;
2457 }
2458
2459 static int
2460 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2461                        struct rte_eth_ntuple_filter *nfilter,
2462                        enum rte_filter_op filter_op)
2463 {
2464         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2465         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2466         int ret;
2467
2468         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2469                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2470                 return -EINVAL;
2471         }
2472
2473         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2474                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2475                 return -EINVAL;
2476         }
2477
2478         bfilter = bnxt_get_unused_filter(bp);
2479         if (bfilter == NULL) {
2480                 PMD_DRV_LOG(ERR,
2481                         "Not enough resources for a new filter.\n");
2482                 return -ENOMEM;
2483         }
2484         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2485         if (ret < 0)
2486                 goto free_filter;
2487
2488         vnic = &bp->vnic_info[nfilter->queue];
2489         vnic0 = &bp->vnic_info[0];
2490         filter1 = STAILQ_FIRST(&vnic0->filter);
2491         if (filter1 == NULL) {
2492                 ret = -EINVAL;
2493                 goto free_filter;
2494         }
2495
2496         bfilter->dst_id = vnic->fw_vnic_id;
2497         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2498         bfilter->enables |=
2499                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2500         bfilter->ethertype = 0x800;
2501         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2502
2503         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2504
2505         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2506             bfilter->dst_id == mfilter->dst_id) {
2507                 PMD_DRV_LOG(ERR, "filter exists.\n");
2508                 ret = -EEXIST;
2509                 goto free_filter;
2510         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2511                    bfilter->dst_id != mfilter->dst_id) {
2512                 mfilter->dst_id = vnic->fw_vnic_id;
2513                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2514                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2515                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2516                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2517                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2518                 goto free_filter;
2519         }
2520         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2521                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2522                 ret = -ENOENT;
2523                 goto free_filter;
2524         }
2525
2526         if (filter_op == RTE_ETH_FILTER_ADD) {
2527                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2528                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2529                 if (ret)
2530                         goto free_filter;
2531                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2532         } else {
2533                 if (mfilter == NULL) {
2534                         /* This should not happen. But for Coverity! */
2535                         ret = -ENOENT;
2536                         goto free_filter;
2537                 }
2538                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2539
2540                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2541                 bnxt_free_filter(bp, mfilter);
2542                 mfilter->fw_l2_filter_id = -1;
2543                 bnxt_free_filter(bp, bfilter);
2544                 bfilter->fw_l2_filter_id = -1;
2545         }
2546
2547         return 0;
2548 free_filter:
2549         bfilter->fw_l2_filter_id = -1;
2550         bnxt_free_filter(bp, bfilter);
2551         return ret;
2552 }
2553
2554 static int
2555 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2556                         enum rte_filter_op filter_op,
2557                         void *arg)
2558 {
2559         struct bnxt *bp = dev->data->dev_private;
2560         int ret;
2561
2562         if (filter_op == RTE_ETH_FILTER_NOP)
2563                 return 0;
2564
2565         if (arg == NULL) {
2566                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2567                             filter_op);
2568                 return -EINVAL;
2569         }
2570
2571         switch (filter_op) {
2572         case RTE_ETH_FILTER_ADD:
2573                 ret = bnxt_cfg_ntuple_filter(bp,
2574                         (struct rte_eth_ntuple_filter *)arg,
2575                         filter_op);
2576                 break;
2577         case RTE_ETH_FILTER_DELETE:
2578                 ret = bnxt_cfg_ntuple_filter(bp,
2579                         (struct rte_eth_ntuple_filter *)arg,
2580                         filter_op);
2581                 break;
2582         default:
2583                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2584                 ret = -EINVAL;
2585                 break;
2586         }
2587         return ret;
2588 }
2589
2590 static int
2591 bnxt_parse_fdir_filter(struct bnxt *bp,
2592                        struct rte_eth_fdir_filter *fdir,
2593                        struct bnxt_filter_info *filter)
2594 {
2595         enum rte_fdir_mode fdir_mode =
2596                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2597         struct bnxt_vnic_info *vnic0, *vnic;
2598         struct bnxt_filter_info *filter1;
2599         uint32_t en = 0;
2600         int i;
2601
2602         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2603                 return -EINVAL;
2604
2605         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2606         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2607
2608         switch (fdir->input.flow_type) {
2609         case RTE_ETH_FLOW_IPV4:
2610         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2611                 /* FALLTHROUGH */
2612                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2613                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2614                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2615                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2616                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2617                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2618                 filter->ip_addr_type =
2619                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2620                 filter->src_ipaddr_mask[0] = 0xffffffff;
2621                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2622                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2623                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2624                 filter->ethertype = 0x800;
2625                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2626                 break;
2627         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2628                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2629                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2630                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2631                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2632                 filter->dst_port_mask = 0xffff;
2633                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2634                 filter->src_port_mask = 0xffff;
2635                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2636                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2637                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2638                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2639                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2640                 filter->ip_protocol = 6;
2641                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2642                 filter->ip_addr_type =
2643                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2644                 filter->src_ipaddr_mask[0] = 0xffffffff;
2645                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2646                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2647                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2648                 filter->ethertype = 0x800;
2649                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2650                 break;
2651         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2652                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2653                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2654                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2655                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2656                 filter->dst_port_mask = 0xffff;
2657                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2658                 filter->src_port_mask = 0xffff;
2659                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2660                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2661                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2662                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2663                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2664                 filter->ip_protocol = 17;
2665                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2666                 filter->ip_addr_type =
2667                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2668                 filter->src_ipaddr_mask[0] = 0xffffffff;
2669                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2670                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2671                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2672                 filter->ethertype = 0x800;
2673                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2674                 break;
2675         case RTE_ETH_FLOW_IPV6:
2676         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2677                 /* FALLTHROUGH */
2678                 filter->ip_addr_type =
2679                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2680                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2681                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2682                 rte_memcpy(filter->src_ipaddr,
2683                            fdir->input.flow.ipv6_flow.src_ip, 16);
2684                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2685                 rte_memcpy(filter->dst_ipaddr,
2686                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2687                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2688                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2689                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2690                 memset(filter->src_ipaddr_mask, 0xff, 16);
2691                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2692                 filter->ethertype = 0x86dd;
2693                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2694                 break;
2695         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2696                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2697                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2698                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2699                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2700                 filter->dst_port_mask = 0xffff;
2701                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2702                 filter->src_port_mask = 0xffff;
2703                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2704                 filter->ip_addr_type =
2705                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2706                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2707                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2708                 rte_memcpy(filter->src_ipaddr,
2709                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2710                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2711                 rte_memcpy(filter->dst_ipaddr,
2712                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2713                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2714                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2715                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2716                 memset(filter->src_ipaddr_mask, 0xff, 16);
2717                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2718                 filter->ethertype = 0x86dd;
2719                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2720                 break;
2721         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2722                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2723                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2724                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2725                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2726                 filter->dst_port_mask = 0xffff;
2727                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2728                 filter->src_port_mask = 0xffff;
2729                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2730                 filter->ip_addr_type =
2731                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2732                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2733                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2734                 rte_memcpy(filter->src_ipaddr,
2735                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2736                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2737                 rte_memcpy(filter->dst_ipaddr,
2738                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2739                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2740                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2741                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2742                 memset(filter->src_ipaddr_mask, 0xff, 16);
2743                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2744                 filter->ethertype = 0x86dd;
2745                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2746                 break;
2747         case RTE_ETH_FLOW_L2_PAYLOAD:
2748                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2749                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2750                 break;
2751         case RTE_ETH_FLOW_VXLAN:
2752                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2753                         return -EINVAL;
2754                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2755                 filter->tunnel_type =
2756                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2757                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2758                 break;
2759         case RTE_ETH_FLOW_NVGRE:
2760                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2761                         return -EINVAL;
2762                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2763                 filter->tunnel_type =
2764                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2765                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2766                 break;
2767         case RTE_ETH_FLOW_UNKNOWN:
2768         case RTE_ETH_FLOW_RAW:
2769         case RTE_ETH_FLOW_FRAG_IPV4:
2770         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2771         case RTE_ETH_FLOW_FRAG_IPV6:
2772         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2773         case RTE_ETH_FLOW_IPV6_EX:
2774         case RTE_ETH_FLOW_IPV6_TCP_EX:
2775         case RTE_ETH_FLOW_IPV6_UDP_EX:
2776         case RTE_ETH_FLOW_GENEVE:
2777                 /* FALLTHROUGH */
2778         default:
2779                 return -EINVAL;
2780         }
2781
2782         vnic0 = &bp->vnic_info[0];
2783         vnic = &bp->vnic_info[fdir->action.rx_queue];
2784         if (vnic == NULL) {
2785                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2786                 return -EINVAL;
2787         }
2788
2789
2790         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2791                 rte_memcpy(filter->dst_macaddr,
2792                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2793                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2794         }
2795
2796         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2797                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2798                 filter1 = STAILQ_FIRST(&vnic0->filter);
2799                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2800         } else {
2801                 filter->dst_id = vnic->fw_vnic_id;
2802                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2803                         if (filter->dst_macaddr[i] == 0x00)
2804                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2805                         else
2806                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2807         }
2808
2809         if (filter1 == NULL)
2810                 return -EINVAL;
2811
2812         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2813         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2814
2815         filter->enables = en;
2816
2817         return 0;
2818 }
2819
2820 static struct bnxt_filter_info *
2821 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2822                 struct bnxt_vnic_info **mvnic)
2823 {
2824         struct bnxt_filter_info *mf = NULL;
2825         int i;
2826
2827         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2828                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2829
2830                 STAILQ_FOREACH(mf, &vnic->filter, next) {
2831                         if (mf->filter_type == nf->filter_type &&
2832                             mf->flags == nf->flags &&
2833                             mf->src_port == nf->src_port &&
2834                             mf->src_port_mask == nf->src_port_mask &&
2835                             mf->dst_port == nf->dst_port &&
2836                             mf->dst_port_mask == nf->dst_port_mask &&
2837                             mf->ip_protocol == nf->ip_protocol &&
2838                             mf->ip_addr_type == nf->ip_addr_type &&
2839                             mf->ethertype == nf->ethertype &&
2840                             mf->vni == nf->vni &&
2841                             mf->tunnel_type == nf->tunnel_type &&
2842                             mf->l2_ovlan == nf->l2_ovlan &&
2843                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2844                             mf->l2_ivlan == nf->l2_ivlan &&
2845                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2846                             !memcmp(mf->l2_addr, nf->l2_addr,
2847                                     RTE_ETHER_ADDR_LEN) &&
2848                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2849                                     RTE_ETHER_ADDR_LEN) &&
2850                             !memcmp(mf->src_macaddr, nf->src_macaddr,
2851                                     RTE_ETHER_ADDR_LEN) &&
2852                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2853                                     RTE_ETHER_ADDR_LEN) &&
2854                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2855                                     sizeof(nf->src_ipaddr)) &&
2856                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2857                                     sizeof(nf->src_ipaddr_mask)) &&
2858                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2859                                     sizeof(nf->dst_ipaddr)) &&
2860                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2861                                     sizeof(nf->dst_ipaddr_mask))) {
2862                                 if (mvnic)
2863                                         *mvnic = vnic;
2864                                 return mf;
2865                         }
2866                 }
2867         }
2868         return NULL;
2869 }
2870
2871 static int
2872 bnxt_fdir_filter(struct rte_eth_dev *dev,
2873                  enum rte_filter_op filter_op,
2874                  void *arg)
2875 {
2876         struct bnxt *bp = dev->data->dev_private;
2877         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
2878         struct bnxt_filter_info *filter, *match;
2879         struct bnxt_vnic_info *vnic, *mvnic;
2880         int ret = 0, i;
2881
2882         if (filter_op == RTE_ETH_FILTER_NOP)
2883                 return 0;
2884
2885         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2886                 return -EINVAL;
2887
2888         switch (filter_op) {
2889         case RTE_ETH_FILTER_ADD:
2890         case RTE_ETH_FILTER_DELETE:
2891                 /* FALLTHROUGH */
2892                 filter = bnxt_get_unused_filter(bp);
2893                 if (filter == NULL) {
2894                         PMD_DRV_LOG(ERR,
2895                                 "Not enough resources for a new flow.\n");
2896                         return -ENOMEM;
2897                 }
2898
2899                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2900                 if (ret != 0)
2901                         goto free_filter;
2902                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2903
2904                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2905                         vnic = &bp->vnic_info[0];
2906                 else
2907                         vnic = &bp->vnic_info[fdir->action.rx_queue];
2908
2909                 match = bnxt_match_fdir(bp, filter, &mvnic);
2910                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2911                         if (match->dst_id == vnic->fw_vnic_id) {
2912                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2913                                 ret = -EEXIST;
2914                                 goto free_filter;
2915                         } else {
2916                                 match->dst_id = vnic->fw_vnic_id;
2917                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
2918                                                                   match->dst_id,
2919                                                                   match);
2920                                 STAILQ_REMOVE(&mvnic->filter, match,
2921                                               bnxt_filter_info, next);
2922                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2923                                 PMD_DRV_LOG(ERR,
2924                                         "Filter with matching pattern exist\n");
2925                                 PMD_DRV_LOG(ERR,
2926                                         "Updated it to new destination q\n");
2927                                 goto free_filter;
2928                         }
2929                 }
2930                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2931                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2932                         ret = -ENOENT;
2933                         goto free_filter;
2934                 }
2935
2936                 if (filter_op == RTE_ETH_FILTER_ADD) {
2937                         ret = bnxt_hwrm_set_ntuple_filter(bp,
2938                                                           filter->dst_id,
2939                                                           filter);
2940                         if (ret)
2941                                 goto free_filter;
2942                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2943                 } else {
2944                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2945                         STAILQ_REMOVE(&vnic->filter, match,
2946                                       bnxt_filter_info, next);
2947                         bnxt_free_filter(bp, match);
2948                         filter->fw_l2_filter_id = -1;
2949                         bnxt_free_filter(bp, filter);
2950                 }
2951                 break;
2952         case RTE_ETH_FILTER_FLUSH:
2953                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2954                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2955
2956                         STAILQ_FOREACH(filter, &vnic->filter, next) {
2957                                 if (filter->filter_type ==
2958                                     HWRM_CFA_NTUPLE_FILTER) {
2959                                         ret =
2960                                         bnxt_hwrm_clear_ntuple_filter(bp,
2961                                                                       filter);
2962                                         STAILQ_REMOVE(&vnic->filter, filter,
2963                                                       bnxt_filter_info, next);
2964                                 }
2965                         }
2966                 }
2967                 return ret;
2968         case RTE_ETH_FILTER_UPDATE:
2969         case RTE_ETH_FILTER_STATS:
2970         case RTE_ETH_FILTER_INFO:
2971                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2972                 break;
2973         default:
2974                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2975                 ret = -EINVAL;
2976                 break;
2977         }
2978         return ret;
2979
2980 free_filter:
2981         filter->fw_l2_filter_id = -1;
2982         bnxt_free_filter(bp, filter);
2983         return ret;
2984 }
2985
2986 static int
2987 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2988                     enum rte_filter_type filter_type,
2989                     enum rte_filter_op filter_op, void *arg)
2990 {
2991         int ret = 0;
2992
2993         ret = is_bnxt_in_error(dev->data->dev_private);
2994         if (ret)
2995                 return ret;
2996
2997         switch (filter_type) {
2998         case RTE_ETH_FILTER_TUNNEL:
2999                 PMD_DRV_LOG(ERR,
3000                         "filter type: %d: To be implemented\n", filter_type);
3001                 break;
3002         case RTE_ETH_FILTER_FDIR:
3003                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3004                 break;
3005         case RTE_ETH_FILTER_NTUPLE:
3006                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3007                 break;
3008         case RTE_ETH_FILTER_ETHERTYPE:
3009                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3010                 break;
3011         case RTE_ETH_FILTER_GENERIC:
3012                 if (filter_op != RTE_ETH_FILTER_GET)
3013                         return -EINVAL;
3014                 *(const void **)arg = &bnxt_flow_ops;
3015                 break;
3016         default:
3017                 PMD_DRV_LOG(ERR,
3018                         "Filter type (%d) not supported", filter_type);
3019                 ret = -EINVAL;
3020                 break;
3021         }
3022         return ret;
3023 }
3024
3025 static const uint32_t *
3026 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3027 {
3028         static const uint32_t ptypes[] = {
3029                 RTE_PTYPE_L2_ETHER_VLAN,
3030                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3031                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3032                 RTE_PTYPE_L4_ICMP,
3033                 RTE_PTYPE_L4_TCP,
3034                 RTE_PTYPE_L4_UDP,
3035                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3036                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3037                 RTE_PTYPE_INNER_L4_ICMP,
3038                 RTE_PTYPE_INNER_L4_TCP,
3039                 RTE_PTYPE_INNER_L4_UDP,
3040                 RTE_PTYPE_UNKNOWN
3041         };
3042
3043         if (!dev->rx_pkt_burst)
3044                 return NULL;
3045
3046         return ptypes;
3047 }
3048
3049 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3050                          int reg_win)
3051 {
3052         uint32_t reg_base = *reg_arr & 0xfffff000;
3053         uint32_t win_off;
3054         int i;
3055
3056         for (i = 0; i < count; i++) {
3057                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3058                         return -ERANGE;
3059         }
3060         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3061         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3062         return 0;
3063 }
3064
3065 static int bnxt_map_ptp_regs(struct bnxt *bp)
3066 {
3067         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3068         uint32_t *reg_arr;
3069         int rc, i;
3070
3071         reg_arr = ptp->rx_regs;
3072         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3073         if (rc)
3074                 return rc;
3075
3076         reg_arr = ptp->tx_regs;
3077         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3078         if (rc)
3079                 return rc;
3080
3081         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3082                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3083
3084         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3085                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3086
3087         return 0;
3088 }
3089
3090 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3091 {
3092         rte_write32(0, (uint8_t *)bp->bar0 +
3093                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3094         rte_write32(0, (uint8_t *)bp->bar0 +
3095                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3096 }
3097
3098 static uint64_t bnxt_cc_read(struct bnxt *bp)
3099 {
3100         uint64_t ns;
3101
3102         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3103                               BNXT_GRCPF_REG_SYNC_TIME));
3104         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3105                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3106         return ns;
3107 }
3108
3109 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3110 {
3111         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3112         uint32_t fifo;
3113
3114         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3115                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3116         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3117                 return -EAGAIN;
3118
3119         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3120                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3121         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3122                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3123         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3124                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3125
3126         return 0;
3127 }
3128
3129 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3130 {
3131         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3132         struct bnxt_pf_info *pf = &bp->pf;
3133         uint16_t port_id;
3134         uint32_t fifo;
3135
3136         if (!ptp)
3137                 return -ENODEV;
3138
3139         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3140                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3141         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3142                 return -EAGAIN;
3143
3144         port_id = pf->port_id;
3145         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3146                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3147
3148         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3149                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3150         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3151 /*              bnxt_clr_rx_ts(bp);       TBD  */
3152                 return -EBUSY;
3153         }
3154
3155         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3156                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3157         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3158                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3159
3160         return 0;
3161 }
3162
3163 static int
3164 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3165 {
3166         uint64_t ns;
3167         struct bnxt *bp = dev->data->dev_private;
3168         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3169
3170         if (!ptp)
3171                 return 0;
3172
3173         ns = rte_timespec_to_ns(ts);
3174         /* Set the timecounters to a new value. */
3175         ptp->tc.nsec = ns;
3176
3177         return 0;
3178 }
3179
3180 static int
3181 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3182 {
3183         uint64_t ns, systime_cycles;
3184         struct bnxt *bp = dev->data->dev_private;
3185         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3186
3187         if (!ptp)
3188                 return 0;
3189
3190         systime_cycles = bnxt_cc_read(bp);
3191         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3192         *ts = rte_ns_to_timespec(ns);
3193
3194         return 0;
3195 }
3196 static int
3197 bnxt_timesync_enable(struct rte_eth_dev *dev)
3198 {
3199         struct bnxt *bp = dev->data->dev_private;
3200         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3201         uint32_t shift = 0;
3202
3203         if (!ptp)
3204                 return 0;
3205
3206         ptp->rx_filter = 1;
3207         ptp->tx_tstamp_en = 1;
3208         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3209
3210         if (!bnxt_hwrm_ptp_cfg(bp))
3211                 bnxt_map_ptp_regs(bp);
3212
3213         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3214         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3215         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3216
3217         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3218         ptp->tc.cc_shift = shift;
3219         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3220
3221         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3222         ptp->rx_tstamp_tc.cc_shift = shift;
3223         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3224
3225         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3226         ptp->tx_tstamp_tc.cc_shift = shift;
3227         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3228
3229         return 0;
3230 }
3231
3232 static int
3233 bnxt_timesync_disable(struct rte_eth_dev *dev)
3234 {
3235         struct bnxt *bp = dev->data->dev_private;
3236         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3237
3238         if (!ptp)
3239                 return 0;
3240
3241         ptp->rx_filter = 0;
3242         ptp->tx_tstamp_en = 0;
3243         ptp->rxctl = 0;
3244
3245         bnxt_hwrm_ptp_cfg(bp);
3246
3247         bnxt_unmap_ptp_regs(bp);
3248
3249         return 0;
3250 }
3251
3252 static int
3253 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3254                                  struct timespec *timestamp,
3255                                  uint32_t flags __rte_unused)
3256 {
3257         struct bnxt *bp = dev->data->dev_private;
3258         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3259         uint64_t rx_tstamp_cycles = 0;
3260         uint64_t ns;
3261
3262         if (!ptp)
3263                 return 0;
3264
3265         bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3266         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3267         *timestamp = rte_ns_to_timespec(ns);
3268         return  0;
3269 }
3270
3271 static int
3272 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3273                                  struct timespec *timestamp)
3274 {
3275         struct bnxt *bp = dev->data->dev_private;
3276         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3277         uint64_t tx_tstamp_cycles = 0;
3278         uint64_t ns;
3279
3280         if (!ptp)
3281                 return 0;
3282
3283         bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3284         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3285         *timestamp = rte_ns_to_timespec(ns);
3286
3287         return 0;
3288 }
3289
3290 static int
3291 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3292 {
3293         struct bnxt *bp = dev->data->dev_private;
3294         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3295
3296         if (!ptp)
3297                 return 0;
3298
3299         ptp->tc.nsec += delta;
3300
3301         return 0;
3302 }
3303
3304 static int
3305 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3306 {
3307         struct bnxt *bp = dev->data->dev_private;
3308         int rc;
3309         uint32_t dir_entries;
3310         uint32_t entry_length;
3311
3312         rc = is_bnxt_in_error(bp);
3313         if (rc)
3314                 return rc;
3315
3316         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3317                 bp->pdev->addr.domain, bp->pdev->addr.bus,
3318                 bp->pdev->addr.devid, bp->pdev->addr.function);
3319
3320         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3321         if (rc != 0)
3322                 return rc;
3323
3324         return dir_entries * entry_length;
3325 }
3326
3327 static int
3328 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3329                 struct rte_dev_eeprom_info *in_eeprom)
3330 {
3331         struct bnxt *bp = dev->data->dev_private;
3332         uint32_t index;
3333         uint32_t offset;
3334         int rc;
3335
3336         rc = is_bnxt_in_error(bp);
3337         if (rc)
3338                 return rc;
3339
3340         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3341                 "len = %d\n", bp->pdev->addr.domain,
3342                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3343                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3344
3345         if (in_eeprom->offset == 0) /* special offset value to get directory */
3346                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3347                                                 in_eeprom->data);
3348
3349         index = in_eeprom->offset >> 24;
3350         offset = in_eeprom->offset & 0xffffff;
3351
3352         if (index != 0)
3353                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3354                                            in_eeprom->length, in_eeprom->data);
3355
3356         return 0;
3357 }
3358
3359 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3360 {
3361         switch (dir_type) {
3362         case BNX_DIR_TYPE_CHIMP_PATCH:
3363         case BNX_DIR_TYPE_BOOTCODE:
3364         case BNX_DIR_TYPE_BOOTCODE_2:
3365         case BNX_DIR_TYPE_APE_FW:
3366         case BNX_DIR_TYPE_APE_PATCH:
3367         case BNX_DIR_TYPE_KONG_FW:
3368         case BNX_DIR_TYPE_KONG_PATCH:
3369         case BNX_DIR_TYPE_BONO_FW:
3370         case BNX_DIR_TYPE_BONO_PATCH:
3371                 /* FALLTHROUGH */
3372                 return true;
3373         }
3374
3375         return false;
3376 }
3377
3378 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3379 {
3380         switch (dir_type) {
3381         case BNX_DIR_TYPE_AVS:
3382         case BNX_DIR_TYPE_EXP_ROM_MBA:
3383         case BNX_DIR_TYPE_PCIE:
3384         case BNX_DIR_TYPE_TSCF_UCODE:
3385         case BNX_DIR_TYPE_EXT_PHY:
3386         case BNX_DIR_TYPE_CCM:
3387         case BNX_DIR_TYPE_ISCSI_BOOT:
3388         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3389         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3390                 /* FALLTHROUGH */
3391                 return true;
3392         }
3393
3394         return false;
3395 }
3396
3397 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3398 {
3399         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3400                 bnxt_dir_type_is_other_exec_format(dir_type);
3401 }
3402
3403 static int
3404 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3405                 struct rte_dev_eeprom_info *in_eeprom)
3406 {
3407         struct bnxt *bp = dev->data->dev_private;
3408         uint8_t index, dir_op;
3409         uint16_t type, ext, ordinal, attr;
3410         int rc;
3411
3412         rc = is_bnxt_in_error(bp);
3413         if (rc)
3414                 return rc;
3415
3416         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3417                 "len = %d\n", bp->pdev->addr.domain,
3418                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3419                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3420
3421         if (!BNXT_PF(bp)) {
3422                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3423                 return -EINVAL;
3424         }
3425
3426         type = in_eeprom->magic >> 16;
3427
3428         if (type == 0xffff) { /* special value for directory operations */
3429                 index = in_eeprom->magic & 0xff;
3430                 dir_op = in_eeprom->magic >> 8;
3431                 if (index == 0)
3432                         return -EINVAL;
3433                 switch (dir_op) {
3434                 case 0x0e: /* erase */
3435                         if (in_eeprom->offset != ~in_eeprom->magic)
3436                                 return -EINVAL;
3437                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3438                 default:
3439                         return -EINVAL;
3440                 }
3441         }
3442
3443         /* Create or re-write an NVM item: */
3444         if (bnxt_dir_type_is_executable(type) == true)
3445                 return -EOPNOTSUPP;
3446         ext = in_eeprom->magic & 0xffff;
3447         ordinal = in_eeprom->offset >> 16;
3448         attr = in_eeprom->offset & 0xffff;
3449
3450         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3451                                      in_eeprom->data, in_eeprom->length);
3452 }
3453
3454 /*
3455  * Initialization
3456  */
3457
3458 static const struct eth_dev_ops bnxt_dev_ops = {
3459         .dev_infos_get = bnxt_dev_info_get_op,
3460         .dev_close = bnxt_dev_close_op,
3461         .dev_configure = bnxt_dev_configure_op,
3462         .dev_start = bnxt_dev_start_op,
3463         .dev_stop = bnxt_dev_stop_op,
3464         .dev_set_link_up = bnxt_dev_set_link_up_op,
3465         .dev_set_link_down = bnxt_dev_set_link_down_op,
3466         .stats_get = bnxt_stats_get_op,
3467         .stats_reset = bnxt_stats_reset_op,
3468         .rx_queue_setup = bnxt_rx_queue_setup_op,
3469         .rx_queue_release = bnxt_rx_queue_release_op,
3470         .tx_queue_setup = bnxt_tx_queue_setup_op,
3471         .tx_queue_release = bnxt_tx_queue_release_op,
3472         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3473         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3474         .reta_update = bnxt_reta_update_op,
3475         .reta_query = bnxt_reta_query_op,
3476         .rss_hash_update = bnxt_rss_hash_update_op,
3477         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3478         .link_update = bnxt_link_update_op,
3479         .promiscuous_enable = bnxt_promiscuous_enable_op,
3480         .promiscuous_disable = bnxt_promiscuous_disable_op,
3481         .allmulticast_enable = bnxt_allmulticast_enable_op,
3482         .allmulticast_disable = bnxt_allmulticast_disable_op,
3483         .mac_addr_add = bnxt_mac_addr_add_op,
3484         .mac_addr_remove = bnxt_mac_addr_remove_op,
3485         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3486         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3487         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3488         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3489         .vlan_filter_set = bnxt_vlan_filter_set_op,
3490         .vlan_offload_set = bnxt_vlan_offload_set_op,
3491         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3492         .mtu_set = bnxt_mtu_set_op,
3493         .mac_addr_set = bnxt_set_default_mac_addr_op,
3494         .xstats_get = bnxt_dev_xstats_get_op,
3495         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3496         .xstats_reset = bnxt_dev_xstats_reset_op,
3497         .fw_version_get = bnxt_fw_version_get,
3498         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3499         .rxq_info_get = bnxt_rxq_info_get_op,
3500         .txq_info_get = bnxt_txq_info_get_op,
3501         .dev_led_on = bnxt_dev_led_on_op,
3502         .dev_led_off = bnxt_dev_led_off_op,
3503         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3504         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3505         .rx_queue_count = bnxt_rx_queue_count_op,
3506         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3507         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3508         .rx_queue_start = bnxt_rx_queue_start,
3509         .rx_queue_stop = bnxt_rx_queue_stop,
3510         .tx_queue_start = bnxt_tx_queue_start,
3511         .tx_queue_stop = bnxt_tx_queue_stop,
3512         .filter_ctrl = bnxt_filter_ctrl_op,
3513         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3514         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3515         .get_eeprom           = bnxt_get_eeprom_op,
3516         .set_eeprom           = bnxt_set_eeprom_op,
3517         .timesync_enable      = bnxt_timesync_enable,
3518         .timesync_disable     = bnxt_timesync_disable,
3519         .timesync_read_time   = bnxt_timesync_read_time,
3520         .timesync_write_time   = bnxt_timesync_write_time,
3521         .timesync_adjust_time = bnxt_timesync_adjust_time,
3522         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3523         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3524 };
3525
3526 static bool bnxt_vf_pciid(uint16_t id)
3527 {
3528         if (id == BROADCOM_DEV_ID_57304_VF ||
3529             id == BROADCOM_DEV_ID_57406_VF ||
3530             id == BROADCOM_DEV_ID_5731X_VF ||
3531             id == BROADCOM_DEV_ID_5741X_VF ||
3532             id == BROADCOM_DEV_ID_57414_VF ||
3533             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3534             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3535             id == BROADCOM_DEV_ID_58802_VF ||
3536             id == BROADCOM_DEV_ID_57500_VF1 ||
3537             id == BROADCOM_DEV_ID_57500_VF2)
3538                 return true;
3539         return false;
3540 }
3541
3542 bool bnxt_stratus_device(struct bnxt *bp)
3543 {
3544         uint16_t id = bp->pdev->id.device_id;
3545
3546         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3547             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3548             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3549                 return true;
3550         return false;
3551 }
3552
3553 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3554 {
3555         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3556         struct bnxt *bp = eth_dev->data->dev_private;
3557
3558         /* enable device (incl. PCI PM wakeup), and bus-mastering */
3559         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3560         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3561         if (!bp->bar0 || !bp->doorbell_base) {
3562                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
3563                 return -ENODEV;
3564         }
3565
3566         bp->eth_dev = eth_dev;
3567         bp->pdev = pci_dev;
3568
3569         return 0;
3570 }
3571
3572 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
3573                                   struct bnxt_ctx_pg_info *ctx_pg,
3574                                   uint32_t mem_size,
3575                                   const char *suffix,
3576                                   uint16_t idx)
3577 {
3578         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
3579         const struct rte_memzone *mz = NULL;
3580         char mz_name[RTE_MEMZONE_NAMESIZE];
3581         rte_iova_t mz_phys_addr;
3582         uint64_t valid_bits = 0;
3583         uint32_t sz;
3584         int i;
3585
3586         if (!mem_size)
3587                 return 0;
3588
3589         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
3590                          BNXT_PAGE_SIZE;
3591         rmem->page_size = BNXT_PAGE_SIZE;
3592         rmem->pg_arr = ctx_pg->ctx_pg_arr;
3593         rmem->dma_arr = ctx_pg->ctx_dma_arr;
3594         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
3595
3596         valid_bits = PTU_PTE_VALID;
3597
3598         if (rmem->nr_pages > 1) {
3599                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3600                          "bnxt_ctx_pg_tbl%s_%x_%d",
3601                          suffix, idx, bp->eth_dev->data->port_id);
3602                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3603                 mz = rte_memzone_lookup(mz_name);
3604                 if (!mz) {
3605                         mz = rte_memzone_reserve_aligned(mz_name,
3606                                                 rmem->nr_pages * 8,
3607                                                 SOCKET_ID_ANY,
3608                                                 RTE_MEMZONE_2MB |
3609                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
3610                                                 RTE_MEMZONE_IOVA_CONTIG,
3611                                                 BNXT_PAGE_SIZE);
3612                         if (mz == NULL)
3613                                 return -ENOMEM;
3614                 }
3615
3616                 memset(mz->addr, 0, mz->len);
3617                 mz_phys_addr = mz->iova;
3618                 if ((unsigned long)mz->addr == mz_phys_addr) {
3619                         PMD_DRV_LOG(WARNING,
3620                                 "Memzone physical address same as virtual.\n");
3621                         PMD_DRV_LOG(WARNING,
3622                                     "Using rte_mem_virt2iova()\n");
3623                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3624                         if (mz_phys_addr == RTE_BAD_IOVA) {
3625                                 PMD_DRV_LOG(ERR,
3626                                         "unable to map addr to phys memory\n");
3627                                 return -ENOMEM;
3628                         }
3629                 }
3630                 rte_mem_lock_page(((char *)mz->addr));
3631
3632                 rmem->pg_tbl = mz->addr;
3633                 rmem->pg_tbl_map = mz_phys_addr;
3634                 rmem->pg_tbl_mz = mz;
3635         }
3636
3637         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
3638                  suffix, idx, bp->eth_dev->data->port_id);
3639         mz = rte_memzone_lookup(mz_name);
3640         if (!mz) {
3641                 mz = rte_memzone_reserve_aligned(mz_name,
3642                                                  mem_size,
3643                                                  SOCKET_ID_ANY,
3644                                                  RTE_MEMZONE_1GB |
3645                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
3646                                                  RTE_MEMZONE_IOVA_CONTIG,
3647                                                  BNXT_PAGE_SIZE);
3648                 if (mz == NULL)
3649                         return -ENOMEM;
3650         }
3651
3652         memset(mz->addr, 0, mz->len);
3653         mz_phys_addr = mz->iova;
3654         if ((unsigned long)mz->addr == mz_phys_addr) {
3655                 PMD_DRV_LOG(WARNING,
3656                             "Memzone physical address same as virtual.\n");
3657                 PMD_DRV_LOG(WARNING,
3658                             "Using rte_mem_virt2iova()\n");
3659                 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
3660                         rte_mem_lock_page(((char *)mz->addr) + sz);
3661                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3662                 if (mz_phys_addr == RTE_BAD_IOVA) {
3663                         PMD_DRV_LOG(ERR,
3664                                     "unable to map addr to phys memory\n");
3665                         return -ENOMEM;
3666                 }
3667         }
3668
3669         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
3670                 rte_mem_lock_page(((char *)mz->addr) + sz);
3671                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
3672                 rmem->dma_arr[i] = mz_phys_addr + sz;
3673
3674                 if (rmem->nr_pages > 1) {
3675                         if (i == rmem->nr_pages - 2 &&
3676                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3677                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
3678                         else if (i == rmem->nr_pages - 1 &&
3679                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3680                                 valid_bits |= PTU_PTE_LAST;
3681
3682                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
3683                                                            valid_bits);
3684                 }
3685         }
3686
3687         rmem->mz = mz;
3688         if (rmem->vmem_size)
3689                 rmem->vmem = (void **)mz->addr;
3690         rmem->dma_arr[0] = mz_phys_addr;
3691         return 0;
3692 }
3693
3694 static void bnxt_free_ctx_mem(struct bnxt *bp)
3695 {
3696         int i;
3697
3698         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
3699                 return;
3700
3701         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
3702         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
3703         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
3704         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
3705         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
3706         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
3707         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
3708         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
3709         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
3710         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
3711         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
3712
3713         for (i = 0; i < BNXT_MAX_Q; i++) {
3714                 if (bp->ctx->tqm_mem[i])
3715                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
3716         }
3717
3718         rte_free(bp->ctx);
3719         bp->ctx = NULL;
3720 }
3721
3722 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
3723
3724 #define min_t(type, x, y) ({                    \
3725         type __min1 = (x);                      \
3726         type __min2 = (y);                      \
3727         __min1 < __min2 ? __min1 : __min2; })
3728
3729 #define max_t(type, x, y) ({                    \
3730         type __max1 = (x);                      \
3731         type __max2 = (y);                      \
3732         __max1 > __max2 ? __max1 : __max2; })
3733
3734 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
3735
3736 int bnxt_alloc_ctx_mem(struct bnxt *bp)
3737 {
3738         struct bnxt_ctx_pg_info *ctx_pg;
3739         struct bnxt_ctx_mem_info *ctx;
3740         uint32_t mem_size, ena, entries;
3741         int i, rc;
3742
3743         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
3744         if (rc) {
3745                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
3746                 return rc;
3747         }
3748         ctx = bp->ctx;
3749         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
3750                 return 0;
3751
3752         ctx_pg = &ctx->qp_mem;
3753         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
3754         mem_size = ctx->qp_entry_size * ctx_pg->entries;
3755         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
3756         if (rc)
3757                 return rc;
3758
3759         ctx_pg = &ctx->srq_mem;
3760         ctx_pg->entries = ctx->srq_max_l2_entries;
3761         mem_size = ctx->srq_entry_size * ctx_pg->entries;
3762         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
3763         if (rc)
3764                 return rc;
3765
3766         ctx_pg = &ctx->cq_mem;
3767         ctx_pg->entries = ctx->cq_max_l2_entries;
3768         mem_size = ctx->cq_entry_size * ctx_pg->entries;
3769         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
3770         if (rc)
3771                 return rc;
3772
3773         ctx_pg = &ctx->vnic_mem;
3774         ctx_pg->entries = ctx->vnic_max_vnic_entries +
3775                 ctx->vnic_max_ring_table_entries;
3776         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
3777         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
3778         if (rc)
3779                 return rc;
3780
3781         ctx_pg = &ctx->stat_mem;
3782         ctx_pg->entries = ctx->stat_max_entries;
3783         mem_size = ctx->stat_entry_size * ctx_pg->entries;
3784         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
3785         if (rc)
3786                 return rc;
3787
3788         entries = ctx->qp_max_l2_entries;
3789         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
3790         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
3791                           ctx->tqm_max_entries_per_ring);
3792         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
3793                 ctx_pg = ctx->tqm_mem[i];
3794                 /* use min tqm entries for now. */
3795                 ctx_pg->entries = entries;
3796                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
3797                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
3798                 if (rc)
3799                         return rc;
3800                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
3801         }
3802
3803         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
3804         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
3805         if (rc)
3806                 PMD_DRV_LOG(ERR,
3807                             "Failed to configure context mem: rc = %d\n", rc);
3808         else
3809                 ctx->flags |= BNXT_CTX_FLAG_INITED;
3810
3811         return rc;
3812 }
3813
3814 static int bnxt_alloc_stats_mem(struct bnxt *bp)
3815 {
3816         struct rte_pci_device *pci_dev = bp->pdev;
3817         char mz_name[RTE_MEMZONE_NAMESIZE];
3818         const struct rte_memzone *mz = NULL;
3819         uint32_t total_alloc_len;
3820         rte_iova_t mz_phys_addr;
3821
3822         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
3823                 return 0;
3824
3825         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3826                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
3827                  pci_dev->addr.bus, pci_dev->addr.devid,
3828                  pci_dev->addr.function, "rx_port_stats");
3829         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3830         mz = rte_memzone_lookup(mz_name);
3831         total_alloc_len =
3832                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
3833                                        sizeof(struct rx_port_stats_ext) + 512);
3834         if (!mz) {
3835                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
3836                                          SOCKET_ID_ANY,
3837                                          RTE_MEMZONE_2MB |
3838                                          RTE_MEMZONE_SIZE_HINT_ONLY |
3839                                          RTE_MEMZONE_IOVA_CONTIG);
3840                 if (mz == NULL)
3841                         return -ENOMEM;
3842         }
3843         memset(mz->addr, 0, mz->len);
3844         mz_phys_addr = mz->iova;
3845         if ((unsigned long)mz->addr == mz_phys_addr) {
3846                 PMD_DRV_LOG(WARNING,
3847                             "Memzone physical address same as virtual.\n");
3848                 PMD_DRV_LOG(WARNING,
3849                             "Using rte_mem_virt2iova()\n");
3850                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3851                 if (mz_phys_addr == RTE_BAD_IOVA) {
3852                         PMD_DRV_LOG(ERR,
3853                                     "Can't map address to physical memory\n");
3854                         return -ENOMEM;
3855                 }
3856         }
3857
3858         bp->rx_mem_zone = (const void *)mz;
3859         bp->hw_rx_port_stats = mz->addr;
3860         bp->hw_rx_port_stats_map = mz_phys_addr;
3861
3862         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3863                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
3864                  pci_dev->addr.bus, pci_dev->addr.devid,
3865                  pci_dev->addr.function, "tx_port_stats");
3866         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3867         mz = rte_memzone_lookup(mz_name);
3868         total_alloc_len =
3869                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
3870                                        sizeof(struct tx_port_stats_ext) + 512);
3871         if (!mz) {
3872                 mz = rte_memzone_reserve(mz_name,
3873                                          total_alloc_len,
3874                                          SOCKET_ID_ANY,
3875                                          RTE_MEMZONE_2MB |
3876                                          RTE_MEMZONE_SIZE_HINT_ONLY |
3877                                          RTE_MEMZONE_IOVA_CONTIG);
3878                 if (mz == NULL)
3879                         return -ENOMEM;
3880         }
3881         memset(mz->addr, 0, mz->len);
3882         mz_phys_addr = mz->iova;
3883         if ((unsigned long)mz->addr == mz_phys_addr) {
3884                 PMD_DRV_LOG(WARNING,
3885                             "Memzone physical address same as virtual\n");
3886                 PMD_DRV_LOG(WARNING,
3887                             "Using rte_mem_virt2iova()\n");
3888                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3889                 if (mz_phys_addr == RTE_BAD_IOVA) {
3890                         PMD_DRV_LOG(ERR,
3891                                     "Can't map address to physical memory\n");
3892                         return -ENOMEM;
3893                 }
3894         }
3895
3896         bp->tx_mem_zone = (const void *)mz;
3897         bp->hw_tx_port_stats = mz->addr;
3898         bp->hw_tx_port_stats_map = mz_phys_addr;
3899         bp->flags |= BNXT_FLAG_PORT_STATS;
3900
3901         /* Display extended statistics if FW supports it */
3902         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
3903             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
3904             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
3905                 return 0;
3906
3907         bp->hw_rx_port_stats_ext = (void *)
3908                 ((uint8_t *)bp->hw_rx_port_stats +
3909                  sizeof(struct rx_port_stats));
3910         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
3911                 sizeof(struct rx_port_stats);
3912         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
3913
3914         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
3915             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
3916                 bp->hw_tx_port_stats_ext = (void *)
3917                         ((uint8_t *)bp->hw_tx_port_stats +
3918                          sizeof(struct tx_port_stats));
3919                 bp->hw_tx_port_stats_ext_map =
3920                         bp->hw_tx_port_stats_map +
3921                         sizeof(struct tx_port_stats);
3922                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
3923         }
3924
3925         return 0;
3926 }
3927
3928 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
3929 {
3930         struct bnxt *bp = eth_dev->data->dev_private;
3931         int rc = 0;
3932
3933         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3934                                                RTE_ETHER_ADDR_LEN *
3935                                                bp->max_l2_ctx,
3936                                                0);
3937         if (eth_dev->data->mac_addrs == NULL) {
3938                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
3939                 return -ENOMEM;
3940         }
3941
3942         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
3943                 if (BNXT_PF(bp))
3944                         return -EINVAL;
3945
3946                 /* Generate a random MAC address, if none was assigned by PF */
3947                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
3948                 bnxt_eth_hw_addr_random(bp->mac_addr);
3949                 PMD_DRV_LOG(INFO,
3950                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
3951                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
3952                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
3953
3954                 rc = bnxt_hwrm_set_mac(bp);
3955                 if (!rc)
3956                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
3957                                RTE_ETHER_ADDR_LEN);
3958                 return rc;
3959         }
3960
3961         /* Copy the permanent MAC from the FUNC_QCAPS response */
3962         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
3963         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
3964
3965         return rc;
3966 }
3967
3968 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
3969 {
3970         if (!BNXT_PF(bp))
3971                 return;
3972
3973 #define ALLOW_FUNC(x)   \
3974         { \
3975                 uint32_t arg = (x); \
3976                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3977                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3978         }
3979
3980         /* Forward all requests if firmware is new enough */
3981         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3982              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3983             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3984                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3985         } else {
3986                 PMD_DRV_LOG(WARNING,
3987                             "Firmware too old for VF mailbox functionality\n");
3988                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3989         }
3990
3991         /*
3992          * The following are used for driver cleanup. If we disallow these,
3993          * VF drivers can't clean up cleanly.
3994          */
3995         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3996         ALLOW_FUNC(HWRM_VNIC_FREE);
3997         ALLOW_FUNC(HWRM_RING_FREE);
3998         ALLOW_FUNC(HWRM_RING_GRP_FREE);
3999         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4000         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4001         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4002         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4003         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4004 }
4005
4006 static int bnxt_init_fw(struct bnxt *bp)
4007 {
4008         uint16_t mtu;
4009         int rc = 0;
4010
4011         rc = bnxt_hwrm_ver_get(bp);
4012         if (rc)
4013                 return rc;
4014
4015         rc = bnxt_hwrm_func_reset(bp);
4016         if (rc)
4017                 return -EIO;
4018
4019         rc = bnxt_hwrm_queue_qportcfg(bp);
4020         if (rc)
4021                 return rc;
4022
4023         /* Get the MAX capabilities for this function */
4024         rc = bnxt_hwrm_func_qcaps(bp);
4025         if (rc)
4026                 return rc;
4027
4028         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4029         if (rc)
4030                 return rc;
4031
4032         if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
4033             mtu != bp->eth_dev->data->mtu)
4034                 bp->eth_dev->data->mtu = mtu;
4035
4036         bnxt_hwrm_port_led_qcaps(bp);
4037
4038         return 0;
4039 }
4040
4041 static int bnxt_init_resources(struct bnxt *bp)
4042 {
4043         int rc;
4044
4045         rc = bnxt_init_fw(bp);
4046         if (rc)
4047                 return rc;
4048
4049         rc = bnxt_setup_mac_addr(bp->eth_dev);
4050         if (rc)
4051                 return rc;
4052
4053         bnxt_config_vf_req_fwd(bp);
4054
4055         rc = bnxt_hwrm_func_driver_register(bp);
4056         if (rc) {
4057                 PMD_DRV_LOG(ERR, "Failed to register driver");
4058                 return -EBUSY;
4059         }
4060
4061         if (BNXT_PF(bp)) {
4062                 if (bp->pdev->max_vfs) {
4063                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4064                         if (rc) {
4065                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4066                                 return rc;
4067                         }
4068                 } else {
4069                         rc = bnxt_hwrm_allocate_pf_only(bp);
4070                         if (rc) {
4071                                 PMD_DRV_LOG(ERR,
4072                                             "Failed to allocate PF resources");
4073                                 return rc;
4074                         }
4075                 }
4076         }
4077
4078         rc = bnxt_alloc_mem(bp);
4079         if (rc)
4080                 return rc;
4081
4082         rc = bnxt_setup_int(bp);
4083         if (rc)
4084                 return rc;
4085
4086         bnxt_init_nic(bp);
4087
4088         rc = bnxt_request_int(bp);
4089         if (rc)
4090                 return rc;
4091
4092         return 0;
4093 }
4094
4095 static int
4096 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4097 {
4098         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4099         static int version_printed;
4100         struct bnxt *bp;
4101         int rc;
4102
4103         if (version_printed++ == 0)
4104                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4105
4106         rte_eth_copy_pci_info(eth_dev, pci_dev);
4107
4108         bp = eth_dev->data->dev_private;
4109
4110         bp->dev_stopped = 1;
4111
4112         eth_dev->dev_ops = &bnxt_dev_ops;
4113         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4114         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4115
4116         /*
4117          * For secondary processes, we don't initialise any further
4118          * as primary has already done this work.
4119          */
4120         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4121                 return 0;
4122
4123         if (bnxt_vf_pciid(pci_dev->id.device_id))
4124                 bp->flags |= BNXT_FLAG_VF;
4125
4126         if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
4127             pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
4128             pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
4129             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 ||
4130             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2)
4131                 bp->flags |= BNXT_FLAG_THOR_CHIP;
4132
4133         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4134             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4135             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4136             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4137                 bp->flags |= BNXT_FLAG_STINGRAY;
4138
4139         rc = bnxt_init_board(eth_dev);
4140         if (rc) {
4141                 PMD_DRV_LOG(ERR,
4142                             "Failed to initialize board rc: %x\n", rc);
4143                 return rc;
4144         }
4145
4146         rc = bnxt_alloc_hwrm_resources(bp);
4147         if (rc) {
4148                 PMD_DRV_LOG(ERR,
4149                             "Failed to allocate hwrm resource rc: %x\n", rc);
4150                 goto error_free;
4151         }
4152         rc = bnxt_init_resources(bp);
4153         if (rc)
4154                 goto error_free;
4155
4156         rc = bnxt_alloc_stats_mem(bp);
4157         if (rc)
4158                 goto error_free;
4159
4160         PMD_DRV_LOG(INFO,
4161                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4162                     pci_dev->mem_resource[0].phys_addr,
4163                     pci_dev->mem_resource[0].addr);
4164
4165         return 0;
4166
4167 error_free:
4168         bnxt_dev_uninit(eth_dev);
4169         return rc;
4170 }
4171
4172 static int
4173 bnxt_uninit_resources(struct bnxt *bp)
4174 {
4175         int rc;
4176
4177         bnxt_disable_int(bp);
4178         bnxt_free_int(bp);
4179         bnxt_free_mem(bp);
4180         bnxt_hwrm_func_buf_unrgtr(bp);
4181         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4182         bp->flags &= ~BNXT_FLAG_REGISTERED;
4183         bnxt_free_ctx_mem(bp);
4184         bnxt_free_hwrm_resources(bp);
4185
4186         return rc;
4187 }
4188
4189 static int
4190 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4191 {
4192         struct bnxt *bp = eth_dev->data->dev_private;
4193         int rc;
4194
4195         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4196                 return -EPERM;
4197
4198         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4199
4200         rc = bnxt_uninit_resources(bp);
4201
4202         if (bp->grp_info != NULL) {
4203                 rte_free(bp->grp_info);
4204                 bp->grp_info = NULL;
4205         }
4206
4207         if (bp->tx_mem_zone) {
4208                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4209                 bp->tx_mem_zone = NULL;
4210         }
4211
4212         if (bp->rx_mem_zone) {
4213                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4214                 bp->rx_mem_zone = NULL;
4215         }
4216
4217         if (bp->dev_stopped == 0)
4218                 bnxt_dev_close_op(eth_dev);
4219         if (bp->pf.vf_info)
4220                 rte_free(bp->pf.vf_info);
4221         eth_dev->dev_ops = NULL;
4222         eth_dev->rx_pkt_burst = NULL;
4223         eth_dev->tx_pkt_burst = NULL;
4224
4225         return rc;
4226 }
4227
4228 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4229         struct rte_pci_device *pci_dev)
4230 {
4231         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4232                 bnxt_dev_init);
4233 }
4234
4235 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4236 {
4237         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4238                 return rte_eth_dev_pci_generic_remove(pci_dev,
4239                                 bnxt_dev_uninit);
4240         else
4241                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4242 }
4243
4244 static struct rte_pci_driver bnxt_rte_pmd = {
4245         .id_table = bnxt_pci_id_map,
4246         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4247         .probe = bnxt_pci_probe,
4248         .remove = bnxt_pci_remove,
4249 };
4250
4251 static bool
4252 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4253 {
4254         if (strcmp(dev->device->driver->name, drv->driver.name))
4255                 return false;
4256
4257         return true;
4258 }
4259
4260 bool is_bnxt_supported(struct rte_eth_dev *dev)
4261 {
4262         return is_device_supported(dev, &bnxt_rte_pmd);
4263 }
4264
4265 RTE_INIT(bnxt_init_log)
4266 {
4267         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4268         if (bnxt_logtype_driver >= 0)
4269                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4270 }
4271
4272 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4273 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4274 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");