1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
18 #include "bnxt_filter.h"
19 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_stats.h"
27 #include "bnxt_vnic.h"
28 #include "hsi_struct_def_dpdk.h"
29 #include "bnxt_nvm_defs.h"
30 #include "bnxt_util.h"
32 #define DRV_MODULE_NAME "bnxt"
33 static const char bnxt_version[] =
34 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
35 int bnxt_logtype_driver;
37 #define PCI_VENDOR_ID_BROADCOM 0x14E4
39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
40 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
41 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
42 #define BROADCOM_DEV_ID_57414_VF 0x16c1
43 #define BROADCOM_DEV_ID_57301 0x16c8
44 #define BROADCOM_DEV_ID_57302 0x16c9
45 #define BROADCOM_DEV_ID_57304_PF 0x16ca
46 #define BROADCOM_DEV_ID_57304_VF 0x16cb
47 #define BROADCOM_DEV_ID_57417_MF 0x16cc
48 #define BROADCOM_DEV_ID_NS2 0x16cd
49 #define BROADCOM_DEV_ID_57311 0x16ce
50 #define BROADCOM_DEV_ID_57312 0x16cf
51 #define BROADCOM_DEV_ID_57402 0x16d0
52 #define BROADCOM_DEV_ID_57404 0x16d1
53 #define BROADCOM_DEV_ID_57406_PF 0x16d2
54 #define BROADCOM_DEV_ID_57406_VF 0x16d3
55 #define BROADCOM_DEV_ID_57402_MF 0x16d4
56 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
57 #define BROADCOM_DEV_ID_57412 0x16d6
58 #define BROADCOM_DEV_ID_57414 0x16d7
59 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
60 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
61 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
62 #define BROADCOM_DEV_ID_57412_MF 0x16de
63 #define BROADCOM_DEV_ID_57314 0x16df
64 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
65 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
66 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
67 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
68 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
69 #define BROADCOM_DEV_ID_57404_MF 0x16e7
70 #define BROADCOM_DEV_ID_57406_MF 0x16e8
71 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
72 #define BROADCOM_DEV_ID_57407_MF 0x16ea
73 #define BROADCOM_DEV_ID_57414_MF 0x16ec
74 #define BROADCOM_DEV_ID_57416_MF 0x16ee
75 #define BROADCOM_DEV_ID_57508 0x1750
76 #define BROADCOM_DEV_ID_57504 0x1751
77 #define BROADCOM_DEV_ID_57502 0x1752
78 #define BROADCOM_DEV_ID_57500_VF1 0x1806
79 #define BROADCOM_DEV_ID_57500_VF2 0x1807
80 #define BROADCOM_DEV_ID_58802 0xd802
81 #define BROADCOM_DEV_ID_58804 0xd804
82 #define BROADCOM_DEV_ID_58808 0x16f0
83 #define BROADCOM_DEV_ID_58802_VF 0xd800
85 static const struct rte_pci_id bnxt_pci_id_map[] = {
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
87 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
89 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
98 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
122 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
123 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
124 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
125 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
126 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
127 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
128 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
129 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
130 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
131 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
132 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
133 { .vendor_id = 0, /* sentinel */ },
136 #define BNXT_ETH_RSS_SUPPORT ( \
138 ETH_RSS_NONFRAG_IPV4_TCP | \
139 ETH_RSS_NONFRAG_IPV4_UDP | \
141 ETH_RSS_NONFRAG_IPV6_TCP | \
142 ETH_RSS_NONFRAG_IPV6_UDP)
144 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
145 DEV_TX_OFFLOAD_IPV4_CKSUM | \
146 DEV_TX_OFFLOAD_TCP_CKSUM | \
147 DEV_TX_OFFLOAD_UDP_CKSUM | \
148 DEV_TX_OFFLOAD_TCP_TSO | \
149 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
150 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
151 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
152 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
153 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
154 DEV_TX_OFFLOAD_QINQ_INSERT | \
155 DEV_TX_OFFLOAD_MULTI_SEGS)
157 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
158 DEV_RX_OFFLOAD_VLAN_STRIP | \
159 DEV_RX_OFFLOAD_IPV4_CKSUM | \
160 DEV_RX_OFFLOAD_UDP_CKSUM | \
161 DEV_RX_OFFLOAD_TCP_CKSUM | \
162 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
163 DEV_RX_OFFLOAD_JUMBO_FRAME | \
164 DEV_RX_OFFLOAD_KEEP_CRC | \
165 DEV_RX_OFFLOAD_VLAN_EXTEND | \
166 DEV_RX_OFFLOAD_TCP_LRO)
168 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
169 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
170 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
171 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
172 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
173 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
174 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
176 int is_bnxt_in_error(struct bnxt *bp)
178 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
180 if (bp->flags & BNXT_FLAG_FW_RESET)
186 /***********************/
189 * High level utility functions
192 uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
194 if (!BNXT_CHIP_THOR(bp))
197 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
198 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
199 BNXT_RSS_ENTRIES_PER_CTX_THOR;
202 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
204 if (!BNXT_CHIP_THOR(bp))
205 return HW_HASH_INDEX_SIZE;
207 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
210 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
212 bnxt_free_filter_mem(bp);
213 bnxt_free_vnic_attributes(bp);
214 bnxt_free_vnic_mem(bp);
216 /* tx/rx rings are configured as part of *_queue_setup callbacks.
217 * If the number of rings change across fw update,
218 * we don't have much choice except to warn the user.
222 bnxt_free_tx_rings(bp);
223 bnxt_free_rx_rings(bp);
225 bnxt_free_async_cp_ring(bp);
228 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
232 rc = bnxt_alloc_ring_grps(bp);
236 rc = bnxt_alloc_async_ring_struct(bp);
240 rc = bnxt_alloc_vnic_mem(bp);
244 rc = bnxt_alloc_vnic_attributes(bp);
248 rc = bnxt_alloc_filter_mem(bp);
252 rc = bnxt_alloc_async_cp_ring(bp);
259 bnxt_free_mem(bp, reconfig);
263 static int bnxt_init_chip(struct bnxt *bp)
265 struct bnxt_rx_queue *rxq;
266 struct rte_eth_link new;
267 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
268 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
269 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
270 uint64_t rx_offloads = dev_conf->rxmode.offloads;
271 uint32_t intr_vector = 0;
272 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
273 uint32_t vec = BNXT_MISC_VEC_ID;
277 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
278 bp->eth_dev->data->dev_conf.rxmode.offloads |=
279 DEV_RX_OFFLOAD_JUMBO_FRAME;
280 bp->flags |= BNXT_FLAG_JUMBO;
282 bp->eth_dev->data->dev_conf.rxmode.offloads &=
283 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
284 bp->flags &= ~BNXT_FLAG_JUMBO;
287 /* THOR does not support ring groups.
288 * But we will use the array to save RSS context IDs.
290 if (BNXT_CHIP_THOR(bp))
291 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
293 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
295 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
299 rc = bnxt_alloc_hwrm_rings(bp);
301 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
305 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
307 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
311 rc = bnxt_mq_rx_configure(bp);
313 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
317 /* VNIC configuration */
318 for (i = 0; i < bp->nr_vnics; i++) {
319 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
320 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
322 rc = bnxt_vnic_grp_alloc(bp, vnic);
326 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
327 i, vnic, vnic->fw_grp_ids);
329 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
331 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
336 /* Alloc RSS context only if RSS mode is enabled */
337 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
338 int j, nr_ctxs = bnxt_rss_ctxts(bp);
341 for (j = 0; j < nr_ctxs; j++) {
342 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
348 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
352 vnic->num_lb_ctxts = nr_ctxs;
356 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
357 * setting is not available at this time, it will not be
358 * configured correctly in the CFA.
360 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
361 vnic->vlan_strip = true;
363 vnic->vlan_strip = false;
365 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
367 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
372 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
375 "HWRM vnic %d filter failure rc: %x\n",
380 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
381 rxq = bp->eth_dev->data->rx_queues[j];
384 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
385 j, rxq->vnic, rxq->vnic->fw_grp_ids);
387 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
388 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
391 rc = bnxt_vnic_rss_configure(bp, vnic);
394 "HWRM vnic set RSS failure rc: %x\n", rc);
398 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
400 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
401 DEV_RX_OFFLOAD_TCP_LRO)
402 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
404 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
406 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
409 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
413 /* check and configure queue intr-vector mapping */
414 if ((rte_intr_cap_multiple(intr_handle) ||
415 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
416 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
417 intr_vector = bp->eth_dev->data->nb_rx_queues;
418 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
419 if (intr_vector > bp->rx_cp_nr_rings) {
420 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
424 rc = rte_intr_efd_enable(intr_handle, intr_vector);
429 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
430 intr_handle->intr_vec =
431 rte_zmalloc("intr_vec",
432 bp->eth_dev->data->nb_rx_queues *
434 if (intr_handle->intr_vec == NULL) {
435 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
436 " intr_vec", bp->eth_dev->data->nb_rx_queues);
440 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
441 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
442 intr_handle->intr_vec, intr_handle->nb_efd,
443 intr_handle->max_intr);
444 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
446 intr_handle->intr_vec[queue_id] =
447 vec + BNXT_RX_VEC_START;
448 if (vec < base + intr_handle->nb_efd - 1)
453 /* enable uio/vfio intr/eventfd mapping */
454 rc = rte_intr_enable(intr_handle);
458 rc = bnxt_get_hwrm_link_config(bp, &new);
460 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
464 if (!bp->link_info.link_up) {
465 rc = bnxt_set_hwrm_link_config(bp, true);
468 "HWRM link config failure rc: %x\n", rc);
472 bnxt_print_link_info(bp->eth_dev);
477 rte_free(intr_handle->intr_vec);
479 rte_intr_efd_disable(intr_handle);
481 /* Some of the error status returned by FW may not be from errno.h */
488 static int bnxt_shutdown_nic(struct bnxt *bp)
490 bnxt_free_all_hwrm_resources(bp);
491 bnxt_free_all_filters(bp);
492 bnxt_free_all_vnics(bp);
496 static int bnxt_init_nic(struct bnxt *bp)
500 if (BNXT_HAS_RING_GRPS(bp)) {
501 rc = bnxt_init_ring_grps(bp);
507 bnxt_init_filters(bp);
513 * Device configuration and status function
516 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
517 struct rte_eth_dev_info *dev_info)
519 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
520 struct bnxt *bp = eth_dev->data->dev_private;
521 uint16_t max_vnics, i, j, vpool, vrxq;
522 unsigned int max_rx_rings;
525 rc = is_bnxt_in_error(bp);
530 dev_info->max_mac_addrs = bp->max_l2_ctx;
531 dev_info->max_hash_mac_addrs = 0;
533 /* PF/VF specifics */
535 dev_info->max_vfs = pdev->max_vfs;
537 max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
538 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
539 dev_info->max_rx_queues = max_rx_rings;
540 dev_info->max_tx_queues = max_rx_rings;
541 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
542 dev_info->hash_key_size = 40;
543 max_vnics = bp->max_vnics;
546 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
547 dev_info->max_mtu = BNXT_MAX_MTU;
549 /* Fast path specifics */
550 dev_info->min_rx_bufsize = 1;
551 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
553 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
554 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
555 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
556 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
557 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
560 dev_info->default_rxconf = (struct rte_eth_rxconf) {
566 .rx_free_thresh = 32,
567 /* If no descriptors available, pkts are dropped by default */
571 dev_info->default_txconf = (struct rte_eth_txconf) {
577 .tx_free_thresh = 32,
580 eth_dev->data->dev_conf.intr_conf.lsc = 1;
582 eth_dev->data->dev_conf.intr_conf.rxq = 1;
583 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
584 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
585 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
586 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
591 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
592 * need further investigation.
596 vpool = 64; /* ETH_64_POOLS */
597 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
598 for (i = 0; i < 4; vpool >>= 1, i++) {
599 if (max_vnics > vpool) {
600 for (j = 0; j < 5; vrxq >>= 1, j++) {
601 if (dev_info->max_rx_queues > vrxq) {
607 /* Not enough resources to support VMDq */
611 /* Not enough resources to support VMDq */
615 dev_info->max_vmdq_pools = vpool;
616 dev_info->vmdq_queue_num = vrxq;
618 dev_info->vmdq_pool_base = 0;
619 dev_info->vmdq_queue_base = 0;
624 /* Configure the device based on the configuration provided */
625 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
627 struct bnxt *bp = eth_dev->data->dev_private;
628 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
631 bp->rx_queues = (void *)eth_dev->data->rx_queues;
632 bp->tx_queues = (void *)eth_dev->data->tx_queues;
633 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
634 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
636 rc = is_bnxt_in_error(bp);
640 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
641 rc = bnxt_hwrm_check_vf_rings(bp);
643 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
647 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
649 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
653 /* legacy driver needs to get updated values */
654 rc = bnxt_hwrm_func_qcaps(bp);
656 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
661 /* Inherit new configurations */
662 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
663 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
664 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
665 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
666 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
670 if (BNXT_HAS_RING_GRPS(bp) &&
671 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
674 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
675 bp->max_vnics < eth_dev->data->nb_rx_queues)
678 bp->rx_cp_nr_rings = bp->rx_nr_rings;
679 bp->tx_cp_nr_rings = bp->tx_nr_rings;
681 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
683 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
684 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
686 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
692 "Insufficient resources to support requested config\n");
694 "Num Queues Requested: Tx %d, Rx %d\n",
695 eth_dev->data->nb_tx_queues,
696 eth_dev->data->nb_rx_queues);
698 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
699 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
700 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
704 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
706 struct rte_eth_link *link = ð_dev->data->dev_link;
708 if (link->link_status)
709 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
710 eth_dev->data->port_id,
711 (uint32_t)link->link_speed,
712 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
713 ("full-duplex") : ("half-duplex\n"));
715 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
716 eth_dev->data->port_id);
720 * Determine whether the current configuration requires support for scattered
721 * receive; return 1 if scattered receive is required and 0 if not.
723 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
728 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
729 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
731 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
732 RTE_PKTMBUF_HEADROOM);
733 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
739 static eth_rx_burst_t
740 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
743 #ifndef RTE_LIBRTE_IEEE1588
745 * Vector mode receive can be enabled only if scatter rx is not
746 * in use and rx offloads are limited to VLAN stripping and
749 if (!eth_dev->data->scattered_rx &&
750 !(eth_dev->data->dev_conf.rxmode.offloads &
751 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
752 DEV_RX_OFFLOAD_KEEP_CRC |
753 DEV_RX_OFFLOAD_JUMBO_FRAME |
754 DEV_RX_OFFLOAD_IPV4_CKSUM |
755 DEV_RX_OFFLOAD_UDP_CKSUM |
756 DEV_RX_OFFLOAD_TCP_CKSUM |
757 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
758 DEV_RX_OFFLOAD_VLAN_FILTER))) {
759 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
760 eth_dev->data->port_id);
761 return bnxt_recv_pkts_vec;
763 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
764 eth_dev->data->port_id);
766 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
767 eth_dev->data->port_id,
768 eth_dev->data->scattered_rx,
769 eth_dev->data->dev_conf.rxmode.offloads);
772 return bnxt_recv_pkts;
775 static eth_tx_burst_t
776 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
779 #ifndef RTE_LIBRTE_IEEE1588
781 * Vector mode transmit can be enabled only if not using scatter rx
784 if (!eth_dev->data->scattered_rx &&
785 !eth_dev->data->dev_conf.txmode.offloads) {
786 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
787 eth_dev->data->port_id);
788 return bnxt_xmit_pkts_vec;
790 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
791 eth_dev->data->port_id);
793 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
794 eth_dev->data->port_id,
795 eth_dev->data->scattered_rx,
796 eth_dev->data->dev_conf.txmode.offloads);
799 return bnxt_xmit_pkts;
802 static int bnxt_handle_if_change_status(struct bnxt *bp)
806 /* Since fw has undergone a reset and lost all contexts,
807 * set fatal flag to not issue hwrm during cleanup
809 bp->flags |= BNXT_FLAG_FATAL_ERROR;
810 bnxt_uninit_resources(bp, true);
812 /* clear fatal flag so that re-init happens */
813 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
814 rc = bnxt_init_resources(bp, true);
816 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
821 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
823 struct bnxt *bp = eth_dev->data->dev_private;
824 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
828 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
830 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
831 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
835 rc = bnxt_hwrm_if_change(bp, 1);
837 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
838 rc = bnxt_handle_if_change_status(bp);
844 rc = bnxt_init_chip(bp);
848 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
850 bnxt_link_update_op(eth_dev, 1);
852 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
853 vlan_mask |= ETH_VLAN_FILTER_MASK;
854 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
855 vlan_mask |= ETH_VLAN_STRIP_MASK;
856 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
860 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
861 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
863 bp->flags |= BNXT_FLAG_INIT_DONE;
864 eth_dev->data->dev_started = 1;
866 bnxt_schedule_fw_health_check(bp);
870 bnxt_hwrm_if_change(bp, 0);
871 bnxt_shutdown_nic(bp);
872 bnxt_free_tx_mbufs(bp);
873 bnxt_free_rx_mbufs(bp);
877 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
879 struct bnxt *bp = eth_dev->data->dev_private;
882 if (!bp->link_info.link_up)
883 rc = bnxt_set_hwrm_link_config(bp, true);
885 eth_dev->data->dev_link.link_status = 1;
887 bnxt_print_link_info(eth_dev);
891 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
893 struct bnxt *bp = eth_dev->data->dev_private;
895 eth_dev->data->dev_link.link_status = 0;
896 bnxt_set_hwrm_link_config(bp, false);
897 bp->link_info.link_up = 0;
902 /* Unload the driver, release resources */
903 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
905 struct bnxt *bp = eth_dev->data->dev_private;
906 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
907 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
909 eth_dev->data->dev_started = 0;
910 /* Prevent crashes when queues are still in use */
911 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
912 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
914 bnxt_disable_int(bp);
916 /* disable uio/vfio intr/eventfd mapping */
917 rte_intr_disable(intr_handle);
919 bnxt_cancel_fw_health_check(bp);
921 bp->flags &= ~BNXT_FLAG_INIT_DONE;
922 if (bp->eth_dev->data->dev_started) {
923 /* TBD: STOP HW queues DMA */
924 eth_dev->data->dev_link.link_status = 0;
926 bnxt_dev_set_link_down_op(eth_dev);
927 /* Wait for link to be reset and the async notification to process. */
928 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL * 2);
930 /* Clean queue intr-vector mapping */
931 rte_intr_efd_disable(intr_handle);
932 if (intr_handle->intr_vec != NULL) {
933 rte_free(intr_handle->intr_vec);
934 intr_handle->intr_vec = NULL;
937 bnxt_hwrm_port_clr_stats(bp);
938 bnxt_free_tx_mbufs(bp);
939 bnxt_free_rx_mbufs(bp);
940 /* Process any remaining notifications in default completion queue */
941 bnxt_int_handler(eth_dev);
942 bnxt_shutdown_nic(bp);
943 bnxt_hwrm_if_change(bp, 0);
947 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
949 struct bnxt *bp = eth_dev->data->dev_private;
951 if (bp->dev_stopped == 0)
952 bnxt_dev_stop_op(eth_dev);
954 if (eth_dev->data->mac_addrs != NULL) {
955 rte_free(eth_dev->data->mac_addrs);
956 eth_dev->data->mac_addrs = NULL;
958 if (bp->grp_info != NULL) {
959 rte_free(bp->grp_info);
963 bnxt_dev_uninit(eth_dev);
966 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
969 struct bnxt *bp = eth_dev->data->dev_private;
970 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
971 struct bnxt_vnic_info *vnic;
972 struct bnxt_filter_info *filter, *temp_filter;
975 if (is_bnxt_in_error(bp))
979 * Loop through all VNICs from the specified filter flow pools to
980 * remove the corresponding MAC addr filter
982 for (i = 0; i < bp->nr_vnics; i++) {
983 if (!(pool_mask & (1ULL << i)))
986 vnic = &bp->vnic_info[i];
987 filter = STAILQ_FIRST(&vnic->filter);
989 temp_filter = STAILQ_NEXT(filter, next);
990 if (filter->mac_index == index) {
991 STAILQ_REMOVE(&vnic->filter, filter,
992 bnxt_filter_info, next);
993 bnxt_hwrm_clear_l2_filter(bp, filter);
994 filter->mac_index = INVALID_MAC_INDEX;
995 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
996 STAILQ_INSERT_TAIL(&bp->free_filter_list,
999 filter = temp_filter;
1004 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1005 struct rte_ether_addr *mac_addr,
1006 uint32_t index, uint32_t pool)
1008 struct bnxt *bp = eth_dev->data->dev_private;
1009 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1010 struct bnxt_filter_info *filter;
1013 rc = is_bnxt_in_error(bp);
1017 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1018 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1023 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1026 /* Attach requested MAC address to the new l2_filter */
1027 STAILQ_FOREACH(filter, &vnic->filter, next) {
1028 if (filter->mac_index == index) {
1030 "MAC addr already existed for pool %d\n", pool);
1034 filter = bnxt_alloc_filter(bp);
1036 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1040 filter->mac_index = index;
1041 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1042 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1044 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1046 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1048 filter->mac_index = INVALID_MAC_INDEX;
1049 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1050 bnxt_free_filter(bp, filter);
1056 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1059 struct bnxt *bp = eth_dev->data->dev_private;
1060 struct rte_eth_link new;
1061 unsigned int cnt = BNXT_LINK_WAIT_CNT;
1063 rc = is_bnxt_in_error(bp);
1067 memset(&new, 0, sizeof(new));
1069 /* Retrieve link info from hardware */
1070 rc = bnxt_get_hwrm_link_config(bp, &new);
1072 new.link_speed = ETH_LINK_SPEED_100M;
1073 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1075 "Failed to retrieve link rc = 0x%x!\n", rc);
1079 if (!wait_to_complete || new.link_status)
1082 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1086 /* Timed out or success */
1087 if (new.link_status != eth_dev->data->dev_link.link_status ||
1088 new.link_speed != eth_dev->data->dev_link.link_speed) {
1089 rte_eth_linkstatus_set(eth_dev, &new);
1091 _rte_eth_dev_callback_process(eth_dev,
1092 RTE_ETH_EVENT_INTR_LSC,
1095 bnxt_print_link_info(eth_dev);
1101 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1103 struct bnxt *bp = eth_dev->data->dev_private;
1104 struct bnxt_vnic_info *vnic;
1108 rc = is_bnxt_in_error(bp);
1112 if (bp->vnic_info == NULL)
1115 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1117 old_flags = vnic->flags;
1118 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1119 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1121 vnic->flags = old_flags;
1126 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1128 struct bnxt *bp = eth_dev->data->dev_private;
1129 struct bnxt_vnic_info *vnic;
1133 rc = is_bnxt_in_error(bp);
1137 if (bp->vnic_info == NULL)
1140 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1142 old_flags = vnic->flags;
1143 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1144 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1146 vnic->flags = old_flags;
1151 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1153 struct bnxt *bp = eth_dev->data->dev_private;
1154 struct bnxt_vnic_info *vnic;
1158 rc = is_bnxt_in_error(bp);
1162 if (bp->vnic_info == NULL)
1165 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1167 old_flags = vnic->flags;
1168 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1169 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1171 vnic->flags = old_flags;
1176 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1178 struct bnxt *bp = eth_dev->data->dev_private;
1179 struct bnxt_vnic_info *vnic;
1183 rc = is_bnxt_in_error(bp);
1187 if (bp->vnic_info == NULL)
1190 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1192 old_flags = vnic->flags;
1193 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1194 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1196 vnic->flags = old_flags;
1201 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1202 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1204 if (qid >= bp->rx_nr_rings)
1207 return bp->eth_dev->data->rx_queues[qid];
1210 /* Return rxq corresponding to a given rss table ring/group ID. */
1211 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1213 struct bnxt_rx_queue *rxq;
1216 if (!BNXT_HAS_RING_GRPS(bp)) {
1217 for (i = 0; i < bp->rx_nr_rings; i++) {
1218 rxq = bp->eth_dev->data->rx_queues[i];
1219 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1223 for (i = 0; i < bp->rx_nr_rings; i++) {
1224 if (bp->grp_info[i].fw_grp_id == fwr)
1229 return INVALID_HW_RING_ID;
1232 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1233 struct rte_eth_rss_reta_entry64 *reta_conf,
1236 struct bnxt *bp = eth_dev->data->dev_private;
1237 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1238 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1239 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1243 rc = is_bnxt_in_error(bp);
1247 if (!vnic->rss_table)
1250 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1253 if (reta_size != tbl_size) {
1254 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1255 "(%d) must equal the size supported by the hardware "
1256 "(%d)\n", reta_size, tbl_size);
1260 for (i = 0; i < reta_size; i++) {
1261 struct bnxt_rx_queue *rxq;
1263 idx = i / RTE_RETA_GROUP_SIZE;
1264 sft = i % RTE_RETA_GROUP_SIZE;
1266 if (!(reta_conf[idx].mask & (1ULL << sft)))
1269 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1271 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1275 if (BNXT_CHIP_THOR(bp)) {
1276 vnic->rss_table[i * 2] =
1277 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1278 vnic->rss_table[i * 2 + 1] =
1279 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1281 vnic->rss_table[i] =
1282 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1285 vnic->rss_table[i] =
1286 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1289 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1293 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1294 struct rte_eth_rss_reta_entry64 *reta_conf,
1297 struct bnxt *bp = eth_dev->data->dev_private;
1298 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1299 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1300 uint16_t idx, sft, i;
1303 rc = is_bnxt_in_error(bp);
1307 /* Retrieve from the default VNIC */
1310 if (!vnic->rss_table)
1313 if (reta_size != tbl_size) {
1314 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1315 "(%d) must equal the size supported by the hardware "
1316 "(%d)\n", reta_size, tbl_size);
1320 for (idx = 0, i = 0; i < reta_size; i++) {
1321 idx = i / RTE_RETA_GROUP_SIZE;
1322 sft = i % RTE_RETA_GROUP_SIZE;
1324 if (reta_conf[idx].mask & (1ULL << sft)) {
1327 if (BNXT_CHIP_THOR(bp))
1328 qid = bnxt_rss_to_qid(bp,
1329 vnic->rss_table[i * 2]);
1331 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1333 if (qid == INVALID_HW_RING_ID) {
1334 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1337 reta_conf[idx].reta[sft] = qid;
1344 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1345 struct rte_eth_rss_conf *rss_conf)
1347 struct bnxt *bp = eth_dev->data->dev_private;
1348 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1349 struct bnxt_vnic_info *vnic;
1352 rc = is_bnxt_in_error(bp);
1357 * If RSS enablement were different than dev_configure,
1358 * then return -EINVAL
1360 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1361 if (!rss_conf->rss_hf)
1362 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1364 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1368 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1369 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1371 /* Update the default RSS VNIC(s) */
1372 vnic = &bp->vnic_info[0];
1373 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1376 * If hashkey is not specified, use the previously configured
1379 if (!rss_conf->rss_key)
1382 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1384 "Invalid hashkey length, should be 16 bytes\n");
1387 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1390 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1394 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1395 struct rte_eth_rss_conf *rss_conf)
1397 struct bnxt *bp = eth_dev->data->dev_private;
1398 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1400 uint32_t hash_types;
1402 rc = is_bnxt_in_error(bp);
1406 /* RSS configuration is the same for all VNICs */
1407 if (vnic && vnic->rss_hash_key) {
1408 if (rss_conf->rss_key) {
1409 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1410 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1411 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1414 hash_types = vnic->hash_type;
1415 rss_conf->rss_hf = 0;
1416 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1417 rss_conf->rss_hf |= ETH_RSS_IPV4;
1418 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1420 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1421 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1423 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1425 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1426 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1428 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1430 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1431 rss_conf->rss_hf |= ETH_RSS_IPV6;
1432 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1434 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1435 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1437 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1439 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1440 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1442 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1446 "Unknwon RSS config from firmware (%08x), RSS disabled",
1451 rss_conf->rss_hf = 0;
1456 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1457 struct rte_eth_fc_conf *fc_conf)
1459 struct bnxt *bp = dev->data->dev_private;
1460 struct rte_eth_link link_info;
1463 rc = is_bnxt_in_error(bp);
1467 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1471 memset(fc_conf, 0, sizeof(*fc_conf));
1472 if (bp->link_info.auto_pause)
1473 fc_conf->autoneg = 1;
1474 switch (bp->link_info.pause) {
1476 fc_conf->mode = RTE_FC_NONE;
1478 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1479 fc_conf->mode = RTE_FC_TX_PAUSE;
1481 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1482 fc_conf->mode = RTE_FC_RX_PAUSE;
1484 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1485 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1486 fc_conf->mode = RTE_FC_FULL;
1492 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1493 struct rte_eth_fc_conf *fc_conf)
1495 struct bnxt *bp = dev->data->dev_private;
1498 rc = is_bnxt_in_error(bp);
1502 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1503 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1507 switch (fc_conf->mode) {
1509 bp->link_info.auto_pause = 0;
1510 bp->link_info.force_pause = 0;
1512 case RTE_FC_RX_PAUSE:
1513 if (fc_conf->autoneg) {
1514 bp->link_info.auto_pause =
1515 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1516 bp->link_info.force_pause = 0;
1518 bp->link_info.auto_pause = 0;
1519 bp->link_info.force_pause =
1520 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1523 case RTE_FC_TX_PAUSE:
1524 if (fc_conf->autoneg) {
1525 bp->link_info.auto_pause =
1526 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1527 bp->link_info.force_pause = 0;
1529 bp->link_info.auto_pause = 0;
1530 bp->link_info.force_pause =
1531 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1535 if (fc_conf->autoneg) {
1536 bp->link_info.auto_pause =
1537 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1538 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1539 bp->link_info.force_pause = 0;
1541 bp->link_info.auto_pause = 0;
1542 bp->link_info.force_pause =
1543 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1544 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1548 return bnxt_set_hwrm_link_config(bp, true);
1551 /* Add UDP tunneling port */
1553 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1554 struct rte_eth_udp_tunnel *udp_tunnel)
1556 struct bnxt *bp = eth_dev->data->dev_private;
1557 uint16_t tunnel_type = 0;
1560 rc = is_bnxt_in_error(bp);
1564 switch (udp_tunnel->prot_type) {
1565 case RTE_TUNNEL_TYPE_VXLAN:
1566 if (bp->vxlan_port_cnt) {
1567 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1568 udp_tunnel->udp_port);
1569 if (bp->vxlan_port != udp_tunnel->udp_port) {
1570 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1573 bp->vxlan_port_cnt++;
1577 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1578 bp->vxlan_port_cnt++;
1580 case RTE_TUNNEL_TYPE_GENEVE:
1581 if (bp->geneve_port_cnt) {
1582 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1583 udp_tunnel->udp_port);
1584 if (bp->geneve_port != udp_tunnel->udp_port) {
1585 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1588 bp->geneve_port_cnt++;
1592 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1593 bp->geneve_port_cnt++;
1596 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1599 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1605 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1606 struct rte_eth_udp_tunnel *udp_tunnel)
1608 struct bnxt *bp = eth_dev->data->dev_private;
1609 uint16_t tunnel_type = 0;
1613 rc = is_bnxt_in_error(bp);
1617 switch (udp_tunnel->prot_type) {
1618 case RTE_TUNNEL_TYPE_VXLAN:
1619 if (!bp->vxlan_port_cnt) {
1620 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1623 if (bp->vxlan_port != udp_tunnel->udp_port) {
1624 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1625 udp_tunnel->udp_port, bp->vxlan_port);
1628 if (--bp->vxlan_port_cnt)
1632 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1633 port = bp->vxlan_fw_dst_port_id;
1635 case RTE_TUNNEL_TYPE_GENEVE:
1636 if (!bp->geneve_port_cnt) {
1637 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1640 if (bp->geneve_port != udp_tunnel->udp_port) {
1641 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1642 udp_tunnel->udp_port, bp->geneve_port);
1645 if (--bp->geneve_port_cnt)
1649 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1650 port = bp->geneve_fw_dst_port_id;
1653 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1657 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1660 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1663 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1664 bp->geneve_port = 0;
1669 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1671 struct bnxt_filter_info *filter;
1672 struct bnxt_vnic_info *vnic;
1674 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1676 /* if VLAN exists && VLAN matches vlan_id
1677 * remove the MAC+VLAN filter
1678 * add a new MAC only filter
1680 * VLAN filter doesn't exist, just skip and continue
1682 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1683 filter = STAILQ_FIRST(&vnic->filter);
1685 /* Search for this matching MAC+VLAN filter */
1686 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1687 !memcmp(filter->l2_addr,
1689 RTE_ETHER_ADDR_LEN)) {
1690 /* Delete the filter */
1691 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1694 STAILQ_REMOVE(&vnic->filter, filter,
1695 bnxt_filter_info, next);
1696 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1699 "Del Vlan filter for %d\n",
1703 filter = STAILQ_NEXT(filter, next);
1708 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1710 struct bnxt_filter_info *filter;
1711 struct bnxt_vnic_info *vnic;
1713 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1714 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1715 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1717 /* Implementation notes on the use of VNIC in this command:
1719 * By default, these filters belong to default vnic for the function.
1720 * Once these filters are set up, only destination VNIC can be modified.
1721 * If the destination VNIC is not specified in this command,
1722 * then the HWRM shall only create an l2 context id.
1725 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1726 filter = STAILQ_FIRST(&vnic->filter);
1727 /* Check if the VLAN has already been added */
1729 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1730 !memcmp(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN))
1733 filter = STAILQ_NEXT(filter, next);
1736 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1737 * command to create MAC+VLAN filter with the right flags, enables set.
1739 filter = bnxt_alloc_filter(bp);
1742 "MAC/VLAN filter alloc failed\n");
1745 /* MAC + VLAN ID filter */
1746 filter->l2_ivlan = vlan_id;
1747 filter->l2_ivlan_mask = 0x0FFF;
1748 filter->enables |= en;
1749 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1750 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1752 /* Free the newly allocated filter as we were
1753 * not able to create the filter in hardware.
1755 filter->fw_l2_filter_id = UINT64_MAX;
1756 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1760 /* Add this new filter to the list */
1761 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1763 "Added Vlan filter for %d\n", vlan_id);
1767 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1768 uint16_t vlan_id, int on)
1770 struct bnxt *bp = eth_dev->data->dev_private;
1773 rc = is_bnxt_in_error(bp);
1777 /* These operations apply to ALL existing MAC/VLAN filters */
1779 return bnxt_add_vlan_filter(bp, vlan_id);
1781 return bnxt_del_vlan_filter(bp, vlan_id);
1785 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1787 struct bnxt *bp = dev->data->dev_private;
1788 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1792 rc = is_bnxt_in_error(bp);
1796 if (mask & ETH_VLAN_FILTER_MASK) {
1797 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1798 /* Remove any VLAN filters programmed */
1799 for (i = 0; i < 4095; i++)
1800 bnxt_del_vlan_filter(bp, i);
1802 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1803 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1806 if (mask & ETH_VLAN_STRIP_MASK) {
1807 /* Enable or disable VLAN stripping */
1808 for (i = 0; i < bp->nr_vnics; i++) {
1809 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1810 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1811 vnic->vlan_strip = true;
1813 vnic->vlan_strip = false;
1814 bnxt_hwrm_vnic_cfg(bp, vnic);
1816 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1817 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1820 if (mask & ETH_VLAN_EXTEND_MASK) {
1821 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1822 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
1824 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
1831 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
1834 struct bnxt *bp = dev->data->dev_private;
1835 int qinq = dev->data->dev_conf.rxmode.offloads &
1836 DEV_RX_OFFLOAD_VLAN_EXTEND;
1838 if (vlan_type != ETH_VLAN_TYPE_INNER &&
1839 vlan_type != ETH_VLAN_TYPE_OUTER) {
1841 "Unsupported vlan type.");
1846 "QinQ not enabled. Needs to be ON as we can "
1847 "accelerate only outer vlan\n");
1851 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
1853 case RTE_ETHER_TYPE_QINQ:
1855 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
1857 case RTE_ETHER_TYPE_VLAN:
1859 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
1863 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
1867 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
1871 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
1874 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
1877 bp->outer_tpid_bd |= tpid;
1878 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
1879 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
1881 "Can accelerate only outer vlan in QinQ\n");
1889 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1890 struct rte_ether_addr *addr)
1892 struct bnxt *bp = dev->data->dev_private;
1893 /* Default Filter is tied to VNIC 0 */
1894 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1895 struct bnxt_filter_info *filter;
1898 rc = is_bnxt_in_error(bp);
1902 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1905 if (rte_is_zero_ether_addr(addr))
1908 STAILQ_FOREACH(filter, &vnic->filter, next) {
1909 /* Default Filter is at Index 0 */
1910 if (filter->mac_index != 0)
1913 memcpy(filter->l2_addr, addr, RTE_ETHER_ADDR_LEN);
1914 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1915 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX |
1916 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1918 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1919 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1921 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1923 memcpy(filter->l2_addr, bp->mac_addr,
1924 RTE_ETHER_ADDR_LEN);
1928 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
1929 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1937 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1938 struct rte_ether_addr *mc_addr_set,
1939 uint32_t nb_mc_addr)
1941 struct bnxt *bp = eth_dev->data->dev_private;
1942 char *mc_addr_list = (char *)mc_addr_set;
1943 struct bnxt_vnic_info *vnic;
1944 uint32_t off = 0, i = 0;
1947 rc = is_bnxt_in_error(bp);
1951 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1953 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1954 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1958 /* TODO Check for Duplicate mcast addresses */
1959 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1960 for (i = 0; i < nb_mc_addr; i++) {
1961 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1962 RTE_ETHER_ADDR_LEN);
1963 off += RTE_ETHER_ADDR_LEN;
1966 vnic->mc_addr_cnt = i;
1969 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1973 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1975 struct bnxt *bp = dev->data->dev_private;
1976 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1977 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1978 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1981 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1982 fw_major, fw_minor, fw_updt);
1984 ret += 1; /* add the size of '\0' */
1985 if (fw_size < (uint32_t)ret)
1992 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1993 struct rte_eth_rxq_info *qinfo)
1995 struct bnxt_rx_queue *rxq;
1997 rxq = dev->data->rx_queues[queue_id];
1999 qinfo->mp = rxq->mb_pool;
2000 qinfo->scattered_rx = dev->data->scattered_rx;
2001 qinfo->nb_desc = rxq->nb_rx_desc;
2003 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2004 qinfo->conf.rx_drop_en = 0;
2005 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2009 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2010 struct rte_eth_txq_info *qinfo)
2012 struct bnxt_tx_queue *txq;
2014 txq = dev->data->tx_queues[queue_id];
2016 qinfo->nb_desc = txq->nb_tx_desc;
2018 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2019 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2020 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2022 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2023 qinfo->conf.tx_rs_thresh = 0;
2024 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2027 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2029 struct bnxt *bp = eth_dev->data->dev_private;
2030 uint32_t new_pkt_size;
2034 rc = is_bnxt_in_error(bp);
2038 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2039 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2043 * If vector-mode tx/rx is active, disallow any MTU change that would
2044 * require scattered receive support.
2046 if (eth_dev->data->dev_started &&
2047 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2048 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2050 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2052 "MTU change would require scattered rx support. ");
2053 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2058 if (new_mtu > RTE_ETHER_MTU) {
2059 bp->flags |= BNXT_FLAG_JUMBO;
2060 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2061 DEV_RX_OFFLOAD_JUMBO_FRAME;
2063 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2064 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2065 bp->flags &= ~BNXT_FLAG_JUMBO;
2068 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2070 for (i = 0; i < bp->nr_vnics; i++) {
2071 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2074 vnic->mru = new_mtu + RTE_ETHER_HDR_LEN +
2075 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
2076 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2080 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2081 size -= RTE_PKTMBUF_HEADROOM;
2083 if (size < new_mtu) {
2084 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2090 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2096 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2098 struct bnxt *bp = dev->data->dev_private;
2099 uint16_t vlan = bp->vlan;
2102 rc = is_bnxt_in_error(bp);
2106 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2108 "PVID cannot be modified for this function\n");
2111 bp->vlan = on ? pvid : 0;
2113 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2120 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2122 struct bnxt *bp = dev->data->dev_private;
2125 rc = is_bnxt_in_error(bp);
2129 return bnxt_hwrm_port_led_cfg(bp, true);
2133 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2135 struct bnxt *bp = dev->data->dev_private;
2138 rc = is_bnxt_in_error(bp);
2142 return bnxt_hwrm_port_led_cfg(bp, false);
2146 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2148 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2149 uint32_t desc = 0, raw_cons = 0, cons;
2150 struct bnxt_cp_ring_info *cpr;
2151 struct bnxt_rx_queue *rxq;
2152 struct rx_pkt_cmpl *rxcmp;
2155 rc = is_bnxt_in_error(bp);
2159 rxq = dev->data->rx_queues[rx_queue_id];
2161 raw_cons = cpr->cp_raw_cons;
2164 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2165 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2166 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2168 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2180 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2182 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2183 struct bnxt_rx_ring_info *rxr;
2184 struct bnxt_cp_ring_info *cpr;
2185 struct bnxt_sw_rx_bd *rx_buf;
2186 struct rx_pkt_cmpl *rxcmp;
2187 uint32_t cons, cp_cons;
2193 rc = is_bnxt_in_error(rxq->bp);
2200 if (offset >= rxq->nb_rx_desc)
2203 cons = RING_CMP(cpr->cp_ring_struct, offset);
2204 cp_cons = cpr->cp_raw_cons;
2205 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2207 if (cons > cp_cons) {
2208 if (CMPL_VALID(rxcmp, cpr->valid))
2209 return RTE_ETH_RX_DESC_DONE;
2211 if (CMPL_VALID(rxcmp, !cpr->valid))
2212 return RTE_ETH_RX_DESC_DONE;
2214 rx_buf = &rxr->rx_buf_ring[cons];
2215 if (rx_buf->mbuf == NULL)
2216 return RTE_ETH_RX_DESC_UNAVAIL;
2219 return RTE_ETH_RX_DESC_AVAIL;
2223 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2225 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2226 struct bnxt_tx_ring_info *txr;
2227 struct bnxt_cp_ring_info *cpr;
2228 struct bnxt_sw_tx_bd *tx_buf;
2229 struct tx_pkt_cmpl *txcmp;
2230 uint32_t cons, cp_cons;
2236 rc = is_bnxt_in_error(txq->bp);
2243 if (offset >= txq->nb_tx_desc)
2246 cons = RING_CMP(cpr->cp_ring_struct, offset);
2247 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2248 cp_cons = cpr->cp_raw_cons;
2250 if (cons > cp_cons) {
2251 if (CMPL_VALID(txcmp, cpr->valid))
2252 return RTE_ETH_TX_DESC_UNAVAIL;
2254 if (CMPL_VALID(txcmp, !cpr->valid))
2255 return RTE_ETH_TX_DESC_UNAVAIL;
2257 tx_buf = &txr->tx_buf_ring[cons];
2258 if (tx_buf->mbuf == NULL)
2259 return RTE_ETH_TX_DESC_DONE;
2261 return RTE_ETH_TX_DESC_FULL;
2264 static struct bnxt_filter_info *
2265 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2266 struct rte_eth_ethertype_filter *efilter,
2267 struct bnxt_vnic_info *vnic0,
2268 struct bnxt_vnic_info *vnic,
2271 struct bnxt_filter_info *mfilter = NULL;
2275 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2276 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2277 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2278 " ethertype filter.", efilter->ether_type);
2282 if (efilter->queue >= bp->rx_nr_rings) {
2283 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2288 vnic0 = &bp->vnic_info[0];
2289 vnic = &bp->vnic_info[efilter->queue];
2291 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2296 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2297 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2298 if ((!memcmp(efilter->mac_addr.addr_bytes,
2299 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2301 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2302 mfilter->ethertype == efilter->ether_type)) {
2308 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2309 if ((!memcmp(efilter->mac_addr.addr_bytes,
2310 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2311 mfilter->ethertype == efilter->ether_type &&
2313 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2327 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2328 enum rte_filter_op filter_op,
2331 struct bnxt *bp = dev->data->dev_private;
2332 struct rte_eth_ethertype_filter *efilter =
2333 (struct rte_eth_ethertype_filter *)arg;
2334 struct bnxt_filter_info *bfilter, *filter1;
2335 struct bnxt_vnic_info *vnic, *vnic0;
2338 if (filter_op == RTE_ETH_FILTER_NOP)
2342 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2347 vnic0 = &bp->vnic_info[0];
2348 vnic = &bp->vnic_info[efilter->queue];
2350 switch (filter_op) {
2351 case RTE_ETH_FILTER_ADD:
2352 bnxt_match_and_validate_ether_filter(bp, efilter,
2357 bfilter = bnxt_get_unused_filter(bp);
2358 if (bfilter == NULL) {
2360 "Not enough resources for a new filter.\n");
2363 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2364 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2365 RTE_ETHER_ADDR_LEN);
2366 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2367 RTE_ETHER_ADDR_LEN);
2368 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2369 bfilter->ethertype = efilter->ether_type;
2370 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2372 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2373 if (filter1 == NULL) {
2378 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2379 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2381 bfilter->dst_id = vnic->fw_vnic_id;
2383 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2385 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2388 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2391 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2393 case RTE_ETH_FILTER_DELETE:
2394 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2396 if (ret == -EEXIST) {
2397 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2399 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2401 bnxt_free_filter(bp, filter1);
2402 } else if (ret == 0) {
2403 PMD_DRV_LOG(ERR, "No matching filter found\n");
2407 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2413 bnxt_free_filter(bp, bfilter);
2419 parse_ntuple_filter(struct bnxt *bp,
2420 struct rte_eth_ntuple_filter *nfilter,
2421 struct bnxt_filter_info *bfilter)
2425 if (nfilter->queue >= bp->rx_nr_rings) {
2426 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2430 switch (nfilter->dst_port_mask) {
2432 bfilter->dst_port_mask = -1;
2433 bfilter->dst_port = nfilter->dst_port;
2434 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2435 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2438 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2442 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2443 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2445 switch (nfilter->proto_mask) {
2447 if (nfilter->proto == 17) /* IPPROTO_UDP */
2448 bfilter->ip_protocol = 17;
2449 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2450 bfilter->ip_protocol = 6;
2453 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2456 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2460 switch (nfilter->dst_ip_mask) {
2462 bfilter->dst_ipaddr_mask[0] = -1;
2463 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2464 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2465 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2468 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2472 switch (nfilter->src_ip_mask) {
2474 bfilter->src_ipaddr_mask[0] = -1;
2475 bfilter->src_ipaddr[0] = nfilter->src_ip;
2476 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2477 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2480 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2484 switch (nfilter->src_port_mask) {
2486 bfilter->src_port_mask = -1;
2487 bfilter->src_port = nfilter->src_port;
2488 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2489 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2492 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2497 //nfilter->priority = (uint8_t)filter->priority;
2499 bfilter->enables = en;
2503 static struct bnxt_filter_info*
2504 bnxt_match_ntuple_filter(struct bnxt *bp,
2505 struct bnxt_filter_info *bfilter,
2506 struct bnxt_vnic_info **mvnic)
2508 struct bnxt_filter_info *mfilter = NULL;
2511 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2512 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2513 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2514 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2515 bfilter->src_ipaddr_mask[0] ==
2516 mfilter->src_ipaddr_mask[0] &&
2517 bfilter->src_port == mfilter->src_port &&
2518 bfilter->src_port_mask == mfilter->src_port_mask &&
2519 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2520 bfilter->dst_ipaddr_mask[0] ==
2521 mfilter->dst_ipaddr_mask[0] &&
2522 bfilter->dst_port == mfilter->dst_port &&
2523 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2524 bfilter->flags == mfilter->flags &&
2525 bfilter->enables == mfilter->enables) {
2536 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2537 struct rte_eth_ntuple_filter *nfilter,
2538 enum rte_filter_op filter_op)
2540 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2541 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2544 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2545 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2549 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2550 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2554 bfilter = bnxt_get_unused_filter(bp);
2555 if (bfilter == NULL) {
2557 "Not enough resources for a new filter.\n");
2560 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2564 vnic = &bp->vnic_info[nfilter->queue];
2565 vnic0 = &bp->vnic_info[0];
2566 filter1 = STAILQ_FIRST(&vnic0->filter);
2567 if (filter1 == NULL) {
2572 bfilter->dst_id = vnic->fw_vnic_id;
2573 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2575 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2576 bfilter->ethertype = 0x800;
2577 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2579 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2581 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2582 bfilter->dst_id == mfilter->dst_id) {
2583 PMD_DRV_LOG(ERR, "filter exists.\n");
2586 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2587 bfilter->dst_id != mfilter->dst_id) {
2588 mfilter->dst_id = vnic->fw_vnic_id;
2589 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2590 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2591 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2592 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2593 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2596 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2597 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2602 if (filter_op == RTE_ETH_FILTER_ADD) {
2603 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2604 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2607 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2609 if (mfilter == NULL) {
2610 /* This should not happen. But for Coverity! */
2614 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2616 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2617 bnxt_free_filter(bp, mfilter);
2618 mfilter->fw_l2_filter_id = -1;
2619 bnxt_free_filter(bp, bfilter);
2620 bfilter->fw_l2_filter_id = -1;
2625 bfilter->fw_l2_filter_id = -1;
2626 bnxt_free_filter(bp, bfilter);
2631 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2632 enum rte_filter_op filter_op,
2635 struct bnxt *bp = dev->data->dev_private;
2638 if (filter_op == RTE_ETH_FILTER_NOP)
2642 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2647 switch (filter_op) {
2648 case RTE_ETH_FILTER_ADD:
2649 ret = bnxt_cfg_ntuple_filter(bp,
2650 (struct rte_eth_ntuple_filter *)arg,
2653 case RTE_ETH_FILTER_DELETE:
2654 ret = bnxt_cfg_ntuple_filter(bp,
2655 (struct rte_eth_ntuple_filter *)arg,
2659 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2667 bnxt_parse_fdir_filter(struct bnxt *bp,
2668 struct rte_eth_fdir_filter *fdir,
2669 struct bnxt_filter_info *filter)
2671 enum rte_fdir_mode fdir_mode =
2672 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2673 struct bnxt_vnic_info *vnic0, *vnic;
2674 struct bnxt_filter_info *filter1;
2678 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2681 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2682 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2684 switch (fdir->input.flow_type) {
2685 case RTE_ETH_FLOW_IPV4:
2686 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2688 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2689 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2690 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2691 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2692 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2693 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2694 filter->ip_addr_type =
2695 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2696 filter->src_ipaddr_mask[0] = 0xffffffff;
2697 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2698 filter->dst_ipaddr_mask[0] = 0xffffffff;
2699 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2700 filter->ethertype = 0x800;
2701 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2703 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2704 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2705 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2706 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2707 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2708 filter->dst_port_mask = 0xffff;
2709 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2710 filter->src_port_mask = 0xffff;
2711 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2712 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2713 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2714 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2715 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2716 filter->ip_protocol = 6;
2717 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2718 filter->ip_addr_type =
2719 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2720 filter->src_ipaddr_mask[0] = 0xffffffff;
2721 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2722 filter->dst_ipaddr_mask[0] = 0xffffffff;
2723 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2724 filter->ethertype = 0x800;
2725 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2727 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2728 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2729 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2730 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2731 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2732 filter->dst_port_mask = 0xffff;
2733 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2734 filter->src_port_mask = 0xffff;
2735 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2736 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2737 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2738 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2739 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2740 filter->ip_protocol = 17;
2741 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2742 filter->ip_addr_type =
2743 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2744 filter->src_ipaddr_mask[0] = 0xffffffff;
2745 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2746 filter->dst_ipaddr_mask[0] = 0xffffffff;
2747 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2748 filter->ethertype = 0x800;
2749 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2751 case RTE_ETH_FLOW_IPV6:
2752 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2754 filter->ip_addr_type =
2755 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2756 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2757 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2758 rte_memcpy(filter->src_ipaddr,
2759 fdir->input.flow.ipv6_flow.src_ip, 16);
2760 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2761 rte_memcpy(filter->dst_ipaddr,
2762 fdir->input.flow.ipv6_flow.dst_ip, 16);
2763 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2764 memset(filter->dst_ipaddr_mask, 0xff, 16);
2765 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2766 memset(filter->src_ipaddr_mask, 0xff, 16);
2767 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2768 filter->ethertype = 0x86dd;
2769 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2771 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2772 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2773 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2774 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2775 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2776 filter->dst_port_mask = 0xffff;
2777 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2778 filter->src_port_mask = 0xffff;
2779 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2780 filter->ip_addr_type =
2781 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2782 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2783 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2784 rte_memcpy(filter->src_ipaddr,
2785 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2786 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2787 rte_memcpy(filter->dst_ipaddr,
2788 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2789 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2790 memset(filter->dst_ipaddr_mask, 0xff, 16);
2791 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2792 memset(filter->src_ipaddr_mask, 0xff, 16);
2793 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2794 filter->ethertype = 0x86dd;
2795 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2797 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2798 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2799 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2800 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2801 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2802 filter->dst_port_mask = 0xffff;
2803 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2804 filter->src_port_mask = 0xffff;
2805 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2806 filter->ip_addr_type =
2807 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2808 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2809 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2810 rte_memcpy(filter->src_ipaddr,
2811 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2812 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2813 rte_memcpy(filter->dst_ipaddr,
2814 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2815 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2816 memset(filter->dst_ipaddr_mask, 0xff, 16);
2817 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2818 memset(filter->src_ipaddr_mask, 0xff, 16);
2819 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2820 filter->ethertype = 0x86dd;
2821 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2823 case RTE_ETH_FLOW_L2_PAYLOAD:
2824 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2825 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2827 case RTE_ETH_FLOW_VXLAN:
2828 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2830 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2831 filter->tunnel_type =
2832 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2833 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2835 case RTE_ETH_FLOW_NVGRE:
2836 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2838 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2839 filter->tunnel_type =
2840 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2841 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2843 case RTE_ETH_FLOW_UNKNOWN:
2844 case RTE_ETH_FLOW_RAW:
2845 case RTE_ETH_FLOW_FRAG_IPV4:
2846 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2847 case RTE_ETH_FLOW_FRAG_IPV6:
2848 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2849 case RTE_ETH_FLOW_IPV6_EX:
2850 case RTE_ETH_FLOW_IPV6_TCP_EX:
2851 case RTE_ETH_FLOW_IPV6_UDP_EX:
2852 case RTE_ETH_FLOW_GENEVE:
2858 vnic0 = &bp->vnic_info[0];
2859 vnic = &bp->vnic_info[fdir->action.rx_queue];
2861 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2866 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2867 rte_memcpy(filter->dst_macaddr,
2868 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2869 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2872 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2873 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2874 filter1 = STAILQ_FIRST(&vnic0->filter);
2875 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2877 filter->dst_id = vnic->fw_vnic_id;
2878 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2879 if (filter->dst_macaddr[i] == 0x00)
2880 filter1 = STAILQ_FIRST(&vnic0->filter);
2882 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2885 if (filter1 == NULL)
2888 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2889 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2891 filter->enables = en;
2896 static struct bnxt_filter_info *
2897 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2898 struct bnxt_vnic_info **mvnic)
2900 struct bnxt_filter_info *mf = NULL;
2903 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2904 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2906 STAILQ_FOREACH(mf, &vnic->filter, next) {
2907 if (mf->filter_type == nf->filter_type &&
2908 mf->flags == nf->flags &&
2909 mf->src_port == nf->src_port &&
2910 mf->src_port_mask == nf->src_port_mask &&
2911 mf->dst_port == nf->dst_port &&
2912 mf->dst_port_mask == nf->dst_port_mask &&
2913 mf->ip_protocol == nf->ip_protocol &&
2914 mf->ip_addr_type == nf->ip_addr_type &&
2915 mf->ethertype == nf->ethertype &&
2916 mf->vni == nf->vni &&
2917 mf->tunnel_type == nf->tunnel_type &&
2918 mf->l2_ovlan == nf->l2_ovlan &&
2919 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2920 mf->l2_ivlan == nf->l2_ivlan &&
2921 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2922 !memcmp(mf->l2_addr, nf->l2_addr,
2923 RTE_ETHER_ADDR_LEN) &&
2924 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2925 RTE_ETHER_ADDR_LEN) &&
2926 !memcmp(mf->src_macaddr, nf->src_macaddr,
2927 RTE_ETHER_ADDR_LEN) &&
2928 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2929 RTE_ETHER_ADDR_LEN) &&
2930 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2931 sizeof(nf->src_ipaddr)) &&
2932 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2933 sizeof(nf->src_ipaddr_mask)) &&
2934 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2935 sizeof(nf->dst_ipaddr)) &&
2936 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2937 sizeof(nf->dst_ipaddr_mask))) {
2948 bnxt_fdir_filter(struct rte_eth_dev *dev,
2949 enum rte_filter_op filter_op,
2952 struct bnxt *bp = dev->data->dev_private;
2953 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
2954 struct bnxt_filter_info *filter, *match;
2955 struct bnxt_vnic_info *vnic, *mvnic;
2958 if (filter_op == RTE_ETH_FILTER_NOP)
2961 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2964 switch (filter_op) {
2965 case RTE_ETH_FILTER_ADD:
2966 case RTE_ETH_FILTER_DELETE:
2968 filter = bnxt_get_unused_filter(bp);
2969 if (filter == NULL) {
2971 "Not enough resources for a new flow.\n");
2975 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2978 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2980 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2981 vnic = &bp->vnic_info[0];
2983 vnic = &bp->vnic_info[fdir->action.rx_queue];
2985 match = bnxt_match_fdir(bp, filter, &mvnic);
2986 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2987 if (match->dst_id == vnic->fw_vnic_id) {
2988 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2992 match->dst_id = vnic->fw_vnic_id;
2993 ret = bnxt_hwrm_set_ntuple_filter(bp,
2996 STAILQ_REMOVE(&mvnic->filter, match,
2997 bnxt_filter_info, next);
2998 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3000 "Filter with matching pattern exist\n");
3002 "Updated it to new destination q\n");
3006 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3007 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3012 if (filter_op == RTE_ETH_FILTER_ADD) {
3013 ret = bnxt_hwrm_set_ntuple_filter(bp,
3018 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3020 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3021 STAILQ_REMOVE(&vnic->filter, match,
3022 bnxt_filter_info, next);
3023 bnxt_free_filter(bp, match);
3024 filter->fw_l2_filter_id = -1;
3025 bnxt_free_filter(bp, filter);
3028 case RTE_ETH_FILTER_FLUSH:
3029 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3030 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3032 STAILQ_FOREACH(filter, &vnic->filter, next) {
3033 if (filter->filter_type ==
3034 HWRM_CFA_NTUPLE_FILTER) {
3036 bnxt_hwrm_clear_ntuple_filter(bp,
3038 STAILQ_REMOVE(&vnic->filter, filter,
3039 bnxt_filter_info, next);
3044 case RTE_ETH_FILTER_UPDATE:
3045 case RTE_ETH_FILTER_STATS:
3046 case RTE_ETH_FILTER_INFO:
3047 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3050 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3057 filter->fw_l2_filter_id = -1;
3058 bnxt_free_filter(bp, filter);
3063 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
3064 enum rte_filter_type filter_type,
3065 enum rte_filter_op filter_op, void *arg)
3069 ret = is_bnxt_in_error(dev->data->dev_private);
3073 switch (filter_type) {
3074 case RTE_ETH_FILTER_TUNNEL:
3076 "filter type: %d: To be implemented\n", filter_type);
3078 case RTE_ETH_FILTER_FDIR:
3079 ret = bnxt_fdir_filter(dev, filter_op, arg);
3081 case RTE_ETH_FILTER_NTUPLE:
3082 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3084 case RTE_ETH_FILTER_ETHERTYPE:
3085 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3087 case RTE_ETH_FILTER_GENERIC:
3088 if (filter_op != RTE_ETH_FILTER_GET)
3090 *(const void **)arg = &bnxt_flow_ops;
3094 "Filter type (%d) not supported", filter_type);
3101 static const uint32_t *
3102 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3104 static const uint32_t ptypes[] = {
3105 RTE_PTYPE_L2_ETHER_VLAN,
3106 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3107 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3111 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3112 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3113 RTE_PTYPE_INNER_L4_ICMP,
3114 RTE_PTYPE_INNER_L4_TCP,
3115 RTE_PTYPE_INNER_L4_UDP,
3119 if (!dev->rx_pkt_burst)
3125 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3128 uint32_t reg_base = *reg_arr & 0xfffff000;
3132 for (i = 0; i < count; i++) {
3133 if ((reg_arr[i] & 0xfffff000) != reg_base)
3136 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3137 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3141 static int bnxt_map_ptp_regs(struct bnxt *bp)
3143 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3147 reg_arr = ptp->rx_regs;
3148 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3152 reg_arr = ptp->tx_regs;
3153 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3157 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3158 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3160 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3161 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3166 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3168 rte_write32(0, (uint8_t *)bp->bar0 +
3169 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3170 rte_write32(0, (uint8_t *)bp->bar0 +
3171 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3174 static uint64_t bnxt_cc_read(struct bnxt *bp)
3178 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3179 BNXT_GRCPF_REG_SYNC_TIME));
3180 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3181 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3185 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3187 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3190 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3191 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3192 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3195 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3196 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3197 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3198 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3199 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3200 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3205 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3207 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3208 struct bnxt_pf_info *pf = &bp->pf;
3215 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3216 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3217 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3220 port_id = pf->port_id;
3221 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3222 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3224 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3225 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3226 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3227 /* bnxt_clr_rx_ts(bp); TBD */
3231 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3232 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3233 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3234 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3240 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3243 struct bnxt *bp = dev->data->dev_private;
3244 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3249 ns = rte_timespec_to_ns(ts);
3250 /* Set the timecounters to a new value. */
3257 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3259 struct bnxt *bp = dev->data->dev_private;
3260 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3261 uint64_t ns, systime_cycles = 0;
3267 if (BNXT_CHIP_THOR(bp))
3268 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3271 systime_cycles = bnxt_cc_read(bp);
3273 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3274 *ts = rte_ns_to_timespec(ns);
3279 bnxt_timesync_enable(struct rte_eth_dev *dev)
3281 struct bnxt *bp = dev->data->dev_private;
3282 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3290 ptp->tx_tstamp_en = 1;
3291 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3293 rc = bnxt_hwrm_ptp_cfg(bp);
3297 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3298 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3299 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3301 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3302 ptp->tc.cc_shift = shift;
3303 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3305 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3306 ptp->rx_tstamp_tc.cc_shift = shift;
3307 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3309 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3310 ptp->tx_tstamp_tc.cc_shift = shift;
3311 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3313 if (!BNXT_CHIP_THOR(bp))
3314 bnxt_map_ptp_regs(bp);
3320 bnxt_timesync_disable(struct rte_eth_dev *dev)
3322 struct bnxt *bp = dev->data->dev_private;
3323 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3329 ptp->tx_tstamp_en = 0;
3332 bnxt_hwrm_ptp_cfg(bp);
3334 if (!BNXT_CHIP_THOR(bp))
3335 bnxt_unmap_ptp_regs(bp);
3341 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3342 struct timespec *timestamp,
3343 uint32_t flags __rte_unused)
3345 struct bnxt *bp = dev->data->dev_private;
3346 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3347 uint64_t rx_tstamp_cycles = 0;
3353 if (BNXT_CHIP_THOR(bp))
3354 rx_tstamp_cycles = ptp->rx_timestamp;
3356 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3358 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3359 *timestamp = rte_ns_to_timespec(ns);
3364 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3365 struct timespec *timestamp)
3367 struct bnxt *bp = dev->data->dev_private;
3368 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3369 uint64_t tx_tstamp_cycles = 0;
3376 if (BNXT_CHIP_THOR(bp))
3377 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3380 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3382 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3383 *timestamp = rte_ns_to_timespec(ns);
3389 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3391 struct bnxt *bp = dev->data->dev_private;
3392 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3397 ptp->tc.nsec += delta;
3403 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3405 struct bnxt *bp = dev->data->dev_private;
3407 uint32_t dir_entries;
3408 uint32_t entry_length;
3410 rc = is_bnxt_in_error(bp);
3414 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3415 bp->pdev->addr.domain, bp->pdev->addr.bus,
3416 bp->pdev->addr.devid, bp->pdev->addr.function);
3418 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3422 return dir_entries * entry_length;
3426 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3427 struct rte_dev_eeprom_info *in_eeprom)
3429 struct bnxt *bp = dev->data->dev_private;
3434 rc = is_bnxt_in_error(bp);
3438 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3439 "len = %d\n", bp->pdev->addr.domain,
3440 bp->pdev->addr.bus, bp->pdev->addr.devid,
3441 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3443 if (in_eeprom->offset == 0) /* special offset value to get directory */
3444 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3447 index = in_eeprom->offset >> 24;
3448 offset = in_eeprom->offset & 0xffffff;
3451 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3452 in_eeprom->length, in_eeprom->data);
3457 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3460 case BNX_DIR_TYPE_CHIMP_PATCH:
3461 case BNX_DIR_TYPE_BOOTCODE:
3462 case BNX_DIR_TYPE_BOOTCODE_2:
3463 case BNX_DIR_TYPE_APE_FW:
3464 case BNX_DIR_TYPE_APE_PATCH:
3465 case BNX_DIR_TYPE_KONG_FW:
3466 case BNX_DIR_TYPE_KONG_PATCH:
3467 case BNX_DIR_TYPE_BONO_FW:
3468 case BNX_DIR_TYPE_BONO_PATCH:
3476 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3479 case BNX_DIR_TYPE_AVS:
3480 case BNX_DIR_TYPE_EXP_ROM_MBA:
3481 case BNX_DIR_TYPE_PCIE:
3482 case BNX_DIR_TYPE_TSCF_UCODE:
3483 case BNX_DIR_TYPE_EXT_PHY:
3484 case BNX_DIR_TYPE_CCM:
3485 case BNX_DIR_TYPE_ISCSI_BOOT:
3486 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3487 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3495 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3497 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3498 bnxt_dir_type_is_other_exec_format(dir_type);
3502 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3503 struct rte_dev_eeprom_info *in_eeprom)
3505 struct bnxt *bp = dev->data->dev_private;
3506 uint8_t index, dir_op;
3507 uint16_t type, ext, ordinal, attr;
3510 rc = is_bnxt_in_error(bp);
3514 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3515 "len = %d\n", bp->pdev->addr.domain,
3516 bp->pdev->addr.bus, bp->pdev->addr.devid,
3517 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3520 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3524 type = in_eeprom->magic >> 16;
3526 if (type == 0xffff) { /* special value for directory operations */
3527 index = in_eeprom->magic & 0xff;
3528 dir_op = in_eeprom->magic >> 8;
3532 case 0x0e: /* erase */
3533 if (in_eeprom->offset != ~in_eeprom->magic)
3535 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3541 /* Create or re-write an NVM item: */
3542 if (bnxt_dir_type_is_executable(type) == true)
3544 ext = in_eeprom->magic & 0xffff;
3545 ordinal = in_eeprom->offset >> 16;
3546 attr = in_eeprom->offset & 0xffff;
3548 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3549 in_eeprom->data, in_eeprom->length);
3556 static const struct eth_dev_ops bnxt_dev_ops = {
3557 .dev_infos_get = bnxt_dev_info_get_op,
3558 .dev_close = bnxt_dev_close_op,
3559 .dev_configure = bnxt_dev_configure_op,
3560 .dev_start = bnxt_dev_start_op,
3561 .dev_stop = bnxt_dev_stop_op,
3562 .dev_set_link_up = bnxt_dev_set_link_up_op,
3563 .dev_set_link_down = bnxt_dev_set_link_down_op,
3564 .stats_get = bnxt_stats_get_op,
3565 .stats_reset = bnxt_stats_reset_op,
3566 .rx_queue_setup = bnxt_rx_queue_setup_op,
3567 .rx_queue_release = bnxt_rx_queue_release_op,
3568 .tx_queue_setup = bnxt_tx_queue_setup_op,
3569 .tx_queue_release = bnxt_tx_queue_release_op,
3570 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3571 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3572 .reta_update = bnxt_reta_update_op,
3573 .reta_query = bnxt_reta_query_op,
3574 .rss_hash_update = bnxt_rss_hash_update_op,
3575 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3576 .link_update = bnxt_link_update_op,
3577 .promiscuous_enable = bnxt_promiscuous_enable_op,
3578 .promiscuous_disable = bnxt_promiscuous_disable_op,
3579 .allmulticast_enable = bnxt_allmulticast_enable_op,
3580 .allmulticast_disable = bnxt_allmulticast_disable_op,
3581 .mac_addr_add = bnxt_mac_addr_add_op,
3582 .mac_addr_remove = bnxt_mac_addr_remove_op,
3583 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3584 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3585 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3586 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3587 .vlan_filter_set = bnxt_vlan_filter_set_op,
3588 .vlan_offload_set = bnxt_vlan_offload_set_op,
3589 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3590 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3591 .mtu_set = bnxt_mtu_set_op,
3592 .mac_addr_set = bnxt_set_default_mac_addr_op,
3593 .xstats_get = bnxt_dev_xstats_get_op,
3594 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3595 .xstats_reset = bnxt_dev_xstats_reset_op,
3596 .fw_version_get = bnxt_fw_version_get,
3597 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3598 .rxq_info_get = bnxt_rxq_info_get_op,
3599 .txq_info_get = bnxt_txq_info_get_op,
3600 .dev_led_on = bnxt_dev_led_on_op,
3601 .dev_led_off = bnxt_dev_led_off_op,
3602 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3603 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3604 .rx_queue_count = bnxt_rx_queue_count_op,
3605 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3606 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3607 .rx_queue_start = bnxt_rx_queue_start,
3608 .rx_queue_stop = bnxt_rx_queue_stop,
3609 .tx_queue_start = bnxt_tx_queue_start,
3610 .tx_queue_stop = bnxt_tx_queue_stop,
3611 .filter_ctrl = bnxt_filter_ctrl_op,
3612 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3613 .get_eeprom_length = bnxt_get_eeprom_length_op,
3614 .get_eeprom = bnxt_get_eeprom_op,
3615 .set_eeprom = bnxt_set_eeprom_op,
3616 .timesync_enable = bnxt_timesync_enable,
3617 .timesync_disable = bnxt_timesync_disable,
3618 .timesync_read_time = bnxt_timesync_read_time,
3619 .timesync_write_time = bnxt_timesync_write_time,
3620 .timesync_adjust_time = bnxt_timesync_adjust_time,
3621 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3622 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3625 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3629 /* Only pre-map the reset GRC registers using window 3 */
3630 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3631 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3633 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3638 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3640 struct bnxt_error_recovery_info *info = bp->recovery_info;
3641 uint32_t reg_base = 0xffffffff;
3644 /* Only pre-map the monitoring GRC registers using window 2 */
3645 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3646 uint32_t reg = info->status_regs[i];
3648 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3651 if (reg_base == 0xffffffff)
3652 reg_base = reg & 0xfffff000;
3653 if ((reg & 0xfffff000) != reg_base)
3656 /* Use mask 0xffc as the Lower 2 bits indicates
3657 * address space location
3659 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3663 if (reg_base == 0xffffffff)
3666 rte_write32(reg_base, (uint8_t *)bp->bar0 +
3667 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3672 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3674 struct bnxt_error_recovery_info *info = bp->recovery_info;
3675 uint32_t delay = info->delay_after_reset[index];
3676 uint32_t val = info->reset_reg_val[index];
3677 uint32_t reg = info->reset_reg[index];
3678 uint32_t type, offset;
3680 type = BNXT_FW_STATUS_REG_TYPE(reg);
3681 offset = BNXT_FW_STATUS_REG_OFF(reg);
3684 case BNXT_FW_STATUS_REG_TYPE_CFG:
3685 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3687 case BNXT_FW_STATUS_REG_TYPE_GRC:
3688 offset = bnxt_map_reset_regs(bp, offset);
3689 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3691 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3692 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3695 /* wait on a specific interval of time until core reset is complete */
3697 rte_delay_ms(delay);
3700 static void bnxt_dev_cleanup(struct bnxt *bp)
3702 bnxt_set_hwrm_link_config(bp, false);
3703 bp->link_info.link_up = 0;
3704 if (bp->dev_stopped == 0)
3705 bnxt_dev_stop_op(bp->eth_dev);
3707 bnxt_uninit_resources(bp, true);
3710 static int bnxt_restore_filters(struct bnxt *bp)
3712 struct rte_eth_dev *dev = bp->eth_dev;
3715 if (dev->data->all_multicast)
3716 ret = bnxt_allmulticast_enable_op(dev);
3717 if (dev->data->promiscuous)
3718 ret = bnxt_promiscuous_enable_op(dev);
3720 /* TODO restore other filters as well */
3724 static void bnxt_dev_recover(void *arg)
3726 struct bnxt *bp = arg;
3727 int timeout = bp->fw_reset_max_msecs;
3730 /* Clear Error flag so that device re-init should happen */
3731 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3734 rc = bnxt_hwrm_ver_get(bp);
3737 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3738 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3739 } while (rc && timeout);
3742 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3746 rc = bnxt_init_resources(bp, true);
3749 "Failed to initialize resources after reset\n");
3752 /* clear reset flag as the device is initialized now */
3753 bp->flags &= ~BNXT_FLAG_FW_RESET;
3755 rc = bnxt_dev_start_op(bp->eth_dev);
3757 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3761 rc = bnxt_restore_filters(bp);
3765 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3768 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3769 bnxt_uninit_resources(bp, false);
3770 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3773 void bnxt_dev_reset_and_resume(void *arg)
3775 struct bnxt *bp = arg;
3778 bnxt_dev_cleanup(bp);
3780 bnxt_wait_for_device_shutdown(bp);
3782 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3783 bnxt_dev_recover, (void *)bp);
3785 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3788 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3790 struct bnxt_error_recovery_info *info = bp->recovery_info;
3791 uint32_t reg = info->status_regs[index];
3792 uint32_t type, offset, val = 0;
3794 type = BNXT_FW_STATUS_REG_TYPE(reg);
3795 offset = BNXT_FW_STATUS_REG_OFF(reg);
3798 case BNXT_FW_STATUS_REG_TYPE_CFG:
3799 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3801 case BNXT_FW_STATUS_REG_TYPE_GRC:
3802 offset = info->mapped_status_regs[index];
3804 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3805 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3813 static int bnxt_fw_reset_all(struct bnxt *bp)
3815 struct bnxt_error_recovery_info *info = bp->recovery_info;
3819 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3820 /* Reset through master function driver */
3821 for (i = 0; i < info->reg_array_cnt; i++)
3822 bnxt_write_fw_reset_reg(bp, i);
3823 /* Wait for time specified by FW after triggering reset */
3824 rte_delay_ms(info->master_func_wait_period_after_reset);
3825 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3826 /* Reset with the help of Kong processor */
3827 rc = bnxt_hwrm_fw_reset(bp);
3829 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3835 static void bnxt_fw_reset_cb(void *arg)
3837 struct bnxt *bp = arg;
3838 struct bnxt_error_recovery_info *info = bp->recovery_info;
3841 /* Only Master function can do FW reset */
3842 if (bnxt_is_master_func(bp) &&
3843 bnxt_is_recovery_enabled(bp)) {
3844 rc = bnxt_fw_reset_all(bp);
3846 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3851 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3852 * EXCEPTION_FATAL_ASYNC event to all the functions
3853 * (including MASTER FUNC). After receiving this Async, all the active
3854 * drivers should treat this case as FW initiated recovery
3856 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3857 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3858 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3860 /* To recover from error */
3861 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3866 /* Driver should poll FW heartbeat, reset_counter with the frequency
3867 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3868 * When the driver detects heartbeat stop or change in reset_counter,
3869 * it has to trigger a reset to recover from the error condition.
3870 * A “master PF” is the function who will have the privilege to
3871 * initiate the chimp reset. The master PF will be elected by the
3872 * firmware and will be notified through async message.
3874 static void bnxt_check_fw_health(void *arg)
3876 struct bnxt *bp = arg;
3877 struct bnxt_error_recovery_info *info = bp->recovery_info;
3878 uint32_t val = 0, wait_msec;
3880 if (!info || !bnxt_is_recovery_enabled(bp) ||
3881 is_bnxt_in_error(bp))
3884 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3885 if (val == info->last_heart_beat)
3888 info->last_heart_beat = val;
3890 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3891 if (val != info->last_reset_counter)
3894 info->last_reset_counter = val;
3896 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3897 bnxt_check_fw_health, (void *)bp);
3901 /* Stop DMA to/from device */
3902 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3903 bp->flags |= BNXT_FLAG_FW_RESET;
3905 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
3907 if (bnxt_is_master_func(bp))
3908 wait_msec = info->master_func_wait_period;
3910 wait_msec = info->normal_func_wait_period;
3912 rte_eal_alarm_set(US_PER_MS * wait_msec,
3913 bnxt_fw_reset_cb, (void *)bp);
3916 void bnxt_schedule_fw_health_check(struct bnxt *bp)
3918 uint32_t polling_freq;
3920 if (!bnxt_is_recovery_enabled(bp))
3923 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
3926 polling_freq = bp->recovery_info->driver_polling_freq;
3928 rte_eal_alarm_set(US_PER_MS * polling_freq,
3929 bnxt_check_fw_health, (void *)bp);
3930 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3933 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
3935 if (!bnxt_is_recovery_enabled(bp))
3938 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
3939 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3942 static bool bnxt_vf_pciid(uint16_t id)
3944 if (id == BROADCOM_DEV_ID_57304_VF ||
3945 id == BROADCOM_DEV_ID_57406_VF ||
3946 id == BROADCOM_DEV_ID_5731X_VF ||
3947 id == BROADCOM_DEV_ID_5741X_VF ||
3948 id == BROADCOM_DEV_ID_57414_VF ||
3949 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3950 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3951 id == BROADCOM_DEV_ID_58802_VF ||
3952 id == BROADCOM_DEV_ID_57500_VF1 ||
3953 id == BROADCOM_DEV_ID_57500_VF2)
3958 bool bnxt_stratus_device(struct bnxt *bp)
3960 uint16_t id = bp->pdev->id.device_id;
3962 if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3963 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3964 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3969 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3971 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3972 struct bnxt *bp = eth_dev->data->dev_private;
3974 /* enable device (incl. PCI PM wakeup), and bus-mastering */
3975 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3976 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3977 if (!bp->bar0 || !bp->doorbell_base) {
3978 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
3982 bp->eth_dev = eth_dev;
3988 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
3989 struct bnxt_ctx_pg_info *ctx_pg,
3994 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
3995 const struct rte_memzone *mz = NULL;
3996 char mz_name[RTE_MEMZONE_NAMESIZE];
3997 rte_iova_t mz_phys_addr;
3998 uint64_t valid_bits = 0;
4005 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4007 rmem->page_size = BNXT_PAGE_SIZE;
4008 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4009 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4010 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4012 valid_bits = PTU_PTE_VALID;
4014 if (rmem->nr_pages > 1) {
4015 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4016 "bnxt_ctx_pg_tbl%s_%x_%d",
4017 suffix, idx, bp->eth_dev->data->port_id);
4018 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4019 mz = rte_memzone_lookup(mz_name);
4021 mz = rte_memzone_reserve_aligned(mz_name,
4025 RTE_MEMZONE_SIZE_HINT_ONLY |
4026 RTE_MEMZONE_IOVA_CONTIG,
4032 memset(mz->addr, 0, mz->len);
4033 mz_phys_addr = mz->iova;
4034 if ((unsigned long)mz->addr == mz_phys_addr) {
4036 "physical address same as virtual\n");
4037 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4038 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4039 if (mz_phys_addr == RTE_BAD_IOVA) {
4041 "unable to map addr to phys memory\n");
4045 rte_mem_lock_page(((char *)mz->addr));
4047 rmem->pg_tbl = mz->addr;
4048 rmem->pg_tbl_map = mz_phys_addr;
4049 rmem->pg_tbl_mz = mz;
4052 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4053 suffix, idx, bp->eth_dev->data->port_id);
4054 mz = rte_memzone_lookup(mz_name);
4056 mz = rte_memzone_reserve_aligned(mz_name,
4060 RTE_MEMZONE_SIZE_HINT_ONLY |
4061 RTE_MEMZONE_IOVA_CONTIG,
4067 memset(mz->addr, 0, mz->len);
4068 mz_phys_addr = mz->iova;
4069 if ((unsigned long)mz->addr == mz_phys_addr) {
4071 "Memzone physical address same as virtual.\n");
4072 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4073 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
4074 rte_mem_lock_page(((char *)mz->addr) + sz);
4075 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4076 if (mz_phys_addr == RTE_BAD_IOVA) {
4078 "unable to map addr to phys memory\n");
4083 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4084 rte_mem_lock_page(((char *)mz->addr) + sz);
4085 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4086 rmem->dma_arr[i] = mz_phys_addr + sz;
4088 if (rmem->nr_pages > 1) {
4089 if (i == rmem->nr_pages - 2 &&
4090 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4091 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4092 else if (i == rmem->nr_pages - 1 &&
4093 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4094 valid_bits |= PTU_PTE_LAST;
4096 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4102 if (rmem->vmem_size)
4103 rmem->vmem = (void **)mz->addr;
4104 rmem->dma_arr[0] = mz_phys_addr;
4108 static void bnxt_free_ctx_mem(struct bnxt *bp)
4112 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4115 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4116 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4117 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4118 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4119 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4120 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4121 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4122 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4123 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4124 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4125 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4127 for (i = 0; i < BNXT_MAX_Q; i++) {
4128 if (bp->ctx->tqm_mem[i])
4129 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4136 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4138 #define min_t(type, x, y) ({ \
4139 type __min1 = (x); \
4140 type __min2 = (y); \
4141 __min1 < __min2 ? __min1 : __min2; })
4143 #define max_t(type, x, y) ({ \
4144 type __max1 = (x); \
4145 type __max2 = (y); \
4146 __max1 > __max2 ? __max1 : __max2; })
4148 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4150 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4152 struct bnxt_ctx_pg_info *ctx_pg;
4153 struct bnxt_ctx_mem_info *ctx;
4154 uint32_t mem_size, ena, entries;
4157 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4159 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4163 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4166 ctx_pg = &ctx->qp_mem;
4167 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4168 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4169 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4173 ctx_pg = &ctx->srq_mem;
4174 ctx_pg->entries = ctx->srq_max_l2_entries;
4175 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4176 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4180 ctx_pg = &ctx->cq_mem;
4181 ctx_pg->entries = ctx->cq_max_l2_entries;
4182 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4183 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4187 ctx_pg = &ctx->vnic_mem;
4188 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4189 ctx->vnic_max_ring_table_entries;
4190 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4191 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4195 ctx_pg = &ctx->stat_mem;
4196 ctx_pg->entries = ctx->stat_max_entries;
4197 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4198 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4202 entries = ctx->qp_max_l2_entries;
4203 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4204 entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4205 ctx->tqm_max_entries_per_ring);
4206 for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4207 ctx_pg = ctx->tqm_mem[i];
4208 /* use min tqm entries for now. */
4209 ctx_pg->entries = entries;
4210 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4211 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4214 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4217 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4218 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4221 "Failed to configure context mem: rc = %d\n", rc);
4223 ctx->flags |= BNXT_CTX_FLAG_INITED;
4228 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4230 struct rte_pci_device *pci_dev = bp->pdev;
4231 char mz_name[RTE_MEMZONE_NAMESIZE];
4232 const struct rte_memzone *mz = NULL;
4233 uint32_t total_alloc_len;
4234 rte_iova_t mz_phys_addr;
4236 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4239 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4240 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4241 pci_dev->addr.bus, pci_dev->addr.devid,
4242 pci_dev->addr.function, "rx_port_stats");
4243 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4244 mz = rte_memzone_lookup(mz_name);
4246 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4247 sizeof(struct rx_port_stats_ext) + 512);
4249 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4252 RTE_MEMZONE_SIZE_HINT_ONLY |
4253 RTE_MEMZONE_IOVA_CONTIG);
4257 memset(mz->addr, 0, mz->len);
4258 mz_phys_addr = mz->iova;
4259 if ((unsigned long)mz->addr == mz_phys_addr) {
4261 "Memzone physical address same as virtual.\n");
4263 "Using rte_mem_virt2iova()\n");
4264 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4265 if (mz_phys_addr == RTE_BAD_IOVA) {
4267 "Can't map address to physical memory\n");
4272 bp->rx_mem_zone = (const void *)mz;
4273 bp->hw_rx_port_stats = mz->addr;
4274 bp->hw_rx_port_stats_map = mz_phys_addr;
4276 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4277 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4278 pci_dev->addr.bus, pci_dev->addr.devid,
4279 pci_dev->addr.function, "tx_port_stats");
4280 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4281 mz = rte_memzone_lookup(mz_name);
4283 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4284 sizeof(struct tx_port_stats_ext) + 512);
4286 mz = rte_memzone_reserve(mz_name,
4290 RTE_MEMZONE_SIZE_HINT_ONLY |
4291 RTE_MEMZONE_IOVA_CONTIG);
4295 memset(mz->addr, 0, mz->len);
4296 mz_phys_addr = mz->iova;
4297 if ((unsigned long)mz->addr == mz_phys_addr) {
4299 "Memzone physical address same as virtual\n");
4300 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4301 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4302 if (mz_phys_addr == RTE_BAD_IOVA) {
4304 "Can't map address to physical memory\n");
4309 bp->tx_mem_zone = (const void *)mz;
4310 bp->hw_tx_port_stats = mz->addr;
4311 bp->hw_tx_port_stats_map = mz_phys_addr;
4312 bp->flags |= BNXT_FLAG_PORT_STATS;
4314 /* Display extended statistics if FW supports it */
4315 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4316 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4317 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4320 bp->hw_rx_port_stats_ext = (void *)
4321 ((uint8_t *)bp->hw_rx_port_stats +
4322 sizeof(struct rx_port_stats));
4323 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4324 sizeof(struct rx_port_stats);
4325 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4327 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4328 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4329 bp->hw_tx_port_stats_ext = (void *)
4330 ((uint8_t *)bp->hw_tx_port_stats +
4331 sizeof(struct tx_port_stats));
4332 bp->hw_tx_port_stats_ext_map =
4333 bp->hw_tx_port_stats_map +
4334 sizeof(struct tx_port_stats);
4335 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4341 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4343 struct bnxt *bp = eth_dev->data->dev_private;
4346 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4347 RTE_ETHER_ADDR_LEN *
4350 if (eth_dev->data->mac_addrs == NULL) {
4351 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4355 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4359 /* Generate a random MAC address, if none was assigned by PF */
4360 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4361 bnxt_eth_hw_addr_random(bp->mac_addr);
4363 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4364 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4365 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4367 rc = bnxt_hwrm_set_mac(bp);
4369 memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4370 RTE_ETHER_ADDR_LEN);
4374 /* Copy the permanent MAC from the FUNC_QCAPS response */
4375 memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4376 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4381 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4385 /* MAC is already configured in FW */
4386 if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4389 /* Restore the old MAC configured */
4390 rc = bnxt_hwrm_set_mac(bp);
4392 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4397 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4402 #define ALLOW_FUNC(x) \
4404 uint32_t arg = (x); \
4405 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4406 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4409 /* Forward all requests if firmware is new enough */
4410 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4411 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4412 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4413 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4415 PMD_DRV_LOG(WARNING,
4416 "Firmware too old for VF mailbox functionality\n");
4417 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4421 * The following are used for driver cleanup. If we disallow these,
4422 * VF drivers can't clean up cleanly.
4424 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4425 ALLOW_FUNC(HWRM_VNIC_FREE);
4426 ALLOW_FUNC(HWRM_RING_FREE);
4427 ALLOW_FUNC(HWRM_RING_GRP_FREE);
4428 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4429 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4430 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4431 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4432 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4435 static int bnxt_init_fw(struct bnxt *bp)
4440 rc = bnxt_hwrm_ver_get(bp);
4444 rc = bnxt_hwrm_func_reset(bp);
4448 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4452 rc = bnxt_hwrm_queue_qportcfg(bp);
4456 /* Get the MAX capabilities for this function */
4457 rc = bnxt_hwrm_func_qcaps(bp);
4461 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4465 /* Get the adapter error recovery support info */
4466 rc = bnxt_hwrm_error_recovery_qcfg(bp);
4468 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
4470 if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
4471 mtu != bp->eth_dev->data->mtu)
4472 bp->eth_dev->data->mtu = mtu;
4474 bnxt_hwrm_port_led_qcaps(bp);
4480 bnxt_init_locks(struct bnxt *bp)
4484 err = pthread_mutex_init(&bp->flow_lock, NULL);
4486 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4490 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4494 rc = bnxt_init_fw(bp);
4498 if (!reconfig_dev) {
4499 rc = bnxt_setup_mac_addr(bp->eth_dev);
4503 rc = bnxt_restore_dflt_mac(bp);
4508 bnxt_config_vf_req_fwd(bp);
4510 rc = bnxt_hwrm_func_driver_register(bp);
4512 PMD_DRV_LOG(ERR, "Failed to register driver");
4517 if (bp->pdev->max_vfs) {
4518 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4520 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4524 rc = bnxt_hwrm_allocate_pf_only(bp);
4527 "Failed to allocate PF resources");
4533 rc = bnxt_alloc_mem(bp, reconfig_dev);
4537 rc = bnxt_setup_int(bp);
4543 rc = bnxt_request_int(bp);
4547 rc = bnxt_init_locks(bp);
4555 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4557 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4558 static int version_printed;
4562 if (version_printed++ == 0)
4563 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4565 eth_dev->dev_ops = &bnxt_dev_ops;
4566 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4567 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4570 * For secondary processes, we don't initialise any further
4571 * as primary has already done this work.
4573 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4576 rte_eth_copy_pci_info(eth_dev, pci_dev);
4578 bp = eth_dev->data->dev_private;
4580 bp->dev_stopped = 1;
4582 if (bnxt_vf_pciid(pci_dev->id.device_id))
4583 bp->flags |= BNXT_FLAG_VF;
4585 if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
4586 pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
4587 pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
4588 pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 ||
4589 pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2)
4590 bp->flags |= BNXT_FLAG_THOR_CHIP;
4592 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4593 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4594 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4595 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4596 bp->flags |= BNXT_FLAG_STINGRAY;
4598 rc = bnxt_init_board(eth_dev);
4601 "Failed to initialize board rc: %x\n", rc);
4605 rc = bnxt_alloc_hwrm_resources(bp);
4608 "Failed to allocate hwrm resource rc: %x\n", rc);
4611 rc = bnxt_init_resources(bp, false);
4615 rc = bnxt_alloc_stats_mem(bp);
4620 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4621 pci_dev->mem_resource[0].phys_addr,
4622 pci_dev->mem_resource[0].addr);
4627 bnxt_dev_uninit(eth_dev);
4632 bnxt_uninit_locks(struct bnxt *bp)
4634 pthread_mutex_destroy(&bp->flow_lock);
4638 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4643 bnxt_free_mem(bp, reconfig_dev);
4644 bnxt_hwrm_func_buf_unrgtr(bp);
4645 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4646 bp->flags &= ~BNXT_FLAG_REGISTERED;
4647 bnxt_free_ctx_mem(bp);
4648 if (!reconfig_dev) {
4649 bnxt_free_hwrm_resources(bp);
4651 if (bp->recovery_info != NULL) {
4652 rte_free(bp->recovery_info);
4653 bp->recovery_info = NULL;
4657 rte_free(bp->ptp_cfg);
4663 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4665 struct bnxt *bp = eth_dev->data->dev_private;
4668 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4671 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4673 rc = bnxt_uninit_resources(bp, false);
4675 if (bp->grp_info != NULL) {
4676 rte_free(bp->grp_info);
4677 bp->grp_info = NULL;
4680 if (bp->tx_mem_zone) {
4681 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4682 bp->tx_mem_zone = NULL;
4685 if (bp->rx_mem_zone) {
4686 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4687 bp->rx_mem_zone = NULL;
4690 if (bp->dev_stopped == 0)
4691 bnxt_dev_close_op(eth_dev);
4693 rte_free(bp->pf.vf_info);
4694 eth_dev->dev_ops = NULL;
4695 eth_dev->rx_pkt_burst = NULL;
4696 eth_dev->tx_pkt_burst = NULL;
4698 bnxt_uninit_locks(bp);
4703 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4704 struct rte_pci_device *pci_dev)
4706 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4710 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4712 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4713 return rte_eth_dev_pci_generic_remove(pci_dev,
4716 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4719 static struct rte_pci_driver bnxt_rte_pmd = {
4720 .id_table = bnxt_pci_id_map,
4721 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4722 .probe = bnxt_pci_probe,
4723 .remove = bnxt_pci_remove,
4727 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4729 if (strcmp(dev->device->driver->name, drv->driver.name))
4735 bool is_bnxt_supported(struct rte_eth_dev *dev)
4737 return is_device_supported(dev, &bnxt_rte_pmd);
4740 RTE_INIT(bnxt_init_log)
4742 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4743 if (bnxt_logtype_driver >= 0)
4744 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4747 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4748 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4749 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");