drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16
  17 #include "bnxt.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_reps.h"
  22 #include "bnxt_ring.h"
  23 #include "bnxt_rxq.h"
  24 #include "bnxt_rxr.h"
  25 #include "bnxt_stats.h"
  26 #include "bnxt_txq.h"
  27 #include "bnxt_txr.h"
  28 #include "bnxt_vnic.h"
  29 #include "hsi_struct_def_dpdk.h"
  30 #include "bnxt_nvm_defs.h"
  31 #include "bnxt_tf_common.h"
  32 #include "ulp_flow_db.h"
  33
  34 #define DRV_MODULE_NAME         "bnxt"
  35 static const char bnxt_version[] =
  36         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  37
  38 /*
  39  * The set of PCI devices this driver supports
  40  */
  41 static const struct rte_pci_id bnxt_pci_id_map[] = {
  42         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  43                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  95         { .vendor_id = 0, /* sentinel */ },
  96 };
  97
  98 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
  99 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
 100 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
 101 #define BNXT_DEVARG_REPRESENTOR "representor"
 102 #define BNXT_DEVARG_REP_BASED_PF  "rep-based-pf"
 103 #define BNXT_DEVARG_REP_IS_PF  "rep-is-pf"
 104 #define BNXT_DEVARG_REP_Q_R2F  "rep-q-r2f"
 105 #define BNXT_DEVARG_REP_Q_F2R  "rep-q-f2r"
 106 #define BNXT_DEVARG_REP_FC_R2F  "rep-fc-r2f"
 107 #define BNXT_DEVARG_REP_FC_F2R  "rep-fc-f2r"
 108
 109 static const char *const bnxt_dev_args[] = {
 110         BNXT_DEVARG_REPRESENTOR,
 111         BNXT_DEVARG_TRUFLOW,
 112         BNXT_DEVARG_FLOW_XSTAT,
 113         BNXT_DEVARG_MAX_NUM_KFLOWS,
 114         BNXT_DEVARG_REP_BASED_PF,
 115         BNXT_DEVARG_REP_IS_PF,
 116         BNXT_DEVARG_REP_Q_R2F,
 117         BNXT_DEVARG_REP_Q_F2R,
 118         BNXT_DEVARG_REP_FC_R2F,
 119         BNXT_DEVARG_REP_FC_F2R,
 120         NULL
 121 };
 122
 123 /*
 124  * truflow == false to disable the feature
 125  * truflow == true to enable the feature
 126  */
 127 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 128
 129 /*
 130  * flow_xstat == false to disable the feature
 131  * flow_xstat == true to enable the feature
 132  */
 133 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 134
 135 /*
 136  * rep_is_pf == false to indicate VF representor
 137  * rep_is_pf == true to indicate PF representor
 138  */
 139 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)        ((rep_is_pf) > 1)
 140
 141 /*
 142  * rep_based_pf == Physical index of the PF
 143  */
 144 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)  ((rep_based_pf) > 15)
 145 /*
 146  * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
 147  */
 148 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)        ((rep_q_r2f) > 3)
 149
 150 /*
 151  * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
 152  */
 153 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)        ((rep_q_f2r) > 3)
 154
 155 /*
 156  * rep_fc_r2f == Flow control for the representor to endpoint direction
 157  */
 158 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)      ((rep_fc_r2f) > 1)
 159
 160 /*
 161  * rep_fc_f2r == Flow control for the endpoint to representor direction
 162  */
 163 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)      ((rep_fc_f2r) > 1)
 164
 165 /*
 166  * max_num_kflows must be >= 32
 167  * and must be a power-of-2 supported value
 168  * return: 1 -> invalid
 169  *         0 -> valid
 170  */
 171 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 172 {
 173         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 174                 return 1;
 175         return 0;
 176 }
 177
 178 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 179 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 180 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 181 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 182 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 183 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 184 static void bnxt_dev_recover(void *arg);
 185 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 186 static void bnxt_free_rep_info(struct bnxt *bp);
 187
 188 int is_bnxt_in_error(struct bnxt *bp)
 189 {
 190         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 191                 return -EIO;
 192         if (bp->flags & BNXT_FLAG_FW_RESET)
 193                 return -EBUSY;
 194
 195         return 0;
 196 }
 197
 198 /***********************/
 199
 200 /*
 201  * High level utility functions
 202  */
 203
 204 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 205 {
 206         if (!BNXT_CHIP_THOR(bp))
 207                 return 1;
 208
 209         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 210                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 211                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 212 }
 213
 214 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 215 {
 216         if (!BNXT_CHIP_THOR(bp))
 217                 return HW_HASH_INDEX_SIZE;
 218
 219         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 220 }
 221
 222 static void bnxt_free_parent_info(struct bnxt *bp)
 223 {
 224         rte_free(bp->parent);
 225 }
 226
 227 static void bnxt_free_pf_info(struct bnxt *bp)
 228 {
 229         rte_free(bp->pf);
 230 }
 231
 232 static void bnxt_free_link_info(struct bnxt *bp)
 233 {
 234         rte_free(bp->link_info);
 235 }
 236
 237 static void bnxt_free_leds_info(struct bnxt *bp)
 238 {
 239         if (BNXT_VF(bp))
 240                 return;
 241
 242         rte_free(bp->leds);
 243         bp->leds = NULL;
 244 }
 245
 246 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 247 {
 248         rte_free(bp->flow_stat);
 249         bp->flow_stat = NULL;
 250 }
 251
 252 static void bnxt_free_cos_queues(struct bnxt *bp)
 253 {
 254         rte_free(bp->rx_cos_queue);
 255         rte_free(bp->tx_cos_queue);
 256 }
 257
 258 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 259 {
 260         bnxt_free_filter_mem(bp);
 261         bnxt_free_vnic_attributes(bp);
 262         bnxt_free_vnic_mem(bp);
 263
 264         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 265          * If the number of rings change across fw update,
 266          * we don't have much choice except to warn the user.
 267          */
 268         if (!reconfig) {
 269                 bnxt_free_stats(bp);
 270                 bnxt_free_tx_rings(bp);
 271                 bnxt_free_rx_rings(bp);
 272         }
 273         bnxt_free_async_cp_ring(bp);
 274         bnxt_free_rxtx_nq_ring(bp);
 275
 276         rte_free(bp->grp_info);
 277         bp->grp_info = NULL;
 278 }
 279
 280 static int bnxt_alloc_parent_info(struct bnxt *bp)
 281 {
 282         bp->parent = rte_zmalloc("bnxt_parent_info",
 283                                  sizeof(struct bnxt_parent_info), 0);
 284         if (bp->parent == NULL)
 285                 return -ENOMEM;
 286
 287         return 0;
 288 }
 289
 290 static int bnxt_alloc_pf_info(struct bnxt *bp)
 291 {
 292         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 293         if (bp->pf == NULL)
 294                 return -ENOMEM;
 295
 296         return 0;
 297 }
 298
 299 static int bnxt_alloc_link_info(struct bnxt *bp)
 300 {
 301         bp->link_info =
 302                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 303         if (bp->link_info == NULL)
 304                 return -ENOMEM;
 305
 306         return 0;
 307 }
 308
 309 static int bnxt_alloc_leds_info(struct bnxt *bp)
 310 {
 311         if (BNXT_VF(bp))
 312                 return 0;
 313
 314         bp->leds = rte_zmalloc("bnxt_leds",
 315                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 316                                0);
 317         if (bp->leds == NULL)
 318                 return -ENOMEM;
 319
 320         return 0;
 321 }
 322
 323 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 324 {
 325         bp->rx_cos_queue =
 326                 rte_zmalloc("bnxt_rx_cosq",
 327                             BNXT_COS_QUEUE_COUNT *
 328                             sizeof(struct bnxt_cos_queue_info),
 329                             0);
 330         if (bp->rx_cos_queue == NULL)
 331                 return -ENOMEM;
 332
 333         bp->tx_cos_queue =
 334                 rte_zmalloc("bnxt_tx_cosq",
 335                             BNXT_COS_QUEUE_COUNT *
 336                             sizeof(struct bnxt_cos_queue_info),
 337                             0);
 338         if (bp->tx_cos_queue == NULL)
 339                 return -ENOMEM;
 340
 341         return 0;
 342 }
 343
 344 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 345 {
 346         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 347                                     sizeof(struct bnxt_flow_stat_info), 0);
 348         if (bp->flow_stat == NULL)
 349                 return -ENOMEM;
 350
 351         return 0;
 352 }
 353
 354 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 355 {
 356         int rc;
 357
 358         rc = bnxt_alloc_ring_grps(bp);
 359         if (rc)
 360                 goto alloc_mem_err;
 361
 362         rc = bnxt_alloc_async_ring_struct(bp);
 363         if (rc)
 364                 goto alloc_mem_err;
 365
 366         rc = bnxt_alloc_vnic_mem(bp);
 367         if (rc)
 368                 goto alloc_mem_err;
 369
 370         rc = bnxt_alloc_vnic_attributes(bp);
 371         if (rc)
 372                 goto alloc_mem_err;
 373
 374         rc = bnxt_alloc_filter_mem(bp);
 375         if (rc)
 376                 goto alloc_mem_err;
 377
 378         rc = bnxt_alloc_async_cp_ring(bp);
 379         if (rc)
 380                 goto alloc_mem_err;
 381
 382         rc = bnxt_alloc_rxtx_nq_ring(bp);
 383         if (rc)
 384                 goto alloc_mem_err;
 385
 386         if (BNXT_FLOW_XSTATS_EN(bp)) {
 387                 rc = bnxt_alloc_flow_stats_info(bp);
 388                 if (rc)
 389                         goto alloc_mem_err;
 390         }
 391
 392         return 0;
 393
 394 alloc_mem_err:
 395         bnxt_free_mem(bp, reconfig);
 396         return rc;
 397 }
 398
 399 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 400 {
 401         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 402         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 403         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 404         struct bnxt_rx_queue *rxq;
 405         unsigned int j;
 406         int rc;
 407
 408         rc = bnxt_vnic_grp_alloc(bp, vnic);
 409         if (rc)
 410                 goto err_out;
 411
 412         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 413                     vnic_id, vnic, vnic->fw_grp_ids);
 414
 415         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 416         if (rc)
 417                 goto err_out;
 418
 419         /* Alloc RSS context only if RSS mode is enabled */
 420         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 421                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 422
 423                 rc = 0;
 424                 for (j = 0; j < nr_ctxs; j++) {
 425                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 426                         if (rc)
 427                                 break;
 428                 }
 429                 if (rc) {
 430                         PMD_DRV_LOG(ERR,
 431                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 432                                     vnic_id, j, rc);
 433                         goto err_out;
 434                 }
 435                 vnic->num_lb_ctxts = nr_ctxs;
 436         }
 437
 438         /*
 439          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 440          * setting is not available at this time, it will not be
 441          * configured correctly in the CFA.
 442          */
 443         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 444                 vnic->vlan_strip = true;
 445         else
 446                 vnic->vlan_strip = false;
 447
 448         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 449         if (rc)
 450                 goto err_out;
 451
 452         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 453         if (rc)
 454                 goto err_out;
 455
 456         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 457                 rxq = bp->eth_dev->data->rx_queues[j];
 458
 459                 PMD_DRV_LOG(DEBUG,
 460                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 461                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 462
 463                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 464                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 465                 else
 466                         vnic->rx_queue_cnt++;
 467         }
 468
 469         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 470
 471         rc = bnxt_vnic_rss_configure(bp, vnic);
 472         if (rc)
 473                 goto err_out;
 474
 475         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 476
 477         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 478                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 479         else
 480                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 481
 482         return 0;
 483 err_out:
 484         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 485                     vnic_id, rc);
 486         return rc;
 487 }
 488
 489 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 490 {
 491         int rc = 0;
 492
 493         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 494                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 495         if (rc)
 496                 return rc;
 497
 498         PMD_DRV_LOG(DEBUG,
 499                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 500                     " rx_fc_in_tbl.ctx_id = %d\n",
 501                     bp->flow_stat->rx_fc_in_tbl.va,
 502                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 503                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 504
 505         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 506                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 507         if (rc)
 508                 return rc;
 509
 510         PMD_DRV_LOG(DEBUG,
 511                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 512                     " rx_fc_out_tbl.ctx_id = %d\n",
 513                     bp->flow_stat->rx_fc_out_tbl.va,
 514                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 515                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 516
 517         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 518                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 519         if (rc)
 520                 return rc;
 521
 522         PMD_DRV_LOG(DEBUG,
 523                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 524                     " tx_fc_in_tbl.ctx_id = %d\n",
 525                     bp->flow_stat->tx_fc_in_tbl.va,
 526                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 527                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 528
 529         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 530                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 531         if (rc)
 532                 return rc;
 533
 534         PMD_DRV_LOG(DEBUG,
 535                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 536                     " tx_fc_out_tbl.ctx_id = %d\n",
 537                     bp->flow_stat->tx_fc_out_tbl.va,
 538                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 539                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 540
 541         memset(bp->flow_stat->rx_fc_out_tbl.va,
 542                0,
 543                bp->flow_stat->rx_fc_out_tbl.size);
 544         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 545                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 546                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 547                                        bp->flow_stat->max_fc,
 548                                        true);
 549         if (rc)
 550                 return rc;
 551
 552         memset(bp->flow_stat->tx_fc_out_tbl.va,
 553                0,
 554                bp->flow_stat->tx_fc_out_tbl.size);
 555         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 556                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 557                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 558                                        bp->flow_stat->max_fc,
 559                                        true);
 560
 561         return rc;
 562 }
 563
 564 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 565                                   struct bnxt_ctx_mem_buf_info *ctx)
 566 {
 567         if (!ctx)
 568                 return -EINVAL;
 569
 570         ctx->va = rte_zmalloc(type, size, 0);
 571         if (ctx->va == NULL)
 572                 return -ENOMEM;
 573         rte_mem_lock_page(ctx->va);
 574         ctx->size = size;
 575         ctx->dma = rte_mem_virt2iova(ctx->va);
 576         if (ctx->dma == RTE_BAD_IOVA)
 577                 return -ENOMEM;
 578
 579         return 0;
 580 }
 581
 582 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 583 {
 584         struct rte_pci_device *pdev = bp->pdev;
 585         char type[RTE_MEMZONE_NAMESIZE];
 586         uint16_t max_fc;
 587         int rc = 0;
 588
 589         max_fc = bp->flow_stat->max_fc;
 590
 591         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 592                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 593         /* 4 bytes for each counter-id */
 594         rc = bnxt_alloc_ctx_mem_buf(type,
 595                                     max_fc * 4,
 596                                     &bp->flow_stat->rx_fc_in_tbl);
 597         if (rc)
 598                 return rc;
 599
 600         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 601                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 602         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 603         rc = bnxt_alloc_ctx_mem_buf(type,
 604                                     max_fc * 16,
 605                                     &bp->flow_stat->rx_fc_out_tbl);
 606         if (rc)
 607                 return rc;
 608
 609         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 610                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 611         /* 4 bytes for each counter-id */
 612         rc = bnxt_alloc_ctx_mem_buf(type,
 613                                     max_fc * 4,
 614                                     &bp->flow_stat->tx_fc_in_tbl);
 615         if (rc)
 616                 return rc;
 617
 618         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 619                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 620         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 621         rc = bnxt_alloc_ctx_mem_buf(type,
 622                                     max_fc * 16,
 623                                     &bp->flow_stat->tx_fc_out_tbl);
 624         if (rc)
 625                 return rc;
 626
 627         rc = bnxt_register_fc_ctx_mem(bp);
 628
 629         return rc;
 630 }
 631
 632 static int bnxt_init_ctx_mem(struct bnxt *bp)
 633 {
 634         int rc = 0;
 635
 636         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 637             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 638             !BNXT_FLOW_XSTATS_EN(bp))
 639                 return 0;
 640
 641         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 642         if (rc)
 643                 return rc;
 644
 645         rc = bnxt_init_fc_ctx_mem(bp);
 646
 647         return rc;
 648 }
 649
 650 static int bnxt_update_phy_setting(struct bnxt *bp)
 651 {
 652         struct rte_eth_link new;
 653         int rc;
 654
 655         rc = bnxt_get_hwrm_link_config(bp, &new);
 656         if (rc) {
 657                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 658                 return rc;
 659         }
 660
 661         /*
 662          * On BCM957508-N2100 adapters, FW will not allow any user other
 663          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 664          * always returns link up. Force phy update always in that case.
 665          */
 666         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 667                 rc = bnxt_set_hwrm_link_config(bp, true);
 668                 if (rc) {
 669                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 670                         return rc;
 671                 }
 672         }
 673
 674         return rc;
 675 }
 676
 677 static int bnxt_init_chip(struct bnxt *bp)
 678 {
 679         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 680         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 681         uint32_t intr_vector = 0;
 682         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 683         uint32_t vec = BNXT_MISC_VEC_ID;
 684         unsigned int i, j;
 685         int rc;
 686
 687         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 688                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 689                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 690                 bp->flags |= BNXT_FLAG_JUMBO;
 691         } else {
 692                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 693                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 694                 bp->flags &= ~BNXT_FLAG_JUMBO;
 695         }
 696
 697         /* THOR does not support ring groups.
 698          * But we will use the array to save RSS context IDs.
 699          */
 700         if (BNXT_CHIP_THOR(bp))
 701                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 702
 703         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 704         if (rc) {
 705                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 706                 goto err_out;
 707         }
 708
 709         rc = bnxt_alloc_hwrm_rings(bp);
 710         if (rc) {
 711                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 712                 goto err_out;
 713         }
 714
 715         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 716         if (rc) {
 717                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 718                 goto err_out;
 719         }
 720
 721         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 722                 goto skip_cosq_cfg;
 723
 724         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 725                 if (bp->rx_cos_queue[i].id != 0xff) {
 726                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 727
 728                         if (!vnic) {
 729                                 PMD_DRV_LOG(ERR,
 730                                             "Num pools more than FW profile\n");
 731                                 rc = -EINVAL;
 732                                 goto err_out;
 733                         }
 734                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 735                         bp->rx_cosq_cnt++;
 736                 }
 737         }
 738
 739 skip_cosq_cfg:
 740         rc = bnxt_mq_rx_configure(bp);
 741         if (rc) {
 742                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 743                 goto err_out;
 744         }
 745
 746         /* VNIC configuration */
 747         for (i = 0; i < bp->nr_vnics; i++) {
 748                 rc = bnxt_setup_one_vnic(bp, i);
 749                 if (rc)
 750                         goto err_out;
 751         }
 752
 753         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 754         if (rc) {
 755                 PMD_DRV_LOG(ERR,
 756                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 757                 goto err_out;
 758         }
 759
 760         /* check and configure queue intr-vector mapping */
 761         if ((rte_intr_cap_multiple(intr_handle) ||
 762              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 763             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 764                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 765                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 766                 if (intr_vector > bp->rx_cp_nr_rings) {
 767                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 768                                         bp->rx_cp_nr_rings);
 769                         return -ENOTSUP;
 770                 }
 771                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 772                 if (rc)
 773                         return rc;
 774         }
 775
 776         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 777                 intr_handle->intr_vec =
 778                         rte_zmalloc("intr_vec",
 779                                     bp->eth_dev->data->nb_rx_queues *
 780                                     sizeof(int), 0);
 781                 if (intr_handle->intr_vec == NULL) {
 782                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 783                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 784                         rc = -ENOMEM;
 785                         goto err_disable;
 786                 }
 787                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 788                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 789                          intr_handle->intr_vec, intr_handle->nb_efd,
 790                         intr_handle->max_intr);
 791                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 792                      queue_id++) {
 793                         intr_handle->intr_vec[queue_id] =
 794                                                         vec + BNXT_RX_VEC_START;
 795                         if (vec < base + intr_handle->nb_efd - 1)
 796                                 vec++;
 797                 }
 798         }
 799
 800         /* enable uio/vfio intr/eventfd mapping */
 801         rc = rte_intr_enable(intr_handle);
 802 #ifndef RTE_EXEC_ENV_FREEBSD
 803         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 804         if (rc)
 805                 goto err_free;
 806 #endif
 807
 808         rc = bnxt_update_phy_setting(bp);
 809         if (rc)
 810                 goto err_free;
 811
 812         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 813         if (!bp->mark_table)
 814                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 815
 816         return 0;
 817
 818 err_free:
 819         rte_free(intr_handle->intr_vec);
 820 err_disable:
 821         rte_intr_efd_disable(intr_handle);
 822 err_out:
 823         /* Some of the error status returned by FW may not be from errno.h */
 824         if (rc > 0)
 825                 rc = -EIO;
 826
 827         return rc;
 828 }
 829
 830 static int bnxt_shutdown_nic(struct bnxt *bp)
 831 {
 832         bnxt_free_all_hwrm_resources(bp);
 833         bnxt_free_all_filters(bp);
 834         bnxt_free_all_vnics(bp);
 835         return 0;
 836 }
 837
 838 /*
 839  * Device configuration and status function
 840  */
 841
 842 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 843 {
 844         uint32_t link_speed = bp->link_info->support_speeds;
 845         uint32_t speed_capa = 0;
 846
 847         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 848                 speed_capa |= ETH_LINK_SPEED_100M;
 849         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 850                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 851         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 852                 speed_capa |= ETH_LINK_SPEED_1G;
 853         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 854                 speed_capa |= ETH_LINK_SPEED_2_5G;
 855         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 856                 speed_capa |= ETH_LINK_SPEED_10G;
 857         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 858                 speed_capa |= ETH_LINK_SPEED_20G;
 859         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 860                 speed_capa |= ETH_LINK_SPEED_25G;
 861         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 862                 speed_capa |= ETH_LINK_SPEED_40G;
 863         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 864                 speed_capa |= ETH_LINK_SPEED_50G;
 865         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 866                 speed_capa |= ETH_LINK_SPEED_100G;
 867         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
 868                 speed_capa |= ETH_LINK_SPEED_50G;
 869         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
 870                 speed_capa |= ETH_LINK_SPEED_100G;
 871         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
 872                 speed_capa |= ETH_LINK_SPEED_200G;
 873
 874         if (bp->link_info->auto_mode ==
 875             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 876                 speed_capa |= ETH_LINK_SPEED_FIXED;
 877         else
 878                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 879
 880         return speed_capa;
 881 }
 882
 883 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 884                                 struct rte_eth_dev_info *dev_info)
 885 {
 886         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 887         struct bnxt *bp = eth_dev->data->dev_private;
 888         uint16_t max_vnics, i, j, vpool, vrxq;
 889         unsigned int max_rx_rings;
 890         int rc;
 891
 892         rc = is_bnxt_in_error(bp);
 893         if (rc)
 894                 return rc;
 895
 896         /* MAC Specifics */
 897         dev_info->max_mac_addrs = bp->max_l2_ctx;
 898         dev_info->max_hash_mac_addrs = 0;
 899
 900         /* PF/VF specifics */
 901         if (BNXT_PF(bp))
 902                 dev_info->max_vfs = pdev->max_vfs;
 903
 904         max_rx_rings = BNXT_MAX_RINGS(bp);
 905         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 906         dev_info->max_rx_queues = max_rx_rings;
 907         dev_info->max_tx_queues = max_rx_rings;
 908         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 909         dev_info->hash_key_size = 40;
 910         max_vnics = bp->max_vnics;
 911
 912         /* MTU specifics */
 913         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 914         dev_info->max_mtu = BNXT_MAX_MTU;
 915
 916         /* Fast path specifics */
 917         dev_info->min_rx_bufsize = 1;
 918         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 919
 920         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 921         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 922                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 923         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 924         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 925
 926         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 927
 928         /* *INDENT-OFF* */
 929         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 930                 .rx_thresh = {
 931                         .pthresh = 8,
 932                         .hthresh = 8,
 933                         .wthresh = 0,
 934                 },
 935                 .rx_free_thresh = 32,
 936                 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
 937         };
 938
 939         dev_info->default_txconf = (struct rte_eth_txconf) {
 940                 .tx_thresh = {
 941                         .pthresh = 32,
 942                         .hthresh = 0,
 943                         .wthresh = 0,
 944                 },
 945                 .tx_free_thresh = 32,
 946                 .tx_rs_thresh = 32,
 947         };
 948         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 949
 950         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 951         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 952         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 953         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 954         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 955
 956         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
 957                 dev_info->switch_info.name = eth_dev->device->name;
 958                 dev_info->switch_info.domain_id = bp->switch_domain_id;
 959                 dev_info->switch_info.port_id =
 960                                 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
 961                                     BNXT_SWITCH_PORT_ID_TRUSTED_VF;
 962         }
 963
 964         /* *INDENT-ON* */
 965
 966         /*
 967          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 968          *       need further investigation.
 969          */
 970
 971         /* VMDq resources */
 972         vpool = 64; /* ETH_64_POOLS */
 973         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 974         for (i = 0; i < 4; vpool >>= 1, i++) {
 975                 if (max_vnics > vpool) {
 976                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 977                                 if (dev_info->max_rx_queues > vrxq) {
 978                                         if (vpool > vrxq)
 979                                                 vpool = vrxq;
 980                                         goto found;
 981                                 }
 982                         }
 983                         /* Not enough resources to support VMDq */
 984                         break;
 985                 }
 986         }
 987         /* Not enough resources to support VMDq */
 988         vpool = 0;
 989         vrxq = 0;
 990 found:
 991         dev_info->max_vmdq_pools = vpool;
 992         dev_info->vmdq_queue_num = vrxq;
 993
 994         dev_info->vmdq_pool_base = 0;
 995         dev_info->vmdq_queue_base = 0;
 996
 997         return 0;
 998 }
 999
1000 /* Configure the device based on the configuration provided */
1001 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1002 {
1003         struct bnxt *bp = eth_dev->data->dev_private;
1004         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1005         int rc;
1006
1007         bp->rx_queues = (void *)eth_dev->data->rx_queues;
1008         bp->tx_queues = (void *)eth_dev->data->tx_queues;
1009         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1010         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1011
1012         rc = is_bnxt_in_error(bp);
1013         if (rc)
1014                 return rc;
1015
1016         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1017                 rc = bnxt_hwrm_check_vf_rings(bp);
1018                 if (rc) {
1019                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1020                         return -ENOSPC;
1021                 }
1022
1023                 /* If a resource has already been allocated - in this case
1024                  * it is the async completion ring, free it. Reallocate it after
1025                  * resource reservation. This will ensure the resource counts
1026                  * are calculated correctly.
1027                  */
1028
1029                 pthread_mutex_lock(&bp->def_cp_lock);
1030
1031                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1032                         bnxt_disable_int(bp);
1033                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
1034                 }
1035
1036                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1037                 if (rc) {
1038                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1039                         pthread_mutex_unlock(&bp->def_cp_lock);
1040                         return -ENOSPC;
1041                 }
1042
1043                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1044                         rc = bnxt_alloc_async_cp_ring(bp);
1045                         if (rc) {
1046                                 pthread_mutex_unlock(&bp->def_cp_lock);
1047                                 return rc;
1048                         }
1049                         bnxt_enable_int(bp);
1050                 }
1051
1052                 pthread_mutex_unlock(&bp->def_cp_lock);
1053         } else {
1054                 /* legacy driver needs to get updated values */
1055                 rc = bnxt_hwrm_func_qcaps(bp);
1056                 if (rc) {
1057                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
1058                         return rc;
1059                 }
1060         }
1061
1062         /* Inherit new configurations */
1063         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1064             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1065             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1066                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1067             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1068             bp->max_stat_ctx)
1069                 goto resource_error;
1070
1071         if (BNXT_HAS_RING_GRPS(bp) &&
1072             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1073                 goto resource_error;
1074
1075         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1076             bp->max_vnics < eth_dev->data->nb_rx_queues)
1077                 goto resource_error;
1078
1079         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1080         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1081
1082         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1083                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1084         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1085
1086         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1087                 eth_dev->data->mtu =
1088                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1089                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1090                         BNXT_NUM_VLANS;
1091                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1092         }
1093         return 0;
1094
1095 resource_error:
1096         PMD_DRV_LOG(ERR,
1097                     "Insufficient resources to support requested config\n");
1098         PMD_DRV_LOG(ERR,
1099                     "Num Queues Requested: Tx %d, Rx %d\n",
1100                     eth_dev->data->nb_tx_queues,
1101                     eth_dev->data->nb_rx_queues);
1102         PMD_DRV_LOG(ERR,
1103                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1104                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1105                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1106         return -ENOSPC;
1107 }
1108
1109 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1110 {
1111         struct rte_eth_link *link = &eth_dev->data->dev_link;
1112
1113         if (link->link_status)
1114                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1115                         eth_dev->data->port_id,
1116                         (uint32_t)link->link_speed,
1117                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1118                         ("full-duplex") : ("half-duplex\n"));
1119         else
1120                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1121                         eth_dev->data->port_id);
1122 }
1123
1124 /*
1125  * Determine whether the current configuration requires support for scattered
1126  * receive; return 1 if scattered receive is required and 0 if not.
1127  */
1128 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1129 {
1130         uint16_t buf_size;
1131         int i;
1132
1133         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1134                 return 1;
1135
1136         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1137                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1138
1139                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1140                                       RTE_PKTMBUF_HEADROOM);
1141                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1142                         return 1;
1143         }
1144         return 0;
1145 }
1146
1147 static eth_rx_burst_t
1148 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1149 {
1150         struct bnxt *bp = eth_dev->data->dev_private;
1151
1152 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1153 #ifndef RTE_LIBRTE_IEEE1588
1154         /*
1155          * Vector mode receive can be enabled only if scatter rx is not
1156          * in use and rx offloads are limited to VLAN stripping and
1157          * CRC stripping.
1158          */
1159         if (!eth_dev->data->scattered_rx &&
1160             !(eth_dev->data->dev_conf.rxmode.offloads &
1161               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1162                 DEV_RX_OFFLOAD_KEEP_CRC |
1163                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1164                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1165                 DEV_RX_OFFLOAD_UDP_CKSUM |
1166                 DEV_RX_OFFLOAD_TCP_CKSUM |
1167                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1168                 DEV_RX_OFFLOAD_RSS_HASH |
1169                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1170             !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp)) {
1171                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1172                             eth_dev->data->port_id);
1173                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1174                 return bnxt_recv_pkts_vec;
1175         }
1176         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1177                     eth_dev->data->port_id);
1178         PMD_DRV_LOG(INFO,
1179                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1180                     eth_dev->data->port_id,
1181                     eth_dev->data->scattered_rx,
1182                     eth_dev->data->dev_conf.rxmode.offloads);
1183 #endif
1184 #endif
1185         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1186         return bnxt_recv_pkts;
1187 }
1188
1189 static eth_tx_burst_t
1190 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1191 {
1192 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1193 #ifndef RTE_LIBRTE_IEEE1588
1194         struct bnxt *bp = eth_dev->data->dev_private;
1195
1196         /*
1197          * Vector mode transmit can be enabled only if not using scatter rx
1198          * or tx offloads.
1199          */
1200         if (!eth_dev->data->scattered_rx &&
1201             !eth_dev->data->dev_conf.txmode.offloads &&
1202             !BNXT_TRUFLOW_EN(bp)) {
1203                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1204                             eth_dev->data->port_id);
1205                 return bnxt_xmit_pkts_vec;
1206         }
1207         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1208                     eth_dev->data->port_id);
1209         PMD_DRV_LOG(INFO,
1210                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1211                     eth_dev->data->port_id,
1212                     eth_dev->data->scattered_rx,
1213                     eth_dev->data->dev_conf.txmode.offloads);
1214 #endif
1215 #endif
1216         return bnxt_xmit_pkts;
1217 }
1218
1219 static int bnxt_handle_if_change_status(struct bnxt *bp)
1220 {
1221         int rc;
1222
1223         /* Since fw has undergone a reset and lost all contexts,
1224          * set fatal flag to not issue hwrm during cleanup
1225          */
1226         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1227         bnxt_uninit_resources(bp, true);
1228
1229         /* clear fatal flag so that re-init happens */
1230         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1231         rc = bnxt_init_resources(bp, true);
1232
1233         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1234
1235         return rc;
1236 }
1237
1238 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1239 {
1240         struct bnxt *bp = eth_dev->data->dev_private;
1241         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1242         int vlan_mask = 0;
1243         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1244
1245         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1246                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1247                 return -EINVAL;
1248         }
1249
1250         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1251                 PMD_DRV_LOG(ERR,
1252                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1253                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1254         }
1255
1256         do {
1257                 rc = bnxt_hwrm_if_change(bp, true);
1258                 if (rc == 0 || rc != -EAGAIN)
1259                         break;
1260
1261                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1262         } while (retry_cnt--);
1263
1264         if (rc)
1265                 return rc;
1266
1267         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1268                 rc = bnxt_handle_if_change_status(bp);
1269                 if (rc)
1270                         return rc;
1271         }
1272
1273         bnxt_enable_int(bp);
1274
1275         rc = bnxt_init_chip(bp);
1276         if (rc)
1277                 goto error;
1278
1279         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1280         eth_dev->data->dev_started = 1;
1281
1282         bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1283
1284         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1285                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1286         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1287                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1288         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1289         if (rc)
1290                 goto error;
1291
1292         /* Initialize bnxt ULP port details */
1293         rc = bnxt_ulp_port_init(bp);
1294         if (rc)
1295                 goto error;
1296
1297         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1298         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1299
1300         bnxt_schedule_fw_health_check(bp);
1301
1302         return 0;
1303
1304 error:
1305         bnxt_shutdown_nic(bp);
1306         bnxt_free_tx_mbufs(bp);
1307         bnxt_free_rx_mbufs(bp);
1308         bnxt_hwrm_if_change(bp, false);
1309         eth_dev->data->dev_started = 0;
1310         return rc;
1311 }
1312
1313 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1314 {
1315         struct bnxt *bp = eth_dev->data->dev_private;
1316         int rc = 0;
1317
1318         if (!bp->link_info->link_up)
1319                 rc = bnxt_set_hwrm_link_config(bp, true);
1320         if (!rc)
1321                 eth_dev->data->dev_link.link_status = 1;
1322
1323         bnxt_print_link_info(eth_dev);
1324         return rc;
1325 }
1326
1327 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1328 {
1329         struct bnxt *bp = eth_dev->data->dev_private;
1330
1331         eth_dev->data->dev_link.link_status = 0;
1332         bnxt_set_hwrm_link_config(bp, false);
1333         bp->link_info->link_up = 0;
1334
1335         return 0;
1336 }
1337
1338 static void bnxt_free_switch_domain(struct bnxt *bp)
1339 {
1340         if (bp->switch_domain_id)
1341                 rte_eth_switch_domain_free(bp->switch_domain_id);
1342 }
1343
1344 /* Unload the driver, release resources */
1345 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1346 {
1347         struct bnxt *bp = eth_dev->data->dev_private;
1348         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1349         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1350
1351         eth_dev->data->dev_started = 0;
1352         eth_dev->data->scattered_rx = 0;
1353
1354         /* Prevent crashes when queues are still in use */
1355         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1356         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1357
1358         bnxt_disable_int(bp);
1359
1360         /* disable uio/vfio intr/eventfd mapping */
1361         rte_intr_disable(intr_handle);
1362
1363         /* Stop the child representors for this device */
1364         bnxt_rep_stop_all(bp);
1365
1366         /* delete the bnxt ULP port details */
1367         bnxt_ulp_port_deinit(bp);
1368
1369         bnxt_cancel_fw_health_check(bp);
1370
1371         /* Do not bring link down during reset recovery */
1372         if (!is_bnxt_in_error(bp))
1373                 bnxt_dev_set_link_down_op(eth_dev);
1374
1375         /* Wait for link to be reset and the async notification to process.
1376          * During reset recovery, there is no need to wait and
1377          * VF/NPAR functions do not have privilege to change PHY config.
1378          */
1379         if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1380                 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1381
1382         /* Clean queue intr-vector mapping */
1383         rte_intr_efd_disable(intr_handle);
1384         if (intr_handle->intr_vec != NULL) {
1385                 rte_free(intr_handle->intr_vec);
1386                 intr_handle->intr_vec = NULL;
1387         }
1388
1389         bnxt_hwrm_port_clr_stats(bp);
1390         bnxt_free_tx_mbufs(bp);
1391         bnxt_free_rx_mbufs(bp);
1392         /* Process any remaining notifications in default completion queue */
1393         bnxt_int_handler(eth_dev);
1394         bnxt_shutdown_nic(bp);
1395         bnxt_hwrm_if_change(bp, false);
1396
1397         rte_free(bp->mark_table);
1398         bp->mark_table = NULL;
1399
1400         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1401         bp->rx_cosq_cnt = 0;
1402         /* All filters are deleted on a port stop. */
1403         if (BNXT_FLOW_XSTATS_EN(bp))
1404                 bp->flow_stat->flow_count = 0;
1405 }
1406
1407 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1408 {
1409         struct bnxt *bp = eth_dev->data->dev_private;
1410
1411         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1412                 return 0;
1413
1414         /* cancel the recovery handler before remove dev */
1415         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1416         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1417         bnxt_cancel_fc_thread(bp);
1418
1419         if (eth_dev->data->dev_started)
1420                 bnxt_dev_stop_op(eth_dev);
1421
1422         bnxt_free_switch_domain(bp);
1423
1424         bnxt_uninit_resources(bp, false);
1425
1426         bnxt_free_leds_info(bp);
1427         bnxt_free_cos_queues(bp);
1428         bnxt_free_link_info(bp);
1429         bnxt_free_pf_info(bp);
1430         bnxt_free_parent_info(bp);
1431
1432         eth_dev->dev_ops = NULL;
1433         eth_dev->rx_pkt_burst = NULL;
1434         eth_dev->tx_pkt_burst = NULL;
1435
1436         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1437         bp->tx_mem_zone = NULL;
1438         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1439         bp->rx_mem_zone = NULL;
1440
1441         bnxt_hwrm_free_vf_info(bp);
1442
1443         rte_free(bp->grp_info);
1444         bp->grp_info = NULL;
1445
1446         return 0;
1447 }
1448
1449 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1450                                     uint32_t index)
1451 {
1452         struct bnxt *bp = eth_dev->data->dev_private;
1453         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1454         struct bnxt_vnic_info *vnic;
1455         struct bnxt_filter_info *filter, *temp_filter;
1456         uint32_t i;
1457
1458         if (is_bnxt_in_error(bp))
1459                 return;
1460
1461         /*
1462          * Loop through all VNICs from the specified filter flow pools to
1463          * remove the corresponding MAC addr filter
1464          */
1465         for (i = 0; i < bp->nr_vnics; i++) {
1466                 if (!(pool_mask & (1ULL << i)))
1467                         continue;
1468
1469                 vnic = &bp->vnic_info[i];
1470                 filter = STAILQ_FIRST(&vnic->filter);
1471                 while (filter) {
1472                         temp_filter = STAILQ_NEXT(filter, next);
1473                         if (filter->mac_index == index) {
1474                                 STAILQ_REMOVE(&vnic->filter, filter,
1475                                                 bnxt_filter_info, next);
1476                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1477                                 bnxt_free_filter(bp, filter);
1478                         }
1479                         filter = temp_filter;
1480                 }
1481         }
1482 }
1483
1484 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1485                                struct rte_ether_addr *mac_addr, uint32_t index,
1486                                uint32_t pool)
1487 {
1488         struct bnxt_filter_info *filter;
1489         int rc = 0;
1490
1491         /* Attach requested MAC address to the new l2_filter */
1492         STAILQ_FOREACH(filter, &vnic->filter, next) {
1493                 if (filter->mac_index == index) {
1494                         PMD_DRV_LOG(DEBUG,
1495                                     "MAC addr already existed for pool %d\n",
1496                                     pool);
1497                         return 0;
1498                 }
1499         }
1500
1501         filter = bnxt_alloc_filter(bp);
1502         if (!filter) {
1503                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1504                 return -ENODEV;
1505         }
1506
1507         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1508          * if the MAC that's been programmed now is a different one, then,
1509          * copy that addr to filter->l2_addr
1510          */
1511         if (mac_addr)
1512                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1513         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1514
1515         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1516         if (!rc) {
1517                 filter->mac_index = index;
1518                 if (filter->mac_index == 0)
1519                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1520                 else
1521                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1522         } else {
1523                 bnxt_free_filter(bp, filter);
1524         }
1525
1526         return rc;
1527 }
1528
1529 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1530                                 struct rte_ether_addr *mac_addr,
1531                                 uint32_t index, uint32_t pool)
1532 {
1533         struct bnxt *bp = eth_dev->data->dev_private;
1534         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1535         int rc = 0;
1536
1537         rc = is_bnxt_in_error(bp);
1538         if (rc)
1539                 return rc;
1540
1541         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1542                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1543                 return -ENOTSUP;
1544         }
1545
1546         if (!vnic) {
1547                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1548                 return -EINVAL;
1549         }
1550
1551         /* Filter settings will get applied when port is started */
1552         if (!eth_dev->data->dev_started)
1553                 return 0;
1554
1555         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1556
1557         return rc;
1558 }
1559
1560 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1561                      bool exp_link_status)
1562 {
1563         int rc = 0;
1564         struct bnxt *bp = eth_dev->data->dev_private;
1565         struct rte_eth_link new;
1566         int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1567                   BNXT_LINK_DOWN_WAIT_CNT;
1568
1569         rc = is_bnxt_in_error(bp);
1570         if (rc)
1571                 return rc;
1572
1573         memset(&new, 0, sizeof(new));
1574         do {
1575                 /* Retrieve link info from hardware */
1576                 rc = bnxt_get_hwrm_link_config(bp, &new);
1577                 if (rc) {
1578                         new.link_speed = ETH_LINK_SPEED_100M;
1579                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1580                         PMD_DRV_LOG(ERR,
1581                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1582                         goto out;
1583                 }
1584
1585                 if (!wait_to_complete || new.link_status == exp_link_status)
1586                         break;
1587
1588                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1589         } while (cnt--);
1590
1591 out:
1592         /* Timed out or success */
1593         if (new.link_status != eth_dev->data->dev_link.link_status ||
1594         new.link_speed != eth_dev->data->dev_link.link_speed) {
1595                 rte_eth_linkstatus_set(eth_dev, &new);
1596
1597                 rte_eth_dev_callback_process(eth_dev,
1598                                              RTE_ETH_EVENT_INTR_LSC,
1599                                              NULL);
1600
1601                 bnxt_print_link_info(eth_dev);
1602         }
1603
1604         return rc;
1605 }
1606
1607 int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1608                         int wait_to_complete)
1609 {
1610         return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1611 }
1612
1613 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1614 {
1615         struct bnxt *bp = eth_dev->data->dev_private;
1616         struct bnxt_vnic_info *vnic;
1617         uint32_t old_flags;
1618         int rc;
1619
1620         rc = is_bnxt_in_error(bp);
1621         if (rc)
1622                 return rc;
1623
1624         /* Filter settings will get applied when port is started */
1625         if (!eth_dev->data->dev_started)
1626                 return 0;
1627
1628         if (bp->vnic_info == NULL)
1629                 return 0;
1630
1631         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1632
1633         old_flags = vnic->flags;
1634         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1635         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1636         if (rc != 0)
1637                 vnic->flags = old_flags;
1638
1639         return rc;
1640 }
1641
1642 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1643 {
1644         struct bnxt *bp = eth_dev->data->dev_private;
1645         struct bnxt_vnic_info *vnic;
1646         uint32_t old_flags;
1647         int rc;
1648
1649         rc = is_bnxt_in_error(bp);
1650         if (rc)
1651                 return rc;
1652
1653         /* Filter settings will get applied when port is started */
1654         if (!eth_dev->data->dev_started)
1655                 return 0;
1656
1657         if (bp->vnic_info == NULL)
1658                 return 0;
1659
1660         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1661
1662         old_flags = vnic->flags;
1663         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1664         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1665         if (rc != 0)
1666                 vnic->flags = old_flags;
1667
1668         return rc;
1669 }
1670
1671 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1672 {
1673         struct bnxt *bp = eth_dev->data->dev_private;
1674         struct bnxt_vnic_info *vnic;
1675         uint32_t old_flags;
1676         int rc;
1677
1678         rc = is_bnxt_in_error(bp);
1679         if (rc)
1680                 return rc;
1681
1682         /* Filter settings will get applied when port is started */
1683         if (!eth_dev->data->dev_started)
1684                 return 0;
1685
1686         if (bp->vnic_info == NULL)
1687                 return 0;
1688
1689         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1690
1691         old_flags = vnic->flags;
1692         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1693         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1694         if (rc != 0)
1695                 vnic->flags = old_flags;
1696
1697         return rc;
1698 }
1699
1700 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1701 {
1702         struct bnxt *bp = eth_dev->data->dev_private;
1703         struct bnxt_vnic_info *vnic;
1704         uint32_t old_flags;
1705         int rc;
1706
1707         rc = is_bnxt_in_error(bp);
1708         if (rc)
1709                 return rc;
1710
1711         /* Filter settings will get applied when port is started */
1712         if (!eth_dev->data->dev_started)
1713                 return 0;
1714
1715         if (bp->vnic_info == NULL)
1716                 return 0;
1717
1718         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1719
1720         old_flags = vnic->flags;
1721         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1722         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1723         if (rc != 0)
1724                 vnic->flags = old_flags;
1725
1726         return rc;
1727 }
1728
1729 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1730 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1731 {
1732         if (qid >= bp->rx_nr_rings)
1733                 return NULL;
1734
1735         return bp->eth_dev->data->rx_queues[qid];
1736 }
1737
1738 /* Return rxq corresponding to a given rss table ring/group ID. */
1739 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1740 {
1741         struct bnxt_rx_queue *rxq;
1742         unsigned int i;
1743
1744         if (!BNXT_HAS_RING_GRPS(bp)) {
1745                 for (i = 0; i < bp->rx_nr_rings; i++) {
1746                         rxq = bp->eth_dev->data->rx_queues[i];
1747                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1748                                 return rxq->index;
1749                 }
1750         } else {
1751                 for (i = 0; i < bp->rx_nr_rings; i++) {
1752                         if (bp->grp_info[i].fw_grp_id == fwr)
1753                                 return i;
1754                 }
1755         }
1756
1757         return INVALID_HW_RING_ID;
1758 }
1759
1760 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1761                             struct rte_eth_rss_reta_entry64 *reta_conf,
1762                             uint16_t reta_size)
1763 {
1764         struct bnxt *bp = eth_dev->data->dev_private;
1765         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1766         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1767         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1768         uint16_t idx, sft;
1769         int i, rc;
1770
1771         rc = is_bnxt_in_error(bp);
1772         if (rc)
1773                 return rc;
1774
1775         if (!vnic->rss_table)
1776                 return -EINVAL;
1777
1778         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1779                 return -EINVAL;
1780
1781         if (reta_size != tbl_size) {
1782                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1783                         "(%d) must equal the size supported by the hardware "
1784                         "(%d)\n", reta_size, tbl_size);
1785                 return -EINVAL;
1786         }
1787
1788         for (i = 0; i < reta_size; i++) {
1789                 struct bnxt_rx_queue *rxq;
1790
1791                 idx = i / RTE_RETA_GROUP_SIZE;
1792                 sft = i % RTE_RETA_GROUP_SIZE;
1793
1794                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1795                         continue;
1796
1797                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1798                 if (!rxq) {
1799                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1800                         return -EINVAL;
1801                 }
1802
1803                 if (BNXT_CHIP_THOR(bp)) {
1804                         vnic->rss_table[i * 2] =
1805                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1806                         vnic->rss_table[i * 2 + 1] =
1807                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1808                 } else {
1809                         vnic->rss_table[i] =
1810                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1811                 }
1812         }
1813
1814         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1815         return 0;
1816 }
1817
1818 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1819                               struct rte_eth_rss_reta_entry64 *reta_conf,
1820                               uint16_t reta_size)
1821 {
1822         struct bnxt *bp = eth_dev->data->dev_private;
1823         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1824         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1825         uint16_t idx, sft, i;
1826         int rc;
1827
1828         rc = is_bnxt_in_error(bp);
1829         if (rc)
1830                 return rc;
1831
1832         /* Retrieve from the default VNIC */
1833         if (!vnic)
1834                 return -EINVAL;
1835         if (!vnic->rss_table)
1836                 return -EINVAL;
1837
1838         if (reta_size != tbl_size) {
1839                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1840                         "(%d) must equal the size supported by the hardware "
1841                         "(%d)\n", reta_size, tbl_size);
1842                 return -EINVAL;
1843         }
1844
1845         for (idx = 0, i = 0; i < reta_size; i++) {
1846                 idx = i / RTE_RETA_GROUP_SIZE;
1847                 sft = i % RTE_RETA_GROUP_SIZE;
1848
1849                 if (reta_conf[idx].mask & (1ULL << sft)) {
1850                         uint16_t qid;
1851
1852                         if (BNXT_CHIP_THOR(bp))
1853                                 qid = bnxt_rss_to_qid(bp,
1854                                                       vnic->rss_table[i * 2]);
1855                         else
1856                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1857
1858                         if (qid == INVALID_HW_RING_ID) {
1859                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1860                                 return -EINVAL;
1861                         }
1862                         reta_conf[idx].reta[sft] = qid;
1863                 }
1864         }
1865
1866         return 0;
1867 }
1868
1869 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1870                                    struct rte_eth_rss_conf *rss_conf)
1871 {
1872         struct bnxt *bp = eth_dev->data->dev_private;
1873         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1874         struct bnxt_vnic_info *vnic;
1875         int rc;
1876
1877         rc = is_bnxt_in_error(bp);
1878         if (rc)
1879                 return rc;
1880
1881         /*
1882          * If RSS enablement were different than dev_configure,
1883          * then return -EINVAL
1884          */
1885         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1886                 if (!rss_conf->rss_hf)
1887                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1888         } else {
1889                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1890                         return -EINVAL;
1891         }
1892
1893         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1894         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
1895                rss_conf,
1896                sizeof(*rss_conf));
1897
1898         /* Update the default RSS VNIC(s) */
1899         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1900         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1901
1902         /*
1903          * If hashkey is not specified, use the previously configured
1904          * hashkey
1905          */
1906         if (!rss_conf->rss_key)
1907                 goto rss_config;
1908
1909         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1910                 PMD_DRV_LOG(ERR,
1911                             "Invalid hashkey length, should be 16 bytes\n");
1912                 return -EINVAL;
1913         }
1914         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1915
1916 rss_config:
1917         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1918         return 0;
1919 }
1920
1921 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1922                                      struct rte_eth_rss_conf *rss_conf)
1923 {
1924         struct bnxt *bp = eth_dev->data->dev_private;
1925         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1926         int len, rc;
1927         uint32_t hash_types;
1928
1929         rc = is_bnxt_in_error(bp);
1930         if (rc)
1931                 return rc;
1932
1933         /* RSS configuration is the same for all VNICs */
1934         if (vnic && vnic->rss_hash_key) {
1935                 if (rss_conf->rss_key) {
1936                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1937                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1938                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1939                 }
1940
1941                 hash_types = vnic->hash_type;
1942                 rss_conf->rss_hf = 0;
1943                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1944                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1945                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1946                 }
1947                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1948                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1949                         hash_types &=
1950                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1951                 }
1952                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1953                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1954                         hash_types &=
1955                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1956                 }
1957                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1958                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1959                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1960                 }
1961                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1962                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1963                         hash_types &=
1964                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1965                 }
1966                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1967                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1968                         hash_types &=
1969                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1970                 }
1971                 if (hash_types) {
1972                         PMD_DRV_LOG(ERR,
1973                                 "Unknown RSS config from firmware (%08x), RSS disabled",
1974                                 vnic->hash_type);
1975                         return -ENOTSUP;
1976                 }
1977         } else {
1978                 rss_conf->rss_hf = 0;
1979         }
1980         return 0;
1981 }
1982
1983 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1984                                struct rte_eth_fc_conf *fc_conf)
1985 {
1986         struct bnxt *bp = dev->data->dev_private;
1987         struct rte_eth_link link_info;
1988         int rc;
1989
1990         rc = is_bnxt_in_error(bp);
1991         if (rc)
1992                 return rc;
1993
1994         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1995         if (rc)
1996                 return rc;
1997
1998         memset(fc_conf, 0, sizeof(*fc_conf));
1999         if (bp->link_info->auto_pause)
2000                 fc_conf->autoneg = 1;
2001         switch (bp->link_info->pause) {
2002         case 0:
2003                 fc_conf->mode = RTE_FC_NONE;
2004                 break;
2005         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2006                 fc_conf->mode = RTE_FC_TX_PAUSE;
2007                 break;
2008         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2009                 fc_conf->mode = RTE_FC_RX_PAUSE;
2010                 break;
2011         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2012                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2013                 fc_conf->mode = RTE_FC_FULL;
2014                 break;
2015         }
2016         return 0;
2017 }
2018
2019 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2020                                struct rte_eth_fc_conf *fc_conf)
2021 {
2022         struct bnxt *bp = dev->data->dev_private;
2023         int rc;
2024
2025         rc = is_bnxt_in_error(bp);
2026         if (rc)
2027                 return rc;
2028
2029         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2030                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2031                 return -ENOTSUP;
2032         }
2033
2034         switch (fc_conf->mode) {
2035         case RTE_FC_NONE:
2036                 bp->link_info->auto_pause = 0;
2037                 bp->link_info->force_pause = 0;
2038                 break;
2039         case RTE_FC_RX_PAUSE:
2040                 if (fc_conf->autoneg) {
2041                         bp->link_info->auto_pause =
2042                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2043                         bp->link_info->force_pause = 0;
2044                 } else {
2045                         bp->link_info->auto_pause = 0;
2046                         bp->link_info->force_pause =
2047                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2048                 }
2049                 break;
2050         case RTE_FC_TX_PAUSE:
2051                 if (fc_conf->autoneg) {
2052                         bp->link_info->auto_pause =
2053                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2054                         bp->link_info->force_pause = 0;
2055                 } else {
2056                         bp->link_info->auto_pause = 0;
2057                         bp->link_info->force_pause =
2058                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2059                 }
2060                 break;
2061         case RTE_FC_FULL:
2062                 if (fc_conf->autoneg) {
2063                         bp->link_info->auto_pause =
2064                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2065                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2066                         bp->link_info->force_pause = 0;
2067                 } else {
2068                         bp->link_info->auto_pause = 0;
2069                         bp->link_info->force_pause =
2070                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2071                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2072                 }
2073                 break;
2074         }
2075         return bnxt_set_hwrm_link_config(bp, true);
2076 }
2077
2078 /* Add UDP tunneling port */
2079 static int
2080 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2081                          struct rte_eth_udp_tunnel *udp_tunnel)
2082 {
2083         struct bnxt *bp = eth_dev->data->dev_private;
2084         uint16_t tunnel_type = 0;
2085         int rc = 0;
2086
2087         rc = is_bnxt_in_error(bp);
2088         if (rc)
2089                 return rc;
2090
2091         switch (udp_tunnel->prot_type) {
2092         case RTE_TUNNEL_TYPE_VXLAN:
2093                 if (bp->vxlan_port_cnt) {
2094                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2095                                 udp_tunnel->udp_port);
2096                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2097                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2098                                 return -ENOSPC;
2099                         }
2100                         bp->vxlan_port_cnt++;
2101                         return 0;
2102                 }
2103                 tunnel_type =
2104                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2105                 bp->vxlan_port_cnt++;
2106                 break;
2107         case RTE_TUNNEL_TYPE_GENEVE:
2108                 if (bp->geneve_port_cnt) {
2109                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2110                                 udp_tunnel->udp_port);
2111                         if (bp->geneve_port != udp_tunnel->udp_port) {
2112                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2113                                 return -ENOSPC;
2114                         }
2115                         bp->geneve_port_cnt++;
2116                         return 0;
2117                 }
2118                 tunnel_type =
2119                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2120                 bp->geneve_port_cnt++;
2121                 break;
2122         default:
2123                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2124                 return -ENOTSUP;
2125         }
2126         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2127                                              tunnel_type);
2128         return rc;
2129 }
2130
2131 static int
2132 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2133                          struct rte_eth_udp_tunnel *udp_tunnel)
2134 {
2135         struct bnxt *bp = eth_dev->data->dev_private;
2136         uint16_t tunnel_type = 0;
2137         uint16_t port = 0;
2138         int rc = 0;
2139
2140         rc = is_bnxt_in_error(bp);
2141         if (rc)
2142                 return rc;
2143
2144         switch (udp_tunnel->prot_type) {
2145         case RTE_TUNNEL_TYPE_VXLAN:
2146                 if (!bp->vxlan_port_cnt) {
2147                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2148                         return -EINVAL;
2149                 }
2150                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2151                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2152                                 udp_tunnel->udp_port, bp->vxlan_port);
2153                         return -EINVAL;
2154                 }
2155                 if (--bp->vxlan_port_cnt)
2156                         return 0;
2157
2158                 tunnel_type =
2159                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2160                 port = bp->vxlan_fw_dst_port_id;
2161                 break;
2162         case RTE_TUNNEL_TYPE_GENEVE:
2163                 if (!bp->geneve_port_cnt) {
2164                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2165                         return -EINVAL;
2166                 }
2167                 if (bp->geneve_port != udp_tunnel->udp_port) {
2168                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2169                                 udp_tunnel->udp_port, bp->geneve_port);
2170                         return -EINVAL;
2171                 }
2172                 if (--bp->geneve_port_cnt)
2173                         return 0;
2174
2175                 tunnel_type =
2176                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2177                 port = bp->geneve_fw_dst_port_id;
2178                 break;
2179         default:
2180                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2181                 return -ENOTSUP;
2182         }
2183
2184         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2185         if (!rc) {
2186                 if (tunnel_type ==
2187                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
2188                         bp->vxlan_port = 0;
2189                 if (tunnel_type ==
2190                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
2191                         bp->geneve_port = 0;
2192         }
2193         return rc;
2194 }
2195
2196 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2197 {
2198         struct bnxt_filter_info *filter;
2199         struct bnxt_vnic_info *vnic;
2200         int rc = 0;
2201         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2202
2203         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2204         filter = STAILQ_FIRST(&vnic->filter);
2205         while (filter) {
2206                 /* Search for this matching MAC+VLAN filter */
2207                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2208                         /* Delete the filter */
2209                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2210                         if (rc)
2211                                 return rc;
2212                         STAILQ_REMOVE(&vnic->filter, filter,
2213                                       bnxt_filter_info, next);
2214                         bnxt_free_filter(bp, filter);
2215                         PMD_DRV_LOG(INFO,
2216                                     "Deleted vlan filter for %d\n",
2217                                     vlan_id);
2218                         return 0;
2219                 }
2220                 filter = STAILQ_NEXT(filter, next);
2221         }
2222         return -ENOENT;
2223 }
2224
2225 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2226 {
2227         struct bnxt_filter_info *filter;
2228         struct bnxt_vnic_info *vnic;
2229         int rc = 0;
2230         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2231                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2232         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2233
2234         /* Implementation notes on the use of VNIC in this command:
2235          *
2236          * By default, these filters belong to default vnic for the function.
2237          * Once these filters are set up, only destination VNIC can be modified.
2238          * If the destination VNIC is not specified in this command,
2239          * then the HWRM shall only create an l2 context id.
2240          */
2241
2242         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2243         filter = STAILQ_FIRST(&vnic->filter);
2244         /* Check if the VLAN has already been added */
2245         while (filter) {
2246                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2247                         return -EEXIST;
2248
2249                 filter = STAILQ_NEXT(filter, next);
2250         }
2251
2252         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2253          * command to create MAC+VLAN filter with the right flags, enables set.
2254          */
2255         filter = bnxt_alloc_filter(bp);
2256         if (!filter) {
2257                 PMD_DRV_LOG(ERR,
2258                             "MAC/VLAN filter alloc failed\n");
2259                 return -ENOMEM;
2260         }
2261         /* MAC + VLAN ID filter */
2262         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2263          * untagged packets are received
2264          *
2265          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2266          * packets and only the programmed vlan's packets are received
2267          */
2268         filter->l2_ivlan = vlan_id;
2269         filter->l2_ivlan_mask = 0x0FFF;
2270         filter->enables |= en;
2271         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2272
2273         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2274         if (rc) {
2275                 /* Free the newly allocated filter as we were
2276                  * not able to create the filter in hardware.
2277                  */
2278                 bnxt_free_filter(bp, filter);
2279                 return rc;
2280         }
2281
2282         filter->mac_index = 0;
2283         /* Add this new filter to the list */
2284         if (vlan_id == 0)
2285                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2286         else
2287                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2288
2289         PMD_DRV_LOG(INFO,
2290                     "Added Vlan filter for %d\n", vlan_id);
2291         return rc;
2292 }
2293
2294 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2295                 uint16_t vlan_id, int on)
2296 {
2297         struct bnxt *bp = eth_dev->data->dev_private;
2298         int rc;
2299
2300         rc = is_bnxt_in_error(bp);
2301         if (rc)
2302                 return rc;
2303
2304         if (!eth_dev->data->dev_started) {
2305                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2306                 return -EINVAL;
2307         }
2308
2309         /* These operations apply to ALL existing MAC/VLAN filters */
2310         if (on)
2311                 return bnxt_add_vlan_filter(bp, vlan_id);
2312         else
2313                 return bnxt_del_vlan_filter(bp, vlan_id);
2314 }
2315
2316 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2317                                     struct bnxt_vnic_info *vnic)
2318 {
2319         struct bnxt_filter_info *filter;
2320         int rc;
2321
2322         filter = STAILQ_FIRST(&vnic->filter);
2323         while (filter) {
2324                 if (filter->mac_index == 0 &&
2325                     !memcmp(filter->l2_addr, bp->mac_addr,
2326                             RTE_ETHER_ADDR_LEN)) {
2327                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2328                         if (!rc) {
2329                                 STAILQ_REMOVE(&vnic->filter, filter,
2330                                               bnxt_filter_info, next);
2331                                 bnxt_free_filter(bp, filter);
2332                         }
2333                         return rc;
2334                 }
2335                 filter = STAILQ_NEXT(filter, next);
2336         }
2337         return 0;
2338 }
2339
2340 static int
2341 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2342 {
2343         struct bnxt_vnic_info *vnic;
2344         unsigned int i;
2345         int rc;
2346
2347         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2348         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2349                 /* Remove any VLAN filters programmed */
2350                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2351                         bnxt_del_vlan_filter(bp, i);
2352
2353                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2354                 if (rc)
2355                         return rc;
2356         } else {
2357                 /* Default filter will allow packets that match the
2358                  * dest mac. So, it has to be deleted, otherwise, we
2359                  * will endup receiving vlan packets for which the
2360                  * filter is not programmed, when hw-vlan-filter
2361                  * configuration is ON
2362                  */
2363                 bnxt_del_dflt_mac_filter(bp, vnic);
2364                 /* This filter will allow only untagged packets */
2365                 bnxt_add_vlan_filter(bp, 0);
2366         }
2367         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2368                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2369
2370         return 0;
2371 }
2372
2373 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2374 {
2375         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2376         unsigned int i;
2377         int rc;
2378
2379         /* Destroy vnic filters and vnic */
2380         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2381             DEV_RX_OFFLOAD_VLAN_FILTER) {
2382                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2383                         bnxt_del_vlan_filter(bp, i);
2384         }
2385         bnxt_del_dflt_mac_filter(bp, vnic);
2386
2387         rc = bnxt_hwrm_vnic_free(bp, vnic);
2388         if (rc)
2389                 return rc;
2390
2391         rte_free(vnic->fw_grp_ids);
2392         vnic->fw_grp_ids = NULL;
2393
2394         vnic->rx_queue_cnt = 0;
2395
2396         return 0;
2397 }
2398
2399 static int
2400 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2401 {
2402         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2403         int rc;
2404
2405         /* Destroy, recreate and reconfigure the default vnic */
2406         rc = bnxt_free_one_vnic(bp, 0);
2407         if (rc)
2408                 return rc;
2409
2410         /* default vnic 0 */
2411         rc = bnxt_setup_one_vnic(bp, 0);
2412         if (rc)
2413                 return rc;
2414
2415         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2416             DEV_RX_OFFLOAD_VLAN_FILTER) {
2417                 rc = bnxt_add_vlan_filter(bp, 0);
2418                 if (rc)
2419                         return rc;
2420                 rc = bnxt_restore_vlan_filters(bp);
2421                 if (rc)
2422                         return rc;
2423         } else {
2424                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2425                 if (rc)
2426                         return rc;
2427         }
2428
2429         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2430         if (rc)
2431                 return rc;
2432
2433         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2434                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2435
2436         return rc;
2437 }
2438
2439 static int
2440 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2441 {
2442         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2443         struct bnxt *bp = dev->data->dev_private;
2444         int rc;
2445
2446         rc = is_bnxt_in_error(bp);
2447         if (rc)
2448                 return rc;
2449
2450         /* Filter settings will get applied when port is started */
2451         if (!dev->data->dev_started)
2452                 return 0;
2453
2454         if (mask & ETH_VLAN_FILTER_MASK) {
2455                 /* Enable or disable VLAN filtering */
2456                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2457                 if (rc)
2458                         return rc;
2459         }
2460
2461         if (mask & ETH_VLAN_STRIP_MASK) {
2462                 /* Enable or disable VLAN stripping */
2463                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2464                 if (rc)
2465                         return rc;
2466         }
2467
2468         if (mask & ETH_VLAN_EXTEND_MASK) {
2469                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2470                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2471                 else
2472                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2473         }
2474
2475         return 0;
2476 }
2477
2478 static int
2479 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2480                       uint16_t tpid)
2481 {
2482         struct bnxt *bp = dev->data->dev_private;
2483         int qinq = dev->data->dev_conf.rxmode.offloads &
2484                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2485
2486         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2487             vlan_type != ETH_VLAN_TYPE_OUTER) {
2488                 PMD_DRV_LOG(ERR,
2489                             "Unsupported vlan type.");
2490                 return -EINVAL;
2491         }
2492         if (!qinq) {
2493                 PMD_DRV_LOG(ERR,
2494                             "QinQ not enabled. Needs to be ON as we can "
2495                             "accelerate only outer vlan\n");
2496                 return -EINVAL;
2497         }
2498
2499         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2500                 switch (tpid) {
2501                 case RTE_ETHER_TYPE_QINQ:
2502                         bp->outer_tpid_bd =
2503                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2504                                 break;
2505                 case RTE_ETHER_TYPE_VLAN:
2506                         bp->outer_tpid_bd =
2507                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2508                                 break;
2509                 case RTE_ETHER_TYPE_QINQ1:
2510                         bp->outer_tpid_bd =
2511                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2512                                 break;
2513                 case RTE_ETHER_TYPE_QINQ2:
2514                         bp->outer_tpid_bd =
2515                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2516                                 break;
2517                 case RTE_ETHER_TYPE_QINQ3:
2518                         bp->outer_tpid_bd =
2519                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2520                                 break;
2521                 default:
2522                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2523                         return -EINVAL;
2524                 }
2525                 bp->outer_tpid_bd |= tpid;
2526                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2527         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2528                 PMD_DRV_LOG(ERR,
2529                             "Can accelerate only outer vlan in QinQ\n");
2530                 return -EINVAL;
2531         }
2532
2533         return 0;
2534 }
2535
2536 static int
2537 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2538                              struct rte_ether_addr *addr)
2539 {
2540         struct bnxt *bp = dev->data->dev_private;
2541         /* Default Filter is tied to VNIC 0 */
2542         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2543         int rc;
2544
2545         rc = is_bnxt_in_error(bp);
2546         if (rc)
2547                 return rc;
2548
2549         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2550                 return -EPERM;
2551
2552         if (rte_is_zero_ether_addr(addr))
2553                 return -EINVAL;
2554
2555         /* Filter settings will get applied when port is started */
2556         if (!dev->data->dev_started)
2557                 return 0;
2558
2559         /* Check if the requested MAC is already added */
2560         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2561                 return 0;
2562
2563         /* Destroy filter and re-create it */
2564         bnxt_del_dflt_mac_filter(bp, vnic);
2565
2566         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2567         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2568                 /* This filter will allow only untagged packets */
2569                 rc = bnxt_add_vlan_filter(bp, 0);
2570         } else {
2571                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2572         }
2573
2574         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2575         return rc;
2576 }
2577
2578 static int
2579 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2580                           struct rte_ether_addr *mc_addr_set,
2581                           uint32_t nb_mc_addr)
2582 {
2583         struct bnxt *bp = eth_dev->data->dev_private;
2584         char *mc_addr_list = (char *)mc_addr_set;
2585         struct bnxt_vnic_info *vnic;
2586         uint32_t off = 0, i = 0;
2587         int rc;
2588
2589         rc = is_bnxt_in_error(bp);
2590         if (rc)
2591                 return rc;
2592
2593         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2594
2595         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2596                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2597                 goto allmulti;
2598         }
2599
2600         /* TODO Check for Duplicate mcast addresses */
2601         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2602         for (i = 0; i < nb_mc_addr; i++) {
2603                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2604                         RTE_ETHER_ADDR_LEN);
2605                 off += RTE_ETHER_ADDR_LEN;
2606         }
2607
2608         vnic->mc_addr_cnt = i;
2609         if (vnic->mc_addr_cnt)
2610                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2611         else
2612                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2613
2614 allmulti:
2615         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2616 }
2617
2618 static int
2619 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2620 {
2621         struct bnxt *bp = dev->data->dev_private;
2622         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2623         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2624         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2625         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2626         int ret;
2627
2628         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2629                         fw_major, fw_minor, fw_updt, fw_rsvd);
2630
2631         ret += 1; /* add the size of '\0' */
2632         if (fw_size < (uint32_t)ret)
2633                 return ret;
2634         else
2635                 return 0;
2636 }
2637
2638 static void
2639 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2640         struct rte_eth_rxq_info *qinfo)
2641 {
2642         struct bnxt *bp = dev->data->dev_private;
2643         struct bnxt_rx_queue *rxq;
2644
2645         if (is_bnxt_in_error(bp))
2646                 return;
2647
2648         rxq = dev->data->rx_queues[queue_id];
2649
2650         qinfo->mp = rxq->mb_pool;
2651         qinfo->scattered_rx = dev->data->scattered_rx;
2652         qinfo->nb_desc = rxq->nb_rx_desc;
2653
2654         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2655         qinfo->conf.rx_drop_en = rxq->drop_en;
2656         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2657         qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2658 }
2659
2660 static void
2661 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2662         struct rte_eth_txq_info *qinfo)
2663 {
2664         struct bnxt *bp = dev->data->dev_private;
2665         struct bnxt_tx_queue *txq;
2666
2667         if (is_bnxt_in_error(bp))
2668                 return;
2669
2670         txq = dev->data->tx_queues[queue_id];
2671
2672         qinfo->nb_desc = txq->nb_tx_desc;
2673
2674         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2675         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2676         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2677
2678         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2679         qinfo->conf.tx_rs_thresh = 0;
2680         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2681         qinfo->conf.offloads = dev->data->dev_conf.txmode.offloads;
2682 }
2683
2684 static const struct {
2685         eth_rx_burst_t pkt_burst;
2686         const char *info;
2687 } bnxt_rx_burst_info[] = {
2688         {bnxt_recv_pkts,        "Scalar"},
2689 #if defined(RTE_ARCH_X86)
2690         {bnxt_recv_pkts_vec,    "Vector SSE"},
2691 #elif defined(RTE_ARCH_ARM64)
2692         {bnxt_recv_pkts_vec,    "Vector Neon"},
2693 #endif
2694 };
2695
2696 static int
2697 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2698                        struct rte_eth_burst_mode *mode)
2699 {
2700         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2701         size_t i;
2702
2703         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2704                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2705                         snprintf(mode->info, sizeof(mode->info), "%s",
2706                                  bnxt_rx_burst_info[i].info);
2707                         return 0;
2708                 }
2709         }
2710
2711         return -EINVAL;
2712 }
2713
2714 static const struct {
2715         eth_tx_burst_t pkt_burst;
2716         const char *info;
2717 } bnxt_tx_burst_info[] = {
2718         {bnxt_xmit_pkts,        "Scalar"},
2719 #if defined(RTE_ARCH_X86)
2720         {bnxt_xmit_pkts_vec,    "Vector SSE"},
2721 #elif defined(RTE_ARCH_ARM64)
2722         {bnxt_xmit_pkts_vec,    "Vector Neon"},
2723 #endif
2724 };
2725
2726 static int
2727 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2728                        struct rte_eth_burst_mode *mode)
2729 {
2730         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2731         size_t i;
2732
2733         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2734                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2735                         snprintf(mode->info, sizeof(mode->info), "%s",
2736                                  bnxt_tx_burst_info[i].info);
2737                         return 0;
2738                 }
2739         }
2740
2741         return -EINVAL;
2742 }
2743
2744 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2745 {
2746         struct bnxt *bp = eth_dev->data->dev_private;
2747         uint32_t new_pkt_size;
2748         uint32_t rc = 0;
2749         uint32_t i;
2750
2751         rc = is_bnxt_in_error(bp);
2752         if (rc)
2753                 return rc;
2754
2755         /* Exit if receive queues are not configured yet */
2756         if (!eth_dev->data->nb_rx_queues)
2757                 return rc;
2758
2759         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2760                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2761
2762         /*
2763          * Disallow any MTU change that would require scattered receive support
2764          * if it is not already enabled.
2765          */
2766         if (eth_dev->data->dev_started &&
2767             !eth_dev->data->scattered_rx &&
2768             (new_pkt_size >
2769              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2770                 PMD_DRV_LOG(ERR,
2771                             "MTU change would require scattered rx support. ");
2772                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2773                 return -EINVAL;
2774         }
2775
2776         if (new_mtu > RTE_ETHER_MTU) {
2777                 bp->flags |= BNXT_FLAG_JUMBO;
2778                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2779                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2780         } else {
2781                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2782                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2783                 bp->flags &= ~BNXT_FLAG_JUMBO;
2784         }
2785
2786         /* Is there a change in mtu setting? */
2787         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2788                 return rc;
2789
2790         for (i = 0; i < bp->nr_vnics; i++) {
2791                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2792                 uint16_t size = 0;
2793
2794                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2795                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2796                 if (rc)
2797                         break;
2798
2799                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2800                 size -= RTE_PKTMBUF_HEADROOM;
2801
2802                 if (size < new_mtu) {
2803                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2804                         if (rc)
2805                                 return rc;
2806                 }
2807         }
2808
2809         if (!rc)
2810                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2811
2812         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2813
2814         return rc;
2815 }
2816
2817 static int
2818 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2819 {
2820         struct bnxt *bp = dev->data->dev_private;
2821         uint16_t vlan = bp->vlan;
2822         int rc;
2823
2824         rc = is_bnxt_in_error(bp);
2825         if (rc)
2826                 return rc;
2827
2828         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2829                 PMD_DRV_LOG(ERR,
2830                         "PVID cannot be modified for this function\n");
2831                 return -ENOTSUP;
2832         }
2833         bp->vlan = on ? pvid : 0;
2834
2835         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2836         if (rc)
2837                 bp->vlan = vlan;
2838         return rc;
2839 }
2840
2841 static int
2842 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2843 {
2844         struct bnxt *bp = dev->data->dev_private;
2845         int rc;
2846
2847         rc = is_bnxt_in_error(bp);
2848         if (rc)
2849                 return rc;
2850
2851         return bnxt_hwrm_port_led_cfg(bp, true);
2852 }
2853
2854 static int
2855 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2856 {
2857         struct bnxt *bp = dev->data->dev_private;
2858         int rc;
2859
2860         rc = is_bnxt_in_error(bp);
2861         if (rc)
2862                 return rc;
2863
2864         return bnxt_hwrm_port_led_cfg(bp, false);
2865 }
2866
2867 static uint32_t
2868 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2869 {
2870         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2871         uint32_t desc = 0, raw_cons = 0, cons;
2872         struct bnxt_cp_ring_info *cpr;
2873         struct bnxt_rx_queue *rxq;
2874         struct rx_pkt_cmpl *rxcmp;
2875         int rc;
2876
2877         rc = is_bnxt_in_error(bp);
2878         if (rc)
2879                 return rc;
2880
2881         rxq = dev->data->rx_queues[rx_queue_id];
2882         cpr = rxq->cp_ring;
2883         raw_cons = cpr->cp_raw_cons;
2884
2885         while (1) {
2886                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2887                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2888                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2889
2890                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2891                         break;
2892                 } else {
2893                         raw_cons++;
2894                         desc++;
2895                 }
2896         }
2897
2898         return desc;
2899 }
2900
2901 static int
2902 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2903 {
2904         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2905         struct bnxt_rx_ring_info *rxr;
2906         struct bnxt_cp_ring_info *cpr;
2907         struct rte_mbuf *rx_buf;
2908         struct rx_pkt_cmpl *rxcmp;
2909         uint32_t cons, cp_cons;
2910         int rc;
2911
2912         if (!rxq)
2913                 return -EINVAL;
2914
2915         rc = is_bnxt_in_error(rxq->bp);
2916         if (rc)
2917                 return rc;
2918
2919         cpr = rxq->cp_ring;
2920         rxr = rxq->rx_ring;
2921
2922         if (offset >= rxq->nb_rx_desc)
2923                 return -EINVAL;
2924
2925         cons = RING_CMP(cpr->cp_ring_struct, offset);
2926         cp_cons = cpr->cp_raw_cons;
2927         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2928
2929         if (cons > cp_cons) {
2930                 if (CMPL_VALID(rxcmp, cpr->valid))
2931                         return RTE_ETH_RX_DESC_DONE;
2932         } else {
2933                 if (CMPL_VALID(rxcmp, !cpr->valid))
2934                         return RTE_ETH_RX_DESC_DONE;
2935         }
2936         rx_buf = rxr->rx_buf_ring[cons];
2937         if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf)
2938                 return RTE_ETH_RX_DESC_UNAVAIL;
2939
2940
2941         return RTE_ETH_RX_DESC_AVAIL;
2942 }
2943
2944 static int
2945 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2946 {
2947         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2948         struct bnxt_tx_ring_info *txr;
2949         struct bnxt_cp_ring_info *cpr;
2950         struct bnxt_sw_tx_bd *tx_buf;
2951         struct tx_pkt_cmpl *txcmp;
2952         uint32_t cons, cp_cons;
2953         int rc;
2954
2955         if (!txq)
2956                 return -EINVAL;
2957
2958         rc = is_bnxt_in_error(txq->bp);
2959         if (rc)
2960                 return rc;
2961
2962         cpr = txq->cp_ring;
2963         txr = txq->tx_ring;
2964
2965         if (offset >= txq->nb_tx_desc)
2966                 return -EINVAL;
2967
2968         cons = RING_CMP(cpr->cp_ring_struct, offset);
2969         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2970         cp_cons = cpr->cp_raw_cons;
2971
2972         if (cons > cp_cons) {
2973                 if (CMPL_VALID(txcmp, cpr->valid))
2974                         return RTE_ETH_TX_DESC_UNAVAIL;
2975         } else {
2976                 if (CMPL_VALID(txcmp, !cpr->valid))
2977                         return RTE_ETH_TX_DESC_UNAVAIL;
2978         }
2979         tx_buf = &txr->tx_buf_ring[cons];
2980         if (tx_buf->mbuf == NULL)
2981                 return RTE_ETH_TX_DESC_DONE;
2982
2983         return RTE_ETH_TX_DESC_FULL;
2984 }
2985
2986 static struct bnxt_filter_info *
2987 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2988                                 struct rte_eth_ethertype_filter *efilter,
2989                                 struct bnxt_vnic_info *vnic0,
2990                                 struct bnxt_vnic_info *vnic,
2991                                 int *ret)
2992 {
2993         struct bnxt_filter_info *mfilter = NULL;
2994         int match = 0;
2995         *ret = 0;
2996
2997         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2998                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2999                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
3000                         " ethertype filter.", efilter->ether_type);
3001                 *ret = -EINVAL;
3002                 goto exit;
3003         }
3004         if (efilter->queue >= bp->rx_nr_rings) {
3005                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
3006                 *ret = -EINVAL;
3007                 goto exit;
3008         }
3009
3010         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3011         vnic = &bp->vnic_info[efilter->queue];
3012         if (vnic == NULL) {
3013                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
3014                 *ret = -EINVAL;
3015                 goto exit;
3016         }
3017
3018         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3019                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
3020                         if ((!memcmp(efilter->mac_addr.addr_bytes,
3021                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
3022                              mfilter->flags ==
3023                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
3024                              mfilter->ethertype == efilter->ether_type)) {
3025                                 match = 1;
3026                                 break;
3027                         }
3028                 }
3029         } else {
3030                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
3031                         if ((!memcmp(efilter->mac_addr.addr_bytes,
3032                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
3033                              mfilter->ethertype == efilter->ether_type &&
3034                              mfilter->flags ==
3035                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
3036                                 match = 1;
3037                                 break;
3038                         }
3039         }
3040
3041         if (match)
3042                 *ret = -EEXIST;
3043
3044 exit:
3045         return mfilter;
3046 }
3047
3048 static int
3049 bnxt_ethertype_filter(struct rte_eth_dev *dev,
3050                         enum rte_filter_op filter_op,
3051                         void *arg)
3052 {
3053         struct bnxt *bp = dev->data->dev_private;
3054         struct rte_eth_ethertype_filter *efilter =
3055                         (struct rte_eth_ethertype_filter *)arg;
3056         struct bnxt_filter_info *bfilter, *filter1;
3057         struct bnxt_vnic_info *vnic, *vnic0;
3058         int ret;
3059
3060         if (filter_op == RTE_ETH_FILTER_NOP)
3061                 return 0;
3062
3063         if (arg == NULL) {
3064                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3065                             filter_op);
3066                 return -EINVAL;
3067         }
3068
3069         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3070         vnic = &bp->vnic_info[efilter->queue];
3071
3072         switch (filter_op) {
3073         case RTE_ETH_FILTER_ADD:
3074                 bnxt_match_and_validate_ether_filter(bp, efilter,
3075                                                         vnic0, vnic, &ret);
3076                 if (ret < 0)
3077                         return ret;
3078
3079                 bfilter = bnxt_get_unused_filter(bp);
3080                 if (bfilter == NULL) {
3081                         PMD_DRV_LOG(ERR,
3082                                 "Not enough resources for a new filter.\n");
3083                         return -ENOMEM;
3084                 }
3085                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3086                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
3087                        RTE_ETHER_ADDR_LEN);
3088                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
3089                        RTE_ETHER_ADDR_LEN);
3090                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3091                 bfilter->ethertype = efilter->ether_type;
3092                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3093
3094                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
3095                 if (filter1 == NULL) {
3096                         ret = -EINVAL;
3097                         goto cleanup;
3098                 }
3099                 bfilter->enables |=
3100                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3101                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3102
3103                 bfilter->dst_id = vnic->fw_vnic_id;
3104
3105                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3106                         bfilter->flags =
3107                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3108                 }
3109
3110                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3111                 if (ret)
3112                         goto cleanup;
3113                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3114                 break;
3115         case RTE_ETH_FILTER_DELETE:
3116                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
3117                                                         vnic0, vnic, &ret);
3118                 if (ret == -EEXIST) {
3119                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
3120
3121                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
3122                                       next);
3123                         bnxt_free_filter(bp, filter1);
3124                 } else if (ret == 0) {
3125                         PMD_DRV_LOG(ERR, "No matching filter found\n");
3126                 }
3127                 break;
3128         default:
3129                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3130                 ret = -EINVAL;
3131                 goto error;
3132         }
3133         return ret;
3134 cleanup:
3135         bnxt_free_filter(bp, bfilter);
3136 error:
3137         return ret;
3138 }
3139
3140 static inline int
3141 parse_ntuple_filter(struct bnxt *bp,
3142                     struct rte_eth_ntuple_filter *nfilter,
3143                     struct bnxt_filter_info *bfilter)
3144 {
3145         uint32_t en = 0;
3146
3147         if (nfilter->queue >= bp->rx_nr_rings) {
3148                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
3149                 return -EINVAL;
3150         }
3151
3152         switch (nfilter->dst_port_mask) {
3153         case UINT16_MAX:
3154                 bfilter->dst_port_mask = -1;
3155                 bfilter->dst_port = nfilter->dst_port;
3156                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
3157                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3158                 break;
3159         default:
3160                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3161                 return -EINVAL;
3162         }
3163
3164         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3165         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3166
3167         switch (nfilter->proto_mask) {
3168         case UINT8_MAX:
3169                 if (nfilter->proto == 17) /* IPPROTO_UDP */
3170                         bfilter->ip_protocol = 17;
3171                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
3172                         bfilter->ip_protocol = 6;
3173                 else
3174                         return -EINVAL;
3175                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3176                 break;
3177         default:
3178                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3179                 return -EINVAL;
3180         }
3181
3182         switch (nfilter->dst_ip_mask) {
3183         case UINT32_MAX:
3184                 bfilter->dst_ipaddr_mask[0] = -1;
3185                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
3186                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
3187                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3188                 break;
3189         default:
3190                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3191                 return -EINVAL;
3192         }
3193
3194         switch (nfilter->src_ip_mask) {
3195         case UINT32_MAX:
3196                 bfilter->src_ipaddr_mask[0] = -1;
3197                 bfilter->src_ipaddr[0] = nfilter->src_ip;
3198                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
3199                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3200                 break;
3201         default:
3202                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3203                 return -EINVAL;
3204         }
3205
3206         switch (nfilter->src_port_mask) {
3207         case UINT16_MAX:
3208                 bfilter->src_port_mask = -1;
3209                 bfilter->src_port = nfilter->src_port;
3210                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
3211                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3212                 break;
3213         default:
3214                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3215                 return -EINVAL;
3216         }
3217
3218         bfilter->enables = en;
3219         return 0;
3220 }
3221
3222 static struct bnxt_filter_info*
3223 bnxt_match_ntuple_filter(struct bnxt *bp,
3224                          struct bnxt_filter_info *bfilter,
3225                          struct bnxt_vnic_info **mvnic)
3226 {
3227         struct bnxt_filter_info *mfilter = NULL;
3228         int i;
3229
3230         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3231                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3232                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
3233                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
3234                             bfilter->src_ipaddr_mask[0] ==
3235                             mfilter->src_ipaddr_mask[0] &&
3236                             bfilter->src_port == mfilter->src_port &&
3237                             bfilter->src_port_mask == mfilter->src_port_mask &&
3238                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
3239                             bfilter->dst_ipaddr_mask[0] ==
3240                             mfilter->dst_ipaddr_mask[0] &&
3241                             bfilter->dst_port == mfilter->dst_port &&
3242                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
3243                             bfilter->flags == mfilter->flags &&
3244                             bfilter->enables == mfilter->enables) {
3245                                 if (mvnic)
3246                                         *mvnic = vnic;
3247                                 return mfilter;
3248                         }
3249                 }
3250         }
3251         return NULL;
3252 }
3253
3254 static int
3255 bnxt_cfg_ntuple_filter(struct bnxt *bp,
3256                        struct rte_eth_ntuple_filter *nfilter,
3257                        enum rte_filter_op filter_op)
3258 {
3259         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
3260         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
3261         int ret;
3262
3263         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
3264                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3265                 return -EINVAL;
3266         }
3267
3268         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
3269                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
3270                 return -EINVAL;
3271         }
3272
3273         bfilter = bnxt_get_unused_filter(bp);
3274         if (bfilter == NULL) {
3275                 PMD_DRV_LOG(ERR,
3276                         "Not enough resources for a new filter.\n");
3277                 return -ENOMEM;
3278         }
3279         ret = parse_ntuple_filter(bp, nfilter, bfilter);
3280         if (ret < 0)
3281                 goto free_filter;
3282
3283         vnic = &bp->vnic_info[nfilter->queue];
3284         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3285         filter1 = STAILQ_FIRST(&vnic0->filter);
3286         if (filter1 == NULL) {
3287                 ret = -EINVAL;
3288                 goto free_filter;
3289         }
3290
3291         bfilter->dst_id = vnic->fw_vnic_id;
3292         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3293         bfilter->enables |=
3294                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3295         bfilter->ethertype = 0x800;
3296         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3297
3298         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3299
3300         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3301             bfilter->dst_id == mfilter->dst_id) {
3302                 PMD_DRV_LOG(ERR, "filter exists.\n");
3303                 ret = -EEXIST;
3304                 goto free_filter;
3305         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3306                    bfilter->dst_id != mfilter->dst_id) {
3307                 mfilter->dst_id = vnic->fw_vnic_id;
3308                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3309                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3310                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3311                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3312                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3313                 goto free_filter;
3314         }
3315         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3316                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3317                 ret = -ENOENT;
3318                 goto free_filter;
3319         }
3320
3321         if (filter_op == RTE_ETH_FILTER_ADD) {
3322                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3323                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3324                 if (ret)
3325                         goto free_filter;
3326                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3327         } else {
3328                 if (mfilter == NULL) {
3329                         /* This should not happen. But for Coverity! */
3330                         ret = -ENOENT;
3331                         goto free_filter;
3332                 }
3333                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3334
3335                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3336                 bnxt_free_filter(bp, mfilter);
3337                 bnxt_free_filter(bp, bfilter);
3338         }
3339
3340         return 0;
3341 free_filter:
3342         bnxt_free_filter(bp, bfilter);
3343         return ret;
3344 }
3345
3346 static int
3347 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3348                         enum rte_filter_op filter_op,
3349                         void *arg)
3350 {
3351         struct bnxt *bp = dev->data->dev_private;
3352         int ret;
3353
3354         if (filter_op == RTE_ETH_FILTER_NOP)
3355                 return 0;
3356
3357         if (arg == NULL) {
3358                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3359                             filter_op);
3360                 return -EINVAL;
3361         }
3362
3363         switch (filter_op) {
3364         case RTE_ETH_FILTER_ADD:
3365                 ret = bnxt_cfg_ntuple_filter(bp,
3366                         (struct rte_eth_ntuple_filter *)arg,
3367                         filter_op);
3368                 break;
3369         case RTE_ETH_FILTER_DELETE:
3370                 ret = bnxt_cfg_ntuple_filter(bp,
3371                         (struct rte_eth_ntuple_filter *)arg,
3372                         filter_op);
3373                 break;
3374         default:
3375                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3376                 ret = -EINVAL;
3377                 break;
3378         }
3379         return ret;
3380 }
3381
3382 static int
3383 bnxt_parse_fdir_filter(struct bnxt *bp,
3384                        struct rte_eth_fdir_filter *fdir,
3385                        struct bnxt_filter_info *filter)
3386 {
3387         enum rte_fdir_mode fdir_mode =
3388                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3389         struct bnxt_vnic_info *vnic0, *vnic;
3390         struct bnxt_filter_info *filter1;
3391         uint32_t en = 0;
3392         int i;
3393
3394         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3395                 return -EINVAL;
3396
3397         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3398         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3399
3400         switch (fdir->input.flow_type) {
3401         case RTE_ETH_FLOW_IPV4:
3402         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3403                 /* FALLTHROUGH */
3404                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3405                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3406                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3407                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3408                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3409                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3410                 filter->ip_addr_type =
3411                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3412                 filter->src_ipaddr_mask[0] = 0xffffffff;
3413                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3414                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3415                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3416                 filter->ethertype = 0x800;
3417                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3418                 break;
3419         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3420                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3421                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3422                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3423                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3424                 filter->dst_port_mask = 0xffff;
3425                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3426                 filter->src_port_mask = 0xffff;
3427                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3428                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3429                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3430                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3431                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3432                 filter->ip_protocol = 6;
3433                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3434                 filter->ip_addr_type =
3435                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3436                 filter->src_ipaddr_mask[0] = 0xffffffff;
3437                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3438                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3439                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3440                 filter->ethertype = 0x800;
3441                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3442                 break;
3443         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3444                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3445                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3446                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3447                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3448                 filter->dst_port_mask = 0xffff;
3449                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3450                 filter->src_port_mask = 0xffff;
3451                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3452                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3453                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3454                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3455                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3456                 filter->ip_protocol = 17;
3457                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3458                 filter->ip_addr_type =
3459                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3460                 filter->src_ipaddr_mask[0] = 0xffffffff;
3461                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3462                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3463                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3464                 filter->ethertype = 0x800;
3465                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3466                 break;
3467         case RTE_ETH_FLOW_IPV6:
3468         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3469                 /* FALLTHROUGH */
3470                 filter->ip_addr_type =
3471                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3472                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3473                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3474                 rte_memcpy(filter->src_ipaddr,
3475                            fdir->input.flow.ipv6_flow.src_ip, 16);
3476                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3477                 rte_memcpy(filter->dst_ipaddr,
3478                            fdir->input.flow.ipv6_flow.dst_ip, 16);
3479                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3480                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3481                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3482                 memset(filter->src_ipaddr_mask, 0xff, 16);
3483                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3484                 filter->ethertype = 0x86dd;
3485                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3486                 break;
3487         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3488                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3489                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3490                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3491                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3492                 filter->dst_port_mask = 0xffff;
3493                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3494                 filter->src_port_mask = 0xffff;
3495                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3496                 filter->ip_addr_type =
3497                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3498                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3499                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3500                 rte_memcpy(filter->src_ipaddr,
3501                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3502                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3503                 rte_memcpy(filter->dst_ipaddr,
3504                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3505                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3506                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3507                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3508                 memset(filter->src_ipaddr_mask, 0xff, 16);
3509                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3510                 filter->ethertype = 0x86dd;
3511                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3512                 break;
3513         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3514                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3515                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3516                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3517                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3518                 filter->dst_port_mask = 0xffff;
3519                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3520                 filter->src_port_mask = 0xffff;
3521                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3522                 filter->ip_addr_type =
3523                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3524                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3525                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3526                 rte_memcpy(filter->src_ipaddr,
3527                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3528                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3529                 rte_memcpy(filter->dst_ipaddr,
3530                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3531                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3532                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3533                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3534                 memset(filter->src_ipaddr_mask, 0xff, 16);
3535                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3536                 filter->ethertype = 0x86dd;
3537                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3538                 break;
3539         case RTE_ETH_FLOW_L2_PAYLOAD:
3540                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3541                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3542                 break;
3543         case RTE_ETH_FLOW_VXLAN:
3544                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3545                         return -EINVAL;
3546                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3547                 filter->tunnel_type =
3548                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3549                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3550                 break;
3551         case RTE_ETH_FLOW_NVGRE:
3552                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3553                         return -EINVAL;
3554                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3555                 filter->tunnel_type =
3556                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3557                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3558                 break;
3559         case RTE_ETH_FLOW_UNKNOWN:
3560         case RTE_ETH_FLOW_RAW:
3561         case RTE_ETH_FLOW_FRAG_IPV4:
3562         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3563         case RTE_ETH_FLOW_FRAG_IPV6:
3564         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3565         case RTE_ETH_FLOW_IPV6_EX:
3566         case RTE_ETH_FLOW_IPV6_TCP_EX:
3567         case RTE_ETH_FLOW_IPV6_UDP_EX:
3568         case RTE_ETH_FLOW_GENEVE:
3569                 /* FALLTHROUGH */
3570         default:
3571                 return -EINVAL;
3572         }
3573
3574         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3575         vnic = &bp->vnic_info[fdir->action.rx_queue];
3576         if (vnic == NULL) {
3577                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3578                 return -EINVAL;
3579         }
3580
3581         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3582                 rte_memcpy(filter->dst_macaddr,
3583                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3584                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3585         }
3586
3587         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3588                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3589                 filter1 = STAILQ_FIRST(&vnic0->filter);
3590                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3591         } else {
3592                 filter->dst_id = vnic->fw_vnic_id;
3593                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3594                         if (filter->dst_macaddr[i] == 0x00)
3595                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3596                         else
3597                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3598         }
3599
3600         if (filter1 == NULL)
3601                 return -EINVAL;
3602
3603         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3604         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3605
3606         filter->enables = en;
3607
3608         return 0;
3609 }
3610
3611 static struct bnxt_filter_info *
3612 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3613                 struct bnxt_vnic_info **mvnic)
3614 {
3615         struct bnxt_filter_info *mf = NULL;
3616         int i;
3617
3618         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3619                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3620
3621                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3622                         if (mf->filter_type == nf->filter_type &&
3623                             mf->flags == nf->flags &&
3624                             mf->src_port == nf->src_port &&
3625                             mf->src_port_mask == nf->src_port_mask &&
3626                             mf->dst_port == nf->dst_port &&
3627                             mf->dst_port_mask == nf->dst_port_mask &&
3628                             mf->ip_protocol == nf->ip_protocol &&
3629                             mf->ip_addr_type == nf->ip_addr_type &&
3630                             mf->ethertype == nf->ethertype &&
3631                             mf->vni == nf->vni &&
3632                             mf->tunnel_type == nf->tunnel_type &&
3633                             mf->l2_ovlan == nf->l2_ovlan &&
3634                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3635                             mf->l2_ivlan == nf->l2_ivlan &&
3636                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3637                             !memcmp(mf->l2_addr, nf->l2_addr,
3638                                     RTE_ETHER_ADDR_LEN) &&
3639                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3640                                     RTE_ETHER_ADDR_LEN) &&
3641                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3642                                     RTE_ETHER_ADDR_LEN) &&
3643                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3644                                     RTE_ETHER_ADDR_LEN) &&
3645                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3646                                     sizeof(nf->src_ipaddr)) &&
3647                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3648                                     sizeof(nf->src_ipaddr_mask)) &&
3649                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3650                                     sizeof(nf->dst_ipaddr)) &&
3651                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3652                                     sizeof(nf->dst_ipaddr_mask))) {
3653                                 if (mvnic)
3654                                         *mvnic = vnic;
3655                                 return mf;
3656                         }
3657                 }
3658         }
3659         return NULL;
3660 }
3661
3662 static int
3663 bnxt_fdir_filter(struct rte_eth_dev *dev,
3664                  enum rte_filter_op filter_op,
3665                  void *arg)
3666 {
3667         struct bnxt *bp = dev->data->dev_private;
3668         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3669         struct bnxt_filter_info *filter, *match;
3670         struct bnxt_vnic_info *vnic, *mvnic;
3671         int ret = 0, i;
3672
3673         if (filter_op == RTE_ETH_FILTER_NOP)
3674                 return 0;
3675
3676         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3677                 return -EINVAL;
3678
3679         switch (filter_op) {
3680         case RTE_ETH_FILTER_ADD:
3681         case RTE_ETH_FILTER_DELETE:
3682                 /* FALLTHROUGH */
3683                 filter = bnxt_get_unused_filter(bp);
3684                 if (filter == NULL) {
3685                         PMD_DRV_LOG(ERR,
3686                                 "Not enough resources for a new flow.\n");
3687                         return -ENOMEM;
3688                 }
3689
3690                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3691                 if (ret != 0)
3692                         goto free_filter;
3693                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3694
3695                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3696                         vnic = &bp->vnic_info[0];
3697                 else
3698                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3699
3700                 match = bnxt_match_fdir(bp, filter, &mvnic);
3701                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3702                         if (match->dst_id == vnic->fw_vnic_id) {
3703                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3704                                 ret = -EEXIST;
3705                                 goto free_filter;
3706                         } else {
3707                                 match->dst_id = vnic->fw_vnic_id;
3708                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3709                                                                   match->dst_id,
3710                                                                   match);
3711                                 STAILQ_REMOVE(&mvnic->filter, match,
3712                                               bnxt_filter_info, next);
3713                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3714                                 PMD_DRV_LOG(ERR,
3715                                         "Filter with matching pattern exist\n");
3716                                 PMD_DRV_LOG(ERR,
3717                                         "Updated it to new destination q\n");
3718                                 goto free_filter;
3719                         }
3720                 }
3721                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3722                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3723                         ret = -ENOENT;
3724                         goto free_filter;
3725                 }
3726
3727                 if (filter_op == RTE_ETH_FILTER_ADD) {
3728                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3729                                                           filter->dst_id,
3730                                                           filter);
3731                         if (ret)
3732                                 goto free_filter;
3733                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3734                 } else {
3735                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3736                         STAILQ_REMOVE(&vnic->filter, match,
3737                                       bnxt_filter_info, next);
3738                         bnxt_free_filter(bp, match);
3739                         bnxt_free_filter(bp, filter);
3740                 }
3741                 break;
3742         case RTE_ETH_FILTER_FLUSH:
3743                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3744                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3745
3746                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3747                                 if (filter->filter_type ==
3748                                     HWRM_CFA_NTUPLE_FILTER) {
3749                                         ret =
3750                                         bnxt_hwrm_clear_ntuple_filter(bp,
3751                                                                       filter);
3752                                         STAILQ_REMOVE(&vnic->filter, filter,
3753                                                       bnxt_filter_info, next);
3754                                 }
3755                         }
3756                 }
3757                 return ret;
3758         case RTE_ETH_FILTER_UPDATE:
3759         case RTE_ETH_FILTER_STATS:
3760         case RTE_ETH_FILTER_INFO:
3761                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3762                 break;
3763         default:
3764                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3765                 ret = -EINVAL;
3766                 break;
3767         }
3768         return ret;
3769
3770 free_filter:
3771         bnxt_free_filter(bp, filter);
3772         return ret;
3773 }
3774
3775 int
3776 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3777                     enum rte_filter_type filter_type,
3778                     enum rte_filter_op filter_op, void *arg)
3779 {
3780         struct bnxt *bp = dev->data->dev_private;
3781         int ret = 0;
3782
3783         if (!bp)
3784                 return -EIO;
3785
3786         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3787                 struct bnxt_representor *vfr = dev->data->dev_private;
3788                 bp = vfr->parent_dev->data->dev_private;
3789                 /* parent is deleted while children are still valid */
3790                 if (!bp) {
3791                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n",
3792                                     dev->data->port_id,
3793                                     filter_type,
3794                                     filter_op);
3795                         return -EIO;
3796                 }
3797         }
3798
3799         ret = is_bnxt_in_error(bp);
3800         if (ret)
3801                 return ret;
3802
3803         switch (filter_type) {
3804         case RTE_ETH_FILTER_TUNNEL:
3805                 PMD_DRV_LOG(ERR,
3806                         "filter type: %d: To be implemented\n", filter_type);
3807                 break;
3808         case RTE_ETH_FILTER_FDIR:
3809                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3810                 break;
3811         case RTE_ETH_FILTER_NTUPLE:
3812                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3813                 break;
3814         case RTE_ETH_FILTER_ETHERTYPE:
3815                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3816                 break;
3817         case RTE_ETH_FILTER_GENERIC:
3818                 if (filter_op != RTE_ETH_FILTER_GET)
3819                         return -EINVAL;
3820                 if (BNXT_TRUFLOW_EN(bp))
3821                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3822                 else
3823                         *(const void **)arg = &bnxt_flow_ops;
3824                 break;
3825         default:
3826                 PMD_DRV_LOG(ERR,
3827                         "Filter type (%d) not supported", filter_type);
3828                 ret = -EINVAL;
3829                 break;
3830         }
3831         return ret;
3832 }
3833
3834 static const uint32_t *
3835 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3836 {
3837         static const uint32_t ptypes[] = {
3838                 RTE_PTYPE_L2_ETHER_VLAN,
3839                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3840                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3841                 RTE_PTYPE_L4_ICMP,
3842                 RTE_PTYPE_L4_TCP,
3843                 RTE_PTYPE_L4_UDP,
3844                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3845                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3846                 RTE_PTYPE_INNER_L4_ICMP,
3847                 RTE_PTYPE_INNER_L4_TCP,
3848                 RTE_PTYPE_INNER_L4_UDP,
3849                 RTE_PTYPE_UNKNOWN
3850         };
3851
3852         if (!dev->rx_pkt_burst)
3853                 return NULL;
3854
3855         return ptypes;
3856 }
3857
3858 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3859                          int reg_win)
3860 {
3861         uint32_t reg_base = *reg_arr & 0xfffff000;
3862         uint32_t win_off;
3863         int i;
3864
3865         for (i = 0; i < count; i++) {
3866                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3867                         return -ERANGE;
3868         }
3869         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3870         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3871         return 0;
3872 }
3873
3874 static int bnxt_map_ptp_regs(struct bnxt *bp)
3875 {
3876         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3877         uint32_t *reg_arr;
3878         int rc, i;
3879
3880         reg_arr = ptp->rx_regs;
3881         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3882         if (rc)
3883                 return rc;
3884
3885         reg_arr = ptp->tx_regs;
3886         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3887         if (rc)
3888                 return rc;
3889
3890         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3891                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3892
3893         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3894                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3895
3896         return 0;
3897 }
3898
3899 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3900 {
3901         rte_write32(0, (uint8_t *)bp->bar0 +
3902                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3903         rte_write32(0, (uint8_t *)bp->bar0 +
3904                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3905 }
3906
3907 static uint64_t bnxt_cc_read(struct bnxt *bp)
3908 {
3909         uint64_t ns;
3910
3911         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3912                               BNXT_GRCPF_REG_SYNC_TIME));
3913         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3914                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3915         return ns;
3916 }
3917
3918 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3919 {
3920         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3921         uint32_t fifo;
3922
3923         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3924                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3925         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3926                 return -EAGAIN;
3927
3928         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3929                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3930         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3931                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3932         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3933                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3934
3935         return 0;
3936 }
3937
3938 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3939 {
3940         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3941         struct bnxt_pf_info *pf = bp->pf;
3942         uint16_t port_id;
3943         uint32_t fifo;
3944
3945         if (!ptp)
3946                 return -ENODEV;
3947
3948         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3949                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3950         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3951                 return -EAGAIN;
3952
3953         port_id = pf->port_id;
3954         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3955                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3956
3957         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3958                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3959         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3960 /*              bnxt_clr_rx_ts(bp);       TBD  */
3961                 return -EBUSY;
3962         }
3963
3964         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3965                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3966         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3967                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3968
3969         return 0;
3970 }
3971
3972 static int
3973 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3974 {
3975         uint64_t ns;
3976         struct bnxt *bp = dev->data->dev_private;
3977         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3978
3979         if (!ptp)
3980                 return 0;
3981
3982         ns = rte_timespec_to_ns(ts);
3983         /* Set the timecounters to a new value. */
3984         ptp->tc.nsec = ns;
3985
3986         return 0;
3987 }
3988
3989 static int
3990 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3991 {
3992         struct bnxt *bp = dev->data->dev_private;
3993         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3994         uint64_t ns, systime_cycles = 0;
3995         int rc = 0;
3996
3997         if (!ptp)
3998                 return 0;
3999
4000         if (BNXT_CHIP_THOR(bp))
4001                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
4002                                              &systime_cycles);
4003         else
4004                 systime_cycles = bnxt_cc_read(bp);
4005
4006         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
4007         *ts = rte_ns_to_timespec(ns);
4008
4009         return rc;
4010 }
4011 static int
4012 bnxt_timesync_enable(struct rte_eth_dev *dev)
4013 {
4014         struct bnxt *bp = dev->data->dev_private;
4015         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4016         uint32_t shift = 0;
4017         int rc;
4018
4019         if (!ptp)
4020                 return 0;
4021
4022         ptp->rx_filter = 1;
4023         ptp->tx_tstamp_en = 1;
4024         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
4025
4026         rc = bnxt_hwrm_ptp_cfg(bp);
4027         if (rc)
4028                 return rc;
4029
4030         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
4031         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4032         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4033
4034         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4035         ptp->tc.cc_shift = shift;
4036         ptp->tc.nsec_mask = (1ULL << shift) - 1;
4037
4038         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4039         ptp->rx_tstamp_tc.cc_shift = shift;
4040         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4041
4042         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4043         ptp->tx_tstamp_tc.cc_shift = shift;
4044         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4045
4046         if (!BNXT_CHIP_THOR(bp))
4047                 bnxt_map_ptp_regs(bp);
4048
4049         return 0;
4050 }
4051
4052 static int
4053 bnxt_timesync_disable(struct rte_eth_dev *dev)
4054 {
4055         struct bnxt *bp = dev->data->dev_private;
4056         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4057
4058         if (!ptp)
4059                 return 0;
4060
4061         ptp->rx_filter = 0;
4062         ptp->tx_tstamp_en = 0;
4063         ptp->rxctl = 0;
4064
4065         bnxt_hwrm_ptp_cfg(bp);
4066
4067         if (!BNXT_CHIP_THOR(bp))
4068                 bnxt_unmap_ptp_regs(bp);
4069
4070         return 0;
4071 }
4072
4073 static int
4074 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4075                                  struct timespec *timestamp,
4076                                  uint32_t flags __rte_unused)
4077 {
4078         struct bnxt *bp = dev->data->dev_private;
4079         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4080         uint64_t rx_tstamp_cycles = 0;
4081         uint64_t ns;
4082
4083         if (!ptp)
4084                 return 0;
4085
4086         if (BNXT_CHIP_THOR(bp))
4087                 rx_tstamp_cycles = ptp->rx_timestamp;
4088         else
4089                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
4090
4091         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
4092         *timestamp = rte_ns_to_timespec(ns);
4093         return  0;
4094 }
4095
4096 static int
4097 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4098                                  struct timespec *timestamp)
4099 {
4100         struct bnxt *bp = dev->data->dev_private;
4101         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4102         uint64_t tx_tstamp_cycles = 0;
4103         uint64_t ns;
4104         int rc = 0;
4105
4106         if (!ptp)
4107                 return 0;
4108
4109         if (BNXT_CHIP_THOR(bp))
4110                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
4111                                              &tx_tstamp_cycles);
4112         else
4113                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
4114
4115         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
4116         *timestamp = rte_ns_to_timespec(ns);
4117
4118         return rc;
4119 }
4120
4121 static int
4122 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4123 {
4124         struct bnxt *bp = dev->data->dev_private;
4125         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4126
4127         if (!ptp)
4128                 return 0;
4129
4130         ptp->tc.nsec += delta;
4131
4132         return 0;
4133 }
4134
4135 static int
4136 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
4137 {
4138         struct bnxt *bp = dev->data->dev_private;
4139         int rc;
4140         uint32_t dir_entries;
4141         uint32_t entry_length;
4142
4143         rc = is_bnxt_in_error(bp);
4144         if (rc)
4145                 return rc;
4146
4147         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
4148                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4149                     bp->pdev->addr.devid, bp->pdev->addr.function);
4150
4151         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4152         if (rc != 0)
4153                 return rc;
4154
4155         return dir_entries * entry_length;
4156 }
4157
4158 static int
4159 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
4160                 struct rte_dev_eeprom_info *in_eeprom)
4161 {
4162         struct bnxt *bp = dev->data->dev_private;
4163         uint32_t index;
4164         uint32_t offset;
4165         int rc;
4166
4167         rc = is_bnxt_in_error(bp);
4168         if (rc)
4169                 return rc;
4170
4171         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4172                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4173                     bp->pdev->addr.devid, bp->pdev->addr.function,
4174                     in_eeprom->offset, in_eeprom->length);
4175
4176         if (in_eeprom->offset == 0) /* special offset value to get directory */
4177                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
4178                                                 in_eeprom->data);
4179
4180         index = in_eeprom->offset >> 24;
4181         offset = in_eeprom->offset & 0xffffff;
4182
4183         if (index != 0)
4184                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
4185                                            in_eeprom->length, in_eeprom->data);
4186
4187         return 0;
4188 }
4189
4190 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
4191 {
4192         switch (dir_type) {
4193         case BNX_DIR_TYPE_CHIMP_PATCH:
4194         case BNX_DIR_TYPE_BOOTCODE:
4195         case BNX_DIR_TYPE_BOOTCODE_2:
4196         case BNX_DIR_TYPE_APE_FW:
4197         case BNX_DIR_TYPE_APE_PATCH:
4198         case BNX_DIR_TYPE_KONG_FW:
4199         case BNX_DIR_TYPE_KONG_PATCH:
4200         case BNX_DIR_TYPE_BONO_FW:
4201         case BNX_DIR_TYPE_BONO_PATCH:
4202                 /* FALLTHROUGH */
4203                 return true;
4204         }
4205
4206         return false;
4207 }
4208
4209 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
4210 {
4211         switch (dir_type) {
4212         case BNX_DIR_TYPE_AVS:
4213         case BNX_DIR_TYPE_EXP_ROM_MBA:
4214         case BNX_DIR_TYPE_PCIE:
4215         case BNX_DIR_TYPE_TSCF_UCODE:
4216         case BNX_DIR_TYPE_EXT_PHY:
4217         case BNX_DIR_TYPE_CCM:
4218         case BNX_DIR_TYPE_ISCSI_BOOT:
4219         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
4220         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
4221                 /* FALLTHROUGH */
4222                 return true;
4223         }
4224
4225         return false;
4226 }
4227
4228 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
4229 {
4230         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
4231                 bnxt_dir_type_is_other_exec_format(dir_type);
4232 }
4233
4234 static int
4235 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
4236                 struct rte_dev_eeprom_info *in_eeprom)
4237 {
4238         struct bnxt *bp = dev->data->dev_private;
4239         uint8_t index, dir_op;
4240         uint16_t type, ext, ordinal, attr;
4241         int rc;
4242
4243         rc = is_bnxt_in_error(bp);
4244         if (rc)
4245                 return rc;
4246
4247         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4248                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4249                     bp->pdev->addr.devid, bp->pdev->addr.function,
4250                     in_eeprom->offset, in_eeprom->length);
4251
4252         if (!BNXT_PF(bp)) {
4253                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
4254                 return -EINVAL;
4255         }
4256
4257         type = in_eeprom->magic >> 16;
4258
4259         if (type == 0xffff) { /* special value for directory operations */
4260                 index = in_eeprom->magic & 0xff;
4261                 dir_op = in_eeprom->magic >> 8;
4262                 if (index == 0)
4263                         return -EINVAL;
4264                 switch (dir_op) {
4265                 case 0x0e: /* erase */
4266                         if (in_eeprom->offset != ~in_eeprom->magic)
4267                                 return -EINVAL;
4268                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
4269                 default:
4270                         return -EINVAL;
4271                 }
4272         }
4273
4274         /* Create or re-write an NVM item: */
4275         if (bnxt_dir_type_is_executable(type) == true)
4276                 return -EOPNOTSUPP;
4277         ext = in_eeprom->magic & 0xffff;
4278         ordinal = in_eeprom->offset >> 16;
4279         attr = in_eeprom->offset & 0xffff;
4280
4281         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
4282                                      in_eeprom->data, in_eeprom->length);
4283 }
4284
4285 /*
4286  * Initialization
4287  */
4288
4289 static const struct eth_dev_ops bnxt_dev_ops = {
4290         .dev_infos_get = bnxt_dev_info_get_op,
4291         .dev_close = bnxt_dev_close_op,
4292         .dev_configure = bnxt_dev_configure_op,
4293         .dev_start = bnxt_dev_start_op,
4294         .dev_stop = bnxt_dev_stop_op,
4295         .dev_set_link_up = bnxt_dev_set_link_up_op,
4296         .dev_set_link_down = bnxt_dev_set_link_down_op,
4297         .stats_get = bnxt_stats_get_op,
4298         .stats_reset = bnxt_stats_reset_op,
4299         .rx_queue_setup = bnxt_rx_queue_setup_op,
4300         .rx_queue_release = bnxt_rx_queue_release_op,
4301         .tx_queue_setup = bnxt_tx_queue_setup_op,
4302         .tx_queue_release = bnxt_tx_queue_release_op,
4303         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4304         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4305         .reta_update = bnxt_reta_update_op,
4306         .reta_query = bnxt_reta_query_op,
4307         .rss_hash_update = bnxt_rss_hash_update_op,
4308         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4309         .link_update = bnxt_link_update_op,
4310         .promiscuous_enable = bnxt_promiscuous_enable_op,
4311         .promiscuous_disable = bnxt_promiscuous_disable_op,
4312         .allmulticast_enable = bnxt_allmulticast_enable_op,
4313         .allmulticast_disable = bnxt_allmulticast_disable_op,
4314         .mac_addr_add = bnxt_mac_addr_add_op,
4315         .mac_addr_remove = bnxt_mac_addr_remove_op,
4316         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4317         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4318         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4319         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4320         .vlan_filter_set = bnxt_vlan_filter_set_op,
4321         .vlan_offload_set = bnxt_vlan_offload_set_op,
4322         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4323         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4324         .mtu_set = bnxt_mtu_set_op,
4325         .mac_addr_set = bnxt_set_default_mac_addr_op,
4326         .xstats_get = bnxt_dev_xstats_get_op,
4327         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4328         .xstats_reset = bnxt_dev_xstats_reset_op,
4329         .fw_version_get = bnxt_fw_version_get,
4330         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4331         .rxq_info_get = bnxt_rxq_info_get_op,
4332         .txq_info_get = bnxt_txq_info_get_op,
4333         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4334         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4335         .dev_led_on = bnxt_dev_led_on_op,
4336         .dev_led_off = bnxt_dev_led_off_op,
4337         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4338         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4339         .rx_queue_start = bnxt_rx_queue_start,
4340         .rx_queue_stop = bnxt_rx_queue_stop,
4341         .tx_queue_start = bnxt_tx_queue_start,
4342         .tx_queue_stop = bnxt_tx_queue_stop,
4343         .filter_ctrl = bnxt_filter_ctrl_op,
4344         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4345         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4346         .get_eeprom           = bnxt_get_eeprom_op,
4347         .set_eeprom           = bnxt_set_eeprom_op,
4348         .timesync_enable      = bnxt_timesync_enable,
4349         .timesync_disable     = bnxt_timesync_disable,
4350         .timesync_read_time   = bnxt_timesync_read_time,
4351         .timesync_write_time   = bnxt_timesync_write_time,
4352         .timesync_adjust_time = bnxt_timesync_adjust_time,
4353         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4354         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4355 };
4356
4357 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4358 {
4359         uint32_t offset;
4360
4361         /* Only pre-map the reset GRC registers using window 3 */
4362         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4363                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4364
4365         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4366
4367         return offset;
4368 }
4369
4370 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4371 {
4372         struct bnxt_error_recovery_info *info = bp->recovery_info;
4373         uint32_t reg_base = 0xffffffff;
4374         int i;
4375
4376         /* Only pre-map the monitoring GRC registers using window 2 */
4377         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4378                 uint32_t reg = info->status_regs[i];
4379
4380                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4381                         continue;
4382
4383                 if (reg_base == 0xffffffff)
4384                         reg_base = reg & 0xfffff000;
4385                 if ((reg & 0xfffff000) != reg_base)
4386                         return -ERANGE;
4387
4388                 /* Use mask 0xffc as the Lower 2 bits indicates
4389                  * address space location
4390                  */
4391                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4392                                                 (reg & 0xffc);
4393         }
4394
4395         if (reg_base == 0xffffffff)
4396                 return 0;
4397
4398         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4399                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4400
4401         return 0;
4402 }
4403
4404 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4405 {
4406         struct bnxt_error_recovery_info *info = bp->recovery_info;
4407         uint32_t delay = info->delay_after_reset[index];
4408         uint32_t val = info->reset_reg_val[index];
4409         uint32_t reg = info->reset_reg[index];
4410         uint32_t type, offset;
4411
4412         type = BNXT_FW_STATUS_REG_TYPE(reg);
4413         offset = BNXT_FW_STATUS_REG_OFF(reg);
4414
4415         switch (type) {
4416         case BNXT_FW_STATUS_REG_TYPE_CFG:
4417                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4418                 break;
4419         case BNXT_FW_STATUS_REG_TYPE_GRC:
4420                 offset = bnxt_map_reset_regs(bp, offset);
4421                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4422                 break;
4423         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4424                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4425                 break;
4426         }
4427         /* wait on a specific interval of time until core reset is complete */
4428         if (delay)
4429                 rte_delay_ms(delay);
4430 }
4431
4432 static void bnxt_dev_cleanup(struct bnxt *bp)
4433 {
4434         bp->eth_dev->data->dev_link.link_status = 0;
4435         bp->link_info->link_up = 0;
4436         if (bp->eth_dev->data->dev_started)
4437                 bnxt_dev_stop_op(bp->eth_dev);
4438
4439         bnxt_uninit_resources(bp, true);
4440 }
4441
4442 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4443 {
4444         struct rte_eth_dev *dev = bp->eth_dev;
4445         struct rte_vlan_filter_conf *vfc;
4446         int vidx, vbit, rc;
4447         uint16_t vlan_id;
4448
4449         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4450                 vfc = &dev->data->vlan_filter_conf;
4451                 vidx = vlan_id / 64;
4452                 vbit = vlan_id % 64;
4453
4454                 /* Each bit corresponds to a VLAN id */
4455                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4456                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4457                         if (rc)
4458                                 return rc;
4459                 }
4460         }
4461
4462         return 0;
4463 }
4464
4465 static int bnxt_restore_mac_filters(struct bnxt *bp)
4466 {
4467         struct rte_eth_dev *dev = bp->eth_dev;
4468         struct rte_eth_dev_info dev_info;
4469         struct rte_ether_addr *addr;
4470         uint64_t pool_mask;
4471         uint32_t pool = 0;
4472         uint16_t i;
4473         int rc;
4474
4475         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4476                 return 0;
4477
4478         rc = bnxt_dev_info_get_op(dev, &dev_info);
4479         if (rc)
4480                 return rc;
4481
4482         /* replay MAC address configuration */
4483         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4484                 addr = &dev->data->mac_addrs[i];
4485
4486                 /* skip zero address */
4487                 if (rte_is_zero_ether_addr(addr))
4488                         continue;
4489
4490                 pool = 0;
4491                 pool_mask = dev->data->mac_pool_sel[i];
4492
4493                 do {
4494                         if (pool_mask & 1ULL) {
4495                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4496                                 if (rc)
4497                                         return rc;
4498                         }
4499                         pool_mask >>= 1;
4500                         pool++;
4501                 } while (pool_mask);
4502         }
4503
4504         return 0;
4505 }
4506
4507 static int bnxt_restore_filters(struct bnxt *bp)
4508 {
4509         struct rte_eth_dev *dev = bp->eth_dev;
4510         int ret = 0;
4511
4512         if (dev->data->all_multicast) {
4513                 ret = bnxt_allmulticast_enable_op(dev);
4514                 if (ret)
4515                         return ret;
4516         }
4517         if (dev->data->promiscuous) {
4518                 ret = bnxt_promiscuous_enable_op(dev);
4519                 if (ret)
4520                         return ret;
4521         }
4522
4523         ret = bnxt_restore_mac_filters(bp);
4524         if (ret)
4525                 return ret;
4526
4527         ret = bnxt_restore_vlan_filters(bp);
4528         /* TODO restore other filters as well */
4529         return ret;
4530 }
4531
4532 static void bnxt_dev_recover(void *arg)
4533 {
4534         struct bnxt *bp = arg;
4535         int timeout = bp->fw_reset_max_msecs;
4536         int rc = 0;
4537
4538         /* Clear Error flag so that device re-init should happen */
4539         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4540
4541         do {
4542                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4543                 if (rc == 0)
4544                         break;
4545                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4546                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4547         } while (rc && timeout);
4548
4549         if (rc) {
4550                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4551                 goto err;
4552         }
4553
4554         rc = bnxt_init_resources(bp, true);
4555         if (rc) {
4556                 PMD_DRV_LOG(ERR,
4557                             "Failed to initialize resources after reset\n");
4558                 goto err;
4559         }
4560         /* clear reset flag as the device is initialized now */
4561         bp->flags &= ~BNXT_FLAG_FW_RESET;
4562
4563         rc = bnxt_dev_start_op(bp->eth_dev);
4564         if (rc) {
4565                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4566                 goto err_start;
4567         }
4568
4569         rc = bnxt_restore_filters(bp);
4570         if (rc)
4571                 goto err_start;
4572
4573         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4574         return;
4575 err_start:
4576         bnxt_dev_stop_op(bp->eth_dev);
4577 err:
4578         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4579         bnxt_uninit_resources(bp, false);
4580         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4581 }
4582
4583 void bnxt_dev_reset_and_resume(void *arg)
4584 {
4585         struct bnxt *bp = arg;
4586         int rc;
4587
4588         bnxt_dev_cleanup(bp);
4589
4590         bnxt_wait_for_device_shutdown(bp);
4591
4592         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4593                                bnxt_dev_recover, (void *)bp);
4594         if (rc)
4595                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4596 }
4597
4598 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4599 {
4600         struct bnxt_error_recovery_info *info = bp->recovery_info;
4601         uint32_t reg = info->status_regs[index];
4602         uint32_t type, offset, val = 0;
4603
4604         type = BNXT_FW_STATUS_REG_TYPE(reg);
4605         offset = BNXT_FW_STATUS_REG_OFF(reg);
4606
4607         switch (type) {
4608         case BNXT_FW_STATUS_REG_TYPE_CFG:
4609                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4610                 break;
4611         case BNXT_FW_STATUS_REG_TYPE_GRC:
4612                 offset = info->mapped_status_regs[index];
4613                 /* FALLTHROUGH */
4614         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4615                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4616                                        offset));
4617                 break;
4618         }
4619
4620         return val;
4621 }
4622
4623 static int bnxt_fw_reset_all(struct bnxt *bp)
4624 {
4625         struct bnxt_error_recovery_info *info = bp->recovery_info;
4626         uint32_t i;
4627         int rc = 0;
4628
4629         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4630                 /* Reset through master function driver */
4631                 for (i = 0; i < info->reg_array_cnt; i++)
4632                         bnxt_write_fw_reset_reg(bp, i);
4633                 /* Wait for time specified by FW after triggering reset */
4634                 rte_delay_ms(info->master_func_wait_period_after_reset);
4635         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4636                 /* Reset with the help of Kong processor */
4637                 rc = bnxt_hwrm_fw_reset(bp);
4638                 if (rc)
4639                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4640         }
4641
4642         return rc;
4643 }
4644
4645 static void bnxt_fw_reset_cb(void *arg)
4646 {
4647         struct bnxt *bp = arg;
4648         struct bnxt_error_recovery_info *info = bp->recovery_info;
4649         int rc = 0;
4650
4651         /* Only Master function can do FW reset */
4652         if (bnxt_is_master_func(bp) &&
4653             bnxt_is_recovery_enabled(bp)) {
4654                 rc = bnxt_fw_reset_all(bp);
4655                 if (rc) {
4656                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4657                         return;
4658                 }
4659         }
4660
4661         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4662          * EXCEPTION_FATAL_ASYNC event to all the functions
4663          * (including MASTER FUNC). After receiving this Async, all the active
4664          * drivers should treat this case as FW initiated recovery
4665          */
4666         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4667                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4668                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4669
4670                 /* To recover from error */
4671                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4672                                   (void *)bp);
4673         }
4674 }
4675
4676 /* Driver should poll FW heartbeat, reset_counter with the frequency
4677  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4678  * When the driver detects heartbeat stop or change in reset_counter,
4679  * it has to trigger a reset to recover from the error condition.
4680  * A “master PF” is the function who will have the privilege to
4681  * initiate the chimp reset. The master PF will be elected by the
4682  * firmware and will be notified through async message.
4683  */
4684 static void bnxt_check_fw_health(void *arg)
4685 {
4686         struct bnxt *bp = arg;
4687         struct bnxt_error_recovery_info *info = bp->recovery_info;
4688         uint32_t val = 0, wait_msec;
4689
4690         if (!info || !bnxt_is_recovery_enabled(bp) ||
4691             is_bnxt_in_error(bp))
4692                 return;
4693
4694         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4695         if (val == info->last_heart_beat)
4696                 goto reset;
4697
4698         info->last_heart_beat = val;
4699
4700         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4701         if (val != info->last_reset_counter)
4702                 goto reset;
4703
4704         info->last_reset_counter = val;
4705
4706         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4707                           bnxt_check_fw_health, (void *)bp);
4708
4709         return;
4710 reset:
4711         /* Stop DMA to/from device */
4712         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4713         bp->flags |= BNXT_FLAG_FW_RESET;
4714
4715         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4716
4717         if (bnxt_is_master_func(bp))
4718                 wait_msec = info->master_func_wait_period;
4719         else
4720                 wait_msec = info->normal_func_wait_period;
4721
4722         rte_eal_alarm_set(US_PER_MS * wait_msec,
4723                           bnxt_fw_reset_cb, (void *)bp);
4724 }
4725
4726 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4727 {
4728         uint32_t polling_freq;
4729
4730         pthread_mutex_lock(&bp->health_check_lock);
4731
4732         if (!bnxt_is_recovery_enabled(bp))
4733                 goto done;
4734
4735         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4736                 goto done;
4737
4738         polling_freq = bp->recovery_info->driver_polling_freq;
4739
4740         rte_eal_alarm_set(US_PER_MS * polling_freq,
4741                           bnxt_check_fw_health, (void *)bp);
4742         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4743
4744 done:
4745         pthread_mutex_unlock(&bp->health_check_lock);
4746 }
4747
4748 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4749 {
4750         if (!bnxt_is_recovery_enabled(bp))
4751                 return;
4752
4753         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4754         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4755 }
4756
4757 static bool bnxt_vf_pciid(uint16_t device_id)
4758 {
4759         switch (device_id) {
4760         case BROADCOM_DEV_ID_57304_VF:
4761         case BROADCOM_DEV_ID_57406_VF:
4762         case BROADCOM_DEV_ID_5731X_VF:
4763         case BROADCOM_DEV_ID_5741X_VF:
4764         case BROADCOM_DEV_ID_57414_VF:
4765         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4766         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4767         case BROADCOM_DEV_ID_58802_VF:
4768         case BROADCOM_DEV_ID_57500_VF1:
4769         case BROADCOM_DEV_ID_57500_VF2:
4770                 /* FALLTHROUGH */
4771                 return true;
4772         default:
4773                 return false;
4774         }
4775 }
4776
4777 static bool bnxt_thor_device(uint16_t device_id)
4778 {
4779         switch (device_id) {
4780         case BROADCOM_DEV_ID_57508:
4781         case BROADCOM_DEV_ID_57504:
4782         case BROADCOM_DEV_ID_57502:
4783         case BROADCOM_DEV_ID_57508_MF1:
4784         case BROADCOM_DEV_ID_57504_MF1:
4785         case BROADCOM_DEV_ID_57502_MF1:
4786         case BROADCOM_DEV_ID_57508_MF2:
4787         case BROADCOM_DEV_ID_57504_MF2:
4788         case BROADCOM_DEV_ID_57502_MF2:
4789         case BROADCOM_DEV_ID_57500_VF1:
4790         case BROADCOM_DEV_ID_57500_VF2:
4791                 /* FALLTHROUGH */
4792                 return true;
4793         default:
4794                 return false;
4795         }
4796 }
4797
4798 bool bnxt_stratus_device(struct bnxt *bp)
4799 {
4800         uint16_t device_id = bp->pdev->id.device_id;
4801
4802         switch (device_id) {
4803         case BROADCOM_DEV_ID_STRATUS_NIC:
4804         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4805         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4806                 /* FALLTHROUGH */
4807                 return true;
4808         default:
4809                 return false;
4810         }
4811 }
4812
4813 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4814 {
4815         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4816         struct bnxt *bp = eth_dev->data->dev_private;
4817
4818         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4819         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4820         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4821         if (!bp->bar0 || !bp->doorbell_base) {
4822                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4823                 return -ENODEV;
4824         }
4825
4826         bp->eth_dev = eth_dev;
4827         bp->pdev = pci_dev;
4828
4829         return 0;
4830 }
4831
4832 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4833                                   struct bnxt_ctx_pg_info *ctx_pg,
4834                                   uint32_t mem_size,
4835                                   const char *suffix,
4836                                   uint16_t idx)
4837 {
4838         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4839         const struct rte_memzone *mz = NULL;
4840         char mz_name[RTE_MEMZONE_NAMESIZE];
4841         rte_iova_t mz_phys_addr;
4842         uint64_t valid_bits = 0;
4843         uint32_t sz;
4844         int i;
4845
4846         if (!mem_size)
4847                 return 0;
4848
4849         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4850                          BNXT_PAGE_SIZE;
4851         rmem->page_size = BNXT_PAGE_SIZE;
4852         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4853         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4854         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4855
4856         valid_bits = PTU_PTE_VALID;
4857
4858         if (rmem->nr_pages > 1) {
4859                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4860                          "bnxt_ctx_pg_tbl%s_%x_%d",
4861                          suffix, idx, bp->eth_dev->data->port_id);
4862                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4863                 mz = rte_memzone_lookup(mz_name);
4864                 if (!mz) {
4865                         mz = rte_memzone_reserve_aligned(mz_name,
4866                                                 rmem->nr_pages * 8,
4867                                                 SOCKET_ID_ANY,
4868                                                 RTE_MEMZONE_2MB |
4869                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4870                                                 RTE_MEMZONE_IOVA_CONTIG,
4871                                                 BNXT_PAGE_SIZE);
4872                         if (mz == NULL)
4873                                 return -ENOMEM;
4874                 }
4875
4876                 memset(mz->addr, 0, mz->len);
4877                 mz_phys_addr = mz->iova;
4878
4879                 rmem->pg_tbl = mz->addr;
4880                 rmem->pg_tbl_map = mz_phys_addr;
4881                 rmem->pg_tbl_mz = mz;
4882         }
4883
4884         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4885                  suffix, idx, bp->eth_dev->data->port_id);
4886         mz = rte_memzone_lookup(mz_name);
4887         if (!mz) {
4888                 mz = rte_memzone_reserve_aligned(mz_name,
4889                                                  mem_size,
4890                                                  SOCKET_ID_ANY,
4891                                                  RTE_MEMZONE_1GB |
4892                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4893                                                  RTE_MEMZONE_IOVA_CONTIG,
4894                                                  BNXT_PAGE_SIZE);
4895                 if (mz == NULL)
4896                         return -ENOMEM;
4897         }
4898
4899         memset(mz->addr, 0, mz->len);
4900         mz_phys_addr = mz->iova;
4901
4902         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4903                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4904                 rmem->dma_arr[i] = mz_phys_addr + sz;
4905
4906                 if (rmem->nr_pages > 1) {
4907                         if (i == rmem->nr_pages - 2 &&
4908                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4909                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4910                         else if (i == rmem->nr_pages - 1 &&
4911                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4912                                 valid_bits |= PTU_PTE_LAST;
4913
4914                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4915                                                            valid_bits);
4916                 }
4917         }
4918
4919         rmem->mz = mz;
4920         if (rmem->vmem_size)
4921                 rmem->vmem = (void **)mz->addr;
4922         rmem->dma_arr[0] = mz_phys_addr;
4923         return 0;
4924 }
4925
4926 static void bnxt_free_ctx_mem(struct bnxt *bp)
4927 {
4928         int i;
4929
4930         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4931                 return;
4932
4933         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4934         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4935         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4936         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4937         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4938         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4939         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4940         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4941         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4942         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4943         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4944
4945         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4946                 if (bp->ctx->tqm_mem[i])
4947                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4948         }
4949
4950         rte_free(bp->ctx);
4951         bp->ctx = NULL;
4952 }
4953
4954 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4955
4956 #define min_t(type, x, y) ({                    \
4957         type __min1 = (x);                      \
4958         type __min2 = (y);                      \
4959         __min1 < __min2 ? __min1 : __min2; })
4960
4961 #define max_t(type, x, y) ({                    \
4962         type __max1 = (x);                      \
4963         type __max2 = (y);                      \
4964         __max1 > __max2 ? __max1 : __max2; })
4965
4966 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4967
4968 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4969 {
4970         struct bnxt_ctx_pg_info *ctx_pg;
4971         struct bnxt_ctx_mem_info *ctx;
4972         uint32_t mem_size, ena, entries;
4973         uint32_t entries_sp, min;
4974         int i, rc;
4975
4976         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4977         if (rc) {
4978                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4979                 return rc;
4980         }
4981         ctx = bp->ctx;
4982         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4983                 return 0;
4984
4985         ctx_pg = &ctx->qp_mem;
4986         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4987         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4988         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4989         if (rc)
4990                 return rc;
4991
4992         ctx_pg = &ctx->srq_mem;
4993         ctx_pg->entries = ctx->srq_max_l2_entries;
4994         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4995         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4996         if (rc)
4997                 return rc;
4998
4999         ctx_pg = &ctx->cq_mem;
5000         ctx_pg->entries = ctx->cq_max_l2_entries;
5001         mem_size = ctx->cq_entry_size * ctx_pg->entries;
5002         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
5003         if (rc)
5004                 return rc;
5005
5006         ctx_pg = &ctx->vnic_mem;
5007         ctx_pg->entries = ctx->vnic_max_vnic_entries +
5008                 ctx->vnic_max_ring_table_entries;
5009         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
5010         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
5011         if (rc)
5012                 return rc;
5013
5014         ctx_pg = &ctx->stat_mem;
5015         ctx_pg->entries = ctx->stat_max_entries;
5016         mem_size = ctx->stat_entry_size * ctx_pg->entries;
5017         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
5018         if (rc)
5019                 return rc;
5020
5021         min = ctx->tqm_min_entries_per_ring;
5022
5023         entries_sp = ctx->qp_max_l2_entries +
5024                      ctx->vnic_max_vnic_entries +
5025                      2 * ctx->qp_min_qp1_entries + min;
5026         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
5027
5028         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
5029         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
5030         entries = clamp_t(uint32_t, entries, min,
5031                           ctx->tqm_max_entries_per_ring);
5032         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
5033                 ctx_pg = ctx->tqm_mem[i];
5034                 ctx_pg->entries = i ? entries : entries_sp;
5035                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
5036                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
5037                 if (rc)
5038                         return rc;
5039                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
5040         }
5041
5042         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
5043         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
5044         if (rc)
5045                 PMD_DRV_LOG(ERR,
5046                             "Failed to configure context mem: rc = %d\n", rc);
5047         else
5048                 ctx->flags |= BNXT_CTX_FLAG_INITED;
5049
5050         return rc;
5051 }
5052
5053 static int bnxt_alloc_stats_mem(struct bnxt *bp)
5054 {
5055         struct rte_pci_device *pci_dev = bp->pdev;
5056         char mz_name[RTE_MEMZONE_NAMESIZE];
5057         const struct rte_memzone *mz = NULL;
5058         uint32_t total_alloc_len;
5059         rte_iova_t mz_phys_addr;
5060
5061         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
5062                 return 0;
5063
5064         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5065                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5066                  pci_dev->addr.bus, pci_dev->addr.devid,
5067                  pci_dev->addr.function, "rx_port_stats");
5068         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5069         mz = rte_memzone_lookup(mz_name);
5070         total_alloc_len =
5071                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
5072                                        sizeof(struct rx_port_stats_ext) + 512);
5073         if (!mz) {
5074                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
5075                                          SOCKET_ID_ANY,
5076                                          RTE_MEMZONE_2MB |
5077                                          RTE_MEMZONE_SIZE_HINT_ONLY |
5078                                          RTE_MEMZONE_IOVA_CONTIG);
5079                 if (mz == NULL)
5080                         return -ENOMEM;
5081         }
5082         memset(mz->addr, 0, mz->len);
5083         mz_phys_addr = mz->iova;
5084
5085         bp->rx_mem_zone = (const void *)mz;
5086         bp->hw_rx_port_stats = mz->addr;
5087         bp->hw_rx_port_stats_map = mz_phys_addr;
5088
5089         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5090                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5091                  pci_dev->addr.bus, pci_dev->addr.devid,
5092                  pci_dev->addr.function, "tx_port_stats");
5093         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5094         mz = rte_memzone_lookup(mz_name);
5095         total_alloc_len =
5096                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
5097                                        sizeof(struct tx_port_stats_ext) + 512);
5098         if (!mz) {
5099                 mz = rte_memzone_reserve(mz_name,
5100                                          total_alloc_len,
5101                                          SOCKET_ID_ANY,
5102                                          RTE_MEMZONE_2MB |
5103                                          RTE_MEMZONE_SIZE_HINT_ONLY |
5104                                          RTE_MEMZONE_IOVA_CONTIG);
5105                 if (mz == NULL)
5106                         return -ENOMEM;
5107         }
5108         memset(mz->addr, 0, mz->len);
5109         mz_phys_addr = mz->iova;
5110
5111         bp->tx_mem_zone = (const void *)mz;
5112         bp->hw_tx_port_stats = mz->addr;
5113         bp->hw_tx_port_stats_map = mz_phys_addr;
5114         bp->flags |= BNXT_FLAG_PORT_STATS;
5115
5116         /* Display extended statistics if FW supports it */
5117         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
5118             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
5119             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
5120                 return 0;
5121
5122         bp->hw_rx_port_stats_ext = (void *)
5123                 ((uint8_t *)bp->hw_rx_port_stats +
5124                  sizeof(struct rx_port_stats));
5125         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
5126                 sizeof(struct rx_port_stats);
5127         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
5128
5129         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
5130             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
5131                 bp->hw_tx_port_stats_ext = (void *)
5132                         ((uint8_t *)bp->hw_tx_port_stats +
5133                          sizeof(struct tx_port_stats));
5134                 bp->hw_tx_port_stats_ext_map =
5135                         bp->hw_tx_port_stats_map +
5136                         sizeof(struct tx_port_stats);
5137                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
5138         }
5139
5140         return 0;
5141 }
5142
5143 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
5144 {
5145         struct bnxt *bp = eth_dev->data->dev_private;
5146         int rc = 0;
5147
5148         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
5149                                                RTE_ETHER_ADDR_LEN *
5150                                                bp->max_l2_ctx,
5151                                                0);
5152         if (eth_dev->data->mac_addrs == NULL) {
5153                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
5154                 return -ENOMEM;
5155         }
5156
5157         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
5158                 if (BNXT_PF(bp))
5159                         return -EINVAL;
5160
5161                 /* Generate a random MAC address, if none was assigned by PF */
5162                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5163                 bnxt_eth_hw_addr_random(bp->mac_addr);
5164                 PMD_DRV_LOG(INFO,
5165                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
5166                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5167                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5168
5169                 rc = bnxt_hwrm_set_mac(bp);
5170                 if (rc)
5171                         return rc;
5172         }
5173
5174         /* Copy the permanent MAC from the FUNC_QCAPS response */
5175         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5176
5177         return rc;
5178 }
5179
5180 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5181 {
5182         int rc = 0;
5183
5184         /* MAC is already configured in FW */
5185         if (BNXT_HAS_DFLT_MAC_SET(bp))
5186                 return 0;
5187
5188         /* Restore the old MAC configured */
5189         rc = bnxt_hwrm_set_mac(bp);
5190         if (rc)
5191                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5192
5193         return rc;
5194 }
5195
5196 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5197 {
5198         if (!BNXT_PF(bp))
5199                 return;
5200
5201 #define ALLOW_FUNC(x)   \
5202         { \
5203                 uint32_t arg = (x); \
5204                 bp->pf->vf_req_fwd[((arg) >> 5)] &= \
5205                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
5206         }
5207
5208         /* Forward all requests if firmware is new enough */
5209         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
5210              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
5211             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
5212                 memset(bp->pf->vf_req_fwd, 0xff, sizeof(bp->pf->vf_req_fwd));
5213         } else {
5214                 PMD_DRV_LOG(WARNING,
5215                             "Firmware too old for VF mailbox functionality\n");
5216                 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5217         }
5218
5219         /*
5220          * The following are used for driver cleanup. If we disallow these,
5221          * VF drivers can't clean up cleanly.
5222          */
5223         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
5224         ALLOW_FUNC(HWRM_VNIC_FREE);
5225         ALLOW_FUNC(HWRM_RING_FREE);
5226         ALLOW_FUNC(HWRM_RING_GRP_FREE);
5227         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
5228         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
5229         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
5230         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
5231         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
5232 }
5233
5234 uint16_t
5235 bnxt_get_svif(uint16_t port_id, bool func_svif,
5236               enum bnxt_ulp_intf_type type)
5237 {
5238         struct rte_eth_dev *eth_dev;
5239         struct bnxt *bp;
5240
5241         eth_dev = &rte_eth_devices[port_id];
5242         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5243                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5244                 if (!vfr)
5245                         return 0;
5246
5247                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5248                         return vfr->svif;
5249
5250                 eth_dev = vfr->parent_dev;
5251         }
5252
5253         bp = eth_dev->data->dev_private;
5254
5255         return func_svif ? bp->func_svif : bp->port_svif;
5256 }
5257
5258 uint16_t
5259 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5260 {
5261         struct rte_eth_dev *eth_dev;
5262         struct bnxt_vnic_info *vnic;
5263         struct bnxt *bp;
5264
5265         eth_dev = &rte_eth_devices[port];
5266         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5267                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5268                 if (!vfr)
5269                         return 0;
5270
5271                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5272                         return vfr->dflt_vnic_id;
5273
5274                 eth_dev = vfr->parent_dev;
5275         }
5276
5277         bp = eth_dev->data->dev_private;
5278
5279         vnic = BNXT_GET_DEFAULT_VNIC(bp);
5280
5281         return vnic->fw_vnic_id;
5282 }
5283
5284 uint16_t
5285 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5286 {
5287         struct rte_eth_dev *eth_dev;
5288         struct bnxt *bp;
5289
5290         eth_dev = &rte_eth_devices[port];
5291         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5292                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5293                 if (!vfr)
5294                         return 0;
5295
5296                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5297                         return vfr->fw_fid;
5298
5299                 eth_dev = vfr->parent_dev;
5300         }
5301
5302         bp = eth_dev->data->dev_private;
5303
5304         return bp->fw_fid;
5305 }
5306
5307 enum bnxt_ulp_intf_type
5308 bnxt_get_interface_type(uint16_t port)
5309 {
5310         struct rte_eth_dev *eth_dev;
5311         struct bnxt *bp;
5312
5313         eth_dev = &rte_eth_devices[port];
5314         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5315                 return BNXT_ULP_INTF_TYPE_VF_REP;
5316
5317         bp = eth_dev->data->dev_private;
5318         if (BNXT_PF(bp))
5319                 return BNXT_ULP_INTF_TYPE_PF;
5320         else if (BNXT_VF_IS_TRUSTED(bp))
5321                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5322         else if (BNXT_VF(bp))
5323                 return BNXT_ULP_INTF_TYPE_VF;
5324
5325         return BNXT_ULP_INTF_TYPE_INVALID;
5326 }
5327
5328 uint16_t
5329 bnxt_get_phy_port_id(uint16_t port_id)
5330 {
5331         struct bnxt_representor *vfr;
5332         struct rte_eth_dev *eth_dev;
5333         struct bnxt *bp;
5334
5335         eth_dev = &rte_eth_devices[port_id];
5336         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5337                 vfr = eth_dev->data->dev_private;
5338                 if (!vfr)
5339                         return 0;
5340
5341                 eth_dev = vfr->parent_dev;
5342         }
5343
5344         bp = eth_dev->data->dev_private;
5345
5346         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5347 }
5348
5349 uint16_t
5350 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5351 {
5352         struct rte_eth_dev *eth_dev;
5353         struct bnxt *bp;
5354
5355         eth_dev = &rte_eth_devices[port_id];
5356         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5357                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5358                 if (!vfr)
5359                         return 0;
5360
5361                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5362                         return vfr->fw_fid - 1;
5363
5364                 eth_dev = vfr->parent_dev;
5365         }
5366
5367         bp = eth_dev->data->dev_private;
5368
5369         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5370 }
5371
5372 uint16_t
5373 bnxt_get_vport(uint16_t port_id)
5374 {
5375         return (1 << bnxt_get_phy_port_id(port_id));
5376 }
5377
5378 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5379 {
5380         struct bnxt_error_recovery_info *info = bp->recovery_info;
5381
5382         if (info) {
5383                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5384                         memset(info, 0, sizeof(*info));
5385                 return;
5386         }
5387
5388         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5389                 return;
5390
5391         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5392                            sizeof(*info), 0);
5393         if (!info)
5394                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5395
5396         bp->recovery_info = info;
5397 }
5398
5399 static void bnxt_check_fw_status(struct bnxt *bp)
5400 {
5401         uint32_t fw_status;
5402
5403         if (!(bp->recovery_info &&
5404               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5405                 return;
5406
5407         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5408         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5409                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5410                             fw_status);
5411 }
5412
5413 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5414 {
5415         struct bnxt_error_recovery_info *info = bp->recovery_info;
5416         uint32_t status_loc;
5417         uint32_t sig_ver;
5418
5419         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5420                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5421         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5422                                    BNXT_GRCP_WINDOW_2_BASE +
5423                                    offsetof(struct hcomm_status,
5424                                             sig_ver)));
5425         /* If the signature is absent, then FW does not support this feature */
5426         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5427             HCOMM_STATUS_SIGNATURE_VAL)
5428                 return 0;
5429
5430         if (!info) {
5431                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5432                                    sizeof(*info), 0);
5433                 if (!info)
5434                         return -ENOMEM;
5435                 bp->recovery_info = info;
5436         } else {
5437                 memset(info, 0, sizeof(*info));
5438         }
5439
5440         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5441                                       BNXT_GRCP_WINDOW_2_BASE +
5442                                       offsetof(struct hcomm_status,
5443                                                fw_status_loc)));
5444
5445         /* Only pre-map the FW health status GRC register */
5446         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5447                 return 0;
5448
5449         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5450         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5451                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5452
5453         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5454                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5455
5456         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5457
5458         return 0;
5459 }
5460
5461 static int bnxt_init_fw(struct bnxt *bp)
5462 {
5463         uint16_t mtu;
5464         int rc = 0;
5465
5466         bp->fw_cap = 0;
5467
5468         rc = bnxt_map_hcomm_fw_status_reg(bp);
5469         if (rc)
5470                 return rc;
5471
5472         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5473         if (rc) {
5474                 bnxt_check_fw_status(bp);
5475                 return rc;
5476         }
5477
5478         rc = bnxt_hwrm_func_reset(bp);
5479         if (rc)
5480                 return -EIO;
5481
5482         rc = bnxt_hwrm_vnic_qcaps(bp);
5483         if (rc)
5484                 return rc;
5485
5486         rc = bnxt_hwrm_queue_qportcfg(bp);
5487         if (rc)
5488                 return rc;
5489
5490         /* Get the MAX capabilities for this function.
5491          * This function also allocates context memory for TQM rings and
5492          * informs the firmware about this allocated backing store memory.
5493          */
5494         rc = bnxt_hwrm_func_qcaps(bp);
5495         if (rc)
5496                 return rc;
5497
5498         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5499         if (rc)
5500                 return rc;
5501
5502         bnxt_hwrm_port_mac_qcfg(bp);
5503
5504         bnxt_hwrm_parent_pf_qcfg(bp);
5505
5506         bnxt_hwrm_port_phy_qcaps(bp);
5507
5508         bnxt_alloc_error_recovery_info(bp);
5509         /* Get the adapter error recovery support info */
5510         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5511         if (rc)
5512                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5513
5514         bnxt_hwrm_port_led_qcaps(bp);
5515
5516         return 0;
5517 }
5518
5519 static int
5520 bnxt_init_locks(struct bnxt *bp)
5521 {
5522         int err;
5523
5524         err = pthread_mutex_init(&bp->flow_lock, NULL);
5525         if (err) {
5526                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5527                 return err;
5528         }
5529
5530         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5531         if (err)
5532                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5533
5534         err = pthread_mutex_init(&bp->health_check_lock, NULL);
5535         if (err)
5536                 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5537         return err;
5538 }
5539
5540 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5541 {
5542         int rc = 0;
5543
5544         rc = bnxt_init_fw(bp);
5545         if (rc)
5546                 return rc;
5547
5548         if (!reconfig_dev) {
5549                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5550                 if (rc)
5551                         return rc;
5552         } else {
5553                 rc = bnxt_restore_dflt_mac(bp);
5554                 if (rc)
5555                         return rc;
5556         }
5557
5558         bnxt_config_vf_req_fwd(bp);
5559
5560         rc = bnxt_hwrm_func_driver_register(bp);
5561         if (rc) {
5562                 PMD_DRV_LOG(ERR, "Failed to register driver");
5563                 return -EBUSY;
5564         }
5565
5566         if (BNXT_PF(bp)) {
5567                 if (bp->pdev->max_vfs) {
5568                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5569                         if (rc) {
5570                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5571                                 return rc;
5572                         }
5573                 } else {
5574                         rc = bnxt_hwrm_allocate_pf_only(bp);
5575                         if (rc) {
5576                                 PMD_DRV_LOG(ERR,
5577                                             "Failed to allocate PF resources");
5578                                 return rc;
5579                         }
5580                 }
5581         }
5582
5583         rc = bnxt_alloc_mem(bp, reconfig_dev);
5584         if (rc)
5585                 return rc;
5586
5587         rc = bnxt_setup_int(bp);
5588         if (rc)
5589                 return rc;
5590
5591         rc = bnxt_request_int(bp);
5592         if (rc)
5593                 return rc;
5594
5595         rc = bnxt_init_ctx_mem(bp);
5596         if (rc) {
5597                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5598                 return rc;
5599         }
5600
5601         rc = bnxt_init_locks(bp);
5602         if (rc)
5603                 return rc;
5604
5605         return 0;
5606 }
5607
5608 static int
5609 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5610                           const char *value, void *opaque_arg)
5611 {
5612         struct bnxt *bp = opaque_arg;
5613         unsigned long truflow;
5614         char *end = NULL;
5615
5616         if (!value || !opaque_arg) {
5617                 PMD_DRV_LOG(ERR,
5618                             "Invalid parameter passed to truflow devargs.\n");
5619                 return -EINVAL;
5620         }
5621
5622         truflow = strtoul(value, &end, 10);
5623         if (end == NULL || *end != '\0' ||
5624             (truflow == ULONG_MAX && errno == ERANGE)) {
5625                 PMD_DRV_LOG(ERR,
5626                             "Invalid parameter passed to truflow devargs.\n");
5627                 return -EINVAL;
5628         }
5629
5630         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5631                 PMD_DRV_LOG(ERR,
5632                             "Invalid value passed to truflow devargs.\n");
5633                 return -EINVAL;
5634         }
5635
5636         if (truflow) {
5637                 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5638                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5639         } else {
5640                 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
5641                 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
5642         }
5643
5644         return 0;
5645 }
5646
5647 static int
5648 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5649                              const char *value, void *opaque_arg)
5650 {
5651         struct bnxt *bp = opaque_arg;
5652         unsigned long flow_xstat;
5653         char *end = NULL;
5654
5655         if (!value || !opaque_arg) {
5656                 PMD_DRV_LOG(ERR,
5657                             "Invalid parameter passed to flow_xstat devarg.\n");
5658                 return -EINVAL;
5659         }
5660
5661         flow_xstat = strtoul(value, &end, 10);
5662         if (end == NULL || *end != '\0' ||
5663             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5664                 PMD_DRV_LOG(ERR,
5665                             "Invalid parameter passed to flow_xstat devarg.\n");
5666                 return -EINVAL;
5667         }
5668
5669         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5670                 PMD_DRV_LOG(ERR,
5671                             "Invalid value passed to flow_xstat devarg.\n");
5672                 return -EINVAL;
5673         }
5674
5675         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5676         if (BNXT_FLOW_XSTATS_EN(bp))
5677                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5678
5679         return 0;
5680 }
5681
5682 static int
5683 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5684                                         const char *value, void *opaque_arg)
5685 {
5686         struct bnxt *bp = opaque_arg;
5687         unsigned long max_num_kflows;
5688         char *end = NULL;
5689
5690         if (!value || !opaque_arg) {
5691                 PMD_DRV_LOG(ERR,
5692                         "Invalid parameter passed to max_num_kflows devarg.\n");
5693                 return -EINVAL;
5694         }
5695
5696         max_num_kflows = strtoul(value, &end, 10);
5697         if (end == NULL || *end != '\0' ||
5698                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5699                 PMD_DRV_LOG(ERR,
5700                         "Invalid parameter passed to max_num_kflows devarg.\n");
5701                 return -EINVAL;
5702         }
5703
5704         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5705                 PMD_DRV_LOG(ERR,
5706                         "Invalid value passed to max_num_kflows devarg.\n");
5707                 return -EINVAL;
5708         }
5709
5710         bp->max_num_kflows = max_num_kflows;
5711         if (bp->max_num_kflows)
5712                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5713                                 max_num_kflows);
5714
5715         return 0;
5716 }
5717
5718 static int
5719 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5720                             const char *value, void *opaque_arg)
5721 {
5722         struct bnxt_representor *vfr_bp = opaque_arg;
5723         unsigned long rep_is_pf;
5724         char *end = NULL;
5725
5726         if (!value || !opaque_arg) {
5727                 PMD_DRV_LOG(ERR,
5728                             "Invalid parameter passed to rep_is_pf devargs.\n");
5729                 return -EINVAL;
5730         }
5731
5732         rep_is_pf = strtoul(value, &end, 10);
5733         if (end == NULL || *end != '\0' ||
5734             (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5735                 PMD_DRV_LOG(ERR,
5736                             "Invalid parameter passed to rep_is_pf devargs.\n");
5737                 return -EINVAL;
5738         }
5739
5740         if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5741                 PMD_DRV_LOG(ERR,
5742                             "Invalid value passed to rep_is_pf devargs.\n");
5743                 return -EINVAL;
5744         }
5745
5746         vfr_bp->flags |= rep_is_pf;
5747         if (BNXT_REP_PF(vfr_bp))
5748                 PMD_DRV_LOG(INFO, "PF representor\n");
5749         else
5750                 PMD_DRV_LOG(INFO, "VF representor\n");
5751
5752         return 0;
5753 }
5754
5755 static int
5756 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5757                                const char *value, void *opaque_arg)
5758 {
5759         struct bnxt_representor *vfr_bp = opaque_arg;
5760         unsigned long rep_based_pf;
5761         char *end = NULL;
5762
5763         if (!value || !opaque_arg) {
5764                 PMD_DRV_LOG(ERR,
5765                             "Invalid parameter passed to rep_based_pf "
5766                             "devargs.\n");
5767                 return -EINVAL;
5768         }
5769
5770         rep_based_pf = strtoul(value, &end, 10);
5771         if (end == NULL || *end != '\0' ||
5772             (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5773                 PMD_DRV_LOG(ERR,
5774                             "Invalid parameter passed to rep_based_pf "
5775                             "devargs.\n");
5776                 return -EINVAL;
5777         }
5778
5779         if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5780                 PMD_DRV_LOG(ERR,
5781                             "Invalid value passed to rep_based_pf devargs.\n");
5782                 return -EINVAL;
5783         }
5784
5785         vfr_bp->rep_based_pf = rep_based_pf;
5786         PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5787
5788         return 0;
5789 }
5790
5791 static int
5792 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5793                             const char *value, void *opaque_arg)
5794 {
5795         struct bnxt_representor *vfr_bp = opaque_arg;
5796         unsigned long rep_q_r2f;
5797         char *end = NULL;
5798
5799         if (!value || !opaque_arg) {
5800                 PMD_DRV_LOG(ERR,
5801                             "Invalid parameter passed to rep_q_r2f "
5802                             "devargs.\n");
5803                 return -EINVAL;
5804         }
5805
5806         rep_q_r2f = strtoul(value, &end, 10);
5807         if (end == NULL || *end != '\0' ||
5808             (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5809                 PMD_DRV_LOG(ERR,
5810                             "Invalid parameter passed to rep_q_r2f "
5811                             "devargs.\n");
5812                 return -EINVAL;
5813         }
5814
5815         if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5816                 PMD_DRV_LOG(ERR,
5817                             "Invalid value passed to rep_q_r2f devargs.\n");
5818                 return -EINVAL;
5819         }
5820
5821         vfr_bp->rep_q_r2f = rep_q_r2f;
5822         vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5823         PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5824
5825         return 0;
5826 }
5827
5828 static int
5829 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5830                             const char *value, void *opaque_arg)
5831 {
5832         struct bnxt_representor *vfr_bp = opaque_arg;
5833         unsigned long rep_q_f2r;
5834         char *end = NULL;
5835
5836         if (!value || !opaque_arg) {
5837                 PMD_DRV_LOG(ERR,
5838                             "Invalid parameter passed to rep_q_f2r "
5839                             "devargs.\n");
5840                 return -EINVAL;
5841         }
5842
5843         rep_q_f2r = strtoul(value, &end, 10);
5844         if (end == NULL || *end != '\0' ||
5845             (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5846                 PMD_DRV_LOG(ERR,
5847                             "Invalid parameter passed to rep_q_f2r "
5848                             "devargs.\n");
5849                 return -EINVAL;
5850         }
5851
5852         if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5853                 PMD_DRV_LOG(ERR,
5854                             "Invalid value passed to rep_q_f2r devargs.\n");
5855                 return -EINVAL;
5856         }
5857
5858         vfr_bp->rep_q_f2r = rep_q_f2r;
5859         vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5860         PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5861
5862         return 0;
5863 }
5864
5865 static int
5866 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5867                              const char *value, void *opaque_arg)
5868 {
5869         struct bnxt_representor *vfr_bp = opaque_arg;
5870         unsigned long rep_fc_r2f;
5871         char *end = NULL;
5872
5873         if (!value || !opaque_arg) {
5874                 PMD_DRV_LOG(ERR,
5875                             "Invalid parameter passed to rep_fc_r2f "
5876                             "devargs.\n");
5877                 return -EINVAL;
5878         }
5879
5880         rep_fc_r2f = strtoul(value, &end, 10);
5881         if (end == NULL || *end != '\0' ||
5882             (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5883                 PMD_DRV_LOG(ERR,
5884                             "Invalid parameter passed to rep_fc_r2f "
5885                             "devargs.\n");
5886                 return -EINVAL;
5887         }
5888
5889         if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5890                 PMD_DRV_LOG(ERR,
5891                             "Invalid value passed to rep_fc_r2f devargs.\n");
5892                 return -EINVAL;
5893         }
5894
5895         vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5896         vfr_bp->rep_fc_r2f = rep_fc_r2f;
5897         PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5898
5899         return 0;
5900 }
5901
5902 static int
5903 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5904                              const char *value, void *opaque_arg)
5905 {
5906         struct bnxt_representor *vfr_bp = opaque_arg;
5907         unsigned long rep_fc_f2r;
5908         char *end = NULL;
5909
5910         if (!value || !opaque_arg) {
5911                 PMD_DRV_LOG(ERR,
5912                             "Invalid parameter passed to rep_fc_f2r "
5913                             "devargs.\n");
5914                 return -EINVAL;
5915         }
5916
5917         rep_fc_f2r = strtoul(value, &end, 10);
5918         if (end == NULL || *end != '\0' ||
5919             (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5920                 PMD_DRV_LOG(ERR,
5921                             "Invalid parameter passed to rep_fc_f2r "
5922                             "devargs.\n");
5923                 return -EINVAL;
5924         }
5925
5926         if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5927                 PMD_DRV_LOG(ERR,
5928                             "Invalid value passed to rep_fc_f2r devargs.\n");
5929                 return -EINVAL;
5930         }
5931
5932         vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5933         vfr_bp->rep_fc_f2r = rep_fc_f2r;
5934         PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5935
5936         return 0;
5937 }
5938
5939 static void
5940 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5941 {
5942         struct rte_kvargs *kvlist;
5943
5944         if (devargs == NULL)
5945                 return;
5946
5947         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5948         if (kvlist == NULL)
5949                 return;
5950
5951         /*
5952          * Handler for "truflow" devarg.
5953          * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1"
5954          */
5955         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5956                            bnxt_parse_devarg_truflow, bp);
5957
5958         /*
5959          * Handler for "flow_xstat" devarg.
5960          * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1"
5961          */
5962         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5963                            bnxt_parse_devarg_flow_xstat, bp);
5964
5965         /*
5966          * Handler for "max_num_kflows" devarg.
5967          * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32"
5968          */
5969         rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5970                            bnxt_parse_devarg_max_num_kflows, bp);
5971
5972         rte_kvargs_free(kvlist);
5973 }
5974
5975 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5976 {
5977         int rc = 0;
5978
5979         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5980                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5981                 if (rc)
5982                         PMD_DRV_LOG(ERR,
5983                                     "Failed to alloc switch domain: %d\n", rc);
5984                 else
5985                         PMD_DRV_LOG(INFO,
5986                                     "Switch domain allocated %d\n",
5987                                     bp->switch_domain_id);
5988         }
5989
5990         return rc;
5991 }
5992
5993 static int
5994 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5995 {
5996         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5997         static int version_printed;
5998         struct bnxt *bp;
5999         int rc;
6000
6001         if (version_printed++ == 0)
6002                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
6003
6004         eth_dev->dev_ops = &bnxt_dev_ops;
6005         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
6006         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
6007         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
6008         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
6009         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
6010
6011         /*
6012          * For secondary processes, we don't initialise any further
6013          * as primary has already done this work.
6014          */
6015         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6016                 return 0;
6017
6018         rte_eth_copy_pci_info(eth_dev, pci_dev);
6019
6020         bp = eth_dev->data->dev_private;
6021
6022         /* Parse dev arguments passed on when starting the DPDK application. */
6023         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
6024
6025         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
6026
6027         if (bnxt_vf_pciid(pci_dev->id.device_id))
6028                 bp->flags |= BNXT_FLAG_VF;
6029
6030         if (bnxt_thor_device(pci_dev->id.device_id))
6031                 bp->flags |= BNXT_FLAG_THOR_CHIP;
6032
6033         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
6034             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
6035             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
6036             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
6037                 bp->flags |= BNXT_FLAG_STINGRAY;
6038
6039         rc = bnxt_init_board(eth_dev);
6040         if (rc) {
6041                 PMD_DRV_LOG(ERR,
6042                             "Failed to initialize board rc: %x\n", rc);
6043                 return rc;
6044         }
6045
6046         rc = bnxt_alloc_pf_info(bp);
6047         if (rc)
6048                 goto error_free;
6049
6050         rc = bnxt_alloc_link_info(bp);
6051         if (rc)
6052                 goto error_free;
6053
6054         rc = bnxt_alloc_parent_info(bp);
6055         if (rc)
6056                 goto error_free;
6057
6058         rc = bnxt_alloc_hwrm_resources(bp);
6059         if (rc) {
6060                 PMD_DRV_LOG(ERR,
6061                             "Failed to allocate hwrm resource rc: %x\n", rc);
6062                 goto error_free;
6063         }
6064         rc = bnxt_alloc_leds_info(bp);
6065         if (rc)
6066                 goto error_free;
6067
6068         rc = bnxt_alloc_cos_queues(bp);
6069         if (rc)
6070                 goto error_free;
6071
6072         rc = bnxt_init_resources(bp, false);
6073         if (rc)
6074                 goto error_free;
6075
6076         rc = bnxt_alloc_stats_mem(bp);
6077         if (rc)
6078                 goto error_free;
6079
6080         bnxt_alloc_switch_domain(bp);
6081
6082         PMD_DRV_LOG(INFO,
6083                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
6084                     pci_dev->mem_resource[0].phys_addr,
6085                     pci_dev->mem_resource[0].addr);
6086
6087         return 0;
6088
6089 error_free:
6090         bnxt_dev_uninit(eth_dev);
6091         return rc;
6092 }
6093
6094
6095 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
6096 {
6097         if (!ctx)
6098                 return;
6099
6100         if (ctx->va)
6101                 rte_free(ctx->va);
6102
6103         ctx->va = NULL;
6104         ctx->dma = RTE_BAD_IOVA;
6105         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
6106 }
6107
6108 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
6109 {
6110         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
6111                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6112                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
6113                                   bp->flow_stat->max_fc,
6114                                   false);
6115
6116         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
6117                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6118                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
6119                                   bp->flow_stat->max_fc,
6120                                   false);
6121
6122         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6123                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
6124         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6125
6126         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6127                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
6128         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6129
6130         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6131                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
6132         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6133
6134         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6135                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
6136         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6137 }
6138
6139 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
6140 {
6141         bnxt_unregister_fc_ctx_mem(bp);
6142
6143         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
6144         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
6145         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
6146         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
6147 }
6148
6149 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
6150 {
6151         if (BNXT_FLOW_XSTATS_EN(bp))
6152                 bnxt_uninit_fc_ctx_mem(bp);
6153 }
6154
6155 static void
6156 bnxt_free_error_recovery_info(struct bnxt *bp)
6157 {
6158         rte_free(bp->recovery_info);
6159         bp->recovery_info = NULL;
6160         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
6161 }
6162
6163 static void
6164 bnxt_uninit_locks(struct bnxt *bp)
6165 {
6166         pthread_mutex_destroy(&bp->flow_lock);
6167         pthread_mutex_destroy(&bp->def_cp_lock);
6168         pthread_mutex_destroy(&bp->health_check_lock);
6169         if (bp->rep_info) {
6170                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
6171                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
6172         }
6173 }
6174
6175 static int
6176 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
6177 {
6178         int rc;
6179
6180         bnxt_free_int(bp);
6181         bnxt_free_mem(bp, reconfig_dev);
6182         bnxt_hwrm_func_buf_unrgtr(bp);
6183         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
6184         bp->flags &= ~BNXT_FLAG_REGISTERED;
6185         bnxt_free_ctx_mem(bp);
6186         if (!reconfig_dev) {
6187                 bnxt_free_hwrm_resources(bp);
6188                 bnxt_free_error_recovery_info(bp);
6189         }
6190
6191         bnxt_uninit_ctx_mem(bp);
6192
6193         bnxt_uninit_locks(bp);
6194         bnxt_free_flow_stats_info(bp);
6195         bnxt_free_rep_info(bp);
6196         rte_free(bp->ptp_cfg);
6197         bp->ptp_cfg = NULL;
6198         return rc;
6199 }
6200
6201 static int
6202 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
6203 {
6204         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6205                 return -EPERM;
6206
6207         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
6208
6209         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
6210                 bnxt_dev_close_op(eth_dev);
6211
6212         return 0;
6213 }
6214
6215 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
6216 {
6217         struct bnxt *bp = eth_dev->data->dev_private;
6218         struct rte_eth_dev *vf_rep_eth_dev;
6219         int ret = 0, i;
6220
6221         if (!bp)
6222                 return -EINVAL;
6223
6224         for (i = 0; i < bp->num_reps; i++) {
6225                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
6226                 if (!vf_rep_eth_dev)
6227                         continue;
6228                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
6229                             vf_rep_eth_dev->data->port_id);
6230                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
6231         }
6232         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
6233                     eth_dev->data->port_id);
6234         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
6235
6236         return ret;
6237 }
6238
6239 static void bnxt_free_rep_info(struct bnxt *bp)
6240 {
6241         rte_free(bp->rep_info);
6242         bp->rep_info = NULL;
6243         rte_free(bp->cfa_code_map);
6244         bp->cfa_code_map = NULL;
6245 }
6246
6247 static int bnxt_init_rep_info(struct bnxt *bp)
6248 {
6249         int i = 0, rc;
6250
6251         if (bp->rep_info)
6252                 return 0;
6253
6254         bp->rep_info = rte_zmalloc("bnxt_rep_info",
6255                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
6256                                    0);
6257         if (!bp->rep_info) {
6258                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
6259                 return -ENOMEM;
6260         }
6261         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
6262                                        sizeof(*bp->cfa_code_map) *
6263                                        BNXT_MAX_CFA_CODE, 0);
6264         if (!bp->cfa_code_map) {
6265                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
6266                 bnxt_free_rep_info(bp);
6267                 return -ENOMEM;
6268         }
6269
6270         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
6271                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
6272
6273         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
6274         if (rc) {
6275                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
6276                 bnxt_free_rep_info(bp);
6277                 return rc;
6278         }
6279
6280         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
6281         if (rc) {
6282                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
6283                 bnxt_free_rep_info(bp);
6284                 return rc;
6285         }
6286
6287         return rc;
6288 }
6289
6290 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
6291                                struct rte_eth_devargs eth_da,
6292                                struct rte_eth_dev *backing_eth_dev,
6293                                const char *dev_args)
6294 {
6295         struct rte_eth_dev *vf_rep_eth_dev;
6296         char name[RTE_ETH_NAME_MAX_LEN];
6297         struct bnxt *backing_bp;
6298         uint16_t num_rep;
6299         int i, ret = 0;
6300         struct rte_kvargs *kvlist;
6301
6302         num_rep = eth_da.nb_representor_ports;
6303         if (num_rep > BNXT_MAX_VF_REPS) {
6304                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
6305                             num_rep, BNXT_MAX_VF_REPS);
6306                 return -EINVAL;
6307         }
6308
6309         if (num_rep >= RTE_MAX_ETHPORTS) {
6310                 PMD_DRV_LOG(ERR,
6311                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6312                             num_rep, RTE_MAX_ETHPORTS);
6313                 return -EINVAL;
6314         }
6315
6316         backing_bp = backing_eth_dev->data->dev_private;
6317
6318         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6319                 PMD_DRV_LOG(ERR,
6320                             "Not a PF or trusted VF. No Representor support\n");
6321                 /* Returning an error is not an option.
6322                  * Applications are not handling this correctly
6323                  */
6324                 return 0;
6325         }
6326
6327         if (bnxt_init_rep_info(backing_bp))
6328                 return 0;
6329
6330         for (i = 0; i < num_rep; i++) {
6331                 struct bnxt_representor representor = {
6332                         .vf_id = eth_da.representor_ports[i],
6333                         .switch_domain_id = backing_bp->switch_domain_id,
6334                         .parent_dev = backing_eth_dev
6335                 };
6336
6337                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6338                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6339                                     representor.vf_id, BNXT_MAX_VF_REPS);
6340                         continue;
6341                 }
6342
6343                 /* representor port net_bdf_port */
6344                 snprintf(name, sizeof(name), "net_%s_representor_%d",
6345                          pci_dev->device.name, eth_da.representor_ports[i]);
6346
6347                 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
6348                 if (kvlist) {
6349                         /*
6350                          * Handler for "rep_is_pf" devarg.
6351                          * Invoked as for ex: "-w 000:00:0d.0,
6352                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6353                          */
6354                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
6355                                            bnxt_parse_devarg_rep_is_pf,
6356                                            (void *)&representor);
6357                         /*
6358                          * Handler for "rep_based_pf" devarg.
6359                          * Invoked as for ex: "-w 000:00:0d.0,
6360                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6361                          */
6362                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_BASED_PF,
6363                                            bnxt_parse_devarg_rep_based_pf,
6364                                            (void *)&representor);
6365                         /*
6366                          * Handler for "rep_based_pf" devarg.
6367                          * Invoked as for ex: "-w 000:00:0d.0,
6368                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6369                          */
6370                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
6371                                            bnxt_parse_devarg_rep_q_r2f,
6372                                            (void *)&representor);
6373                         /*
6374                          * Handler for "rep_based_pf" devarg.
6375                          * Invoked as for ex: "-w 000:00:0d.0,
6376                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6377                          */
6378                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
6379                                            bnxt_parse_devarg_rep_q_f2r,
6380                                            (void *)&representor);
6381                         /*
6382                          * Handler for "rep_based_pf" devarg.
6383                          * Invoked as for ex: "-w 000:00:0d.0,
6384                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6385                          */
6386                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
6387                                            bnxt_parse_devarg_rep_fc_r2f,
6388                                            (void *)&representor);
6389                         /*
6390                          * Handler for "rep_based_pf" devarg.
6391                          * Invoked as for ex: "-w 000:00:0d.0,
6392                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6393                          */
6394                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
6395                                            bnxt_parse_devarg_rep_fc_f2r,
6396                                            (void *)&representor);
6397                 }
6398
6399                 ret = rte_eth_dev_create(&pci_dev->device, name,
6400                                          sizeof(struct bnxt_representor),
6401                                          NULL, NULL,
6402                                          bnxt_representor_init,
6403                                          &representor);
6404                 if (ret) {
6405                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6406                                     "representor %s.", name);
6407                         goto err;
6408                 }
6409
6410                 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6411                 if (!vf_rep_eth_dev) {
6412                         PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6413                                     " for VF-Rep: %s.", name);
6414                         ret = -ENODEV;
6415                         goto err;
6416                 }
6417
6418                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6419                             backing_eth_dev->data->port_id);
6420                 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6421                                                          vf_rep_eth_dev;
6422                 backing_bp->num_reps++;
6423
6424         }
6425
6426         return 0;
6427
6428 err:
6429         /* If num_rep > 1, then rollback already created
6430          * ports, since we'll be failing the probe anyway
6431          */
6432         if (num_rep > 1)
6433                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6434
6435         return ret;
6436 }
6437
6438 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6439                           struct rte_pci_device *pci_dev)
6440 {
6441         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6442         struct rte_eth_dev *backing_eth_dev;
6443         uint16_t num_rep;
6444         int ret = 0;
6445
6446         if (pci_dev->device.devargs) {
6447                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6448                                             &eth_da);
6449                 if (ret)
6450                         return ret;
6451         }
6452
6453         num_rep = eth_da.nb_representor_ports;
6454         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6455                     num_rep);
6456
6457         /* We could come here after first level of probe is already invoked
6458          * as part of an application bringup(OVS-DPDK vswitchd), so first check
6459          * for already allocated eth_dev for the backing device (PF/Trusted VF)
6460          */
6461         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6462         if (backing_eth_dev == NULL) {
6463                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6464                                          sizeof(struct bnxt),
6465                                          eth_dev_pci_specific_init, pci_dev,
6466                                          bnxt_dev_init, NULL);
6467
6468                 if (ret || !num_rep)
6469                         return ret;
6470
6471                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6472         }
6473         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6474                     backing_eth_dev->data->port_id);
6475
6476         if (!num_rep)
6477                 return ret;
6478
6479         /* probe representor ports now */
6480         ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev,
6481                                   pci_dev->device.devargs->args);
6482
6483         return ret;
6484 }
6485
6486 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6487 {
6488         struct rte_eth_dev *eth_dev;
6489
6490         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6491         if (!eth_dev)
6492                 return 0; /* Invoked typically only by OVS-DPDK, by the
6493                            * time it comes here the eth_dev is already
6494                            * deleted by rte_eth_dev_close(), so returning
6495                            * +ve value will at least help in proper cleanup
6496                            */
6497
6498         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6499         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6500                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6501                         return rte_eth_dev_destroy(eth_dev,
6502                                                    bnxt_representor_uninit);
6503                 else
6504                         return rte_eth_dev_destroy(eth_dev,
6505                                                    bnxt_dev_uninit);
6506         } else {
6507                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6508         }
6509 }
6510
6511 static struct rte_pci_driver bnxt_rte_pmd = {
6512         .id_table = bnxt_pci_id_map,
6513         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6514                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6515                                                   * and OVS-DPDK
6516                                                   */
6517         .probe = bnxt_pci_probe,
6518         .remove = bnxt_pci_remove,
6519 };
6520
6521 static bool
6522 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6523 {
6524         if (strcmp(dev->device->driver->name, drv->driver.name))
6525                 return false;
6526
6527         return true;
6528 }
6529
6530 bool is_bnxt_supported(struct rte_eth_dev *dev)
6531 {
6532         return is_device_supported(dev, &bnxt_rte_pmd);
6533 }
6534
6535 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
6536 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6537 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6538 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");