drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <ethdev_driver.h>
  11 #include <ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16 #include <rte_vect.h>
  17
  18 #include "bnxt.h"
  19 #include "bnxt_filter.h"
  20 #include "bnxt_hwrm.h"
  21 #include "bnxt_irq.h"
  22 #include "bnxt_reps.h"
  23 #include "bnxt_ring.h"
  24 #include "bnxt_rxq.h"
  25 #include "bnxt_rxr.h"
  26 #include "bnxt_stats.h"
  27 #include "bnxt_txq.h"
  28 #include "bnxt_txr.h"
  29 #include "bnxt_vnic.h"
  30 #include "hsi_struct_def_dpdk.h"
  31 #include "bnxt_nvm_defs.h"
  32 #include "bnxt_tf_common.h"
  33 #include "ulp_flow_db.h"
  34 #include "rte_pmd_bnxt.h"
  35
  36 #define DRV_MODULE_NAME         "bnxt"
  37 static const char bnxt_version[] =
  38         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  39
  40 /*
  41  * The set of PCI devices this driver supports
  42  */
  43 static const struct rte_pci_id bnxt_pci_id_map[] = {
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  47                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
  87         { .vendor_id = 0, /* sentinel */ },
  88 };
  89
  90 #define BNXT_DEVARG_ACCUM_STATS "accum-stats"
  91 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
  92 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
  93 #define BNXT_DEVARG_REPRESENTOR "representor"
  94 #define BNXT_DEVARG_REP_BASED_PF  "rep-based-pf"
  95 #define BNXT_DEVARG_REP_IS_PF  "rep-is-pf"
  96 #define BNXT_DEVARG_REP_Q_R2F  "rep-q-r2f"
  97 #define BNXT_DEVARG_REP_Q_F2R  "rep-q-f2r"
  98 #define BNXT_DEVARG_REP_FC_R2F  "rep-fc-r2f"
  99 #define BNXT_DEVARG_REP_FC_F2R  "rep-fc-f2r"
 100 #define BNXT_DEVARG_APP_ID      "app-id"
 101
 102 static const char *const bnxt_dev_args[] = {
 103         BNXT_DEVARG_REPRESENTOR,
 104         BNXT_DEVARG_ACCUM_STATS,
 105         BNXT_DEVARG_FLOW_XSTAT,
 106         BNXT_DEVARG_MAX_NUM_KFLOWS,
 107         BNXT_DEVARG_REP_BASED_PF,
 108         BNXT_DEVARG_REP_IS_PF,
 109         BNXT_DEVARG_REP_Q_R2F,
 110         BNXT_DEVARG_REP_Q_F2R,
 111         BNXT_DEVARG_REP_FC_R2F,
 112         BNXT_DEVARG_REP_FC_F2R,
 113         BNXT_DEVARG_APP_ID,
 114         NULL
 115 };
 116
 117 /*
 118  * accum-stats == false to disable flow counter accumulation
 119  * accum-stats == true to enable flow counter accumulation
 120  */
 121 #define BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats)    ((accum_stats) > 1)
 122
 123 /*
 124  * app-id = an non-negative 8-bit number
 125  */
 126 #define BNXT_DEVARG_APP_ID_INVALID(val)                 ((val) > 255)
 127
 128 /*
 129  * flow_xstat == false to disable the feature
 130  * flow_xstat == true to enable the feature
 131  */
 132 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 133
 134 /*
 135  * rep_is_pf == false to indicate VF representor
 136  * rep_is_pf == true to indicate PF representor
 137  */
 138 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)        ((rep_is_pf) > 1)
 139
 140 /*
 141  * rep_based_pf == Physical index of the PF
 142  */
 143 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)  ((rep_based_pf) > 15)
 144 /*
 145  * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
 146  */
 147 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)        ((rep_q_r2f) > 3)
 148
 149 /*
 150  * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
 151  */
 152 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)        ((rep_q_f2r) > 3)
 153
 154 /*
 155  * rep_fc_r2f == Flow control for the representor to endpoint direction
 156  */
 157 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)      ((rep_fc_r2f) > 1)
 158
 159 /*
 160  * rep_fc_f2r == Flow control for the endpoint to representor direction
 161  */
 162 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)      ((rep_fc_f2r) > 1)
 163
 164 int bnxt_cfa_code_dynfield_offset = -1;
 165
 166 /*
 167  * max_num_kflows must be >= 32
 168  * and must be a power-of-2 supported value
 169  * return: 1 -> invalid
 170  *         0 -> valid
 171  */
 172 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 173 {
 174         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 175                 return 1;
 176         return 0;
 177 }
 178
 179 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 180 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 181 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 182 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 183 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 184 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 185 static void bnxt_dev_recover(void *arg);
 186 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 187 static void bnxt_free_rep_info(struct bnxt *bp);
 188
 189 int is_bnxt_in_error(struct bnxt *bp)
 190 {
 191         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 192                 return -EIO;
 193         if (bp->flags & BNXT_FLAG_FW_RESET)
 194                 return -EBUSY;
 195
 196         return 0;
 197 }
 198
 199 /***********************/
 200
 201 /*
 202  * High level utility functions
 203  */
 204
 205 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 206 {
 207         unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
 208                                              BNXT_RSS_TBL_SIZE_P5);
 209
 210         if (!BNXT_CHIP_P5(bp))
 211                 return 1;
 212
 213         return RTE_ALIGN_MUL_CEIL(num_rss_rings,
 214                                   BNXT_RSS_ENTRIES_PER_CTX_P5) /
 215                                   BNXT_RSS_ENTRIES_PER_CTX_P5;
 216 }
 217
 218 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 219 {
 220         if (!BNXT_CHIP_P5(bp))
 221                 return HW_HASH_INDEX_SIZE;
 222
 223         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
 224 }
 225
 226 static void bnxt_free_parent_info(struct bnxt *bp)
 227 {
 228         rte_free(bp->parent);
 229         bp->parent = NULL;
 230 }
 231
 232 static void bnxt_free_pf_info(struct bnxt *bp)
 233 {
 234         rte_free(bp->pf);
 235         bp->pf = NULL;
 236 }
 237
 238 static void bnxt_free_link_info(struct bnxt *bp)
 239 {
 240         rte_free(bp->link_info);
 241         bp->link_info = NULL;
 242 }
 243
 244 static void bnxt_free_leds_info(struct bnxt *bp)
 245 {
 246         if (BNXT_VF(bp))
 247                 return;
 248
 249         rte_free(bp->leds);
 250         bp->leds = NULL;
 251 }
 252
 253 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 254 {
 255         rte_free(bp->flow_stat);
 256         bp->flow_stat = NULL;
 257 }
 258
 259 static void bnxt_free_cos_queues(struct bnxt *bp)
 260 {
 261         rte_free(bp->rx_cos_queue);
 262         bp->rx_cos_queue = NULL;
 263         rte_free(bp->tx_cos_queue);
 264         bp->tx_cos_queue = NULL;
 265 }
 266
 267 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 268 {
 269         bnxt_free_filter_mem(bp);
 270         bnxt_free_vnic_attributes(bp);
 271         bnxt_free_vnic_mem(bp);
 272
 273         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 274          * If the number of rings change across fw update,
 275          * we don't have much choice except to warn the user.
 276          */
 277         if (!reconfig) {
 278                 bnxt_free_stats(bp);
 279                 bnxt_free_tx_rings(bp);
 280                 bnxt_free_rx_rings(bp);
 281         }
 282         bnxt_free_async_cp_ring(bp);
 283         bnxt_free_rxtx_nq_ring(bp);
 284
 285         rte_free(bp->grp_info);
 286         bp->grp_info = NULL;
 287 }
 288
 289 static int bnxt_alloc_parent_info(struct bnxt *bp)
 290 {
 291         bp->parent = rte_zmalloc("bnxt_parent_info",
 292                                  sizeof(struct bnxt_parent_info), 0);
 293         if (bp->parent == NULL)
 294                 return -ENOMEM;
 295
 296         return 0;
 297 }
 298
 299 static int bnxt_alloc_pf_info(struct bnxt *bp)
 300 {
 301         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 302         if (bp->pf == NULL)
 303                 return -ENOMEM;
 304
 305         return 0;
 306 }
 307
 308 static int bnxt_alloc_link_info(struct bnxt *bp)
 309 {
 310         bp->link_info =
 311                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 312         if (bp->link_info == NULL)
 313                 return -ENOMEM;
 314
 315         return 0;
 316 }
 317
 318 static int bnxt_alloc_leds_info(struct bnxt *bp)
 319 {
 320         if (BNXT_VF(bp))
 321                 return 0;
 322
 323         bp->leds = rte_zmalloc("bnxt_leds",
 324                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 325                                0);
 326         if (bp->leds == NULL)
 327                 return -ENOMEM;
 328
 329         return 0;
 330 }
 331
 332 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 333 {
 334         bp->rx_cos_queue =
 335                 rte_zmalloc("bnxt_rx_cosq",
 336                             BNXT_COS_QUEUE_COUNT *
 337                             sizeof(struct bnxt_cos_queue_info),
 338                             0);
 339         if (bp->rx_cos_queue == NULL)
 340                 return -ENOMEM;
 341
 342         bp->tx_cos_queue =
 343                 rte_zmalloc("bnxt_tx_cosq",
 344                             BNXT_COS_QUEUE_COUNT *
 345                             sizeof(struct bnxt_cos_queue_info),
 346                             0);
 347         if (bp->tx_cos_queue == NULL)
 348                 return -ENOMEM;
 349
 350         return 0;
 351 }
 352
 353 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 354 {
 355         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 356                                     sizeof(struct bnxt_flow_stat_info), 0);
 357         if (bp->flow_stat == NULL)
 358                 return -ENOMEM;
 359
 360         return 0;
 361 }
 362
 363 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 364 {
 365         int rc;
 366
 367         rc = bnxt_alloc_ring_grps(bp);
 368         if (rc)
 369                 goto alloc_mem_err;
 370
 371         rc = bnxt_alloc_async_ring_struct(bp);
 372         if (rc)
 373                 goto alloc_mem_err;
 374
 375         rc = bnxt_alloc_vnic_mem(bp);
 376         if (rc)
 377                 goto alloc_mem_err;
 378
 379         rc = bnxt_alloc_vnic_attributes(bp);
 380         if (rc)
 381                 goto alloc_mem_err;
 382
 383         rc = bnxt_alloc_filter_mem(bp);
 384         if (rc)
 385                 goto alloc_mem_err;
 386
 387         rc = bnxt_alloc_async_cp_ring(bp);
 388         if (rc)
 389                 goto alloc_mem_err;
 390
 391         rc = bnxt_alloc_rxtx_nq_ring(bp);
 392         if (rc)
 393                 goto alloc_mem_err;
 394
 395         if (BNXT_FLOW_XSTATS_EN(bp)) {
 396                 rc = bnxt_alloc_flow_stats_info(bp);
 397                 if (rc)
 398                         goto alloc_mem_err;
 399         }
 400
 401         return 0;
 402
 403 alloc_mem_err:
 404         bnxt_free_mem(bp, reconfig);
 405         return rc;
 406 }
 407
 408 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 409 {
 410         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 411         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 412         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 413         struct bnxt_rx_queue *rxq;
 414         unsigned int j;
 415         int rc;
 416
 417         rc = bnxt_vnic_grp_alloc(bp, vnic);
 418         if (rc)
 419                 goto err_out;
 420
 421         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 422                     vnic_id, vnic, vnic->fw_grp_ids);
 423
 424         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 425         if (rc)
 426                 goto err_out;
 427
 428         /* Alloc RSS context only if RSS mode is enabled */
 429         if (dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS) {
 430                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 431
 432                 /* RSS table size in Thor is 512.
 433                  * Cap max Rx rings to same value
 434                  */
 435                 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
 436                         PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
 437                                     bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
 438                         goto err_out;
 439                 }
 440
 441                 rc = 0;
 442                 for (j = 0; j < nr_ctxs; j++) {
 443                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 444                         if (rc)
 445                                 break;
 446                 }
 447                 if (rc) {
 448                         PMD_DRV_LOG(ERR,
 449                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 450                                     vnic_id, j, rc);
 451                         goto err_out;
 452                 }
 453                 vnic->num_lb_ctxts = nr_ctxs;
 454         }
 455
 456         /*
 457          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 458          * setting is not available at this time, it will not be
 459          * configured correctly in the CFA.
 460          */
 461         if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
 462                 vnic->vlan_strip = true;
 463         else
 464                 vnic->vlan_strip = false;
 465
 466         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 467         if (rc)
 468                 goto err_out;
 469
 470         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 471         if (rc)
 472                 goto err_out;
 473
 474         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 475                 rxq = bp->eth_dev->data->rx_queues[j];
 476
 477                 PMD_DRV_LOG(DEBUG,
 478                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 479                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 480
 481                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 482                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 483                 else
 484                         vnic->rx_queue_cnt++;
 485         }
 486
 487         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 488
 489         rc = bnxt_vnic_rss_configure(bp, vnic);
 490         if (rc)
 491                 goto err_out;
 492
 493         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 494
 495         rc = bnxt_hwrm_vnic_tpa_cfg(bp, vnic,
 496                                     (rx_offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO) ?
 497                                     true : false);
 498         if (rc)
 499                 goto err_out;
 500
 501         return 0;
 502 err_out:
 503         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 504                     vnic_id, rc);
 505         return rc;
 506 }
 507
 508 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 509 {
 510         int rc = 0;
 511
 512         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 513                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 514         if (rc)
 515                 return rc;
 516
 517         PMD_DRV_LOG(DEBUG,
 518                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 519                     " rx_fc_in_tbl.ctx_id = %d\n",
 520                     bp->flow_stat->rx_fc_in_tbl.va,
 521                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 522                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 523
 524         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 525                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 526         if (rc)
 527                 return rc;
 528
 529         PMD_DRV_LOG(DEBUG,
 530                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 531                     " rx_fc_out_tbl.ctx_id = %d\n",
 532                     bp->flow_stat->rx_fc_out_tbl.va,
 533                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 534                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 535
 536         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 537                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 538         if (rc)
 539                 return rc;
 540
 541         PMD_DRV_LOG(DEBUG,
 542                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 543                     " tx_fc_in_tbl.ctx_id = %d\n",
 544                     bp->flow_stat->tx_fc_in_tbl.va,
 545                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 546                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 547
 548         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 549                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 550         if (rc)
 551                 return rc;
 552
 553         PMD_DRV_LOG(DEBUG,
 554                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 555                     " tx_fc_out_tbl.ctx_id = %d\n",
 556                     bp->flow_stat->tx_fc_out_tbl.va,
 557                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 558                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 559
 560         memset(bp->flow_stat->rx_fc_out_tbl.va,
 561                0,
 562                bp->flow_stat->rx_fc_out_tbl.size);
 563         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 564                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 565                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 566                                        bp->flow_stat->max_fc,
 567                                        true);
 568         if (rc)
 569                 return rc;
 570
 571         memset(bp->flow_stat->tx_fc_out_tbl.va,
 572                0,
 573                bp->flow_stat->tx_fc_out_tbl.size);
 574         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 575                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 576                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 577                                        bp->flow_stat->max_fc,
 578                                        true);
 579
 580         return rc;
 581 }
 582
 583 static int bnxt_alloc_ctx_mem_buf(struct bnxt *bp, char *type, size_t size,
 584                                   struct bnxt_ctx_mem_buf_info *ctx)
 585 {
 586         if (!ctx)
 587                 return -EINVAL;
 588
 589         ctx->va = rte_zmalloc_socket(type, size, 0,
 590                                      bp->eth_dev->device->numa_node);
 591         if (ctx->va == NULL)
 592                 return -ENOMEM;
 593         rte_mem_lock_page(ctx->va);
 594         ctx->size = size;
 595         ctx->dma = rte_mem_virt2iova(ctx->va);
 596         if (ctx->dma == RTE_BAD_IOVA)
 597                 return -ENOMEM;
 598
 599         return 0;
 600 }
 601
 602 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 603 {
 604         struct rte_pci_device *pdev = bp->pdev;
 605         char type[RTE_MEMZONE_NAMESIZE];
 606         uint16_t max_fc;
 607         int rc = 0;
 608
 609         max_fc = bp->flow_stat->max_fc;
 610
 611         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 612                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 613         /* 4 bytes for each counter-id */
 614         rc = bnxt_alloc_ctx_mem_buf(bp, type,
 615                                     max_fc * 4,
 616                                     &bp->flow_stat->rx_fc_in_tbl);
 617         if (rc)
 618                 return rc;
 619
 620         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 621                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 622         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 623         rc = bnxt_alloc_ctx_mem_buf(bp, type,
 624                                     max_fc * 16,
 625                                     &bp->flow_stat->rx_fc_out_tbl);
 626         if (rc)
 627                 return rc;
 628
 629         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 630                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 631         /* 4 bytes for each counter-id */
 632         rc = bnxt_alloc_ctx_mem_buf(bp, type,
 633                                     max_fc * 4,
 634                                     &bp->flow_stat->tx_fc_in_tbl);
 635         if (rc)
 636                 return rc;
 637
 638         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 639                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 640         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 641         rc = bnxt_alloc_ctx_mem_buf(bp, type,
 642                                     max_fc * 16,
 643                                     &bp->flow_stat->tx_fc_out_tbl);
 644         if (rc)
 645                 return rc;
 646
 647         rc = bnxt_register_fc_ctx_mem(bp);
 648
 649         return rc;
 650 }
 651
 652 static int bnxt_init_ctx_mem(struct bnxt *bp)
 653 {
 654         int rc = 0;
 655
 656         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 657             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 658             !BNXT_FLOW_XSTATS_EN(bp))
 659                 return 0;
 660
 661         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 662         if (rc)
 663                 return rc;
 664
 665         rc = bnxt_init_fc_ctx_mem(bp);
 666
 667         return rc;
 668 }
 669
 670 static int bnxt_update_phy_setting(struct bnxt *bp)
 671 {
 672         struct rte_eth_link new;
 673         int rc;
 674
 675         rc = bnxt_get_hwrm_link_config(bp, &new);
 676         if (rc) {
 677                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 678                 return rc;
 679         }
 680
 681         /*
 682          * On BCM957508-N2100 adapters, FW will not allow any user other
 683          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 684          * always returns link up. Force phy update always in that case.
 685          */
 686         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 687                 rc = bnxt_set_hwrm_link_config(bp, true);
 688                 if (rc) {
 689                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 690                         return rc;
 691                 }
 692         }
 693
 694         return rc;
 695 }
 696
 697 static void bnxt_free_prev_ring_stats(struct bnxt *bp)
 698 {
 699         rte_free(bp->prev_rx_ring_stats);
 700         rte_free(bp->prev_tx_ring_stats);
 701
 702         bp->prev_rx_ring_stats = NULL;
 703         bp->prev_tx_ring_stats = NULL;
 704 }
 705
 706 static int bnxt_alloc_prev_ring_stats(struct bnxt *bp)
 707 {
 708         bp->prev_rx_ring_stats =  rte_zmalloc("bnxt_prev_rx_ring_stats",
 709                                               sizeof(struct bnxt_ring_stats) *
 710                                               bp->rx_cp_nr_rings,
 711                                               0);
 712         if (bp->prev_rx_ring_stats == NULL)
 713                 return -ENOMEM;
 714
 715         bp->prev_tx_ring_stats = rte_zmalloc("bnxt_prev_tx_ring_stats",
 716                                              sizeof(struct bnxt_ring_stats) *
 717                                              bp->tx_cp_nr_rings,
 718                                              0);
 719         if (bp->prev_tx_ring_stats == NULL)
 720                 goto error;
 721
 722         return 0;
 723
 724 error:
 725         bnxt_free_prev_ring_stats(bp);
 726         return -ENOMEM;
 727 }
 728
 729 static int bnxt_start_nic(struct bnxt *bp)
 730 {
 731         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 732         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
 733         uint32_t intr_vector = 0;
 734         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 735         uint32_t vec = BNXT_MISC_VEC_ID;
 736         unsigned int i, j;
 737         int rc;
 738
 739         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU)
 740                 bp->flags |= BNXT_FLAG_JUMBO;
 741         else
 742                 bp->flags &= ~BNXT_FLAG_JUMBO;
 743
 744         /* THOR does not support ring groups.
 745          * But we will use the array to save RSS context IDs.
 746          */
 747         if (BNXT_CHIP_P5(bp))
 748                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
 749
 750         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 751         if (rc) {
 752                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 753                 goto err_out;
 754         }
 755
 756         rc = bnxt_alloc_hwrm_rings(bp);
 757         if (rc) {
 758                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 759                 goto err_out;
 760         }
 761
 762         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 763         if (rc) {
 764                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 765                 goto err_out;
 766         }
 767
 768         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 769                 goto skip_cosq_cfg;
 770
 771         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 772                 if (bp->rx_cos_queue[i].id != 0xff) {
 773                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 774
 775                         if (!vnic) {
 776                                 PMD_DRV_LOG(ERR,
 777                                             "Num pools more than FW profile\n");
 778                                 rc = -EINVAL;
 779                                 goto err_out;
 780                         }
 781                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 782                         bp->rx_cosq_cnt++;
 783                 }
 784         }
 785
 786 skip_cosq_cfg:
 787         rc = bnxt_mq_rx_configure(bp);
 788         if (rc) {
 789                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 790                 goto err_out;
 791         }
 792
 793         for (j = 0; j < bp->rx_nr_rings; j++) {
 794                 struct bnxt_rx_queue *rxq = bp->rx_queues[j];
 795
 796                 if (!rxq->rx_deferred_start) {
 797                         bp->eth_dev->data->rx_queue_state[j] =
 798                                 RTE_ETH_QUEUE_STATE_STARTED;
 799                         rxq->rx_started = true;
 800                 }
 801         }
 802
 803         /* default vnic 0 */
 804         rc = bnxt_setup_one_vnic(bp, 0);
 805         if (rc)
 806                 goto err_out;
 807         /* VNIC configuration */
 808         if (BNXT_RFS_NEEDS_VNIC(bp)) {
 809                 for (i = 1; i < bp->nr_vnics; i++) {
 810                         rc = bnxt_setup_one_vnic(bp, i);
 811                         if (rc)
 812                                 goto err_out;
 813                 }
 814         }
 815
 816         for (j = 0; j < bp->tx_nr_rings; j++) {
 817                 struct bnxt_tx_queue *txq = bp->tx_queues[j];
 818
 819                 if (!txq->tx_deferred_start) {
 820                         bp->eth_dev->data->tx_queue_state[j] =
 821                                 RTE_ETH_QUEUE_STATE_STARTED;
 822                         txq->tx_started = true;
 823                 }
 824         }
 825
 826         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 827         if (rc) {
 828                 PMD_DRV_LOG(ERR,
 829                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 830                 goto err_out;
 831         }
 832
 833         /* check and configure queue intr-vector mapping */
 834         if ((rte_intr_cap_multiple(intr_handle) ||
 835              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 836             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 837                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 838                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 839                 if (intr_vector > bp->rx_cp_nr_rings) {
 840                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 841                                         bp->rx_cp_nr_rings);
 842                         return -ENOTSUP;
 843                 }
 844                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 845                 if (rc)
 846                         return rc;
 847         }
 848
 849         if (rte_intr_dp_is_en(intr_handle)) {
 850                 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
 851                                         bp->eth_dev->data->nb_rx_queues)) {
 852                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 853                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 854                         rc = -ENOMEM;
 855                         goto err_out;
 856                 }
 857                 PMD_DRV_LOG(DEBUG, "intr_handle->nb_efd = %d "
 858                             "intr_handle->max_intr = %d\n",
 859                             rte_intr_nb_efd_get(intr_handle),
 860                             rte_intr_max_intr_get(intr_handle));
 861                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 862                      queue_id++) {
 863                         rte_intr_vec_list_index_set(intr_handle,
 864                                         queue_id, vec + BNXT_RX_VEC_START);
 865                         if (vec < base + rte_intr_nb_efd_get(intr_handle)
 866                             - 1)
 867                                 vec++;
 868                 }
 869         }
 870
 871         /* enable uio/vfio intr/eventfd mapping */
 872         rc = rte_intr_enable(intr_handle);
 873 #ifndef RTE_EXEC_ENV_FREEBSD
 874         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 875         if (rc)
 876                 goto err_out;
 877 #endif
 878
 879         rc = bnxt_update_phy_setting(bp);
 880         if (rc)
 881                 goto err_out;
 882
 883         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 884         if (!bp->mark_table)
 885                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 886
 887         return 0;
 888
 889 err_out:
 890         /* Some of the error status returned by FW may not be from errno.h */
 891         if (rc > 0)
 892                 rc = -EIO;
 893
 894         return rc;
 895 }
 896
 897 static int bnxt_shutdown_nic(struct bnxt *bp)
 898 {
 899         bnxt_free_all_hwrm_resources(bp);
 900         bnxt_free_all_filters(bp);
 901         bnxt_free_all_vnics(bp);
 902         return 0;
 903 }
 904
 905 /*
 906  * Device configuration and status function
 907  */
 908
 909 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 910 {
 911         uint32_t link_speed = 0;
 912         uint32_t speed_capa = 0;
 913
 914         if (bp->link_info == NULL)
 915                 return 0;
 916
 917         link_speed = bp->link_info->support_speeds;
 918
 919         /* If PAM4 is configured, use PAM4 supported speed */
 920         if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
 921                 link_speed = bp->link_info->support_pam4_speeds;
 922
 923         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 924                 speed_capa |= RTE_ETH_LINK_SPEED_100M;
 925         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 926                 speed_capa |= RTE_ETH_LINK_SPEED_100M_HD;
 927         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 928                 speed_capa |= RTE_ETH_LINK_SPEED_1G;
 929         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 930                 speed_capa |= RTE_ETH_LINK_SPEED_2_5G;
 931         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 932                 speed_capa |= RTE_ETH_LINK_SPEED_10G;
 933         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 934                 speed_capa |= RTE_ETH_LINK_SPEED_20G;
 935         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 936                 speed_capa |= RTE_ETH_LINK_SPEED_25G;
 937         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 938                 speed_capa |= RTE_ETH_LINK_SPEED_40G;
 939         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 940                 speed_capa |= RTE_ETH_LINK_SPEED_50G;
 941         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 942                 speed_capa |= RTE_ETH_LINK_SPEED_100G;
 943         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
 944                 speed_capa |= RTE_ETH_LINK_SPEED_50G;
 945         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
 946                 speed_capa |= RTE_ETH_LINK_SPEED_100G;
 947         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
 948                 speed_capa |= RTE_ETH_LINK_SPEED_200G;
 949
 950         if (bp->link_info->auto_mode ==
 951             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 952                 speed_capa |= RTE_ETH_LINK_SPEED_FIXED;
 953
 954         return speed_capa;
 955 }
 956
 957 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 958                                 struct rte_eth_dev_info *dev_info)
 959 {
 960         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 961         struct bnxt *bp = eth_dev->data->dev_private;
 962         uint16_t max_vnics, i, j, vpool, vrxq;
 963         unsigned int max_rx_rings;
 964         int rc;
 965
 966         rc = is_bnxt_in_error(bp);
 967         if (rc)
 968                 return rc;
 969
 970         /* MAC Specifics */
 971         dev_info->max_mac_addrs = bp->max_l2_ctx;
 972         dev_info->max_hash_mac_addrs = 0;
 973
 974         /* PF/VF specifics */
 975         if (BNXT_PF(bp))
 976                 dev_info->max_vfs = pdev->max_vfs;
 977
 978         max_rx_rings = bnxt_max_rings(bp);
 979         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 980         dev_info->max_rx_queues = max_rx_rings;
 981         dev_info->max_tx_queues = max_rx_rings;
 982         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 983         dev_info->hash_key_size = HW_HASH_KEY_SIZE;
 984         max_vnics = bp->max_vnics;
 985
 986         /* MTU specifics */
 987         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 988         dev_info->max_mtu = BNXT_MAX_MTU;
 989
 990         /* Fast path specifics */
 991         dev_info->min_rx_bufsize = 1;
 992         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 993
 994         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 995         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 996                 dev_info->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_TIMESTAMP;
 997         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_VLAN_RX_STRIP)
 998                 dev_info->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_VLAN_STRIP;
 999         dev_info->tx_queue_offload_capa = RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE;
1000         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
1001                                     dev_info->tx_queue_offload_capa;
1002         if (bp->fw_cap & BNXT_FW_CAP_VLAN_TX_INSERT)
1003                 dev_info->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_VLAN_INSERT;
1004         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
1005
1006         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
1007         dev_info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
1008                              RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
1009
1010         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1011                 .rx_thresh = {
1012                         .pthresh = 8,
1013                         .hthresh = 8,
1014                         .wthresh = 0,
1015                 },
1016                 .rx_free_thresh = 32,
1017                 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
1018         };
1019
1020         dev_info->default_txconf = (struct rte_eth_txconf) {
1021                 .tx_thresh = {
1022                         .pthresh = 32,
1023                         .hthresh = 0,
1024                         .wthresh = 0,
1025                 },
1026                 .tx_free_thresh = 32,
1027                 .tx_rs_thresh = 32,
1028         };
1029         eth_dev->data->dev_conf.intr_conf.lsc = 1;
1030
1031         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
1032         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
1033         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
1034         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
1035
1036         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
1037                 dev_info->switch_info.name = eth_dev->device->name;
1038                 dev_info->switch_info.domain_id = bp->switch_domain_id;
1039                 dev_info->switch_info.port_id =
1040                                 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
1041                                     BNXT_SWITCH_PORT_ID_TRUSTED_VF;
1042         }
1043
1044         /*
1045          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
1046          *       need further investigation.
1047          */
1048
1049         /* VMDq resources */
1050         vpool = 64; /* RTE_ETH_64_POOLS */
1051         vrxq = 128; /* RTE_ETH_VMDQ_DCB_NUM_QUEUES */
1052         for (i = 0; i < 4; vpool >>= 1, i++) {
1053                 if (max_vnics > vpool) {
1054                         for (j = 0; j < 5; vrxq >>= 1, j++) {
1055                                 if (dev_info->max_rx_queues > vrxq) {
1056                                         if (vpool > vrxq)
1057                                                 vpool = vrxq;
1058                                         goto found;
1059                                 }
1060                         }
1061                         /* Not enough resources to support VMDq */
1062                         break;
1063                 }
1064         }
1065         /* Not enough resources to support VMDq */
1066         vpool = 0;
1067         vrxq = 0;
1068 found:
1069         dev_info->max_vmdq_pools = vpool;
1070         dev_info->vmdq_queue_num = vrxq;
1071
1072         dev_info->vmdq_pool_base = 0;
1073         dev_info->vmdq_queue_base = 0;
1074
1075         return 0;
1076 }
1077
1078 /* Configure the device based on the configuration provided */
1079 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1080 {
1081         struct bnxt *bp = eth_dev->data->dev_private;
1082         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1083         int rc;
1084
1085         bp->rx_queues = (void *)eth_dev->data->rx_queues;
1086         bp->tx_queues = (void *)eth_dev->data->tx_queues;
1087         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1088         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1089
1090         rc = is_bnxt_in_error(bp);
1091         if (rc)
1092                 return rc;
1093
1094         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1095                 rc = bnxt_hwrm_check_vf_rings(bp);
1096                 if (rc) {
1097                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1098                         return -ENOSPC;
1099                 }
1100
1101                 /* If a resource has already been allocated - in this case
1102                  * it is the async completion ring, free it. Reallocate it after
1103                  * resource reservation. This will ensure the resource counts
1104                  * are calculated correctly.
1105                  */
1106
1107                 pthread_mutex_lock(&bp->def_cp_lock);
1108
1109                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1110                         bnxt_disable_int(bp);
1111                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
1112                 }
1113
1114                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1115                 if (rc) {
1116                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1117                         pthread_mutex_unlock(&bp->def_cp_lock);
1118                         return -ENOSPC;
1119                 }
1120
1121                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1122                         rc = bnxt_alloc_async_cp_ring(bp);
1123                         if (rc) {
1124                                 pthread_mutex_unlock(&bp->def_cp_lock);
1125                                 return rc;
1126                         }
1127                         bnxt_enable_int(bp);
1128                 }
1129
1130                 pthread_mutex_unlock(&bp->def_cp_lock);
1131         }
1132
1133         /* Inherit new configurations */
1134         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1135             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1136             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1137                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1138             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1139             bp->max_stat_ctx)
1140                 goto resource_error;
1141
1142         if (BNXT_HAS_RING_GRPS(bp) &&
1143             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1144                 goto resource_error;
1145
1146         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS) &&
1147             bp->max_vnics < eth_dev->data->nb_rx_queues)
1148                 goto resource_error;
1149
1150         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1151         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1152
1153         if (eth_dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)
1154                 rx_offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
1155         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1156
1157         bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1158
1159         return 0;
1160
1161 resource_error:
1162         PMD_DRV_LOG(ERR,
1163                     "Insufficient resources to support requested config\n");
1164         PMD_DRV_LOG(ERR,
1165                     "Num Queues Requested: Tx %d, Rx %d\n",
1166                     eth_dev->data->nb_tx_queues,
1167                     eth_dev->data->nb_rx_queues);
1168         PMD_DRV_LOG(ERR,
1169                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1170                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1171                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1172         return -ENOSPC;
1173 }
1174
1175 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1176 {
1177         struct rte_eth_link *link = &eth_dev->data->dev_link;
1178
1179         if (link->link_status)
1180                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1181                         eth_dev->data->port_id,
1182                         (uint32_t)link->link_speed,
1183                         (link->link_duplex == RTE_ETH_LINK_FULL_DUPLEX) ?
1184                         ("full-duplex") : ("half-duplex\n"));
1185         else
1186                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1187                         eth_dev->data->port_id);
1188 }
1189
1190 /*
1191  * Determine whether the current configuration requires support for scattered
1192  * receive; return 1 if scattered receive is required and 0 if not.
1193  */
1194 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1195 {
1196         uint32_t overhead = BNXT_MAX_PKT_LEN - BNXT_MAX_MTU;
1197         uint16_t buf_size;
1198         int i;
1199
1200         if (eth_dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_SCATTER)
1201                 return 1;
1202
1203         if (eth_dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO)
1204                 return 1;
1205
1206         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1207                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1208
1209                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1210                                       RTE_PKTMBUF_HEADROOM);
1211                 if (eth_dev->data->mtu + overhead > buf_size)
1212                         return 1;
1213         }
1214         return 0;
1215 }
1216
1217 static eth_rx_burst_t
1218 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1219 {
1220         struct bnxt *bp = eth_dev->data->dev_private;
1221
1222         /* Disable vector mode RX for Stingray2 for now */
1223         if (BNXT_CHIP_SR2(bp)) {
1224                 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1225                 return bnxt_recv_pkts;
1226         }
1227
1228 #if (defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)) && \
1229         !defined(RTE_LIBRTE_IEEE1588)
1230
1231         /* Vector mode receive cannot be enabled if scattered rx is in use. */
1232         if (eth_dev->data->scattered_rx)
1233                 goto use_scalar_rx;
1234
1235         /*
1236          * Vector mode receive cannot be enabled if Truflow is enabled or if
1237          * asynchronous completions and receive completions can be placed in
1238          * the same completion ring.
1239          */
1240         if (BNXT_TRUFLOW_EN(bp) || !BNXT_NUM_ASYNC_CPR(bp))
1241                 goto use_scalar_rx;
1242
1243         /*
1244          * Vector mode receive cannot be enabled if any receive offloads outside
1245          * a limited subset have been enabled.
1246          */
1247         if (eth_dev->data->dev_conf.rxmode.offloads &
1248                 ~(RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
1249                   RTE_ETH_RX_OFFLOAD_KEEP_CRC |
1250                   RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
1251                   RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
1252                   RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
1253                   RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1254                   RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM |
1255                   RTE_ETH_RX_OFFLOAD_RSS_HASH |
1256                   RTE_ETH_RX_OFFLOAD_VLAN_FILTER))
1257                 goto use_scalar_rx;
1258
1259 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1260         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1261             rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1262                 PMD_DRV_LOG(INFO,
1263                             "Using AVX2 vector mode receive for port %d\n",
1264                             eth_dev->data->port_id);
1265                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1266                 return bnxt_recv_pkts_vec_avx2;
1267         }
1268  #endif
1269         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1270                 PMD_DRV_LOG(INFO,
1271                             "Using SSE vector mode receive for port %d\n",
1272                             eth_dev->data->port_id);
1273                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1274                 return bnxt_recv_pkts_vec;
1275         }
1276
1277 use_scalar_rx:
1278         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1279                     eth_dev->data->port_id);
1280         PMD_DRV_LOG(INFO,
1281                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1282                     eth_dev->data->port_id,
1283                     eth_dev->data->scattered_rx,
1284                     eth_dev->data->dev_conf.rxmode.offloads);
1285 #endif
1286         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1287         return bnxt_recv_pkts;
1288 }
1289
1290 static eth_tx_burst_t
1291 bnxt_transmit_function(struct rte_eth_dev *eth_dev)
1292 {
1293         struct bnxt *bp = eth_dev->data->dev_private;
1294
1295         /* Disable vector mode TX for Stingray2 for now */
1296         if (BNXT_CHIP_SR2(bp))
1297                 return bnxt_xmit_pkts;
1298
1299 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) && \
1300         !defined(RTE_LIBRTE_IEEE1588)
1301         uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1302
1303         /*
1304          * Vector mode transmit can be enabled only if not using scatter rx
1305          * or tx offloads.
1306          */
1307         if (eth_dev->data->scattered_rx ||
1308             (offloads & ~RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) ||
1309             BNXT_TRUFLOW_EN(bp))
1310                 goto use_scalar_tx;
1311
1312 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1313         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1314             rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1315                 PMD_DRV_LOG(INFO,
1316                             "Using AVX2 vector mode transmit for port %d\n",
1317                             eth_dev->data->port_id);
1318                 return bnxt_xmit_pkts_vec_avx2;
1319         }
1320 #endif
1321         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1322                 PMD_DRV_LOG(INFO,
1323                             "Using SSE vector mode transmit for port %d\n",
1324                             eth_dev->data->port_id);
1325                 return bnxt_xmit_pkts_vec;
1326         }
1327
1328 use_scalar_tx:
1329         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1330                     eth_dev->data->port_id);
1331         PMD_DRV_LOG(INFO,
1332                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1333                     eth_dev->data->port_id,
1334                     eth_dev->data->scattered_rx,
1335                     offloads);
1336 #endif
1337         return bnxt_xmit_pkts;
1338 }
1339
1340 static int bnxt_handle_if_change_status(struct bnxt *bp)
1341 {
1342         int rc;
1343
1344         /* Since fw has undergone a reset and lost all contexts,
1345          * set fatal flag to not issue hwrm during cleanup
1346          */
1347         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1348         bnxt_uninit_resources(bp, true);
1349
1350         /* clear fatal flag so that re-init happens */
1351         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1352         rc = bnxt_init_resources(bp, true);
1353
1354         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1355
1356         return rc;
1357 }
1358
1359 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1360 {
1361         struct bnxt *bp = eth_dev->data->dev_private;
1362         int rc = 0;
1363
1364         if (!BNXT_SINGLE_PF(bp))
1365                 return -ENOTSUP;
1366
1367         if (!bp->link_info->link_up)
1368                 rc = bnxt_set_hwrm_link_config(bp, true);
1369         if (!rc)
1370                 eth_dev->data->dev_link.link_status = 1;
1371
1372         bnxt_print_link_info(eth_dev);
1373         return rc;
1374 }
1375
1376 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1377 {
1378         struct bnxt *bp = eth_dev->data->dev_private;
1379
1380         if (!BNXT_SINGLE_PF(bp))
1381                 return -ENOTSUP;
1382
1383         eth_dev->data->dev_link.link_status = 0;
1384         bnxt_set_hwrm_link_config(bp, false);
1385         bp->link_info->link_up = 0;
1386
1387         return 0;
1388 }
1389
1390 static void bnxt_free_switch_domain(struct bnxt *bp)
1391 {
1392         int rc = 0;
1393
1394         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)))
1395                 return;
1396
1397         rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1398         if (rc)
1399                 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1400                             bp->switch_domain_id, rc);
1401 }
1402
1403 static void bnxt_ptp_get_current_time(void *arg)
1404 {
1405         struct bnxt *bp = arg;
1406         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1407         int rc;
1408
1409         rc = is_bnxt_in_error(bp);
1410         if (rc)
1411                 return;
1412
1413         if (!ptp)
1414                 return;
1415
1416         bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1417                                 &ptp->current_time);
1418
1419         rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1420         if (rc != 0) {
1421                 PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n");
1422                 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1423         }
1424 }
1425
1426 static int bnxt_schedule_ptp_alarm(struct bnxt *bp)
1427 {
1428         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1429         int rc;
1430
1431         if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED)
1432                 return 0;
1433
1434         bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1435                                 &ptp->current_time);
1436
1437         rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1438         return rc;
1439 }
1440
1441 static void bnxt_cancel_ptp_alarm(struct bnxt *bp)
1442 {
1443         if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) {
1444                 rte_eal_alarm_cancel(bnxt_ptp_get_current_time, (void *)bp);
1445                 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1446         }
1447 }
1448
1449 static void bnxt_ptp_stop(struct bnxt *bp)
1450 {
1451         bnxt_cancel_ptp_alarm(bp);
1452         bp->flags2 &= ~BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1453 }
1454
1455 static int bnxt_ptp_start(struct bnxt *bp)
1456 {
1457         int rc;
1458
1459         rc = bnxt_schedule_ptp_alarm(bp);
1460         if (rc != 0) {
1461                 PMD_DRV_LOG(ERR, "Failed to schedule PTP alarm\n");
1462         } else {
1463                 bp->flags2 |= BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1464                 bp->flags2 |= BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1465         }
1466
1467         return rc;
1468 }
1469
1470 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev)
1471 {
1472         struct bnxt *bp = eth_dev->data->dev_private;
1473         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1474         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1475         struct rte_eth_link link;
1476         int ret;
1477
1478         eth_dev->data->dev_started = 0;
1479
1480         /* Prevent crashes when queues are still in use */
1481         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1482         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1483
1484         bnxt_disable_int(bp);
1485
1486         /* disable uio/vfio intr/eventfd mapping */
1487         rte_intr_disable(intr_handle);
1488
1489         /* Stop the child representors for this device */
1490         ret = bnxt_rep_stop_all(bp);
1491         if (ret != 0)
1492                 return ret;
1493
1494         /* delete the bnxt ULP port details */
1495         bnxt_ulp_port_deinit(bp);
1496
1497         bnxt_cancel_fw_health_check(bp);
1498
1499         if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1500                 bnxt_cancel_ptp_alarm(bp);
1501
1502         /* Do not bring link down during reset recovery */
1503         if (!is_bnxt_in_error(bp)) {
1504                 bnxt_dev_set_link_down_op(eth_dev);
1505                 /* Wait for link to be reset */
1506                 if (BNXT_SINGLE_PF(bp))
1507                         rte_delay_ms(500);
1508                 /* clear the recorded link status */
1509                 memset(&link, 0, sizeof(link));
1510                 rte_eth_linkstatus_set(eth_dev, &link);
1511         }
1512
1513         /* Clean queue intr-vector mapping */
1514         rte_intr_efd_disable(intr_handle);
1515         rte_intr_vec_list_free(intr_handle);
1516
1517         bnxt_hwrm_port_clr_stats(bp);
1518         bnxt_free_tx_mbufs(bp);
1519         bnxt_free_rx_mbufs(bp);
1520         /* Process any remaining notifications in default completion queue */
1521         bnxt_int_handler(eth_dev);
1522         bnxt_shutdown_nic(bp);
1523         bnxt_hwrm_if_change(bp, false);
1524
1525         bnxt_free_prev_ring_stats(bp);
1526         rte_free(bp->mark_table);
1527         bp->mark_table = NULL;
1528
1529         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1530         bp->rx_cosq_cnt = 0;
1531         /* All filters are deleted on a port stop. */
1532         if (BNXT_FLOW_XSTATS_EN(bp))
1533                 bp->flow_stat->flow_count = 0;
1534
1535         eth_dev->data->scattered_rx = 0;
1536
1537         return 0;
1538 }
1539
1540 /* Unload the driver, release resources */
1541 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1542 {
1543         struct bnxt *bp = eth_dev->data->dev_private;
1544
1545         pthread_mutex_lock(&bp->err_recovery_lock);
1546         if (bp->flags & BNXT_FLAG_FW_RESET) {
1547                 PMD_DRV_LOG(ERR,
1548                             "Adapter recovering from error..Please retry\n");
1549                 pthread_mutex_unlock(&bp->err_recovery_lock);
1550                 return -EAGAIN;
1551         }
1552         pthread_mutex_unlock(&bp->err_recovery_lock);
1553
1554         return bnxt_dev_stop(eth_dev);
1555 }
1556
1557 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1558 {
1559         struct bnxt *bp = eth_dev->data->dev_private;
1560         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1561         int vlan_mask = 0;
1562         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1563
1564         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1565                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1566                 return -EINVAL;
1567         }
1568
1569         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1570                 PMD_DRV_LOG(ERR,
1571                             "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1572                             bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1573
1574         do {
1575                 rc = bnxt_hwrm_if_change(bp, true);
1576                 if (rc == 0 || rc != -EAGAIN)
1577                         break;
1578
1579                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1580         } while (retry_cnt--);
1581
1582         if (rc)
1583                 return rc;
1584
1585         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1586                 rc = bnxt_handle_if_change_status(bp);
1587                 if (rc)
1588                         return rc;
1589         }
1590
1591         bnxt_enable_int(bp);
1592
1593         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1594
1595         rc = bnxt_start_nic(bp);
1596         if (rc)
1597                 goto error;
1598
1599         rc = bnxt_alloc_prev_ring_stats(bp);
1600         if (rc)
1601                 goto error;
1602
1603         eth_dev->data->dev_started = 1;
1604
1605         bnxt_link_update_op(eth_dev, 1);
1606
1607         if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
1608                 vlan_mask |= RTE_ETH_VLAN_FILTER_MASK;
1609         if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
1610                 vlan_mask |= RTE_ETH_VLAN_STRIP_MASK;
1611         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1612         if (rc)
1613                 goto error;
1614
1615         /* Initialize bnxt ULP port details */
1616         rc = bnxt_ulp_port_init(bp);
1617         if (rc)
1618                 goto error;
1619
1620         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1621         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1622
1623         bnxt_schedule_fw_health_check(bp);
1624
1625         if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1626                 bnxt_schedule_ptp_alarm(bp);
1627
1628         return 0;
1629
1630 error:
1631         bnxt_dev_stop(eth_dev);
1632         return rc;
1633 }
1634
1635 static void
1636 bnxt_uninit_locks(struct bnxt *bp)
1637 {
1638         pthread_mutex_destroy(&bp->flow_lock);
1639         pthread_mutex_destroy(&bp->def_cp_lock);
1640         pthread_mutex_destroy(&bp->health_check_lock);
1641         pthread_mutex_destroy(&bp->err_recovery_lock);
1642         if (bp->rep_info) {
1643                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
1644                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
1645         }
1646 }
1647
1648 static void bnxt_drv_uninit(struct bnxt *bp)
1649 {
1650         bnxt_free_leds_info(bp);
1651         bnxt_free_cos_queues(bp);
1652         bnxt_free_link_info(bp);
1653         bnxt_free_parent_info(bp);
1654         bnxt_uninit_locks(bp);
1655
1656         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1657         bp->tx_mem_zone = NULL;
1658         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1659         bp->rx_mem_zone = NULL;
1660
1661         bnxt_free_vf_info(bp);
1662         bnxt_free_pf_info(bp);
1663
1664         rte_free(bp->grp_info);
1665         bp->grp_info = NULL;
1666 }
1667
1668 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1669 {
1670         struct bnxt *bp = eth_dev->data->dev_private;
1671         int ret = 0;
1672
1673         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1674                 return 0;
1675
1676         pthread_mutex_lock(&bp->err_recovery_lock);
1677         if (bp->flags & BNXT_FLAG_FW_RESET) {
1678                 PMD_DRV_LOG(ERR,
1679                             "Adapter recovering from error...Please retry\n");
1680                 pthread_mutex_unlock(&bp->err_recovery_lock);
1681                 return -EAGAIN;
1682         }
1683         pthread_mutex_unlock(&bp->err_recovery_lock);
1684
1685         /* cancel the recovery handler before remove dev */
1686         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1687         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1688         bnxt_cancel_fc_thread(bp);
1689
1690         if (eth_dev->data->dev_started)
1691                 ret = bnxt_dev_stop(eth_dev);
1692
1693         bnxt_uninit_resources(bp, false);
1694
1695         bnxt_drv_uninit(bp);
1696
1697         return ret;
1698 }
1699
1700 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1701                                     uint32_t index)
1702 {
1703         struct bnxt *bp = eth_dev->data->dev_private;
1704         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1705         struct bnxt_vnic_info *vnic;
1706         struct bnxt_filter_info *filter, *temp_filter;
1707         uint32_t i;
1708
1709         if (is_bnxt_in_error(bp))
1710                 return;
1711
1712         /*
1713          * Loop through all VNICs from the specified filter flow pools to
1714          * remove the corresponding MAC addr filter
1715          */
1716         for (i = 0; i < bp->nr_vnics; i++) {
1717                 if (!(pool_mask & (1ULL << i)))
1718                         continue;
1719
1720                 vnic = &bp->vnic_info[i];
1721                 filter = STAILQ_FIRST(&vnic->filter);
1722                 while (filter) {
1723                         temp_filter = STAILQ_NEXT(filter, next);
1724                         if (filter->mac_index == index) {
1725                                 STAILQ_REMOVE(&vnic->filter, filter,
1726                                                 bnxt_filter_info, next);
1727                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1728                                 bnxt_free_filter(bp, filter);
1729                         }
1730                         filter = temp_filter;
1731                 }
1732         }
1733 }
1734
1735 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1736                                struct rte_ether_addr *mac_addr, uint32_t index,
1737                                uint32_t pool)
1738 {
1739         struct bnxt_filter_info *filter;
1740         int rc = 0;
1741
1742         /* Attach requested MAC address to the new l2_filter */
1743         STAILQ_FOREACH(filter, &vnic->filter, next) {
1744                 if (filter->mac_index == index) {
1745                         PMD_DRV_LOG(DEBUG,
1746                                     "MAC addr already existed for pool %d\n",
1747                                     pool);
1748                         return 0;
1749                 }
1750         }
1751
1752         filter = bnxt_alloc_filter(bp);
1753         if (!filter) {
1754                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1755                 return -ENODEV;
1756         }
1757
1758         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1759          * if the MAC that's been programmed now is a different one, then,
1760          * copy that addr to filter->l2_addr
1761          */
1762         if (mac_addr)
1763                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1764         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1765
1766         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1767         if (!rc) {
1768                 filter->mac_index = index;
1769                 if (filter->mac_index == 0)
1770                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1771                 else
1772                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1773         } else {
1774                 bnxt_free_filter(bp, filter);
1775         }
1776
1777         return rc;
1778 }
1779
1780 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1781                                 struct rte_ether_addr *mac_addr,
1782                                 uint32_t index, uint32_t pool)
1783 {
1784         struct bnxt *bp = eth_dev->data->dev_private;
1785         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1786         int rc = 0;
1787
1788         rc = is_bnxt_in_error(bp);
1789         if (rc)
1790                 return rc;
1791
1792         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1793                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1794                 return -ENOTSUP;
1795         }
1796
1797         if (!vnic) {
1798                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1799                 return -EINVAL;
1800         }
1801
1802         /* Filter settings will get applied when port is started */
1803         if (!eth_dev->data->dev_started)
1804                 return 0;
1805
1806         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1807
1808         return rc;
1809 }
1810
1811 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1812 {
1813         int rc = 0;
1814         struct bnxt *bp = eth_dev->data->dev_private;
1815         struct rte_eth_link new;
1816         int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1817                         BNXT_MIN_LINK_WAIT_CNT;
1818
1819         rc = is_bnxt_in_error(bp);
1820         if (rc)
1821                 return rc;
1822
1823         memset(&new, 0, sizeof(new));
1824
1825         if (bp->link_info == NULL)
1826                 goto out;
1827
1828         do {
1829                 /* Retrieve link info from hardware */
1830                 rc = bnxt_get_hwrm_link_config(bp, &new);
1831                 if (rc) {
1832                         new.link_speed = RTE_ETH_LINK_SPEED_100M;
1833                         new.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
1834                         PMD_DRV_LOG(ERR,
1835                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1836                         goto out;
1837                 }
1838
1839                 if (!wait_to_complete || new.link_status)
1840                         break;
1841
1842                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1843         } while (cnt--);
1844
1845         /* Only single function PF can bring phy down.
1846          * When port is stopped, report link down for VF/MH/NPAR functions.
1847          */
1848         if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1849                 memset(&new, 0, sizeof(new));
1850
1851 out:
1852         /* Timed out or success */
1853         if (new.link_status != eth_dev->data->dev_link.link_status ||
1854             new.link_speed != eth_dev->data->dev_link.link_speed) {
1855                 rte_eth_linkstatus_set(eth_dev, &new);
1856                 bnxt_print_link_info(eth_dev);
1857         }
1858
1859         return rc;
1860 }
1861
1862 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1863 {
1864         struct bnxt *bp = eth_dev->data->dev_private;
1865         struct bnxt_vnic_info *vnic;
1866         uint32_t old_flags;
1867         int rc;
1868
1869         rc = is_bnxt_in_error(bp);
1870         if (rc)
1871                 return rc;
1872
1873         /* Filter settings will get applied when port is started */
1874         if (!eth_dev->data->dev_started)
1875                 return 0;
1876
1877         if (bp->vnic_info == NULL)
1878                 return 0;
1879
1880         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1881
1882         old_flags = vnic->flags;
1883         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1884         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1885         if (rc != 0)
1886                 vnic->flags = old_flags;
1887
1888         return rc;
1889 }
1890
1891 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1892 {
1893         struct bnxt *bp = eth_dev->data->dev_private;
1894         struct bnxt_vnic_info *vnic;
1895         uint32_t old_flags;
1896         int rc;
1897
1898         rc = is_bnxt_in_error(bp);
1899         if (rc)
1900                 return rc;
1901
1902         /* Filter settings will get applied when port is started */
1903         if (!eth_dev->data->dev_started)
1904                 return 0;
1905
1906         if (bp->vnic_info == NULL)
1907                 return 0;
1908
1909         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1910
1911         old_flags = vnic->flags;
1912         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1913         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1914         if (rc != 0)
1915                 vnic->flags = old_flags;
1916
1917         return rc;
1918 }
1919
1920 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1921 {
1922         struct bnxt *bp = eth_dev->data->dev_private;
1923         struct bnxt_vnic_info *vnic;
1924         uint32_t old_flags;
1925         int rc;
1926
1927         rc = is_bnxt_in_error(bp);
1928         if (rc)
1929                 return rc;
1930
1931         /* Filter settings will get applied when port is started */
1932         if (!eth_dev->data->dev_started)
1933                 return 0;
1934
1935         if (bp->vnic_info == NULL)
1936                 return 0;
1937
1938         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1939
1940         old_flags = vnic->flags;
1941         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1942         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1943         if (rc != 0)
1944                 vnic->flags = old_flags;
1945
1946         return rc;
1947 }
1948
1949 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1950 {
1951         struct bnxt *bp = eth_dev->data->dev_private;
1952         struct bnxt_vnic_info *vnic;
1953         uint32_t old_flags;
1954         int rc;
1955
1956         rc = is_bnxt_in_error(bp);
1957         if (rc)
1958                 return rc;
1959
1960         /* Filter settings will get applied when port is started */
1961         if (!eth_dev->data->dev_started)
1962                 return 0;
1963
1964         if (bp->vnic_info == NULL)
1965                 return 0;
1966
1967         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1968
1969         old_flags = vnic->flags;
1970         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1971         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1972         if (rc != 0)
1973                 vnic->flags = old_flags;
1974
1975         return rc;
1976 }
1977
1978 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1979 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1980 {
1981         if (qid >= bp->rx_nr_rings)
1982                 return NULL;
1983
1984         return bp->eth_dev->data->rx_queues[qid];
1985 }
1986
1987 /* Return rxq corresponding to a given rss table ring/group ID. */
1988 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1989 {
1990         struct bnxt_rx_queue *rxq;
1991         unsigned int i;
1992
1993         if (!BNXT_HAS_RING_GRPS(bp)) {
1994                 for (i = 0; i < bp->rx_nr_rings; i++) {
1995                         rxq = bp->eth_dev->data->rx_queues[i];
1996                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1997                                 return rxq->index;
1998                 }
1999         } else {
2000                 for (i = 0; i < bp->rx_nr_rings; i++) {
2001                         if (bp->grp_info[i].fw_grp_id == fwr)
2002                                 return i;
2003                 }
2004         }
2005
2006         return INVALID_HW_RING_ID;
2007 }
2008
2009 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
2010                             struct rte_eth_rss_reta_entry64 *reta_conf,
2011                             uint16_t reta_size)
2012 {
2013         struct bnxt *bp = eth_dev->data->dev_private;
2014         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2015         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2016         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
2017         uint16_t idx, sft;
2018         int i, rc;
2019
2020         rc = is_bnxt_in_error(bp);
2021         if (rc)
2022                 return rc;
2023
2024         if (!vnic->rss_table)
2025                 return -EINVAL;
2026
2027         if (!(dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG))
2028                 return -EINVAL;
2029
2030         if (reta_size != tbl_size) {
2031                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2032                         "(%d) must equal the size supported by the hardware "
2033                         "(%d)\n", reta_size, tbl_size);
2034                 return -EINVAL;
2035         }
2036
2037         for (i = 0; i < reta_size; i++) {
2038                 struct bnxt_rx_queue *rxq;
2039
2040                 idx = i / RTE_ETH_RETA_GROUP_SIZE;
2041                 sft = i % RTE_ETH_RETA_GROUP_SIZE;
2042
2043                 if (!(reta_conf[idx].mask & (1ULL << sft)))
2044                         continue;
2045
2046                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
2047                 if (!rxq) {
2048                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
2049                         return -EINVAL;
2050                 }
2051
2052                 if (BNXT_CHIP_P5(bp)) {
2053                         vnic->rss_table[i * 2] =
2054                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
2055                         vnic->rss_table[i * 2 + 1] =
2056                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
2057                 } else {
2058                         vnic->rss_table[i] =
2059                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
2060                 }
2061         }
2062
2063         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2064         return rc;
2065 }
2066
2067 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
2068                               struct rte_eth_rss_reta_entry64 *reta_conf,
2069                               uint16_t reta_size)
2070 {
2071         struct bnxt *bp = eth_dev->data->dev_private;
2072         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2073         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
2074         uint16_t idx, sft, i;
2075         int rc;
2076
2077         rc = is_bnxt_in_error(bp);
2078         if (rc)
2079                 return rc;
2080
2081         if (!vnic)
2082                 return -EINVAL;
2083         if (!vnic->rss_table)
2084                 return -EINVAL;
2085
2086         if (reta_size != tbl_size) {
2087                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2088                         "(%d) must equal the size supported by the hardware "
2089                         "(%d)\n", reta_size, tbl_size);
2090                 return -EINVAL;
2091         }
2092
2093         for (idx = 0, i = 0; i < reta_size; i++) {
2094                 idx = i / RTE_ETH_RETA_GROUP_SIZE;
2095                 sft = i % RTE_ETH_RETA_GROUP_SIZE;
2096
2097                 if (reta_conf[idx].mask & (1ULL << sft)) {
2098                         uint16_t qid;
2099
2100                         if (BNXT_CHIP_P5(bp))
2101                                 qid = bnxt_rss_to_qid(bp,
2102                                                       vnic->rss_table[i * 2]);
2103                         else
2104                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
2105
2106                         if (qid == INVALID_HW_RING_ID) {
2107                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
2108                                 return -EINVAL;
2109                         }
2110                         reta_conf[idx].reta[sft] = qid;
2111                 }
2112         }
2113
2114         return 0;
2115 }
2116
2117 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
2118                                    struct rte_eth_rss_conf *rss_conf)
2119 {
2120         struct bnxt *bp = eth_dev->data->dev_private;
2121         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2122         struct bnxt_vnic_info *vnic;
2123         int rc;
2124
2125         rc = is_bnxt_in_error(bp);
2126         if (rc)
2127                 return rc;
2128
2129         /*
2130          * If RSS enablement were different than dev_configure,
2131          * then return -EINVAL
2132          */
2133         if (dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
2134                 if (!rss_conf->rss_hf)
2135                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
2136         } else {
2137                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
2138                         return -EINVAL;
2139         }
2140
2141         bp->flags |= BNXT_FLAG_UPDATE_HASH;
2142         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
2143                rss_conf,
2144                sizeof(*rss_conf));
2145
2146         /* Update the default RSS VNIC(s) */
2147         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2148         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
2149         vnic->hash_mode =
2150                 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
2151                                             RTE_ETH_RSS_LEVEL(rss_conf->rss_hf));
2152
2153         /*
2154          * If hashkey is not specified, use the previously configured
2155          * hashkey
2156          */
2157         if (!rss_conf->rss_key)
2158                 goto rss_config;
2159
2160         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
2161                 PMD_DRV_LOG(ERR,
2162                             "Invalid hashkey length, should be %d bytes\n",
2163                             HW_HASH_KEY_SIZE);
2164                 return -EINVAL;
2165         }
2166         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
2167
2168 rss_config:
2169         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2170         return rc;
2171 }
2172
2173 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
2174                                      struct rte_eth_rss_conf *rss_conf)
2175 {
2176         struct bnxt *bp = eth_dev->data->dev_private;
2177         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2178         int len, rc;
2179         uint32_t hash_types;
2180
2181         rc = is_bnxt_in_error(bp);
2182         if (rc)
2183                 return rc;
2184
2185         /* RSS configuration is the same for all VNICs */
2186         if (vnic && vnic->rss_hash_key) {
2187                 if (rss_conf->rss_key) {
2188                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
2189                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
2190                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
2191                 }
2192
2193                 hash_types = vnic->hash_type;
2194                 rss_conf->rss_hf = 0;
2195                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
2196                         rss_conf->rss_hf |= RTE_ETH_RSS_IPV4;
2197                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
2198                 }
2199                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
2200                         rss_conf->rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_TCP;
2201                         hash_types &=
2202                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
2203                 }
2204                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
2205                         rss_conf->rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_UDP;
2206                         hash_types &=
2207                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
2208                 }
2209                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
2210                         rss_conf->rss_hf |= RTE_ETH_RSS_IPV6;
2211                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
2212                 }
2213                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
2214                         rss_conf->rss_hf |= RTE_ETH_RSS_NONFRAG_IPV6_TCP;
2215                         hash_types &=
2216                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
2217                 }
2218                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
2219                         rss_conf->rss_hf |= RTE_ETH_RSS_NONFRAG_IPV6_UDP;
2220                         hash_types &=
2221                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2222                 }
2223
2224                 rss_conf->rss_hf |=
2225                         bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2226
2227                 if (hash_types) {
2228                         PMD_DRV_LOG(ERR,
2229                                 "Unknown RSS config from firmware (%08x), RSS disabled",
2230                                 vnic->hash_type);
2231                         return -ENOTSUP;
2232                 }
2233         } else {
2234                 rss_conf->rss_hf = 0;
2235         }
2236         return 0;
2237 }
2238
2239 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2240                                struct rte_eth_fc_conf *fc_conf)
2241 {
2242         struct bnxt *bp = dev->data->dev_private;
2243         struct rte_eth_link link_info;
2244         int rc;
2245
2246         rc = is_bnxt_in_error(bp);
2247         if (rc)
2248                 return rc;
2249
2250         rc = bnxt_get_hwrm_link_config(bp, &link_info);
2251         if (rc)
2252                 return rc;
2253
2254         memset(fc_conf, 0, sizeof(*fc_conf));
2255         if (bp->link_info->auto_pause)
2256                 fc_conf->autoneg = 1;
2257         switch (bp->link_info->pause) {
2258         case 0:
2259                 fc_conf->mode = RTE_ETH_FC_NONE;
2260                 break;
2261         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2262                 fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
2263                 break;
2264         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2265                 fc_conf->mode = RTE_ETH_FC_RX_PAUSE;
2266                 break;
2267         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2268                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2269                 fc_conf->mode = RTE_ETH_FC_FULL;
2270                 break;
2271         }
2272         return 0;
2273 }
2274
2275 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2276                                struct rte_eth_fc_conf *fc_conf)
2277 {
2278         struct bnxt *bp = dev->data->dev_private;
2279         int rc;
2280
2281         rc = is_bnxt_in_error(bp);
2282         if (rc)
2283                 return rc;
2284
2285         if (!BNXT_SINGLE_PF(bp)) {
2286                 PMD_DRV_LOG(ERR,
2287                             "Flow Control Settings cannot be modified on VF or on shared PF\n");
2288                 return -ENOTSUP;
2289         }
2290
2291         switch (fc_conf->mode) {
2292         case RTE_ETH_FC_NONE:
2293                 bp->link_info->auto_pause = 0;
2294                 bp->link_info->force_pause = 0;
2295                 break;
2296         case RTE_ETH_FC_RX_PAUSE:
2297                 if (fc_conf->autoneg) {
2298                         bp->link_info->auto_pause =
2299                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2300                         bp->link_info->force_pause = 0;
2301                 } else {
2302                         bp->link_info->auto_pause = 0;
2303                         bp->link_info->force_pause =
2304                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2305                 }
2306                 break;
2307         case RTE_ETH_FC_TX_PAUSE:
2308                 if (fc_conf->autoneg) {
2309                         bp->link_info->auto_pause =
2310                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2311                         bp->link_info->force_pause = 0;
2312                 } else {
2313                         bp->link_info->auto_pause = 0;
2314                         bp->link_info->force_pause =
2315                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2316                 }
2317                 break;
2318         case RTE_ETH_FC_FULL:
2319                 if (fc_conf->autoneg) {
2320                         bp->link_info->auto_pause =
2321                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2322                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2323                         bp->link_info->force_pause = 0;
2324                 } else {
2325                         bp->link_info->auto_pause = 0;
2326                         bp->link_info->force_pause =
2327                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2328                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2329                 }
2330                 break;
2331         }
2332         return bnxt_set_hwrm_link_config(bp, true);
2333 }
2334
2335 /* Add UDP tunneling port */
2336 static int
2337 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2338                          struct rte_eth_udp_tunnel *udp_tunnel)
2339 {
2340         struct bnxt *bp = eth_dev->data->dev_private;
2341         uint16_t tunnel_type = 0;
2342         int rc = 0;
2343
2344         rc = is_bnxt_in_error(bp);
2345         if (rc)
2346                 return rc;
2347
2348         switch (udp_tunnel->prot_type) {
2349         case RTE_ETH_TUNNEL_TYPE_VXLAN:
2350                 if (bp->vxlan_port_cnt) {
2351                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2352                                 udp_tunnel->udp_port);
2353                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2354                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2355                                 return -ENOSPC;
2356                         }
2357                         bp->vxlan_port_cnt++;
2358                         return 0;
2359                 }
2360                 tunnel_type =
2361                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2362                 break;
2363         case RTE_ETH_TUNNEL_TYPE_GENEVE:
2364                 if (bp->geneve_port_cnt) {
2365                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2366                                 udp_tunnel->udp_port);
2367                         if (bp->geneve_port != udp_tunnel->udp_port) {
2368                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2369                                 return -ENOSPC;
2370                         }
2371                         bp->geneve_port_cnt++;
2372                         return 0;
2373                 }
2374                 tunnel_type =
2375                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2376                 break;
2377         default:
2378                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2379                 return -ENOTSUP;
2380         }
2381         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2382                                              tunnel_type);
2383
2384         if (rc != 0)
2385                 return rc;
2386
2387         if (tunnel_type ==
2388             HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN)
2389                 bp->vxlan_port_cnt++;
2390
2391         if (tunnel_type ==
2392             HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE)
2393                 bp->geneve_port_cnt++;
2394
2395         return rc;
2396 }
2397
2398 static int
2399 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2400                          struct rte_eth_udp_tunnel *udp_tunnel)
2401 {
2402         struct bnxt *bp = eth_dev->data->dev_private;
2403         uint16_t tunnel_type = 0;
2404         uint16_t port = 0;
2405         int rc = 0;
2406
2407         rc = is_bnxt_in_error(bp);
2408         if (rc)
2409                 return rc;
2410
2411         switch (udp_tunnel->prot_type) {
2412         case RTE_ETH_TUNNEL_TYPE_VXLAN:
2413                 if (!bp->vxlan_port_cnt) {
2414                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2415                         return -EINVAL;
2416                 }
2417                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2418                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2419                                 udp_tunnel->udp_port, bp->vxlan_port);
2420                         return -EINVAL;
2421                 }
2422                 if (--bp->vxlan_port_cnt)
2423                         return 0;
2424
2425                 tunnel_type =
2426                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2427                 port = bp->vxlan_fw_dst_port_id;
2428                 break;
2429         case RTE_ETH_TUNNEL_TYPE_GENEVE:
2430                 if (!bp->geneve_port_cnt) {
2431                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2432                         return -EINVAL;
2433                 }
2434                 if (bp->geneve_port != udp_tunnel->udp_port) {
2435                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2436                                 udp_tunnel->udp_port, bp->geneve_port);
2437                         return -EINVAL;
2438                 }
2439                 if (--bp->geneve_port_cnt)
2440                         return 0;
2441
2442                 tunnel_type =
2443                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2444                 port = bp->geneve_fw_dst_port_id;
2445                 break;
2446         default:
2447                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2448                 return -ENOTSUP;
2449         }
2450
2451         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2452         return rc;
2453 }
2454
2455 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2456 {
2457         struct bnxt_filter_info *filter;
2458         struct bnxt_vnic_info *vnic;
2459         int rc = 0;
2460         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2461
2462         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2463         filter = STAILQ_FIRST(&vnic->filter);
2464         while (filter) {
2465                 /* Search for this matching MAC+VLAN filter */
2466                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2467                         /* Delete the filter */
2468                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2469                         if (rc)
2470                                 return rc;
2471                         STAILQ_REMOVE(&vnic->filter, filter,
2472                                       bnxt_filter_info, next);
2473                         bnxt_free_filter(bp, filter);
2474                         PMD_DRV_LOG(INFO,
2475                                     "Deleted vlan filter for %d\n",
2476                                     vlan_id);
2477                         return 0;
2478                 }
2479                 filter = STAILQ_NEXT(filter, next);
2480         }
2481         return -ENOENT;
2482 }
2483
2484 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2485 {
2486         struct bnxt_filter_info *filter;
2487         struct bnxt_vnic_info *vnic;
2488         int rc = 0;
2489         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2490                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2491         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2492
2493         /* Implementation notes on the use of VNIC in this command:
2494          *
2495          * By default, these filters belong to default vnic for the function.
2496          * Once these filters are set up, only destination VNIC can be modified.
2497          * If the destination VNIC is not specified in this command,
2498          * then the HWRM shall only create an l2 context id.
2499          */
2500
2501         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2502         filter = STAILQ_FIRST(&vnic->filter);
2503         /* Check if the VLAN has already been added */
2504         while (filter) {
2505                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2506                         return -EEXIST;
2507
2508                 filter = STAILQ_NEXT(filter, next);
2509         }
2510
2511         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2512          * command to create MAC+VLAN filter with the right flags, enables set.
2513          */
2514         filter = bnxt_alloc_filter(bp);
2515         if (!filter) {
2516                 PMD_DRV_LOG(ERR,
2517                             "MAC/VLAN filter alloc failed\n");
2518                 return -ENOMEM;
2519         }
2520         /* MAC + VLAN ID filter */
2521         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2522          * untagged packets are received
2523          *
2524          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2525          * packets and only the programmed vlan's packets are received
2526          */
2527         filter->l2_ivlan = vlan_id;
2528         filter->l2_ivlan_mask = 0x0FFF;
2529         filter->enables |= en;
2530         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2531
2532         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2533         if (rc) {
2534                 /* Free the newly allocated filter as we were
2535                  * not able to create the filter in hardware.
2536                  */
2537                 bnxt_free_filter(bp, filter);
2538                 return rc;
2539         }
2540
2541         filter->mac_index = 0;
2542         /* Add this new filter to the list */
2543         if (vlan_id == 0)
2544                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2545         else
2546                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2547
2548         PMD_DRV_LOG(INFO,
2549                     "Added Vlan filter for %d\n", vlan_id);
2550         return rc;
2551 }
2552
2553 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2554                 uint16_t vlan_id, int on)
2555 {
2556         struct bnxt *bp = eth_dev->data->dev_private;
2557         int rc;
2558
2559         rc = is_bnxt_in_error(bp);
2560         if (rc)
2561                 return rc;
2562
2563         if (!eth_dev->data->dev_started) {
2564                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2565                 return -EINVAL;
2566         }
2567
2568         /* These operations apply to ALL existing MAC/VLAN filters */
2569         if (on)
2570                 return bnxt_add_vlan_filter(bp, vlan_id);
2571         else
2572                 return bnxt_del_vlan_filter(bp, vlan_id);
2573 }
2574
2575 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2576                                     struct bnxt_vnic_info *vnic)
2577 {
2578         struct bnxt_filter_info *filter;
2579         int rc;
2580
2581         filter = STAILQ_FIRST(&vnic->filter);
2582         while (filter) {
2583                 if (filter->mac_index == 0 &&
2584                     !memcmp(filter->l2_addr, bp->mac_addr,
2585                             RTE_ETHER_ADDR_LEN)) {
2586                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2587                         if (!rc) {
2588                                 STAILQ_REMOVE(&vnic->filter, filter,
2589                                               bnxt_filter_info, next);
2590                                 bnxt_free_filter(bp, filter);
2591                         }
2592                         return rc;
2593                 }
2594                 filter = STAILQ_NEXT(filter, next);
2595         }
2596         return 0;
2597 }
2598
2599 static int
2600 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2601 {
2602         struct bnxt_vnic_info *vnic;
2603         unsigned int i;
2604         int rc;
2605
2606         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2607         if (!(rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)) {
2608                 /* Remove any VLAN filters programmed */
2609                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2610                         bnxt_del_vlan_filter(bp, i);
2611
2612                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2613                 if (rc)
2614                         return rc;
2615         } else {
2616                 /* Default filter will allow packets that match the
2617                  * dest mac. So, it has to be deleted, otherwise, we
2618                  * will endup receiving vlan packets for which the
2619                  * filter is not programmed, when hw-vlan-filter
2620                  * configuration is ON
2621                  */
2622                 bnxt_del_dflt_mac_filter(bp, vnic);
2623                 /* This filter will allow only untagged packets */
2624                 bnxt_add_vlan_filter(bp, 0);
2625         }
2626         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2627                     !!(rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER));
2628
2629         return 0;
2630 }
2631
2632 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2633 {
2634         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2635         unsigned int i;
2636         int rc;
2637
2638         /* Destroy vnic filters and vnic */
2639         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2640             RTE_ETH_RX_OFFLOAD_VLAN_FILTER) {
2641                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2642                         bnxt_del_vlan_filter(bp, i);
2643         }
2644         bnxt_del_dflt_mac_filter(bp, vnic);
2645
2646         rc = bnxt_hwrm_vnic_ctx_free(bp, vnic);
2647         if (rc)
2648                 return rc;
2649
2650         rc = bnxt_hwrm_vnic_free(bp, vnic);
2651         if (rc)
2652                 return rc;
2653
2654         rte_free(vnic->fw_grp_ids);
2655         vnic->fw_grp_ids = NULL;
2656
2657         vnic->rx_queue_cnt = 0;
2658
2659         return 0;
2660 }
2661
2662 static int
2663 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2664 {
2665         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2666         int rc;
2667
2668         /* Destroy, recreate and reconfigure the default vnic */
2669         rc = bnxt_free_one_vnic(bp, 0);
2670         if (rc)
2671                 return rc;
2672
2673         /* default vnic 0 */
2674         rc = bnxt_setup_one_vnic(bp, 0);
2675         if (rc)
2676                 return rc;
2677
2678         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2679             RTE_ETH_RX_OFFLOAD_VLAN_FILTER) {
2680                 rc = bnxt_add_vlan_filter(bp, 0);
2681                 if (rc)
2682                         return rc;
2683                 rc = bnxt_restore_vlan_filters(bp);
2684                 if (rc)
2685                         return rc;
2686         } else {
2687                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2688                 if (rc)
2689                         return rc;
2690         }
2691
2692         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2693         if (rc)
2694                 return rc;
2695
2696         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2697                     !!(rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP));
2698
2699         return rc;
2700 }
2701
2702 static int
2703 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2704 {
2705         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2706         struct bnxt *bp = dev->data->dev_private;
2707         int rc;
2708
2709         rc = is_bnxt_in_error(bp);
2710         if (rc)
2711                 return rc;
2712
2713         /* Filter settings will get applied when port is started */
2714         if (!dev->data->dev_started)
2715                 return 0;
2716
2717         if (mask & RTE_ETH_VLAN_FILTER_MASK) {
2718                 /* Enable or disable VLAN filtering */
2719                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2720                 if (rc)
2721                         return rc;
2722         }
2723
2724         if (mask & RTE_ETH_VLAN_STRIP_MASK) {
2725                 /* Enable or disable VLAN stripping */
2726                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2727                 if (rc)
2728                         return rc;
2729         }
2730
2731         if (mask & RTE_ETH_VLAN_EXTEND_MASK) {
2732                 if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND)
2733                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2734                 else
2735                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2736         }
2737
2738         return 0;
2739 }
2740
2741 static int
2742 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2743                       uint16_t tpid)
2744 {
2745         struct bnxt *bp = dev->data->dev_private;
2746         int qinq = dev->data->dev_conf.rxmode.offloads &
2747                    RTE_ETH_RX_OFFLOAD_VLAN_EXTEND;
2748
2749         if (vlan_type != RTE_ETH_VLAN_TYPE_INNER &&
2750             vlan_type != RTE_ETH_VLAN_TYPE_OUTER) {
2751                 PMD_DRV_LOG(ERR,
2752                             "Unsupported vlan type.");
2753                 return -EINVAL;
2754         }
2755         if (!qinq) {
2756                 PMD_DRV_LOG(ERR,
2757                             "QinQ not enabled. Needs to be ON as we can "
2758                             "accelerate only outer vlan\n");
2759                 return -EINVAL;
2760         }
2761
2762         if (vlan_type == RTE_ETH_VLAN_TYPE_OUTER) {
2763                 switch (tpid) {
2764                 case RTE_ETHER_TYPE_QINQ:
2765                         bp->outer_tpid_bd =
2766                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2767                                 break;
2768                 case RTE_ETHER_TYPE_VLAN:
2769                         bp->outer_tpid_bd =
2770                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2771                                 break;
2772                 case RTE_ETHER_TYPE_QINQ1:
2773                         bp->outer_tpid_bd =
2774                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2775                                 break;
2776                 case RTE_ETHER_TYPE_QINQ2:
2777                         bp->outer_tpid_bd =
2778                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2779                                 break;
2780                 case RTE_ETHER_TYPE_QINQ3:
2781                         bp->outer_tpid_bd =
2782                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2783                                 break;
2784                 default:
2785                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2786                         return -EINVAL;
2787                 }
2788                 bp->outer_tpid_bd |= tpid;
2789                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2790         } else if (vlan_type == RTE_ETH_VLAN_TYPE_INNER) {
2791                 PMD_DRV_LOG(ERR,
2792                             "Can accelerate only outer vlan in QinQ\n");
2793                 return -EINVAL;
2794         }
2795
2796         return 0;
2797 }
2798
2799 static int
2800 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2801                              struct rte_ether_addr *addr)
2802 {
2803         struct bnxt *bp = dev->data->dev_private;
2804         /* Default Filter is tied to VNIC 0 */
2805         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2806         int rc;
2807
2808         rc = is_bnxt_in_error(bp);
2809         if (rc)
2810                 return rc;
2811
2812         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2813                 return -EPERM;
2814
2815         if (rte_is_zero_ether_addr(addr))
2816                 return -EINVAL;
2817
2818         /* Filter settings will get applied when port is started */
2819         if (!dev->data->dev_started)
2820                 return 0;
2821
2822         /* Check if the requested MAC is already added */
2823         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2824                 return 0;
2825
2826         /* Destroy filter and re-create it */
2827         bnxt_del_dflt_mac_filter(bp, vnic);
2828
2829         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2830         if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) {
2831                 /* This filter will allow only untagged packets */
2832                 rc = bnxt_add_vlan_filter(bp, 0);
2833         } else {
2834                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2835         }
2836
2837         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2838         return rc;
2839 }
2840
2841 static int
2842 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2843                           struct rte_ether_addr *mc_addr_set,
2844                           uint32_t nb_mc_addr)
2845 {
2846         struct bnxt *bp = eth_dev->data->dev_private;
2847         char *mc_addr_list = (char *)mc_addr_set;
2848         struct bnxt_vnic_info *vnic;
2849         uint32_t off = 0, i = 0;
2850         int rc;
2851
2852         rc = is_bnxt_in_error(bp);
2853         if (rc)
2854                 return rc;
2855
2856         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2857
2858         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2859                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2860                 goto allmulti;
2861         }
2862
2863         /* TODO Check for Duplicate mcast addresses */
2864         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2865         for (i = 0; i < nb_mc_addr; i++) {
2866                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2867                         RTE_ETHER_ADDR_LEN);
2868                 off += RTE_ETHER_ADDR_LEN;
2869         }
2870
2871         vnic->mc_addr_cnt = i;
2872         if (vnic->mc_addr_cnt)
2873                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2874         else
2875                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2876
2877 allmulti:
2878         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2879 }
2880
2881 static int
2882 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2883 {
2884         struct bnxt *bp = dev->data->dev_private;
2885         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2886         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2887         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2888         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2889         int ret;
2890
2891         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2892                         fw_major, fw_minor, fw_updt, fw_rsvd);
2893         if (ret < 0)
2894                 return -EINVAL;
2895
2896         ret += 1; /* add the size of '\0' */
2897         if (fw_size < (size_t)ret)
2898                 return ret;
2899         else
2900                 return 0;
2901 }
2902
2903 static void
2904 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2905         struct rte_eth_rxq_info *qinfo)
2906 {
2907         struct bnxt *bp = dev->data->dev_private;
2908         struct bnxt_rx_queue *rxq;
2909
2910         if (is_bnxt_in_error(bp))
2911                 return;
2912
2913         rxq = dev->data->rx_queues[queue_id];
2914
2915         qinfo->mp = rxq->mb_pool;
2916         qinfo->scattered_rx = dev->data->scattered_rx;
2917         qinfo->nb_desc = rxq->nb_rx_desc;
2918
2919         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2920         qinfo->conf.rx_drop_en = rxq->drop_en;
2921         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2922         qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2923 }
2924
2925 static void
2926 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2927         struct rte_eth_txq_info *qinfo)
2928 {
2929         struct bnxt *bp = dev->data->dev_private;
2930         struct bnxt_tx_queue *txq;
2931
2932         if (is_bnxt_in_error(bp))
2933                 return;
2934
2935         txq = dev->data->tx_queues[queue_id];
2936
2937         qinfo->nb_desc = txq->nb_tx_desc;
2938
2939         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2940         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2941         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2942
2943         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2944         qinfo->conf.tx_rs_thresh = 0;
2945         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2946         qinfo->conf.offloads = txq->offloads;
2947 }
2948
2949 static const struct {
2950         eth_rx_burst_t pkt_burst;
2951         const char *info;
2952 } bnxt_rx_burst_info[] = {
2953         {bnxt_recv_pkts,                "Scalar"},
2954 #if defined(RTE_ARCH_X86)
2955         {bnxt_recv_pkts_vec,            "Vector SSE"},
2956 #endif
2957 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2958         {bnxt_recv_pkts_vec_avx2,       "Vector AVX2"},
2959 #endif
2960 #if defined(RTE_ARCH_ARM64)
2961         {bnxt_recv_pkts_vec,            "Vector Neon"},
2962 #endif
2963 };
2964
2965 static int
2966 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2967                        struct rte_eth_burst_mode *mode)
2968 {
2969         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2970         size_t i;
2971
2972         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2973                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2974                         snprintf(mode->info, sizeof(mode->info), "%s",
2975                                  bnxt_rx_burst_info[i].info);
2976                         return 0;
2977                 }
2978         }
2979
2980         return -EINVAL;
2981 }
2982
2983 static const struct {
2984         eth_tx_burst_t pkt_burst;
2985         const char *info;
2986 } bnxt_tx_burst_info[] = {
2987         {bnxt_xmit_pkts,                "Scalar"},
2988 #if defined(RTE_ARCH_X86)
2989         {bnxt_xmit_pkts_vec,            "Vector SSE"},
2990 #endif
2991 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2992         {bnxt_xmit_pkts_vec_avx2,       "Vector AVX2"},
2993 #endif
2994 #if defined(RTE_ARCH_ARM64)
2995         {bnxt_xmit_pkts_vec,            "Vector Neon"},
2996 #endif
2997 };
2998
2999 static int
3000 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3001                        struct rte_eth_burst_mode *mode)
3002 {
3003         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3004         size_t i;
3005
3006         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
3007                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
3008                         snprintf(mode->info, sizeof(mode->info), "%s",
3009                                  bnxt_tx_burst_info[i].info);
3010                         return 0;
3011                 }
3012         }
3013
3014         return -EINVAL;
3015 }
3016
3017 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
3018 {
3019         uint32_t overhead = BNXT_MAX_PKT_LEN - BNXT_MAX_MTU;
3020         struct bnxt *bp = eth_dev->data->dev_private;
3021         uint32_t new_pkt_size;
3022         uint32_t rc;
3023         uint32_t i;
3024
3025         rc = is_bnxt_in_error(bp);
3026         if (rc)
3027                 return rc;
3028
3029         /* Exit if receive queues are not configured yet */
3030         if (!eth_dev->data->nb_rx_queues)
3031                 return rc;
3032
3033         new_pkt_size = new_mtu + overhead;
3034
3035         /*
3036          * Disallow any MTU change that would require scattered receive support
3037          * if it is not already enabled.
3038          */
3039         if (eth_dev->data->dev_started &&
3040             !eth_dev->data->scattered_rx &&
3041             (new_pkt_size >
3042              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
3043                 PMD_DRV_LOG(ERR,
3044                             "MTU change would require scattered rx support. ");
3045                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
3046                 return -EINVAL;
3047         }
3048
3049         if (new_mtu > RTE_ETHER_MTU)
3050                 bp->flags |= BNXT_FLAG_JUMBO;
3051         else
3052                 bp->flags &= ~BNXT_FLAG_JUMBO;
3053
3054         /* Is there a change in mtu setting? */
3055         if (eth_dev->data->mtu == new_mtu)
3056                 return rc;
3057
3058         for (i = 0; i < bp->nr_vnics; i++) {
3059                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3060                 uint16_t size = 0;
3061
3062                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
3063                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
3064                 if (rc)
3065                         break;
3066
3067                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
3068                 size -= RTE_PKTMBUF_HEADROOM;
3069
3070                 if (size < new_mtu) {
3071                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
3072                         if (rc)
3073                                 return rc;
3074                 }
3075         }
3076
3077         if (bnxt_hwrm_config_host_mtu(bp))
3078                 PMD_DRV_LOG(WARNING, "Failed to configure host MTU\n");
3079
3080         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
3081
3082         return rc;
3083 }
3084
3085 static int
3086 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
3087 {
3088         struct bnxt *bp = dev->data->dev_private;
3089         uint16_t vlan = bp->vlan;
3090         int rc;
3091
3092         rc = is_bnxt_in_error(bp);
3093         if (rc)
3094                 return rc;
3095
3096         if (!BNXT_SINGLE_PF(bp)) {
3097                 PMD_DRV_LOG(ERR, "PVID cannot be modified on VF or on shared PF\n");
3098                 return -ENOTSUP;
3099         }
3100         bp->vlan = on ? pvid : 0;
3101
3102         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
3103         if (rc)
3104                 bp->vlan = vlan;
3105         return rc;
3106 }
3107
3108 static int
3109 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
3110 {
3111         struct bnxt *bp = dev->data->dev_private;
3112         int rc;
3113
3114         rc = is_bnxt_in_error(bp);
3115         if (rc)
3116                 return rc;
3117
3118         return bnxt_hwrm_port_led_cfg(bp, true);
3119 }
3120
3121 static int
3122 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
3123 {
3124         struct bnxt *bp = dev->data->dev_private;
3125         int rc;
3126
3127         rc = is_bnxt_in_error(bp);
3128         if (rc)
3129                 return rc;
3130
3131         return bnxt_hwrm_port_led_cfg(bp, false);
3132 }
3133
3134 static uint32_t
3135 bnxt_rx_queue_count_op(void *rx_queue)
3136 {
3137         struct bnxt *bp;
3138         struct bnxt_cp_ring_info *cpr;
3139         uint32_t desc = 0, raw_cons, cp_ring_size;
3140         struct bnxt_rx_queue *rxq;
3141         struct rx_pkt_cmpl *rxcmp;
3142         int rc;
3143
3144         rxq = rx_queue;
3145         bp = rxq->bp;
3146
3147         rc = is_bnxt_in_error(bp);
3148         if (rc)
3149                 return rc;
3150
3151         cpr = rxq->cp_ring;
3152         raw_cons = cpr->cp_raw_cons;
3153         cp_ring_size = cpr->cp_ring_struct->ring_size;
3154
3155         while (1) {
3156                 uint32_t agg_cnt, cons, cmpl_type;
3157
3158                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3159                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3160
3161                 if (!bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size))
3162                         break;
3163
3164                 cmpl_type = CMP_TYPE(rxcmp);
3165
3166                 switch (cmpl_type) {
3167                 case CMPL_BASE_TYPE_RX_L2:
3168                 case CMPL_BASE_TYPE_RX_L2_V2:
3169                         agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3170                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3171                         desc++;
3172                         break;
3173
3174                 case CMPL_BASE_TYPE_RX_TPA_END:
3175                         if (BNXT_CHIP_P5(rxq->bp)) {
3176                                 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3177
3178                                 p5_tpa_end = (void *)rxcmp;
3179                                 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3180                         } else {
3181                                 struct rx_tpa_end_cmpl *tpa_end;
3182
3183                                 tpa_end = (void *)rxcmp;
3184                                 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3185                         }
3186
3187                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3188                         desc++;
3189                         break;
3190
3191                 default:
3192                         raw_cons += CMP_LEN(cmpl_type);
3193                 }
3194         }
3195
3196         return desc;
3197 }
3198
3199 static int
3200 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
3201 {
3202         struct bnxt_rx_queue *rxq = rx_queue;
3203         struct bnxt_cp_ring_info *cpr;
3204         struct bnxt_rx_ring_info *rxr;
3205         uint32_t desc, raw_cons, cp_ring_size;
3206         struct bnxt *bp = rxq->bp;
3207         struct rx_pkt_cmpl *rxcmp;
3208         int rc;
3209
3210         rc = is_bnxt_in_error(bp);
3211         if (rc)
3212                 return rc;
3213
3214         if (offset >= rxq->nb_rx_desc)
3215                 return -EINVAL;
3216
3217         rxr = rxq->rx_ring;
3218         cpr = rxq->cp_ring;
3219         cp_ring_size = cpr->cp_ring_struct->ring_size;
3220
3221         /*
3222          * For the vector receive case, the completion at the requested
3223          * offset can be indexed directly.
3224          */
3225 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
3226         if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) {
3227                 struct rx_pkt_cmpl *rxcmp;
3228                 uint32_t cons;
3229
3230                 /* Check status of completion descriptor. */
3231                 raw_cons = cpr->cp_raw_cons +
3232                            offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2);
3233                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3234                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3235
3236                 if (bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size))
3237                         return RTE_ETH_RX_DESC_DONE;
3238
3239                 /* Check whether rx desc has an mbuf attached. */
3240                 cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2);
3241                 if (cons >= rxq->rxrearm_start &&
3242                     cons < rxq->rxrearm_start + rxq->rxrearm_nb) {
3243                         return RTE_ETH_RX_DESC_UNAVAIL;
3244                 }
3245
3246                 return RTE_ETH_RX_DESC_AVAIL;
3247         }
3248 #endif
3249
3250         /*
3251          * For the non-vector receive case, scan the completion ring to
3252          * locate the completion descriptor for the requested offset.
3253          */
3254         raw_cons = cpr->cp_raw_cons;
3255         desc = 0;
3256         while (1) {
3257                 uint32_t agg_cnt, cons, cmpl_type;
3258
3259                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3260                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3261
3262                 if (!bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size))
3263                         break;
3264
3265                 cmpl_type = CMP_TYPE(rxcmp);
3266
3267                 switch (cmpl_type) {
3268                 case CMPL_BASE_TYPE_RX_L2:
3269                 case CMPL_BASE_TYPE_RX_L2_V2:
3270                         if (desc == offset) {
3271                                 cons = rxcmp->opaque;
3272                                 if (rxr->rx_buf_ring[cons])
3273                                         return RTE_ETH_RX_DESC_DONE;
3274                                 else
3275                                         return RTE_ETH_RX_DESC_UNAVAIL;
3276                         }
3277                         agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3278                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3279                         desc++;
3280                         break;
3281
3282                 case CMPL_BASE_TYPE_RX_TPA_END:
3283                         if (desc == offset)
3284                                 return RTE_ETH_RX_DESC_DONE;
3285
3286                         if (BNXT_CHIP_P5(rxq->bp)) {
3287                                 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3288
3289                                 p5_tpa_end = (void *)rxcmp;
3290                                 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3291                         } else {
3292                                 struct rx_tpa_end_cmpl *tpa_end;
3293
3294                                 tpa_end = (void *)rxcmp;
3295                                 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3296                         }
3297
3298                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3299                         desc++;
3300                         break;
3301
3302                 default:
3303                         raw_cons += CMP_LEN(cmpl_type);
3304                 }
3305         }
3306
3307         return RTE_ETH_RX_DESC_AVAIL;
3308 }
3309
3310 static int
3311 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
3312 {
3313         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
3314         struct bnxt_cp_ring_info *cpr = txq->cp_ring;
3315         uint32_t ring_mask, raw_cons, nb_tx_pkts = 0;
3316         struct cmpl_base *cp_desc_ring;
3317         int rc;
3318
3319         rc = is_bnxt_in_error(txq->bp);
3320         if (rc)
3321                 return rc;
3322
3323         if (offset >= txq->nb_tx_desc)
3324                 return -EINVAL;
3325
3326         /* Return "desc done" if descriptor is available for use. */
3327         if (bnxt_tx_bds_in_hw(txq) <= offset)
3328                 return RTE_ETH_TX_DESC_DONE;
3329
3330         raw_cons = cpr->cp_raw_cons;
3331         cp_desc_ring = cpr->cp_desc_ring;
3332         ring_mask = cpr->cp_ring_struct->ring_mask;
3333
3334         /* Check to see if hw has posted a completion for the descriptor. */
3335         while (1) {
3336                 struct tx_cmpl *txcmp;
3337                 uint32_t cons;
3338
3339                 cons = RING_CMPL(ring_mask, raw_cons);
3340                 txcmp = (struct tx_cmpl *)&cp_desc_ring[cons];
3341
3342                 if (!bnxt_cpr_cmp_valid(txcmp, raw_cons, ring_mask + 1))
3343                         break;
3344
3345                 if (CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2)
3346                         nb_tx_pkts += rte_le_to_cpu_32(txcmp->opaque);
3347
3348                 if (nb_tx_pkts > offset)
3349                         return RTE_ETH_TX_DESC_DONE;
3350
3351                 raw_cons = NEXT_RAW_CMP(raw_cons);
3352         }
3353
3354         /* Descriptor is pending transmit, not yet completed by hardware. */
3355         return RTE_ETH_TX_DESC_FULL;
3356 }
3357
3358 int
3359 bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
3360                      const struct rte_flow_ops **ops)
3361 {
3362         struct bnxt *bp = dev->data->dev_private;
3363         int ret = 0;
3364
3365         if (!bp)
3366                 return -EIO;
3367
3368         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3369                 struct bnxt_representor *vfr = dev->data->dev_private;
3370                 bp = vfr->parent_dev->data->dev_private;
3371                 /* parent is deleted while children are still valid */
3372                 if (!bp) {
3373                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error\n",
3374                                     dev->data->port_id);
3375                         return -EIO;
3376                 }
3377         }
3378
3379         ret = is_bnxt_in_error(bp);
3380         if (ret)
3381                 return ret;
3382
3383         /* PMD supports thread-safe flow operations.  rte_flow API
3384          * functions can avoid mutex for multi-thread safety.
3385          */
3386         dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3387
3388         if (BNXT_TRUFLOW_EN(bp))
3389                 *ops = &bnxt_ulp_rte_flow_ops;
3390         else
3391                 *ops = &bnxt_flow_ops;
3392
3393         return ret;
3394 }
3395
3396 static const uint32_t *
3397 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3398 {
3399         static const uint32_t ptypes[] = {
3400                 RTE_PTYPE_L2_ETHER_VLAN,
3401                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3402                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3403                 RTE_PTYPE_L4_ICMP,
3404                 RTE_PTYPE_L4_TCP,
3405                 RTE_PTYPE_L4_UDP,
3406                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3407                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3408                 RTE_PTYPE_INNER_L4_ICMP,
3409                 RTE_PTYPE_INNER_L4_TCP,
3410                 RTE_PTYPE_INNER_L4_UDP,
3411                 RTE_PTYPE_UNKNOWN
3412         };
3413
3414         if (!dev->rx_pkt_burst)
3415                 return NULL;
3416
3417         return ptypes;
3418 }
3419
3420 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3421                          int reg_win)
3422 {
3423         uint32_t reg_base = *reg_arr & 0xfffff000;
3424         uint32_t win_off;
3425         int i;
3426
3427         for (i = 0; i < count; i++) {
3428                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3429                         return -ERANGE;
3430         }
3431         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3432         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3433         return 0;
3434 }
3435
3436 static int bnxt_map_ptp_regs(struct bnxt *bp)
3437 {
3438         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3439         uint32_t *reg_arr;
3440         int rc, i;
3441
3442         reg_arr = ptp->rx_regs;
3443         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3444         if (rc)
3445                 return rc;
3446
3447         reg_arr = ptp->tx_regs;
3448         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3449         if (rc)
3450                 return rc;
3451
3452         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3453                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3454
3455         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3456                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3457
3458         return 0;
3459 }
3460
3461 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3462 {
3463         rte_write32(0, (uint8_t *)bp->bar0 +
3464                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3465         rte_write32(0, (uint8_t *)bp->bar0 +
3466                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3467 }
3468
3469 static uint64_t bnxt_cc_read(struct bnxt *bp)
3470 {
3471         uint64_t ns;
3472
3473         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3474                               BNXT_GRCPF_REG_SYNC_TIME));
3475         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3476                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3477         return ns;
3478 }
3479
3480 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3481 {
3482         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3483         uint32_t fifo;
3484
3485         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3486                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3487         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3488                 return -EAGAIN;
3489
3490         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3491                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3492         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3493                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3494         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3495                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3496         rte_read32((uint8_t *)bp->bar0 + ptp->tx_mapped_regs[BNXT_PTP_TX_SEQ]);
3497
3498         return 0;
3499 }
3500
3501 static int bnxt_clr_rx_ts(struct bnxt *bp, uint64_t *last_ts)
3502 {
3503         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3504         struct bnxt_pf_info *pf = bp->pf;
3505         uint16_t port_id;
3506         int i = 0;
3507         uint32_t fifo;
3508
3509         if (!ptp || (bp->flags & BNXT_FLAG_CHIP_P5))
3510                 return -EINVAL;
3511
3512         port_id = pf->port_id;
3513         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3514                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3515         while ((fifo & BNXT_PTP_RX_FIFO_PENDING) && (i < BNXT_PTP_RX_PND_CNT)) {
3516                 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3517                             ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3518                 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3519                                         ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3520                 *last_ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3521                                         ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3522                 *last_ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3523                                         ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3524                 i++;
3525         }
3526
3527         if (i >= BNXT_PTP_RX_PND_CNT)
3528                 return -EBUSY;
3529
3530         return 0;
3531 }
3532
3533 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3534 {
3535         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3536         struct bnxt_pf_info *pf = bp->pf;
3537         uint16_t port_id;
3538         uint32_t fifo;
3539
3540         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3541                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3542         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3543                 return -EAGAIN;
3544
3545         port_id = pf->port_id;
3546         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3547                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3548
3549         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3550                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3551         if (fifo & BNXT_PTP_RX_FIFO_PENDING)
3552                 return bnxt_clr_rx_ts(bp, ts);
3553
3554         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3555                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3556         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3557                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3558
3559         return 0;
3560 }
3561
3562 static int
3563 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3564 {
3565         uint64_t ns;
3566         struct bnxt *bp = dev->data->dev_private;
3567         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3568
3569         if (!ptp)
3570                 return -ENOTSUP;
3571
3572         ns = rte_timespec_to_ns(ts);
3573         /* Set the timecounters to a new value. */
3574         ptp->tc.nsec = ns;
3575         ptp->tx_tstamp_tc.nsec = ns;
3576         ptp->rx_tstamp_tc.nsec = ns;
3577
3578         return 0;
3579 }
3580
3581 static int
3582 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3583 {
3584         struct bnxt *bp = dev->data->dev_private;
3585         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3586         uint64_t ns, systime_cycles = 0;
3587         int rc = 0;
3588
3589         if (!ptp)
3590                 return -ENOTSUP;
3591
3592         if (BNXT_CHIP_P5(bp))
3593                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3594                                              &systime_cycles);
3595         else
3596                 systime_cycles = bnxt_cc_read(bp);
3597
3598         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3599         *ts = rte_ns_to_timespec(ns);
3600
3601         return rc;
3602 }
3603 static int
3604 bnxt_timesync_enable(struct rte_eth_dev *dev)
3605 {
3606         struct bnxt *bp = dev->data->dev_private;
3607         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3608         uint32_t shift = 0;
3609         int rc;
3610
3611         if (!ptp)
3612                 return -ENOTSUP;
3613
3614         ptp->rx_filter = 1;
3615         ptp->tx_tstamp_en = 1;
3616         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3617
3618         rc = bnxt_hwrm_ptp_cfg(bp);
3619         if (rc)
3620                 return rc;
3621
3622         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3623         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3624         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3625
3626         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3627         ptp->tc.cc_shift = shift;
3628         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3629
3630         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3631         ptp->rx_tstamp_tc.cc_shift = shift;
3632         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3633
3634         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3635         ptp->tx_tstamp_tc.cc_shift = shift;
3636         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3637
3638         if (!BNXT_CHIP_P5(bp))
3639                 bnxt_map_ptp_regs(bp);
3640         else
3641                 rc = bnxt_ptp_start(bp);
3642
3643         return rc;
3644 }
3645
3646 static int
3647 bnxt_timesync_disable(struct rte_eth_dev *dev)
3648 {
3649         struct bnxt *bp = dev->data->dev_private;
3650         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3651
3652         if (!ptp)
3653                 return -ENOTSUP;
3654
3655         ptp->rx_filter = 0;
3656         ptp->tx_tstamp_en = 0;
3657         ptp->rxctl = 0;
3658
3659         bnxt_hwrm_ptp_cfg(bp);
3660
3661         if (!BNXT_CHIP_P5(bp))
3662                 bnxt_unmap_ptp_regs(bp);
3663         else
3664                 bnxt_ptp_stop(bp);
3665
3666         return 0;
3667 }
3668
3669 static int
3670 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3671                                  struct timespec *timestamp,
3672                                  uint32_t flags __rte_unused)
3673 {
3674         struct bnxt *bp = dev->data->dev_private;
3675         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3676         uint64_t rx_tstamp_cycles = 0;
3677         uint64_t ns;
3678
3679         if (!ptp)
3680                 return -ENOTSUP;
3681
3682         if (BNXT_CHIP_P5(bp))
3683                 rx_tstamp_cycles = ptp->rx_timestamp;
3684         else
3685                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3686
3687         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3688         *timestamp = rte_ns_to_timespec(ns);
3689         return  0;
3690 }
3691
3692 static int
3693 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3694                                  struct timespec *timestamp)
3695 {
3696         struct bnxt *bp = dev->data->dev_private;
3697         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3698         uint64_t tx_tstamp_cycles = 0;
3699         uint64_t ns;
3700         int rc = 0;
3701
3702         if (!ptp)
3703                 return -ENOTSUP;
3704
3705         if (BNXT_CHIP_P5(bp))
3706                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3707                                              &tx_tstamp_cycles);
3708         else
3709                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3710
3711         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3712         *timestamp = rte_ns_to_timespec(ns);
3713
3714         return rc;
3715 }
3716
3717 static int
3718 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3719 {
3720         struct bnxt *bp = dev->data->dev_private;
3721         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3722
3723         if (!ptp)
3724                 return -ENOTSUP;
3725
3726         ptp->tc.nsec += delta;
3727         ptp->tx_tstamp_tc.nsec += delta;
3728         ptp->rx_tstamp_tc.nsec += delta;
3729
3730         return 0;
3731 }
3732
3733 static int
3734 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3735 {
3736         struct bnxt *bp = dev->data->dev_private;
3737         int rc;
3738         uint32_t dir_entries;
3739         uint32_t entry_length;
3740
3741         rc = is_bnxt_in_error(bp);
3742         if (rc)
3743                 return rc;
3744
3745         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3746                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3747                     bp->pdev->addr.devid, bp->pdev->addr.function);
3748
3749         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3750         if (rc != 0)
3751                 return rc;
3752
3753         return dir_entries * entry_length;
3754 }
3755
3756 static int
3757 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3758                 struct rte_dev_eeprom_info *in_eeprom)
3759 {
3760         struct bnxt *bp = dev->data->dev_private;
3761         uint32_t index;
3762         uint32_t offset;
3763         int rc;
3764
3765         rc = is_bnxt_in_error(bp);
3766         if (rc)
3767                 return rc;
3768
3769         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3770                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3771                     bp->pdev->addr.devid, bp->pdev->addr.function,
3772                     in_eeprom->offset, in_eeprom->length);
3773
3774         if (in_eeprom->offset == 0) /* special offset value to get directory */
3775                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3776                                                 in_eeprom->data);
3777
3778         index = in_eeprom->offset >> 24;
3779         offset = in_eeprom->offset & 0xffffff;
3780
3781         if (index != 0)
3782                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3783                                            in_eeprom->length, in_eeprom->data);
3784
3785         return 0;
3786 }
3787
3788 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3789 {
3790         switch (dir_type) {
3791         case BNX_DIR_TYPE_CHIMP_PATCH:
3792         case BNX_DIR_TYPE_BOOTCODE:
3793         case BNX_DIR_TYPE_BOOTCODE_2:
3794         case BNX_DIR_TYPE_APE_FW:
3795         case BNX_DIR_TYPE_APE_PATCH:
3796         case BNX_DIR_TYPE_KONG_FW:
3797         case BNX_DIR_TYPE_KONG_PATCH:
3798         case BNX_DIR_TYPE_BONO_FW:
3799         case BNX_DIR_TYPE_BONO_PATCH:
3800                 /* FALLTHROUGH */
3801                 return true;
3802         }
3803
3804         return false;
3805 }
3806
3807 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3808 {
3809         switch (dir_type) {
3810         case BNX_DIR_TYPE_AVS:
3811         case BNX_DIR_TYPE_EXP_ROM_MBA:
3812         case BNX_DIR_TYPE_PCIE:
3813         case BNX_DIR_TYPE_TSCF_UCODE:
3814         case BNX_DIR_TYPE_EXT_PHY:
3815         case BNX_DIR_TYPE_CCM:
3816         case BNX_DIR_TYPE_ISCSI_BOOT:
3817         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3818         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3819                 /* FALLTHROUGH */
3820                 return true;
3821         }
3822
3823         return false;
3824 }
3825
3826 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3827 {
3828         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3829                 bnxt_dir_type_is_other_exec_format(dir_type);
3830 }
3831
3832 static int
3833 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3834                 struct rte_dev_eeprom_info *in_eeprom)
3835 {
3836         struct bnxt *bp = dev->data->dev_private;
3837         uint8_t index, dir_op;
3838         uint16_t type, ext, ordinal, attr;
3839         int rc;
3840
3841         rc = is_bnxt_in_error(bp);
3842         if (rc)
3843                 return rc;
3844
3845         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3846                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3847                     bp->pdev->addr.devid, bp->pdev->addr.function,
3848                     in_eeprom->offset, in_eeprom->length);
3849
3850         if (!BNXT_PF(bp)) {
3851                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3852                 return -EINVAL;
3853         }
3854
3855         type = in_eeprom->magic >> 16;
3856
3857         if (type == 0xffff) { /* special value for directory operations */
3858                 index = in_eeprom->magic & 0xff;
3859                 dir_op = in_eeprom->magic >> 8;
3860                 if (index == 0)
3861                         return -EINVAL;
3862                 switch (dir_op) {
3863                 case 0x0e: /* erase */
3864                         if (in_eeprom->offset != ~in_eeprom->magic)
3865                                 return -EINVAL;
3866                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3867                 default:
3868                         return -EINVAL;
3869                 }
3870         }
3871
3872         /* Create or re-write an NVM item: */
3873         if (bnxt_dir_type_is_executable(type) == true)
3874                 return -EOPNOTSUPP;
3875         ext = in_eeprom->magic & 0xffff;
3876         ordinal = in_eeprom->offset >> 16;
3877         attr = in_eeprom->offset & 0xffff;
3878
3879         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3880                                      in_eeprom->data, in_eeprom->length);
3881 }
3882
3883 static int bnxt_get_module_info(struct rte_eth_dev *dev,
3884                                 struct rte_eth_dev_module_info *modinfo)
3885 {
3886         uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1];
3887         struct bnxt *bp = dev->data->dev_private;
3888         int rc;
3889
3890         /* No point in going further if phy status indicates
3891          * module is not inserted or if it is powered down or
3892          * if it is of type 10GBase-T
3893          */
3894         if (bp->link_info->module_status >
3895             HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG) {
3896                 PMD_DRV_LOG(NOTICE, "Port %u : Module is not inserted or is powered down\n",
3897                             dev->data->port_id);
3898                 return -ENOTSUP;
3899         }
3900
3901         /* This feature is not supported in older firmware versions */
3902         if (bp->hwrm_spec_code < 0x10202) {
3903                 PMD_DRV_LOG(NOTICE, "Port %u : Feature is not supported in older firmware\n",
3904                             dev->data->port_id);
3905                 return -ENOTSUP;
3906         }
3907
3908         rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
3909                                                    SFF_DIAG_SUPPORT_OFFSET + 1,
3910                                                    module_info);
3911
3912         if (rc)
3913                 return rc;
3914
3915         switch (module_info[0]) {
3916         case SFF_MODULE_ID_SFP:
3917                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
3918                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
3919                 if (module_info[SFF_DIAG_SUPPORT_OFFSET] == 0)
3920                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN;
3921                 break;
3922         case SFF_MODULE_ID_QSFP:
3923         case SFF_MODULE_ID_QSFP_PLUS:
3924                 modinfo->type = RTE_ETH_MODULE_SFF_8436;
3925                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN;
3926                 break;
3927         case SFF_MODULE_ID_QSFP28:
3928                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
3929                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
3930                 if (module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK)
3931                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_LEN;
3932                 break;
3933         default:
3934                 PMD_DRV_LOG(NOTICE, "Port %u : Unsupported module\n", dev->data->port_id);
3935                 return -ENOTSUP;
3936         }
3937
3938         PMD_DRV_LOG(INFO, "Port %u : modinfo->type = %d modinfo->eeprom_len = %d\n",
3939                     dev->data->port_id, modinfo->type, modinfo->eeprom_len);
3940
3941         return 0;
3942 }
3943
3944 static int bnxt_get_module_eeprom(struct rte_eth_dev *dev,
3945                                   struct rte_dev_eeprom_info *info)
3946 {
3947         uint8_t pg_addr[5] = { I2C_DEV_ADDR_A0, I2C_DEV_ADDR_A0 };
3948         uint32_t offset = info->offset, length = info->length;
3949         uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1];
3950         struct bnxt *bp = dev->data->dev_private;
3951         uint8_t *data = info->data;
3952         uint8_t page = offset >> 7;
3953         uint8_t max_pages = 2;
3954         uint8_t opt_pages;
3955         int rc;
3956
3957         rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
3958                                                    SFF_DIAG_SUPPORT_OFFSET + 1,
3959                                                    module_info);
3960         if (rc)
3961                 return rc;
3962
3963         switch (module_info[0]) {
3964         case SFF_MODULE_ID_SFP:
3965                 module_info[SFF_DIAG_SUPPORT_OFFSET] = 0;
3966                 if (module_info[SFF_DIAG_SUPPORT_OFFSET]) {
3967                         pg_addr[2] = I2C_DEV_ADDR_A2;
3968                         pg_addr[3] = I2C_DEV_ADDR_A2;
3969                         max_pages = 4;
3970                 }
3971                 break;
3972         case SFF_MODULE_ID_QSFP28:
3973                 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0,
3974                                                            SFF8636_OPT_PAGES_OFFSET,
3975                                                            1, &opt_pages);
3976                 if (rc)
3977                         return rc;
3978
3979                 if (opt_pages & SFF8636_PAGE1_MASK) {
3980                         pg_addr[2] = I2C_DEV_ADDR_A0;
3981                         max_pages = 3;
3982                 }
3983                 if (opt_pages & SFF8636_PAGE2_MASK) {
3984                         pg_addr[3] = I2C_DEV_ADDR_A0;
3985                         max_pages = 4;
3986                 }
3987                 if (~module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK) {
3988                         pg_addr[4] = I2C_DEV_ADDR_A0;
3989                         max_pages = 5;
3990                 }
3991                 break;
3992         default:
3993                 break;
3994         }
3995
3996         memset(data, 0, length);
3997
3998         offset &= 0xff;
3999         while (length && page < max_pages) {
4000                 uint8_t raw_page = page ? page - 1 : 0;
4001                 uint16_t chunk;
4002
4003                 if (pg_addr[page] == I2C_DEV_ADDR_A2)
4004                         raw_page = 0;
4005                 else if (page)
4006                         offset |= 0x80;
4007                 chunk = RTE_MIN(length, 256 - offset);
4008
4009                 if (pg_addr[page]) {
4010                         rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, pg_addr[page],
4011                                                                    raw_page, offset,
4012                                                                    chunk, data);
4013                         if (rc)
4014                                 return rc;
4015                 }
4016
4017                 data += chunk;
4018                 length -= chunk;
4019                 offset = 0;
4020                 page += 1 + (chunk > 128);
4021         }
4022
4023         return length ? -EINVAL : 0;
4024 }
4025
4026 /*
4027  * Initialization
4028  */
4029
4030 static const struct eth_dev_ops bnxt_dev_ops = {
4031         .dev_infos_get = bnxt_dev_info_get_op,
4032         .dev_close = bnxt_dev_close_op,
4033         .dev_configure = bnxt_dev_configure_op,
4034         .dev_start = bnxt_dev_start_op,
4035         .dev_stop = bnxt_dev_stop_op,
4036         .dev_set_link_up = bnxt_dev_set_link_up_op,
4037         .dev_set_link_down = bnxt_dev_set_link_down_op,
4038         .stats_get = bnxt_stats_get_op,
4039         .stats_reset = bnxt_stats_reset_op,
4040         .rx_queue_setup = bnxt_rx_queue_setup_op,
4041         .rx_queue_release = bnxt_rx_queue_release_op,
4042         .tx_queue_setup = bnxt_tx_queue_setup_op,
4043         .tx_queue_release = bnxt_tx_queue_release_op,
4044         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4045         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4046         .reta_update = bnxt_reta_update_op,
4047         .reta_query = bnxt_reta_query_op,
4048         .rss_hash_update = bnxt_rss_hash_update_op,
4049         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4050         .link_update = bnxt_link_update_op,
4051         .promiscuous_enable = bnxt_promiscuous_enable_op,
4052         .promiscuous_disable = bnxt_promiscuous_disable_op,
4053         .allmulticast_enable = bnxt_allmulticast_enable_op,
4054         .allmulticast_disable = bnxt_allmulticast_disable_op,
4055         .mac_addr_add = bnxt_mac_addr_add_op,
4056         .mac_addr_remove = bnxt_mac_addr_remove_op,
4057         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4058         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4059         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4060         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4061         .vlan_filter_set = bnxt_vlan_filter_set_op,
4062         .vlan_offload_set = bnxt_vlan_offload_set_op,
4063         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4064         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4065         .mtu_set = bnxt_mtu_set_op,
4066         .mac_addr_set = bnxt_set_default_mac_addr_op,
4067         .xstats_get = bnxt_dev_xstats_get_op,
4068         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4069         .xstats_reset = bnxt_dev_xstats_reset_op,
4070         .fw_version_get = bnxt_fw_version_get,
4071         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4072         .rxq_info_get = bnxt_rxq_info_get_op,
4073         .txq_info_get = bnxt_txq_info_get_op,
4074         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4075         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4076         .dev_led_on = bnxt_dev_led_on_op,
4077         .dev_led_off = bnxt_dev_led_off_op,
4078         .rx_queue_start = bnxt_rx_queue_start,
4079         .rx_queue_stop = bnxt_rx_queue_stop,
4080         .tx_queue_start = bnxt_tx_queue_start,
4081         .tx_queue_stop = bnxt_tx_queue_stop,
4082         .flow_ops_get = bnxt_flow_ops_get_op,
4083         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4084         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4085         .get_eeprom           = bnxt_get_eeprom_op,
4086         .set_eeprom           = bnxt_set_eeprom_op,
4087         .get_module_info = bnxt_get_module_info,
4088         .get_module_eeprom = bnxt_get_module_eeprom,
4089         .timesync_enable      = bnxt_timesync_enable,
4090         .timesync_disable     = bnxt_timesync_disable,
4091         .timesync_read_time   = bnxt_timesync_read_time,
4092         .timesync_write_time   = bnxt_timesync_write_time,
4093         .timesync_adjust_time = bnxt_timesync_adjust_time,
4094         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4095         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4096 };
4097
4098 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4099 {
4100         uint32_t offset;
4101
4102         /* Only pre-map the reset GRC registers using window 3 */
4103         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4104                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4105
4106         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4107
4108         return offset;
4109 }
4110
4111 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4112 {
4113         struct bnxt_error_recovery_info *info = bp->recovery_info;
4114         uint32_t reg_base = 0xffffffff;
4115         int i;
4116
4117         /* Only pre-map the monitoring GRC registers using window 2 */
4118         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4119                 uint32_t reg = info->status_regs[i];
4120
4121                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4122                         continue;
4123
4124                 if (reg_base == 0xffffffff)
4125                         reg_base = reg & 0xfffff000;
4126                 if ((reg & 0xfffff000) != reg_base)
4127                         return -ERANGE;
4128
4129                 /* Use mask 0xffc as the Lower 2 bits indicates
4130                  * address space location
4131                  */
4132                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4133                                                 (reg & 0xffc);
4134         }
4135
4136         if (reg_base == 0xffffffff)
4137                 return 0;
4138
4139         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4140                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4141
4142         return 0;
4143 }
4144
4145 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4146 {
4147         struct bnxt_error_recovery_info *info = bp->recovery_info;
4148         uint32_t delay = info->delay_after_reset[index];
4149         uint32_t val = info->reset_reg_val[index];
4150         uint32_t reg = info->reset_reg[index];
4151         uint32_t type, offset;
4152         int ret;
4153
4154         type = BNXT_FW_STATUS_REG_TYPE(reg);
4155         offset = BNXT_FW_STATUS_REG_OFF(reg);
4156
4157         switch (type) {
4158         case BNXT_FW_STATUS_REG_TYPE_CFG:
4159                 ret = rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4160                 if (ret < 0) {
4161                         PMD_DRV_LOG(ERR, "Failed to write %#x at PCI offset %#x",
4162                                     val, offset);
4163                         return;
4164                 }
4165                 break;
4166         case BNXT_FW_STATUS_REG_TYPE_GRC:
4167                 offset = bnxt_map_reset_regs(bp, offset);
4168                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4169                 break;
4170         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4171                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4172                 break;
4173         }
4174         /* wait on a specific interval of time until core reset is complete */
4175         if (delay)
4176                 rte_delay_ms(delay);
4177 }
4178
4179 static void bnxt_dev_cleanup(struct bnxt *bp)
4180 {
4181         bp->eth_dev->data->dev_link.link_status = 0;
4182         bp->link_info->link_up = 0;
4183         if (bp->eth_dev->data->dev_started)
4184                 bnxt_dev_stop(bp->eth_dev);
4185
4186         bnxt_uninit_resources(bp, true);
4187 }
4188
4189 static int
4190 bnxt_check_fw_reset_done(struct bnxt *bp)
4191 {
4192         int timeout = bp->fw_reset_max_msecs;
4193         uint16_t val = 0;
4194         int rc;
4195
4196         do {
4197                 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4198                 if (rc < 0) {
4199                         PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4200                         return rc;
4201                 }
4202                 if (val != 0xffff)
4203                         break;
4204                 rte_delay_ms(1);
4205         } while (timeout--);
4206
4207         if (val == 0xffff) {
4208                 PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n");
4209                 return -1;
4210         }
4211
4212         return 0;
4213 }
4214
4215 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4216 {
4217         struct rte_eth_dev *dev = bp->eth_dev;
4218         struct rte_vlan_filter_conf *vfc;
4219         int vidx, vbit, rc;
4220         uint16_t vlan_id;
4221
4222         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4223                 vfc = &dev->data->vlan_filter_conf;
4224                 vidx = vlan_id / 64;
4225                 vbit = vlan_id % 64;
4226
4227                 /* Each bit corresponds to a VLAN id */
4228                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4229                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4230                         if (rc)
4231                                 return rc;
4232                 }
4233         }
4234
4235         return 0;
4236 }
4237
4238 static int bnxt_restore_mac_filters(struct bnxt *bp)
4239 {
4240         struct rte_eth_dev *dev = bp->eth_dev;
4241         struct rte_eth_dev_info dev_info;
4242         struct rte_ether_addr *addr;
4243         uint64_t pool_mask;
4244         uint32_t pool = 0;
4245         uint32_t i;
4246         int rc;
4247
4248         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4249                 return 0;
4250
4251         rc = bnxt_dev_info_get_op(dev, &dev_info);
4252         if (rc)
4253                 return rc;
4254
4255         /* replay MAC address configuration */
4256         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4257                 addr = &dev->data->mac_addrs[i];
4258
4259                 /* skip zero address */
4260                 if (rte_is_zero_ether_addr(addr))
4261                         continue;
4262
4263                 pool = 0;
4264                 pool_mask = dev->data->mac_pool_sel[i];
4265
4266                 do {
4267                         if (pool_mask & 1ULL) {
4268                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4269                                 if (rc)
4270                                         return rc;
4271                         }
4272                         pool_mask >>= 1;
4273                         pool++;
4274                 } while (pool_mask);
4275         }
4276
4277         return 0;
4278 }
4279
4280 static int bnxt_restore_filters(struct bnxt *bp)
4281 {
4282         struct rte_eth_dev *dev = bp->eth_dev;
4283         int ret = 0;
4284
4285         if (dev->data->all_multicast) {
4286                 ret = bnxt_allmulticast_enable_op(dev);
4287                 if (ret)
4288                         return ret;
4289         }
4290         if (dev->data->promiscuous) {
4291                 ret = bnxt_promiscuous_enable_op(dev);
4292                 if (ret)
4293                         return ret;
4294         }
4295
4296         ret = bnxt_restore_mac_filters(bp);
4297         if (ret)
4298                 return ret;
4299
4300         ret = bnxt_restore_vlan_filters(bp);
4301         /* TODO restore other filters as well */
4302         return ret;
4303 }
4304
4305 static int bnxt_check_fw_ready(struct bnxt *bp)
4306 {
4307         int timeout = bp->fw_reset_max_msecs;
4308         int rc = 0;
4309
4310         do {
4311                 rc = bnxt_hwrm_poll_ver_get(bp);
4312                 if (rc == 0)
4313                         break;
4314                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4315                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4316         } while (rc && timeout > 0);
4317
4318         if (rc)
4319                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4320
4321         return rc;
4322 }
4323
4324 static void bnxt_dev_recover(void *arg)
4325 {
4326         struct bnxt *bp = arg;
4327         int rc = 0;
4328
4329         pthread_mutex_lock(&bp->err_recovery_lock);
4330
4331         if (!bp->fw_reset_min_msecs) {
4332                 rc = bnxt_check_fw_reset_done(bp);
4333                 if (rc)
4334                         goto err;
4335         }
4336
4337         /* Clear Error flag so that device re-init should happen */
4338         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4339
4340         rc = bnxt_check_fw_ready(bp);
4341         if (rc)
4342                 goto err;
4343
4344         rc = bnxt_init_resources(bp, true);
4345         if (rc) {
4346                 PMD_DRV_LOG(ERR,
4347                             "Failed to initialize resources after reset\n");
4348                 goto err;
4349         }
4350         /* clear reset flag as the device is initialized now */
4351         bp->flags &= ~BNXT_FLAG_FW_RESET;
4352
4353         rc = bnxt_dev_start_op(bp->eth_dev);
4354         if (rc) {
4355                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4356                 goto err_start;
4357         }
4358
4359         rc = bnxt_restore_filters(bp);
4360         if (rc)
4361                 goto err_start;
4362
4363         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4364         pthread_mutex_unlock(&bp->err_recovery_lock);
4365
4366         return;
4367 err_start:
4368         bnxt_dev_stop(bp->eth_dev);
4369 err:
4370         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4371         bnxt_uninit_resources(bp, false);
4372         if (bp->eth_dev->data->dev_conf.intr_conf.rmv)
4373                 rte_eth_dev_callback_process(bp->eth_dev,
4374                                              RTE_ETH_EVENT_INTR_RMV,
4375                                              NULL);
4376         pthread_mutex_unlock(&bp->err_recovery_lock);
4377         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4378 }
4379
4380 void bnxt_dev_reset_and_resume(void *arg)
4381 {
4382         struct bnxt *bp = arg;
4383         uint32_t us = US_PER_MS * bp->fw_reset_min_msecs;
4384         uint16_t val = 0;
4385         int rc;
4386
4387         bnxt_dev_cleanup(bp);
4388
4389         bnxt_wait_for_device_shutdown(bp);
4390
4391         /* During some fatal firmware error conditions, the PCI config space
4392          * register 0x2e which normally contains the subsystem ID will become
4393          * 0xffff. This register will revert back to the normal value after
4394          * the chip has completed core reset. If we detect this condition,
4395          * we can poll this config register immediately for the value to revert.
4396          */
4397         if (bp->flags & BNXT_FLAG_FATAL_ERROR) {
4398                 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4399                 if (rc < 0) {
4400                         PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4401                         return;
4402                 }
4403                 if (val == 0xffff) {
4404                         bp->fw_reset_min_msecs = 0;
4405                         us = 1;
4406                 }
4407         }
4408
4409         rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp);
4410         if (rc)
4411                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4412 }
4413
4414 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4415 {
4416         struct bnxt_error_recovery_info *info = bp->recovery_info;
4417         uint32_t reg = info->status_regs[index];
4418         uint32_t type, offset, val = 0;
4419         int ret = 0;
4420
4421         type = BNXT_FW_STATUS_REG_TYPE(reg);
4422         offset = BNXT_FW_STATUS_REG_OFF(reg);
4423
4424         switch (type) {
4425         case BNXT_FW_STATUS_REG_TYPE_CFG:
4426                 ret = rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4427                 if (ret < 0)
4428                         PMD_DRV_LOG(ERR, "Failed to read PCI offset %#x",
4429                                     offset);
4430                 break;
4431         case BNXT_FW_STATUS_REG_TYPE_GRC:
4432                 offset = info->mapped_status_regs[index];
4433                 /* FALLTHROUGH */
4434         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4435                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4436                                        offset));
4437                 break;
4438         }
4439
4440         return val;
4441 }
4442
4443 static int bnxt_fw_reset_all(struct bnxt *bp)
4444 {
4445         struct bnxt_error_recovery_info *info = bp->recovery_info;
4446         uint32_t i;
4447         int rc = 0;
4448
4449         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4450                 /* Reset through primary function driver */
4451                 for (i = 0; i < info->reg_array_cnt; i++)
4452                         bnxt_write_fw_reset_reg(bp, i);
4453                 /* Wait for time specified by FW after triggering reset */
4454                 rte_delay_ms(info->primary_func_wait_period_after_reset);
4455         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4456                 /* Reset with the help of Kong processor */
4457                 rc = bnxt_hwrm_fw_reset(bp);
4458                 if (rc)
4459                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4460         }
4461
4462         return rc;
4463 }
4464
4465 static void bnxt_fw_reset_cb(void *arg)
4466 {
4467         struct bnxt *bp = arg;
4468         struct bnxt_error_recovery_info *info = bp->recovery_info;
4469         int rc = 0;
4470
4471         /* Only Primary function can do FW reset */
4472         if (bnxt_is_primary_func(bp) &&
4473             bnxt_is_recovery_enabled(bp)) {
4474                 rc = bnxt_fw_reset_all(bp);
4475                 if (rc) {
4476                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4477                         return;
4478                 }
4479         }
4480
4481         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4482          * EXCEPTION_FATAL_ASYNC event to all the functions
4483          * (including MASTER FUNC). After receiving this Async, all the active
4484          * drivers should treat this case as FW initiated recovery
4485          */
4486         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4487                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4488                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4489
4490                 /* To recover from error */
4491                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4492                                   (void *)bp);
4493         }
4494 }
4495
4496 /* Driver should poll FW heartbeat, reset_counter with the frequency
4497  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4498  * When the driver detects heartbeat stop or change in reset_counter,
4499  * it has to trigger a reset to recover from the error condition.
4500  * A “primary function” is the function who will have the privilege to
4501  * initiate the chimp reset. The primary function will be elected by the
4502  * firmware and will be notified through async message.
4503  */
4504 static void bnxt_check_fw_health(void *arg)
4505 {
4506         struct bnxt *bp = arg;
4507         struct bnxt_error_recovery_info *info = bp->recovery_info;
4508         uint32_t val = 0, wait_msec;
4509
4510         if (!info || !bnxt_is_recovery_enabled(bp) ||
4511             is_bnxt_in_error(bp))
4512                 return;
4513
4514         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4515         if (val == info->last_heart_beat)
4516                 goto reset;
4517
4518         info->last_heart_beat = val;
4519
4520         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4521         if (val != info->last_reset_counter)
4522                 goto reset;
4523
4524         info->last_reset_counter = val;
4525
4526         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4527                           bnxt_check_fw_health, (void *)bp);
4528
4529         return;
4530 reset:
4531         /* Stop DMA to/from device */
4532         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4533         bp->flags |= BNXT_FLAG_FW_RESET;
4534
4535         bnxt_stop_rxtx(bp);
4536
4537         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4538
4539         if (bnxt_is_primary_func(bp))
4540                 wait_msec = info->primary_func_wait_period;
4541         else
4542                 wait_msec = info->normal_func_wait_period;
4543
4544         rte_eal_alarm_set(US_PER_MS * wait_msec,
4545                           bnxt_fw_reset_cb, (void *)bp);
4546 }
4547
4548 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4549 {
4550         uint32_t polling_freq;
4551
4552         pthread_mutex_lock(&bp->health_check_lock);
4553
4554         if (!bnxt_is_recovery_enabled(bp))
4555                 goto done;
4556
4557         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4558                 goto done;
4559
4560         polling_freq = bp->recovery_info->driver_polling_freq;
4561
4562         rte_eal_alarm_set(US_PER_MS * polling_freq,
4563                           bnxt_check_fw_health, (void *)bp);
4564         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4565
4566 done:
4567         pthread_mutex_unlock(&bp->health_check_lock);
4568 }
4569
4570 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4571 {
4572         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4573         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4574 }
4575
4576 static bool bnxt_vf_pciid(uint16_t device_id)
4577 {
4578         switch (device_id) {
4579         case BROADCOM_DEV_ID_57304_VF:
4580         case BROADCOM_DEV_ID_57406_VF:
4581         case BROADCOM_DEV_ID_5731X_VF:
4582         case BROADCOM_DEV_ID_5741X_VF:
4583         case BROADCOM_DEV_ID_57414_VF:
4584         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4585         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4586         case BROADCOM_DEV_ID_58802_VF:
4587         case BROADCOM_DEV_ID_57500_VF1:
4588         case BROADCOM_DEV_ID_57500_VF2:
4589         case BROADCOM_DEV_ID_58818_VF:
4590                 /* FALLTHROUGH */
4591                 return true;
4592         default:
4593                 return false;
4594         }
4595 }
4596
4597 /* Phase 5 device */
4598 static bool bnxt_p5_device(uint16_t device_id)
4599 {
4600         switch (device_id) {
4601         case BROADCOM_DEV_ID_57508:
4602         case BROADCOM_DEV_ID_57504:
4603         case BROADCOM_DEV_ID_57502:
4604         case BROADCOM_DEV_ID_57508_MF1:
4605         case BROADCOM_DEV_ID_57504_MF1:
4606         case BROADCOM_DEV_ID_57502_MF1:
4607         case BROADCOM_DEV_ID_57508_MF2:
4608         case BROADCOM_DEV_ID_57504_MF2:
4609         case BROADCOM_DEV_ID_57502_MF2:
4610         case BROADCOM_DEV_ID_57500_VF1:
4611         case BROADCOM_DEV_ID_57500_VF2:
4612         case BROADCOM_DEV_ID_58812:
4613         case BROADCOM_DEV_ID_58814:
4614         case BROADCOM_DEV_ID_58818:
4615         case BROADCOM_DEV_ID_58818_VF:
4616                 /* FALLTHROUGH */
4617                 return true;
4618         default:
4619                 return false;
4620         }
4621 }
4622
4623 bool bnxt_stratus_device(struct bnxt *bp)
4624 {
4625         uint16_t device_id = bp->pdev->id.device_id;
4626
4627         switch (device_id) {
4628         case BROADCOM_DEV_ID_STRATUS_NIC:
4629         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4630         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4631                 /* FALLTHROUGH */
4632                 return true;
4633         default:
4634                 return false;
4635         }
4636 }
4637
4638 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev)
4639 {
4640         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4641         struct bnxt *bp = eth_dev->data->dev_private;
4642
4643         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4644         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4645         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4646         if (!bp->bar0 || !bp->doorbell_base) {
4647                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4648                 return -ENODEV;
4649         }
4650
4651         bp->eth_dev = eth_dev;
4652         bp->pdev = pci_dev;
4653
4654         return 0;
4655 }
4656
4657 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4658                                   struct bnxt_ctx_pg_info *ctx_pg,
4659                                   uint32_t mem_size,
4660                                   const char *suffix,
4661                                   uint16_t idx)
4662 {
4663         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4664         const struct rte_memzone *mz = NULL;
4665         char mz_name[RTE_MEMZONE_NAMESIZE];
4666         rte_iova_t mz_phys_addr;
4667         uint64_t valid_bits = 0;
4668         uint32_t sz;
4669         int i;
4670
4671         if (!mem_size)
4672                 return 0;
4673
4674         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4675                          BNXT_PAGE_SIZE;
4676         rmem->page_size = BNXT_PAGE_SIZE;
4677         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4678         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4679         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4680
4681         valid_bits = PTU_PTE_VALID;
4682
4683         if (rmem->nr_pages > 1) {
4684                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4685                          "bnxt_ctx_pg_tbl%s_%x_%d",
4686                          suffix, idx, bp->eth_dev->data->port_id);
4687                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4688                 mz = rte_memzone_lookup(mz_name);
4689                 if (!mz) {
4690                         mz = rte_memzone_reserve_aligned(mz_name,
4691                                                 rmem->nr_pages * 8,
4692                                                 bp->eth_dev->device->numa_node,
4693                                                 RTE_MEMZONE_2MB |
4694                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4695                                                 RTE_MEMZONE_IOVA_CONTIG,
4696                                                 BNXT_PAGE_SIZE);
4697                         if (mz == NULL)
4698                                 return -ENOMEM;
4699                 }
4700
4701                 memset(mz->addr, 0, mz->len);
4702                 mz_phys_addr = mz->iova;
4703
4704                 rmem->pg_tbl = mz->addr;
4705                 rmem->pg_tbl_map = mz_phys_addr;
4706                 rmem->pg_tbl_mz = mz;
4707         }
4708
4709         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4710                  suffix, idx, bp->eth_dev->data->port_id);
4711         mz = rte_memzone_lookup(mz_name);
4712         if (!mz) {
4713                 mz = rte_memzone_reserve_aligned(mz_name,
4714                                                  mem_size,
4715                                                  bp->eth_dev->device->numa_node,
4716                                                  RTE_MEMZONE_1GB |
4717                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4718                                                  RTE_MEMZONE_IOVA_CONTIG,
4719                                                  BNXT_PAGE_SIZE);
4720                 if (mz == NULL)
4721                         return -ENOMEM;
4722         }
4723
4724         memset(mz->addr, 0, mz->len);
4725         mz_phys_addr = mz->iova;
4726
4727         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4728                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4729                 rmem->dma_arr[i] = mz_phys_addr + sz;
4730
4731                 if (rmem->nr_pages > 1) {
4732                         if (i == rmem->nr_pages - 2 &&
4733                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4734                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4735                         else if (i == rmem->nr_pages - 1 &&
4736                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4737                                 valid_bits |= PTU_PTE_LAST;
4738
4739                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4740                                                            valid_bits);
4741                 }
4742         }
4743
4744         rmem->mz = mz;
4745         if (rmem->vmem_size)
4746                 rmem->vmem = (void **)mz->addr;
4747         rmem->dma_arr[0] = mz_phys_addr;
4748         return 0;
4749 }
4750
4751 static void bnxt_free_ctx_mem(struct bnxt *bp)
4752 {
4753         int i;
4754
4755         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4756                 return;
4757
4758         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4759         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4760         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4761         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4762         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4763         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4764         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4765         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4766         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4767         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4768         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4769
4770         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4771                 if (bp->ctx->tqm_mem[i])
4772                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4773         }
4774
4775         rte_free(bp->ctx);
4776         bp->ctx = NULL;
4777 }
4778
4779 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4780
4781 #define min_t(type, x, y) ({                    \
4782         type __min1 = (x);                      \
4783         type __min2 = (y);                      \
4784         __min1 < __min2 ? __min1 : __min2; })
4785
4786 #define max_t(type, x, y) ({                    \
4787         type __max1 = (x);                      \
4788         type __max2 = (y);                      \
4789         __max1 > __max2 ? __max1 : __max2; })
4790
4791 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4792
4793 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4794 {
4795         struct bnxt_ctx_pg_info *ctx_pg;
4796         struct bnxt_ctx_mem_info *ctx;
4797         uint32_t mem_size, ena, entries;
4798         uint32_t entries_sp, min;
4799         int i, rc;
4800
4801         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4802         if (rc) {
4803                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4804                 return rc;
4805         }
4806         ctx = bp->ctx;
4807         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4808                 return 0;
4809
4810         ctx_pg = &ctx->qp_mem;
4811         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4812         if (ctx->qp_entry_size) {
4813                 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4814                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4815                 if (rc)
4816                         return rc;
4817         }
4818
4819         ctx_pg = &ctx->srq_mem;
4820         ctx_pg->entries = ctx->srq_max_l2_entries;
4821         if (ctx->srq_entry_size) {
4822                 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4823                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4824                 if (rc)
4825                         return rc;
4826         }
4827
4828         ctx_pg = &ctx->cq_mem;
4829         ctx_pg->entries = ctx->cq_max_l2_entries;
4830         if (ctx->cq_entry_size) {
4831                 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4832                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4833                 if (rc)
4834                         return rc;
4835         }
4836
4837         ctx_pg = &ctx->vnic_mem;
4838         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4839                 ctx->vnic_max_ring_table_entries;
4840         if (ctx->vnic_entry_size) {
4841                 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4842                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4843                 if (rc)
4844                         return rc;
4845         }
4846
4847         ctx_pg = &ctx->stat_mem;
4848         ctx_pg->entries = ctx->stat_max_entries;
4849         if (ctx->stat_entry_size) {
4850                 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4851                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4852                 if (rc)
4853                         return rc;
4854         }
4855
4856         min = ctx->tqm_min_entries_per_ring;
4857
4858         entries_sp = ctx->qp_max_l2_entries +
4859                      ctx->vnic_max_vnic_entries +
4860                      2 * ctx->qp_min_qp1_entries + min;
4861         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4862
4863         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4864         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4865         entries = clamp_t(uint32_t, entries, min,
4866                           ctx->tqm_max_entries_per_ring);
4867         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4868                 /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7.
4869                  * i > 8 is other ext rings.
4870                  */
4871                 ctx_pg = ctx->tqm_mem[i];
4872                 ctx_pg->entries = i ? entries : entries_sp;
4873                 if (ctx->tqm_entry_size) {
4874                         mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4875                         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size,
4876                                                     "tqm_mem", i);
4877                         if (rc)
4878                                 return rc;
4879                 }
4880                 if (i < BNXT_MAX_TQM_LEGACY_RINGS)
4881                         ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4882                 else
4883                         ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8;
4884         }
4885
4886         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4887         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4888         if (rc)
4889                 PMD_DRV_LOG(ERR,
4890                             "Failed to configure context mem: rc = %d\n", rc);
4891         else
4892                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4893
4894         return rc;
4895 }
4896
4897 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4898 {
4899         struct rte_pci_device *pci_dev = bp->pdev;
4900         char mz_name[RTE_MEMZONE_NAMESIZE];
4901         const struct rte_memzone *mz = NULL;
4902         uint32_t total_alloc_len;
4903         rte_iova_t mz_phys_addr;
4904
4905         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4906                 return 0;
4907
4908         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4909                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4910                  pci_dev->addr.bus, pci_dev->addr.devid,
4911                  pci_dev->addr.function, "rx_port_stats");
4912         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4913         mz = rte_memzone_lookup(mz_name);
4914         total_alloc_len =
4915                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4916                                        sizeof(struct rx_port_stats_ext) + 512);
4917         if (!mz) {
4918                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4919                                          SOCKET_ID_ANY,
4920                                          RTE_MEMZONE_2MB |
4921                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4922                                          RTE_MEMZONE_IOVA_CONTIG);
4923                 if (mz == NULL)
4924                         return -ENOMEM;
4925         }
4926         memset(mz->addr, 0, mz->len);
4927         mz_phys_addr = mz->iova;
4928
4929         bp->rx_mem_zone = (const void *)mz;
4930         bp->hw_rx_port_stats = mz->addr;
4931         bp->hw_rx_port_stats_map = mz_phys_addr;
4932
4933         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4934                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4935                  pci_dev->addr.bus, pci_dev->addr.devid,
4936                  pci_dev->addr.function, "tx_port_stats");
4937         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4938         mz = rte_memzone_lookup(mz_name);
4939         total_alloc_len =
4940                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4941                                        sizeof(struct tx_port_stats_ext) + 512);
4942         if (!mz) {
4943                 mz = rte_memzone_reserve(mz_name,
4944                                          total_alloc_len,
4945                                          SOCKET_ID_ANY,
4946                                          RTE_MEMZONE_2MB |
4947                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4948                                          RTE_MEMZONE_IOVA_CONTIG);
4949                 if (mz == NULL)
4950                         return -ENOMEM;
4951         }
4952         memset(mz->addr, 0, mz->len);
4953         mz_phys_addr = mz->iova;
4954
4955         bp->tx_mem_zone = (const void *)mz;
4956         bp->hw_tx_port_stats = mz->addr;
4957         bp->hw_tx_port_stats_map = mz_phys_addr;
4958         bp->flags |= BNXT_FLAG_PORT_STATS;
4959
4960         /* Display extended statistics if FW supports it */
4961         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4962             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4963             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4964                 return 0;
4965
4966         bp->hw_rx_port_stats_ext = (void *)
4967                 ((uint8_t *)bp->hw_rx_port_stats +
4968                  sizeof(struct rx_port_stats));
4969         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4970                 sizeof(struct rx_port_stats);
4971         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4972
4973         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4974             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4975                 bp->hw_tx_port_stats_ext = (void *)
4976                         ((uint8_t *)bp->hw_tx_port_stats +
4977                          sizeof(struct tx_port_stats));
4978                 bp->hw_tx_port_stats_ext_map =
4979                         bp->hw_tx_port_stats_map +
4980                         sizeof(struct tx_port_stats);
4981                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4982         }
4983
4984         return 0;
4985 }
4986
4987 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4988 {
4989         struct bnxt *bp = eth_dev->data->dev_private;
4990         int rc = 0;
4991
4992         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4993                                                RTE_ETHER_ADDR_LEN *
4994                                                bp->max_l2_ctx,
4995                                                0);
4996         if (eth_dev->data->mac_addrs == NULL) {
4997                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4998                 return -ENOMEM;
4999         }
5000
5001         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
5002                 if (BNXT_PF(bp))
5003                         return -EINVAL;
5004
5005                 /* Generate a random MAC address, if none was assigned by PF */
5006                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5007                 bnxt_eth_hw_addr_random(bp->mac_addr);
5008                 PMD_DRV_LOG(INFO,
5009                             "Assign random MAC:" RTE_ETHER_ADDR_PRT_FMT "\n",
5010                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5011                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5012
5013                 rc = bnxt_hwrm_set_mac(bp);
5014                 if (rc)
5015                         return rc;
5016         }
5017
5018         /* Copy the permanent MAC from the FUNC_QCAPS response */
5019         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5020
5021         return rc;
5022 }
5023
5024 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5025 {
5026         int rc = 0;
5027
5028         /* MAC is already configured in FW */
5029         if (BNXT_HAS_DFLT_MAC_SET(bp))
5030                 return 0;
5031
5032         /* Restore the old MAC configured */
5033         rc = bnxt_hwrm_set_mac(bp);
5034         if (rc)
5035                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5036
5037         return rc;
5038 }
5039
5040 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5041 {
5042         if (!BNXT_PF(bp))
5043                 return;
5044
5045         memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5046
5047         if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
5048                 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
5049         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
5050         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
5051         BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
5052         BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
5053 }
5054
5055 struct bnxt *
5056 bnxt_get_bp(uint16_t port)
5057 {
5058         struct bnxt *bp;
5059         struct rte_eth_dev *dev;
5060
5061         if (!rte_eth_dev_is_valid_port(port)) {
5062                 PMD_DRV_LOG(ERR, "Invalid port %d\n", port);
5063                 return NULL;
5064         }
5065
5066         dev = &rte_eth_devices[port];
5067         if (!is_bnxt_supported(dev)) {
5068                 PMD_DRV_LOG(ERR, "Device %d not supported\n", port);
5069                 return NULL;
5070         }
5071
5072         bp = (struct bnxt *)dev->data->dev_private;
5073         if (!BNXT_TRUFLOW_EN(bp)) {
5074                 PMD_DRV_LOG(ERR, "TRUFLOW not enabled\n");
5075                 return NULL;
5076         }
5077
5078         return bp;
5079 }
5080
5081 uint16_t
5082 bnxt_get_svif(uint16_t port_id, bool func_svif,
5083               enum bnxt_ulp_intf_type type)
5084 {
5085         struct rte_eth_dev *eth_dev;
5086         struct bnxt *bp;
5087
5088         eth_dev = &rte_eth_devices[port_id];
5089         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5090                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5091                 if (!vfr)
5092                         return 0;
5093
5094                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5095                         return vfr->svif;
5096
5097                 eth_dev = vfr->parent_dev;
5098         }
5099
5100         bp = eth_dev->data->dev_private;
5101
5102         return func_svif ? bp->func_svif : bp->port_svif;
5103 }
5104
5105 void
5106 bnxt_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type,
5107                    uint8_t *mac, uint8_t *parent_mac)
5108 {
5109         struct rte_eth_dev *eth_dev;
5110         struct bnxt *bp;
5111
5112         if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF &&
5113             type != BNXT_ULP_INTF_TYPE_PF)
5114                 return;
5115
5116         eth_dev = &rte_eth_devices[port];
5117         bp = eth_dev->data->dev_private;
5118         memcpy(mac, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5119
5120         if (type == BNXT_ULP_INTF_TYPE_TRUSTED_VF)
5121                 memcpy(parent_mac, bp->parent->mac_addr, RTE_ETHER_ADDR_LEN);
5122 }
5123
5124 uint16_t
5125 bnxt_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5126 {
5127         struct rte_eth_dev *eth_dev;
5128         struct bnxt *bp;
5129
5130         if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF)
5131                 return 0;
5132
5133         eth_dev = &rte_eth_devices[port];
5134         bp = eth_dev->data->dev_private;
5135
5136         return bp->parent->vnic;
5137 }
5138 uint16_t
5139 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5140 {
5141         struct rte_eth_dev *eth_dev;
5142         struct bnxt_vnic_info *vnic;
5143         struct bnxt *bp;
5144
5145         eth_dev = &rte_eth_devices[port];
5146         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5147                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5148                 if (!vfr)
5149                         return 0;
5150
5151                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5152                         return vfr->dflt_vnic_id;
5153
5154                 eth_dev = vfr->parent_dev;
5155         }
5156
5157         bp = eth_dev->data->dev_private;
5158
5159         vnic = BNXT_GET_DEFAULT_VNIC(bp);
5160
5161         return vnic->fw_vnic_id;
5162 }
5163
5164 uint16_t
5165 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5166 {
5167         struct rte_eth_dev *eth_dev;
5168         struct bnxt *bp;
5169
5170         eth_dev = &rte_eth_devices[port];
5171         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5172                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5173                 if (!vfr)
5174                         return 0;
5175
5176                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5177                         return vfr->fw_fid;
5178
5179                 eth_dev = vfr->parent_dev;
5180         }
5181
5182         bp = eth_dev->data->dev_private;
5183
5184         return bp->fw_fid;
5185 }
5186
5187 enum bnxt_ulp_intf_type
5188 bnxt_get_interface_type(uint16_t port)
5189 {
5190         struct rte_eth_dev *eth_dev;
5191         struct bnxt *bp;
5192
5193         eth_dev = &rte_eth_devices[port];
5194         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5195                 return BNXT_ULP_INTF_TYPE_VF_REP;
5196
5197         bp = eth_dev->data->dev_private;
5198         if (BNXT_PF(bp))
5199                 return BNXT_ULP_INTF_TYPE_PF;
5200         else if (BNXT_VF_IS_TRUSTED(bp))
5201                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5202         else if (BNXT_VF(bp))
5203                 return BNXT_ULP_INTF_TYPE_VF;
5204
5205         return BNXT_ULP_INTF_TYPE_INVALID;
5206 }
5207
5208 uint16_t
5209 bnxt_get_phy_port_id(uint16_t port_id)
5210 {
5211         struct bnxt_representor *vfr;
5212         struct rte_eth_dev *eth_dev;
5213         struct bnxt *bp;
5214
5215         eth_dev = &rte_eth_devices[port_id];
5216         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5217                 vfr = eth_dev->data->dev_private;
5218                 if (!vfr)
5219                         return 0;
5220
5221                 eth_dev = vfr->parent_dev;
5222         }
5223
5224         bp = eth_dev->data->dev_private;
5225
5226         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5227 }
5228
5229 uint16_t
5230 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5231 {
5232         struct rte_eth_dev *eth_dev;
5233         struct bnxt *bp;
5234
5235         eth_dev = &rte_eth_devices[port_id];
5236         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5237                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5238                 if (!vfr)
5239                         return 0;
5240
5241                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5242                         return vfr->fw_fid - 1;
5243
5244                 eth_dev = vfr->parent_dev;
5245         }
5246
5247         bp = eth_dev->data->dev_private;
5248
5249         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5250 }
5251
5252 uint16_t
5253 bnxt_get_vport(uint16_t port_id)
5254 {
5255         return (1 << bnxt_get_phy_port_id(port_id));
5256 }
5257
5258 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5259 {
5260         struct bnxt_error_recovery_info *info = bp->recovery_info;
5261
5262         if (info) {
5263                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5264                         memset(info, 0, sizeof(*info));
5265                 return;
5266         }
5267
5268         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5269                 return;
5270
5271         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5272                            sizeof(*info), 0);
5273         if (!info)
5274                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5275
5276         bp->recovery_info = info;
5277 }
5278
5279 static void bnxt_check_fw_status(struct bnxt *bp)
5280 {
5281         uint32_t fw_status;
5282
5283         if (!(bp->recovery_info &&
5284               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5285                 return;
5286
5287         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5288         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5289                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5290                             fw_status);
5291 }
5292
5293 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5294 {
5295         struct bnxt_error_recovery_info *info = bp->recovery_info;
5296         uint32_t status_loc;
5297         uint32_t sig_ver;
5298
5299         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5300                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5301         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5302                                    BNXT_GRCP_WINDOW_2_BASE +
5303                                    offsetof(struct hcomm_status,
5304                                             sig_ver)));
5305         /* If the signature is absent, then FW does not support this feature */
5306         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5307             HCOMM_STATUS_SIGNATURE_VAL)
5308                 return 0;
5309
5310         if (!info) {
5311                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5312                                    sizeof(*info), 0);
5313                 if (!info)
5314                         return -ENOMEM;
5315                 bp->recovery_info = info;
5316         } else {
5317                 memset(info, 0, sizeof(*info));
5318         }
5319
5320         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5321                                       BNXT_GRCP_WINDOW_2_BASE +
5322                                       offsetof(struct hcomm_status,
5323                                                fw_status_loc)));
5324
5325         /* Only pre-map the FW health status GRC register */
5326         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5327                 return 0;
5328
5329         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5330         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5331                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5332
5333         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5334                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5335
5336         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5337
5338         return 0;
5339 }
5340
5341 /* This function gets the FW version along with the
5342  * capabilities(MAX and current) of the function, vnic,
5343  * error recovery, phy and other chip related info
5344  */
5345 static int bnxt_get_config(struct bnxt *bp)
5346 {
5347         uint16_t mtu;
5348         int rc = 0;
5349
5350         bp->fw_cap = 0;
5351
5352         rc = bnxt_map_hcomm_fw_status_reg(bp);
5353         if (rc)
5354                 return rc;
5355
5356         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5357         if (rc) {
5358                 bnxt_check_fw_status(bp);
5359                 return rc;
5360         }
5361
5362         rc = bnxt_hwrm_func_reset(bp);
5363         if (rc)
5364                 return -EIO;
5365
5366         rc = bnxt_hwrm_vnic_qcaps(bp);
5367         if (rc)
5368                 return rc;
5369
5370         rc = bnxt_hwrm_queue_qportcfg(bp);
5371         if (rc)
5372                 return rc;
5373
5374         /* Get the MAX capabilities for this function.
5375          * This function also allocates context memory for TQM rings and
5376          * informs the firmware about this allocated backing store memory.
5377          */
5378         rc = bnxt_hwrm_func_qcaps(bp);
5379         if (rc)
5380                 return rc;
5381
5382         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5383         if (rc)
5384                 return rc;
5385
5386         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5387         if (rc)
5388                 return rc;
5389
5390         bnxt_hwrm_port_mac_qcfg(bp);
5391
5392         bnxt_hwrm_parent_pf_qcfg(bp);
5393
5394         bnxt_hwrm_port_phy_qcaps(bp);
5395
5396         bnxt_alloc_error_recovery_info(bp);
5397         /* Get the adapter error recovery support info */
5398         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5399         if (rc)
5400                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5401
5402         bnxt_hwrm_port_led_qcaps(bp);
5403
5404         return 0;
5405 }
5406
5407 static int
5408 bnxt_init_locks(struct bnxt *bp)
5409 {
5410         int err;
5411
5412         err = pthread_mutex_init(&bp->flow_lock, NULL);
5413         if (err) {
5414                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5415                 return err;
5416         }
5417
5418         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5419         if (err) {
5420                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5421                 return err;
5422         }
5423
5424         err = pthread_mutex_init(&bp->health_check_lock, NULL);
5425         if (err) {
5426                 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5427                 return err;
5428         }
5429
5430         err = pthread_mutex_init(&bp->err_recovery_lock, NULL);
5431         if (err)
5432                 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n");
5433
5434         return err;
5435 }
5436
5437 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5438 {
5439         int rc = 0;
5440
5441         rc = bnxt_get_config(bp);
5442         if (rc)
5443                 return rc;
5444
5445         if (!reconfig_dev) {
5446                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5447                 if (rc)
5448                         return rc;
5449         } else {
5450                 rc = bnxt_restore_dflt_mac(bp);
5451                 if (rc)
5452                         return rc;
5453         }
5454
5455         bnxt_config_vf_req_fwd(bp);
5456
5457         rc = bnxt_hwrm_func_driver_register(bp);
5458         if (rc) {
5459                 PMD_DRV_LOG(ERR, "Failed to register driver");
5460                 return -EBUSY;
5461         }
5462
5463         if (BNXT_PF(bp)) {
5464                 if (bp->pdev->max_vfs) {
5465                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5466                         if (rc) {
5467                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5468                                 return rc;
5469                         }
5470                 } else {
5471                         rc = bnxt_hwrm_allocate_pf_only(bp);
5472                         if (rc) {
5473                                 PMD_DRV_LOG(ERR,
5474                                             "Failed to allocate PF resources");
5475                                 return rc;
5476                         }
5477                 }
5478         }
5479
5480         rc = bnxt_alloc_mem(bp, reconfig_dev);
5481         if (rc)
5482                 return rc;
5483
5484         rc = bnxt_setup_int(bp);
5485         if (rc)
5486                 return rc;
5487
5488         rc = bnxt_request_int(bp);
5489         if (rc)
5490                 return rc;
5491
5492         rc = bnxt_init_ctx_mem(bp);
5493         if (rc) {
5494                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5495                 return rc;
5496         }
5497
5498         return 0;
5499 }
5500
5501 static int
5502 bnxt_parse_devarg_accum_stats(__rte_unused const char *key,
5503                               const char *value, void *opaque_arg)
5504 {
5505         struct bnxt *bp = opaque_arg;
5506         unsigned long accum_stats;
5507         char *end = NULL;
5508
5509         if (!value || !opaque_arg) {
5510                 PMD_DRV_LOG(ERR,
5511                             "Invalid parameter passed to accum-stats devargs.\n");
5512                 return -EINVAL;
5513         }
5514
5515         accum_stats = strtoul(value, &end, 10);
5516         if (end == NULL || *end != '\0' ||
5517             (accum_stats == ULONG_MAX && errno == ERANGE)) {
5518                 PMD_DRV_LOG(ERR,
5519                             "Invalid parameter passed to accum-stats devargs.\n");
5520                 return -EINVAL;
5521         }
5522
5523         if (BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats)) {
5524                 PMD_DRV_LOG(ERR,
5525                             "Invalid value passed to accum-stats devargs.\n");
5526                 return -EINVAL;
5527         }
5528
5529         if (accum_stats) {
5530                 bp->flags2 |= BNXT_FLAGS2_ACCUM_STATS_EN;
5531                 PMD_DRV_LOG(INFO, "Host-based accum-stats feature enabled.\n");
5532         } else {
5533                 bp->flags2 &= ~BNXT_FLAGS2_ACCUM_STATS_EN;
5534                 PMD_DRV_LOG(INFO, "Host-based accum-stats feature disabled.\n");
5535         }
5536
5537         return 0;
5538 }
5539
5540 static int
5541 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5542                              const char *value, void *opaque_arg)
5543 {
5544         struct bnxt *bp = opaque_arg;
5545         unsigned long flow_xstat;
5546         char *end = NULL;
5547
5548         if (!value || !opaque_arg) {
5549                 PMD_DRV_LOG(ERR,
5550                             "Invalid parameter passed to flow_xstat devarg.\n");
5551                 return -EINVAL;
5552         }
5553
5554         flow_xstat = strtoul(value, &end, 10);
5555         if (end == NULL || *end != '\0' ||
5556             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5557                 PMD_DRV_LOG(ERR,
5558                             "Invalid parameter passed to flow_xstat devarg.\n");
5559                 return -EINVAL;
5560         }
5561
5562         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5563                 PMD_DRV_LOG(ERR,
5564                             "Invalid value passed to flow_xstat devarg.\n");
5565                 return -EINVAL;
5566         }
5567
5568         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5569         if (BNXT_FLOW_XSTATS_EN(bp))
5570                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5571
5572         return 0;
5573 }
5574
5575 static int
5576 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5577                                         const char *value, void *opaque_arg)
5578 {
5579         struct bnxt *bp = opaque_arg;
5580         unsigned long max_num_kflows;
5581         char *end = NULL;
5582
5583         if (!value || !opaque_arg) {
5584                 PMD_DRV_LOG(ERR,
5585                         "Invalid parameter passed to max_num_kflows devarg.\n");
5586                 return -EINVAL;
5587         }
5588
5589         max_num_kflows = strtoul(value, &end, 10);
5590         if (end == NULL || *end != '\0' ||
5591                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5592                 PMD_DRV_LOG(ERR,
5593                         "Invalid parameter passed to max_num_kflows devarg.\n");
5594                 return -EINVAL;
5595         }
5596
5597         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5598                 PMD_DRV_LOG(ERR,
5599                         "Invalid value passed to max_num_kflows devarg.\n");
5600                 return -EINVAL;
5601         }
5602
5603         bp->max_num_kflows = max_num_kflows;
5604         if (bp->max_num_kflows)
5605                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5606                                 max_num_kflows);
5607
5608         return 0;
5609 }
5610
5611 static int
5612 bnxt_parse_devarg_app_id(__rte_unused const char *key,
5613                                  const char *value, void *opaque_arg)
5614 {
5615         struct bnxt *bp = opaque_arg;
5616         unsigned long app_id;
5617         char *end = NULL;
5618
5619         if (!value || !opaque_arg) {
5620                 PMD_DRV_LOG(ERR,
5621                             "Invalid parameter passed to app-id "
5622                             "devargs.\n");
5623                 return -EINVAL;
5624         }
5625
5626         app_id = strtoul(value, &end, 10);
5627         if (end == NULL || *end != '\0' ||
5628             (app_id == ULONG_MAX && errno == ERANGE)) {
5629                 PMD_DRV_LOG(ERR,
5630                             "Invalid parameter passed to app_id "
5631                             "devargs.\n");
5632                 return -EINVAL;
5633         }
5634
5635         if (BNXT_DEVARG_APP_ID_INVALID(app_id)) {
5636                 PMD_DRV_LOG(ERR, "Invalid app-id(%d) devargs.\n",
5637                             (uint16_t)app_id);
5638                 return -EINVAL;
5639         }
5640
5641         bp->app_id = app_id;
5642         PMD_DRV_LOG(INFO, "app-id=%d feature enabled.\n", (uint16_t)app_id);
5643
5644         return 0;
5645 }
5646
5647 static int
5648 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5649                             const char *value, void *opaque_arg)
5650 {
5651         struct bnxt_representor *vfr_bp = opaque_arg;
5652         unsigned long rep_is_pf;
5653         char *end = NULL;
5654
5655         if (!value || !opaque_arg) {
5656                 PMD_DRV_LOG(ERR,
5657                             "Invalid parameter passed to rep_is_pf devargs.\n");
5658                 return -EINVAL;
5659         }
5660
5661         rep_is_pf = strtoul(value, &end, 10);
5662         if (end == NULL || *end != '\0' ||
5663             (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5664                 PMD_DRV_LOG(ERR,
5665                             "Invalid parameter passed to rep_is_pf devargs.\n");
5666                 return -EINVAL;
5667         }
5668
5669         if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5670                 PMD_DRV_LOG(ERR,
5671                             "Invalid value passed to rep_is_pf devargs.\n");
5672                 return -EINVAL;
5673         }
5674
5675         vfr_bp->flags |= rep_is_pf;
5676         if (BNXT_REP_PF(vfr_bp))
5677                 PMD_DRV_LOG(INFO, "PF representor\n");
5678         else
5679                 PMD_DRV_LOG(INFO, "VF representor\n");
5680
5681         return 0;
5682 }
5683
5684 static int
5685 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5686                                const char *value, void *opaque_arg)
5687 {
5688         struct bnxt_representor *vfr_bp = opaque_arg;
5689         unsigned long rep_based_pf;
5690         char *end = NULL;
5691
5692         if (!value || !opaque_arg) {
5693                 PMD_DRV_LOG(ERR,
5694                             "Invalid parameter passed to rep_based_pf "
5695                             "devargs.\n");
5696                 return -EINVAL;
5697         }
5698
5699         rep_based_pf = strtoul(value, &end, 10);
5700         if (end == NULL || *end != '\0' ||
5701             (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5702                 PMD_DRV_LOG(ERR,
5703                             "Invalid parameter passed to rep_based_pf "
5704                             "devargs.\n");
5705                 return -EINVAL;
5706         }
5707
5708         if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5709                 PMD_DRV_LOG(ERR,
5710                             "Invalid value passed to rep_based_pf devargs.\n");
5711                 return -EINVAL;
5712         }
5713
5714         vfr_bp->rep_based_pf = rep_based_pf;
5715         vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
5716
5717         PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5718
5719         return 0;
5720 }
5721
5722 static int
5723 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5724                             const char *value, void *opaque_arg)
5725 {
5726         struct bnxt_representor *vfr_bp = opaque_arg;
5727         unsigned long rep_q_r2f;
5728         char *end = NULL;
5729
5730         if (!value || !opaque_arg) {
5731                 PMD_DRV_LOG(ERR,
5732                             "Invalid parameter passed to rep_q_r2f "
5733                             "devargs.\n");
5734                 return -EINVAL;
5735         }
5736
5737         rep_q_r2f = strtoul(value, &end, 10);
5738         if (end == NULL || *end != '\0' ||
5739             (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5740                 PMD_DRV_LOG(ERR,
5741                             "Invalid parameter passed to rep_q_r2f "
5742                             "devargs.\n");
5743                 return -EINVAL;
5744         }
5745
5746         if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5747                 PMD_DRV_LOG(ERR,
5748                             "Invalid value passed to rep_q_r2f devargs.\n");
5749                 return -EINVAL;
5750         }
5751
5752         vfr_bp->rep_q_r2f = rep_q_r2f;
5753         vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5754         PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5755
5756         return 0;
5757 }
5758
5759 static int
5760 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5761                             const char *value, void *opaque_arg)
5762 {
5763         struct bnxt_representor *vfr_bp = opaque_arg;
5764         unsigned long rep_q_f2r;
5765         char *end = NULL;
5766
5767         if (!value || !opaque_arg) {
5768                 PMD_DRV_LOG(ERR,
5769                             "Invalid parameter passed to rep_q_f2r "
5770                             "devargs.\n");
5771                 return -EINVAL;
5772         }
5773
5774         rep_q_f2r = strtoul(value, &end, 10);
5775         if (end == NULL || *end != '\0' ||
5776             (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5777                 PMD_DRV_LOG(ERR,
5778                             "Invalid parameter passed to rep_q_f2r "
5779                             "devargs.\n");
5780                 return -EINVAL;
5781         }
5782
5783         if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5784                 PMD_DRV_LOG(ERR,
5785                             "Invalid value passed to rep_q_f2r devargs.\n");
5786                 return -EINVAL;
5787         }
5788
5789         vfr_bp->rep_q_f2r = rep_q_f2r;
5790         vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5791         PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5792
5793         return 0;
5794 }
5795
5796 static int
5797 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5798                              const char *value, void *opaque_arg)
5799 {
5800         struct bnxt_representor *vfr_bp = opaque_arg;
5801         unsigned long rep_fc_r2f;
5802         char *end = NULL;
5803
5804         if (!value || !opaque_arg) {
5805                 PMD_DRV_LOG(ERR,
5806                             "Invalid parameter passed to rep_fc_r2f "
5807                             "devargs.\n");
5808                 return -EINVAL;
5809         }
5810
5811         rep_fc_r2f = strtoul(value, &end, 10);
5812         if (end == NULL || *end != '\0' ||
5813             (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5814                 PMD_DRV_LOG(ERR,
5815                             "Invalid parameter passed to rep_fc_r2f "
5816                             "devargs.\n");
5817                 return -EINVAL;
5818         }
5819
5820         if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5821                 PMD_DRV_LOG(ERR,
5822                             "Invalid value passed to rep_fc_r2f devargs.\n");
5823                 return -EINVAL;
5824         }
5825
5826         vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5827         vfr_bp->rep_fc_r2f = rep_fc_r2f;
5828         PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5829
5830         return 0;
5831 }
5832
5833 static int
5834 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5835                              const char *value, void *opaque_arg)
5836 {
5837         struct bnxt_representor *vfr_bp = opaque_arg;
5838         unsigned long rep_fc_f2r;
5839         char *end = NULL;
5840
5841         if (!value || !opaque_arg) {
5842                 PMD_DRV_LOG(ERR,
5843                             "Invalid parameter passed to rep_fc_f2r "
5844                             "devargs.\n");
5845                 return -EINVAL;
5846         }
5847
5848         rep_fc_f2r = strtoul(value, &end, 10);
5849         if (end == NULL || *end != '\0' ||
5850             (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5851                 PMD_DRV_LOG(ERR,
5852                             "Invalid parameter passed to rep_fc_f2r "
5853                             "devargs.\n");
5854                 return -EINVAL;
5855         }
5856
5857         if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5858                 PMD_DRV_LOG(ERR,
5859                             "Invalid value passed to rep_fc_f2r devargs.\n");
5860                 return -EINVAL;
5861         }
5862
5863         vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5864         vfr_bp->rep_fc_f2r = rep_fc_f2r;
5865         PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5866
5867         return 0;
5868 }
5869
5870 static int
5871 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5872 {
5873         struct rte_kvargs *kvlist;
5874         int ret;
5875
5876         if (devargs == NULL)
5877                 return 0;
5878
5879         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5880         if (kvlist == NULL)
5881                 return -EINVAL;
5882
5883         /*
5884          * Handler for "flow_xstat" devarg.
5885          * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5886          */
5887         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5888                                  bnxt_parse_devarg_flow_xstat, bp);
5889         if (ret)
5890                 goto err;
5891
5892         /*
5893          * Handler for "accum-stats" devarg.
5894          * Invoked as for ex: "-a 0000:00:0d.0,accum-stats=1"
5895          */
5896         rte_kvargs_process(kvlist, BNXT_DEVARG_ACCUM_STATS,
5897                            bnxt_parse_devarg_accum_stats, bp);
5898         /*
5899          * Handler for "max_num_kflows" devarg.
5900          * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5901          */
5902         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5903                                  bnxt_parse_devarg_max_num_kflows, bp);
5904         if (ret)
5905                 goto err;
5906
5907 err:
5908         /*
5909          * Handler for "app-id" devarg.
5910          * Invoked as for ex: "-a 000:00:0d.0,app-id=1"
5911          */
5912         rte_kvargs_process(kvlist, BNXT_DEVARG_APP_ID,
5913                            bnxt_parse_devarg_app_id, bp);
5914
5915         rte_kvargs_free(kvlist);
5916         return ret;
5917 }
5918
5919 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5920 {
5921         int rc = 0;
5922
5923         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5924                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5925                 if (rc)
5926                         PMD_DRV_LOG(ERR,
5927                                     "Failed to alloc switch domain: %d\n", rc);
5928                 else
5929                         PMD_DRV_LOG(INFO,
5930                                     "Switch domain allocated %d\n",
5931                                     bp->switch_domain_id);
5932         }
5933
5934         return rc;
5935 }
5936
5937 /* Allocate and initialize various fields in bnxt struct that
5938  * need to be allocated/destroyed only once in the lifetime of the driver
5939  */
5940 static int bnxt_drv_init(struct rte_eth_dev *eth_dev)
5941 {
5942         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5943         struct bnxt *bp = eth_dev->data->dev_private;
5944         int rc = 0;
5945
5946         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5947
5948         if (bnxt_vf_pciid(pci_dev->id.device_id))
5949                 bp->flags |= BNXT_FLAG_VF;
5950
5951         if (bnxt_p5_device(pci_dev->id.device_id))
5952                 bp->flags |= BNXT_FLAG_CHIP_P5;
5953
5954         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5955             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5956             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5957             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5958                 bp->flags |= BNXT_FLAG_STINGRAY;
5959
5960         if (BNXT_TRUFLOW_EN(bp)) {
5961                 /* extra mbuf field is required to store CFA code from mark */
5962                 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5963                         .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5964                         .size = sizeof(bnxt_cfa_code_dynfield_t),
5965                         .align = __alignof__(bnxt_cfa_code_dynfield_t),
5966                 };
5967                 bnxt_cfa_code_dynfield_offset =
5968                         rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5969                 if (bnxt_cfa_code_dynfield_offset < 0) {
5970                         PMD_DRV_LOG(ERR,
5971                             "Failed to register mbuf field for TruFlow mark\n");
5972                         return -rte_errno;
5973                 }
5974         }
5975
5976         rc = bnxt_map_pci_bars(eth_dev);
5977         if (rc) {
5978                 PMD_DRV_LOG(ERR,
5979                             "Failed to initialize board rc: %x\n", rc);
5980                 return rc;
5981         }
5982
5983         rc = bnxt_alloc_pf_info(bp);
5984         if (rc)
5985                 return rc;
5986
5987         rc = bnxt_alloc_link_info(bp);
5988         if (rc)
5989                 return rc;
5990
5991         rc = bnxt_alloc_parent_info(bp);
5992         if (rc)
5993                 return rc;
5994
5995         rc = bnxt_alloc_hwrm_resources(bp);
5996         if (rc) {
5997                 PMD_DRV_LOG(ERR,
5998                             "Failed to allocate response buffer rc: %x\n", rc);
5999                 return rc;
6000         }
6001         rc = bnxt_alloc_leds_info(bp);
6002         if (rc)
6003                 return rc;
6004
6005         rc = bnxt_alloc_cos_queues(bp);
6006         if (rc)
6007                 return rc;
6008
6009         rc = bnxt_init_locks(bp);
6010         if (rc)
6011                 return rc;
6012
6013         rc = bnxt_alloc_switch_domain(bp);
6014         if (rc)
6015                 return rc;
6016
6017         return rc;
6018 }
6019
6020 static int
6021 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
6022 {
6023         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
6024         static int version_printed;
6025         struct bnxt *bp;
6026         int rc;
6027
6028         if (version_printed++ == 0)
6029                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
6030
6031         eth_dev->dev_ops = &bnxt_dev_ops;
6032         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
6033         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
6034         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
6035         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
6036         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
6037
6038         /*
6039          * For secondary processes, we don't initialise any further
6040          * as primary has already done this work.
6041          */
6042         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6043                 return 0;
6044
6045         rte_eth_copy_pci_info(eth_dev, pci_dev);
6046         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
6047
6048         bp = eth_dev->data->dev_private;
6049
6050         /* Parse dev arguments passed on when starting the DPDK application. */
6051         rc = bnxt_parse_dev_args(bp, pci_dev->device.devargs);
6052         if (rc)
6053                 goto error_free;
6054
6055         rc = bnxt_drv_init(eth_dev);
6056         if (rc)
6057                 goto error_free;
6058
6059         rc = bnxt_init_resources(bp, false);
6060         if (rc)
6061                 goto error_free;
6062
6063         rc = bnxt_alloc_stats_mem(bp);
6064         if (rc)
6065                 goto error_free;
6066
6067         PMD_DRV_LOG(INFO,
6068                     "Found %s device at mem %" PRIX64 ", node addr %pM\n",
6069                     DRV_MODULE_NAME,
6070                     pci_dev->mem_resource[0].phys_addr,
6071                     pci_dev->mem_resource[0].addr);
6072
6073         return 0;
6074
6075 error_free:
6076         bnxt_dev_uninit(eth_dev);
6077         return rc;
6078 }
6079
6080
6081 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
6082 {
6083         if (!ctx)
6084                 return;
6085
6086         if (ctx->va)
6087                 rte_free(ctx->va);
6088
6089         ctx->va = NULL;
6090         ctx->dma = RTE_BAD_IOVA;
6091         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
6092 }
6093
6094 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
6095 {
6096         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
6097                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6098                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
6099                                   bp->flow_stat->max_fc,
6100                                   false);
6101
6102         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
6103                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6104                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
6105                                   bp->flow_stat->max_fc,
6106                                   false);
6107
6108         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6109                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
6110         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6111
6112         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6113                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
6114         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6115
6116         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6117                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
6118         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6119
6120         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6121                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
6122         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6123 }
6124
6125 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
6126 {
6127         bnxt_unregister_fc_ctx_mem(bp);
6128
6129         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
6130         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
6131         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
6132         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
6133 }
6134
6135 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
6136 {
6137         if (BNXT_FLOW_XSTATS_EN(bp))
6138                 bnxt_uninit_fc_ctx_mem(bp);
6139 }
6140
6141 static void
6142 bnxt_free_error_recovery_info(struct bnxt *bp)
6143 {
6144         rte_free(bp->recovery_info);
6145         bp->recovery_info = NULL;
6146         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
6147 }
6148
6149 static int
6150 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
6151 {
6152         int rc;
6153
6154         bnxt_free_int(bp);
6155         bnxt_free_mem(bp, reconfig_dev);
6156
6157         bnxt_hwrm_func_buf_unrgtr(bp);
6158         if (bp->pf != NULL) {
6159                 rte_free(bp->pf->vf_req_buf);
6160                 bp->pf->vf_req_buf = NULL;
6161         }
6162
6163         rc = bnxt_hwrm_func_driver_unregister(bp);
6164         bp->flags &= ~BNXT_FLAG_REGISTERED;
6165         bnxt_free_ctx_mem(bp);
6166         if (!reconfig_dev) {
6167                 bnxt_free_hwrm_resources(bp);
6168                 bnxt_free_error_recovery_info(bp);
6169         }
6170
6171         bnxt_uninit_ctx_mem(bp);
6172
6173         bnxt_free_flow_stats_info(bp);
6174         if (bp->rep_info != NULL)
6175                 bnxt_free_switch_domain(bp);
6176         bnxt_free_rep_info(bp);
6177         rte_free(bp->ptp_cfg);
6178         bp->ptp_cfg = NULL;
6179         return rc;
6180 }
6181
6182 static int
6183 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
6184 {
6185         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6186                 return -EPERM;
6187
6188         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
6189
6190         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
6191                 bnxt_dev_close_op(eth_dev);
6192
6193         return 0;
6194 }
6195
6196 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
6197 {
6198         struct bnxt *bp = eth_dev->data->dev_private;
6199         struct rte_eth_dev *vf_rep_eth_dev;
6200         int ret = 0, i;
6201
6202         if (!bp)
6203                 return -EINVAL;
6204
6205         for (i = 0; i < bp->num_reps; i++) {
6206                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
6207                 if (!vf_rep_eth_dev)
6208                         continue;
6209                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
6210                             vf_rep_eth_dev->data->port_id);
6211                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
6212         }
6213         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
6214                     eth_dev->data->port_id);
6215         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
6216
6217         return ret;
6218 }
6219
6220 static void bnxt_free_rep_info(struct bnxt *bp)
6221 {
6222         rte_free(bp->rep_info);
6223         bp->rep_info = NULL;
6224         rte_free(bp->cfa_code_map);
6225         bp->cfa_code_map = NULL;
6226 }
6227
6228 static int bnxt_init_rep_info(struct bnxt *bp)
6229 {
6230         int i = 0, rc;
6231
6232         if (bp->rep_info)
6233                 return 0;
6234
6235         bp->rep_info = rte_zmalloc("bnxt_rep_info",
6236                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
6237                                    0);
6238         if (!bp->rep_info) {
6239                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
6240                 return -ENOMEM;
6241         }
6242         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
6243                                        sizeof(*bp->cfa_code_map) *
6244                                        BNXT_MAX_CFA_CODE, 0);
6245         if (!bp->cfa_code_map) {
6246                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
6247                 bnxt_free_rep_info(bp);
6248                 return -ENOMEM;
6249         }
6250
6251         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
6252                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
6253
6254         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
6255         if (rc) {
6256                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
6257                 bnxt_free_rep_info(bp);
6258                 return rc;
6259         }
6260
6261         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
6262         if (rc) {
6263                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
6264                 bnxt_free_rep_info(bp);
6265                 return rc;
6266         }
6267
6268         return rc;
6269 }
6270
6271 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
6272                                struct rte_eth_devargs *eth_da,
6273                                struct rte_eth_dev *backing_eth_dev,
6274                                const char *dev_args)
6275 {
6276         struct rte_eth_dev *vf_rep_eth_dev;
6277         char name[RTE_ETH_NAME_MAX_LEN];
6278         struct bnxt *backing_bp;
6279         uint16_t num_rep;
6280         int i, ret = 0;
6281         struct rte_kvargs *kvlist = NULL;
6282
6283         if (eth_da->type == RTE_ETH_REPRESENTOR_NONE)
6284                 return 0;
6285         if (eth_da->type != RTE_ETH_REPRESENTOR_VF) {
6286                 PMD_DRV_LOG(ERR, "unsupported representor type %d\n",
6287                             eth_da->type);
6288                 return -ENOTSUP;
6289         }
6290         num_rep = eth_da->nb_representor_ports;
6291         if (num_rep > BNXT_MAX_VF_REPS) {
6292                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
6293                             num_rep, BNXT_MAX_VF_REPS);
6294                 return -EINVAL;
6295         }
6296
6297         if (num_rep >= RTE_MAX_ETHPORTS) {
6298                 PMD_DRV_LOG(ERR,
6299                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6300                             num_rep, RTE_MAX_ETHPORTS);
6301                 return -EINVAL;
6302         }
6303
6304         backing_bp = backing_eth_dev->data->dev_private;
6305
6306         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6307                 PMD_DRV_LOG(ERR,
6308                             "Not a PF or trusted VF. No Representor support\n");
6309                 /* Returning an error is not an option.
6310                  * Applications are not handling this correctly
6311                  */
6312                 return 0;
6313         }
6314
6315         if (bnxt_init_rep_info(backing_bp))
6316                 return 0;
6317
6318         for (i = 0; i < num_rep; i++) {
6319                 struct bnxt_representor representor = {
6320                         .vf_id = eth_da->representor_ports[i],
6321                         .switch_domain_id = backing_bp->switch_domain_id,
6322                         .parent_dev = backing_eth_dev
6323                 };
6324
6325                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6326                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6327                                     representor.vf_id, BNXT_MAX_VF_REPS);
6328                         continue;
6329                 }
6330
6331                 /* representor port net_bdf_port */
6332                 snprintf(name, sizeof(name), "net_%s_representor_%d",
6333                          pci_dev->device.name, eth_da->representor_ports[i]);
6334
6335                 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
6336                 if (kvlist) {
6337                         /*
6338                          * Handler for "rep_is_pf" devarg.
6339                          * Invoked as for ex: "-a 000:00:0d.0,
6340                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6341                          */
6342                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
6343                                                  bnxt_parse_devarg_rep_is_pf,
6344                                                  (void *)&representor);
6345                         if (ret) {
6346                                 ret = -EINVAL;
6347                                 goto err;
6348                         }
6349                         /*
6350                          * Handler for "rep_based_pf" devarg.
6351                          * Invoked as for ex: "-a 000:00:0d.0,
6352                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6353                          */
6354                         ret = rte_kvargs_process(kvlist,
6355                                                  BNXT_DEVARG_REP_BASED_PF,
6356                                                  bnxt_parse_devarg_rep_based_pf,
6357                                                  (void *)&representor);
6358                         if (ret) {
6359                                 ret = -EINVAL;
6360                                 goto err;
6361                         }
6362                         /*
6363                          * Handler for "rep_based_pf" devarg.
6364                          * Invoked as for ex: "-a 000:00:0d.0,
6365                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6366                          */
6367                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
6368                                                  bnxt_parse_devarg_rep_q_r2f,
6369                                                  (void *)&representor);
6370                         if (ret) {
6371                                 ret = -EINVAL;
6372                                 goto err;
6373                         }
6374                         /*
6375                          * Handler for "rep_based_pf" devarg.
6376                          * Invoked as for ex: "-a 000:00:0d.0,
6377                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6378                          */
6379                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
6380                                                  bnxt_parse_devarg_rep_q_f2r,
6381                                                  (void *)&representor);
6382                         if (ret) {
6383                                 ret = -EINVAL;
6384                                 goto err;
6385                         }
6386                         /*
6387                          * Handler for "rep_based_pf" devarg.
6388                          * Invoked as for ex: "-a 000:00:0d.0,
6389                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6390                          */
6391                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
6392                                                  bnxt_parse_devarg_rep_fc_r2f,
6393                                                  (void *)&representor);
6394                         if (ret) {
6395                                 ret = -EINVAL;
6396                                 goto err;
6397                         }
6398                         /*
6399                          * Handler for "rep_based_pf" devarg.
6400                          * Invoked as for ex: "-a 000:00:0d.0,
6401                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6402                          */
6403                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
6404                                                  bnxt_parse_devarg_rep_fc_f2r,
6405                                                  (void *)&representor);
6406                         if (ret) {
6407                                 ret = -EINVAL;
6408                                 goto err;
6409                         }
6410                 }
6411
6412                 ret = rte_eth_dev_create(&pci_dev->device, name,
6413                                          sizeof(struct bnxt_representor),
6414                                          NULL, NULL,
6415                                          bnxt_representor_init,
6416                                          &representor);
6417                 if (ret) {
6418                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6419                                     "representor %s.", name);
6420                         goto err;
6421                 }
6422
6423                 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6424                 if (!vf_rep_eth_dev) {
6425                         PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6426                                     " for VF-Rep: %s.", name);
6427                         ret = -ENODEV;
6428                         goto err;
6429                 }
6430
6431                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6432                             backing_eth_dev->data->port_id);
6433                 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6434                                                          vf_rep_eth_dev;
6435                 backing_bp->num_reps++;
6436
6437         }
6438
6439         rte_kvargs_free(kvlist);
6440         return 0;
6441
6442 err:
6443         /* If num_rep > 1, then rollback already created
6444          * ports, since we'll be failing the probe anyway
6445          */
6446         if (num_rep > 1)
6447                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6448         rte_errno = -ret;
6449         rte_kvargs_free(kvlist);
6450
6451         return ret;
6452 }
6453
6454 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6455                           struct rte_pci_device *pci_dev)
6456 {
6457         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6458         struct rte_eth_dev *backing_eth_dev;
6459         uint16_t num_rep;
6460         int ret = 0;
6461
6462         if (pci_dev->device.devargs) {
6463                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6464                                             &eth_da);
6465                 if (ret)
6466                         return ret;
6467         }
6468
6469         num_rep = eth_da.nb_representor_ports;
6470         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6471                     num_rep);
6472
6473         /* We could come here after first level of probe is already invoked
6474          * as part of an application bringup(OVS-DPDK vswitchd), so first check
6475          * for already allocated eth_dev for the backing device (PF/Trusted VF)
6476          */
6477         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6478         if (backing_eth_dev == NULL) {
6479                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6480                                          sizeof(struct bnxt),
6481                                          eth_dev_pci_specific_init, pci_dev,
6482                                          bnxt_dev_init, NULL);
6483
6484                 if (ret || !num_rep)
6485                         return ret;
6486
6487                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6488         }
6489         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6490                     backing_eth_dev->data->port_id);
6491
6492         if (!num_rep)
6493                 return ret;
6494
6495         /* probe representor ports now */
6496         ret = bnxt_rep_port_probe(pci_dev, &eth_da, backing_eth_dev,
6497                                   pci_dev->device.devargs->args);
6498
6499         return ret;
6500 }
6501
6502 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6503 {
6504         struct rte_eth_dev *eth_dev;
6505
6506         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6507         if (!eth_dev)
6508                 return 0; /* Invoked typically only by OVS-DPDK, by the
6509                            * time it comes here the eth_dev is already
6510                            * deleted by rte_eth_dev_close(), so returning
6511                            * +ve value will at least help in proper cleanup
6512                            */
6513
6514         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6515         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6516                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6517                         return rte_eth_dev_destroy(eth_dev,
6518                                                    bnxt_representor_uninit);
6519                 else
6520                         return rte_eth_dev_destroy(eth_dev,
6521                                                    bnxt_dev_uninit);
6522         } else {
6523                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6524         }
6525 }
6526
6527 static struct rte_pci_driver bnxt_rte_pmd = {
6528         .id_table = bnxt_pci_id_map,
6529         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6530                         RTE_PCI_DRV_INTR_RMV |
6531                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6532                                                   * and OVS-DPDK
6533                                                   */
6534         .probe = bnxt_pci_probe,
6535         .remove = bnxt_pci_remove,
6536 };
6537
6538 static bool
6539 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6540 {
6541         if (strcmp(dev->device->driver->name, drv->driver.name))
6542                 return false;
6543
6544         return true;
6545 }
6546
6547 bool is_bnxt_supported(struct rte_eth_dev *dev)
6548 {
6549         return is_device_supported(dev, &bnxt_rte_pmd);
6550 }
6551
6552 RTE_LOG_REGISTER_SUFFIX(bnxt_logtype_driver, driver, NOTICE);
6553 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6554 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6555