drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_irq.h"
  20 #include "bnxt_ring.h"
  21 #include "bnxt_rxq.h"
  22 #include "bnxt_rxr.h"
  23 #include "bnxt_stats.h"
  24 #include "bnxt_txq.h"
  25 #include "bnxt_txr.h"
  26 #include "bnxt_vnic.h"
  27 #include "hsi_struct_def_dpdk.h"
  28 #include "bnxt_nvm_defs.h"
  29
  30 #define DRV_MODULE_NAME         "bnxt"
  31 static const char bnxt_version[] =
  32         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  33 int bnxt_logtype_driver;
  34
  35 /*
  36  * The set of PCI devices this driver supports
  37  */
  38 static const struct rte_pci_id bnxt_pci_id_map[] = {
  39         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  40                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  41         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  42                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  43         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  45         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  92         { .vendor_id = 0, /* sentinel */ },
  93 };
  94
  95 #define BNXT_ETH_RSS_SUPPORT (  \
  96         ETH_RSS_IPV4 |          \
  97         ETH_RSS_NONFRAG_IPV4_TCP |      \
  98         ETH_RSS_NONFRAG_IPV4_UDP |      \
  99         ETH_RSS_IPV6 |          \
 100         ETH_RSS_NONFRAG_IPV6_TCP |      \
 101         ETH_RSS_NONFRAG_IPV6_UDP)
 102
 103 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 104                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 105                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 106                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 107                                      DEV_TX_OFFLOAD_TCP_TSO | \
 108                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 109                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 110                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 111                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 112                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 113                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 114                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 115
 116 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 117                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 118                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 119                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 120                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 121                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 122                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 123                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 124                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 125                                      DEV_RX_OFFLOAD_TCP_LRO | \
 126                                      DEV_RX_OFFLOAD_SCATTER)
 127
 128 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 129 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 130 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 131 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 132 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 133 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 134
 135 int is_bnxt_in_error(struct bnxt *bp)
 136 {
 137         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 138                 return -EIO;
 139         if (bp->flags & BNXT_FLAG_FW_RESET)
 140                 return -EBUSY;
 141
 142         return 0;
 143 }
 144
 145 /***********************/
 146
 147 /*
 148  * High level utility functions
 149  */
 150
 151 uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 152 {
 153         if (!BNXT_CHIP_THOR(bp))
 154                 return 1;
 155
 156         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 157                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 158                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 159 }
 160
 161 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 162 {
 163         if (!BNXT_CHIP_THOR(bp))
 164                 return HW_HASH_INDEX_SIZE;
 165
 166         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 167 }
 168
 169 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 170 {
 171         bnxt_free_filter_mem(bp);
 172         bnxt_free_vnic_attributes(bp);
 173         bnxt_free_vnic_mem(bp);
 174
 175         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 176          * If the number of rings change across fw update,
 177          * we don't have much choice except to warn the user.
 178          */
 179         if (!reconfig) {
 180                 bnxt_free_stats(bp);
 181                 bnxt_free_tx_rings(bp);
 182                 bnxt_free_rx_rings(bp);
 183         }
 184         bnxt_free_async_cp_ring(bp);
 185         bnxt_free_rxtx_nq_ring(bp);
 186
 187         rte_free(bp->grp_info);
 188         bp->grp_info = NULL;
 189 }
 190
 191 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 192 {
 193         int rc;
 194
 195         rc = bnxt_alloc_ring_grps(bp);
 196         if (rc)
 197                 goto alloc_mem_err;
 198
 199         rc = bnxt_alloc_async_ring_struct(bp);
 200         if (rc)
 201                 goto alloc_mem_err;
 202
 203         rc = bnxt_alloc_vnic_mem(bp);
 204         if (rc)
 205                 goto alloc_mem_err;
 206
 207         rc = bnxt_alloc_vnic_attributes(bp);
 208         if (rc)
 209                 goto alloc_mem_err;
 210
 211         rc = bnxt_alloc_filter_mem(bp);
 212         if (rc)
 213                 goto alloc_mem_err;
 214
 215         rc = bnxt_alloc_async_cp_ring(bp);
 216         if (rc)
 217                 goto alloc_mem_err;
 218
 219         rc = bnxt_alloc_rxtx_nq_ring(bp);
 220         if (rc)
 221                 goto alloc_mem_err;
 222
 223         return 0;
 224
 225 alloc_mem_err:
 226         bnxt_free_mem(bp, reconfig);
 227         return rc;
 228 }
 229
 230 static int bnxt_init_chip(struct bnxt *bp)
 231 {
 232         struct bnxt_rx_queue *rxq;
 233         struct rte_eth_link new;
 234         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 235         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 236         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 237         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 238         uint32_t intr_vector = 0;
 239         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 240         uint32_t vec = BNXT_MISC_VEC_ID;
 241         unsigned int i, j;
 242         int rc;
 243
 244         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 245                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 246                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 247                 bp->flags |= BNXT_FLAG_JUMBO;
 248         } else {
 249                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 250                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 251                 bp->flags &= ~BNXT_FLAG_JUMBO;
 252         }
 253
 254         /* THOR does not support ring groups.
 255          * But we will use the array to save RSS context IDs.
 256          */
 257         if (BNXT_CHIP_THOR(bp))
 258                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 259
 260         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 261         if (rc) {
 262                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 263                 goto err_out;
 264         }
 265
 266         rc = bnxt_alloc_hwrm_rings(bp);
 267         if (rc) {
 268                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 269                 goto err_out;
 270         }
 271
 272         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 273         if (rc) {
 274                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 275                 goto err_out;
 276         }
 277
 278         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 279                 goto skip_cosq_cfg;
 280
 281         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 282                 if (bp->rx_cos_queue[i].id != 0xff) {
 283                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 284
 285                         if (!vnic) {
 286                                 PMD_DRV_LOG(ERR,
 287                                             "Num pools more than FW profile\n");
 288                                 rc = -EINVAL;
 289                                 goto err_out;
 290                         }
 291                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 292                         bp->rx_cosq_cnt++;
 293                 }
 294         }
 295
 296 skip_cosq_cfg:
 297         rc = bnxt_mq_rx_configure(bp);
 298         if (rc) {
 299                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 300                 goto err_out;
 301         }
 302
 303         /* VNIC configuration */
 304         for (i = 0; i < bp->nr_vnics; i++) {
 305                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 306                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 307
 308                 rc = bnxt_vnic_grp_alloc(bp, vnic);
 309                 if (rc)
 310                         goto err_out;
 311
 312                 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 313                             i, vnic, vnic->fw_grp_ids);
 314
 315                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 316                 if (rc) {
 317                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 318                                 i, rc);
 319                         goto err_out;
 320                 }
 321
 322                 /* Alloc RSS context only if RSS mode is enabled */
 323                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 324                         int j, nr_ctxs = bnxt_rss_ctxts(bp);
 325
 326                         rc = 0;
 327                         for (j = 0; j < nr_ctxs; j++) {
 328                                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 329                                 if (rc)
 330                                         break;
 331                         }
 332                         if (rc) {
 333                                 PMD_DRV_LOG(ERR,
 334                                   "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 335                                   i, j, rc);
 336                                 goto err_out;
 337                         }
 338                         vnic->num_lb_ctxts = nr_ctxs;
 339                 }
 340
 341                 /*
 342                  * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 343                  * setting is not available at this time, it will not be
 344                  * configured correctly in the CFA.
 345                  */
 346                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 347                         vnic->vlan_strip = true;
 348                 else
 349                         vnic->vlan_strip = false;
 350
 351                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 352                 if (rc) {
 353                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 354                                 i, rc);
 355                         goto err_out;
 356                 }
 357
 358                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 359                 if (rc) {
 360                         PMD_DRV_LOG(ERR,
 361                                 "HWRM vnic %d filter failure rc: %x\n",
 362                                 i, rc);
 363                         goto err_out;
 364                 }
 365
 366                 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 367                         rxq = bp->eth_dev->data->rx_queues[j];
 368
 369                         PMD_DRV_LOG(DEBUG,
 370                                     "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 371                                     j, rxq->vnic, rxq->vnic->fw_grp_ids);
 372
 373                         if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 374                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 375                 }
 376
 377                 rc = bnxt_vnic_rss_configure(bp, vnic);
 378                 if (rc) {
 379                         PMD_DRV_LOG(ERR,
 380                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 381                         goto err_out;
 382                 }
 383
 384                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 385
 386                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 387                     DEV_RX_OFFLOAD_TCP_LRO)
 388                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 389                 else
 390                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 391         }
 392         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 393         if (rc) {
 394                 PMD_DRV_LOG(ERR,
 395                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 396                 goto err_out;
 397         }
 398
 399         /* check and configure queue intr-vector mapping */
 400         if ((rte_intr_cap_multiple(intr_handle) ||
 401              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 402             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 403                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 404                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 405                 if (intr_vector > bp->rx_cp_nr_rings) {
 406                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 407                                         bp->rx_cp_nr_rings);
 408                         return -ENOTSUP;
 409                 }
 410                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 411                 if (rc)
 412                         return rc;
 413         }
 414
 415         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 416                 intr_handle->intr_vec =
 417                         rte_zmalloc("intr_vec",
 418                                     bp->eth_dev->data->nb_rx_queues *
 419                                     sizeof(int), 0);
 420                 if (intr_handle->intr_vec == NULL) {
 421                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 422                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 423                         rc = -ENOMEM;
 424                         goto err_disable;
 425                 }
 426                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 427                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 428                          intr_handle->intr_vec, intr_handle->nb_efd,
 429                         intr_handle->max_intr);
 430                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 431                      queue_id++) {
 432                         intr_handle->intr_vec[queue_id] =
 433                                                         vec + BNXT_RX_VEC_START;
 434                         if (vec < base + intr_handle->nb_efd - 1)
 435                                 vec++;
 436                 }
 437         }
 438
 439         /* enable uio/vfio intr/eventfd mapping */
 440         rc = rte_intr_enable(intr_handle);
 441         if (rc)
 442                 goto err_free;
 443
 444         rc = bnxt_get_hwrm_link_config(bp, &new);
 445         if (rc) {
 446                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 447                 goto err_free;
 448         }
 449
 450         if (!bp->link_info.link_up) {
 451                 rc = bnxt_set_hwrm_link_config(bp, true);
 452                 if (rc) {
 453                         PMD_DRV_LOG(ERR,
 454                                 "HWRM link config failure rc: %x\n", rc);
 455                         goto err_free;
 456                 }
 457         }
 458         bnxt_print_link_info(bp->eth_dev);
 459
 460         return 0;
 461
 462 err_free:
 463         rte_free(intr_handle->intr_vec);
 464 err_disable:
 465         rte_intr_efd_disable(intr_handle);
 466 err_out:
 467         /* Some of the error status returned by FW may not be from errno.h */
 468         if (rc > 0)
 469                 rc = -EIO;
 470
 471         return rc;
 472 }
 473
 474 static int bnxt_shutdown_nic(struct bnxt *bp)
 475 {
 476         bnxt_free_all_hwrm_resources(bp);
 477         bnxt_free_all_filters(bp);
 478         bnxt_free_all_vnics(bp);
 479         return 0;
 480 }
 481
 482 static int bnxt_init_nic(struct bnxt *bp)
 483 {
 484         int rc;
 485
 486         if (BNXT_HAS_RING_GRPS(bp)) {
 487                 rc = bnxt_init_ring_grps(bp);
 488                 if (rc)
 489                         return rc;
 490         }
 491
 492         bnxt_init_vnics(bp);
 493         bnxt_init_filters(bp);
 494
 495         return 0;
 496 }
 497
 498 /*
 499  * Device configuration and status function
 500  */
 501
 502 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 503                                 struct rte_eth_dev_info *dev_info)
 504 {
 505         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 506         struct bnxt *bp = eth_dev->data->dev_private;
 507         uint16_t max_vnics, i, j, vpool, vrxq;
 508         unsigned int max_rx_rings;
 509         int rc;
 510
 511         rc = is_bnxt_in_error(bp);
 512         if (rc)
 513                 return rc;
 514
 515         /* MAC Specifics */
 516         dev_info->max_mac_addrs = bp->max_l2_ctx;
 517         dev_info->max_hash_mac_addrs = 0;
 518
 519         /* PF/VF specifics */
 520         if (BNXT_PF(bp))
 521                 dev_info->max_vfs = pdev->max_vfs;
 522
 523         max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
 524         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 525         dev_info->max_rx_queues = max_rx_rings;
 526         dev_info->max_tx_queues = max_rx_rings;
 527         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 528         dev_info->hash_key_size = 40;
 529         max_vnics = bp->max_vnics;
 530
 531         /* MTU specifics */
 532         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 533         dev_info->max_mtu = BNXT_MAX_MTU;
 534
 535         /* Fast path specifics */
 536         dev_info->min_rx_bufsize = 1;
 537         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 538
 539         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 540         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 541                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 542         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 543         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 544
 545         /* *INDENT-OFF* */
 546         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 547                 .rx_thresh = {
 548                         .pthresh = 8,
 549                         .hthresh = 8,
 550                         .wthresh = 0,
 551                 },
 552                 .rx_free_thresh = 32,
 553                 /* If no descriptors available, pkts are dropped by default */
 554                 .rx_drop_en = 1,
 555         };
 556
 557         dev_info->default_txconf = (struct rte_eth_txconf) {
 558                 .tx_thresh = {
 559                         .pthresh = 32,
 560                         .hthresh = 0,
 561                         .wthresh = 0,
 562                 },
 563                 .tx_free_thresh = 32,
 564                 .tx_rs_thresh = 32,
 565         };
 566         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 567
 568         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 569         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 570         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 571         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 572         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 573
 574         /* *INDENT-ON* */
 575
 576         /*
 577          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 578          *       need further investigation.
 579          */
 580
 581         /* VMDq resources */
 582         vpool = 64; /* ETH_64_POOLS */
 583         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 584         for (i = 0; i < 4; vpool >>= 1, i++) {
 585                 if (max_vnics > vpool) {
 586                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 587                                 if (dev_info->max_rx_queues > vrxq) {
 588                                         if (vpool > vrxq)
 589                                                 vpool = vrxq;
 590                                         goto found;
 591                                 }
 592                         }
 593                         /* Not enough resources to support VMDq */
 594                         break;
 595                 }
 596         }
 597         /* Not enough resources to support VMDq */
 598         vpool = 0;
 599         vrxq = 0;
 600 found:
 601         dev_info->max_vmdq_pools = vpool;
 602         dev_info->vmdq_queue_num = vrxq;
 603
 604         dev_info->vmdq_pool_base = 0;
 605         dev_info->vmdq_queue_base = 0;
 606
 607         return 0;
 608 }
 609
 610 /* Configure the device based on the configuration provided */
 611 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 612 {
 613         struct bnxt *bp = eth_dev->data->dev_private;
 614         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 615         int rc;
 616
 617         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 618         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 619         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 620         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 621
 622         rc = is_bnxt_in_error(bp);
 623         if (rc)
 624                 return rc;
 625
 626         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 627                 rc = bnxt_hwrm_check_vf_rings(bp);
 628                 if (rc) {
 629                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 630                         return -ENOSPC;
 631                 }
 632
 633                 /* If a resource has already been allocated - in this case
 634                  * it is the async completion ring, free it. Reallocate it after
 635                  * resource reservation. This will ensure the resource counts
 636                  * are calculated correctly.
 637                  */
 638
 639                 pthread_mutex_lock(&bp->def_cp_lock);
 640
 641                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 642                         bnxt_disable_int(bp);
 643                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 644                 }
 645
 646                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 647                 if (rc) {
 648                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 649                         pthread_mutex_unlock(&bp->def_cp_lock);
 650                         return -ENOSPC;
 651                 }
 652
 653                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 654                         rc = bnxt_alloc_async_cp_ring(bp);
 655                         if (rc) {
 656                                 pthread_mutex_unlock(&bp->def_cp_lock);
 657                                 return rc;
 658                         }
 659                         bnxt_enable_int(bp);
 660                 }
 661
 662                 pthread_mutex_unlock(&bp->def_cp_lock);
 663         } else {
 664                 /* legacy driver needs to get updated values */
 665                 rc = bnxt_hwrm_func_qcaps(bp);
 666                 if (rc) {
 667                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 668                         return rc;
 669                 }
 670         }
 671
 672         /* Inherit new configurations */
 673         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 674             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 675             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 676                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 677             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 678             bp->max_stat_ctx)
 679                 goto resource_error;
 680
 681         if (BNXT_HAS_RING_GRPS(bp) &&
 682             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 683                 goto resource_error;
 684
 685         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 686             bp->max_vnics < eth_dev->data->nb_rx_queues)
 687                 goto resource_error;
 688
 689         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 690         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 691
 692         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 693                 eth_dev->data->mtu =
 694                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 695                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 696                         BNXT_NUM_VLANS;
 697                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 698         }
 699         return 0;
 700
 701 resource_error:
 702         PMD_DRV_LOG(ERR,
 703                     "Insufficient resources to support requested config\n");
 704         PMD_DRV_LOG(ERR,
 705                     "Num Queues Requested: Tx %d, Rx %d\n",
 706                     eth_dev->data->nb_tx_queues,
 707                     eth_dev->data->nb_rx_queues);
 708         PMD_DRV_LOG(ERR,
 709                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 710                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 711                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 712         return -ENOSPC;
 713 }
 714
 715 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 716 {
 717         struct rte_eth_link *link = &eth_dev->data->dev_link;
 718
 719         if (link->link_status)
 720                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 721                         eth_dev->data->port_id,
 722                         (uint32_t)link->link_speed,
 723                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 724                         ("full-duplex") : ("half-duplex\n"));
 725         else
 726                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 727                         eth_dev->data->port_id);
 728 }
 729
 730 /*
 731  * Determine whether the current configuration requires support for scattered
 732  * receive; return 1 if scattered receive is required and 0 if not.
 733  */
 734 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 735 {
 736         uint16_t buf_size;
 737         int i;
 738
 739         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
 740                 return 1;
 741
 742         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 743                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 744
 745                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 746                                       RTE_PKTMBUF_HEADROOM);
 747                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 748                         return 1;
 749         }
 750         return 0;
 751 }
 752
 753 static eth_rx_burst_t
 754 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
 755 {
 756 #ifdef RTE_ARCH_X86
 757 #ifndef RTE_LIBRTE_IEEE1588
 758         /*
 759          * Vector mode receive can be enabled only if scatter rx is not
 760          * in use and rx offloads are limited to VLAN stripping and
 761          * CRC stripping.
 762          */
 763         if (!eth_dev->data->scattered_rx &&
 764             !(eth_dev->data->dev_conf.rxmode.offloads &
 765               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 766                 DEV_RX_OFFLOAD_KEEP_CRC |
 767                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 768                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 769                 DEV_RX_OFFLOAD_UDP_CKSUM |
 770                 DEV_RX_OFFLOAD_TCP_CKSUM |
 771                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 772                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 773                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 774                             eth_dev->data->port_id);
 775                 return bnxt_recv_pkts_vec;
 776         }
 777         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 778                     eth_dev->data->port_id);
 779         PMD_DRV_LOG(INFO,
 780                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 781                     eth_dev->data->port_id,
 782                     eth_dev->data->scattered_rx,
 783                     eth_dev->data->dev_conf.rxmode.offloads);
 784 #endif
 785 #endif
 786         return bnxt_recv_pkts;
 787 }
 788
 789 static eth_tx_burst_t
 790 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 791 {
 792 #ifdef RTE_ARCH_X86
 793 #ifndef RTE_LIBRTE_IEEE1588
 794         /*
 795          * Vector mode transmit can be enabled only if not using scatter rx
 796          * or tx offloads.
 797          */
 798         if (!eth_dev->data->scattered_rx &&
 799             !eth_dev->data->dev_conf.txmode.offloads) {
 800                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 801                             eth_dev->data->port_id);
 802                 return bnxt_xmit_pkts_vec;
 803         }
 804         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 805                     eth_dev->data->port_id);
 806         PMD_DRV_LOG(INFO,
 807                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 808                     eth_dev->data->port_id,
 809                     eth_dev->data->scattered_rx,
 810                     eth_dev->data->dev_conf.txmode.offloads);
 811 #endif
 812 #endif
 813         return bnxt_xmit_pkts;
 814 }
 815
 816 static int bnxt_handle_if_change_status(struct bnxt *bp)
 817 {
 818         int rc;
 819
 820         /* Since fw has undergone a reset and lost all contexts,
 821          * set fatal flag to not issue hwrm during cleanup
 822          */
 823         bp->flags |= BNXT_FLAG_FATAL_ERROR;
 824         bnxt_uninit_resources(bp, true);
 825
 826         /* clear fatal flag so that re-init happens */
 827         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
 828         rc = bnxt_init_resources(bp, true);
 829
 830         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
 831
 832         return rc;
 833 }
 834
 835 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 836 {
 837         struct bnxt *bp = eth_dev->data->dev_private;
 838         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 839         int vlan_mask = 0;
 840         int rc;
 841
 842         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
 843                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
 844                 return -EINVAL;
 845         }
 846
 847         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 848                 PMD_DRV_LOG(ERR,
 849                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 850                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 851         }
 852
 853         rc = bnxt_hwrm_if_change(bp, 1);
 854         if (!rc) {
 855                 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
 856                         rc = bnxt_handle_if_change_status(bp);
 857                         if (rc)
 858                                 return rc;
 859                 }
 860         }
 861         bnxt_enable_int(bp);
 862
 863         rc = bnxt_init_chip(bp);
 864         if (rc)
 865                 goto error;
 866
 867         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 868
 869         bnxt_link_update_op(eth_dev, 1);
 870
 871         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 872                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 873         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 874                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 875         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 876         if (rc)
 877                 goto error;
 878
 879         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 880         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 881
 882         bp->flags |= BNXT_FLAG_INIT_DONE;
 883         eth_dev->data->dev_started = 1;
 884         bp->dev_stopped = 0;
 885         pthread_mutex_lock(&bp->def_cp_lock);
 886         bnxt_schedule_fw_health_check(bp);
 887         pthread_mutex_unlock(&bp->def_cp_lock);
 888         return 0;
 889
 890 error:
 891         bnxt_hwrm_if_change(bp, 0);
 892         bnxt_shutdown_nic(bp);
 893         bnxt_free_tx_mbufs(bp);
 894         bnxt_free_rx_mbufs(bp);
 895         return rc;
 896 }
 897
 898 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 899 {
 900         struct bnxt *bp = eth_dev->data->dev_private;
 901         int rc = 0;
 902
 903         if (!bp->link_info.link_up)
 904                 rc = bnxt_set_hwrm_link_config(bp, true);
 905         if (!rc)
 906                 eth_dev->data->dev_link.link_status = 1;
 907
 908         bnxt_print_link_info(eth_dev);
 909         return rc;
 910 }
 911
 912 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 913 {
 914         struct bnxt *bp = eth_dev->data->dev_private;
 915
 916         eth_dev->data->dev_link.link_status = 0;
 917         bnxt_set_hwrm_link_config(bp, false);
 918         bp->link_info.link_up = 0;
 919
 920         return 0;
 921 }
 922
 923 /* Unload the driver, release resources */
 924 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 925 {
 926         struct bnxt *bp = eth_dev->data->dev_private;
 927         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 928         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 929
 930         eth_dev->data->dev_started = 0;
 931         /* Prevent crashes when queues are still in use */
 932         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
 933         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
 934
 935         bnxt_disable_int(bp);
 936
 937         /* disable uio/vfio intr/eventfd mapping */
 938         rte_intr_disable(intr_handle);
 939
 940         bnxt_cancel_fw_health_check(bp);
 941
 942         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 943         if (bp->eth_dev->data->dev_started) {
 944                 /* TBD: STOP HW queues DMA */
 945                 eth_dev->data->dev_link.link_status = 0;
 946         }
 947         bnxt_dev_set_link_down_op(eth_dev);
 948
 949         /* Wait for link to be reset and the async notification to process.
 950          * During reset recovery, there is no need to wait
 951          */
 952         if (!is_bnxt_in_error(bp))
 953                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL * 2);
 954
 955         /* Clean queue intr-vector mapping */
 956         rte_intr_efd_disable(intr_handle);
 957         if (intr_handle->intr_vec != NULL) {
 958                 rte_free(intr_handle->intr_vec);
 959                 intr_handle->intr_vec = NULL;
 960         }
 961
 962         bnxt_hwrm_port_clr_stats(bp);
 963         bnxt_free_tx_mbufs(bp);
 964         bnxt_free_rx_mbufs(bp);
 965         /* Process any remaining notifications in default completion queue */
 966         bnxt_int_handler(eth_dev);
 967         bnxt_shutdown_nic(bp);
 968         bnxt_hwrm_if_change(bp, 0);
 969         bp->dev_stopped = 1;
 970         bp->rx_cosq_cnt = 0;
 971 }
 972
 973 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 974 {
 975         struct bnxt *bp = eth_dev->data->dev_private;
 976
 977         if (bp->dev_stopped == 0)
 978                 bnxt_dev_stop_op(eth_dev);
 979
 980         if (eth_dev->data->mac_addrs != NULL) {
 981                 rte_free(eth_dev->data->mac_addrs);
 982                 eth_dev->data->mac_addrs = NULL;
 983         }
 984         if (bp->grp_info != NULL) {
 985                 rte_free(bp->grp_info);
 986                 bp->grp_info = NULL;
 987         }
 988
 989         bnxt_dev_uninit(eth_dev);
 990 }
 991
 992 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 993                                     uint32_t index)
 994 {
 995         struct bnxt *bp = eth_dev->data->dev_private;
 996         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 997         struct bnxt_vnic_info *vnic;
 998         struct bnxt_filter_info *filter, *temp_filter;
 999         uint32_t i;
1000
1001         if (is_bnxt_in_error(bp))
1002                 return;
1003
1004         /*
1005          * Loop through all VNICs from the specified filter flow pools to
1006          * remove the corresponding MAC addr filter
1007          */
1008         for (i = 0; i < bp->nr_vnics; i++) {
1009                 if (!(pool_mask & (1ULL << i)))
1010                         continue;
1011
1012                 vnic = &bp->vnic_info[i];
1013                 filter = STAILQ_FIRST(&vnic->filter);
1014                 while (filter) {
1015                         temp_filter = STAILQ_NEXT(filter, next);
1016                         if (filter->mac_index == index) {
1017                                 STAILQ_REMOVE(&vnic->filter, filter,
1018                                                 bnxt_filter_info, next);
1019                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1020                                 filter->mac_index = INVALID_MAC_INDEX;
1021                                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1022                                 bnxt_free_filter(bp, filter);
1023                         }
1024                         filter = temp_filter;
1025                 }
1026         }
1027 }
1028
1029 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1030                                struct rte_ether_addr *mac_addr, uint32_t index,
1031                                uint32_t pool)
1032 {
1033         struct bnxt_filter_info *filter;
1034         int rc = 0;
1035
1036         /* Attach requested MAC address to the new l2_filter */
1037         STAILQ_FOREACH(filter, &vnic->filter, next) {
1038                 if (filter->mac_index == index) {
1039                         PMD_DRV_LOG(ERR,
1040                                     "MAC addr already existed for pool %d\n",
1041                                     pool);
1042                         return 0;
1043                 }
1044         }
1045
1046         filter = bnxt_alloc_filter(bp);
1047         if (!filter) {
1048                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1049                 return -ENODEV;
1050         }
1051
1052         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1053          * if the MAC that's been programmed now is a different one, then,
1054          * copy that addr to filter->l2_addr
1055          */
1056         if (mac_addr)
1057                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1058         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1059
1060         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1061         if (!rc) {
1062                 filter->mac_index = index;
1063                 if (filter->mac_index == 0)
1064                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1065                 else
1066                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1067         } else {
1068                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1069                 bnxt_free_filter(bp, filter);
1070         }
1071
1072         return rc;
1073 }
1074
1075 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1076                                 struct rte_ether_addr *mac_addr,
1077                                 uint32_t index, uint32_t pool)
1078 {
1079         struct bnxt *bp = eth_dev->data->dev_private;
1080         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1081         int rc = 0;
1082
1083         rc = is_bnxt_in_error(bp);
1084         if (rc)
1085                 return rc;
1086
1087         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1088                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1089                 return -ENOTSUP;
1090         }
1091
1092         if (!vnic) {
1093                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1094                 return -EINVAL;
1095         }
1096
1097         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1098
1099         return rc;
1100 }
1101
1102 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1103 {
1104         int rc = 0;
1105         struct bnxt *bp = eth_dev->data->dev_private;
1106         struct rte_eth_link new;
1107         unsigned int cnt = BNXT_LINK_WAIT_CNT;
1108
1109         rc = is_bnxt_in_error(bp);
1110         if (rc)
1111                 return rc;
1112
1113         memset(&new, 0, sizeof(new));
1114         do {
1115                 /* Retrieve link info from hardware */
1116                 rc = bnxt_get_hwrm_link_config(bp, &new);
1117                 if (rc) {
1118                         new.link_speed = ETH_LINK_SPEED_100M;
1119                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1120                         PMD_DRV_LOG(ERR,
1121                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1122                         goto out;
1123                 }
1124
1125                 if (!wait_to_complete || new.link_status)
1126                         break;
1127
1128                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1129         } while (cnt--);
1130
1131 out:
1132         /* Timed out or success */
1133         if (new.link_status != eth_dev->data->dev_link.link_status ||
1134         new.link_speed != eth_dev->data->dev_link.link_speed) {
1135                 rte_eth_linkstatus_set(eth_dev, &new);
1136
1137                 _rte_eth_dev_callback_process(eth_dev,
1138                                               RTE_ETH_EVENT_INTR_LSC,
1139                                               NULL);
1140
1141                 bnxt_print_link_info(eth_dev);
1142         }
1143
1144         return rc;
1145 }
1146
1147 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1148 {
1149         struct bnxt *bp = eth_dev->data->dev_private;
1150         struct bnxt_vnic_info *vnic;
1151         uint32_t old_flags;
1152         int rc;
1153
1154         rc = is_bnxt_in_error(bp);
1155         if (rc)
1156                 return rc;
1157
1158         if (bp->vnic_info == NULL)
1159                 return 0;
1160
1161         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1162
1163         old_flags = vnic->flags;
1164         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1165         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1166         if (rc != 0)
1167                 vnic->flags = old_flags;
1168
1169         return rc;
1170 }
1171
1172 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1173 {
1174         struct bnxt *bp = eth_dev->data->dev_private;
1175         struct bnxt_vnic_info *vnic;
1176         uint32_t old_flags;
1177         int rc;
1178
1179         rc = is_bnxt_in_error(bp);
1180         if (rc)
1181                 return rc;
1182
1183         if (bp->vnic_info == NULL)
1184                 return 0;
1185
1186         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1187
1188         old_flags = vnic->flags;
1189         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1190         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1191         if (rc != 0)
1192                 vnic->flags = old_flags;
1193
1194         return rc;
1195 }
1196
1197 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1198 {
1199         struct bnxt *bp = eth_dev->data->dev_private;
1200         struct bnxt_vnic_info *vnic;
1201         uint32_t old_flags;
1202         int rc;
1203
1204         rc = is_bnxt_in_error(bp);
1205         if (rc)
1206                 return rc;
1207
1208         if (bp->vnic_info == NULL)
1209                 return 0;
1210
1211         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1212
1213         old_flags = vnic->flags;
1214         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1215         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1216         if (rc != 0)
1217                 vnic->flags = old_flags;
1218
1219         return rc;
1220 }
1221
1222 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1223 {
1224         struct bnxt *bp = eth_dev->data->dev_private;
1225         struct bnxt_vnic_info *vnic;
1226         uint32_t old_flags;
1227         int rc;
1228
1229         rc = is_bnxt_in_error(bp);
1230         if (rc)
1231                 return rc;
1232
1233         if (bp->vnic_info == NULL)
1234                 return 0;
1235
1236         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1237
1238         old_flags = vnic->flags;
1239         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1240         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1241         if (rc != 0)
1242                 vnic->flags = old_flags;
1243
1244         return rc;
1245 }
1246
1247 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1248 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1249 {
1250         if (qid >= bp->rx_nr_rings)
1251                 return NULL;
1252
1253         return bp->eth_dev->data->rx_queues[qid];
1254 }
1255
1256 /* Return rxq corresponding to a given rss table ring/group ID. */
1257 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1258 {
1259         struct bnxt_rx_queue *rxq;
1260         unsigned int i;
1261
1262         if (!BNXT_HAS_RING_GRPS(bp)) {
1263                 for (i = 0; i < bp->rx_nr_rings; i++) {
1264                         rxq = bp->eth_dev->data->rx_queues[i];
1265                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1266                                 return rxq->index;
1267                 }
1268         } else {
1269                 for (i = 0; i < bp->rx_nr_rings; i++) {
1270                         if (bp->grp_info[i].fw_grp_id == fwr)
1271                                 return i;
1272                 }
1273         }
1274
1275         return INVALID_HW_RING_ID;
1276 }
1277
1278 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1279                             struct rte_eth_rss_reta_entry64 *reta_conf,
1280                             uint16_t reta_size)
1281 {
1282         struct bnxt *bp = eth_dev->data->dev_private;
1283         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1284         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1285         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1286         uint16_t idx, sft;
1287         int i, rc;
1288
1289         rc = is_bnxt_in_error(bp);
1290         if (rc)
1291                 return rc;
1292
1293         if (!vnic->rss_table)
1294                 return -EINVAL;
1295
1296         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1297                 return -EINVAL;
1298
1299         if (reta_size != tbl_size) {
1300                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1301                         "(%d) must equal the size supported by the hardware "
1302                         "(%d)\n", reta_size, tbl_size);
1303                 return -EINVAL;
1304         }
1305
1306         for (i = 0; i < reta_size; i++) {
1307                 struct bnxt_rx_queue *rxq;
1308
1309                 idx = i / RTE_RETA_GROUP_SIZE;
1310                 sft = i % RTE_RETA_GROUP_SIZE;
1311
1312                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1313                         continue;
1314
1315                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1316                 if (!rxq) {
1317                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1318                         return -EINVAL;
1319                 }
1320
1321                 if (BNXT_CHIP_THOR(bp)) {
1322                         vnic->rss_table[i * 2] =
1323                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1324                         vnic->rss_table[i * 2 + 1] =
1325                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1326                 } else {
1327                         vnic->rss_table[i] =
1328                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1329                 }
1330         }
1331
1332         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1333         return 0;
1334 }
1335
1336 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1337                               struct rte_eth_rss_reta_entry64 *reta_conf,
1338                               uint16_t reta_size)
1339 {
1340         struct bnxt *bp = eth_dev->data->dev_private;
1341         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1342         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1343         uint16_t idx, sft, i;
1344         int rc;
1345
1346         rc = is_bnxt_in_error(bp);
1347         if (rc)
1348                 return rc;
1349
1350         /* Retrieve from the default VNIC */
1351         if (!vnic)
1352                 return -EINVAL;
1353         if (!vnic->rss_table)
1354                 return -EINVAL;
1355
1356         if (reta_size != tbl_size) {
1357                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1358                         "(%d) must equal the size supported by the hardware "
1359                         "(%d)\n", reta_size, tbl_size);
1360                 return -EINVAL;
1361         }
1362
1363         for (idx = 0, i = 0; i < reta_size; i++) {
1364                 idx = i / RTE_RETA_GROUP_SIZE;
1365                 sft = i % RTE_RETA_GROUP_SIZE;
1366
1367                 if (reta_conf[idx].mask & (1ULL << sft)) {
1368                         uint16_t qid;
1369
1370                         if (BNXT_CHIP_THOR(bp))
1371                                 qid = bnxt_rss_to_qid(bp,
1372                                                       vnic->rss_table[i * 2]);
1373                         else
1374                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1375
1376                         if (qid == INVALID_HW_RING_ID) {
1377                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1378                                 return -EINVAL;
1379                         }
1380                         reta_conf[idx].reta[sft] = qid;
1381                 }
1382         }
1383
1384         return 0;
1385 }
1386
1387 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1388                                    struct rte_eth_rss_conf *rss_conf)
1389 {
1390         struct bnxt *bp = eth_dev->data->dev_private;
1391         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1392         struct bnxt_vnic_info *vnic;
1393         int rc;
1394
1395         rc = is_bnxt_in_error(bp);
1396         if (rc)
1397                 return rc;
1398
1399         /*
1400          * If RSS enablement were different than dev_configure,
1401          * then return -EINVAL
1402          */
1403         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1404                 if (!rss_conf->rss_hf)
1405                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1406         } else {
1407                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1408                         return -EINVAL;
1409         }
1410
1411         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1412         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1413
1414         /* Update the default RSS VNIC(s) */
1415         vnic = &bp->vnic_info[0];
1416         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1417
1418         /*
1419          * If hashkey is not specified, use the previously configured
1420          * hashkey
1421          */
1422         if (!rss_conf->rss_key)
1423                 goto rss_config;
1424
1425         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1426                 PMD_DRV_LOG(ERR,
1427                             "Invalid hashkey length, should be 16 bytes\n");
1428                 return -EINVAL;
1429         }
1430         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1431
1432 rss_config:
1433         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1434         return 0;
1435 }
1436
1437 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1438                                      struct rte_eth_rss_conf *rss_conf)
1439 {
1440         struct bnxt *bp = eth_dev->data->dev_private;
1441         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1442         int len, rc;
1443         uint32_t hash_types;
1444
1445         rc = is_bnxt_in_error(bp);
1446         if (rc)
1447                 return rc;
1448
1449         /* RSS configuration is the same for all VNICs */
1450         if (vnic && vnic->rss_hash_key) {
1451                 if (rss_conf->rss_key) {
1452                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1453                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1454                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1455                 }
1456
1457                 hash_types = vnic->hash_type;
1458                 rss_conf->rss_hf = 0;
1459                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1460                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1461                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1462                 }
1463                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1464                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1465                         hash_types &=
1466                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1467                 }
1468                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1469                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1470                         hash_types &=
1471                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1472                 }
1473                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1474                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1475                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1476                 }
1477                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1478                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1479                         hash_types &=
1480                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1481                 }
1482                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1483                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1484                         hash_types &=
1485                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1486                 }
1487                 if (hash_types) {
1488                         PMD_DRV_LOG(ERR,
1489                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1490                                 vnic->hash_type);
1491                         return -ENOTSUP;
1492                 }
1493         } else {
1494                 rss_conf->rss_hf = 0;
1495         }
1496         return 0;
1497 }
1498
1499 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1500                                struct rte_eth_fc_conf *fc_conf)
1501 {
1502         struct bnxt *bp = dev->data->dev_private;
1503         struct rte_eth_link link_info;
1504         int rc;
1505
1506         rc = is_bnxt_in_error(bp);
1507         if (rc)
1508                 return rc;
1509
1510         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1511         if (rc)
1512                 return rc;
1513
1514         memset(fc_conf, 0, sizeof(*fc_conf));
1515         if (bp->link_info.auto_pause)
1516                 fc_conf->autoneg = 1;
1517         switch (bp->link_info.pause) {
1518         case 0:
1519                 fc_conf->mode = RTE_FC_NONE;
1520                 break;
1521         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1522                 fc_conf->mode = RTE_FC_TX_PAUSE;
1523                 break;
1524         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1525                 fc_conf->mode = RTE_FC_RX_PAUSE;
1526                 break;
1527         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1528                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1529                 fc_conf->mode = RTE_FC_FULL;
1530                 break;
1531         }
1532         return 0;
1533 }
1534
1535 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1536                                struct rte_eth_fc_conf *fc_conf)
1537 {
1538         struct bnxt *bp = dev->data->dev_private;
1539         int rc;
1540
1541         rc = is_bnxt_in_error(bp);
1542         if (rc)
1543                 return rc;
1544
1545         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1546                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1547                 return -ENOTSUP;
1548         }
1549
1550         switch (fc_conf->mode) {
1551         case RTE_FC_NONE:
1552                 bp->link_info.auto_pause = 0;
1553                 bp->link_info.force_pause = 0;
1554                 break;
1555         case RTE_FC_RX_PAUSE:
1556                 if (fc_conf->autoneg) {
1557                         bp->link_info.auto_pause =
1558                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1559                         bp->link_info.force_pause = 0;
1560                 } else {
1561                         bp->link_info.auto_pause = 0;
1562                         bp->link_info.force_pause =
1563                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1564                 }
1565                 break;
1566         case RTE_FC_TX_PAUSE:
1567                 if (fc_conf->autoneg) {
1568                         bp->link_info.auto_pause =
1569                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1570                         bp->link_info.force_pause = 0;
1571                 } else {
1572                         bp->link_info.auto_pause = 0;
1573                         bp->link_info.force_pause =
1574                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1575                 }
1576                 break;
1577         case RTE_FC_FULL:
1578                 if (fc_conf->autoneg) {
1579                         bp->link_info.auto_pause =
1580                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1581                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1582                         bp->link_info.force_pause = 0;
1583                 } else {
1584                         bp->link_info.auto_pause = 0;
1585                         bp->link_info.force_pause =
1586                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1587                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1588                 }
1589                 break;
1590         }
1591         return bnxt_set_hwrm_link_config(bp, true);
1592 }
1593
1594 /* Add UDP tunneling port */
1595 static int
1596 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1597                          struct rte_eth_udp_tunnel *udp_tunnel)
1598 {
1599         struct bnxt *bp = eth_dev->data->dev_private;
1600         uint16_t tunnel_type = 0;
1601         int rc = 0;
1602
1603         rc = is_bnxt_in_error(bp);
1604         if (rc)
1605                 return rc;
1606
1607         switch (udp_tunnel->prot_type) {
1608         case RTE_TUNNEL_TYPE_VXLAN:
1609                 if (bp->vxlan_port_cnt) {
1610                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1611                                 udp_tunnel->udp_port);
1612                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1613                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1614                                 return -ENOSPC;
1615                         }
1616                         bp->vxlan_port_cnt++;
1617                         return 0;
1618                 }
1619                 tunnel_type =
1620                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1621                 bp->vxlan_port_cnt++;
1622                 break;
1623         case RTE_TUNNEL_TYPE_GENEVE:
1624                 if (bp->geneve_port_cnt) {
1625                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1626                                 udp_tunnel->udp_port);
1627                         if (bp->geneve_port != udp_tunnel->udp_port) {
1628                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1629                                 return -ENOSPC;
1630                         }
1631                         bp->geneve_port_cnt++;
1632                         return 0;
1633                 }
1634                 tunnel_type =
1635                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1636                 bp->geneve_port_cnt++;
1637                 break;
1638         default:
1639                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1640                 return -ENOTSUP;
1641         }
1642         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1643                                              tunnel_type);
1644         return rc;
1645 }
1646
1647 static int
1648 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1649                          struct rte_eth_udp_tunnel *udp_tunnel)
1650 {
1651         struct bnxt *bp = eth_dev->data->dev_private;
1652         uint16_t tunnel_type = 0;
1653         uint16_t port = 0;
1654         int rc = 0;
1655
1656         rc = is_bnxt_in_error(bp);
1657         if (rc)
1658                 return rc;
1659
1660         switch (udp_tunnel->prot_type) {
1661         case RTE_TUNNEL_TYPE_VXLAN:
1662                 if (!bp->vxlan_port_cnt) {
1663                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1664                         return -EINVAL;
1665                 }
1666                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1667                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1668                                 udp_tunnel->udp_port, bp->vxlan_port);
1669                         return -EINVAL;
1670                 }
1671                 if (--bp->vxlan_port_cnt)
1672                         return 0;
1673
1674                 tunnel_type =
1675                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1676                 port = bp->vxlan_fw_dst_port_id;
1677                 break;
1678         case RTE_TUNNEL_TYPE_GENEVE:
1679                 if (!bp->geneve_port_cnt) {
1680                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1681                         return -EINVAL;
1682                 }
1683                 if (bp->geneve_port != udp_tunnel->udp_port) {
1684                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1685                                 udp_tunnel->udp_port, bp->geneve_port);
1686                         return -EINVAL;
1687                 }
1688                 if (--bp->geneve_port_cnt)
1689                         return 0;
1690
1691                 tunnel_type =
1692                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1693                 port = bp->geneve_fw_dst_port_id;
1694                 break;
1695         default:
1696                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1697                 return -ENOTSUP;
1698         }
1699
1700         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1701         if (!rc) {
1702                 if (tunnel_type ==
1703                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1704                         bp->vxlan_port = 0;
1705                 if (tunnel_type ==
1706                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1707                         bp->geneve_port = 0;
1708         }
1709         return rc;
1710 }
1711
1712 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1713 {
1714         struct bnxt_filter_info *filter;
1715         struct bnxt_vnic_info *vnic;
1716         int rc = 0;
1717         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1718
1719         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1720         filter = STAILQ_FIRST(&vnic->filter);
1721         while (filter) {
1722                 /* Search for this matching MAC+VLAN filter */
1723                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
1724                         /* Delete the filter */
1725                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1726                         if (rc)
1727                                 return rc;
1728                         STAILQ_REMOVE(&vnic->filter, filter,
1729                                       bnxt_filter_info, next);
1730                         bnxt_free_filter(bp, filter);
1731                         PMD_DRV_LOG(INFO,
1732                                     "Deleted vlan filter for %d\n",
1733                                     vlan_id);
1734                         return 0;
1735                 }
1736                 filter = STAILQ_NEXT(filter, next);
1737         }
1738         return -ENOENT;
1739 }
1740
1741 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1742 {
1743         struct bnxt_filter_info *filter;
1744         struct bnxt_vnic_info *vnic;
1745         int rc = 0;
1746         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1747                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1748         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1749
1750         /* Implementation notes on the use of VNIC in this command:
1751          *
1752          * By default, these filters belong to default vnic for the function.
1753          * Once these filters are set up, only destination VNIC can be modified.
1754          * If the destination VNIC is not specified in this command,
1755          * then the HWRM shall only create an l2 context id.
1756          */
1757
1758         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1759         filter = STAILQ_FIRST(&vnic->filter);
1760         /* Check if the VLAN has already been added */
1761         while (filter) {
1762                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
1763                         return -EEXIST;
1764
1765                 filter = STAILQ_NEXT(filter, next);
1766         }
1767
1768         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1769          * command to create MAC+VLAN filter with the right flags, enables set.
1770          */
1771         filter = bnxt_alloc_filter(bp);
1772         if (!filter) {
1773                 PMD_DRV_LOG(ERR,
1774                             "MAC/VLAN filter alloc failed\n");
1775                 return -ENOMEM;
1776         }
1777         /* MAC + VLAN ID filter */
1778         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1779          * untagged packets are received
1780          *
1781          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
1782          * packets and only the programmed vlan's packets are received
1783          */
1784         filter->l2_ivlan = vlan_id;
1785         filter->l2_ivlan_mask = 0x0FFF;
1786         filter->enables |= en;
1787         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1788
1789         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1790         if (rc) {
1791                 /* Free the newly allocated filter as we were
1792                  * not able to create the filter in hardware.
1793                  */
1794                 filter->fw_l2_filter_id = UINT64_MAX;
1795                 bnxt_free_filter(bp, filter);
1796                 return rc;
1797         }
1798
1799         filter->mac_index = 0;
1800         /* Add this new filter to the list */
1801         if (vlan_id == 0)
1802                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1803         else
1804                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1805
1806         PMD_DRV_LOG(INFO,
1807                     "Added Vlan filter for %d\n", vlan_id);
1808         return rc;
1809 }
1810
1811 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1812                 uint16_t vlan_id, int on)
1813 {
1814         struct bnxt *bp = eth_dev->data->dev_private;
1815         int rc;
1816
1817         rc = is_bnxt_in_error(bp);
1818         if (rc)
1819                 return rc;
1820
1821         /* These operations apply to ALL existing MAC/VLAN filters */
1822         if (on)
1823                 return bnxt_add_vlan_filter(bp, vlan_id);
1824         else
1825                 return bnxt_del_vlan_filter(bp, vlan_id);
1826 }
1827
1828 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
1829                                     struct bnxt_vnic_info *vnic)
1830 {
1831         struct bnxt_filter_info *filter;
1832         int rc;
1833
1834         filter = STAILQ_FIRST(&vnic->filter);
1835         while (filter) {
1836                 if (filter->mac_index == 0 &&
1837                     !memcmp(filter->l2_addr, bp->mac_addr,
1838                             RTE_ETHER_ADDR_LEN)) {
1839                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1840                         if (!rc) {
1841                                 STAILQ_REMOVE(&vnic->filter, filter,
1842                                               bnxt_filter_info, next);
1843                                 bnxt_free_filter(bp, filter);
1844                                 filter->fw_l2_filter_id = UINT64_MAX;
1845                         }
1846                         return rc;
1847                 }
1848                 filter = STAILQ_NEXT(filter, next);
1849         }
1850         return 0;
1851 }
1852
1853 static int
1854 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1855 {
1856         struct bnxt *bp = dev->data->dev_private;
1857         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1858         struct bnxt_vnic_info *vnic;
1859         unsigned int i;
1860         int rc;
1861
1862         rc = is_bnxt_in_error(bp);
1863         if (rc)
1864                 return rc;
1865
1866         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1867         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1868                 /* Remove any VLAN filters programmed */
1869                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1870                         bnxt_del_vlan_filter(bp, i);
1871
1872                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1873                 if (rc)
1874                         return rc;
1875         } else {
1876                 /* Default filter will allow packets that match the
1877                  * dest mac. So, it has to be deleted, otherwise, we
1878                  * will endup receiving vlan packets for which the
1879                  * filter is not programmed, when hw-vlan-filter
1880                  * configuration is ON
1881                  */
1882                 bnxt_del_dflt_mac_filter(bp, vnic);
1883                 /* This filter will allow only untagged packets */
1884                 bnxt_add_vlan_filter(bp, 0);
1885         }
1886         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1887                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1888
1889         if (mask & ETH_VLAN_STRIP_MASK) {
1890                 /* Enable or disable VLAN stripping */
1891                 for (i = 0; i < bp->nr_vnics; i++) {
1892                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1893                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1894                                 vnic->vlan_strip = true;
1895                         else
1896                                 vnic->vlan_strip = false;
1897                         bnxt_hwrm_vnic_cfg(bp, vnic);
1898                 }
1899                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1900                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1901         }
1902
1903         if (mask & ETH_VLAN_EXTEND_MASK) {
1904                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1905                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
1906                 else
1907                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
1908         }
1909
1910         return 0;
1911 }
1912
1913 static int
1914 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
1915                       uint16_t tpid)
1916 {
1917         struct bnxt *bp = dev->data->dev_private;
1918         int qinq = dev->data->dev_conf.rxmode.offloads &
1919                    DEV_RX_OFFLOAD_VLAN_EXTEND;
1920
1921         if (vlan_type != ETH_VLAN_TYPE_INNER &&
1922             vlan_type != ETH_VLAN_TYPE_OUTER) {
1923                 PMD_DRV_LOG(ERR,
1924                             "Unsupported vlan type.");
1925                 return -EINVAL;
1926         }
1927         if (!qinq) {
1928                 PMD_DRV_LOG(ERR,
1929                             "QinQ not enabled. Needs to be ON as we can "
1930                             "accelerate only outer vlan\n");
1931                 return -EINVAL;
1932         }
1933
1934         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
1935                 switch (tpid) {
1936                 case RTE_ETHER_TYPE_QINQ:
1937                         bp->outer_tpid_bd =
1938                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
1939                                 break;
1940                 case RTE_ETHER_TYPE_VLAN:
1941                         bp->outer_tpid_bd =
1942                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
1943                                 break;
1944                 case 0x9100:
1945                         bp->outer_tpid_bd =
1946                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
1947                                 break;
1948                 case 0x9200:
1949                         bp->outer_tpid_bd =
1950                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
1951                                 break;
1952                 case 0x9300:
1953                         bp->outer_tpid_bd =
1954                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
1955                                 break;
1956                 default:
1957                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
1958                         return -EINVAL;
1959                 }
1960                 bp->outer_tpid_bd |= tpid;
1961                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
1962         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
1963                 PMD_DRV_LOG(ERR,
1964                             "Can accelerate only outer vlan in QinQ\n");
1965                 return -EINVAL;
1966         }
1967
1968         return 0;
1969 }
1970
1971 static int
1972 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1973                              struct rte_ether_addr *addr)
1974 {
1975         struct bnxt *bp = dev->data->dev_private;
1976         /* Default Filter is tied to VNIC 0 */
1977         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1978         struct bnxt_filter_info *filter;
1979         int rc;
1980
1981         rc = is_bnxt_in_error(bp);
1982         if (rc)
1983                 return rc;
1984
1985         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1986                 return -EPERM;
1987
1988         if (rte_is_zero_ether_addr(addr))
1989                 return -EINVAL;
1990
1991         STAILQ_FOREACH(filter, &vnic->filter, next) {
1992                 /* Default Filter is at Index 0 */
1993                 if (filter->mac_index != 0)
1994                         continue;
1995
1996                 memcpy(filter->l2_addr, addr, RTE_ETHER_ADDR_LEN);
1997                 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1998                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX |
1999                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2000                 filter->enables |=
2001                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
2002                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
2003
2004                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2005                 if (rc) {
2006                         memcpy(filter->l2_addr, bp->mac_addr,
2007                                RTE_ETHER_ADDR_LEN);
2008                         return rc;
2009                 }
2010
2011                 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2012                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2013                 return 0;
2014         }
2015
2016         return 0;
2017 }
2018
2019 static int
2020 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2021                           struct rte_ether_addr *mc_addr_set,
2022                           uint32_t nb_mc_addr)
2023 {
2024         struct bnxt *bp = eth_dev->data->dev_private;
2025         char *mc_addr_list = (char *)mc_addr_set;
2026         struct bnxt_vnic_info *vnic;
2027         uint32_t off = 0, i = 0;
2028         int rc;
2029
2030         rc = is_bnxt_in_error(bp);
2031         if (rc)
2032                 return rc;
2033
2034         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2035
2036         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2037                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2038                 goto allmulti;
2039         }
2040
2041         /* TODO Check for Duplicate mcast addresses */
2042         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2043         for (i = 0; i < nb_mc_addr; i++) {
2044                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2045                         RTE_ETHER_ADDR_LEN);
2046                 off += RTE_ETHER_ADDR_LEN;
2047         }
2048
2049         vnic->mc_addr_cnt = i;
2050         if (vnic->mc_addr_cnt)
2051                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2052         else
2053                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2054
2055 allmulti:
2056         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2057 }
2058
2059 static int
2060 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2061 {
2062         struct bnxt *bp = dev->data->dev_private;
2063         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2064         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2065         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2066         int ret;
2067
2068         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2069                         fw_major, fw_minor, fw_updt);
2070
2071         ret += 1; /* add the size of '\0' */
2072         if (fw_size < (uint32_t)ret)
2073                 return ret;
2074         else
2075                 return 0;
2076 }
2077
2078 static void
2079 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2080         struct rte_eth_rxq_info *qinfo)
2081 {
2082         struct bnxt_rx_queue *rxq;
2083
2084         rxq = dev->data->rx_queues[queue_id];
2085
2086         qinfo->mp = rxq->mb_pool;
2087         qinfo->scattered_rx = dev->data->scattered_rx;
2088         qinfo->nb_desc = rxq->nb_rx_desc;
2089
2090         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2091         qinfo->conf.rx_drop_en = 0;
2092         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2093 }
2094
2095 static void
2096 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2097         struct rte_eth_txq_info *qinfo)
2098 {
2099         struct bnxt_tx_queue *txq;
2100
2101         txq = dev->data->tx_queues[queue_id];
2102
2103         qinfo->nb_desc = txq->nb_tx_desc;
2104
2105         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2106         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2107         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2108
2109         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2110         qinfo->conf.tx_rs_thresh = 0;
2111         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2112 }
2113
2114 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2115 {
2116         struct bnxt *bp = eth_dev->data->dev_private;
2117         uint32_t new_pkt_size;
2118         uint32_t rc = 0;
2119         uint32_t i;
2120
2121         rc = is_bnxt_in_error(bp);
2122         if (rc)
2123                 return rc;
2124
2125         /* Exit if receive queues are not configured yet */
2126         if (!eth_dev->data->nb_rx_queues)
2127                 return rc;
2128
2129         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2130                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2131
2132 #ifdef RTE_ARCH_X86
2133         /*
2134          * If vector-mode tx/rx is active, disallow any MTU change that would
2135          * require scattered receive support.
2136          */
2137         if (eth_dev->data->dev_started &&
2138             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2139              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2140             (new_pkt_size >
2141              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2142                 PMD_DRV_LOG(ERR,
2143                             "MTU change would require scattered rx support. ");
2144                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2145                 return -EINVAL;
2146         }
2147 #endif
2148
2149         if (new_mtu > RTE_ETHER_MTU) {
2150                 bp->flags |= BNXT_FLAG_JUMBO;
2151                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2152                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2153         } else {
2154                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2155                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2156                 bp->flags &= ~BNXT_FLAG_JUMBO;
2157         }
2158
2159         /* Is there a change in mtu setting? */
2160         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2161                 return rc;
2162
2163         for (i = 0; i < bp->nr_vnics; i++) {
2164                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2165                 uint16_t size = 0;
2166
2167                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2168                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2169                 if (rc)
2170                         break;
2171
2172                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2173                 size -= RTE_PKTMBUF_HEADROOM;
2174
2175                 if (size < new_mtu) {
2176                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2177                         if (rc)
2178                                 return rc;
2179                 }
2180         }
2181
2182         if (!rc)
2183                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2184
2185         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2186
2187         return rc;
2188 }
2189
2190 static int
2191 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2192 {
2193         struct bnxt *bp = dev->data->dev_private;
2194         uint16_t vlan = bp->vlan;
2195         int rc;
2196
2197         rc = is_bnxt_in_error(bp);
2198         if (rc)
2199                 return rc;
2200
2201         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2202                 PMD_DRV_LOG(ERR,
2203                         "PVID cannot be modified for this function\n");
2204                 return -ENOTSUP;
2205         }
2206         bp->vlan = on ? pvid : 0;
2207
2208         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2209         if (rc)
2210                 bp->vlan = vlan;
2211         return rc;
2212 }
2213
2214 static int
2215 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2216 {
2217         struct bnxt *bp = dev->data->dev_private;
2218         int rc;
2219
2220         rc = is_bnxt_in_error(bp);
2221         if (rc)
2222                 return rc;
2223
2224         return bnxt_hwrm_port_led_cfg(bp, true);
2225 }
2226
2227 static int
2228 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2229 {
2230         struct bnxt *bp = dev->data->dev_private;
2231         int rc;
2232
2233         rc = is_bnxt_in_error(bp);
2234         if (rc)
2235                 return rc;
2236
2237         return bnxt_hwrm_port_led_cfg(bp, false);
2238 }
2239
2240 static uint32_t
2241 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2242 {
2243         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2244         uint32_t desc = 0, raw_cons = 0, cons;
2245         struct bnxt_cp_ring_info *cpr;
2246         struct bnxt_rx_queue *rxq;
2247         struct rx_pkt_cmpl *rxcmp;
2248         int rc;
2249
2250         rc = is_bnxt_in_error(bp);
2251         if (rc)
2252                 return rc;
2253
2254         rxq = dev->data->rx_queues[rx_queue_id];
2255         cpr = rxq->cp_ring;
2256         raw_cons = cpr->cp_raw_cons;
2257
2258         while (1) {
2259                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2260                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2261                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2262
2263                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2264                         break;
2265                 } else {
2266                         raw_cons++;
2267                         desc++;
2268                 }
2269         }
2270
2271         return desc;
2272 }
2273
2274 static int
2275 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2276 {
2277         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2278         struct bnxt_rx_ring_info *rxr;
2279         struct bnxt_cp_ring_info *cpr;
2280         struct bnxt_sw_rx_bd *rx_buf;
2281         struct rx_pkt_cmpl *rxcmp;
2282         uint32_t cons, cp_cons;
2283         int rc;
2284
2285         if (!rxq)
2286                 return -EINVAL;
2287
2288         rc = is_bnxt_in_error(rxq->bp);
2289         if (rc)
2290                 return rc;
2291
2292         cpr = rxq->cp_ring;
2293         rxr = rxq->rx_ring;
2294
2295         if (offset >= rxq->nb_rx_desc)
2296                 return -EINVAL;
2297
2298         cons = RING_CMP(cpr->cp_ring_struct, offset);
2299         cp_cons = cpr->cp_raw_cons;
2300         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2301
2302         if (cons > cp_cons) {
2303                 if (CMPL_VALID(rxcmp, cpr->valid))
2304                         return RTE_ETH_RX_DESC_DONE;
2305         } else {
2306                 if (CMPL_VALID(rxcmp, !cpr->valid))
2307                         return RTE_ETH_RX_DESC_DONE;
2308         }
2309         rx_buf = &rxr->rx_buf_ring[cons];
2310         if (rx_buf->mbuf == NULL)
2311                 return RTE_ETH_RX_DESC_UNAVAIL;
2312
2313
2314         return RTE_ETH_RX_DESC_AVAIL;
2315 }
2316
2317 static int
2318 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2319 {
2320         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2321         struct bnxt_tx_ring_info *txr;
2322         struct bnxt_cp_ring_info *cpr;
2323         struct bnxt_sw_tx_bd *tx_buf;
2324         struct tx_pkt_cmpl *txcmp;
2325         uint32_t cons, cp_cons;
2326         int rc;
2327
2328         if (!txq)
2329                 return -EINVAL;
2330
2331         rc = is_bnxt_in_error(txq->bp);
2332         if (rc)
2333                 return rc;
2334
2335         cpr = txq->cp_ring;
2336         txr = txq->tx_ring;
2337
2338         if (offset >= txq->nb_tx_desc)
2339                 return -EINVAL;
2340
2341         cons = RING_CMP(cpr->cp_ring_struct, offset);
2342         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2343         cp_cons = cpr->cp_raw_cons;
2344
2345         if (cons > cp_cons) {
2346                 if (CMPL_VALID(txcmp, cpr->valid))
2347                         return RTE_ETH_TX_DESC_UNAVAIL;
2348         } else {
2349                 if (CMPL_VALID(txcmp, !cpr->valid))
2350                         return RTE_ETH_TX_DESC_UNAVAIL;
2351         }
2352         tx_buf = &txr->tx_buf_ring[cons];
2353         if (tx_buf->mbuf == NULL)
2354                 return RTE_ETH_TX_DESC_DONE;
2355
2356         return RTE_ETH_TX_DESC_FULL;
2357 }
2358
2359 static struct bnxt_filter_info *
2360 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2361                                 struct rte_eth_ethertype_filter *efilter,
2362                                 struct bnxt_vnic_info *vnic0,
2363                                 struct bnxt_vnic_info *vnic,
2364                                 int *ret)
2365 {
2366         struct bnxt_filter_info *mfilter = NULL;
2367         int match = 0;
2368         *ret = 0;
2369
2370         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2371                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2372                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2373                         " ethertype filter.", efilter->ether_type);
2374                 *ret = -EINVAL;
2375                 goto exit;
2376         }
2377         if (efilter->queue >= bp->rx_nr_rings) {
2378                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2379                 *ret = -EINVAL;
2380                 goto exit;
2381         }
2382
2383         vnic0 = &bp->vnic_info[0];
2384         vnic = &bp->vnic_info[efilter->queue];
2385         if (vnic == NULL) {
2386                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2387                 *ret = -EINVAL;
2388                 goto exit;
2389         }
2390
2391         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2392                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2393                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2394                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2395                              mfilter->flags ==
2396                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2397                              mfilter->ethertype == efilter->ether_type)) {
2398                                 match = 1;
2399                                 break;
2400                         }
2401                 }
2402         } else {
2403                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2404                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2405                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2406                              mfilter->ethertype == efilter->ether_type &&
2407                              mfilter->flags ==
2408                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2409                                 match = 1;
2410                                 break;
2411                         }
2412         }
2413
2414         if (match)
2415                 *ret = -EEXIST;
2416
2417 exit:
2418         return mfilter;
2419 }
2420
2421 static int
2422 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2423                         enum rte_filter_op filter_op,
2424                         void *arg)
2425 {
2426         struct bnxt *bp = dev->data->dev_private;
2427         struct rte_eth_ethertype_filter *efilter =
2428                         (struct rte_eth_ethertype_filter *)arg;
2429         struct bnxt_filter_info *bfilter, *filter1;
2430         struct bnxt_vnic_info *vnic, *vnic0;
2431         int ret;
2432
2433         if (filter_op == RTE_ETH_FILTER_NOP)
2434                 return 0;
2435
2436         if (arg == NULL) {
2437                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2438                             filter_op);
2439                 return -EINVAL;
2440         }
2441
2442         vnic0 = &bp->vnic_info[0];
2443         vnic = &bp->vnic_info[efilter->queue];
2444
2445         switch (filter_op) {
2446         case RTE_ETH_FILTER_ADD:
2447                 bnxt_match_and_validate_ether_filter(bp, efilter,
2448                                                         vnic0, vnic, &ret);
2449                 if (ret < 0)
2450                         return ret;
2451
2452                 bfilter = bnxt_get_unused_filter(bp);
2453                 if (bfilter == NULL) {
2454                         PMD_DRV_LOG(ERR,
2455                                 "Not enough resources for a new filter.\n");
2456                         return -ENOMEM;
2457                 }
2458                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2459                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2460                        RTE_ETHER_ADDR_LEN);
2461                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2462                        RTE_ETHER_ADDR_LEN);
2463                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2464                 bfilter->ethertype = efilter->ether_type;
2465                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2466
2467                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2468                 if (filter1 == NULL) {
2469                         ret = -EINVAL;
2470                         goto cleanup;
2471                 }
2472                 bfilter->enables |=
2473                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2474                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2475
2476                 bfilter->dst_id = vnic->fw_vnic_id;
2477
2478                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2479                         bfilter->flags =
2480                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2481                 }
2482
2483                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2484                 if (ret)
2485                         goto cleanup;
2486                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2487                 break;
2488         case RTE_ETH_FILTER_DELETE:
2489                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2490                                                         vnic0, vnic, &ret);
2491                 if (ret == -EEXIST) {
2492                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2493
2494                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2495                                       next);
2496                         bnxt_free_filter(bp, filter1);
2497                 } else if (ret == 0) {
2498                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2499                 }
2500                 break;
2501         default:
2502                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2503                 ret = -EINVAL;
2504                 goto error;
2505         }
2506         return ret;
2507 cleanup:
2508         bnxt_free_filter(bp, bfilter);
2509 error:
2510         return ret;
2511 }
2512
2513 static inline int
2514 parse_ntuple_filter(struct bnxt *bp,
2515                     struct rte_eth_ntuple_filter *nfilter,
2516                     struct bnxt_filter_info *bfilter)
2517 {
2518         uint32_t en = 0;
2519
2520         if (nfilter->queue >= bp->rx_nr_rings) {
2521                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2522                 return -EINVAL;
2523         }
2524
2525         switch (nfilter->dst_port_mask) {
2526         case UINT16_MAX:
2527                 bfilter->dst_port_mask = -1;
2528                 bfilter->dst_port = nfilter->dst_port;
2529                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2530                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2531                 break;
2532         default:
2533                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2534                 return -EINVAL;
2535         }
2536
2537         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2538         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2539
2540         switch (nfilter->proto_mask) {
2541         case UINT8_MAX:
2542                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2543                         bfilter->ip_protocol = 17;
2544                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2545                         bfilter->ip_protocol = 6;
2546                 else
2547                         return -EINVAL;
2548                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2549                 break;
2550         default:
2551                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2552                 return -EINVAL;
2553         }
2554
2555         switch (nfilter->dst_ip_mask) {
2556         case UINT32_MAX:
2557                 bfilter->dst_ipaddr_mask[0] = -1;
2558                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2559                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2560                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2561                 break;
2562         default:
2563                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2564                 return -EINVAL;
2565         }
2566
2567         switch (nfilter->src_ip_mask) {
2568         case UINT32_MAX:
2569                 bfilter->src_ipaddr_mask[0] = -1;
2570                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2571                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2572                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2573                 break;
2574         default:
2575                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2576                 return -EINVAL;
2577         }
2578
2579         switch (nfilter->src_port_mask) {
2580         case UINT16_MAX:
2581                 bfilter->src_port_mask = -1;
2582                 bfilter->src_port = nfilter->src_port;
2583                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2584                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2585                 break;
2586         default:
2587                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2588                 return -EINVAL;
2589         }
2590
2591         bfilter->enables = en;
2592         return 0;
2593 }
2594
2595 static struct bnxt_filter_info*
2596 bnxt_match_ntuple_filter(struct bnxt *bp,
2597                          struct bnxt_filter_info *bfilter,
2598                          struct bnxt_vnic_info **mvnic)
2599 {
2600         struct bnxt_filter_info *mfilter = NULL;
2601         int i;
2602
2603         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2604                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2605                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2606                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2607                             bfilter->src_ipaddr_mask[0] ==
2608                             mfilter->src_ipaddr_mask[0] &&
2609                             bfilter->src_port == mfilter->src_port &&
2610                             bfilter->src_port_mask == mfilter->src_port_mask &&
2611                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2612                             bfilter->dst_ipaddr_mask[0] ==
2613                             mfilter->dst_ipaddr_mask[0] &&
2614                             bfilter->dst_port == mfilter->dst_port &&
2615                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2616                             bfilter->flags == mfilter->flags &&
2617                             bfilter->enables == mfilter->enables) {
2618                                 if (mvnic)
2619                                         *mvnic = vnic;
2620                                 return mfilter;
2621                         }
2622                 }
2623         }
2624         return NULL;
2625 }
2626
2627 static int
2628 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2629                        struct rte_eth_ntuple_filter *nfilter,
2630                        enum rte_filter_op filter_op)
2631 {
2632         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2633         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2634         int ret;
2635
2636         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2637                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2638                 return -EINVAL;
2639         }
2640
2641         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2642                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2643                 return -EINVAL;
2644         }
2645
2646         bfilter = bnxt_get_unused_filter(bp);
2647         if (bfilter == NULL) {
2648                 PMD_DRV_LOG(ERR,
2649                         "Not enough resources for a new filter.\n");
2650                 return -ENOMEM;
2651         }
2652         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2653         if (ret < 0)
2654                 goto free_filter;
2655
2656         vnic = &bp->vnic_info[nfilter->queue];
2657         vnic0 = &bp->vnic_info[0];
2658         filter1 = STAILQ_FIRST(&vnic0->filter);
2659         if (filter1 == NULL) {
2660                 ret = -EINVAL;
2661                 goto free_filter;
2662         }
2663
2664         bfilter->dst_id = vnic->fw_vnic_id;
2665         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2666         bfilter->enables |=
2667                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2668         bfilter->ethertype = 0x800;
2669         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2670
2671         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2672
2673         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2674             bfilter->dst_id == mfilter->dst_id) {
2675                 PMD_DRV_LOG(ERR, "filter exists.\n");
2676                 ret = -EEXIST;
2677                 goto free_filter;
2678         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2679                    bfilter->dst_id != mfilter->dst_id) {
2680                 mfilter->dst_id = vnic->fw_vnic_id;
2681                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2682                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2683                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2684                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2685                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2686                 goto free_filter;
2687         }
2688         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2689                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2690                 ret = -ENOENT;
2691                 goto free_filter;
2692         }
2693
2694         if (filter_op == RTE_ETH_FILTER_ADD) {
2695                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2696                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2697                 if (ret)
2698                         goto free_filter;
2699                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2700         } else {
2701                 if (mfilter == NULL) {
2702                         /* This should not happen. But for Coverity! */
2703                         ret = -ENOENT;
2704                         goto free_filter;
2705                 }
2706                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2707
2708                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2709                 bnxt_free_filter(bp, mfilter);
2710                 mfilter->fw_l2_filter_id = -1;
2711                 bnxt_free_filter(bp, bfilter);
2712                 bfilter->fw_l2_filter_id = -1;
2713         }
2714
2715         return 0;
2716 free_filter:
2717         bfilter->fw_l2_filter_id = -1;
2718         bnxt_free_filter(bp, bfilter);
2719         return ret;
2720 }
2721
2722 static int
2723 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2724                         enum rte_filter_op filter_op,
2725                         void *arg)
2726 {
2727         struct bnxt *bp = dev->data->dev_private;
2728         int ret;
2729
2730         if (filter_op == RTE_ETH_FILTER_NOP)
2731                 return 0;
2732
2733         if (arg == NULL) {
2734                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2735                             filter_op);
2736                 return -EINVAL;
2737         }
2738
2739         switch (filter_op) {
2740         case RTE_ETH_FILTER_ADD:
2741                 ret = bnxt_cfg_ntuple_filter(bp,
2742                         (struct rte_eth_ntuple_filter *)arg,
2743                         filter_op);
2744                 break;
2745         case RTE_ETH_FILTER_DELETE:
2746                 ret = bnxt_cfg_ntuple_filter(bp,
2747                         (struct rte_eth_ntuple_filter *)arg,
2748                         filter_op);
2749                 break;
2750         default:
2751                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2752                 ret = -EINVAL;
2753                 break;
2754         }
2755         return ret;
2756 }
2757
2758 static int
2759 bnxt_parse_fdir_filter(struct bnxt *bp,
2760                        struct rte_eth_fdir_filter *fdir,
2761                        struct bnxt_filter_info *filter)
2762 {
2763         enum rte_fdir_mode fdir_mode =
2764                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2765         struct bnxt_vnic_info *vnic0, *vnic;
2766         struct bnxt_filter_info *filter1;
2767         uint32_t en = 0;
2768         int i;
2769
2770         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2771                 return -EINVAL;
2772
2773         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2774         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2775
2776         switch (fdir->input.flow_type) {
2777         case RTE_ETH_FLOW_IPV4:
2778         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2779                 /* FALLTHROUGH */
2780                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2781                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2782                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2783                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2784                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2785                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2786                 filter->ip_addr_type =
2787                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2788                 filter->src_ipaddr_mask[0] = 0xffffffff;
2789                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2790                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2791                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2792                 filter->ethertype = 0x800;
2793                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2794                 break;
2795         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2796                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2797                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2798                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2799                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2800                 filter->dst_port_mask = 0xffff;
2801                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2802                 filter->src_port_mask = 0xffff;
2803                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2804                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2805                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2806                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2807                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2808                 filter->ip_protocol = 6;
2809                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2810                 filter->ip_addr_type =
2811                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2812                 filter->src_ipaddr_mask[0] = 0xffffffff;
2813                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2814                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2815                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2816                 filter->ethertype = 0x800;
2817                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2818                 break;
2819         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2820                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2821                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2822                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2823                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2824                 filter->dst_port_mask = 0xffff;
2825                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2826                 filter->src_port_mask = 0xffff;
2827                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2828                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2829                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2830                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2831                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2832                 filter->ip_protocol = 17;
2833                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2834                 filter->ip_addr_type =
2835                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2836                 filter->src_ipaddr_mask[0] = 0xffffffff;
2837                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2838                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2839                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2840                 filter->ethertype = 0x800;
2841                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2842                 break;
2843         case RTE_ETH_FLOW_IPV6:
2844         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2845                 /* FALLTHROUGH */
2846                 filter->ip_addr_type =
2847                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2848                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2849                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2850                 rte_memcpy(filter->src_ipaddr,
2851                            fdir->input.flow.ipv6_flow.src_ip, 16);
2852                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2853                 rte_memcpy(filter->dst_ipaddr,
2854                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2855                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2856                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2857                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2858                 memset(filter->src_ipaddr_mask, 0xff, 16);
2859                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2860                 filter->ethertype = 0x86dd;
2861                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2862                 break;
2863         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2864                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2865                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2866                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2867                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2868                 filter->dst_port_mask = 0xffff;
2869                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2870                 filter->src_port_mask = 0xffff;
2871                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2872                 filter->ip_addr_type =
2873                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2874                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2875                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2876                 rte_memcpy(filter->src_ipaddr,
2877                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2878                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2879                 rte_memcpy(filter->dst_ipaddr,
2880                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2881                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2882                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2883                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2884                 memset(filter->src_ipaddr_mask, 0xff, 16);
2885                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2886                 filter->ethertype = 0x86dd;
2887                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2888                 break;
2889         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2890                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2891                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2892                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2893                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2894                 filter->dst_port_mask = 0xffff;
2895                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2896                 filter->src_port_mask = 0xffff;
2897                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2898                 filter->ip_addr_type =
2899                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2900                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2901                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2902                 rte_memcpy(filter->src_ipaddr,
2903                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2904                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2905                 rte_memcpy(filter->dst_ipaddr,
2906                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2907                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2908                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2909                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2910                 memset(filter->src_ipaddr_mask, 0xff, 16);
2911                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2912                 filter->ethertype = 0x86dd;
2913                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2914                 break;
2915         case RTE_ETH_FLOW_L2_PAYLOAD:
2916                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2917                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2918                 break;
2919         case RTE_ETH_FLOW_VXLAN:
2920                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2921                         return -EINVAL;
2922                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2923                 filter->tunnel_type =
2924                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2925                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2926                 break;
2927         case RTE_ETH_FLOW_NVGRE:
2928                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2929                         return -EINVAL;
2930                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2931                 filter->tunnel_type =
2932                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2933                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2934                 break;
2935         case RTE_ETH_FLOW_UNKNOWN:
2936         case RTE_ETH_FLOW_RAW:
2937         case RTE_ETH_FLOW_FRAG_IPV4:
2938         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2939         case RTE_ETH_FLOW_FRAG_IPV6:
2940         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2941         case RTE_ETH_FLOW_IPV6_EX:
2942         case RTE_ETH_FLOW_IPV6_TCP_EX:
2943         case RTE_ETH_FLOW_IPV6_UDP_EX:
2944         case RTE_ETH_FLOW_GENEVE:
2945                 /* FALLTHROUGH */
2946         default:
2947                 return -EINVAL;
2948         }
2949
2950         vnic0 = &bp->vnic_info[0];
2951         vnic = &bp->vnic_info[fdir->action.rx_queue];
2952         if (vnic == NULL) {
2953                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2954                 return -EINVAL;
2955         }
2956
2957         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2958                 rte_memcpy(filter->dst_macaddr,
2959                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2960                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2961         }
2962
2963         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2964                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2965                 filter1 = STAILQ_FIRST(&vnic0->filter);
2966                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2967         } else {
2968                 filter->dst_id = vnic->fw_vnic_id;
2969                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2970                         if (filter->dst_macaddr[i] == 0x00)
2971                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2972                         else
2973                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2974         }
2975
2976         if (filter1 == NULL)
2977                 return -EINVAL;
2978
2979         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2980         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2981
2982         filter->enables = en;
2983
2984         return 0;
2985 }
2986
2987 static struct bnxt_filter_info *
2988 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2989                 struct bnxt_vnic_info **mvnic)
2990 {
2991         struct bnxt_filter_info *mf = NULL;
2992         int i;
2993
2994         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2995                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2996
2997                 STAILQ_FOREACH(mf, &vnic->filter, next) {
2998                         if (mf->filter_type == nf->filter_type &&
2999                             mf->flags == nf->flags &&
3000                             mf->src_port == nf->src_port &&
3001                             mf->src_port_mask == nf->src_port_mask &&
3002                             mf->dst_port == nf->dst_port &&
3003                             mf->dst_port_mask == nf->dst_port_mask &&
3004                             mf->ip_protocol == nf->ip_protocol &&
3005                             mf->ip_addr_type == nf->ip_addr_type &&
3006                             mf->ethertype == nf->ethertype &&
3007                             mf->vni == nf->vni &&
3008                             mf->tunnel_type == nf->tunnel_type &&
3009                             mf->l2_ovlan == nf->l2_ovlan &&
3010                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3011                             mf->l2_ivlan == nf->l2_ivlan &&
3012                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3013                             !memcmp(mf->l2_addr, nf->l2_addr,
3014                                     RTE_ETHER_ADDR_LEN) &&
3015                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3016                                     RTE_ETHER_ADDR_LEN) &&
3017                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3018                                     RTE_ETHER_ADDR_LEN) &&
3019                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3020                                     RTE_ETHER_ADDR_LEN) &&
3021                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3022                                     sizeof(nf->src_ipaddr)) &&
3023                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3024                                     sizeof(nf->src_ipaddr_mask)) &&
3025                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3026                                     sizeof(nf->dst_ipaddr)) &&
3027                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3028                                     sizeof(nf->dst_ipaddr_mask))) {
3029                                 if (mvnic)
3030                                         *mvnic = vnic;
3031                                 return mf;
3032                         }
3033                 }
3034         }
3035         return NULL;
3036 }
3037
3038 static int
3039 bnxt_fdir_filter(struct rte_eth_dev *dev,
3040                  enum rte_filter_op filter_op,
3041                  void *arg)
3042 {
3043         struct bnxt *bp = dev->data->dev_private;
3044         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3045         struct bnxt_filter_info *filter, *match;
3046         struct bnxt_vnic_info *vnic, *mvnic;
3047         int ret = 0, i;
3048
3049         if (filter_op == RTE_ETH_FILTER_NOP)
3050                 return 0;
3051
3052         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3053                 return -EINVAL;
3054
3055         switch (filter_op) {
3056         case RTE_ETH_FILTER_ADD:
3057         case RTE_ETH_FILTER_DELETE:
3058                 /* FALLTHROUGH */
3059                 filter = bnxt_get_unused_filter(bp);
3060                 if (filter == NULL) {
3061                         PMD_DRV_LOG(ERR,
3062                                 "Not enough resources for a new flow.\n");
3063                         return -ENOMEM;
3064                 }
3065
3066                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3067                 if (ret != 0)
3068                         goto free_filter;
3069                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3070
3071                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3072                         vnic = &bp->vnic_info[0];
3073                 else
3074                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3075
3076                 match = bnxt_match_fdir(bp, filter, &mvnic);
3077                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3078                         if (match->dst_id == vnic->fw_vnic_id) {
3079                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3080                                 ret = -EEXIST;
3081                                 goto free_filter;
3082                         } else {
3083                                 match->dst_id = vnic->fw_vnic_id;
3084                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3085                                                                   match->dst_id,
3086                                                                   match);
3087                                 STAILQ_REMOVE(&mvnic->filter, match,
3088                                               bnxt_filter_info, next);
3089                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3090                                 PMD_DRV_LOG(ERR,
3091                                         "Filter with matching pattern exist\n");
3092                                 PMD_DRV_LOG(ERR,
3093                                         "Updated it to new destination q\n");
3094                                 goto free_filter;
3095                         }
3096                 }
3097                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3098                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3099                         ret = -ENOENT;
3100                         goto free_filter;
3101                 }
3102
3103                 if (filter_op == RTE_ETH_FILTER_ADD) {
3104                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3105                                                           filter->dst_id,
3106                                                           filter);
3107                         if (ret)
3108                                 goto free_filter;
3109                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3110                 } else {
3111                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3112                         STAILQ_REMOVE(&vnic->filter, match,
3113                                       bnxt_filter_info, next);
3114                         bnxt_free_filter(bp, match);
3115                         filter->fw_l2_filter_id = -1;
3116                         bnxt_free_filter(bp, filter);
3117                 }
3118                 break;
3119         case RTE_ETH_FILTER_FLUSH:
3120                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3121                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3122
3123                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3124                                 if (filter->filter_type ==
3125                                     HWRM_CFA_NTUPLE_FILTER) {
3126                                         ret =
3127                                         bnxt_hwrm_clear_ntuple_filter(bp,
3128                                                                       filter);
3129                                         STAILQ_REMOVE(&vnic->filter, filter,
3130                                                       bnxt_filter_info, next);
3131                                 }
3132                         }
3133                 }
3134                 return ret;
3135         case RTE_ETH_FILTER_UPDATE:
3136         case RTE_ETH_FILTER_STATS:
3137         case RTE_ETH_FILTER_INFO:
3138                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3139                 break;
3140         default:
3141                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3142                 ret = -EINVAL;
3143                 break;
3144         }
3145         return ret;
3146
3147 free_filter:
3148         filter->fw_l2_filter_id = -1;
3149         bnxt_free_filter(bp, filter);
3150         return ret;
3151 }
3152
3153 static int
3154 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
3155                     enum rte_filter_type filter_type,
3156                     enum rte_filter_op filter_op, void *arg)
3157 {
3158         int ret = 0;
3159
3160         ret = is_bnxt_in_error(dev->data->dev_private);
3161         if (ret)
3162                 return ret;
3163
3164         switch (filter_type) {
3165         case RTE_ETH_FILTER_TUNNEL:
3166                 PMD_DRV_LOG(ERR,
3167                         "filter type: %d: To be implemented\n", filter_type);
3168                 break;
3169         case RTE_ETH_FILTER_FDIR:
3170                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3171                 break;
3172         case RTE_ETH_FILTER_NTUPLE:
3173                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3174                 break;
3175         case RTE_ETH_FILTER_ETHERTYPE:
3176                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3177                 break;
3178         case RTE_ETH_FILTER_GENERIC:
3179                 if (filter_op != RTE_ETH_FILTER_GET)
3180                         return -EINVAL;
3181                 *(const void **)arg = &bnxt_flow_ops;
3182                 break;
3183         default:
3184                 PMD_DRV_LOG(ERR,
3185                         "Filter type (%d) not supported", filter_type);
3186                 ret = -EINVAL;
3187                 break;
3188         }
3189         return ret;
3190 }
3191
3192 static const uint32_t *
3193 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3194 {
3195         static const uint32_t ptypes[] = {
3196                 RTE_PTYPE_L2_ETHER_VLAN,
3197                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3198                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3199                 RTE_PTYPE_L4_ICMP,
3200                 RTE_PTYPE_L4_TCP,
3201                 RTE_PTYPE_L4_UDP,
3202                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3203                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3204                 RTE_PTYPE_INNER_L4_ICMP,
3205                 RTE_PTYPE_INNER_L4_TCP,
3206                 RTE_PTYPE_INNER_L4_UDP,
3207                 RTE_PTYPE_UNKNOWN
3208         };
3209
3210         if (!dev->rx_pkt_burst)
3211                 return NULL;
3212
3213         return ptypes;
3214 }
3215
3216 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3217                          int reg_win)
3218 {
3219         uint32_t reg_base = *reg_arr & 0xfffff000;
3220         uint32_t win_off;
3221         int i;
3222
3223         for (i = 0; i < count; i++) {
3224                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3225                         return -ERANGE;
3226         }
3227         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3228         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3229         return 0;
3230 }
3231
3232 static int bnxt_map_ptp_regs(struct bnxt *bp)
3233 {
3234         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3235         uint32_t *reg_arr;
3236         int rc, i;
3237
3238         reg_arr = ptp->rx_regs;
3239         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3240         if (rc)
3241                 return rc;
3242
3243         reg_arr = ptp->tx_regs;
3244         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3245         if (rc)
3246                 return rc;
3247
3248         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3249                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3250
3251         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3252                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3253
3254         return 0;
3255 }
3256
3257 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3258 {
3259         rte_write32(0, (uint8_t *)bp->bar0 +
3260                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3261         rte_write32(0, (uint8_t *)bp->bar0 +
3262                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3263 }
3264
3265 static uint64_t bnxt_cc_read(struct bnxt *bp)
3266 {
3267         uint64_t ns;
3268
3269         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3270                               BNXT_GRCPF_REG_SYNC_TIME));
3271         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3272                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3273         return ns;
3274 }
3275
3276 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3277 {
3278         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3279         uint32_t fifo;
3280
3281         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3282                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3283         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3284                 return -EAGAIN;
3285
3286         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3287                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3288         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3289                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3290         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3291                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3292
3293         return 0;
3294 }
3295
3296 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3297 {
3298         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3299         struct bnxt_pf_info *pf = &bp->pf;
3300         uint16_t port_id;
3301         uint32_t fifo;
3302
3303         if (!ptp)
3304                 return -ENODEV;
3305
3306         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3307                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3308         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3309                 return -EAGAIN;
3310
3311         port_id = pf->port_id;
3312         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3313                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3314
3315         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3316                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3317         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3318 /*              bnxt_clr_rx_ts(bp);       TBD  */
3319                 return -EBUSY;
3320         }
3321
3322         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3323                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3324         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3325                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3326
3327         return 0;
3328 }
3329
3330 static int
3331 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3332 {
3333         uint64_t ns;
3334         struct bnxt *bp = dev->data->dev_private;
3335         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3336
3337         if (!ptp)
3338                 return 0;
3339
3340         ns = rte_timespec_to_ns(ts);
3341         /* Set the timecounters to a new value. */
3342         ptp->tc.nsec = ns;
3343
3344         return 0;
3345 }
3346
3347 static int
3348 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3349 {
3350         struct bnxt *bp = dev->data->dev_private;
3351         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3352         uint64_t ns, systime_cycles = 0;
3353         int rc = 0;
3354
3355         if (!ptp)
3356                 return 0;
3357
3358         if (BNXT_CHIP_THOR(bp))
3359                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3360                                              &systime_cycles);
3361         else
3362                 systime_cycles = bnxt_cc_read(bp);
3363
3364         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3365         *ts = rte_ns_to_timespec(ns);
3366
3367         return rc;
3368 }
3369 static int
3370 bnxt_timesync_enable(struct rte_eth_dev *dev)
3371 {
3372         struct bnxt *bp = dev->data->dev_private;
3373         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3374         uint32_t shift = 0;
3375         int rc;
3376
3377         if (!ptp)
3378                 return 0;
3379
3380         ptp->rx_filter = 1;
3381         ptp->tx_tstamp_en = 1;
3382         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3383
3384         rc = bnxt_hwrm_ptp_cfg(bp);
3385         if (rc)
3386                 return rc;
3387
3388         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3389         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3390         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3391
3392         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3393         ptp->tc.cc_shift = shift;
3394         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3395
3396         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3397         ptp->rx_tstamp_tc.cc_shift = shift;
3398         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3399
3400         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3401         ptp->tx_tstamp_tc.cc_shift = shift;
3402         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3403
3404         if (!BNXT_CHIP_THOR(bp))
3405                 bnxt_map_ptp_regs(bp);
3406
3407         return 0;
3408 }
3409
3410 static int
3411 bnxt_timesync_disable(struct rte_eth_dev *dev)
3412 {
3413         struct bnxt *bp = dev->data->dev_private;
3414         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3415
3416         if (!ptp)
3417                 return 0;
3418
3419         ptp->rx_filter = 0;
3420         ptp->tx_tstamp_en = 0;
3421         ptp->rxctl = 0;
3422
3423         bnxt_hwrm_ptp_cfg(bp);
3424
3425         if (!BNXT_CHIP_THOR(bp))
3426                 bnxt_unmap_ptp_regs(bp);
3427
3428         return 0;
3429 }
3430
3431 static int
3432 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3433                                  struct timespec *timestamp,
3434                                  uint32_t flags __rte_unused)
3435 {
3436         struct bnxt *bp = dev->data->dev_private;
3437         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3438         uint64_t rx_tstamp_cycles = 0;
3439         uint64_t ns;
3440
3441         if (!ptp)
3442                 return 0;
3443
3444         if (BNXT_CHIP_THOR(bp))
3445                 rx_tstamp_cycles = ptp->rx_timestamp;
3446         else
3447                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3448
3449         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3450         *timestamp = rte_ns_to_timespec(ns);
3451         return  0;
3452 }
3453
3454 static int
3455 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3456                                  struct timespec *timestamp)
3457 {
3458         struct bnxt *bp = dev->data->dev_private;
3459         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3460         uint64_t tx_tstamp_cycles = 0;
3461         uint64_t ns;
3462         int rc = 0;
3463
3464         if (!ptp)
3465                 return 0;
3466
3467         if (BNXT_CHIP_THOR(bp))
3468                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3469                                              &tx_tstamp_cycles);
3470         else
3471                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3472
3473         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3474         *timestamp = rte_ns_to_timespec(ns);
3475
3476         return rc;
3477 }
3478
3479 static int
3480 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3481 {
3482         struct bnxt *bp = dev->data->dev_private;
3483         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3484
3485         if (!ptp)
3486                 return 0;
3487
3488         ptp->tc.nsec += delta;
3489
3490         return 0;
3491 }
3492
3493 static int
3494 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3495 {
3496         struct bnxt *bp = dev->data->dev_private;
3497         int rc;
3498         uint32_t dir_entries;
3499         uint32_t entry_length;
3500
3501         rc = is_bnxt_in_error(bp);
3502         if (rc)
3503                 return rc;
3504
3505         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3506                 bp->pdev->addr.domain, bp->pdev->addr.bus,
3507                 bp->pdev->addr.devid, bp->pdev->addr.function);
3508
3509         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3510         if (rc != 0)
3511                 return rc;
3512
3513         return dir_entries * entry_length;
3514 }
3515
3516 static int
3517 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3518                 struct rte_dev_eeprom_info *in_eeprom)
3519 {
3520         struct bnxt *bp = dev->data->dev_private;
3521         uint32_t index;
3522         uint32_t offset;
3523         int rc;
3524
3525         rc = is_bnxt_in_error(bp);
3526         if (rc)
3527                 return rc;
3528
3529         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3530                 "len = %d\n", bp->pdev->addr.domain,
3531                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3532                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3533
3534         if (in_eeprom->offset == 0) /* special offset value to get directory */
3535                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3536                                                 in_eeprom->data);
3537
3538         index = in_eeprom->offset >> 24;
3539         offset = in_eeprom->offset & 0xffffff;
3540
3541         if (index != 0)
3542                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3543                                            in_eeprom->length, in_eeprom->data);
3544
3545         return 0;
3546 }
3547
3548 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3549 {
3550         switch (dir_type) {
3551         case BNX_DIR_TYPE_CHIMP_PATCH:
3552         case BNX_DIR_TYPE_BOOTCODE:
3553         case BNX_DIR_TYPE_BOOTCODE_2:
3554         case BNX_DIR_TYPE_APE_FW:
3555         case BNX_DIR_TYPE_APE_PATCH:
3556         case BNX_DIR_TYPE_KONG_FW:
3557         case BNX_DIR_TYPE_KONG_PATCH:
3558         case BNX_DIR_TYPE_BONO_FW:
3559         case BNX_DIR_TYPE_BONO_PATCH:
3560                 /* FALLTHROUGH */
3561                 return true;
3562         }
3563
3564         return false;
3565 }
3566
3567 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3568 {
3569         switch (dir_type) {
3570         case BNX_DIR_TYPE_AVS:
3571         case BNX_DIR_TYPE_EXP_ROM_MBA:
3572         case BNX_DIR_TYPE_PCIE:
3573         case BNX_DIR_TYPE_TSCF_UCODE:
3574         case BNX_DIR_TYPE_EXT_PHY:
3575         case BNX_DIR_TYPE_CCM:
3576         case BNX_DIR_TYPE_ISCSI_BOOT:
3577         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3578         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3579                 /* FALLTHROUGH */
3580                 return true;
3581         }
3582
3583         return false;
3584 }
3585
3586 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3587 {
3588         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3589                 bnxt_dir_type_is_other_exec_format(dir_type);
3590 }
3591
3592 static int
3593 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3594                 struct rte_dev_eeprom_info *in_eeprom)
3595 {
3596         struct bnxt *bp = dev->data->dev_private;
3597         uint8_t index, dir_op;
3598         uint16_t type, ext, ordinal, attr;
3599         int rc;
3600
3601         rc = is_bnxt_in_error(bp);
3602         if (rc)
3603                 return rc;
3604
3605         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3606                 "len = %d\n", bp->pdev->addr.domain,
3607                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3608                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3609
3610         if (!BNXT_PF(bp)) {
3611                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3612                 return -EINVAL;
3613         }
3614
3615         type = in_eeprom->magic >> 16;
3616
3617         if (type == 0xffff) { /* special value for directory operations */
3618                 index = in_eeprom->magic & 0xff;
3619                 dir_op = in_eeprom->magic >> 8;
3620                 if (index == 0)
3621                         return -EINVAL;
3622                 switch (dir_op) {
3623                 case 0x0e: /* erase */
3624                         if (in_eeprom->offset != ~in_eeprom->magic)
3625                                 return -EINVAL;
3626                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3627                 default:
3628                         return -EINVAL;
3629                 }
3630         }
3631
3632         /* Create or re-write an NVM item: */
3633         if (bnxt_dir_type_is_executable(type) == true)
3634                 return -EOPNOTSUPP;
3635         ext = in_eeprom->magic & 0xffff;
3636         ordinal = in_eeprom->offset >> 16;
3637         attr = in_eeprom->offset & 0xffff;
3638
3639         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3640                                      in_eeprom->data, in_eeprom->length);
3641 }
3642
3643 /*
3644  * Initialization
3645  */
3646
3647 static const struct eth_dev_ops bnxt_dev_ops = {
3648         .dev_infos_get = bnxt_dev_info_get_op,
3649         .dev_close = bnxt_dev_close_op,
3650         .dev_configure = bnxt_dev_configure_op,
3651         .dev_start = bnxt_dev_start_op,
3652         .dev_stop = bnxt_dev_stop_op,
3653         .dev_set_link_up = bnxt_dev_set_link_up_op,
3654         .dev_set_link_down = bnxt_dev_set_link_down_op,
3655         .stats_get = bnxt_stats_get_op,
3656         .stats_reset = bnxt_stats_reset_op,
3657         .rx_queue_setup = bnxt_rx_queue_setup_op,
3658         .rx_queue_release = bnxt_rx_queue_release_op,
3659         .tx_queue_setup = bnxt_tx_queue_setup_op,
3660         .tx_queue_release = bnxt_tx_queue_release_op,
3661         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3662         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3663         .reta_update = bnxt_reta_update_op,
3664         .reta_query = bnxt_reta_query_op,
3665         .rss_hash_update = bnxt_rss_hash_update_op,
3666         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3667         .link_update = bnxt_link_update_op,
3668         .promiscuous_enable = bnxt_promiscuous_enable_op,
3669         .promiscuous_disable = bnxt_promiscuous_disable_op,
3670         .allmulticast_enable = bnxt_allmulticast_enable_op,
3671         .allmulticast_disable = bnxt_allmulticast_disable_op,
3672         .mac_addr_add = bnxt_mac_addr_add_op,
3673         .mac_addr_remove = bnxt_mac_addr_remove_op,
3674         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3675         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3676         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3677         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3678         .vlan_filter_set = bnxt_vlan_filter_set_op,
3679         .vlan_offload_set = bnxt_vlan_offload_set_op,
3680         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3681         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3682         .mtu_set = bnxt_mtu_set_op,
3683         .mac_addr_set = bnxt_set_default_mac_addr_op,
3684         .xstats_get = bnxt_dev_xstats_get_op,
3685         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3686         .xstats_reset = bnxt_dev_xstats_reset_op,
3687         .fw_version_get = bnxt_fw_version_get,
3688         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3689         .rxq_info_get = bnxt_rxq_info_get_op,
3690         .txq_info_get = bnxt_txq_info_get_op,
3691         .dev_led_on = bnxt_dev_led_on_op,
3692         .dev_led_off = bnxt_dev_led_off_op,
3693         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3694         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3695         .rx_queue_count = bnxt_rx_queue_count_op,
3696         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3697         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3698         .rx_queue_start = bnxt_rx_queue_start,
3699         .rx_queue_stop = bnxt_rx_queue_stop,
3700         .tx_queue_start = bnxt_tx_queue_start,
3701         .tx_queue_stop = bnxt_tx_queue_stop,
3702         .filter_ctrl = bnxt_filter_ctrl_op,
3703         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3704         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3705         .get_eeprom           = bnxt_get_eeprom_op,
3706         .set_eeprom           = bnxt_set_eeprom_op,
3707         .timesync_enable      = bnxt_timesync_enable,
3708         .timesync_disable     = bnxt_timesync_disable,
3709         .timesync_read_time   = bnxt_timesync_read_time,
3710         .timesync_write_time   = bnxt_timesync_write_time,
3711         .timesync_adjust_time = bnxt_timesync_adjust_time,
3712         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3713         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3714 };
3715
3716 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3717 {
3718         uint32_t offset;
3719
3720         /* Only pre-map the reset GRC registers using window 3 */
3721         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3722                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3723
3724         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3725
3726         return offset;
3727 }
3728
3729 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3730 {
3731         struct bnxt_error_recovery_info *info = bp->recovery_info;
3732         uint32_t reg_base = 0xffffffff;
3733         int i;
3734
3735         /* Only pre-map the monitoring GRC registers using window 2 */
3736         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3737                 uint32_t reg = info->status_regs[i];
3738
3739                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3740                         continue;
3741
3742                 if (reg_base == 0xffffffff)
3743                         reg_base = reg & 0xfffff000;
3744                 if ((reg & 0xfffff000) != reg_base)
3745                         return -ERANGE;
3746
3747                 /* Use mask 0xffc as the Lower 2 bits indicates
3748                  * address space location
3749                  */
3750                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3751                                                 (reg & 0xffc);
3752         }
3753
3754         if (reg_base == 0xffffffff)
3755                 return 0;
3756
3757         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3758                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3759
3760         return 0;
3761 }
3762
3763 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3764 {
3765         struct bnxt_error_recovery_info *info = bp->recovery_info;
3766         uint32_t delay = info->delay_after_reset[index];
3767         uint32_t val = info->reset_reg_val[index];
3768         uint32_t reg = info->reset_reg[index];
3769         uint32_t type, offset;
3770
3771         type = BNXT_FW_STATUS_REG_TYPE(reg);
3772         offset = BNXT_FW_STATUS_REG_OFF(reg);
3773
3774         switch (type) {
3775         case BNXT_FW_STATUS_REG_TYPE_CFG:
3776                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3777                 break;
3778         case BNXT_FW_STATUS_REG_TYPE_GRC:
3779                 offset = bnxt_map_reset_regs(bp, offset);
3780                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3781                 break;
3782         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3783                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3784                 break;
3785         }
3786         /* wait on a specific interval of time until core reset is complete */
3787         if (delay)
3788                 rte_delay_ms(delay);
3789 }
3790
3791 static void bnxt_dev_cleanup(struct bnxt *bp)
3792 {
3793         bnxt_set_hwrm_link_config(bp, false);
3794         bp->link_info.link_up = 0;
3795         if (bp->dev_stopped == 0)
3796                 bnxt_dev_stop_op(bp->eth_dev);
3797
3798         bnxt_uninit_resources(bp, true);
3799 }
3800
3801 static int bnxt_restore_filters(struct bnxt *bp)
3802 {
3803         struct rte_eth_dev *dev = bp->eth_dev;
3804         int ret = 0;
3805
3806         if (dev->data->all_multicast)
3807                 ret = bnxt_allmulticast_enable_op(dev);
3808         if (dev->data->promiscuous)
3809                 ret = bnxt_promiscuous_enable_op(dev);
3810
3811         /* TODO restore other filters as well */
3812         return ret;
3813 }
3814
3815 static void bnxt_dev_recover(void *arg)
3816 {
3817         struct bnxt *bp = arg;
3818         int timeout = bp->fw_reset_max_msecs;
3819         int rc = 0;
3820
3821         /* Clear Error flag so that device re-init should happen */
3822         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3823
3824         do {
3825                 rc = bnxt_hwrm_ver_get(bp);
3826                 if (rc == 0)
3827                         break;
3828                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3829                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3830         } while (rc && timeout);
3831
3832         if (rc) {
3833                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3834                 goto err;
3835         }
3836
3837         rc = bnxt_init_resources(bp, true);
3838         if (rc) {
3839                 PMD_DRV_LOG(ERR,
3840                             "Failed to initialize resources after reset\n");
3841                 goto err;
3842         }
3843         /* clear reset flag as the device is initialized now */
3844         bp->flags &= ~BNXT_FLAG_FW_RESET;
3845
3846         rc = bnxt_dev_start_op(bp->eth_dev);
3847         if (rc) {
3848                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3849                 goto err;
3850         }
3851
3852         rc = bnxt_restore_filters(bp);
3853         if (rc)
3854                 goto err;
3855
3856         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3857         return;
3858 err:
3859         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3860         bnxt_uninit_resources(bp, false);
3861         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3862 }
3863
3864 void bnxt_dev_reset_and_resume(void *arg)
3865 {
3866         struct bnxt *bp = arg;
3867         int rc;
3868
3869         bnxt_dev_cleanup(bp);
3870
3871         bnxt_wait_for_device_shutdown(bp);
3872
3873         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3874                                bnxt_dev_recover, (void *)bp);
3875         if (rc)
3876                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3877 }
3878
3879 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3880 {
3881         struct bnxt_error_recovery_info *info = bp->recovery_info;
3882         uint32_t reg = info->status_regs[index];
3883         uint32_t type, offset, val = 0;
3884
3885         type = BNXT_FW_STATUS_REG_TYPE(reg);
3886         offset = BNXT_FW_STATUS_REG_OFF(reg);
3887
3888         switch (type) {
3889         case BNXT_FW_STATUS_REG_TYPE_CFG:
3890                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3891                 break;
3892         case BNXT_FW_STATUS_REG_TYPE_GRC:
3893                 offset = info->mapped_status_regs[index];
3894                 /* FALLTHROUGH */
3895         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3896                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3897                                        offset));
3898                 break;
3899         }
3900
3901         return val;
3902 }
3903
3904 static int bnxt_fw_reset_all(struct bnxt *bp)
3905 {
3906         struct bnxt_error_recovery_info *info = bp->recovery_info;
3907         uint32_t i;
3908         int rc = 0;
3909
3910         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3911                 /* Reset through master function driver */
3912                 for (i = 0; i < info->reg_array_cnt; i++)
3913                         bnxt_write_fw_reset_reg(bp, i);
3914                 /* Wait for time specified by FW after triggering reset */
3915                 rte_delay_ms(info->master_func_wait_period_after_reset);
3916         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3917                 /* Reset with the help of Kong processor */
3918                 rc = bnxt_hwrm_fw_reset(bp);
3919                 if (rc)
3920                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3921         }
3922
3923         return rc;
3924 }
3925
3926 static void bnxt_fw_reset_cb(void *arg)
3927 {
3928         struct bnxt *bp = arg;
3929         struct bnxt_error_recovery_info *info = bp->recovery_info;
3930         int rc = 0;
3931
3932         /* Only Master function can do FW reset */
3933         if (bnxt_is_master_func(bp) &&
3934             bnxt_is_recovery_enabled(bp)) {
3935                 rc = bnxt_fw_reset_all(bp);
3936                 if (rc) {
3937                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3938                         return;
3939                 }
3940         }
3941
3942         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3943          * EXCEPTION_FATAL_ASYNC event to all the functions
3944          * (including MASTER FUNC). After receiving this Async, all the active
3945          * drivers should treat this case as FW initiated recovery
3946          */
3947         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3948                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3949                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3950
3951                 /* To recover from error */
3952                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3953                                   (void *)bp);
3954         }
3955 }
3956
3957 /* Driver should poll FW heartbeat, reset_counter with the frequency
3958  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3959  * When the driver detects heartbeat stop or change in reset_counter,
3960  * it has to trigger a reset to recover from the error condition.
3961  * A “master PF” is the function who will have the privilege to
3962  * initiate the chimp reset. The master PF will be elected by the
3963  * firmware and will be notified through async message.
3964  */
3965 static void bnxt_check_fw_health(void *arg)
3966 {
3967         struct bnxt *bp = arg;
3968         struct bnxt_error_recovery_info *info = bp->recovery_info;
3969         uint32_t val = 0, wait_msec;
3970
3971         if (!info || !bnxt_is_recovery_enabled(bp) ||
3972             is_bnxt_in_error(bp))
3973                 return;
3974
3975         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3976         if (val == info->last_heart_beat)
3977                 goto reset;
3978
3979         info->last_heart_beat = val;
3980
3981         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3982         if (val != info->last_reset_counter)
3983                 goto reset;
3984
3985         info->last_reset_counter = val;
3986
3987         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3988                           bnxt_check_fw_health, (void *)bp);
3989
3990         return;
3991 reset:
3992         /* Stop DMA to/from device */
3993         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3994         bp->flags |= BNXT_FLAG_FW_RESET;
3995
3996         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
3997
3998         if (bnxt_is_master_func(bp))
3999                 wait_msec = info->master_func_wait_period;
4000         else
4001                 wait_msec = info->normal_func_wait_period;
4002
4003         rte_eal_alarm_set(US_PER_MS * wait_msec,
4004                           bnxt_fw_reset_cb, (void *)bp);
4005 }
4006
4007 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4008 {
4009         uint32_t polling_freq;
4010
4011         if (!bnxt_is_recovery_enabled(bp))
4012                 return;
4013
4014         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4015                 return;
4016
4017         polling_freq = bp->recovery_info->driver_polling_freq;
4018
4019         rte_eal_alarm_set(US_PER_MS * polling_freq,
4020                           bnxt_check_fw_health, (void *)bp);
4021         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4022 }
4023
4024 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4025 {
4026         if (!bnxt_is_recovery_enabled(bp))
4027                 return;
4028
4029         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4030         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4031 }
4032
4033 static bool bnxt_vf_pciid(uint16_t id)
4034 {
4035         if (id == BROADCOM_DEV_ID_57304_VF ||
4036             id == BROADCOM_DEV_ID_57406_VF ||
4037             id == BROADCOM_DEV_ID_5731X_VF ||
4038             id == BROADCOM_DEV_ID_5741X_VF ||
4039             id == BROADCOM_DEV_ID_57414_VF ||
4040             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
4041             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
4042             id == BROADCOM_DEV_ID_58802_VF ||
4043             id == BROADCOM_DEV_ID_57500_VF1 ||
4044             id == BROADCOM_DEV_ID_57500_VF2)
4045                 return true;
4046         return false;
4047 }
4048
4049 static bool bnxt_thor_device(uint16_t id)
4050 {
4051         if (id == BROADCOM_DEV_ID_57508 ||
4052             id == BROADCOM_DEV_ID_57504 ||
4053             id == BROADCOM_DEV_ID_57502 ||
4054             id == BROADCOM_DEV_ID_57508_MF1 ||
4055             id == BROADCOM_DEV_ID_57504_MF1 ||
4056             id == BROADCOM_DEV_ID_57502_MF1 ||
4057             id == BROADCOM_DEV_ID_57508_MF2 ||
4058             id == BROADCOM_DEV_ID_57504_MF2 ||
4059             id == BROADCOM_DEV_ID_57502_MF2 ||
4060             id == BROADCOM_DEV_ID_57500_VF1 ||
4061             id == BROADCOM_DEV_ID_57500_VF2)
4062                 return true;
4063
4064         return false;
4065 }
4066
4067 bool bnxt_stratus_device(struct bnxt *bp)
4068 {
4069         uint16_t id = bp->pdev->id.device_id;
4070
4071         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
4072             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
4073             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
4074                 return true;
4075         return false;
4076 }
4077
4078 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4079 {
4080         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4081         struct bnxt *bp = eth_dev->data->dev_private;
4082
4083         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4084         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4085         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4086         if (!bp->bar0 || !bp->doorbell_base) {
4087                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4088                 return -ENODEV;
4089         }
4090
4091         bp->eth_dev = eth_dev;
4092         bp->pdev = pci_dev;
4093
4094         return 0;
4095 }
4096
4097 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
4098                                   struct bnxt_ctx_pg_info *ctx_pg,
4099                                   uint32_t mem_size,
4100                                   const char *suffix,
4101                                   uint16_t idx)
4102 {
4103         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4104         const struct rte_memzone *mz = NULL;
4105         char mz_name[RTE_MEMZONE_NAMESIZE];
4106         rte_iova_t mz_phys_addr;
4107         uint64_t valid_bits = 0;
4108         uint32_t sz;
4109         int i;
4110
4111         if (!mem_size)
4112                 return 0;
4113
4114         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4115                          BNXT_PAGE_SIZE;
4116         rmem->page_size = BNXT_PAGE_SIZE;
4117         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4118         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4119         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4120
4121         valid_bits = PTU_PTE_VALID;
4122
4123         if (rmem->nr_pages > 1) {
4124                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4125                          "bnxt_ctx_pg_tbl%s_%x_%d",
4126                          suffix, idx, bp->eth_dev->data->port_id);
4127                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4128                 mz = rte_memzone_lookup(mz_name);
4129                 if (!mz) {
4130                         mz = rte_memzone_reserve_aligned(mz_name,
4131                                                 rmem->nr_pages * 8,
4132                                                 SOCKET_ID_ANY,
4133                                                 RTE_MEMZONE_2MB |
4134                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4135                                                 RTE_MEMZONE_IOVA_CONTIG,
4136                                                 BNXT_PAGE_SIZE);
4137                         if (mz == NULL)
4138                                 return -ENOMEM;
4139                 }
4140
4141                 memset(mz->addr, 0, mz->len);
4142                 mz_phys_addr = mz->iova;
4143                 if ((unsigned long)mz->addr == mz_phys_addr) {
4144                         PMD_DRV_LOG(DEBUG,
4145                                     "physical address same as virtual\n");
4146                         PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4147                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
4148                         if (mz_phys_addr == RTE_BAD_IOVA) {
4149                                 PMD_DRV_LOG(ERR,
4150                                         "unable to map addr to phys memory\n");
4151                                 return -ENOMEM;
4152                         }
4153                 }
4154                 rte_mem_lock_page(((char *)mz->addr));
4155
4156                 rmem->pg_tbl = mz->addr;
4157                 rmem->pg_tbl_map = mz_phys_addr;
4158                 rmem->pg_tbl_mz = mz;
4159         }
4160
4161         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4162                  suffix, idx, bp->eth_dev->data->port_id);
4163         mz = rte_memzone_lookup(mz_name);
4164         if (!mz) {
4165                 mz = rte_memzone_reserve_aligned(mz_name,
4166                                                  mem_size,
4167                                                  SOCKET_ID_ANY,
4168                                                  RTE_MEMZONE_1GB |
4169                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4170                                                  RTE_MEMZONE_IOVA_CONTIG,
4171                                                  BNXT_PAGE_SIZE);
4172                 if (mz == NULL)
4173                         return -ENOMEM;
4174         }
4175
4176         memset(mz->addr, 0, mz->len);
4177         mz_phys_addr = mz->iova;
4178         if ((unsigned long)mz->addr == mz_phys_addr) {
4179                 PMD_DRV_LOG(DEBUG,
4180                             "Memzone physical address same as virtual.\n");
4181                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4182                 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
4183                         rte_mem_lock_page(((char *)mz->addr) + sz);
4184                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4185                 if (mz_phys_addr == RTE_BAD_IOVA) {
4186                         PMD_DRV_LOG(ERR,
4187                                     "unable to map addr to phys memory\n");
4188                         return -ENOMEM;
4189                 }
4190         }
4191
4192         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4193                 rte_mem_lock_page(((char *)mz->addr) + sz);
4194                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4195                 rmem->dma_arr[i] = mz_phys_addr + sz;
4196
4197                 if (rmem->nr_pages > 1) {
4198                         if (i == rmem->nr_pages - 2 &&
4199                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4200                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4201                         else if (i == rmem->nr_pages - 1 &&
4202                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4203                                 valid_bits |= PTU_PTE_LAST;
4204
4205                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4206                                                            valid_bits);
4207                 }
4208         }
4209
4210         rmem->mz = mz;
4211         if (rmem->vmem_size)
4212                 rmem->vmem = (void **)mz->addr;
4213         rmem->dma_arr[0] = mz_phys_addr;
4214         return 0;
4215 }
4216
4217 static void bnxt_free_ctx_mem(struct bnxt *bp)
4218 {
4219         int i;
4220
4221         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4222                 return;
4223
4224         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4225         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4226         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4227         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4228         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4229         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4230         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4231         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4232         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4233         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4234         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4235
4236         for (i = 0; i < BNXT_MAX_Q; i++) {
4237                 if (bp->ctx->tqm_mem[i])
4238                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4239         }
4240
4241         rte_free(bp->ctx);
4242         bp->ctx = NULL;
4243 }
4244
4245 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4246
4247 #define min_t(type, x, y) ({                    \
4248         type __min1 = (x);                      \
4249         type __min2 = (y);                      \
4250         __min1 < __min2 ? __min1 : __min2; })
4251
4252 #define max_t(type, x, y) ({                    \
4253         type __max1 = (x);                      \
4254         type __max2 = (y);                      \
4255         __max1 > __max2 ? __max1 : __max2; })
4256
4257 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4258
4259 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4260 {
4261         struct bnxt_ctx_pg_info *ctx_pg;
4262         struct bnxt_ctx_mem_info *ctx;
4263         uint32_t mem_size, ena, entries;
4264         int i, rc;
4265
4266         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4267         if (rc) {
4268                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4269                 return rc;
4270         }
4271         ctx = bp->ctx;
4272         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4273                 return 0;
4274
4275         ctx_pg = &ctx->qp_mem;
4276         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4277         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4278         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4279         if (rc)
4280                 return rc;
4281
4282         ctx_pg = &ctx->srq_mem;
4283         ctx_pg->entries = ctx->srq_max_l2_entries;
4284         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4285         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4286         if (rc)
4287                 return rc;
4288
4289         ctx_pg = &ctx->cq_mem;
4290         ctx_pg->entries = ctx->cq_max_l2_entries;
4291         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4292         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4293         if (rc)
4294                 return rc;
4295
4296         ctx_pg = &ctx->vnic_mem;
4297         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4298                 ctx->vnic_max_ring_table_entries;
4299         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4300         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4301         if (rc)
4302                 return rc;
4303
4304         ctx_pg = &ctx->stat_mem;
4305         ctx_pg->entries = ctx->stat_max_entries;
4306         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4307         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4308         if (rc)
4309                 return rc;
4310
4311         entries = ctx->qp_max_l2_entries +
4312                   ctx->vnic_max_vnic_entries +
4313                   ctx->tqm_min_entries_per_ring;
4314         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4315         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4316                           ctx->tqm_max_entries_per_ring);
4317         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4318                 ctx_pg = ctx->tqm_mem[i];
4319                 /* use min tqm entries for now. */
4320                 ctx_pg->entries = entries;
4321                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4322                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4323                 if (rc)
4324                         return rc;
4325                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4326         }
4327
4328         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4329         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4330         if (rc)
4331                 PMD_DRV_LOG(ERR,
4332                             "Failed to configure context mem: rc = %d\n", rc);
4333         else
4334                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4335
4336         return rc;
4337 }
4338
4339 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4340 {
4341         struct rte_pci_device *pci_dev = bp->pdev;
4342         char mz_name[RTE_MEMZONE_NAMESIZE];
4343         const struct rte_memzone *mz = NULL;
4344         uint32_t total_alloc_len;
4345         rte_iova_t mz_phys_addr;
4346
4347         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4348                 return 0;
4349
4350         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4351                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4352                  pci_dev->addr.bus, pci_dev->addr.devid,
4353                  pci_dev->addr.function, "rx_port_stats");
4354         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4355         mz = rte_memzone_lookup(mz_name);
4356         total_alloc_len =
4357                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4358                                        sizeof(struct rx_port_stats_ext) + 512);
4359         if (!mz) {
4360                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4361                                          SOCKET_ID_ANY,
4362                                          RTE_MEMZONE_2MB |
4363                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4364                                          RTE_MEMZONE_IOVA_CONTIG);
4365                 if (mz == NULL)
4366                         return -ENOMEM;
4367         }
4368         memset(mz->addr, 0, mz->len);
4369         mz_phys_addr = mz->iova;
4370         if ((unsigned long)mz->addr == mz_phys_addr) {
4371                 PMD_DRV_LOG(DEBUG,
4372                             "Memzone physical address same as virtual.\n");
4373                 PMD_DRV_LOG(DEBUG,
4374                             "Using rte_mem_virt2iova()\n");
4375                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4376                 if (mz_phys_addr == RTE_BAD_IOVA) {
4377                         PMD_DRV_LOG(ERR,
4378                                     "Can't map address to physical memory\n");
4379                         return -ENOMEM;
4380                 }
4381         }
4382
4383         bp->rx_mem_zone = (const void *)mz;
4384         bp->hw_rx_port_stats = mz->addr;
4385         bp->hw_rx_port_stats_map = mz_phys_addr;
4386
4387         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4388                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4389                  pci_dev->addr.bus, pci_dev->addr.devid,
4390                  pci_dev->addr.function, "tx_port_stats");
4391         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4392         mz = rte_memzone_lookup(mz_name);
4393         total_alloc_len =
4394                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4395                                        sizeof(struct tx_port_stats_ext) + 512);
4396         if (!mz) {
4397                 mz = rte_memzone_reserve(mz_name,
4398                                          total_alloc_len,
4399                                          SOCKET_ID_ANY,
4400                                          RTE_MEMZONE_2MB |
4401                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4402                                          RTE_MEMZONE_IOVA_CONTIG);
4403                 if (mz == NULL)
4404                         return -ENOMEM;
4405         }
4406         memset(mz->addr, 0, mz->len);
4407         mz_phys_addr = mz->iova;
4408         if ((unsigned long)mz->addr == mz_phys_addr) {
4409                 PMD_DRV_LOG(DEBUG,
4410                             "Memzone physical address same as virtual\n");
4411                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4412                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4413                 if (mz_phys_addr == RTE_BAD_IOVA) {
4414                         PMD_DRV_LOG(ERR,
4415                                     "Can't map address to physical memory\n");
4416                         return -ENOMEM;
4417                 }
4418         }
4419
4420         bp->tx_mem_zone = (const void *)mz;
4421         bp->hw_tx_port_stats = mz->addr;
4422         bp->hw_tx_port_stats_map = mz_phys_addr;
4423         bp->flags |= BNXT_FLAG_PORT_STATS;
4424
4425         /* Display extended statistics if FW supports it */
4426         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4427             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4428             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4429                 return 0;
4430
4431         bp->hw_rx_port_stats_ext = (void *)
4432                 ((uint8_t *)bp->hw_rx_port_stats +
4433                  sizeof(struct rx_port_stats));
4434         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4435                 sizeof(struct rx_port_stats);
4436         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4437
4438         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4439             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4440                 bp->hw_tx_port_stats_ext = (void *)
4441                         ((uint8_t *)bp->hw_tx_port_stats +
4442                          sizeof(struct tx_port_stats));
4443                 bp->hw_tx_port_stats_ext_map =
4444                         bp->hw_tx_port_stats_map +
4445                         sizeof(struct tx_port_stats);
4446                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4447         }
4448
4449         return 0;
4450 }
4451
4452 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4453 {
4454         struct bnxt *bp = eth_dev->data->dev_private;
4455         int rc = 0;
4456
4457         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4458                                                RTE_ETHER_ADDR_LEN *
4459                                                bp->max_l2_ctx,
4460                                                0);
4461         if (eth_dev->data->mac_addrs == NULL) {
4462                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4463                 return -ENOMEM;
4464         }
4465
4466         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4467                 if (BNXT_PF(bp))
4468                         return -EINVAL;
4469
4470                 /* Generate a random MAC address, if none was assigned by PF */
4471                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4472                 bnxt_eth_hw_addr_random(bp->mac_addr);
4473                 PMD_DRV_LOG(INFO,
4474                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4475                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4476                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4477
4478                 rc = bnxt_hwrm_set_mac(bp);
4479                 if (!rc)
4480                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4481                                RTE_ETHER_ADDR_LEN);
4482                 return rc;
4483         }
4484
4485         /* Copy the permanent MAC from the FUNC_QCAPS response */
4486         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4487         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4488
4489         return rc;
4490 }
4491
4492 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4493 {
4494         int rc = 0;
4495
4496         /* MAC is already configured in FW */
4497         if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4498                 return 0;
4499
4500         /* Restore the old MAC configured */
4501         rc = bnxt_hwrm_set_mac(bp);
4502         if (rc)
4503                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4504
4505         return rc;
4506 }
4507
4508 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4509 {
4510         if (!BNXT_PF(bp))
4511                 return;
4512
4513 #define ALLOW_FUNC(x)   \
4514         { \
4515                 uint32_t arg = (x); \
4516                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4517                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4518         }
4519
4520         /* Forward all requests if firmware is new enough */
4521         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4522              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4523             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4524                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4525         } else {
4526                 PMD_DRV_LOG(WARNING,
4527                             "Firmware too old for VF mailbox functionality\n");
4528                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4529         }
4530
4531         /*
4532          * The following are used for driver cleanup. If we disallow these,
4533          * VF drivers can't clean up cleanly.
4534          */
4535         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4536         ALLOW_FUNC(HWRM_VNIC_FREE);
4537         ALLOW_FUNC(HWRM_RING_FREE);
4538         ALLOW_FUNC(HWRM_RING_GRP_FREE);
4539         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4540         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4541         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4542         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4543         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4544 }
4545
4546 static int bnxt_init_fw(struct bnxt *bp)
4547 {
4548         uint16_t mtu;
4549         int rc = 0;
4550
4551         rc = bnxt_hwrm_ver_get(bp);
4552         if (rc)
4553                 return rc;
4554
4555         rc = bnxt_hwrm_func_reset(bp);
4556         if (rc)
4557                 return -EIO;
4558
4559         rc = bnxt_hwrm_vnic_qcaps(bp);
4560         if (rc)
4561                 return rc;
4562
4563         rc = bnxt_hwrm_queue_qportcfg(bp);
4564         if (rc)
4565                 return rc;
4566
4567         /* Get the MAX capabilities for this function.
4568          * This function also allocates context memory for TQM rings and
4569          * informs the firmware about this allocated backing store memory.
4570          */
4571         rc = bnxt_hwrm_func_qcaps(bp);
4572         if (rc)
4573                 return rc;
4574
4575         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4576         if (rc)
4577                 return rc;
4578
4579         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4580         if (rc)
4581                 return rc;
4582
4583         /* Get the adapter error recovery support info */
4584         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4585         if (rc)
4586                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
4587
4588         if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
4589             mtu != bp->eth_dev->data->mtu)
4590                 bp->eth_dev->data->mtu = mtu;
4591
4592         bnxt_hwrm_port_led_qcaps(bp);
4593
4594         return 0;
4595 }
4596
4597 static int
4598 bnxt_init_locks(struct bnxt *bp)
4599 {
4600         int err;
4601
4602         err = pthread_mutex_init(&bp->flow_lock, NULL);
4603         if (err) {
4604                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4605                 return err;
4606         }
4607
4608         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4609         if (err)
4610                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4611         return err;
4612 }
4613
4614 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4615 {
4616         int rc;
4617
4618         rc = bnxt_init_fw(bp);
4619         if (rc)
4620                 return rc;
4621
4622         if (!reconfig_dev) {
4623                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4624                 if (rc)
4625                         return rc;
4626         } else {
4627                 rc = bnxt_restore_dflt_mac(bp);
4628                 if (rc)
4629                         return rc;
4630         }
4631
4632         bnxt_config_vf_req_fwd(bp);
4633
4634         rc = bnxt_hwrm_func_driver_register(bp);
4635         if (rc) {
4636                 PMD_DRV_LOG(ERR, "Failed to register driver");
4637                 return -EBUSY;
4638         }
4639
4640         if (BNXT_PF(bp)) {
4641                 if (bp->pdev->max_vfs) {
4642                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4643                         if (rc) {
4644                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4645                                 return rc;
4646                         }
4647                 } else {
4648                         rc = bnxt_hwrm_allocate_pf_only(bp);
4649                         if (rc) {
4650                                 PMD_DRV_LOG(ERR,
4651                                             "Failed to allocate PF resources");
4652                                 return rc;
4653                         }
4654                 }
4655         }
4656
4657         rc = bnxt_alloc_mem(bp, reconfig_dev);
4658         if (rc)
4659                 return rc;
4660
4661         rc = bnxt_setup_int(bp);
4662         if (rc)
4663                 return rc;
4664
4665         bnxt_init_nic(bp);
4666
4667         rc = bnxt_request_int(bp);
4668         if (rc)
4669                 return rc;
4670
4671         rc = bnxt_init_locks(bp);
4672         if (rc)
4673                 return rc;
4674
4675         return 0;
4676 }
4677
4678 static int
4679 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4680 {
4681         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4682         static int version_printed;
4683         struct bnxt *bp;
4684         int rc;
4685
4686         if (version_printed++ == 0)
4687                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4688
4689         eth_dev->dev_ops = &bnxt_dev_ops;
4690         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4691         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4692
4693         /*
4694          * For secondary processes, we don't initialise any further
4695          * as primary has already done this work.
4696          */
4697         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4698                 return 0;
4699
4700         rte_eth_copy_pci_info(eth_dev, pci_dev);
4701
4702         bp = eth_dev->data->dev_private;
4703
4704         bp->dev_stopped = 1;
4705
4706         if (bnxt_vf_pciid(pci_dev->id.device_id))
4707                 bp->flags |= BNXT_FLAG_VF;
4708
4709         if (bnxt_thor_device(pci_dev->id.device_id))
4710                 bp->flags |= BNXT_FLAG_THOR_CHIP;
4711
4712         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4713             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4714             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4715             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4716                 bp->flags |= BNXT_FLAG_STINGRAY;
4717
4718         rc = bnxt_init_board(eth_dev);
4719         if (rc) {
4720                 PMD_DRV_LOG(ERR,
4721                             "Failed to initialize board rc: %x\n", rc);
4722                 return rc;
4723         }
4724
4725         rc = bnxt_alloc_hwrm_resources(bp);
4726         if (rc) {
4727                 PMD_DRV_LOG(ERR,
4728                             "Failed to allocate hwrm resource rc: %x\n", rc);
4729                 goto error_free;
4730         }
4731         rc = bnxt_init_resources(bp, false);
4732         if (rc)
4733                 goto error_free;
4734
4735         rc = bnxt_alloc_stats_mem(bp);
4736         if (rc)
4737                 goto error_free;
4738
4739         PMD_DRV_LOG(INFO,
4740                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4741                     pci_dev->mem_resource[0].phys_addr,
4742                     pci_dev->mem_resource[0].addr);
4743
4744         return 0;
4745
4746 error_free:
4747         bnxt_dev_uninit(eth_dev);
4748         return rc;
4749 }
4750
4751 static void
4752 bnxt_uninit_locks(struct bnxt *bp)
4753 {
4754         pthread_mutex_destroy(&bp->flow_lock);
4755         pthread_mutex_destroy(&bp->def_cp_lock);
4756 }
4757
4758 static int
4759 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4760 {
4761         int rc;
4762
4763         bnxt_free_int(bp);
4764         bnxt_free_mem(bp, reconfig_dev);
4765         bnxt_hwrm_func_buf_unrgtr(bp);
4766         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4767         bp->flags &= ~BNXT_FLAG_REGISTERED;
4768         bnxt_free_ctx_mem(bp);
4769         if (!reconfig_dev) {
4770                 bnxt_free_hwrm_resources(bp);
4771
4772                 if (bp->recovery_info != NULL) {
4773                         rte_free(bp->recovery_info);
4774                         bp->recovery_info = NULL;
4775                 }
4776         }
4777
4778         bnxt_uninit_locks(bp);
4779         rte_free(bp->ptp_cfg);
4780         bp->ptp_cfg = NULL;
4781         return rc;
4782 }
4783
4784 static int
4785 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4786 {
4787         struct bnxt *bp = eth_dev->data->dev_private;
4788         int rc;
4789
4790         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4791                 return -EPERM;
4792
4793         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4794
4795         rc = bnxt_uninit_resources(bp, false);
4796
4797         if (bp->tx_mem_zone) {
4798                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4799                 bp->tx_mem_zone = NULL;
4800         }
4801
4802         if (bp->rx_mem_zone) {
4803                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4804                 bp->rx_mem_zone = NULL;
4805         }
4806
4807         if (bp->dev_stopped == 0)
4808                 bnxt_dev_close_op(eth_dev);
4809         if (bp->pf.vf_info)
4810                 rte_free(bp->pf.vf_info);
4811         eth_dev->dev_ops = NULL;
4812         eth_dev->rx_pkt_burst = NULL;
4813         eth_dev->tx_pkt_burst = NULL;
4814
4815         return rc;
4816 }
4817
4818 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4819         struct rte_pci_device *pci_dev)
4820 {
4821         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4822                 bnxt_dev_init);
4823 }
4824
4825 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4826 {
4827         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4828                 return rte_eth_dev_pci_generic_remove(pci_dev,
4829                                 bnxt_dev_uninit);
4830         else
4831                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4832 }
4833
4834 static struct rte_pci_driver bnxt_rte_pmd = {
4835         .id_table = bnxt_pci_id_map,
4836         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4837         .probe = bnxt_pci_probe,
4838         .remove = bnxt_pci_remove,
4839 };
4840
4841 static bool
4842 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4843 {
4844         if (strcmp(dev->device->driver->name, drv->driver.name))
4845                 return false;
4846
4847         return true;
4848 }
4849
4850 bool is_bnxt_supported(struct rte_eth_dev *dev)
4851 {
4852         return is_device_supported(dev, &bnxt_rte_pmd);
4853 }
4854
4855 RTE_INIT(bnxt_init_log)
4856 {
4857         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4858         if (bnxt_logtype_driver >= 0)
4859                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4860 }
4861
4862 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4863 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4864 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");