1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2021 Broadcom
10 #include <ethdev_driver.h>
11 #include <ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
15 #include <rte_kvargs.h>
19 #include "bnxt_filter.h"
20 #include "bnxt_hwrm.h"
22 #include "bnxt_reps.h"
23 #include "bnxt_ring.h"
26 #include "bnxt_stats.h"
29 #include "bnxt_vnic.h"
30 #include "hsi_struct_def_dpdk.h"
31 #include "bnxt_nvm_defs.h"
32 #include "bnxt_tf_common.h"
33 #include "ulp_flow_db.h"
34 #include "rte_pmd_bnxt.h"
36 #define DRV_MODULE_NAME "bnxt"
37 static const char bnxt_version[] =
38 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
41 * The set of PCI devices this driver supports
43 static const struct rte_pci_id bnxt_pci_id_map[] = {
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
45 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
47 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
87 { .vendor_id = 0, /* sentinel */ },
90 #define BNXT_DEVARG_TRUFLOW "host-based-truflow"
91 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat"
92 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows"
93 #define BNXT_DEVARG_REPRESENTOR "representor"
94 #define BNXT_DEVARG_REP_BASED_PF "rep-based-pf"
95 #define BNXT_DEVARG_REP_IS_PF "rep-is-pf"
96 #define BNXT_DEVARG_REP_Q_R2F "rep-q-r2f"
97 #define BNXT_DEVARG_REP_Q_F2R "rep-q-f2r"
98 #define BNXT_DEVARG_REP_FC_R2F "rep-fc-r2f"
99 #define BNXT_DEVARG_REP_FC_F2R "rep-fc-f2r"
101 static const char *const bnxt_dev_args[] = {
102 BNXT_DEVARG_REPRESENTOR,
104 BNXT_DEVARG_FLOW_XSTAT,
105 BNXT_DEVARG_MAX_NUM_KFLOWS,
106 BNXT_DEVARG_REP_BASED_PF,
107 BNXT_DEVARG_REP_IS_PF,
108 BNXT_DEVARG_REP_Q_R2F,
109 BNXT_DEVARG_REP_Q_F2R,
110 BNXT_DEVARG_REP_FC_R2F,
111 BNXT_DEVARG_REP_FC_F2R,
116 * truflow == false to disable the feature
117 * truflow == true to enable the feature
119 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1)
122 * flow_xstat == false to disable the feature
123 * flow_xstat == true to enable the feature
125 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1)
128 * rep_is_pf == false to indicate VF representor
129 * rep_is_pf == true to indicate PF representor
131 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf) ((rep_is_pf) > 1)
134 * rep_based_pf == Physical index of the PF
136 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf) ((rep_based_pf) > 15)
138 * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
140 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f) ((rep_q_r2f) > 3)
143 * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
145 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r) ((rep_q_f2r) > 3)
148 * rep_fc_r2f == Flow control for the representor to endpoint direction
150 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f) ((rep_fc_r2f) > 1)
153 * rep_fc_f2r == Flow control for the endpoint to representor direction
155 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r) ((rep_fc_f2r) > 1)
157 int bnxt_cfa_code_dynfield_offset = -1;
160 * max_num_kflows must be >= 32
161 * and must be a power-of-2 supported value
162 * return: 1 -> invalid
165 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
167 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
172 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
173 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
174 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
175 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
176 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
177 static int bnxt_restore_vlan_filters(struct bnxt *bp);
178 static void bnxt_dev_recover(void *arg);
179 static void bnxt_free_error_recovery_info(struct bnxt *bp);
180 static void bnxt_free_rep_info(struct bnxt *bp);
182 int is_bnxt_in_error(struct bnxt *bp)
184 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
186 if (bp->flags & BNXT_FLAG_FW_RESET)
192 /***********************/
195 * High level utility functions
198 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
200 unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
201 BNXT_RSS_TBL_SIZE_P5);
203 if (!BNXT_CHIP_P5(bp))
206 return RTE_ALIGN_MUL_CEIL(num_rss_rings,
207 BNXT_RSS_ENTRIES_PER_CTX_P5) /
208 BNXT_RSS_ENTRIES_PER_CTX_P5;
211 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
213 if (!BNXT_CHIP_P5(bp))
214 return HW_HASH_INDEX_SIZE;
216 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
219 static void bnxt_free_parent_info(struct bnxt *bp)
221 rte_free(bp->parent);
224 static void bnxt_free_pf_info(struct bnxt *bp)
229 static void bnxt_free_link_info(struct bnxt *bp)
231 rte_free(bp->link_info);
234 static void bnxt_free_leds_info(struct bnxt *bp)
243 static void bnxt_free_flow_stats_info(struct bnxt *bp)
245 rte_free(bp->flow_stat);
246 bp->flow_stat = NULL;
249 static void bnxt_free_cos_queues(struct bnxt *bp)
251 rte_free(bp->rx_cos_queue);
252 rte_free(bp->tx_cos_queue);
255 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
257 bnxt_free_filter_mem(bp);
258 bnxt_free_vnic_attributes(bp);
259 bnxt_free_vnic_mem(bp);
261 /* tx/rx rings are configured as part of *_queue_setup callbacks.
262 * If the number of rings change across fw update,
263 * we don't have much choice except to warn the user.
267 bnxt_free_tx_rings(bp);
268 bnxt_free_rx_rings(bp);
270 bnxt_free_async_cp_ring(bp);
271 bnxt_free_rxtx_nq_ring(bp);
273 rte_free(bp->grp_info);
277 static int bnxt_alloc_parent_info(struct bnxt *bp)
279 bp->parent = rte_zmalloc("bnxt_parent_info",
280 sizeof(struct bnxt_parent_info), 0);
281 if (bp->parent == NULL)
287 static int bnxt_alloc_pf_info(struct bnxt *bp)
289 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
296 static int bnxt_alloc_link_info(struct bnxt *bp)
299 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
300 if (bp->link_info == NULL)
306 static int bnxt_alloc_leds_info(struct bnxt *bp)
311 bp->leds = rte_zmalloc("bnxt_leds",
312 BNXT_MAX_LED * sizeof(struct bnxt_led_info),
314 if (bp->leds == NULL)
320 static int bnxt_alloc_cos_queues(struct bnxt *bp)
323 rte_zmalloc("bnxt_rx_cosq",
324 BNXT_COS_QUEUE_COUNT *
325 sizeof(struct bnxt_cos_queue_info),
327 if (bp->rx_cos_queue == NULL)
331 rte_zmalloc("bnxt_tx_cosq",
332 BNXT_COS_QUEUE_COUNT *
333 sizeof(struct bnxt_cos_queue_info),
335 if (bp->tx_cos_queue == NULL)
341 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
343 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
344 sizeof(struct bnxt_flow_stat_info), 0);
345 if (bp->flow_stat == NULL)
351 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
355 rc = bnxt_alloc_ring_grps(bp);
359 rc = bnxt_alloc_async_ring_struct(bp);
363 rc = bnxt_alloc_vnic_mem(bp);
367 rc = bnxt_alloc_vnic_attributes(bp);
371 rc = bnxt_alloc_filter_mem(bp);
375 rc = bnxt_alloc_async_cp_ring(bp);
379 rc = bnxt_alloc_rxtx_nq_ring(bp);
383 if (BNXT_FLOW_XSTATS_EN(bp)) {
384 rc = bnxt_alloc_flow_stats_info(bp);
392 bnxt_free_mem(bp, reconfig);
396 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
398 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
399 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
400 uint64_t rx_offloads = dev_conf->rxmode.offloads;
401 struct bnxt_rx_queue *rxq;
405 rc = bnxt_vnic_grp_alloc(bp, vnic);
409 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
410 vnic_id, vnic, vnic->fw_grp_ids);
412 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
416 /* Alloc RSS context only if RSS mode is enabled */
417 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
418 int j, nr_ctxs = bnxt_rss_ctxts(bp);
420 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
421 PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
422 bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
424 "Only queues 0-%d will be in RSS table\n",
425 BNXT_RSS_TBL_SIZE_P5 - 1);
429 for (j = 0; j < nr_ctxs; j++) {
430 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
436 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
440 vnic->num_lb_ctxts = nr_ctxs;
444 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
445 * setting is not available at this time, it will not be
446 * configured correctly in the CFA.
448 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
449 vnic->vlan_strip = true;
451 vnic->vlan_strip = false;
453 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
457 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
461 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
462 rxq = bp->eth_dev->data->rx_queues[j];
465 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
466 j, rxq->vnic, rxq->vnic->fw_grp_ids);
468 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
469 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
471 vnic->rx_queue_cnt++;
474 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
476 rc = bnxt_vnic_rss_configure(bp, vnic);
480 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
482 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
483 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
485 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
489 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
494 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
498 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
499 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
504 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
505 " rx_fc_in_tbl.ctx_id = %d\n",
506 bp->flow_stat->rx_fc_in_tbl.va,
507 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
508 bp->flow_stat->rx_fc_in_tbl.ctx_id);
510 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
511 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
516 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
517 " rx_fc_out_tbl.ctx_id = %d\n",
518 bp->flow_stat->rx_fc_out_tbl.va,
519 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
520 bp->flow_stat->rx_fc_out_tbl.ctx_id);
522 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
523 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
528 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
529 " tx_fc_in_tbl.ctx_id = %d\n",
530 bp->flow_stat->tx_fc_in_tbl.va,
531 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
532 bp->flow_stat->tx_fc_in_tbl.ctx_id);
534 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
535 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
540 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
541 " tx_fc_out_tbl.ctx_id = %d\n",
542 bp->flow_stat->tx_fc_out_tbl.va,
543 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
544 bp->flow_stat->tx_fc_out_tbl.ctx_id);
546 memset(bp->flow_stat->rx_fc_out_tbl.va,
548 bp->flow_stat->rx_fc_out_tbl.size);
549 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
550 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
551 bp->flow_stat->rx_fc_out_tbl.ctx_id,
552 bp->flow_stat->max_fc,
557 memset(bp->flow_stat->tx_fc_out_tbl.va,
559 bp->flow_stat->tx_fc_out_tbl.size);
560 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
561 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
562 bp->flow_stat->tx_fc_out_tbl.ctx_id,
563 bp->flow_stat->max_fc,
569 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
570 struct bnxt_ctx_mem_buf_info *ctx)
575 ctx->va = rte_zmalloc(type, size, 0);
578 rte_mem_lock_page(ctx->va);
580 ctx->dma = rte_mem_virt2iova(ctx->va);
581 if (ctx->dma == RTE_BAD_IOVA)
587 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
589 struct rte_pci_device *pdev = bp->pdev;
590 char type[RTE_MEMZONE_NAMESIZE];
594 max_fc = bp->flow_stat->max_fc;
596 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
597 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
598 /* 4 bytes for each counter-id */
599 rc = bnxt_alloc_ctx_mem_buf(type,
601 &bp->flow_stat->rx_fc_in_tbl);
605 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
606 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
607 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
608 rc = bnxt_alloc_ctx_mem_buf(type,
610 &bp->flow_stat->rx_fc_out_tbl);
614 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
615 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
616 /* 4 bytes for each counter-id */
617 rc = bnxt_alloc_ctx_mem_buf(type,
619 &bp->flow_stat->tx_fc_in_tbl);
623 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
624 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
625 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
626 rc = bnxt_alloc_ctx_mem_buf(type,
628 &bp->flow_stat->tx_fc_out_tbl);
632 rc = bnxt_register_fc_ctx_mem(bp);
637 static int bnxt_init_ctx_mem(struct bnxt *bp)
641 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
642 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
643 !BNXT_FLOW_XSTATS_EN(bp))
646 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
650 rc = bnxt_init_fc_ctx_mem(bp);
655 static int bnxt_update_phy_setting(struct bnxt *bp)
657 struct rte_eth_link new;
660 rc = bnxt_get_hwrm_link_config(bp, &new);
662 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
667 * On BCM957508-N2100 adapters, FW will not allow any user other
668 * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
669 * always returns link up. Force phy update always in that case.
671 if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
672 rc = bnxt_set_hwrm_link_config(bp, true);
674 PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
682 static int bnxt_start_nic(struct bnxt *bp)
684 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
685 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
686 uint32_t intr_vector = 0;
687 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
688 uint32_t vec = BNXT_MISC_VEC_ID;
692 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
693 bp->eth_dev->data->dev_conf.rxmode.offloads |=
694 DEV_RX_OFFLOAD_JUMBO_FRAME;
695 bp->flags |= BNXT_FLAG_JUMBO;
697 bp->eth_dev->data->dev_conf.rxmode.offloads &=
698 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
699 bp->flags &= ~BNXT_FLAG_JUMBO;
702 /* THOR does not support ring groups.
703 * But we will use the array to save RSS context IDs.
705 if (BNXT_CHIP_P5(bp))
706 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
708 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
710 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
714 rc = bnxt_alloc_hwrm_rings(bp);
716 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
720 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
722 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
726 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
729 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
730 if (bp->rx_cos_queue[i].id != 0xff) {
731 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
735 "Num pools more than FW profile\n");
739 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
745 rc = bnxt_mq_rx_configure(bp);
747 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
752 rc = bnxt_setup_one_vnic(bp, 0);
755 /* VNIC configuration */
756 if (BNXT_RFS_NEEDS_VNIC(bp)) {
757 for (i = 1; i < bp->nr_vnics; i++) {
758 rc = bnxt_setup_one_vnic(bp, i);
764 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
767 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
771 /* check and configure queue intr-vector mapping */
772 if ((rte_intr_cap_multiple(intr_handle) ||
773 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
774 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
775 intr_vector = bp->eth_dev->data->nb_rx_queues;
776 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
777 if (intr_vector > bp->rx_cp_nr_rings) {
778 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
782 rc = rte_intr_efd_enable(intr_handle, intr_vector);
787 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
788 intr_handle->intr_vec =
789 rte_zmalloc("intr_vec",
790 bp->eth_dev->data->nb_rx_queues *
792 if (intr_handle->intr_vec == NULL) {
793 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
794 " intr_vec", bp->eth_dev->data->nb_rx_queues);
798 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
799 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
800 intr_handle->intr_vec, intr_handle->nb_efd,
801 intr_handle->max_intr);
802 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
804 intr_handle->intr_vec[queue_id] =
805 vec + BNXT_RX_VEC_START;
806 if (vec < base + intr_handle->nb_efd - 1)
811 /* enable uio/vfio intr/eventfd mapping */
812 rc = rte_intr_enable(intr_handle);
813 #ifndef RTE_EXEC_ENV_FREEBSD
814 /* In FreeBSD OS, nic_uio driver does not support interrupts */
819 rc = bnxt_update_phy_setting(bp);
823 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
825 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
830 rte_free(intr_handle->intr_vec);
832 rte_intr_efd_disable(intr_handle);
834 /* Some of the error status returned by FW may not be from errno.h */
841 static int bnxt_shutdown_nic(struct bnxt *bp)
843 bnxt_free_all_hwrm_resources(bp);
844 bnxt_free_all_filters(bp);
845 bnxt_free_all_vnics(bp);
850 * Device configuration and status function
853 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
855 uint32_t link_speed = bp->link_info->support_speeds;
856 uint32_t speed_capa = 0;
858 /* If PAM4 is configured, use PAM4 supported speed */
859 if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
860 link_speed = bp->link_info->support_pam4_speeds;
862 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
863 speed_capa |= ETH_LINK_SPEED_100M;
864 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
865 speed_capa |= ETH_LINK_SPEED_100M_HD;
866 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
867 speed_capa |= ETH_LINK_SPEED_1G;
868 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
869 speed_capa |= ETH_LINK_SPEED_2_5G;
870 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
871 speed_capa |= ETH_LINK_SPEED_10G;
872 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
873 speed_capa |= ETH_LINK_SPEED_20G;
874 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
875 speed_capa |= ETH_LINK_SPEED_25G;
876 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
877 speed_capa |= ETH_LINK_SPEED_40G;
878 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
879 speed_capa |= ETH_LINK_SPEED_50G;
880 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
881 speed_capa |= ETH_LINK_SPEED_100G;
882 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
883 speed_capa |= ETH_LINK_SPEED_50G;
884 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
885 speed_capa |= ETH_LINK_SPEED_100G;
886 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
887 speed_capa |= ETH_LINK_SPEED_200G;
889 if (bp->link_info->auto_mode ==
890 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
891 speed_capa |= ETH_LINK_SPEED_FIXED;
893 speed_capa |= ETH_LINK_SPEED_AUTONEG;
898 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
899 struct rte_eth_dev_info *dev_info)
901 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
902 struct bnxt *bp = eth_dev->data->dev_private;
903 uint16_t max_vnics, i, j, vpool, vrxq;
904 unsigned int max_rx_rings;
907 rc = is_bnxt_in_error(bp);
912 dev_info->max_mac_addrs = bp->max_l2_ctx;
913 dev_info->max_hash_mac_addrs = 0;
915 /* PF/VF specifics */
917 dev_info->max_vfs = pdev->max_vfs;
919 max_rx_rings = bnxt_max_rings(bp);
920 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
921 dev_info->max_rx_queues = max_rx_rings;
922 dev_info->max_tx_queues = max_rx_rings;
923 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
924 dev_info->hash_key_size = 40;
925 max_vnics = bp->max_vnics;
928 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
929 dev_info->max_mtu = BNXT_MAX_MTU;
931 /* Fast path specifics */
932 dev_info->min_rx_bufsize = 1;
933 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
935 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
936 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
937 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
938 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
939 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
940 dev_info->tx_queue_offload_capa;
941 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
943 dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
946 dev_info->default_rxconf = (struct rte_eth_rxconf) {
952 .rx_free_thresh = 32,
953 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
956 dev_info->default_txconf = (struct rte_eth_txconf) {
962 .tx_free_thresh = 32,
965 eth_dev->data->dev_conf.intr_conf.lsc = 1;
967 eth_dev->data->dev_conf.intr_conf.rxq = 1;
968 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
969 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
970 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
971 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
973 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
974 dev_info->switch_info.name = eth_dev->device->name;
975 dev_info->switch_info.domain_id = bp->switch_domain_id;
976 dev_info->switch_info.port_id =
977 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
978 BNXT_SWITCH_PORT_ID_TRUSTED_VF;
984 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
985 * need further investigation.
989 vpool = 64; /* ETH_64_POOLS */
990 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
991 for (i = 0; i < 4; vpool >>= 1, i++) {
992 if (max_vnics > vpool) {
993 for (j = 0; j < 5; vrxq >>= 1, j++) {
994 if (dev_info->max_rx_queues > vrxq) {
1000 /* Not enough resources to support VMDq */
1004 /* Not enough resources to support VMDq */
1008 dev_info->max_vmdq_pools = vpool;
1009 dev_info->vmdq_queue_num = vrxq;
1011 dev_info->vmdq_pool_base = 0;
1012 dev_info->vmdq_queue_base = 0;
1017 /* Configure the device based on the configuration provided */
1018 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1020 struct bnxt *bp = eth_dev->data->dev_private;
1021 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1024 bp->rx_queues = (void *)eth_dev->data->rx_queues;
1025 bp->tx_queues = (void *)eth_dev->data->tx_queues;
1026 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1027 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1029 rc = is_bnxt_in_error(bp);
1033 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1034 rc = bnxt_hwrm_check_vf_rings(bp);
1036 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1040 /* If a resource has already been allocated - in this case
1041 * it is the async completion ring, free it. Reallocate it after
1042 * resource reservation. This will ensure the resource counts
1043 * are calculated correctly.
1046 pthread_mutex_lock(&bp->def_cp_lock);
1048 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1049 bnxt_disable_int(bp);
1050 bnxt_free_cp_ring(bp, bp->async_cp_ring);
1053 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1055 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1056 pthread_mutex_unlock(&bp->def_cp_lock);
1060 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1061 rc = bnxt_alloc_async_cp_ring(bp);
1063 pthread_mutex_unlock(&bp->def_cp_lock);
1066 bnxt_enable_int(bp);
1069 pthread_mutex_unlock(&bp->def_cp_lock);
1072 /* Inherit new configurations */
1073 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1074 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1075 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1076 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1077 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1079 goto resource_error;
1081 if (BNXT_HAS_RING_GRPS(bp) &&
1082 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1083 goto resource_error;
1085 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1086 bp->max_vnics < eth_dev->data->nb_rx_queues)
1087 goto resource_error;
1089 bp->rx_cp_nr_rings = bp->rx_nr_rings;
1090 bp->tx_cp_nr_rings = bp->tx_nr_rings;
1092 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1093 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1094 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1096 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1097 eth_dev->data->mtu =
1098 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1099 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1101 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1107 "Insufficient resources to support requested config\n");
1109 "Num Queues Requested: Tx %d, Rx %d\n",
1110 eth_dev->data->nb_tx_queues,
1111 eth_dev->data->nb_rx_queues);
1113 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1114 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1115 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1119 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1121 struct rte_eth_link *link = ð_dev->data->dev_link;
1123 if (link->link_status)
1124 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1125 eth_dev->data->port_id,
1126 (uint32_t)link->link_speed,
1127 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1128 ("full-duplex") : ("half-duplex\n"));
1130 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1131 eth_dev->data->port_id);
1135 * Determine whether the current configuration requires support for scattered
1136 * receive; return 1 if scattered receive is required and 0 if not.
1138 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1143 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1146 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO)
1149 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1150 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1152 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1153 RTE_PKTMBUF_HEADROOM);
1154 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1160 static eth_rx_burst_t
1161 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1163 struct bnxt *bp = eth_dev->data->dev_private;
1165 /* Disable vector mode RX for Stingray2 for now */
1166 if (BNXT_CHIP_SR2(bp)) {
1167 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1168 return bnxt_recv_pkts;
1171 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1172 #ifndef RTE_LIBRTE_IEEE1588
1174 * Vector mode receive can be enabled only if scatter rx is not
1175 * in use and rx offloads are limited to VLAN stripping and
1178 if (!eth_dev->data->scattered_rx &&
1179 !(eth_dev->data->dev_conf.rxmode.offloads &
1180 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1181 DEV_RX_OFFLOAD_KEEP_CRC |
1182 DEV_RX_OFFLOAD_JUMBO_FRAME |
1183 DEV_RX_OFFLOAD_IPV4_CKSUM |
1184 DEV_RX_OFFLOAD_UDP_CKSUM |
1185 DEV_RX_OFFLOAD_TCP_CKSUM |
1186 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1187 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1188 DEV_RX_OFFLOAD_RSS_HASH |
1189 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1190 !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp) &&
1191 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1192 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1193 eth_dev->data->port_id);
1194 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1195 return bnxt_recv_pkts_vec;
1197 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1198 eth_dev->data->port_id);
1200 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1201 eth_dev->data->port_id,
1202 eth_dev->data->scattered_rx,
1203 eth_dev->data->dev_conf.rxmode.offloads);
1206 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1207 return bnxt_recv_pkts;
1210 static eth_tx_burst_t
1211 bnxt_transmit_function(struct rte_eth_dev *eth_dev)
1213 struct bnxt *bp = eth_dev->data->dev_private;
1215 /* Disable vector mode TX for Stingray2 for now */
1216 if (BNXT_CHIP_SR2(bp))
1217 return bnxt_xmit_pkts;
1219 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1220 #ifndef RTE_LIBRTE_IEEE1588
1221 uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1224 * Vector mode transmit can be enabled only if not using scatter rx
1227 if (!eth_dev->data->scattered_rx &&
1228 !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
1229 !BNXT_TRUFLOW_EN(bp) &&
1230 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1231 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1232 eth_dev->data->port_id);
1233 return bnxt_xmit_pkts_vec;
1235 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1236 eth_dev->data->port_id);
1238 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1239 eth_dev->data->port_id,
1240 eth_dev->data->scattered_rx,
1244 return bnxt_xmit_pkts;
1247 static int bnxt_handle_if_change_status(struct bnxt *bp)
1251 /* Since fw has undergone a reset and lost all contexts,
1252 * set fatal flag to not issue hwrm during cleanup
1254 bp->flags |= BNXT_FLAG_FATAL_ERROR;
1255 bnxt_uninit_resources(bp, true);
1257 /* clear fatal flag so that re-init happens */
1258 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1259 rc = bnxt_init_resources(bp, true);
1261 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1266 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1268 struct bnxt *bp = eth_dev->data->dev_private;
1271 if (!BNXT_SINGLE_PF(bp))
1274 if (!bp->link_info->link_up)
1275 rc = bnxt_set_hwrm_link_config(bp, true);
1277 eth_dev->data->dev_link.link_status = 1;
1279 bnxt_print_link_info(eth_dev);
1283 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1285 struct bnxt *bp = eth_dev->data->dev_private;
1287 if (!BNXT_SINGLE_PF(bp))
1290 eth_dev->data->dev_link.link_status = 0;
1291 bnxt_set_hwrm_link_config(bp, false);
1292 bp->link_info->link_up = 0;
1297 static void bnxt_free_switch_domain(struct bnxt *bp)
1301 if (bp->switch_domain_id) {
1302 rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1304 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1305 bp->switch_domain_id, rc);
1309 static void bnxt_ptp_get_current_time(void *arg)
1311 struct bnxt *bp = arg;
1312 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1315 rc = is_bnxt_in_error(bp);
1322 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1323 &ptp->current_time);
1325 rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1327 PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n");
1328 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1332 static int bnxt_schedule_ptp_alarm(struct bnxt *bp)
1334 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1337 if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED)
1340 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1341 &ptp->current_time);
1343 rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1347 static void bnxt_cancel_ptp_alarm(struct bnxt *bp)
1349 if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) {
1350 rte_eal_alarm_cancel(bnxt_ptp_get_current_time, (void *)bp);
1351 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1355 static void bnxt_ptp_stop(struct bnxt *bp)
1357 bnxt_cancel_ptp_alarm(bp);
1358 bp->flags2 &= ~BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1361 static int bnxt_ptp_start(struct bnxt *bp)
1365 rc = bnxt_schedule_ptp_alarm(bp);
1367 PMD_DRV_LOG(ERR, "Failed to schedule PTP alarm\n");
1369 bp->flags2 |= BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1370 bp->flags2 |= BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1376 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev)
1378 struct bnxt *bp = eth_dev->data->dev_private;
1379 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1380 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1381 struct rte_eth_link link;
1384 eth_dev->data->dev_started = 0;
1385 eth_dev->data->scattered_rx = 0;
1387 /* Prevent crashes when queues are still in use */
1388 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1389 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1391 bnxt_disable_int(bp);
1393 /* disable uio/vfio intr/eventfd mapping */
1394 rte_intr_disable(intr_handle);
1396 /* Stop the child representors for this device */
1397 ret = bnxt_rep_stop_all(bp);
1401 /* delete the bnxt ULP port details */
1402 bnxt_ulp_port_deinit(bp);
1404 bnxt_cancel_fw_health_check(bp);
1406 if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1407 bnxt_cancel_ptp_alarm(bp);
1409 /* Do not bring link down during reset recovery */
1410 if (!is_bnxt_in_error(bp)) {
1411 bnxt_dev_set_link_down_op(eth_dev);
1412 /* Wait for link to be reset */
1413 if (BNXT_SINGLE_PF(bp))
1415 /* clear the recorded link status */
1416 memset(&link, 0, sizeof(link));
1417 rte_eth_linkstatus_set(eth_dev, &link);
1420 /* Clean queue intr-vector mapping */
1421 rte_intr_efd_disable(intr_handle);
1422 if (intr_handle->intr_vec != NULL) {
1423 rte_free(intr_handle->intr_vec);
1424 intr_handle->intr_vec = NULL;
1427 bnxt_hwrm_port_clr_stats(bp);
1428 bnxt_free_tx_mbufs(bp);
1429 bnxt_free_rx_mbufs(bp);
1430 /* Process any remaining notifications in default completion queue */
1431 bnxt_int_handler(eth_dev);
1432 bnxt_shutdown_nic(bp);
1433 bnxt_hwrm_if_change(bp, false);
1435 rte_free(bp->mark_table);
1436 bp->mark_table = NULL;
1438 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1439 bp->rx_cosq_cnt = 0;
1440 /* All filters are deleted on a port stop. */
1441 if (BNXT_FLOW_XSTATS_EN(bp))
1442 bp->flow_stat->flow_count = 0;
1447 /* Unload the driver, release resources */
1448 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1450 struct bnxt *bp = eth_dev->data->dev_private;
1452 pthread_mutex_lock(&bp->err_recovery_lock);
1453 if (bp->flags & BNXT_FLAG_FW_RESET) {
1455 "Adapter recovering from error..Please retry\n");
1456 pthread_mutex_unlock(&bp->err_recovery_lock);
1459 pthread_mutex_unlock(&bp->err_recovery_lock);
1461 return bnxt_dev_stop(eth_dev);
1464 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1466 struct bnxt *bp = eth_dev->data->dev_private;
1467 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1469 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1471 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1472 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1476 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1478 "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1479 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1482 rc = bnxt_hwrm_if_change(bp, true);
1483 if (rc == 0 || rc != -EAGAIN)
1486 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1487 } while (retry_cnt--);
1492 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1493 rc = bnxt_handle_if_change_status(bp);
1498 bnxt_enable_int(bp);
1500 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1502 rc = bnxt_start_nic(bp);
1506 eth_dev->data->dev_started = 1;
1508 bnxt_link_update_op(eth_dev, 1);
1510 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1511 vlan_mask |= ETH_VLAN_FILTER_MASK;
1512 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1513 vlan_mask |= ETH_VLAN_STRIP_MASK;
1514 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1518 /* Initialize bnxt ULP port details */
1519 rc = bnxt_ulp_port_init(bp);
1523 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1524 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1526 bnxt_schedule_fw_health_check(bp);
1528 if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1529 bnxt_schedule_ptp_alarm(bp);
1534 bnxt_dev_stop(eth_dev);
1539 bnxt_uninit_locks(struct bnxt *bp)
1541 pthread_mutex_destroy(&bp->flow_lock);
1542 pthread_mutex_destroy(&bp->def_cp_lock);
1543 pthread_mutex_destroy(&bp->health_check_lock);
1544 pthread_mutex_destroy(&bp->err_recovery_lock);
1546 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
1547 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
1551 static void bnxt_drv_uninit(struct bnxt *bp)
1553 bnxt_free_switch_domain(bp);
1554 bnxt_free_leds_info(bp);
1555 bnxt_free_cos_queues(bp);
1556 bnxt_free_link_info(bp);
1557 bnxt_free_pf_info(bp);
1558 bnxt_free_parent_info(bp);
1559 bnxt_uninit_locks(bp);
1561 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1562 bp->tx_mem_zone = NULL;
1563 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1564 bp->rx_mem_zone = NULL;
1566 bnxt_free_vf_info(bp);
1568 rte_free(bp->grp_info);
1569 bp->grp_info = NULL;
1572 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1574 struct bnxt *bp = eth_dev->data->dev_private;
1577 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1580 pthread_mutex_lock(&bp->err_recovery_lock);
1581 if (bp->flags & BNXT_FLAG_FW_RESET) {
1583 "Adapter recovering from error...Please retry\n");
1584 pthread_mutex_unlock(&bp->err_recovery_lock);
1587 pthread_mutex_unlock(&bp->err_recovery_lock);
1589 /* cancel the recovery handler before remove dev */
1590 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1591 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1592 bnxt_cancel_fc_thread(bp);
1594 if (eth_dev->data->dev_started)
1595 ret = bnxt_dev_stop(eth_dev);
1597 bnxt_uninit_resources(bp, false);
1599 bnxt_drv_uninit(bp);
1604 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1607 struct bnxt *bp = eth_dev->data->dev_private;
1608 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1609 struct bnxt_vnic_info *vnic;
1610 struct bnxt_filter_info *filter, *temp_filter;
1613 if (is_bnxt_in_error(bp))
1617 * Loop through all VNICs from the specified filter flow pools to
1618 * remove the corresponding MAC addr filter
1620 for (i = 0; i < bp->nr_vnics; i++) {
1621 if (!(pool_mask & (1ULL << i)))
1624 vnic = &bp->vnic_info[i];
1625 filter = STAILQ_FIRST(&vnic->filter);
1627 temp_filter = STAILQ_NEXT(filter, next);
1628 if (filter->mac_index == index) {
1629 STAILQ_REMOVE(&vnic->filter, filter,
1630 bnxt_filter_info, next);
1631 bnxt_hwrm_clear_l2_filter(bp, filter);
1632 bnxt_free_filter(bp, filter);
1634 filter = temp_filter;
1639 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1640 struct rte_ether_addr *mac_addr, uint32_t index,
1643 struct bnxt_filter_info *filter;
1646 /* Attach requested MAC address to the new l2_filter */
1647 STAILQ_FOREACH(filter, &vnic->filter, next) {
1648 if (filter->mac_index == index) {
1650 "MAC addr already existed for pool %d\n",
1656 filter = bnxt_alloc_filter(bp);
1658 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1662 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1663 * if the MAC that's been programmed now is a different one, then,
1664 * copy that addr to filter->l2_addr
1667 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1668 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1670 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1672 filter->mac_index = index;
1673 if (filter->mac_index == 0)
1674 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1676 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1678 bnxt_free_filter(bp, filter);
1684 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1685 struct rte_ether_addr *mac_addr,
1686 uint32_t index, uint32_t pool)
1688 struct bnxt *bp = eth_dev->data->dev_private;
1689 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1692 rc = is_bnxt_in_error(bp);
1696 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1697 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1702 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1706 /* Filter settings will get applied when port is started */
1707 if (!eth_dev->data->dev_started)
1710 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1715 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1718 struct bnxt *bp = eth_dev->data->dev_private;
1719 struct rte_eth_link new;
1720 int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1721 BNXT_MIN_LINK_WAIT_CNT;
1723 rc = is_bnxt_in_error(bp);
1727 memset(&new, 0, sizeof(new));
1729 /* Retrieve link info from hardware */
1730 rc = bnxt_get_hwrm_link_config(bp, &new);
1732 new.link_speed = ETH_LINK_SPEED_100M;
1733 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1735 "Failed to retrieve link rc = 0x%x!\n", rc);
1739 if (!wait_to_complete || new.link_status)
1742 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1745 /* Only single function PF can bring phy down.
1746 * When port is stopped, report link down for VF/MH/NPAR functions.
1748 if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1749 memset(&new, 0, sizeof(new));
1752 /* Timed out or success */
1753 if (new.link_status != eth_dev->data->dev_link.link_status ||
1754 new.link_speed != eth_dev->data->dev_link.link_speed) {
1755 rte_eth_linkstatus_set(eth_dev, &new);
1757 rte_eth_dev_callback_process(eth_dev,
1758 RTE_ETH_EVENT_INTR_LSC,
1761 bnxt_print_link_info(eth_dev);
1767 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1769 struct bnxt *bp = eth_dev->data->dev_private;
1770 struct bnxt_vnic_info *vnic;
1774 rc = is_bnxt_in_error(bp);
1778 /* Filter settings will get applied when port is started */
1779 if (!eth_dev->data->dev_started)
1782 if (bp->vnic_info == NULL)
1785 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1787 old_flags = vnic->flags;
1788 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1789 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1791 vnic->flags = old_flags;
1796 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1798 struct bnxt *bp = eth_dev->data->dev_private;
1799 struct bnxt_vnic_info *vnic;
1803 rc = is_bnxt_in_error(bp);
1807 /* Filter settings will get applied when port is started */
1808 if (!eth_dev->data->dev_started)
1811 if (bp->vnic_info == NULL)
1814 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1816 old_flags = vnic->flags;
1817 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1818 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1820 vnic->flags = old_flags;
1825 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1827 struct bnxt *bp = eth_dev->data->dev_private;
1828 struct bnxt_vnic_info *vnic;
1832 rc = is_bnxt_in_error(bp);
1836 /* Filter settings will get applied when port is started */
1837 if (!eth_dev->data->dev_started)
1840 if (bp->vnic_info == NULL)
1843 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1845 old_flags = vnic->flags;
1846 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1847 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1849 vnic->flags = old_flags;
1854 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1856 struct bnxt *bp = eth_dev->data->dev_private;
1857 struct bnxt_vnic_info *vnic;
1861 rc = is_bnxt_in_error(bp);
1865 /* Filter settings will get applied when port is started */
1866 if (!eth_dev->data->dev_started)
1869 if (bp->vnic_info == NULL)
1872 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1874 old_flags = vnic->flags;
1875 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1876 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1878 vnic->flags = old_flags;
1883 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1884 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1886 if (qid >= bp->rx_nr_rings)
1889 return bp->eth_dev->data->rx_queues[qid];
1892 /* Return rxq corresponding to a given rss table ring/group ID. */
1893 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1895 struct bnxt_rx_queue *rxq;
1898 if (!BNXT_HAS_RING_GRPS(bp)) {
1899 for (i = 0; i < bp->rx_nr_rings; i++) {
1900 rxq = bp->eth_dev->data->rx_queues[i];
1901 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1905 for (i = 0; i < bp->rx_nr_rings; i++) {
1906 if (bp->grp_info[i].fw_grp_id == fwr)
1911 return INVALID_HW_RING_ID;
1914 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1915 struct rte_eth_rss_reta_entry64 *reta_conf,
1918 struct bnxt *bp = eth_dev->data->dev_private;
1919 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1920 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1921 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1925 rc = is_bnxt_in_error(bp);
1929 if (!vnic->rss_table)
1932 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1935 if (reta_size != tbl_size) {
1936 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1937 "(%d) must equal the size supported by the hardware "
1938 "(%d)\n", reta_size, tbl_size);
1942 for (i = 0; i < reta_size; i++) {
1943 struct bnxt_rx_queue *rxq;
1945 idx = i / RTE_RETA_GROUP_SIZE;
1946 sft = i % RTE_RETA_GROUP_SIZE;
1948 if (!(reta_conf[idx].mask & (1ULL << sft)))
1951 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1953 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1957 if (BNXT_CHIP_P5(bp)) {
1958 vnic->rss_table[i * 2] =
1959 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1960 vnic->rss_table[i * 2 + 1] =
1961 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1963 vnic->rss_table[i] =
1964 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1968 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1972 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1973 struct rte_eth_rss_reta_entry64 *reta_conf,
1976 struct bnxt *bp = eth_dev->data->dev_private;
1977 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1978 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1979 uint16_t idx, sft, i;
1982 rc = is_bnxt_in_error(bp);
1986 /* Retrieve from the default VNIC */
1989 if (!vnic->rss_table)
1992 if (reta_size != tbl_size) {
1993 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1994 "(%d) must equal the size supported by the hardware "
1995 "(%d)\n", reta_size, tbl_size);
1999 for (idx = 0, i = 0; i < reta_size; i++) {
2000 idx = i / RTE_RETA_GROUP_SIZE;
2001 sft = i % RTE_RETA_GROUP_SIZE;
2003 if (reta_conf[idx].mask & (1ULL << sft)) {
2006 if (BNXT_CHIP_P5(bp))
2007 qid = bnxt_rss_to_qid(bp,
2008 vnic->rss_table[i * 2]);
2010 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
2012 if (qid == INVALID_HW_RING_ID) {
2013 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
2016 reta_conf[idx].reta[sft] = qid;
2023 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
2024 struct rte_eth_rss_conf *rss_conf)
2026 struct bnxt *bp = eth_dev->data->dev_private;
2027 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2028 struct bnxt_vnic_info *vnic;
2031 rc = is_bnxt_in_error(bp);
2036 * If RSS enablement were different than dev_configure,
2037 * then return -EINVAL
2039 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
2040 if (!rss_conf->rss_hf)
2041 PMD_DRV_LOG(ERR, "Hash type NONE\n");
2043 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
2047 bp->flags |= BNXT_FLAG_UPDATE_HASH;
2048 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf,
2052 /* Update the default RSS VNIC(s) */
2053 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2054 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
2056 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
2057 ETH_RSS_LEVEL(rss_conf->rss_hf));
2060 * If hashkey is not specified, use the previously configured
2063 if (!rss_conf->rss_key)
2066 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
2068 "Invalid hashkey length, should be 16 bytes\n");
2071 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
2074 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2078 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
2079 struct rte_eth_rss_conf *rss_conf)
2081 struct bnxt *bp = eth_dev->data->dev_private;
2082 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2084 uint32_t hash_types;
2086 rc = is_bnxt_in_error(bp);
2090 /* RSS configuration is the same for all VNICs */
2091 if (vnic && vnic->rss_hash_key) {
2092 if (rss_conf->rss_key) {
2093 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
2094 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
2095 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
2098 hash_types = vnic->hash_type;
2099 rss_conf->rss_hf = 0;
2100 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
2101 rss_conf->rss_hf |= ETH_RSS_IPV4;
2102 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
2104 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
2105 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2107 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
2109 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
2110 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2112 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
2114 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
2115 rss_conf->rss_hf |= ETH_RSS_IPV6;
2116 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
2118 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
2119 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2121 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
2123 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
2124 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2126 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2130 bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2134 "Unknown RSS config from firmware (%08x), RSS disabled",
2139 rss_conf->rss_hf = 0;
2144 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2145 struct rte_eth_fc_conf *fc_conf)
2147 struct bnxt *bp = dev->data->dev_private;
2148 struct rte_eth_link link_info;
2151 rc = is_bnxt_in_error(bp);
2155 rc = bnxt_get_hwrm_link_config(bp, &link_info);
2159 memset(fc_conf, 0, sizeof(*fc_conf));
2160 if (bp->link_info->auto_pause)
2161 fc_conf->autoneg = 1;
2162 switch (bp->link_info->pause) {
2164 fc_conf->mode = RTE_FC_NONE;
2166 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2167 fc_conf->mode = RTE_FC_TX_PAUSE;
2169 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2170 fc_conf->mode = RTE_FC_RX_PAUSE;
2172 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2173 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2174 fc_conf->mode = RTE_FC_FULL;
2180 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2181 struct rte_eth_fc_conf *fc_conf)
2183 struct bnxt *bp = dev->data->dev_private;
2186 rc = is_bnxt_in_error(bp);
2190 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2191 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2195 switch (fc_conf->mode) {
2197 bp->link_info->auto_pause = 0;
2198 bp->link_info->force_pause = 0;
2200 case RTE_FC_RX_PAUSE:
2201 if (fc_conf->autoneg) {
2202 bp->link_info->auto_pause =
2203 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2204 bp->link_info->force_pause = 0;
2206 bp->link_info->auto_pause = 0;
2207 bp->link_info->force_pause =
2208 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2211 case RTE_FC_TX_PAUSE:
2212 if (fc_conf->autoneg) {
2213 bp->link_info->auto_pause =
2214 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2215 bp->link_info->force_pause = 0;
2217 bp->link_info->auto_pause = 0;
2218 bp->link_info->force_pause =
2219 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2223 if (fc_conf->autoneg) {
2224 bp->link_info->auto_pause =
2225 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2226 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2227 bp->link_info->force_pause = 0;
2229 bp->link_info->auto_pause = 0;
2230 bp->link_info->force_pause =
2231 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2232 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2236 return bnxt_set_hwrm_link_config(bp, true);
2239 /* Add UDP tunneling port */
2241 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2242 struct rte_eth_udp_tunnel *udp_tunnel)
2244 struct bnxt *bp = eth_dev->data->dev_private;
2245 uint16_t tunnel_type = 0;
2248 rc = is_bnxt_in_error(bp);
2252 switch (udp_tunnel->prot_type) {
2253 case RTE_TUNNEL_TYPE_VXLAN:
2254 if (bp->vxlan_port_cnt) {
2255 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2256 udp_tunnel->udp_port);
2257 if (bp->vxlan_port != udp_tunnel->udp_port) {
2258 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2261 bp->vxlan_port_cnt++;
2265 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2266 bp->vxlan_port_cnt++;
2268 case RTE_TUNNEL_TYPE_GENEVE:
2269 if (bp->geneve_port_cnt) {
2270 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2271 udp_tunnel->udp_port);
2272 if (bp->geneve_port != udp_tunnel->udp_port) {
2273 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2276 bp->geneve_port_cnt++;
2280 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2281 bp->geneve_port_cnt++;
2284 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2287 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2293 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2294 struct rte_eth_udp_tunnel *udp_tunnel)
2296 struct bnxt *bp = eth_dev->data->dev_private;
2297 uint16_t tunnel_type = 0;
2301 rc = is_bnxt_in_error(bp);
2305 switch (udp_tunnel->prot_type) {
2306 case RTE_TUNNEL_TYPE_VXLAN:
2307 if (!bp->vxlan_port_cnt) {
2308 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2311 if (bp->vxlan_port != udp_tunnel->udp_port) {
2312 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2313 udp_tunnel->udp_port, bp->vxlan_port);
2316 if (--bp->vxlan_port_cnt)
2320 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2321 port = bp->vxlan_fw_dst_port_id;
2323 case RTE_TUNNEL_TYPE_GENEVE:
2324 if (!bp->geneve_port_cnt) {
2325 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2328 if (bp->geneve_port != udp_tunnel->udp_port) {
2329 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2330 udp_tunnel->udp_port, bp->geneve_port);
2333 if (--bp->geneve_port_cnt)
2337 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2338 port = bp->geneve_fw_dst_port_id;
2341 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2345 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2349 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2351 struct bnxt_filter_info *filter;
2352 struct bnxt_vnic_info *vnic;
2354 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2356 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2357 filter = STAILQ_FIRST(&vnic->filter);
2359 /* Search for this matching MAC+VLAN filter */
2360 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2361 /* Delete the filter */
2362 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2365 STAILQ_REMOVE(&vnic->filter, filter,
2366 bnxt_filter_info, next);
2367 bnxt_free_filter(bp, filter);
2369 "Deleted vlan filter for %d\n",
2373 filter = STAILQ_NEXT(filter, next);
2378 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2380 struct bnxt_filter_info *filter;
2381 struct bnxt_vnic_info *vnic;
2383 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2384 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2385 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2387 /* Implementation notes on the use of VNIC in this command:
2389 * By default, these filters belong to default vnic for the function.
2390 * Once these filters are set up, only destination VNIC can be modified.
2391 * If the destination VNIC is not specified in this command,
2392 * then the HWRM shall only create an l2 context id.
2395 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2396 filter = STAILQ_FIRST(&vnic->filter);
2397 /* Check if the VLAN has already been added */
2399 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2402 filter = STAILQ_NEXT(filter, next);
2405 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2406 * command to create MAC+VLAN filter with the right flags, enables set.
2408 filter = bnxt_alloc_filter(bp);
2411 "MAC/VLAN filter alloc failed\n");
2414 /* MAC + VLAN ID filter */
2415 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2416 * untagged packets are received
2418 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2419 * packets and only the programmed vlan's packets are received
2421 filter->l2_ivlan = vlan_id;
2422 filter->l2_ivlan_mask = 0x0FFF;
2423 filter->enables |= en;
2424 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2426 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2428 /* Free the newly allocated filter as we were
2429 * not able to create the filter in hardware.
2431 bnxt_free_filter(bp, filter);
2435 filter->mac_index = 0;
2436 /* Add this new filter to the list */
2438 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2440 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2443 "Added Vlan filter for %d\n", vlan_id);
2447 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2448 uint16_t vlan_id, int on)
2450 struct bnxt *bp = eth_dev->data->dev_private;
2453 rc = is_bnxt_in_error(bp);
2457 if (!eth_dev->data->dev_started) {
2458 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2462 /* These operations apply to ALL existing MAC/VLAN filters */
2464 return bnxt_add_vlan_filter(bp, vlan_id);
2466 return bnxt_del_vlan_filter(bp, vlan_id);
2469 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2470 struct bnxt_vnic_info *vnic)
2472 struct bnxt_filter_info *filter;
2475 filter = STAILQ_FIRST(&vnic->filter);
2477 if (filter->mac_index == 0 &&
2478 !memcmp(filter->l2_addr, bp->mac_addr,
2479 RTE_ETHER_ADDR_LEN)) {
2480 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2482 STAILQ_REMOVE(&vnic->filter, filter,
2483 bnxt_filter_info, next);
2484 bnxt_free_filter(bp, filter);
2488 filter = STAILQ_NEXT(filter, next);
2494 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2496 struct bnxt_vnic_info *vnic;
2500 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2501 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2502 /* Remove any VLAN filters programmed */
2503 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2504 bnxt_del_vlan_filter(bp, i);
2506 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2510 /* Default filter will allow packets that match the
2511 * dest mac. So, it has to be deleted, otherwise, we
2512 * will endup receiving vlan packets for which the
2513 * filter is not programmed, when hw-vlan-filter
2514 * configuration is ON
2516 bnxt_del_dflt_mac_filter(bp, vnic);
2517 /* This filter will allow only untagged packets */
2518 bnxt_add_vlan_filter(bp, 0);
2520 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2521 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2526 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2528 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2532 /* Destroy vnic filters and vnic */
2533 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2534 DEV_RX_OFFLOAD_VLAN_FILTER) {
2535 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2536 bnxt_del_vlan_filter(bp, i);
2538 bnxt_del_dflt_mac_filter(bp, vnic);
2540 rc = bnxt_hwrm_vnic_ctx_free(bp, vnic);
2544 rc = bnxt_hwrm_vnic_free(bp, vnic);
2548 rte_free(vnic->fw_grp_ids);
2549 vnic->fw_grp_ids = NULL;
2551 vnic->rx_queue_cnt = 0;
2557 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2559 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2562 /* Destroy, recreate and reconfigure the default vnic */
2563 rc = bnxt_free_one_vnic(bp, 0);
2567 /* default vnic 0 */
2568 rc = bnxt_setup_one_vnic(bp, 0);
2572 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2573 DEV_RX_OFFLOAD_VLAN_FILTER) {
2574 rc = bnxt_add_vlan_filter(bp, 0);
2577 rc = bnxt_restore_vlan_filters(bp);
2581 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2586 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2590 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2591 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2597 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2599 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2600 struct bnxt *bp = dev->data->dev_private;
2603 rc = is_bnxt_in_error(bp);
2607 /* Filter settings will get applied when port is started */
2608 if (!dev->data->dev_started)
2611 if (mask & ETH_VLAN_FILTER_MASK) {
2612 /* Enable or disable VLAN filtering */
2613 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2618 if (mask & ETH_VLAN_STRIP_MASK) {
2619 /* Enable or disable VLAN stripping */
2620 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2625 if (mask & ETH_VLAN_EXTEND_MASK) {
2626 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2627 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2629 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2636 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2639 struct bnxt *bp = dev->data->dev_private;
2640 int qinq = dev->data->dev_conf.rxmode.offloads &
2641 DEV_RX_OFFLOAD_VLAN_EXTEND;
2643 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2644 vlan_type != ETH_VLAN_TYPE_OUTER) {
2646 "Unsupported vlan type.");
2651 "QinQ not enabled. Needs to be ON as we can "
2652 "accelerate only outer vlan\n");
2656 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2658 case RTE_ETHER_TYPE_QINQ:
2660 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2662 case RTE_ETHER_TYPE_VLAN:
2664 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2666 case RTE_ETHER_TYPE_QINQ1:
2668 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2670 case RTE_ETHER_TYPE_QINQ2:
2672 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2674 case RTE_ETHER_TYPE_QINQ3:
2676 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2679 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2682 bp->outer_tpid_bd |= tpid;
2683 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2684 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2686 "Can accelerate only outer vlan in QinQ\n");
2694 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2695 struct rte_ether_addr *addr)
2697 struct bnxt *bp = dev->data->dev_private;
2698 /* Default Filter is tied to VNIC 0 */
2699 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2702 rc = is_bnxt_in_error(bp);
2706 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2709 if (rte_is_zero_ether_addr(addr))
2712 /* Filter settings will get applied when port is started */
2713 if (!dev->data->dev_started)
2716 /* Check if the requested MAC is already added */
2717 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2720 /* Destroy filter and re-create it */
2721 bnxt_del_dflt_mac_filter(bp, vnic);
2723 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2724 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2725 /* This filter will allow only untagged packets */
2726 rc = bnxt_add_vlan_filter(bp, 0);
2728 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2731 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2736 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2737 struct rte_ether_addr *mc_addr_set,
2738 uint32_t nb_mc_addr)
2740 struct bnxt *bp = eth_dev->data->dev_private;
2741 char *mc_addr_list = (char *)mc_addr_set;
2742 struct bnxt_vnic_info *vnic;
2743 uint32_t off = 0, i = 0;
2746 rc = is_bnxt_in_error(bp);
2750 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2752 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2753 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2757 /* TODO Check for Duplicate mcast addresses */
2758 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2759 for (i = 0; i < nb_mc_addr; i++) {
2760 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2761 RTE_ETHER_ADDR_LEN);
2762 off += RTE_ETHER_ADDR_LEN;
2765 vnic->mc_addr_cnt = i;
2766 if (vnic->mc_addr_cnt)
2767 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2769 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2772 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2776 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2778 struct bnxt *bp = dev->data->dev_private;
2779 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2780 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2781 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2782 uint8_t fw_rsvd = bp->fw_ver & 0xff;
2785 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2786 fw_major, fw_minor, fw_updt, fw_rsvd);
2788 ret += 1; /* add the size of '\0' */
2789 if (fw_size < (uint32_t)ret)
2796 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2797 struct rte_eth_rxq_info *qinfo)
2799 struct bnxt *bp = dev->data->dev_private;
2800 struct bnxt_rx_queue *rxq;
2802 if (is_bnxt_in_error(bp))
2805 rxq = dev->data->rx_queues[queue_id];
2807 qinfo->mp = rxq->mb_pool;
2808 qinfo->scattered_rx = dev->data->scattered_rx;
2809 qinfo->nb_desc = rxq->nb_rx_desc;
2811 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2812 qinfo->conf.rx_drop_en = rxq->drop_en;
2813 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2814 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2818 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2819 struct rte_eth_txq_info *qinfo)
2821 struct bnxt *bp = dev->data->dev_private;
2822 struct bnxt_tx_queue *txq;
2824 if (is_bnxt_in_error(bp))
2827 txq = dev->data->tx_queues[queue_id];
2829 qinfo->nb_desc = txq->nb_tx_desc;
2831 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2832 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2833 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2835 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2836 qinfo->conf.tx_rs_thresh = 0;
2837 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2838 qinfo->conf.offloads = txq->offloads;
2841 static const struct {
2842 eth_rx_burst_t pkt_burst;
2844 } bnxt_rx_burst_info[] = {
2845 {bnxt_recv_pkts, "Scalar"},
2846 #if defined(RTE_ARCH_X86)
2847 {bnxt_recv_pkts_vec, "Vector SSE"},
2848 #elif defined(RTE_ARCH_ARM64)
2849 {bnxt_recv_pkts_vec, "Vector Neon"},
2854 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2855 struct rte_eth_burst_mode *mode)
2857 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2860 for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2861 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2862 snprintf(mode->info, sizeof(mode->info), "%s",
2863 bnxt_rx_burst_info[i].info);
2871 static const struct {
2872 eth_tx_burst_t pkt_burst;
2874 } bnxt_tx_burst_info[] = {
2875 {bnxt_xmit_pkts, "Scalar"},
2876 #if defined(RTE_ARCH_X86)
2877 {bnxt_xmit_pkts_vec, "Vector SSE"},
2878 #elif defined(RTE_ARCH_ARM64)
2879 {bnxt_xmit_pkts_vec, "Vector Neon"},
2884 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2885 struct rte_eth_burst_mode *mode)
2887 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2890 for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2891 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2892 snprintf(mode->info, sizeof(mode->info), "%s",
2893 bnxt_tx_burst_info[i].info);
2901 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2903 struct bnxt *bp = eth_dev->data->dev_private;
2904 uint32_t new_pkt_size;
2908 rc = is_bnxt_in_error(bp);
2912 /* Exit if receive queues are not configured yet */
2913 if (!eth_dev->data->nb_rx_queues)
2916 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2917 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2920 * Disallow any MTU change that would require scattered receive support
2921 * if it is not already enabled.
2923 if (eth_dev->data->dev_started &&
2924 !eth_dev->data->scattered_rx &&
2926 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2928 "MTU change would require scattered rx support. ");
2929 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2933 if (new_mtu > RTE_ETHER_MTU) {
2934 bp->flags |= BNXT_FLAG_JUMBO;
2935 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2936 DEV_RX_OFFLOAD_JUMBO_FRAME;
2938 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2939 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2940 bp->flags &= ~BNXT_FLAG_JUMBO;
2943 /* Is there a change in mtu setting? */
2944 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2947 for (i = 0; i < bp->nr_vnics; i++) {
2948 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2951 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2952 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2956 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2957 size -= RTE_PKTMBUF_HEADROOM;
2959 if (size < new_mtu) {
2960 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2967 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2969 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2975 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2977 struct bnxt *bp = dev->data->dev_private;
2978 uint16_t vlan = bp->vlan;
2981 rc = is_bnxt_in_error(bp);
2985 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2987 "PVID cannot be modified for this function\n");
2990 bp->vlan = on ? pvid : 0;
2992 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2999 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
3001 struct bnxt *bp = dev->data->dev_private;
3004 rc = is_bnxt_in_error(bp);
3008 return bnxt_hwrm_port_led_cfg(bp, true);
3012 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
3014 struct bnxt *bp = dev->data->dev_private;
3017 rc = is_bnxt_in_error(bp);
3021 return bnxt_hwrm_port_led_cfg(bp, false);
3025 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3027 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
3028 struct bnxt_cp_ring_info *cpr;
3029 uint32_t desc = 0, raw_cons;
3030 struct bnxt_rx_queue *rxq;
3031 struct rx_pkt_cmpl *rxcmp;
3034 rc = is_bnxt_in_error(bp);
3038 rxq = dev->data->rx_queues[rx_queue_id];
3040 raw_cons = cpr->cp_raw_cons;
3043 uint32_t agg_cnt, cons, cmpl_type;
3045 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3046 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3048 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3051 cmpl_type = CMP_TYPE(rxcmp);
3053 switch (cmpl_type) {
3054 case CMPL_BASE_TYPE_RX_L2:
3055 case CMPL_BASE_TYPE_RX_L2_V2:
3056 agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3057 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3061 case CMPL_BASE_TYPE_RX_TPA_END:
3062 if (BNXT_CHIP_P5(rxq->bp)) {
3063 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3065 p5_tpa_end = (void *)rxcmp;
3066 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3068 struct rx_tpa_end_cmpl *tpa_end;
3070 tpa_end = (void *)rxcmp;
3071 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3074 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3079 raw_cons += CMP_LEN(cmpl_type);
3087 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
3089 struct bnxt_rx_queue *rxq = rx_queue;
3090 struct bnxt_cp_ring_info *cpr;
3091 struct bnxt_rx_ring_info *rxr;
3092 uint32_t desc, raw_cons;
3093 struct bnxt *bp = rxq->bp;
3094 struct rx_pkt_cmpl *rxcmp;
3097 rc = is_bnxt_in_error(bp);
3101 if (offset >= rxq->nb_rx_desc)
3108 * For the vector receive case, the completion at the requested
3109 * offset can be indexed directly.
3111 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
3112 if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) {
3113 struct rx_pkt_cmpl *rxcmp;
3116 /* Check status of completion descriptor. */
3117 raw_cons = cpr->cp_raw_cons +
3118 offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2);
3119 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3120 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3122 if (CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3123 return RTE_ETH_RX_DESC_DONE;
3125 /* Check whether rx desc has an mbuf attached. */
3126 cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2);
3127 if (cons >= rxq->rxrearm_start &&
3128 cons < rxq->rxrearm_start + rxq->rxrearm_nb) {
3129 return RTE_ETH_RX_DESC_UNAVAIL;
3132 return RTE_ETH_RX_DESC_AVAIL;
3137 * For the non-vector receive case, scan the completion ring to
3138 * locate the completion descriptor for the requested offset.
3140 raw_cons = cpr->cp_raw_cons;
3143 uint32_t agg_cnt, cons, cmpl_type;
3145 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3146 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3148 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3151 cmpl_type = CMP_TYPE(rxcmp);
3153 switch (cmpl_type) {
3154 case CMPL_BASE_TYPE_RX_L2:
3155 case CMPL_BASE_TYPE_RX_L2_V2:
3156 if (desc == offset) {
3157 cons = rxcmp->opaque;
3158 if (rxr->rx_buf_ring[cons])
3159 return RTE_ETH_RX_DESC_DONE;
3161 return RTE_ETH_RX_DESC_UNAVAIL;
3163 agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3164 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3168 case CMPL_BASE_TYPE_RX_TPA_END:
3170 return RTE_ETH_RX_DESC_DONE;
3172 if (BNXT_CHIP_P5(rxq->bp)) {
3173 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3175 p5_tpa_end = (void *)rxcmp;
3176 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3178 struct rx_tpa_end_cmpl *tpa_end;
3180 tpa_end = (void *)rxcmp;
3181 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3184 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3189 raw_cons += CMP_LEN(cmpl_type);
3193 return RTE_ETH_RX_DESC_AVAIL;
3197 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
3199 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
3200 struct bnxt_tx_ring_info *txr;
3201 struct bnxt_cp_ring_info *cpr;
3202 struct rte_mbuf **tx_buf;
3203 struct tx_pkt_cmpl *txcmp;
3204 uint32_t cons, cp_cons;
3210 rc = is_bnxt_in_error(txq->bp);
3217 if (offset >= txq->nb_tx_desc)
3220 cons = RING_CMP(cpr->cp_ring_struct, offset);
3221 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3222 cp_cons = cpr->cp_raw_cons;
3224 if (cons > cp_cons) {
3225 if (CMPL_VALID(txcmp, cpr->valid))
3226 return RTE_ETH_TX_DESC_UNAVAIL;
3228 if (CMPL_VALID(txcmp, !cpr->valid))
3229 return RTE_ETH_TX_DESC_UNAVAIL;
3231 tx_buf = &txr->tx_buf_ring[cons];
3232 if (*tx_buf == NULL)
3233 return RTE_ETH_TX_DESC_DONE;
3235 return RTE_ETH_TX_DESC_FULL;
3239 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3240 enum rte_filter_type filter_type,
3241 enum rte_filter_op filter_op, void *arg)
3243 struct bnxt *bp = dev->data->dev_private;
3249 if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3250 struct bnxt_representor *vfr = dev->data->dev_private;
3251 bp = vfr->parent_dev->data->dev_private;
3252 /* parent is deleted while children are still valid */
3254 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n",
3262 ret = is_bnxt_in_error(bp);
3266 switch (filter_type) {
3267 case RTE_ETH_FILTER_GENERIC:
3268 if (filter_op != RTE_ETH_FILTER_GET)
3271 /* PMD supports thread-safe flow operations. rte_flow API
3272 * functions can avoid mutex for multi-thread safety.
3274 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3276 if (BNXT_TRUFLOW_EN(bp))
3277 *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3279 *(const void **)arg = &bnxt_flow_ops;
3283 "Filter type (%d) not supported", filter_type);
3290 static const uint32_t *
3291 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3293 static const uint32_t ptypes[] = {
3294 RTE_PTYPE_L2_ETHER_VLAN,
3295 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3296 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3300 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3301 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3302 RTE_PTYPE_INNER_L4_ICMP,
3303 RTE_PTYPE_INNER_L4_TCP,
3304 RTE_PTYPE_INNER_L4_UDP,
3308 if (!dev->rx_pkt_burst)
3314 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3317 uint32_t reg_base = *reg_arr & 0xfffff000;
3321 for (i = 0; i < count; i++) {
3322 if ((reg_arr[i] & 0xfffff000) != reg_base)
3325 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3326 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3330 static int bnxt_map_ptp_regs(struct bnxt *bp)
3332 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3336 reg_arr = ptp->rx_regs;
3337 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3341 reg_arr = ptp->tx_regs;
3342 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3346 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3347 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3349 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3350 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3355 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3357 rte_write32(0, (uint8_t *)bp->bar0 +
3358 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3359 rte_write32(0, (uint8_t *)bp->bar0 +
3360 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3363 static uint64_t bnxt_cc_read(struct bnxt *bp)
3367 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3368 BNXT_GRCPF_REG_SYNC_TIME));
3369 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3370 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3374 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3376 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3379 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3380 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3381 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3384 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3385 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3386 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3387 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3388 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3389 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3390 rte_read32((uint8_t *)bp->bar0 + ptp->tx_mapped_regs[BNXT_PTP_TX_SEQ]);
3395 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3397 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3398 struct bnxt_pf_info *pf = bp->pf;
3405 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3406 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3407 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3410 port_id = pf->port_id;
3411 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3412 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3414 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3415 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3416 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3417 /* bnxt_clr_rx_ts(bp); TBD */
3421 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3422 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3423 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3424 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3430 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3433 struct bnxt *bp = dev->data->dev_private;
3434 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3439 ns = rte_timespec_to_ns(ts);
3440 /* Set the timecounters to a new value. */
3442 ptp->tx_tstamp_tc.nsec = ns;
3443 ptp->rx_tstamp_tc.nsec = ns;
3449 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3451 struct bnxt *bp = dev->data->dev_private;
3452 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3453 uint64_t ns, systime_cycles = 0;
3459 if (BNXT_CHIP_P5(bp))
3460 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3463 systime_cycles = bnxt_cc_read(bp);
3465 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3466 *ts = rte_ns_to_timespec(ns);
3471 bnxt_timesync_enable(struct rte_eth_dev *dev)
3473 struct bnxt *bp = dev->data->dev_private;
3474 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3482 ptp->tx_tstamp_en = 1;
3483 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3485 rc = bnxt_hwrm_ptp_cfg(bp);
3489 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3490 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3491 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3493 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3494 ptp->tc.cc_shift = shift;
3495 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3497 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3498 ptp->rx_tstamp_tc.cc_shift = shift;
3499 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3501 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3502 ptp->tx_tstamp_tc.cc_shift = shift;
3503 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3505 if (!BNXT_CHIP_P5(bp))
3506 bnxt_map_ptp_regs(bp);
3508 rc = bnxt_ptp_start(bp);
3514 bnxt_timesync_disable(struct rte_eth_dev *dev)
3516 struct bnxt *bp = dev->data->dev_private;
3517 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3523 ptp->tx_tstamp_en = 0;
3526 bnxt_hwrm_ptp_cfg(bp);
3528 if (!BNXT_CHIP_P5(bp))
3529 bnxt_unmap_ptp_regs(bp);
3537 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3538 struct timespec *timestamp,
3539 uint32_t flags __rte_unused)
3541 struct bnxt *bp = dev->data->dev_private;
3542 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3543 uint64_t rx_tstamp_cycles = 0;
3549 if (BNXT_CHIP_P5(bp))
3550 rx_tstamp_cycles = ptp->rx_timestamp;
3552 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3554 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3555 *timestamp = rte_ns_to_timespec(ns);
3560 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3561 struct timespec *timestamp)
3563 struct bnxt *bp = dev->data->dev_private;
3564 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3565 uint64_t tx_tstamp_cycles = 0;
3572 if (BNXT_CHIP_P5(bp))
3573 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3576 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3578 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3579 *timestamp = rte_ns_to_timespec(ns);
3585 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3587 struct bnxt *bp = dev->data->dev_private;
3588 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3593 ptp->tc.nsec += delta;
3594 ptp->tx_tstamp_tc.nsec += delta;
3595 ptp->rx_tstamp_tc.nsec += delta;
3601 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3603 struct bnxt *bp = dev->data->dev_private;
3605 uint32_t dir_entries;
3606 uint32_t entry_length;
3608 rc = is_bnxt_in_error(bp);
3612 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3613 bp->pdev->addr.domain, bp->pdev->addr.bus,
3614 bp->pdev->addr.devid, bp->pdev->addr.function);
3616 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3620 return dir_entries * entry_length;
3624 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3625 struct rte_dev_eeprom_info *in_eeprom)
3627 struct bnxt *bp = dev->data->dev_private;
3632 rc = is_bnxt_in_error(bp);
3636 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3637 bp->pdev->addr.domain, bp->pdev->addr.bus,
3638 bp->pdev->addr.devid, bp->pdev->addr.function,
3639 in_eeprom->offset, in_eeprom->length);
3641 if (in_eeprom->offset == 0) /* special offset value to get directory */
3642 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3645 index = in_eeprom->offset >> 24;
3646 offset = in_eeprom->offset & 0xffffff;
3649 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3650 in_eeprom->length, in_eeprom->data);
3655 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3658 case BNX_DIR_TYPE_CHIMP_PATCH:
3659 case BNX_DIR_TYPE_BOOTCODE:
3660 case BNX_DIR_TYPE_BOOTCODE_2:
3661 case BNX_DIR_TYPE_APE_FW:
3662 case BNX_DIR_TYPE_APE_PATCH:
3663 case BNX_DIR_TYPE_KONG_FW:
3664 case BNX_DIR_TYPE_KONG_PATCH:
3665 case BNX_DIR_TYPE_BONO_FW:
3666 case BNX_DIR_TYPE_BONO_PATCH:
3674 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3677 case BNX_DIR_TYPE_AVS:
3678 case BNX_DIR_TYPE_EXP_ROM_MBA:
3679 case BNX_DIR_TYPE_PCIE:
3680 case BNX_DIR_TYPE_TSCF_UCODE:
3681 case BNX_DIR_TYPE_EXT_PHY:
3682 case BNX_DIR_TYPE_CCM:
3683 case BNX_DIR_TYPE_ISCSI_BOOT:
3684 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3685 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3693 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3695 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3696 bnxt_dir_type_is_other_exec_format(dir_type);
3700 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3701 struct rte_dev_eeprom_info *in_eeprom)
3703 struct bnxt *bp = dev->data->dev_private;
3704 uint8_t index, dir_op;
3705 uint16_t type, ext, ordinal, attr;
3708 rc = is_bnxt_in_error(bp);
3712 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3713 bp->pdev->addr.domain, bp->pdev->addr.bus,
3714 bp->pdev->addr.devid, bp->pdev->addr.function,
3715 in_eeprom->offset, in_eeprom->length);
3718 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3722 type = in_eeprom->magic >> 16;
3724 if (type == 0xffff) { /* special value for directory operations */
3725 index = in_eeprom->magic & 0xff;
3726 dir_op = in_eeprom->magic >> 8;
3730 case 0x0e: /* erase */
3731 if (in_eeprom->offset != ~in_eeprom->magic)
3733 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3739 /* Create or re-write an NVM item: */
3740 if (bnxt_dir_type_is_executable(type) == true)
3742 ext = in_eeprom->magic & 0xffff;
3743 ordinal = in_eeprom->offset >> 16;
3744 attr = in_eeprom->offset & 0xffff;
3746 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3747 in_eeprom->data, in_eeprom->length);
3754 static const struct eth_dev_ops bnxt_dev_ops = {
3755 .dev_infos_get = bnxt_dev_info_get_op,
3756 .dev_close = bnxt_dev_close_op,
3757 .dev_configure = bnxt_dev_configure_op,
3758 .dev_start = bnxt_dev_start_op,
3759 .dev_stop = bnxt_dev_stop_op,
3760 .dev_set_link_up = bnxt_dev_set_link_up_op,
3761 .dev_set_link_down = bnxt_dev_set_link_down_op,
3762 .stats_get = bnxt_stats_get_op,
3763 .stats_reset = bnxt_stats_reset_op,
3764 .rx_queue_setup = bnxt_rx_queue_setup_op,
3765 .rx_queue_release = bnxt_rx_queue_release_op,
3766 .tx_queue_setup = bnxt_tx_queue_setup_op,
3767 .tx_queue_release = bnxt_tx_queue_release_op,
3768 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3769 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3770 .reta_update = bnxt_reta_update_op,
3771 .reta_query = bnxt_reta_query_op,
3772 .rss_hash_update = bnxt_rss_hash_update_op,
3773 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3774 .link_update = bnxt_link_update_op,
3775 .promiscuous_enable = bnxt_promiscuous_enable_op,
3776 .promiscuous_disable = bnxt_promiscuous_disable_op,
3777 .allmulticast_enable = bnxt_allmulticast_enable_op,
3778 .allmulticast_disable = bnxt_allmulticast_disable_op,
3779 .mac_addr_add = bnxt_mac_addr_add_op,
3780 .mac_addr_remove = bnxt_mac_addr_remove_op,
3781 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3782 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3783 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3784 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3785 .vlan_filter_set = bnxt_vlan_filter_set_op,
3786 .vlan_offload_set = bnxt_vlan_offload_set_op,
3787 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3788 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3789 .mtu_set = bnxt_mtu_set_op,
3790 .mac_addr_set = bnxt_set_default_mac_addr_op,
3791 .xstats_get = bnxt_dev_xstats_get_op,
3792 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3793 .xstats_reset = bnxt_dev_xstats_reset_op,
3794 .fw_version_get = bnxt_fw_version_get,
3795 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3796 .rxq_info_get = bnxt_rxq_info_get_op,
3797 .txq_info_get = bnxt_txq_info_get_op,
3798 .rx_burst_mode_get = bnxt_rx_burst_mode_get,
3799 .tx_burst_mode_get = bnxt_tx_burst_mode_get,
3800 .dev_led_on = bnxt_dev_led_on_op,
3801 .dev_led_off = bnxt_dev_led_off_op,
3802 .rx_queue_start = bnxt_rx_queue_start,
3803 .rx_queue_stop = bnxt_rx_queue_stop,
3804 .tx_queue_start = bnxt_tx_queue_start,
3805 .tx_queue_stop = bnxt_tx_queue_stop,
3806 .filter_ctrl = bnxt_filter_ctrl_op,
3807 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3808 .get_eeprom_length = bnxt_get_eeprom_length_op,
3809 .get_eeprom = bnxt_get_eeprom_op,
3810 .set_eeprom = bnxt_set_eeprom_op,
3811 .timesync_enable = bnxt_timesync_enable,
3812 .timesync_disable = bnxt_timesync_disable,
3813 .timesync_read_time = bnxt_timesync_read_time,
3814 .timesync_write_time = bnxt_timesync_write_time,
3815 .timesync_adjust_time = bnxt_timesync_adjust_time,
3816 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3817 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3820 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3824 /* Only pre-map the reset GRC registers using window 3 */
3825 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3826 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3828 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3833 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3835 struct bnxt_error_recovery_info *info = bp->recovery_info;
3836 uint32_t reg_base = 0xffffffff;
3839 /* Only pre-map the monitoring GRC registers using window 2 */
3840 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3841 uint32_t reg = info->status_regs[i];
3843 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3846 if (reg_base == 0xffffffff)
3847 reg_base = reg & 0xfffff000;
3848 if ((reg & 0xfffff000) != reg_base)
3851 /* Use mask 0xffc as the Lower 2 bits indicates
3852 * address space location
3854 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3858 if (reg_base == 0xffffffff)
3861 rte_write32(reg_base, (uint8_t *)bp->bar0 +
3862 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3867 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3869 struct bnxt_error_recovery_info *info = bp->recovery_info;
3870 uint32_t delay = info->delay_after_reset[index];
3871 uint32_t val = info->reset_reg_val[index];
3872 uint32_t reg = info->reset_reg[index];
3873 uint32_t type, offset;
3876 type = BNXT_FW_STATUS_REG_TYPE(reg);
3877 offset = BNXT_FW_STATUS_REG_OFF(reg);
3880 case BNXT_FW_STATUS_REG_TYPE_CFG:
3881 ret = rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3883 PMD_DRV_LOG(ERR, "Failed to write %#x at PCI offset %#x",
3888 case BNXT_FW_STATUS_REG_TYPE_GRC:
3889 offset = bnxt_map_reset_regs(bp, offset);
3890 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3892 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3893 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3896 /* wait on a specific interval of time until core reset is complete */
3898 rte_delay_ms(delay);
3901 static void bnxt_dev_cleanup(struct bnxt *bp)
3903 bp->eth_dev->data->dev_link.link_status = 0;
3904 bp->link_info->link_up = 0;
3905 if (bp->eth_dev->data->dev_started)
3906 bnxt_dev_stop(bp->eth_dev);
3908 bnxt_uninit_resources(bp, true);
3912 bnxt_check_fw_reset_done(struct bnxt *bp)
3914 int timeout = bp->fw_reset_max_msecs;
3919 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
3921 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
3927 } while (timeout--);
3929 if (val == 0xffff) {
3930 PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n");
3937 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3939 struct rte_eth_dev *dev = bp->eth_dev;
3940 struct rte_vlan_filter_conf *vfc;
3944 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3945 vfc = &dev->data->vlan_filter_conf;
3946 vidx = vlan_id / 64;
3947 vbit = vlan_id % 64;
3949 /* Each bit corresponds to a VLAN id */
3950 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3951 rc = bnxt_add_vlan_filter(bp, vlan_id);
3960 static int bnxt_restore_mac_filters(struct bnxt *bp)
3962 struct rte_eth_dev *dev = bp->eth_dev;
3963 struct rte_eth_dev_info dev_info;
3964 struct rte_ether_addr *addr;
3970 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3973 rc = bnxt_dev_info_get_op(dev, &dev_info);
3977 /* replay MAC address configuration */
3978 for (i = 1; i < dev_info.max_mac_addrs; i++) {
3979 addr = &dev->data->mac_addrs[i];
3981 /* skip zero address */
3982 if (rte_is_zero_ether_addr(addr))
3986 pool_mask = dev->data->mac_pool_sel[i];
3989 if (pool_mask & 1ULL) {
3990 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3996 } while (pool_mask);
4002 static int bnxt_restore_filters(struct bnxt *bp)
4004 struct rte_eth_dev *dev = bp->eth_dev;
4007 if (dev->data->all_multicast) {
4008 ret = bnxt_allmulticast_enable_op(dev);
4012 if (dev->data->promiscuous) {
4013 ret = bnxt_promiscuous_enable_op(dev);
4018 ret = bnxt_restore_mac_filters(bp);
4022 ret = bnxt_restore_vlan_filters(bp);
4023 /* TODO restore other filters as well */
4027 static int bnxt_check_fw_ready(struct bnxt *bp)
4029 int timeout = bp->fw_reset_max_msecs;
4033 rc = bnxt_hwrm_poll_ver_get(bp);
4036 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4037 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4038 } while (rc && timeout > 0);
4041 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4046 static void bnxt_dev_recover(void *arg)
4048 struct bnxt *bp = arg;
4051 pthread_mutex_lock(&bp->err_recovery_lock);
4053 if (!bp->fw_reset_min_msecs) {
4054 rc = bnxt_check_fw_reset_done(bp);
4059 /* Clear Error flag so that device re-init should happen */
4060 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4062 rc = bnxt_check_fw_ready(bp);
4066 rc = bnxt_init_resources(bp, true);
4069 "Failed to initialize resources after reset\n");
4072 /* clear reset flag as the device is initialized now */
4073 bp->flags &= ~BNXT_FLAG_FW_RESET;
4075 rc = bnxt_dev_start_op(bp->eth_dev);
4077 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4081 rc = bnxt_restore_filters(bp);
4085 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4086 pthread_mutex_unlock(&bp->err_recovery_lock);
4090 bnxt_dev_stop(bp->eth_dev);
4092 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4093 bnxt_uninit_resources(bp, false);
4094 pthread_mutex_unlock(&bp->err_recovery_lock);
4095 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4098 void bnxt_dev_reset_and_resume(void *arg)
4100 struct bnxt *bp = arg;
4101 uint32_t us = US_PER_MS * bp->fw_reset_min_msecs;
4105 bnxt_dev_cleanup(bp);
4107 bnxt_wait_for_device_shutdown(bp);
4109 /* During some fatal firmware error conditions, the PCI config space
4110 * register 0x2e which normally contains the subsystem ID will become
4111 * 0xffff. This register will revert back to the normal value after
4112 * the chip has completed core reset. If we detect this condition,
4113 * we can poll this config register immediately for the value to revert.
4115 if (bp->flags & BNXT_FLAG_FATAL_ERROR) {
4116 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4118 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4121 if (val == 0xffff) {
4122 bp->fw_reset_min_msecs = 0;
4127 rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp);
4129 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4132 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4134 struct bnxt_error_recovery_info *info = bp->recovery_info;
4135 uint32_t reg = info->status_regs[index];
4136 uint32_t type, offset, val = 0;
4138 type = BNXT_FW_STATUS_REG_TYPE(reg);
4139 offset = BNXT_FW_STATUS_REG_OFF(reg);
4142 case BNXT_FW_STATUS_REG_TYPE_CFG:
4143 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4145 case BNXT_FW_STATUS_REG_TYPE_GRC:
4146 offset = info->mapped_status_regs[index];
4148 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4149 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4157 static int bnxt_fw_reset_all(struct bnxt *bp)
4159 struct bnxt_error_recovery_info *info = bp->recovery_info;
4163 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4164 /* Reset through master function driver */
4165 for (i = 0; i < info->reg_array_cnt; i++)
4166 bnxt_write_fw_reset_reg(bp, i);
4167 /* Wait for time specified by FW after triggering reset */
4168 rte_delay_ms(info->master_func_wait_period_after_reset);
4169 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4170 /* Reset with the help of Kong processor */
4171 rc = bnxt_hwrm_fw_reset(bp);
4173 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4179 static void bnxt_fw_reset_cb(void *arg)
4181 struct bnxt *bp = arg;
4182 struct bnxt_error_recovery_info *info = bp->recovery_info;
4185 /* Only Master function can do FW reset */
4186 if (bnxt_is_master_func(bp) &&
4187 bnxt_is_recovery_enabled(bp)) {
4188 rc = bnxt_fw_reset_all(bp);
4190 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4195 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4196 * EXCEPTION_FATAL_ASYNC event to all the functions
4197 * (including MASTER FUNC). After receiving this Async, all the active
4198 * drivers should treat this case as FW initiated recovery
4200 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4201 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4202 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4204 /* To recover from error */
4205 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4210 /* Driver should poll FW heartbeat, reset_counter with the frequency
4211 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4212 * When the driver detects heartbeat stop or change in reset_counter,
4213 * it has to trigger a reset to recover from the error condition.
4214 * A “master PF” is the function who will have the privilege to
4215 * initiate the chimp reset. The master PF will be elected by the
4216 * firmware and will be notified through async message.
4218 static void bnxt_check_fw_health(void *arg)
4220 struct bnxt *bp = arg;
4221 struct bnxt_error_recovery_info *info = bp->recovery_info;
4222 uint32_t val = 0, wait_msec;
4224 if (!info || !bnxt_is_recovery_enabled(bp) ||
4225 is_bnxt_in_error(bp))
4228 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4229 if (val == info->last_heart_beat)
4232 info->last_heart_beat = val;
4234 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4235 if (val != info->last_reset_counter)
4238 info->last_reset_counter = val;
4240 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4241 bnxt_check_fw_health, (void *)bp);
4245 /* Stop DMA to/from device */
4246 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4247 bp->flags |= BNXT_FLAG_FW_RESET;
4249 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4251 if (bnxt_is_master_func(bp))
4252 wait_msec = info->master_func_wait_period;
4254 wait_msec = info->normal_func_wait_period;
4256 rte_eal_alarm_set(US_PER_MS * wait_msec,
4257 bnxt_fw_reset_cb, (void *)bp);
4260 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4262 uint32_t polling_freq;
4264 pthread_mutex_lock(&bp->health_check_lock);
4266 if (!bnxt_is_recovery_enabled(bp))
4269 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4272 polling_freq = bp->recovery_info->driver_polling_freq;
4274 rte_eal_alarm_set(US_PER_MS * polling_freq,
4275 bnxt_check_fw_health, (void *)bp);
4276 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4279 pthread_mutex_unlock(&bp->health_check_lock);
4282 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4284 if (!bnxt_is_recovery_enabled(bp))
4287 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4288 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4291 static bool bnxt_vf_pciid(uint16_t device_id)
4293 switch (device_id) {
4294 case BROADCOM_DEV_ID_57304_VF:
4295 case BROADCOM_DEV_ID_57406_VF:
4296 case BROADCOM_DEV_ID_5731X_VF:
4297 case BROADCOM_DEV_ID_5741X_VF:
4298 case BROADCOM_DEV_ID_57414_VF:
4299 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4300 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4301 case BROADCOM_DEV_ID_58802_VF:
4302 case BROADCOM_DEV_ID_57500_VF1:
4303 case BROADCOM_DEV_ID_57500_VF2:
4304 case BROADCOM_DEV_ID_58818_VF:
4312 /* Phase 5 device */
4313 static bool bnxt_p5_device(uint16_t device_id)
4315 switch (device_id) {
4316 case BROADCOM_DEV_ID_57508:
4317 case BROADCOM_DEV_ID_57504:
4318 case BROADCOM_DEV_ID_57502:
4319 case BROADCOM_DEV_ID_57508_MF1:
4320 case BROADCOM_DEV_ID_57504_MF1:
4321 case BROADCOM_DEV_ID_57502_MF1:
4322 case BROADCOM_DEV_ID_57508_MF2:
4323 case BROADCOM_DEV_ID_57504_MF2:
4324 case BROADCOM_DEV_ID_57502_MF2:
4325 case BROADCOM_DEV_ID_57500_VF1:
4326 case BROADCOM_DEV_ID_57500_VF2:
4327 case BROADCOM_DEV_ID_58812:
4328 case BROADCOM_DEV_ID_58814:
4329 case BROADCOM_DEV_ID_58818:
4330 case BROADCOM_DEV_ID_58818_VF:
4338 bool bnxt_stratus_device(struct bnxt *bp)
4340 uint16_t device_id = bp->pdev->id.device_id;
4342 switch (device_id) {
4343 case BROADCOM_DEV_ID_STRATUS_NIC:
4344 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4345 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4353 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev)
4355 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4356 struct bnxt *bp = eth_dev->data->dev_private;
4358 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4359 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4360 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4361 if (!bp->bar0 || !bp->doorbell_base) {
4362 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4366 bp->eth_dev = eth_dev;
4372 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4373 struct bnxt_ctx_pg_info *ctx_pg,
4378 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4379 const struct rte_memzone *mz = NULL;
4380 char mz_name[RTE_MEMZONE_NAMESIZE];
4381 rte_iova_t mz_phys_addr;
4382 uint64_t valid_bits = 0;
4389 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4391 rmem->page_size = BNXT_PAGE_SIZE;
4392 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4393 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4394 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4396 valid_bits = PTU_PTE_VALID;
4398 if (rmem->nr_pages > 1) {
4399 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4400 "bnxt_ctx_pg_tbl%s_%x_%d",
4401 suffix, idx, bp->eth_dev->data->port_id);
4402 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4403 mz = rte_memzone_lookup(mz_name);
4405 mz = rte_memzone_reserve_aligned(mz_name,
4409 RTE_MEMZONE_SIZE_HINT_ONLY |
4410 RTE_MEMZONE_IOVA_CONTIG,
4416 memset(mz->addr, 0, mz->len);
4417 mz_phys_addr = mz->iova;
4419 rmem->pg_tbl = mz->addr;
4420 rmem->pg_tbl_map = mz_phys_addr;
4421 rmem->pg_tbl_mz = mz;
4424 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4425 suffix, idx, bp->eth_dev->data->port_id);
4426 mz = rte_memzone_lookup(mz_name);
4428 mz = rte_memzone_reserve_aligned(mz_name,
4432 RTE_MEMZONE_SIZE_HINT_ONLY |
4433 RTE_MEMZONE_IOVA_CONTIG,
4439 memset(mz->addr, 0, mz->len);
4440 mz_phys_addr = mz->iova;
4442 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4443 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4444 rmem->dma_arr[i] = mz_phys_addr + sz;
4446 if (rmem->nr_pages > 1) {
4447 if (i == rmem->nr_pages - 2 &&
4448 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4449 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4450 else if (i == rmem->nr_pages - 1 &&
4451 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4452 valid_bits |= PTU_PTE_LAST;
4454 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4460 if (rmem->vmem_size)
4461 rmem->vmem = (void **)mz->addr;
4462 rmem->dma_arr[0] = mz_phys_addr;
4466 static void bnxt_free_ctx_mem(struct bnxt *bp)
4470 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4473 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4474 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4475 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4476 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4477 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4478 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4479 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4480 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4481 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4482 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4483 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4485 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4486 if (bp->ctx->tqm_mem[i])
4487 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4494 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4496 #define min_t(type, x, y) ({ \
4497 type __min1 = (x); \
4498 type __min2 = (y); \
4499 __min1 < __min2 ? __min1 : __min2; })
4501 #define max_t(type, x, y) ({ \
4502 type __max1 = (x); \
4503 type __max2 = (y); \
4504 __max1 > __max2 ? __max1 : __max2; })
4506 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4508 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4510 struct bnxt_ctx_pg_info *ctx_pg;
4511 struct bnxt_ctx_mem_info *ctx;
4512 uint32_t mem_size, ena, entries;
4513 uint32_t entries_sp, min;
4516 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4518 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4522 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4525 ctx_pg = &ctx->qp_mem;
4526 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4527 if (ctx->qp_entry_size) {
4528 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4529 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4534 ctx_pg = &ctx->srq_mem;
4535 ctx_pg->entries = ctx->srq_max_l2_entries;
4536 if (ctx->srq_entry_size) {
4537 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4538 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4543 ctx_pg = &ctx->cq_mem;
4544 ctx_pg->entries = ctx->cq_max_l2_entries;
4545 if (ctx->cq_entry_size) {
4546 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4547 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4552 ctx_pg = &ctx->vnic_mem;
4553 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4554 ctx->vnic_max_ring_table_entries;
4555 if (ctx->vnic_entry_size) {
4556 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4557 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4562 ctx_pg = &ctx->stat_mem;
4563 ctx_pg->entries = ctx->stat_max_entries;
4564 if (ctx->stat_entry_size) {
4565 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4566 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4571 min = ctx->tqm_min_entries_per_ring;
4573 entries_sp = ctx->qp_max_l2_entries +
4574 ctx->vnic_max_vnic_entries +
4575 2 * ctx->qp_min_qp1_entries + min;
4576 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4578 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4579 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4580 entries = clamp_t(uint32_t, entries, min,
4581 ctx->tqm_max_entries_per_ring);
4582 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4583 /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7.
4584 * i > 8 is other ext rings.
4586 ctx_pg = ctx->tqm_mem[i];
4587 ctx_pg->entries = i ? entries : entries_sp;
4588 if (ctx->tqm_entry_size) {
4589 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4590 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size,
4595 if (i < BNXT_MAX_TQM_LEGACY_RINGS)
4596 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4598 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8;
4601 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4602 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4605 "Failed to configure context mem: rc = %d\n", rc);
4607 ctx->flags |= BNXT_CTX_FLAG_INITED;
4612 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4614 struct rte_pci_device *pci_dev = bp->pdev;
4615 char mz_name[RTE_MEMZONE_NAMESIZE];
4616 const struct rte_memzone *mz = NULL;
4617 uint32_t total_alloc_len;
4618 rte_iova_t mz_phys_addr;
4620 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4623 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4624 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4625 pci_dev->addr.bus, pci_dev->addr.devid,
4626 pci_dev->addr.function, "rx_port_stats");
4627 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4628 mz = rte_memzone_lookup(mz_name);
4630 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4631 sizeof(struct rx_port_stats_ext) + 512);
4633 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4636 RTE_MEMZONE_SIZE_HINT_ONLY |
4637 RTE_MEMZONE_IOVA_CONTIG);
4641 memset(mz->addr, 0, mz->len);
4642 mz_phys_addr = mz->iova;
4644 bp->rx_mem_zone = (const void *)mz;
4645 bp->hw_rx_port_stats = mz->addr;
4646 bp->hw_rx_port_stats_map = mz_phys_addr;
4648 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4649 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4650 pci_dev->addr.bus, pci_dev->addr.devid,
4651 pci_dev->addr.function, "tx_port_stats");
4652 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4653 mz = rte_memzone_lookup(mz_name);
4655 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4656 sizeof(struct tx_port_stats_ext) + 512);
4658 mz = rte_memzone_reserve(mz_name,
4662 RTE_MEMZONE_SIZE_HINT_ONLY |
4663 RTE_MEMZONE_IOVA_CONTIG);
4667 memset(mz->addr, 0, mz->len);
4668 mz_phys_addr = mz->iova;
4670 bp->tx_mem_zone = (const void *)mz;
4671 bp->hw_tx_port_stats = mz->addr;
4672 bp->hw_tx_port_stats_map = mz_phys_addr;
4673 bp->flags |= BNXT_FLAG_PORT_STATS;
4675 /* Display extended statistics if FW supports it */
4676 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4677 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4678 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4681 bp->hw_rx_port_stats_ext = (void *)
4682 ((uint8_t *)bp->hw_rx_port_stats +
4683 sizeof(struct rx_port_stats));
4684 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4685 sizeof(struct rx_port_stats);
4686 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4688 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4689 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4690 bp->hw_tx_port_stats_ext = (void *)
4691 ((uint8_t *)bp->hw_tx_port_stats +
4692 sizeof(struct tx_port_stats));
4693 bp->hw_tx_port_stats_ext_map =
4694 bp->hw_tx_port_stats_map +
4695 sizeof(struct tx_port_stats);
4696 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4702 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4704 struct bnxt *bp = eth_dev->data->dev_private;
4707 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4708 RTE_ETHER_ADDR_LEN *
4711 if (eth_dev->data->mac_addrs == NULL) {
4712 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4716 if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4720 /* Generate a random MAC address, if none was assigned by PF */
4721 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4722 bnxt_eth_hw_addr_random(bp->mac_addr);
4724 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4725 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4726 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4728 rc = bnxt_hwrm_set_mac(bp);
4733 /* Copy the permanent MAC from the FUNC_QCAPS response */
4734 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4739 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4743 /* MAC is already configured in FW */
4744 if (BNXT_HAS_DFLT_MAC_SET(bp))
4747 /* Restore the old MAC configured */
4748 rc = bnxt_hwrm_set_mac(bp);
4750 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4755 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4760 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
4762 if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
4763 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
4764 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
4765 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
4766 BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
4767 BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
4771 bnxt_get_svif(uint16_t port_id, bool func_svif,
4772 enum bnxt_ulp_intf_type type)
4774 struct rte_eth_dev *eth_dev;
4777 eth_dev = &rte_eth_devices[port_id];
4778 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4779 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4783 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4786 eth_dev = vfr->parent_dev;
4789 bp = eth_dev->data->dev_private;
4791 return func_svif ? bp->func_svif : bp->port_svif;
4795 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
4797 struct rte_eth_dev *eth_dev;
4798 struct bnxt_vnic_info *vnic;
4801 eth_dev = &rte_eth_devices[port];
4802 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4803 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4807 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4808 return vfr->dflt_vnic_id;
4810 eth_dev = vfr->parent_dev;
4813 bp = eth_dev->data->dev_private;
4815 vnic = BNXT_GET_DEFAULT_VNIC(bp);
4817 return vnic->fw_vnic_id;
4821 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
4823 struct rte_eth_dev *eth_dev;
4826 eth_dev = &rte_eth_devices[port];
4827 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4828 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4832 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4835 eth_dev = vfr->parent_dev;
4838 bp = eth_dev->data->dev_private;
4843 enum bnxt_ulp_intf_type
4844 bnxt_get_interface_type(uint16_t port)
4846 struct rte_eth_dev *eth_dev;
4849 eth_dev = &rte_eth_devices[port];
4850 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
4851 return BNXT_ULP_INTF_TYPE_VF_REP;
4853 bp = eth_dev->data->dev_private;
4855 return BNXT_ULP_INTF_TYPE_PF;
4856 else if (BNXT_VF_IS_TRUSTED(bp))
4857 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
4858 else if (BNXT_VF(bp))
4859 return BNXT_ULP_INTF_TYPE_VF;
4861 return BNXT_ULP_INTF_TYPE_INVALID;
4865 bnxt_get_phy_port_id(uint16_t port_id)
4867 struct bnxt_representor *vfr;
4868 struct rte_eth_dev *eth_dev;
4871 eth_dev = &rte_eth_devices[port_id];
4872 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4873 vfr = eth_dev->data->dev_private;
4877 eth_dev = vfr->parent_dev;
4880 bp = eth_dev->data->dev_private;
4882 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
4886 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
4888 struct rte_eth_dev *eth_dev;
4891 eth_dev = &rte_eth_devices[port_id];
4892 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4893 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4897 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4898 return vfr->fw_fid - 1;
4900 eth_dev = vfr->parent_dev;
4903 bp = eth_dev->data->dev_private;
4905 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
4909 bnxt_get_vport(uint16_t port_id)
4911 return (1 << bnxt_get_phy_port_id(port_id));
4914 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
4916 struct bnxt_error_recovery_info *info = bp->recovery_info;
4919 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
4920 memset(info, 0, sizeof(*info));
4924 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4927 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4930 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4932 bp->recovery_info = info;
4935 static void bnxt_check_fw_status(struct bnxt *bp)
4939 if (!(bp->recovery_info &&
4940 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
4943 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
4944 if (fw_status != BNXT_FW_STATUS_HEALTHY)
4945 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
4949 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
4951 struct bnxt_error_recovery_info *info = bp->recovery_info;
4952 uint32_t status_loc;
4955 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
4956 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4957 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4958 BNXT_GRCP_WINDOW_2_BASE +
4959 offsetof(struct hcomm_status,
4961 /* If the signature is absent, then FW does not support this feature */
4962 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
4963 HCOMM_STATUS_SIGNATURE_VAL)
4967 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4971 bp->recovery_info = info;
4973 memset(info, 0, sizeof(*info));
4976 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4977 BNXT_GRCP_WINDOW_2_BASE +
4978 offsetof(struct hcomm_status,
4981 /* Only pre-map the FW health status GRC register */
4982 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
4985 info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
4986 info->mapped_status_regs[BNXT_FW_STATUS_REG] =
4987 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
4989 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
4990 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4992 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
4997 /* This function gets the FW version along with the
4998 * capabilities(MAX and current) of the function, vnic,
4999 * error recovery, phy and other chip related info
5001 static int bnxt_get_config(struct bnxt *bp)
5008 rc = bnxt_map_hcomm_fw_status_reg(bp);
5012 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5014 bnxt_check_fw_status(bp);
5018 rc = bnxt_hwrm_func_reset(bp);
5022 rc = bnxt_hwrm_vnic_qcaps(bp);
5026 rc = bnxt_hwrm_queue_qportcfg(bp);
5030 /* Get the MAX capabilities for this function.
5031 * This function also allocates context memory for TQM rings and
5032 * informs the firmware about this allocated backing store memory.
5034 rc = bnxt_hwrm_func_qcaps(bp);
5038 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5042 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5046 bnxt_hwrm_port_mac_qcfg(bp);
5048 bnxt_hwrm_parent_pf_qcfg(bp);
5050 bnxt_hwrm_port_phy_qcaps(bp);
5052 bnxt_alloc_error_recovery_info(bp);
5053 /* Get the adapter error recovery support info */
5054 rc = bnxt_hwrm_error_recovery_qcfg(bp);
5056 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5058 bnxt_hwrm_port_led_qcaps(bp);
5064 bnxt_init_locks(struct bnxt *bp)
5068 err = pthread_mutex_init(&bp->flow_lock, NULL);
5070 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5074 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5076 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5080 err = pthread_mutex_init(&bp->health_check_lock, NULL);
5082 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5086 err = pthread_mutex_init(&bp->err_recovery_lock, NULL);
5088 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n");
5093 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5097 rc = bnxt_get_config(bp);
5101 if (!reconfig_dev) {
5102 rc = bnxt_setup_mac_addr(bp->eth_dev);
5106 rc = bnxt_restore_dflt_mac(bp);
5111 bnxt_config_vf_req_fwd(bp);
5113 rc = bnxt_hwrm_func_driver_register(bp);
5115 PMD_DRV_LOG(ERR, "Failed to register driver");
5120 if (bp->pdev->max_vfs) {
5121 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5123 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5127 rc = bnxt_hwrm_allocate_pf_only(bp);
5130 "Failed to allocate PF resources");
5136 rc = bnxt_alloc_mem(bp, reconfig_dev);
5140 rc = bnxt_setup_int(bp);
5144 rc = bnxt_request_int(bp);
5148 rc = bnxt_init_ctx_mem(bp);
5150 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5158 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5159 const char *value, void *opaque_arg)
5161 struct bnxt *bp = opaque_arg;
5162 unsigned long truflow;
5165 if (!value || !opaque_arg) {
5167 "Invalid parameter passed to truflow devargs.\n");
5171 truflow = strtoul(value, &end, 10);
5172 if (end == NULL || *end != '\0' ||
5173 (truflow == ULONG_MAX && errno == ERANGE)) {
5175 "Invalid parameter passed to truflow devargs.\n");
5179 if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5181 "Invalid value passed to truflow devargs.\n");
5186 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5187 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5189 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
5190 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
5197 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5198 const char *value, void *opaque_arg)
5200 struct bnxt *bp = opaque_arg;
5201 unsigned long flow_xstat;
5204 if (!value || !opaque_arg) {
5206 "Invalid parameter passed to flow_xstat devarg.\n");
5210 flow_xstat = strtoul(value, &end, 10);
5211 if (end == NULL || *end != '\0' ||
5212 (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5214 "Invalid parameter passed to flow_xstat devarg.\n");
5218 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5220 "Invalid value passed to flow_xstat devarg.\n");
5224 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5225 if (BNXT_FLOW_XSTATS_EN(bp))
5226 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5232 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5233 const char *value, void *opaque_arg)
5235 struct bnxt *bp = opaque_arg;
5236 unsigned long max_num_kflows;
5239 if (!value || !opaque_arg) {
5241 "Invalid parameter passed to max_num_kflows devarg.\n");
5245 max_num_kflows = strtoul(value, &end, 10);
5246 if (end == NULL || *end != '\0' ||
5247 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5249 "Invalid parameter passed to max_num_kflows devarg.\n");
5253 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5255 "Invalid value passed to max_num_kflows devarg.\n");
5259 bp->max_num_kflows = max_num_kflows;
5260 if (bp->max_num_kflows)
5261 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5268 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5269 const char *value, void *opaque_arg)
5271 struct bnxt_representor *vfr_bp = opaque_arg;
5272 unsigned long rep_is_pf;
5275 if (!value || !opaque_arg) {
5277 "Invalid parameter passed to rep_is_pf devargs.\n");
5281 rep_is_pf = strtoul(value, &end, 10);
5282 if (end == NULL || *end != '\0' ||
5283 (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5285 "Invalid parameter passed to rep_is_pf devargs.\n");
5289 if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5291 "Invalid value passed to rep_is_pf devargs.\n");
5295 vfr_bp->flags |= rep_is_pf;
5296 if (BNXT_REP_PF(vfr_bp))
5297 PMD_DRV_LOG(INFO, "PF representor\n");
5299 PMD_DRV_LOG(INFO, "VF representor\n");
5305 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5306 const char *value, void *opaque_arg)
5308 struct bnxt_representor *vfr_bp = opaque_arg;
5309 unsigned long rep_based_pf;
5312 if (!value || !opaque_arg) {
5314 "Invalid parameter passed to rep_based_pf "
5319 rep_based_pf = strtoul(value, &end, 10);
5320 if (end == NULL || *end != '\0' ||
5321 (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5323 "Invalid parameter passed to rep_based_pf "
5328 if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5330 "Invalid value passed to rep_based_pf devargs.\n");
5334 vfr_bp->rep_based_pf = rep_based_pf;
5335 vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
5337 PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5343 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5344 const char *value, void *opaque_arg)
5346 struct bnxt_representor *vfr_bp = opaque_arg;
5347 unsigned long rep_q_r2f;
5350 if (!value || !opaque_arg) {
5352 "Invalid parameter passed to rep_q_r2f "
5357 rep_q_r2f = strtoul(value, &end, 10);
5358 if (end == NULL || *end != '\0' ||
5359 (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5361 "Invalid parameter passed to rep_q_r2f "
5366 if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5368 "Invalid value passed to rep_q_r2f devargs.\n");
5372 vfr_bp->rep_q_r2f = rep_q_r2f;
5373 vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5374 PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5380 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5381 const char *value, void *opaque_arg)
5383 struct bnxt_representor *vfr_bp = opaque_arg;
5384 unsigned long rep_q_f2r;
5387 if (!value || !opaque_arg) {
5389 "Invalid parameter passed to rep_q_f2r "
5394 rep_q_f2r = strtoul(value, &end, 10);
5395 if (end == NULL || *end != '\0' ||
5396 (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5398 "Invalid parameter passed to rep_q_f2r "
5403 if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5405 "Invalid value passed to rep_q_f2r devargs.\n");
5409 vfr_bp->rep_q_f2r = rep_q_f2r;
5410 vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5411 PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5417 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5418 const char *value, void *opaque_arg)
5420 struct bnxt_representor *vfr_bp = opaque_arg;
5421 unsigned long rep_fc_r2f;
5424 if (!value || !opaque_arg) {
5426 "Invalid parameter passed to rep_fc_r2f "
5431 rep_fc_r2f = strtoul(value, &end, 10);
5432 if (end == NULL || *end != '\0' ||
5433 (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5435 "Invalid parameter passed to rep_fc_r2f "
5440 if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5442 "Invalid value passed to rep_fc_r2f devargs.\n");
5446 vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5447 vfr_bp->rep_fc_r2f = rep_fc_r2f;
5448 PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5454 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5455 const char *value, void *opaque_arg)
5457 struct bnxt_representor *vfr_bp = opaque_arg;
5458 unsigned long rep_fc_f2r;
5461 if (!value || !opaque_arg) {
5463 "Invalid parameter passed to rep_fc_f2r "
5468 rep_fc_f2r = strtoul(value, &end, 10);
5469 if (end == NULL || *end != '\0' ||
5470 (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5472 "Invalid parameter passed to rep_fc_f2r "
5477 if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5479 "Invalid value passed to rep_fc_f2r devargs.\n");
5483 vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5484 vfr_bp->rep_fc_f2r = rep_fc_f2r;
5485 PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5491 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5493 struct rte_kvargs *kvlist;
5495 if (devargs == NULL)
5498 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5503 * Handler for "truflow" devarg.
5504 * Invoked as for ex: "-a 0000:00:0d.0,host-based-truflow=1"
5506 rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5507 bnxt_parse_devarg_truflow, bp);
5510 * Handler for "flow_xstat" devarg.
5511 * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5513 rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5514 bnxt_parse_devarg_flow_xstat, bp);
5517 * Handler for "max_num_kflows" devarg.
5518 * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5520 rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5521 bnxt_parse_devarg_max_num_kflows, bp);
5523 rte_kvargs_free(kvlist);
5526 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5530 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5531 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5534 "Failed to alloc switch domain: %d\n", rc);
5537 "Switch domain allocated %d\n",
5538 bp->switch_domain_id);
5544 /* Allocate and initialize various fields in bnxt struct that
5545 * need to be allocated/destroyed only once in the lifetime of the driver
5547 static int bnxt_drv_init(struct rte_eth_dev *eth_dev)
5549 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5550 struct bnxt *bp = eth_dev->data->dev_private;
5553 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5555 if (bnxt_vf_pciid(pci_dev->id.device_id))
5556 bp->flags |= BNXT_FLAG_VF;
5558 if (bnxt_p5_device(pci_dev->id.device_id))
5559 bp->flags |= BNXT_FLAG_CHIP_P5;
5561 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5562 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5563 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5564 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5565 bp->flags |= BNXT_FLAG_STINGRAY;
5567 if (BNXT_TRUFLOW_EN(bp)) {
5568 /* extra mbuf field is required to store CFA code from mark */
5569 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5570 .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5571 .size = sizeof(bnxt_cfa_code_dynfield_t),
5572 .align = __alignof__(bnxt_cfa_code_dynfield_t),
5574 bnxt_cfa_code_dynfield_offset =
5575 rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5576 if (bnxt_cfa_code_dynfield_offset < 0) {
5578 "Failed to register mbuf field for TruFlow mark\n");
5583 rc = bnxt_map_pci_bars(eth_dev);
5586 "Failed to initialize board rc: %x\n", rc);
5590 rc = bnxt_alloc_pf_info(bp);
5594 rc = bnxt_alloc_link_info(bp);
5598 rc = bnxt_alloc_parent_info(bp);
5602 rc = bnxt_alloc_hwrm_resources(bp);
5605 "Failed to allocate hwrm resource rc: %x\n", rc);
5608 rc = bnxt_alloc_leds_info(bp);
5612 rc = bnxt_alloc_cos_queues(bp);
5616 rc = bnxt_init_locks(bp);
5620 rc = bnxt_alloc_switch_domain(bp);
5628 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5630 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5631 static int version_printed;
5635 if (version_printed++ == 0)
5636 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5638 eth_dev->dev_ops = &bnxt_dev_ops;
5639 eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5640 eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5641 eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5642 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5643 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5646 * For secondary processes, we don't initialise any further
5647 * as primary has already done this work.
5649 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5652 rte_eth_copy_pci_info(eth_dev, pci_dev);
5653 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
5655 bp = eth_dev->data->dev_private;
5657 /* Parse dev arguments passed on when starting the DPDK application. */
5658 bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5660 rc = bnxt_drv_init(eth_dev);
5664 rc = bnxt_init_resources(bp, false);
5668 rc = bnxt_alloc_stats_mem(bp);
5673 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5674 pci_dev->mem_resource[0].phys_addr,
5675 pci_dev->mem_resource[0].addr);
5680 bnxt_dev_uninit(eth_dev);
5685 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5694 ctx->dma = RTE_BAD_IOVA;
5695 ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5698 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5700 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5701 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5702 bp->flow_stat->rx_fc_out_tbl.ctx_id,
5703 bp->flow_stat->max_fc,
5706 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5707 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5708 bp->flow_stat->tx_fc_out_tbl.ctx_id,
5709 bp->flow_stat->max_fc,
5712 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5713 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5714 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5716 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5717 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5718 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5720 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5721 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5722 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5724 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5725 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5726 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5729 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5731 bnxt_unregister_fc_ctx_mem(bp);
5733 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5734 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5735 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5736 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5739 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5741 if (BNXT_FLOW_XSTATS_EN(bp))
5742 bnxt_uninit_fc_ctx_mem(bp);
5746 bnxt_free_error_recovery_info(struct bnxt *bp)
5748 rte_free(bp->recovery_info);
5749 bp->recovery_info = NULL;
5750 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5754 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5759 bnxt_free_mem(bp, reconfig_dev);
5761 bnxt_hwrm_func_buf_unrgtr(bp);
5762 rte_free(bp->pf->vf_req_buf);
5764 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5765 bp->flags &= ~BNXT_FLAG_REGISTERED;
5766 bnxt_free_ctx_mem(bp);
5767 if (!reconfig_dev) {
5768 bnxt_free_hwrm_resources(bp);
5769 bnxt_free_error_recovery_info(bp);
5772 bnxt_uninit_ctx_mem(bp);
5774 bnxt_free_flow_stats_info(bp);
5775 bnxt_free_rep_info(bp);
5776 rte_free(bp->ptp_cfg);
5782 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5784 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5787 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5789 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5790 bnxt_dev_close_op(eth_dev);
5795 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5797 struct bnxt *bp = eth_dev->data->dev_private;
5798 struct rte_eth_dev *vf_rep_eth_dev;
5804 for (i = 0; i < bp->num_reps; i++) {
5805 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5806 if (!vf_rep_eth_dev)
5808 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
5809 vf_rep_eth_dev->data->port_id);
5810 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
5812 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
5813 eth_dev->data->port_id);
5814 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5819 static void bnxt_free_rep_info(struct bnxt *bp)
5821 rte_free(bp->rep_info);
5822 bp->rep_info = NULL;
5823 rte_free(bp->cfa_code_map);
5824 bp->cfa_code_map = NULL;
5827 static int bnxt_init_rep_info(struct bnxt *bp)
5834 bp->rep_info = rte_zmalloc("bnxt_rep_info",
5835 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5837 if (!bp->rep_info) {
5838 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5841 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5842 sizeof(*bp->cfa_code_map) *
5843 BNXT_MAX_CFA_CODE, 0);
5844 if (!bp->cfa_code_map) {
5845 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5846 bnxt_free_rep_info(bp);
5850 for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5851 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5853 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5855 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5856 bnxt_free_rep_info(bp);
5860 rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
5862 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
5863 bnxt_free_rep_info(bp);
5870 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5871 struct rte_eth_devargs *eth_da,
5872 struct rte_eth_dev *backing_eth_dev,
5873 const char *dev_args)
5875 struct rte_eth_dev *vf_rep_eth_dev;
5876 char name[RTE_ETH_NAME_MAX_LEN];
5877 struct bnxt *backing_bp;
5880 struct rte_kvargs *kvlist = NULL;
5882 if (eth_da->type == RTE_ETH_REPRESENTOR_NONE)
5884 if (eth_da->type != RTE_ETH_REPRESENTOR_VF) {
5885 PMD_DRV_LOG(ERR, "unsupported representor type %d\n",
5889 num_rep = eth_da->nb_representor_ports;
5890 if (num_rep > BNXT_MAX_VF_REPS) {
5891 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5892 num_rep, BNXT_MAX_VF_REPS);
5896 if (num_rep >= RTE_MAX_ETHPORTS) {
5898 "nb_representor_ports = %d > %d MAX ETHPORTS\n",
5899 num_rep, RTE_MAX_ETHPORTS);
5903 backing_bp = backing_eth_dev->data->dev_private;
5905 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
5907 "Not a PF or trusted VF. No Representor support\n");
5908 /* Returning an error is not an option.
5909 * Applications are not handling this correctly
5914 if (bnxt_init_rep_info(backing_bp))
5917 for (i = 0; i < num_rep; i++) {
5918 struct bnxt_representor representor = {
5919 .vf_id = eth_da->representor_ports[i],
5920 .switch_domain_id = backing_bp->switch_domain_id,
5921 .parent_dev = backing_eth_dev
5924 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
5925 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
5926 representor.vf_id, BNXT_MAX_VF_REPS);
5930 /* representor port net_bdf_port */
5931 snprintf(name, sizeof(name), "net_%s_representor_%d",
5932 pci_dev->device.name, eth_da->representor_ports[i]);
5934 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
5937 * Handler for "rep_is_pf" devarg.
5938 * Invoked as for ex: "-a 000:00:0d.0,
5939 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5941 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
5942 bnxt_parse_devarg_rep_is_pf,
5943 (void *)&representor);
5949 * Handler for "rep_based_pf" devarg.
5950 * Invoked as for ex: "-a 000:00:0d.0,
5951 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5953 ret = rte_kvargs_process(kvlist,
5954 BNXT_DEVARG_REP_BASED_PF,
5955 bnxt_parse_devarg_rep_based_pf,
5956 (void *)&representor);
5962 * Handler for "rep_based_pf" devarg.
5963 * Invoked as for ex: "-a 000:00:0d.0,
5964 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5966 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
5967 bnxt_parse_devarg_rep_q_r2f,
5968 (void *)&representor);
5974 * Handler for "rep_based_pf" devarg.
5975 * Invoked as for ex: "-a 000:00:0d.0,
5976 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5978 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
5979 bnxt_parse_devarg_rep_q_f2r,
5980 (void *)&representor);
5986 * Handler for "rep_based_pf" devarg.
5987 * Invoked as for ex: "-a 000:00:0d.0,
5988 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5990 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
5991 bnxt_parse_devarg_rep_fc_r2f,
5992 (void *)&representor);
5998 * Handler for "rep_based_pf" devarg.
5999 * Invoked as for ex: "-a 000:00:0d.0,
6000 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6002 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
6003 bnxt_parse_devarg_rep_fc_f2r,
6004 (void *)&representor);
6011 ret = rte_eth_dev_create(&pci_dev->device, name,
6012 sizeof(struct bnxt_representor),
6014 bnxt_representor_init,
6017 PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6018 "representor %s.", name);
6022 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6023 if (!vf_rep_eth_dev) {
6024 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6025 " for VF-Rep: %s.", name);
6030 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6031 backing_eth_dev->data->port_id);
6032 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6034 backing_bp->num_reps++;
6038 rte_kvargs_free(kvlist);
6042 /* If num_rep > 1, then rollback already created
6043 * ports, since we'll be failing the probe anyway
6046 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6048 rte_kvargs_free(kvlist);
6053 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6054 struct rte_pci_device *pci_dev)
6056 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6057 struct rte_eth_dev *backing_eth_dev;
6061 if (pci_dev->device.devargs) {
6062 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6068 num_rep = eth_da.nb_representor_ports;
6069 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6072 /* We could come here after first level of probe is already invoked
6073 * as part of an application bringup(OVS-DPDK vswitchd), so first check
6074 * for already allocated eth_dev for the backing device (PF/Trusted VF)
6076 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6077 if (backing_eth_dev == NULL) {
6078 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6079 sizeof(struct bnxt),
6080 eth_dev_pci_specific_init, pci_dev,
6081 bnxt_dev_init, NULL);
6083 if (ret || !num_rep)
6086 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6088 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6089 backing_eth_dev->data->port_id);
6094 /* probe representor ports now */
6095 ret = bnxt_rep_port_probe(pci_dev, ð_da, backing_eth_dev,
6096 pci_dev->device.devargs->args);
6101 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6103 struct rte_eth_dev *eth_dev;
6105 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6107 return 0; /* Invoked typically only by OVS-DPDK, by the
6108 * time it comes here the eth_dev is already
6109 * deleted by rte_eth_dev_close(), so returning
6110 * +ve value will at least help in proper cleanup
6113 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6114 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6115 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6116 return rte_eth_dev_destroy(eth_dev,
6117 bnxt_representor_uninit);
6119 return rte_eth_dev_destroy(eth_dev,
6122 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6126 static struct rte_pci_driver bnxt_rte_pmd = {
6127 .id_table = bnxt_pci_id_map,
6128 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6129 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6132 .probe = bnxt_pci_probe,
6133 .remove = bnxt_pci_remove,
6137 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6139 if (strcmp(dev->device->driver->name, drv->driver.name))
6145 bool is_bnxt_supported(struct rte_eth_dev *dev)
6147 return is_device_supported(dev, &bnxt_rte_pmd);
6150 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
6151 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6152 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6153 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");