drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_irq.h"
  20 #include "bnxt_ring.h"
  21 #include "bnxt_rxq.h"
  22 #include "bnxt_rxr.h"
  23 #include "bnxt_stats.h"
  24 #include "bnxt_txq.h"
  25 #include "bnxt_txr.h"
  26 #include "bnxt_vnic.h"
  27 #include "hsi_struct_def_dpdk.h"
  28 #include "bnxt_nvm_defs.h"
  29 #include "bnxt_util.h"
  30
  31 #define DRV_MODULE_NAME         "bnxt"
  32 static const char bnxt_version[] =
  33         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  34 int bnxt_logtype_driver;
  35
  36 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  37
  38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  40 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
  41 #define BROADCOM_DEV_ID_57414_VF 0x16c1
  42 #define BROADCOM_DEV_ID_57301 0x16c8
  43 #define BROADCOM_DEV_ID_57302 0x16c9
  44 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  45 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  46 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  47 #define BROADCOM_DEV_ID_NS2 0x16cd
  48 #define BROADCOM_DEV_ID_57311 0x16ce
  49 #define BROADCOM_DEV_ID_57312 0x16cf
  50 #define BROADCOM_DEV_ID_57402 0x16d0
  51 #define BROADCOM_DEV_ID_57404 0x16d1
  52 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  53 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  54 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  55 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  56 #define BROADCOM_DEV_ID_57412 0x16d6
  57 #define BROADCOM_DEV_ID_57414 0x16d7
  58 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  59 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  60 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  61 #define BROADCOM_DEV_ID_57412_MF 0x16de
  62 #define BROADCOM_DEV_ID_57314 0x16df
  63 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  64 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  65 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  66 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  67 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  68 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  69 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  70 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  71 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  72 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  73 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  74 #define BROADCOM_DEV_ID_57508 0x1750
  75 #define BROADCOM_DEV_ID_57504 0x1751
  76 #define BROADCOM_DEV_ID_57502 0x1752
  77 #define BROADCOM_DEV_ID_57500_VF1 0x1806
  78 #define BROADCOM_DEV_ID_57500_VF2 0x1807
  79 #define BROADCOM_DEV_ID_58802 0xd802
  80 #define BROADCOM_DEV_ID_58804 0xd804
  81 #define BROADCOM_DEV_ID_58808 0x16f0
  82 #define BROADCOM_DEV_ID_58802_VF 0xd800
  83
  84 static const struct rte_pci_id bnxt_pci_id_map[] = {
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  86                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  88                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
 100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
 102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 119         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 121         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 122         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 123         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
 124         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
 125         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
 126         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
 127         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
 128         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
 129         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
 130         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
 131         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
 132         { .vendor_id = 0, /* sentinel */ },
 133 };
 134
 135 #define BNXT_ETH_RSS_SUPPORT (  \
 136         ETH_RSS_IPV4 |          \
 137         ETH_RSS_NONFRAG_IPV4_TCP |      \
 138         ETH_RSS_NONFRAG_IPV4_UDP |      \
 139         ETH_RSS_IPV6 |          \
 140         ETH_RSS_NONFRAG_IPV6_TCP |      \
 141         ETH_RSS_NONFRAG_IPV6_UDP)
 142
 143 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 144                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 145                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 146                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 147                                      DEV_TX_OFFLOAD_TCP_TSO | \
 148                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 149                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 150                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 151                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 152                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 153                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 154
 155 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 156                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 157                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 158                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 159                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 160                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 161                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 162                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 163                                      DEV_RX_OFFLOAD_TCP_LRO)
 164
 165 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 166 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 167 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 168 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 169
 170 /***********************/
 171
 172 /*
 173  * High level utility functions
 174  */
 175
 176 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 177 {
 178         if (!BNXT_CHIP_THOR(bp))
 179                 return 1;
 180
 181         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 182                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 183                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 184 }
 185
 186 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 187 {
 188         if (!BNXT_CHIP_THOR(bp))
 189                 return HW_HASH_INDEX_SIZE;
 190
 191         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 192 }
 193
 194 static void bnxt_free_mem(struct bnxt *bp)
 195 {
 196         bnxt_free_filter_mem(bp);
 197         bnxt_free_vnic_attributes(bp);
 198         bnxt_free_vnic_mem(bp);
 199
 200         bnxt_free_stats(bp);
 201         bnxt_free_tx_rings(bp);
 202         bnxt_free_rx_rings(bp);
 203 }
 204
 205 static int bnxt_alloc_mem(struct bnxt *bp)
 206 {
 207         int rc;
 208
 209         rc = bnxt_alloc_vnic_mem(bp);
 210         if (rc)
 211                 goto alloc_mem_err;
 212
 213         rc = bnxt_alloc_vnic_attributes(bp);
 214         if (rc)
 215                 goto alloc_mem_err;
 216
 217         rc = bnxt_alloc_filter_mem(bp);
 218         if (rc)
 219                 goto alloc_mem_err;
 220
 221         return 0;
 222
 223 alloc_mem_err:
 224         bnxt_free_mem(bp);
 225         return rc;
 226 }
 227
 228 static int bnxt_init_chip(struct bnxt *bp)
 229 {
 230         struct bnxt_rx_queue *rxq;
 231         struct rte_eth_link new;
 232         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 233         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 234         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 235         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 236         uint32_t intr_vector = 0;
 237         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 238         uint32_t vec = BNXT_MISC_VEC_ID;
 239         unsigned int i, j;
 240         int rc;
 241
 242         /* disable uio/vfio intr/eventfd mapping */
 243         rte_intr_disable(intr_handle);
 244
 245         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 246                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 247                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 248                 bp->flags |= BNXT_FLAG_JUMBO;
 249         } else {
 250                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 251                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 252                 bp->flags &= ~BNXT_FLAG_JUMBO;
 253         }
 254
 255         /* THOR does not support ring groups.
 256          * But we will use the array to save RSS context IDs.
 257          */
 258         if (BNXT_CHIP_THOR(bp))
 259                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 260
 261         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 262         if (rc) {
 263                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 264                 goto err_out;
 265         }
 266
 267         rc = bnxt_alloc_hwrm_rings(bp);
 268         if (rc) {
 269                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 270                 goto err_out;
 271         }
 272
 273         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 274         if (rc) {
 275                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 276                 goto err_out;
 277         }
 278
 279         rc = bnxt_mq_rx_configure(bp);
 280         if (rc) {
 281                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 282                 goto err_out;
 283         }
 284
 285         /* VNIC configuration */
 286         for (i = 0; i < bp->nr_vnics; i++) {
 287                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 288                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 289                 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
 290
 291                 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
 292                 if (!vnic->fw_grp_ids) {
 293                         PMD_DRV_LOG(ERR,
 294                                     "Failed to alloc %d bytes for group ids\n",
 295                                     size);
 296                         rc = -ENOMEM;
 297                         goto err_out;
 298                 }
 299                 memset(vnic->fw_grp_ids, -1, size);
 300
 301                 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 302                             i, vnic, vnic->fw_grp_ids);
 303
 304                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 305                 if (rc) {
 306                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 307                                 i, rc);
 308                         goto err_out;
 309                 }
 310
 311                 /* Alloc RSS context only if RSS mode is enabled */
 312                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 313                         int j, nr_ctxs = bnxt_rss_ctxts(bp);
 314
 315                         rc = 0;
 316                         for (j = 0; j < nr_ctxs; j++) {
 317                                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 318                                 if (rc)
 319                                         break;
 320                         }
 321                         if (rc) {
 322                                 PMD_DRV_LOG(ERR,
 323                                   "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 324                                   i, j, rc);
 325                                 goto err_out;
 326                         }
 327                         vnic->num_lb_ctxts = nr_ctxs;
 328                 }
 329
 330                 /*
 331                  * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 332                  * setting is not available at this time, it will not be
 333                  * configured correctly in the CFA.
 334                  */
 335                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 336                         vnic->vlan_strip = true;
 337                 else
 338                         vnic->vlan_strip = false;
 339
 340                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 341                 if (rc) {
 342                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 343                                 i, rc);
 344                         goto err_out;
 345                 }
 346
 347                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 348                 if (rc) {
 349                         PMD_DRV_LOG(ERR,
 350                                 "HWRM vnic %d filter failure rc: %x\n",
 351                                 i, rc);
 352                         goto err_out;
 353                 }
 354
 355                 for (j = 0; j < bp->rx_nr_rings; j++) {
 356                         rxq = bp->eth_dev->data->rx_queues[j];
 357
 358                         PMD_DRV_LOG(DEBUG,
 359                                     "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 360                                     j, rxq->vnic, rxq->vnic->fw_grp_ids);
 361
 362                         if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 363                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 364                 }
 365
 366                 rc = bnxt_vnic_rss_configure(bp, vnic);
 367                 if (rc) {
 368                         PMD_DRV_LOG(ERR,
 369                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 370                         goto err_out;
 371                 }
 372
 373                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 374
 375                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 376                     DEV_RX_OFFLOAD_TCP_LRO)
 377                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 378                 else
 379                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 380         }
 381         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 382         if (rc) {
 383                 PMD_DRV_LOG(ERR,
 384                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 385                 goto err_out;
 386         }
 387
 388         /* check and configure queue intr-vector mapping */
 389         if ((rte_intr_cap_multiple(intr_handle) ||
 390              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 391             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 392                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 393                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 394                 if (intr_vector > bp->rx_cp_nr_rings) {
 395                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 396                                         bp->rx_cp_nr_rings);
 397                         return -ENOTSUP;
 398                 }
 399                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 400                 if (rc)
 401                         return rc;
 402         }
 403
 404         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 405                 intr_handle->intr_vec =
 406                         rte_zmalloc("intr_vec",
 407                                     bp->eth_dev->data->nb_rx_queues *
 408                                     sizeof(int), 0);
 409                 if (intr_handle->intr_vec == NULL) {
 410                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 411                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 412                         rc = -ENOMEM;
 413                         goto err_disable;
 414                 }
 415                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 416                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 417                          intr_handle->intr_vec, intr_handle->nb_efd,
 418                         intr_handle->max_intr);
 419                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 420                      queue_id++) {
 421                         intr_handle->intr_vec[queue_id] = vec;
 422                         if (vec < base + intr_handle->nb_efd - 1)
 423                                 vec++;
 424                 }
 425         }
 426
 427         /* enable uio/vfio intr/eventfd mapping */
 428         rc = rte_intr_enable(intr_handle);
 429         if (rc)
 430                 goto err_free;
 431
 432         rc = bnxt_get_hwrm_link_config(bp, &new);
 433         if (rc) {
 434                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 435                 goto err_free;
 436         }
 437
 438         if (!bp->link_info.link_up) {
 439                 rc = bnxt_set_hwrm_link_config(bp, true);
 440                 if (rc) {
 441                         PMD_DRV_LOG(ERR,
 442                                 "HWRM link config failure rc: %x\n", rc);
 443                         goto err_free;
 444                 }
 445         }
 446         bnxt_print_link_info(bp->eth_dev);
 447
 448         return 0;
 449
 450 err_free:
 451         rte_free(intr_handle->intr_vec);
 452 err_disable:
 453         rte_intr_efd_disable(intr_handle);
 454 err_out:
 455         /* Some of the error status returned by FW may not be from errno.h */
 456         if (rc > 0)
 457                 rc = -EIO;
 458
 459         return rc;
 460 }
 461
 462 static int bnxt_shutdown_nic(struct bnxt *bp)
 463 {
 464         bnxt_free_all_hwrm_resources(bp);
 465         bnxt_free_all_filters(bp);
 466         bnxt_free_all_vnics(bp);
 467         return 0;
 468 }
 469
 470 static int bnxt_init_nic(struct bnxt *bp)
 471 {
 472         int rc;
 473
 474         if (BNXT_HAS_RING_GRPS(bp)) {
 475                 rc = bnxt_init_ring_grps(bp);
 476                 if (rc)
 477                         return rc;
 478         }
 479
 480         bnxt_init_vnics(bp);
 481         bnxt_init_filters(bp);
 482
 483         return 0;
 484 }
 485
 486 /*
 487  * Device configuration and status function
 488  */
 489
 490 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 491                                   struct rte_eth_dev_info *dev_info)
 492 {
 493         struct bnxt *bp = eth_dev->data->dev_private;
 494         uint16_t max_vnics, i, j, vpool, vrxq;
 495         unsigned int max_rx_rings;
 496
 497         /* MAC Specifics */
 498         dev_info->max_mac_addrs = bp->max_l2_ctx;
 499         dev_info->max_hash_mac_addrs = 0;
 500
 501         /* PF/VF specifics */
 502         if (BNXT_PF(bp))
 503                 dev_info->max_vfs = bp->pdev->max_vfs;
 504         max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
 505         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 506         dev_info->max_rx_queues = max_rx_rings;
 507         dev_info->max_tx_queues = max_rx_rings;
 508         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 509         dev_info->hash_key_size = 40;
 510         max_vnics = bp->max_vnics;
 511
 512         /* Fast path specifics */
 513         dev_info->min_rx_bufsize = 1;
 514         dev_info->max_rx_pktlen = BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +
 515                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
 516
 517         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 518         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 519                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 520         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 521         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 522
 523         /* *INDENT-OFF* */
 524         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 525                 .rx_thresh = {
 526                         .pthresh = 8,
 527                         .hthresh = 8,
 528                         .wthresh = 0,
 529                 },
 530                 .rx_free_thresh = 32,
 531                 /* If no descriptors available, pkts are dropped by default */
 532                 .rx_drop_en = 1,
 533         };
 534
 535         dev_info->default_txconf = (struct rte_eth_txconf) {
 536                 .tx_thresh = {
 537                         .pthresh = 32,
 538                         .hthresh = 0,
 539                         .wthresh = 0,
 540                 },
 541                 .tx_free_thresh = 32,
 542                 .tx_rs_thresh = 32,
 543         };
 544         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 545
 546         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 547         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 548         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 549         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 550         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 551
 552         /* *INDENT-ON* */
 553
 554         /*
 555          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 556          *       need further investigation.
 557          */
 558
 559         /* VMDq resources */
 560         vpool = 64; /* ETH_64_POOLS */
 561         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 562         for (i = 0; i < 4; vpool >>= 1, i++) {
 563                 if (max_vnics > vpool) {
 564                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 565                                 if (dev_info->max_rx_queues > vrxq) {
 566                                         if (vpool > vrxq)
 567                                                 vpool = vrxq;
 568                                         goto found;
 569                                 }
 570                         }
 571                         /* Not enough resources to support VMDq */
 572                         break;
 573                 }
 574         }
 575         /* Not enough resources to support VMDq */
 576         vpool = 0;
 577         vrxq = 0;
 578 found:
 579         dev_info->max_vmdq_pools = vpool;
 580         dev_info->vmdq_queue_num = vrxq;
 581
 582         dev_info->vmdq_pool_base = 0;
 583         dev_info->vmdq_queue_base = 0;
 584 }
 585
 586 /* Configure the device based on the configuration provided */
 587 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 588 {
 589         struct bnxt *bp = eth_dev->data->dev_private;
 590         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 591         int rc;
 592
 593         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 594         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 595         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 596         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 597
 598         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 599                 rc = bnxt_hwrm_check_vf_rings(bp);
 600                 if (rc) {
 601                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 602                         return -ENOSPC;
 603                 }
 604
 605                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 606                 if (rc) {
 607                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 608                         return -ENOSPC;
 609                 }
 610         } else {
 611                 /* legacy driver needs to get updated values */
 612                 rc = bnxt_hwrm_func_qcaps(bp);
 613                 if (rc) {
 614                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 615                         return rc;
 616                 }
 617         }
 618
 619         /* Inherit new configurations */
 620         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 621             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 622             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 623             bp->max_cp_rings ||
 624             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 625             bp->max_stat_ctx)
 626                 goto resource_error;
 627
 628         if (BNXT_HAS_RING_GRPS(bp) &&
 629             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 630                 goto resource_error;
 631
 632         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 633             bp->max_vnics < eth_dev->data->nb_rx_queues)
 634                 goto resource_error;
 635
 636         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 637         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 638
 639         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 640                 eth_dev->data->mtu =
 641                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 642                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 643                         BNXT_NUM_VLANS;
 644                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 645         }
 646         return 0;
 647
 648 resource_error:
 649         PMD_DRV_LOG(ERR,
 650                     "Insufficient resources to support requested config\n");
 651         PMD_DRV_LOG(ERR,
 652                     "Num Queues Requested: Tx %d, Rx %d\n",
 653                     eth_dev->data->nb_tx_queues,
 654                     eth_dev->data->nb_rx_queues);
 655         PMD_DRV_LOG(ERR,
 656                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 657                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 658                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 659         return -ENOSPC;
 660 }
 661
 662 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 663 {
 664         struct rte_eth_link *link = &eth_dev->data->dev_link;
 665
 666         if (link->link_status)
 667                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 668                         eth_dev->data->port_id,
 669                         (uint32_t)link->link_speed,
 670                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 671                         ("full-duplex") : ("half-duplex\n"));
 672         else
 673                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 674                         eth_dev->data->port_id);
 675 }
 676
 677 /*
 678  * Determine whether the current configuration requires support for scattered
 679  * receive; return 1 if scattered receive is required and 0 if not.
 680  */
 681 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 682 {
 683         uint16_t buf_size;
 684         int i;
 685
 686         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 687                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 688
 689                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 690                                       RTE_PKTMBUF_HEADROOM);
 691                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 692                         return 1;
 693         }
 694         return 0;
 695 }
 696
 697 static eth_rx_burst_t
 698 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
 699 {
 700 #ifdef RTE_ARCH_X86
 701         /*
 702          * Vector mode receive can be enabled only if scatter rx is not
 703          * in use and rx offloads are limited to VLAN stripping and
 704          * CRC stripping.
 705          */
 706         if (!eth_dev->data->scattered_rx &&
 707             !(eth_dev->data->dev_conf.rxmode.offloads &
 708               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 709                 DEV_RX_OFFLOAD_KEEP_CRC |
 710                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 711                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 712                 DEV_RX_OFFLOAD_UDP_CKSUM |
 713                 DEV_RX_OFFLOAD_TCP_CKSUM |
 714                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 715                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 716                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 717                             eth_dev->data->port_id);
 718                 return bnxt_recv_pkts_vec;
 719         }
 720         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 721                     eth_dev->data->port_id);
 722         PMD_DRV_LOG(INFO,
 723                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 724                     eth_dev->data->port_id,
 725                     eth_dev->data->scattered_rx,
 726                     eth_dev->data->dev_conf.rxmode.offloads);
 727 #endif
 728         return bnxt_recv_pkts;
 729 }
 730
 731 static eth_tx_burst_t
 732 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 733 {
 734 #ifdef RTE_ARCH_X86
 735         /*
 736          * Vector mode receive can be enabled only if scatter tx is not
 737          * in use and tx offloads other than VLAN insertion are not
 738          * in use.
 739          */
 740         if (!eth_dev->data->scattered_rx &&
 741             !(eth_dev->data->dev_conf.txmode.offloads &
 742               ~DEV_TX_OFFLOAD_VLAN_INSERT)) {
 743                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 744                             eth_dev->data->port_id);
 745                 return bnxt_xmit_pkts_vec;
 746         }
 747         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 748                     eth_dev->data->port_id);
 749         PMD_DRV_LOG(INFO,
 750                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 751                     eth_dev->data->port_id,
 752                     eth_dev->data->scattered_rx,
 753                     eth_dev->data->dev_conf.txmode.offloads);
 754 #endif
 755         return bnxt_xmit_pkts;
 756 }
 757
 758 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 759 {
 760         struct bnxt *bp = eth_dev->data->dev_private;
 761         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 762         int vlan_mask = 0;
 763         int rc;
 764
 765         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 766                 PMD_DRV_LOG(ERR,
 767                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 768                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 769         }
 770
 771         rc = bnxt_init_chip(bp);
 772         if (rc)
 773                 goto error;
 774
 775         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 776
 777         bnxt_link_update_op(eth_dev, 1);
 778
 779         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 780                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 781         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 782                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 783         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 784         if (rc)
 785                 goto error;
 786
 787         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 788         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 789         bnxt_enable_int(bp);
 790         bp->flags |= BNXT_FLAG_INIT_DONE;
 791         bp->dev_stopped = 0;
 792         return 0;
 793
 794 error:
 795         bnxt_shutdown_nic(bp);
 796         bnxt_free_tx_mbufs(bp);
 797         bnxt_free_rx_mbufs(bp);
 798         return rc;
 799 }
 800
 801 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 802 {
 803         struct bnxt *bp = eth_dev->data->dev_private;
 804         int rc = 0;
 805
 806         if (!bp->link_info.link_up)
 807                 rc = bnxt_set_hwrm_link_config(bp, true);
 808         if (!rc)
 809                 eth_dev->data->dev_link.link_status = 1;
 810
 811         bnxt_print_link_info(eth_dev);
 812         return 0;
 813 }
 814
 815 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 816 {
 817         struct bnxt *bp = eth_dev->data->dev_private;
 818
 819         eth_dev->data->dev_link.link_status = 0;
 820         bnxt_set_hwrm_link_config(bp, false);
 821         bp->link_info.link_up = 0;
 822
 823         return 0;
 824 }
 825
 826 /* Unload the driver, release resources */
 827 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 828 {
 829         struct bnxt *bp = eth_dev->data->dev_private;
 830         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 831         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 832
 833         bnxt_disable_int(bp);
 834
 835         /* disable uio/vfio intr/eventfd mapping */
 836         rte_intr_disable(intr_handle);
 837
 838         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 839         if (bp->eth_dev->data->dev_started) {
 840                 /* TBD: STOP HW queues DMA */
 841                 eth_dev->data->dev_link.link_status = 0;
 842         }
 843         bnxt_set_hwrm_link_config(bp, false);
 844
 845         /* Clean queue intr-vector mapping */
 846         rte_intr_efd_disable(intr_handle);
 847         if (intr_handle->intr_vec != NULL) {
 848                 rte_free(intr_handle->intr_vec);
 849                 intr_handle->intr_vec = NULL;
 850         }
 851
 852         bnxt_hwrm_port_clr_stats(bp);
 853         bnxt_free_tx_mbufs(bp);
 854         bnxt_free_rx_mbufs(bp);
 855         bnxt_shutdown_nic(bp);
 856         bp->dev_stopped = 1;
 857 }
 858
 859 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 860 {
 861         struct bnxt *bp = eth_dev->data->dev_private;
 862
 863         if (bp->dev_stopped == 0)
 864                 bnxt_dev_stop_op(eth_dev);
 865
 866         if (eth_dev->data->mac_addrs != NULL) {
 867                 rte_free(eth_dev->data->mac_addrs);
 868                 eth_dev->data->mac_addrs = NULL;
 869         }
 870         if (bp->grp_info != NULL) {
 871                 rte_free(bp->grp_info);
 872                 bp->grp_info = NULL;
 873         }
 874
 875         bnxt_dev_uninit(eth_dev);
 876 }
 877
 878 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 879                                     uint32_t index)
 880 {
 881         struct bnxt *bp = eth_dev->data->dev_private;
 882         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 883         struct bnxt_vnic_info *vnic;
 884         struct bnxt_filter_info *filter, *temp_filter;
 885         uint32_t i;
 886
 887         /*
 888          * Loop through all VNICs from the specified filter flow pools to
 889          * remove the corresponding MAC addr filter
 890          */
 891         for (i = 0; i < bp->nr_vnics; i++) {
 892                 if (!(pool_mask & (1ULL << i)))
 893                         continue;
 894
 895                 vnic = &bp->vnic_info[i];
 896                 filter = STAILQ_FIRST(&vnic->filter);
 897                 while (filter) {
 898                         temp_filter = STAILQ_NEXT(filter, next);
 899                         if (filter->mac_index == index) {
 900                                 STAILQ_REMOVE(&vnic->filter, filter,
 901                                                 bnxt_filter_info, next);
 902                                 bnxt_hwrm_clear_l2_filter(bp, filter);
 903                                 filter->mac_index = INVALID_MAC_INDEX;
 904                                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
 905                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
 906                                                    filter, next);
 907                         }
 908                         filter = temp_filter;
 909                 }
 910         }
 911 }
 912
 913 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
 914                                 struct rte_ether_addr *mac_addr,
 915                                 uint32_t index, uint32_t pool)
 916 {
 917         struct bnxt *bp = eth_dev->data->dev_private;
 918         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
 919         struct bnxt_filter_info *filter;
 920         int rc = 0;
 921
 922         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
 923                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
 924                 return -ENOTSUP;
 925         }
 926
 927         if (!vnic) {
 928                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
 929                 return -EINVAL;
 930         }
 931         /* Attach requested MAC address to the new l2_filter */
 932         STAILQ_FOREACH(filter, &vnic->filter, next) {
 933                 if (filter->mac_index == index) {
 934                         PMD_DRV_LOG(ERR,
 935                                 "MAC addr already existed for pool %d\n", pool);
 936                         return 0;
 937                 }
 938         }
 939         filter = bnxt_alloc_filter(bp);
 940         if (!filter) {
 941                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
 942                 return -ENODEV;
 943         }
 944
 945         filter->mac_index = index;
 946         memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
 947
 948         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
 949         if (!rc) {
 950                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
 951         } else {
 952                 filter->mac_index = INVALID_MAC_INDEX;
 953                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
 954                 bnxt_free_filter(bp, filter);
 955         }
 956
 957         return rc;
 958 }
 959
 960 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
 961 {
 962         int rc = 0;
 963         struct bnxt *bp = eth_dev->data->dev_private;
 964         struct rte_eth_link new;
 965         unsigned int cnt = BNXT_LINK_WAIT_CNT;
 966
 967         memset(&new, 0, sizeof(new));
 968         do {
 969                 /* Retrieve link info from hardware */
 970                 rc = bnxt_get_hwrm_link_config(bp, &new);
 971                 if (rc) {
 972                         new.link_speed = ETH_LINK_SPEED_100M;
 973                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
 974                         PMD_DRV_LOG(ERR,
 975                                 "Failed to retrieve link rc = 0x%x!\n", rc);
 976                         goto out;
 977                 }
 978
 979                 if (!wait_to_complete || new.link_status)
 980                         break;
 981
 982                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
 983         } while (cnt--);
 984
 985 out:
 986         /* Timed out or success */
 987         if (new.link_status != eth_dev->data->dev_link.link_status ||
 988         new.link_speed != eth_dev->data->dev_link.link_speed) {
 989                 memcpy(&eth_dev->data->dev_link, &new,
 990                         sizeof(struct rte_eth_link));
 991
 992                 _rte_eth_dev_callback_process(eth_dev,
 993                                               RTE_ETH_EVENT_INTR_LSC,
 994                                               NULL);
 995
 996                 bnxt_print_link_info(eth_dev);
 997         }
 998
 999         return rc;
1000 }
1001
1002 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1003 {
1004         struct bnxt *bp = eth_dev->data->dev_private;
1005         struct bnxt_vnic_info *vnic;
1006
1007         if (bp->vnic_info == NULL)
1008                 return;
1009
1010         vnic = &bp->vnic_info[0];
1011
1012         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1013         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1014 }
1015
1016 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1017 {
1018         struct bnxt *bp = eth_dev->data->dev_private;
1019         struct bnxt_vnic_info *vnic;
1020
1021         if (bp->vnic_info == NULL)
1022                 return;
1023
1024         vnic = &bp->vnic_info[0];
1025
1026         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1027         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1028 }
1029
1030 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1031 {
1032         struct bnxt *bp = eth_dev->data->dev_private;
1033         struct bnxt_vnic_info *vnic;
1034
1035         if (bp->vnic_info == NULL)
1036                 return;
1037
1038         vnic = &bp->vnic_info[0];
1039
1040         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1041         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1042 }
1043
1044 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1045 {
1046         struct bnxt *bp = eth_dev->data->dev_private;
1047         struct bnxt_vnic_info *vnic;
1048
1049         if (bp->vnic_info == NULL)
1050                 return;
1051
1052         vnic = &bp->vnic_info[0];
1053
1054         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1055         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1056 }
1057
1058 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1059 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1060 {
1061         if (qid >= bp->rx_nr_rings)
1062                 return NULL;
1063
1064         return bp->eth_dev->data->rx_queues[qid];
1065 }
1066
1067 /* Return rxq corresponding to a given rss table ring/group ID. */
1068 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1069 {
1070         struct bnxt_rx_queue *rxq;
1071         unsigned int i;
1072
1073         if (!BNXT_HAS_RING_GRPS(bp)) {
1074                 for (i = 0; i < bp->rx_nr_rings; i++) {
1075                         rxq = bp->eth_dev->data->rx_queues[i];
1076                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1077                                 return rxq->index;
1078                 }
1079         } else {
1080                 for (i = 0; i < bp->rx_nr_rings; i++) {
1081                         if (bp->grp_info[i].fw_grp_id == fwr)
1082                                 return i;
1083                 }
1084         }
1085
1086         return INVALID_HW_RING_ID;
1087 }
1088
1089 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1090                             struct rte_eth_rss_reta_entry64 *reta_conf,
1091                             uint16_t reta_size)
1092 {
1093         struct bnxt *bp = eth_dev->data->dev_private;
1094         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1095         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1096         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1097         uint16_t idx, sft;
1098         int i;
1099
1100         if (!vnic->rss_table)
1101                 return -EINVAL;
1102
1103         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1104                 return -EINVAL;
1105
1106         if (reta_size != tbl_size) {
1107                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1108                         "(%d) must equal the size supported by the hardware "
1109                         "(%d)\n", reta_size, tbl_size);
1110                 return -EINVAL;
1111         }
1112
1113         for (i = 0; i < reta_size; i++) {
1114                 struct bnxt_rx_queue *rxq;
1115
1116                 idx = i / RTE_RETA_GROUP_SIZE;
1117                 sft = i % RTE_RETA_GROUP_SIZE;
1118
1119                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1120                         continue;
1121
1122                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1123                 if (!rxq) {
1124                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1125                         return -EINVAL;
1126                 }
1127
1128                 if (BNXT_CHIP_THOR(bp)) {
1129                         vnic->rss_table[i * 2] =
1130                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1131                         vnic->rss_table[i * 2 + 1] =
1132                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1133                 } else {
1134                         vnic->rss_table[i] =
1135                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1136                 }
1137
1138                 vnic->rss_table[i] =
1139                     vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1140         }
1141
1142         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1143         return 0;
1144 }
1145
1146 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1147                               struct rte_eth_rss_reta_entry64 *reta_conf,
1148                               uint16_t reta_size)
1149 {
1150         struct bnxt *bp = eth_dev->data->dev_private;
1151         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1152         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1153         uint16_t idx, sft, i;
1154
1155         /* Retrieve from the default VNIC */
1156         if (!vnic)
1157                 return -EINVAL;
1158         if (!vnic->rss_table)
1159                 return -EINVAL;
1160
1161         if (reta_size != tbl_size) {
1162                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1163                         "(%d) must equal the size supported by the hardware "
1164                         "(%d)\n", reta_size, tbl_size);
1165                 return -EINVAL;
1166         }
1167
1168         for (idx = 0, i = 0; i < reta_size; i++) {
1169                 idx = i / RTE_RETA_GROUP_SIZE;
1170                 sft = i % RTE_RETA_GROUP_SIZE;
1171
1172                 if (reta_conf[idx].mask & (1ULL << sft)) {
1173                         uint16_t qid;
1174
1175                         if (BNXT_CHIP_THOR(bp))
1176                                 qid = bnxt_rss_to_qid(bp,
1177                                                       vnic->rss_table[i * 2]);
1178                         else
1179                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1180
1181                         if (qid == INVALID_HW_RING_ID) {
1182                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1183                                 return -EINVAL;
1184                         }
1185                         reta_conf[idx].reta[sft] = qid;
1186                 }
1187         }
1188
1189         return 0;
1190 }
1191
1192 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1193                                    struct rte_eth_rss_conf *rss_conf)
1194 {
1195         struct bnxt *bp = eth_dev->data->dev_private;
1196         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1197         struct bnxt_vnic_info *vnic;
1198         uint16_t hash_type = 0;
1199         unsigned int i;
1200
1201         /*
1202          * If RSS enablement were different than dev_configure,
1203          * then return -EINVAL
1204          */
1205         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1206                 if (!rss_conf->rss_hf)
1207                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1208         } else {
1209                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1210                         return -EINVAL;
1211         }
1212
1213         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1214         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1215
1216         if (rss_conf->rss_hf & ETH_RSS_IPV4)
1217                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1218         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1219                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1220         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1221                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1222         if (rss_conf->rss_hf & ETH_RSS_IPV6)
1223                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1224         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1225                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1226         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1227                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1228
1229         /* Update the RSS VNIC(s) */
1230         for (i = 0; i < bp->nr_vnics; i++) {
1231                 vnic = &bp->vnic_info[i];
1232                 vnic->hash_type = hash_type;
1233
1234                 /*
1235                  * Use the supplied key if the key length is
1236                  * acceptable and the rss_key is not NULL
1237                  */
1238                 if (rss_conf->rss_key &&
1239                     rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1240                         memcpy(vnic->rss_hash_key, rss_conf->rss_key,
1241                                rss_conf->rss_key_len);
1242
1243                 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1244         }
1245         return 0;
1246 }
1247
1248 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1249                                      struct rte_eth_rss_conf *rss_conf)
1250 {
1251         struct bnxt *bp = eth_dev->data->dev_private;
1252         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1253         int len;
1254         uint32_t hash_types;
1255
1256         /* RSS configuration is the same for all VNICs */
1257         if (vnic && vnic->rss_hash_key) {
1258                 if (rss_conf->rss_key) {
1259                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1260                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1261                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1262                 }
1263
1264                 hash_types = vnic->hash_type;
1265                 rss_conf->rss_hf = 0;
1266                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1267                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1268                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1269                 }
1270                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1271                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1272                         hash_types &=
1273                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1274                 }
1275                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1276                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1277                         hash_types &=
1278                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1279                 }
1280                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1281                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1282                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1283                 }
1284                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1285                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1286                         hash_types &=
1287                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1288                 }
1289                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1290                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1291                         hash_types &=
1292                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1293                 }
1294                 if (hash_types) {
1295                         PMD_DRV_LOG(ERR,
1296                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1297                                 vnic->hash_type);
1298                         return -ENOTSUP;
1299                 }
1300         } else {
1301                 rss_conf->rss_hf = 0;
1302         }
1303         return 0;
1304 }
1305
1306 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1307                                struct rte_eth_fc_conf *fc_conf)
1308 {
1309         struct bnxt *bp = dev->data->dev_private;
1310         struct rte_eth_link link_info;
1311         int rc;
1312
1313         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1314         if (rc)
1315                 return rc;
1316
1317         memset(fc_conf, 0, sizeof(*fc_conf));
1318         if (bp->link_info.auto_pause)
1319                 fc_conf->autoneg = 1;
1320         switch (bp->link_info.pause) {
1321         case 0:
1322                 fc_conf->mode = RTE_FC_NONE;
1323                 break;
1324         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1325                 fc_conf->mode = RTE_FC_TX_PAUSE;
1326                 break;
1327         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1328                 fc_conf->mode = RTE_FC_RX_PAUSE;
1329                 break;
1330         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1331                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1332                 fc_conf->mode = RTE_FC_FULL;
1333                 break;
1334         }
1335         return 0;
1336 }
1337
1338 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1339                                struct rte_eth_fc_conf *fc_conf)
1340 {
1341         struct bnxt *bp = dev->data->dev_private;
1342
1343         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1344                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1345                 return -ENOTSUP;
1346         }
1347
1348         switch (fc_conf->mode) {
1349         case RTE_FC_NONE:
1350                 bp->link_info.auto_pause = 0;
1351                 bp->link_info.force_pause = 0;
1352                 break;
1353         case RTE_FC_RX_PAUSE:
1354                 if (fc_conf->autoneg) {
1355                         bp->link_info.auto_pause =
1356                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1357                         bp->link_info.force_pause = 0;
1358                 } else {
1359                         bp->link_info.auto_pause = 0;
1360                         bp->link_info.force_pause =
1361                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1362                 }
1363                 break;
1364         case RTE_FC_TX_PAUSE:
1365                 if (fc_conf->autoneg) {
1366                         bp->link_info.auto_pause =
1367                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1368                         bp->link_info.force_pause = 0;
1369                 } else {
1370                         bp->link_info.auto_pause = 0;
1371                         bp->link_info.force_pause =
1372                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1373                 }
1374                 break;
1375         case RTE_FC_FULL:
1376                 if (fc_conf->autoneg) {
1377                         bp->link_info.auto_pause =
1378                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1379                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1380                         bp->link_info.force_pause = 0;
1381                 } else {
1382                         bp->link_info.auto_pause = 0;
1383                         bp->link_info.force_pause =
1384                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1385                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1386                 }
1387                 break;
1388         }
1389         return bnxt_set_hwrm_link_config(bp, true);
1390 }
1391
1392 /* Add UDP tunneling port */
1393 static int
1394 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1395                          struct rte_eth_udp_tunnel *udp_tunnel)
1396 {
1397         struct bnxt *bp = eth_dev->data->dev_private;
1398         uint16_t tunnel_type = 0;
1399         int rc = 0;
1400
1401         switch (udp_tunnel->prot_type) {
1402         case RTE_TUNNEL_TYPE_VXLAN:
1403                 if (bp->vxlan_port_cnt) {
1404                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1405                                 udp_tunnel->udp_port);
1406                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1407                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1408                                 return -ENOSPC;
1409                         }
1410                         bp->vxlan_port_cnt++;
1411                         return 0;
1412                 }
1413                 tunnel_type =
1414                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1415                 bp->vxlan_port_cnt++;
1416                 break;
1417         case RTE_TUNNEL_TYPE_GENEVE:
1418                 if (bp->geneve_port_cnt) {
1419                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1420                                 udp_tunnel->udp_port);
1421                         if (bp->geneve_port != udp_tunnel->udp_port) {
1422                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1423                                 return -ENOSPC;
1424                         }
1425                         bp->geneve_port_cnt++;
1426                         return 0;
1427                 }
1428                 tunnel_type =
1429                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1430                 bp->geneve_port_cnt++;
1431                 break;
1432         default:
1433                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1434                 return -ENOTSUP;
1435         }
1436         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1437                                              tunnel_type);
1438         return rc;
1439 }
1440
1441 static int
1442 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1443                          struct rte_eth_udp_tunnel *udp_tunnel)
1444 {
1445         struct bnxt *bp = eth_dev->data->dev_private;
1446         uint16_t tunnel_type = 0;
1447         uint16_t port = 0;
1448         int rc = 0;
1449
1450         switch (udp_tunnel->prot_type) {
1451         case RTE_TUNNEL_TYPE_VXLAN:
1452                 if (!bp->vxlan_port_cnt) {
1453                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1454                         return -EINVAL;
1455                 }
1456                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1457                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1458                                 udp_tunnel->udp_port, bp->vxlan_port);
1459                         return -EINVAL;
1460                 }
1461                 if (--bp->vxlan_port_cnt)
1462                         return 0;
1463
1464                 tunnel_type =
1465                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1466                 port = bp->vxlan_fw_dst_port_id;
1467                 break;
1468         case RTE_TUNNEL_TYPE_GENEVE:
1469                 if (!bp->geneve_port_cnt) {
1470                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1471                         return -EINVAL;
1472                 }
1473                 if (bp->geneve_port != udp_tunnel->udp_port) {
1474                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1475                                 udp_tunnel->udp_port, bp->geneve_port);
1476                         return -EINVAL;
1477                 }
1478                 if (--bp->geneve_port_cnt)
1479                         return 0;
1480
1481                 tunnel_type =
1482                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1483                 port = bp->geneve_fw_dst_port_id;
1484                 break;
1485         default:
1486                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1487                 return -ENOTSUP;
1488         }
1489
1490         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1491         if (!rc) {
1492                 if (tunnel_type ==
1493                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1494                         bp->vxlan_port = 0;
1495                 if (tunnel_type ==
1496                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1497                         bp->geneve_port = 0;
1498         }
1499         return rc;
1500 }
1501
1502 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1503 {
1504         struct bnxt_filter_info *filter;
1505         struct bnxt_vnic_info *vnic;
1506         int rc = 0;
1507         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1508
1509         /* if VLAN exists && VLAN matches vlan_id
1510          *      remove the MAC+VLAN filter
1511          *      add a new MAC only filter
1512          * else
1513          *      VLAN filter doesn't exist, just skip and continue
1514          */
1515         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1516         filter = STAILQ_FIRST(&vnic->filter);
1517         while (filter) {
1518                 /* Search for this matching MAC+VLAN filter */
1519                 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1520                     !memcmp(filter->l2_addr,
1521                             bp->mac_addr,
1522                             RTE_ETHER_ADDR_LEN)) {
1523                         /* Delete the filter */
1524                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1525                         if (rc)
1526                                 return rc;
1527                         STAILQ_REMOVE(&vnic->filter, filter,
1528                                       bnxt_filter_info, next);
1529                         STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1530
1531                         PMD_DRV_LOG(INFO,
1532                                     "Del Vlan filter for %d\n",
1533                                     vlan_id);
1534                         return rc;
1535                 }
1536                 filter = STAILQ_NEXT(filter, next);
1537         }
1538         return -ENOENT;
1539 }
1540
1541 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1542 {
1543         struct bnxt_filter_info *filter;
1544         struct bnxt_vnic_info *vnic;
1545         int rc = 0;
1546         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1547                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1548         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1549
1550         /* Implementation notes on the use of VNIC in this command:
1551          *
1552          * By default, these filters belong to default vnic for the function.
1553          * Once these filters are set up, only destination VNIC can be modified.
1554          * If the destination VNIC is not specified in this command,
1555          * then the HWRM shall only create an l2 context id.
1556          */
1557
1558         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1559         filter = STAILQ_FIRST(&vnic->filter);
1560         /* Check if the VLAN has already been added */
1561         while (filter) {
1562                 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1563                     !memcmp(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN))
1564                         return -EEXIST;
1565
1566                 filter = STAILQ_NEXT(filter, next);
1567         }
1568
1569         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1570          * command to create MAC+VLAN filter with the right flags, enables set.
1571          */
1572         filter = bnxt_alloc_filter(bp);
1573         if (!filter) {
1574                 PMD_DRV_LOG(ERR,
1575                             "MAC/VLAN filter alloc failed\n");
1576                 return -ENOMEM;
1577         }
1578         /* MAC + VLAN ID filter */
1579         filter->l2_ivlan = vlan_id;
1580         filter->l2_ivlan_mask = 0x0FFF;
1581         filter->enables |= en;
1582         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1583         if (rc) {
1584                 /* Free the newly allocated filter as we were
1585                  * not able to create the filter in hardware.
1586                  */
1587                 filter->fw_l2_filter_id = UINT64_MAX;
1588                 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1589                 return rc;
1590         }
1591
1592         /* Add this new filter to the list */
1593         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1594         PMD_DRV_LOG(INFO,
1595                     "Added Vlan filter for %d\n", vlan_id);
1596         return rc;
1597 }
1598
1599 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1600                 uint16_t vlan_id, int on)
1601 {
1602         struct bnxt *bp = eth_dev->data->dev_private;
1603
1604         /* These operations apply to ALL existing MAC/VLAN filters */
1605         if (on)
1606                 return bnxt_add_vlan_filter(bp, vlan_id);
1607         else
1608                 return bnxt_del_vlan_filter(bp, vlan_id);
1609 }
1610
1611 static int
1612 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1613 {
1614         struct bnxt *bp = dev->data->dev_private;
1615         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1616         unsigned int i;
1617
1618         if (mask & ETH_VLAN_FILTER_MASK) {
1619                 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1620                         /* Remove any VLAN filters programmed */
1621                         for (i = 0; i < 4095; i++)
1622                                 bnxt_del_vlan_filter(bp, i);
1623                 }
1624                 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1625                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1626         }
1627
1628         if (mask & ETH_VLAN_STRIP_MASK) {
1629                 /* Enable or disable VLAN stripping */
1630                 for (i = 0; i < bp->nr_vnics; i++) {
1631                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1632                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1633                                 vnic->vlan_strip = true;
1634                         else
1635                                 vnic->vlan_strip = false;
1636                         bnxt_hwrm_vnic_cfg(bp, vnic);
1637                 }
1638                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1639                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1640         }
1641
1642         if (mask & ETH_VLAN_EXTEND_MASK)
1643                 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1644
1645         return 0;
1646 }
1647
1648 static int
1649 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1650                         struct rte_ether_addr *addr)
1651 {
1652         struct bnxt *bp = dev->data->dev_private;
1653         /* Default Filter is tied to VNIC 0 */
1654         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1655         struct bnxt_filter_info *filter;
1656         int rc;
1657
1658         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1659                 return -EPERM;
1660
1661         if (rte_is_zero_ether_addr(addr))
1662                 return -EINVAL;
1663
1664         STAILQ_FOREACH(filter, &vnic->filter, next) {
1665                 /* Default Filter is at Index 0 */
1666                 if (filter->mac_index != 0)
1667                         continue;
1668
1669                 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
1670                 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1671                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1672                 filter->enables |=
1673                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1674                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1675
1676                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1677                 if (rc)
1678                         return rc;
1679
1680                 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
1681                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1682                 return 0;
1683         }
1684
1685         return 0;
1686 }
1687
1688 static int
1689 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1690                           struct rte_ether_addr *mc_addr_set,
1691                           uint32_t nb_mc_addr)
1692 {
1693         struct bnxt *bp = eth_dev->data->dev_private;
1694         char *mc_addr_list = (char *)mc_addr_set;
1695         struct bnxt_vnic_info *vnic;
1696         uint32_t off = 0, i = 0;
1697
1698         vnic = &bp->vnic_info[0];
1699
1700         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1701                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1702                 goto allmulti;
1703         }
1704
1705         /* TODO Check for Duplicate mcast addresses */
1706         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1707         for (i = 0; i < nb_mc_addr; i++) {
1708                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1709                         RTE_ETHER_ADDR_LEN);
1710                 off += RTE_ETHER_ADDR_LEN;
1711         }
1712
1713         vnic->mc_addr_cnt = i;
1714
1715 allmulti:
1716         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1717 }
1718
1719 static int
1720 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1721 {
1722         struct bnxt *bp = dev->data->dev_private;
1723         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1724         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1725         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1726         int ret;
1727
1728         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1729                         fw_major, fw_minor, fw_updt);
1730
1731         ret += 1; /* add the size of '\0' */
1732         if (fw_size < (uint32_t)ret)
1733                 return ret;
1734         else
1735                 return 0;
1736 }
1737
1738 static void
1739 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1740         struct rte_eth_rxq_info *qinfo)
1741 {
1742         struct bnxt_rx_queue *rxq;
1743
1744         rxq = dev->data->rx_queues[queue_id];
1745
1746         qinfo->mp = rxq->mb_pool;
1747         qinfo->scattered_rx = dev->data->scattered_rx;
1748         qinfo->nb_desc = rxq->nb_rx_desc;
1749
1750         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1751         qinfo->conf.rx_drop_en = 0;
1752         qinfo->conf.rx_deferred_start = 0;
1753 }
1754
1755 static void
1756 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1757         struct rte_eth_txq_info *qinfo)
1758 {
1759         struct bnxt_tx_queue *txq;
1760
1761         txq = dev->data->tx_queues[queue_id];
1762
1763         qinfo->nb_desc = txq->nb_tx_desc;
1764
1765         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1766         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1767         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1768
1769         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1770         qinfo->conf.tx_rs_thresh = 0;
1771         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1772 }
1773
1774 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1775 {
1776         struct bnxt *bp = eth_dev->data->dev_private;
1777         struct rte_eth_dev_info dev_info;
1778         uint32_t new_pkt_size;
1779         uint32_t rc = 0;
1780         uint32_t i;
1781
1782         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1783                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
1784
1785         bnxt_dev_info_get_op(eth_dev, &dev_info);
1786
1787         if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > BNXT_MAX_MTU) {
1788                 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1789                         RTE_ETHER_MIN_MTU, BNXT_MAX_MTU);
1790                 return -EINVAL;
1791         }
1792
1793 #ifdef RTE_ARCH_X86
1794         /*
1795          * If vector-mode tx/rx is active, disallow any MTU change that would
1796          * require scattered receive support.
1797          */
1798         if (eth_dev->data->dev_started &&
1799             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
1800              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
1801             (new_pkt_size >
1802              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
1803                 PMD_DRV_LOG(ERR,
1804                             "MTU change would require scattered rx support. ");
1805                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
1806                 return -EINVAL;
1807         }
1808 #endif
1809
1810         if (new_mtu > RTE_ETHER_MTU) {
1811                 bp->flags |= BNXT_FLAG_JUMBO;
1812                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1813                         DEV_RX_OFFLOAD_JUMBO_FRAME;
1814         } else {
1815                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1816                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1817                 bp->flags &= ~BNXT_FLAG_JUMBO;
1818         }
1819
1820         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
1821
1822         eth_dev->data->mtu = new_mtu;
1823         PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1824
1825         for (i = 0; i < bp->nr_vnics; i++) {
1826                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1827                 uint16_t size = 0;
1828
1829                 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1830                                         RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1831                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1832                 if (rc)
1833                         break;
1834
1835                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1836                 size -= RTE_PKTMBUF_HEADROOM;
1837
1838                 if (size < new_mtu) {
1839                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1840                         if (rc)
1841                                 return rc;
1842                 }
1843         }
1844
1845         return rc;
1846 }
1847
1848 static int
1849 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1850 {
1851         struct bnxt *bp = dev->data->dev_private;
1852         uint16_t vlan = bp->vlan;
1853         int rc;
1854
1855         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1856                 PMD_DRV_LOG(ERR,
1857                         "PVID cannot be modified for this function\n");
1858                 return -ENOTSUP;
1859         }
1860         bp->vlan = on ? pvid : 0;
1861
1862         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1863         if (rc)
1864                 bp->vlan = vlan;
1865         return rc;
1866 }
1867
1868 static int
1869 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1870 {
1871         struct bnxt *bp = dev->data->dev_private;
1872
1873         return bnxt_hwrm_port_led_cfg(bp, true);
1874 }
1875
1876 static int
1877 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1878 {
1879         struct bnxt *bp = dev->data->dev_private;
1880
1881         return bnxt_hwrm_port_led_cfg(bp, false);
1882 }
1883
1884 static uint32_t
1885 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1886 {
1887         uint32_t desc = 0, raw_cons = 0, cons;
1888         struct bnxt_cp_ring_info *cpr;
1889         struct bnxt_rx_queue *rxq;
1890         struct rx_pkt_cmpl *rxcmp;
1891         uint16_t cmp_type;
1892         uint8_t cmp = 1;
1893         bool valid;
1894
1895         rxq = dev->data->rx_queues[rx_queue_id];
1896         cpr = rxq->cp_ring;
1897         valid = cpr->valid;
1898
1899         while (raw_cons < rxq->nb_rx_desc) {
1900                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1901                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1902
1903                 if (!CMPL_VALID(rxcmp, valid))
1904                         goto nothing_to_do;
1905                 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1906                 cmp_type = CMP_TYPE(rxcmp);
1907                 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1908                         cmp = (rte_le_to_cpu_32(
1909                                         ((struct rx_tpa_end_cmpl *)
1910                                          (rxcmp))->agg_bufs_v1) &
1911                                RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1912                                 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1913                         desc++;
1914                 } else if (cmp_type == 0x11) {
1915                         desc++;
1916                         cmp = (rxcmp->agg_bufs_v1 &
1917                                    RX_PKT_CMPL_AGG_BUFS_MASK) >>
1918                                 RX_PKT_CMPL_AGG_BUFS_SFT;
1919                 } else {
1920                         cmp = 1;
1921                 }
1922 nothing_to_do:
1923                 raw_cons += cmp ? cmp : 2;
1924         }
1925
1926         return desc;
1927 }
1928
1929 static int
1930 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1931 {
1932         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1933         struct bnxt_rx_ring_info *rxr;
1934         struct bnxt_cp_ring_info *cpr;
1935         struct bnxt_sw_rx_bd *rx_buf;
1936         struct rx_pkt_cmpl *rxcmp;
1937         uint32_t cons, cp_cons;
1938
1939         if (!rxq)
1940                 return -EINVAL;
1941
1942         cpr = rxq->cp_ring;
1943         rxr = rxq->rx_ring;
1944
1945         if (offset >= rxq->nb_rx_desc)
1946                 return -EINVAL;
1947
1948         cons = RING_CMP(cpr->cp_ring_struct, offset);
1949         cp_cons = cpr->cp_raw_cons;
1950         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1951
1952         if (cons > cp_cons) {
1953                 if (CMPL_VALID(rxcmp, cpr->valid))
1954                         return RTE_ETH_RX_DESC_DONE;
1955         } else {
1956                 if (CMPL_VALID(rxcmp, !cpr->valid))
1957                         return RTE_ETH_RX_DESC_DONE;
1958         }
1959         rx_buf = &rxr->rx_buf_ring[cons];
1960         if (rx_buf->mbuf == NULL)
1961                 return RTE_ETH_RX_DESC_UNAVAIL;
1962
1963
1964         return RTE_ETH_RX_DESC_AVAIL;
1965 }
1966
1967 static int
1968 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1969 {
1970         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1971         struct bnxt_tx_ring_info *txr;
1972         struct bnxt_cp_ring_info *cpr;
1973         struct bnxt_sw_tx_bd *tx_buf;
1974         struct tx_pkt_cmpl *txcmp;
1975         uint32_t cons, cp_cons;
1976
1977         if (!txq)
1978                 return -EINVAL;
1979
1980         cpr = txq->cp_ring;
1981         txr = txq->tx_ring;
1982
1983         if (offset >= txq->nb_tx_desc)
1984                 return -EINVAL;
1985
1986         cons = RING_CMP(cpr->cp_ring_struct, offset);
1987         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1988         cp_cons = cpr->cp_raw_cons;
1989
1990         if (cons > cp_cons) {
1991                 if (CMPL_VALID(txcmp, cpr->valid))
1992                         return RTE_ETH_TX_DESC_UNAVAIL;
1993         } else {
1994                 if (CMPL_VALID(txcmp, !cpr->valid))
1995                         return RTE_ETH_TX_DESC_UNAVAIL;
1996         }
1997         tx_buf = &txr->tx_buf_ring[cons];
1998         if (tx_buf->mbuf == NULL)
1999                 return RTE_ETH_TX_DESC_DONE;
2000
2001         return RTE_ETH_TX_DESC_FULL;
2002 }
2003
2004 static struct bnxt_filter_info *
2005 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2006                                 struct rte_eth_ethertype_filter *efilter,
2007                                 struct bnxt_vnic_info *vnic0,
2008                                 struct bnxt_vnic_info *vnic,
2009                                 int *ret)
2010 {
2011         struct bnxt_filter_info *mfilter = NULL;
2012         int match = 0;
2013         *ret = 0;
2014
2015         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2016                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2017                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2018                         " ethertype filter.", efilter->ether_type);
2019                 *ret = -EINVAL;
2020                 goto exit;
2021         }
2022         if (efilter->queue >= bp->rx_nr_rings) {
2023                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2024                 *ret = -EINVAL;
2025                 goto exit;
2026         }
2027
2028         vnic0 = &bp->vnic_info[0];
2029         vnic = &bp->vnic_info[efilter->queue];
2030         if (vnic == NULL) {
2031                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2032                 *ret = -EINVAL;
2033                 goto exit;
2034         }
2035
2036         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2037                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2038                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2039                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2040                              mfilter->flags ==
2041                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2042                              mfilter->ethertype == efilter->ether_type)) {
2043                                 match = 1;
2044                                 break;
2045                         }
2046                 }
2047         } else {
2048                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2049                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2050                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2051                              mfilter->ethertype == efilter->ether_type &&
2052                              mfilter->flags ==
2053                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2054                                 match = 1;
2055                                 break;
2056                         }
2057         }
2058
2059         if (match)
2060                 *ret = -EEXIST;
2061
2062 exit:
2063         return mfilter;
2064 }
2065
2066 static int
2067 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2068                         enum rte_filter_op filter_op,
2069                         void *arg)
2070 {
2071         struct bnxt *bp = dev->data->dev_private;
2072         struct rte_eth_ethertype_filter *efilter =
2073                         (struct rte_eth_ethertype_filter *)arg;
2074         struct bnxt_filter_info *bfilter, *filter1;
2075         struct bnxt_vnic_info *vnic, *vnic0;
2076         int ret;
2077
2078         if (filter_op == RTE_ETH_FILTER_NOP)
2079                 return 0;
2080
2081         if (arg == NULL) {
2082                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2083                             filter_op);
2084                 return -EINVAL;
2085         }
2086
2087         vnic0 = &bp->vnic_info[0];
2088         vnic = &bp->vnic_info[efilter->queue];
2089
2090         switch (filter_op) {
2091         case RTE_ETH_FILTER_ADD:
2092                 bnxt_match_and_validate_ether_filter(bp, efilter,
2093                                                         vnic0, vnic, &ret);
2094                 if (ret < 0)
2095                         return ret;
2096
2097                 bfilter = bnxt_get_unused_filter(bp);
2098                 if (bfilter == NULL) {
2099                         PMD_DRV_LOG(ERR,
2100                                 "Not enough resources for a new filter.\n");
2101                         return -ENOMEM;
2102                 }
2103                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2104                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2105                        RTE_ETHER_ADDR_LEN);
2106                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2107                        RTE_ETHER_ADDR_LEN);
2108                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2109                 bfilter->ethertype = efilter->ether_type;
2110                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2111
2112                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2113                 if (filter1 == NULL) {
2114                         ret = -EINVAL;
2115                         goto cleanup;
2116                 }
2117                 bfilter->enables |=
2118                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2119                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2120
2121                 bfilter->dst_id = vnic->fw_vnic_id;
2122
2123                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2124                         bfilter->flags =
2125                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2126                 }
2127
2128                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2129                 if (ret)
2130                         goto cleanup;
2131                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2132                 break;
2133         case RTE_ETH_FILTER_DELETE:
2134                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2135                                                         vnic0, vnic, &ret);
2136                 if (ret == -EEXIST) {
2137                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2138
2139                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2140                                       next);
2141                         bnxt_free_filter(bp, filter1);
2142                 } else if (ret == 0) {
2143                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2144                 }
2145                 break;
2146         default:
2147                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2148                 ret = -EINVAL;
2149                 goto error;
2150         }
2151         return ret;
2152 cleanup:
2153         bnxt_free_filter(bp, bfilter);
2154 error:
2155         return ret;
2156 }
2157
2158 static inline int
2159 parse_ntuple_filter(struct bnxt *bp,
2160                     struct rte_eth_ntuple_filter *nfilter,
2161                     struct bnxt_filter_info *bfilter)
2162 {
2163         uint32_t en = 0;
2164
2165         if (nfilter->queue >= bp->rx_nr_rings) {
2166                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2167                 return -EINVAL;
2168         }
2169
2170         switch (nfilter->dst_port_mask) {
2171         case UINT16_MAX:
2172                 bfilter->dst_port_mask = -1;
2173                 bfilter->dst_port = nfilter->dst_port;
2174                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2175                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2176                 break;
2177         default:
2178                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2179                 return -EINVAL;
2180         }
2181
2182         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2183         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2184
2185         switch (nfilter->proto_mask) {
2186         case UINT8_MAX:
2187                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2188                         bfilter->ip_protocol = 17;
2189                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2190                         bfilter->ip_protocol = 6;
2191                 else
2192                         return -EINVAL;
2193                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2194                 break;
2195         default:
2196                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2197                 return -EINVAL;
2198         }
2199
2200         switch (nfilter->dst_ip_mask) {
2201         case UINT32_MAX:
2202                 bfilter->dst_ipaddr_mask[0] = -1;
2203                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2204                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2205                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2206                 break;
2207         default:
2208                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2209                 return -EINVAL;
2210         }
2211
2212         switch (nfilter->src_ip_mask) {
2213         case UINT32_MAX:
2214                 bfilter->src_ipaddr_mask[0] = -1;
2215                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2216                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2217                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2218                 break;
2219         default:
2220                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2221                 return -EINVAL;
2222         }
2223
2224         switch (nfilter->src_port_mask) {
2225         case UINT16_MAX:
2226                 bfilter->src_port_mask = -1;
2227                 bfilter->src_port = nfilter->src_port;
2228                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2229                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2230                 break;
2231         default:
2232                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2233                 return -EINVAL;
2234         }
2235
2236         //TODO Priority
2237         //nfilter->priority = (uint8_t)filter->priority;
2238
2239         bfilter->enables = en;
2240         return 0;
2241 }
2242
2243 static struct bnxt_filter_info*
2244 bnxt_match_ntuple_filter(struct bnxt *bp,
2245                          struct bnxt_filter_info *bfilter,
2246                          struct bnxt_vnic_info **mvnic)
2247 {
2248         struct bnxt_filter_info *mfilter = NULL;
2249         int i;
2250
2251         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2252                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2253                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2254                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2255                             bfilter->src_ipaddr_mask[0] ==
2256                             mfilter->src_ipaddr_mask[0] &&
2257                             bfilter->src_port == mfilter->src_port &&
2258                             bfilter->src_port_mask == mfilter->src_port_mask &&
2259                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2260                             bfilter->dst_ipaddr_mask[0] ==
2261                             mfilter->dst_ipaddr_mask[0] &&
2262                             bfilter->dst_port == mfilter->dst_port &&
2263                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2264                             bfilter->flags == mfilter->flags &&
2265                             bfilter->enables == mfilter->enables) {
2266                                 if (mvnic)
2267                                         *mvnic = vnic;
2268                                 return mfilter;
2269                         }
2270                 }
2271         }
2272         return NULL;
2273 }
2274
2275 static int
2276 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2277                        struct rte_eth_ntuple_filter *nfilter,
2278                        enum rte_filter_op filter_op)
2279 {
2280         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2281         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2282         int ret;
2283
2284         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2285                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2286                 return -EINVAL;
2287         }
2288
2289         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2290                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2291                 return -EINVAL;
2292         }
2293
2294         bfilter = bnxt_get_unused_filter(bp);
2295         if (bfilter == NULL) {
2296                 PMD_DRV_LOG(ERR,
2297                         "Not enough resources for a new filter.\n");
2298                 return -ENOMEM;
2299         }
2300         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2301         if (ret < 0)
2302                 goto free_filter;
2303
2304         vnic = &bp->vnic_info[nfilter->queue];
2305         vnic0 = &bp->vnic_info[0];
2306         filter1 = STAILQ_FIRST(&vnic0->filter);
2307         if (filter1 == NULL) {
2308                 ret = -EINVAL;
2309                 goto free_filter;
2310         }
2311
2312         bfilter->dst_id = vnic->fw_vnic_id;
2313         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2314         bfilter->enables |=
2315                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2316         bfilter->ethertype = 0x800;
2317         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2318
2319         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2320
2321         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2322             bfilter->dst_id == mfilter->dst_id) {
2323                 PMD_DRV_LOG(ERR, "filter exists.\n");
2324                 ret = -EEXIST;
2325                 goto free_filter;
2326         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2327                    bfilter->dst_id != mfilter->dst_id) {
2328                 mfilter->dst_id = vnic->fw_vnic_id;
2329                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2330                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2331                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2332                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2333                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2334                 goto free_filter;
2335         }
2336         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2337                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2338                 ret = -ENOENT;
2339                 goto free_filter;
2340         }
2341
2342         if (filter_op == RTE_ETH_FILTER_ADD) {
2343                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2344                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2345                 if (ret)
2346                         goto free_filter;
2347                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2348         } else {
2349                 if (mfilter == NULL) {
2350                         /* This should not happen. But for Coverity! */
2351                         ret = -ENOENT;
2352                         goto free_filter;
2353                 }
2354                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2355
2356                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2357                 bnxt_free_filter(bp, mfilter);
2358                 mfilter->fw_l2_filter_id = -1;
2359                 bnxt_free_filter(bp, bfilter);
2360                 bfilter->fw_l2_filter_id = -1;
2361         }
2362
2363         return 0;
2364 free_filter:
2365         bfilter->fw_l2_filter_id = -1;
2366         bnxt_free_filter(bp, bfilter);
2367         return ret;
2368 }
2369
2370 static int
2371 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2372                         enum rte_filter_op filter_op,
2373                         void *arg)
2374 {
2375         struct bnxt *bp = dev->data->dev_private;
2376         int ret;
2377
2378         if (filter_op == RTE_ETH_FILTER_NOP)
2379                 return 0;
2380
2381         if (arg == NULL) {
2382                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2383                             filter_op);
2384                 return -EINVAL;
2385         }
2386
2387         switch (filter_op) {
2388         case RTE_ETH_FILTER_ADD:
2389                 ret = bnxt_cfg_ntuple_filter(bp,
2390                         (struct rte_eth_ntuple_filter *)arg,
2391                         filter_op);
2392                 break;
2393         case RTE_ETH_FILTER_DELETE:
2394                 ret = bnxt_cfg_ntuple_filter(bp,
2395                         (struct rte_eth_ntuple_filter *)arg,
2396                         filter_op);
2397                 break;
2398         default:
2399                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2400                 ret = -EINVAL;
2401                 break;
2402         }
2403         return ret;
2404 }
2405
2406 static int
2407 bnxt_parse_fdir_filter(struct bnxt *bp,
2408                        struct rte_eth_fdir_filter *fdir,
2409                        struct bnxt_filter_info *filter)
2410 {
2411         enum rte_fdir_mode fdir_mode =
2412                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2413         struct bnxt_vnic_info *vnic0, *vnic;
2414         struct bnxt_filter_info *filter1;
2415         uint32_t en = 0;
2416         int i;
2417
2418         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2419                 return -EINVAL;
2420
2421         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2422         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2423
2424         switch (fdir->input.flow_type) {
2425         case RTE_ETH_FLOW_IPV4:
2426         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2427                 /* FALLTHROUGH */
2428                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2429                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2430                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2431                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2432                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2433                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2434                 filter->ip_addr_type =
2435                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2436                 filter->src_ipaddr_mask[0] = 0xffffffff;
2437                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2438                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2439                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2440                 filter->ethertype = 0x800;
2441                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2442                 break;
2443         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2444                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2445                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2446                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2447                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2448                 filter->dst_port_mask = 0xffff;
2449                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2450                 filter->src_port_mask = 0xffff;
2451                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2452                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2453                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2454                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2455                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2456                 filter->ip_protocol = 6;
2457                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2458                 filter->ip_addr_type =
2459                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2460                 filter->src_ipaddr_mask[0] = 0xffffffff;
2461                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2462                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2463                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2464                 filter->ethertype = 0x800;
2465                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2466                 break;
2467         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2468                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2469                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2470                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2471                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2472                 filter->dst_port_mask = 0xffff;
2473                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2474                 filter->src_port_mask = 0xffff;
2475                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2476                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2477                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2478                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2479                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2480                 filter->ip_protocol = 17;
2481                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2482                 filter->ip_addr_type =
2483                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2484                 filter->src_ipaddr_mask[0] = 0xffffffff;
2485                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2486                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2487                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2488                 filter->ethertype = 0x800;
2489                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2490                 break;
2491         case RTE_ETH_FLOW_IPV6:
2492         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2493                 /* FALLTHROUGH */
2494                 filter->ip_addr_type =
2495                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2496                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2497                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2498                 rte_memcpy(filter->src_ipaddr,
2499                            fdir->input.flow.ipv6_flow.src_ip, 16);
2500                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2501                 rte_memcpy(filter->dst_ipaddr,
2502                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2503                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2504                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2505                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2506                 memset(filter->src_ipaddr_mask, 0xff, 16);
2507                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2508                 filter->ethertype = 0x86dd;
2509                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2510                 break;
2511         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2512                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2513                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2514                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2515                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2516                 filter->dst_port_mask = 0xffff;
2517                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2518                 filter->src_port_mask = 0xffff;
2519                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2520                 filter->ip_addr_type =
2521                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2522                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2523                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2524                 rte_memcpy(filter->src_ipaddr,
2525                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2526                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2527                 rte_memcpy(filter->dst_ipaddr,
2528                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2529                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2530                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2531                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2532                 memset(filter->src_ipaddr_mask, 0xff, 16);
2533                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2534                 filter->ethertype = 0x86dd;
2535                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2536                 break;
2537         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2538                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2539                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2540                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2541                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2542                 filter->dst_port_mask = 0xffff;
2543                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2544                 filter->src_port_mask = 0xffff;
2545                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2546                 filter->ip_addr_type =
2547                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2548                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2549                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2550                 rte_memcpy(filter->src_ipaddr,
2551                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2552                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2553                 rte_memcpy(filter->dst_ipaddr,
2554                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2555                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2556                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2557                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2558                 memset(filter->src_ipaddr_mask, 0xff, 16);
2559                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2560                 filter->ethertype = 0x86dd;
2561                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2562                 break;
2563         case RTE_ETH_FLOW_L2_PAYLOAD:
2564                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2565                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2566                 break;
2567         case RTE_ETH_FLOW_VXLAN:
2568                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2569                         return -EINVAL;
2570                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2571                 filter->tunnel_type =
2572                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2573                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2574                 break;
2575         case RTE_ETH_FLOW_NVGRE:
2576                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2577                         return -EINVAL;
2578                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2579                 filter->tunnel_type =
2580                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2581                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2582                 break;
2583         case RTE_ETH_FLOW_UNKNOWN:
2584         case RTE_ETH_FLOW_RAW:
2585         case RTE_ETH_FLOW_FRAG_IPV4:
2586         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2587         case RTE_ETH_FLOW_FRAG_IPV6:
2588         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2589         case RTE_ETH_FLOW_IPV6_EX:
2590         case RTE_ETH_FLOW_IPV6_TCP_EX:
2591         case RTE_ETH_FLOW_IPV6_UDP_EX:
2592         case RTE_ETH_FLOW_GENEVE:
2593                 /* FALLTHROUGH */
2594         default:
2595                 return -EINVAL;
2596         }
2597
2598         vnic0 = &bp->vnic_info[0];
2599         vnic = &bp->vnic_info[fdir->action.rx_queue];
2600         if (vnic == NULL) {
2601                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2602                 return -EINVAL;
2603         }
2604
2605
2606         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2607                 rte_memcpy(filter->dst_macaddr,
2608                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2609                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2610         }
2611
2612         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2613                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2614                 filter1 = STAILQ_FIRST(&vnic0->filter);
2615                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2616         } else {
2617                 filter->dst_id = vnic->fw_vnic_id;
2618                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2619                         if (filter->dst_macaddr[i] == 0x00)
2620                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2621                         else
2622                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2623         }
2624
2625         if (filter1 == NULL)
2626                 return -EINVAL;
2627
2628         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2629         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2630
2631         filter->enables = en;
2632
2633         return 0;
2634 }
2635
2636 static struct bnxt_filter_info *
2637 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2638                 struct bnxt_vnic_info **mvnic)
2639 {
2640         struct bnxt_filter_info *mf = NULL;
2641         int i;
2642
2643         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2644                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2645
2646                 STAILQ_FOREACH(mf, &vnic->filter, next) {
2647                         if (mf->filter_type == nf->filter_type &&
2648                             mf->flags == nf->flags &&
2649                             mf->src_port == nf->src_port &&
2650                             mf->src_port_mask == nf->src_port_mask &&
2651                             mf->dst_port == nf->dst_port &&
2652                             mf->dst_port_mask == nf->dst_port_mask &&
2653                             mf->ip_protocol == nf->ip_protocol &&
2654                             mf->ip_addr_type == nf->ip_addr_type &&
2655                             mf->ethertype == nf->ethertype &&
2656                             mf->vni == nf->vni &&
2657                             mf->tunnel_type == nf->tunnel_type &&
2658                             mf->l2_ovlan == nf->l2_ovlan &&
2659                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2660                             mf->l2_ivlan == nf->l2_ivlan &&
2661                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2662                             !memcmp(mf->l2_addr, nf->l2_addr,
2663                                     RTE_ETHER_ADDR_LEN) &&
2664                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2665                                     RTE_ETHER_ADDR_LEN) &&
2666                             !memcmp(mf->src_macaddr, nf->src_macaddr,
2667                                     RTE_ETHER_ADDR_LEN) &&
2668                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2669                                     RTE_ETHER_ADDR_LEN) &&
2670                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2671                                     sizeof(nf->src_ipaddr)) &&
2672                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2673                                     sizeof(nf->src_ipaddr_mask)) &&
2674                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2675                                     sizeof(nf->dst_ipaddr)) &&
2676                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2677                                     sizeof(nf->dst_ipaddr_mask))) {
2678                                 if (mvnic)
2679                                         *mvnic = vnic;
2680                                 return mf;
2681                         }
2682                 }
2683         }
2684         return NULL;
2685 }
2686
2687 static int
2688 bnxt_fdir_filter(struct rte_eth_dev *dev,
2689                  enum rte_filter_op filter_op,
2690                  void *arg)
2691 {
2692         struct bnxt *bp = dev->data->dev_private;
2693         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
2694         struct bnxt_filter_info *filter, *match;
2695         struct bnxt_vnic_info *vnic, *mvnic;
2696         int ret = 0, i;
2697
2698         if (filter_op == RTE_ETH_FILTER_NOP)
2699                 return 0;
2700
2701         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2702                 return -EINVAL;
2703
2704         switch (filter_op) {
2705         case RTE_ETH_FILTER_ADD:
2706         case RTE_ETH_FILTER_DELETE:
2707                 /* FALLTHROUGH */
2708                 filter = bnxt_get_unused_filter(bp);
2709                 if (filter == NULL) {
2710                         PMD_DRV_LOG(ERR,
2711                                 "Not enough resources for a new flow.\n");
2712                         return -ENOMEM;
2713                 }
2714
2715                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2716                 if (ret != 0)
2717                         goto free_filter;
2718                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2719
2720                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2721                         vnic = &bp->vnic_info[0];
2722                 else
2723                         vnic = &bp->vnic_info[fdir->action.rx_queue];
2724
2725                 match = bnxt_match_fdir(bp, filter, &mvnic);
2726                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2727                         if (match->dst_id == vnic->fw_vnic_id) {
2728                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2729                                 ret = -EEXIST;
2730                                 goto free_filter;
2731                         } else {
2732                                 match->dst_id = vnic->fw_vnic_id;
2733                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
2734                                                                   match->dst_id,
2735                                                                   match);
2736                                 STAILQ_REMOVE(&mvnic->filter, match,
2737                                               bnxt_filter_info, next);
2738                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2739                                 PMD_DRV_LOG(ERR,
2740                                         "Filter with matching pattern exist\n");
2741                                 PMD_DRV_LOG(ERR,
2742                                         "Updated it to new destination q\n");
2743                                 goto free_filter;
2744                         }
2745                 }
2746                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2747                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2748                         ret = -ENOENT;
2749                         goto free_filter;
2750                 }
2751
2752                 if (filter_op == RTE_ETH_FILTER_ADD) {
2753                         ret = bnxt_hwrm_set_ntuple_filter(bp,
2754                                                           filter->dst_id,
2755                                                           filter);
2756                         if (ret)
2757                                 goto free_filter;
2758                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2759                 } else {
2760                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2761                         STAILQ_REMOVE(&vnic->filter, match,
2762                                       bnxt_filter_info, next);
2763                         bnxt_free_filter(bp, match);
2764                         filter->fw_l2_filter_id = -1;
2765                         bnxt_free_filter(bp, filter);
2766                 }
2767                 break;
2768         case RTE_ETH_FILTER_FLUSH:
2769                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2770                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2771
2772                         STAILQ_FOREACH(filter, &vnic->filter, next) {
2773                                 if (filter->filter_type ==
2774                                     HWRM_CFA_NTUPLE_FILTER) {
2775                                         ret =
2776                                         bnxt_hwrm_clear_ntuple_filter(bp,
2777                                                                       filter);
2778                                         STAILQ_REMOVE(&vnic->filter, filter,
2779                                                       bnxt_filter_info, next);
2780                                 }
2781                         }
2782                 }
2783                 return ret;
2784         case RTE_ETH_FILTER_UPDATE:
2785         case RTE_ETH_FILTER_STATS:
2786         case RTE_ETH_FILTER_INFO:
2787                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2788                 break;
2789         default:
2790                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2791                 ret = -EINVAL;
2792                 break;
2793         }
2794         return ret;
2795
2796 free_filter:
2797         filter->fw_l2_filter_id = -1;
2798         bnxt_free_filter(bp, filter);
2799         return ret;
2800 }
2801
2802 static int
2803 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2804                     enum rte_filter_type filter_type,
2805                     enum rte_filter_op filter_op, void *arg)
2806 {
2807         int ret = 0;
2808
2809         switch (filter_type) {
2810         case RTE_ETH_FILTER_TUNNEL:
2811                 PMD_DRV_LOG(ERR,
2812                         "filter type: %d: To be implemented\n", filter_type);
2813                 break;
2814         case RTE_ETH_FILTER_FDIR:
2815                 ret = bnxt_fdir_filter(dev, filter_op, arg);
2816                 break;
2817         case RTE_ETH_FILTER_NTUPLE:
2818                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2819                 break;
2820         case RTE_ETH_FILTER_ETHERTYPE:
2821                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2822                 break;
2823         case RTE_ETH_FILTER_GENERIC:
2824                 if (filter_op != RTE_ETH_FILTER_GET)
2825                         return -EINVAL;
2826                 *(const void **)arg = &bnxt_flow_ops;
2827                 break;
2828         default:
2829                 PMD_DRV_LOG(ERR,
2830                         "Filter type (%d) not supported", filter_type);
2831                 ret = -EINVAL;
2832                 break;
2833         }
2834         return ret;
2835 }
2836
2837 static const uint32_t *
2838 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2839 {
2840         static const uint32_t ptypes[] = {
2841                 RTE_PTYPE_L2_ETHER_VLAN,
2842                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2843                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2844                 RTE_PTYPE_L4_ICMP,
2845                 RTE_PTYPE_L4_TCP,
2846                 RTE_PTYPE_L4_UDP,
2847                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2848                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2849                 RTE_PTYPE_INNER_L4_ICMP,
2850                 RTE_PTYPE_INNER_L4_TCP,
2851                 RTE_PTYPE_INNER_L4_UDP,
2852                 RTE_PTYPE_UNKNOWN
2853         };
2854
2855         if (!dev->rx_pkt_burst)
2856                 return NULL;
2857
2858         return ptypes;
2859 }
2860
2861 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2862                          int reg_win)
2863 {
2864         uint32_t reg_base = *reg_arr & 0xfffff000;
2865         uint32_t win_off;
2866         int i;
2867
2868         for (i = 0; i < count; i++) {
2869                 if ((reg_arr[i] & 0xfffff000) != reg_base)
2870                         return -ERANGE;
2871         }
2872         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2873         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
2874         return 0;
2875 }
2876
2877 static int bnxt_map_ptp_regs(struct bnxt *bp)
2878 {
2879         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2880         uint32_t *reg_arr;
2881         int rc, i;
2882
2883         reg_arr = ptp->rx_regs;
2884         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2885         if (rc)
2886                 return rc;
2887
2888         reg_arr = ptp->tx_regs;
2889         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2890         if (rc)
2891                 return rc;
2892
2893         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2894                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2895
2896         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2897                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2898
2899         return 0;
2900 }
2901
2902 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2903 {
2904         rte_write32(0, (uint8_t *)bp->bar0 +
2905                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
2906         rte_write32(0, (uint8_t *)bp->bar0 +
2907                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
2908 }
2909
2910 static uint64_t bnxt_cc_read(struct bnxt *bp)
2911 {
2912         uint64_t ns;
2913
2914         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2915                               BNXT_GRCPF_REG_SYNC_TIME));
2916         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2917                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2918         return ns;
2919 }
2920
2921 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2922 {
2923         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2924         uint32_t fifo;
2925
2926         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2927                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2928         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2929                 return -EAGAIN;
2930
2931         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2932                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2933         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2934                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2935         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2936                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2937
2938         return 0;
2939 }
2940
2941 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2942 {
2943         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2944         struct bnxt_pf_info *pf = &bp->pf;
2945         uint16_t port_id;
2946         uint32_t fifo;
2947
2948         if (!ptp)
2949                 return -ENODEV;
2950
2951         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2952                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2953         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2954                 return -EAGAIN;
2955
2956         port_id = pf->port_id;
2957         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2958                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
2959
2960         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2961                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2962         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
2963 /*              bnxt_clr_rx_ts(bp);       TBD  */
2964                 return -EBUSY;
2965         }
2966
2967         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2968                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
2969         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2970                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
2971
2972         return 0;
2973 }
2974
2975 static int
2976 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
2977 {
2978         uint64_t ns;
2979         struct bnxt *bp = dev->data->dev_private;
2980         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2981
2982         if (!ptp)
2983                 return 0;
2984
2985         ns = rte_timespec_to_ns(ts);
2986         /* Set the timecounters to a new value. */
2987         ptp->tc.nsec = ns;
2988
2989         return 0;
2990 }
2991
2992 static int
2993 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
2994 {
2995         uint64_t ns, systime_cycles;
2996         struct bnxt *bp = dev->data->dev_private;
2997         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2998
2999         if (!ptp)
3000                 return 0;
3001
3002         systime_cycles = bnxt_cc_read(bp);
3003         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3004         *ts = rte_ns_to_timespec(ns);
3005
3006         return 0;
3007 }
3008 static int
3009 bnxt_timesync_enable(struct rte_eth_dev *dev)
3010 {
3011         struct bnxt *bp = dev->data->dev_private;
3012         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3013         uint32_t shift = 0;
3014
3015         if (!ptp)
3016                 return 0;
3017
3018         ptp->rx_filter = 1;
3019         ptp->tx_tstamp_en = 1;
3020         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3021
3022         if (!bnxt_hwrm_ptp_cfg(bp))
3023                 bnxt_map_ptp_regs(bp);
3024
3025         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3026         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3027         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3028
3029         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3030         ptp->tc.cc_shift = shift;
3031         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3032
3033         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3034         ptp->rx_tstamp_tc.cc_shift = shift;
3035         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3036
3037         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3038         ptp->tx_tstamp_tc.cc_shift = shift;
3039         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3040
3041         return 0;
3042 }
3043
3044 static int
3045 bnxt_timesync_disable(struct rte_eth_dev *dev)
3046 {
3047         struct bnxt *bp = dev->data->dev_private;
3048         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3049
3050         if (!ptp)
3051                 return 0;
3052
3053         ptp->rx_filter = 0;
3054         ptp->tx_tstamp_en = 0;
3055         ptp->rxctl = 0;
3056
3057         bnxt_hwrm_ptp_cfg(bp);
3058
3059         bnxt_unmap_ptp_regs(bp);
3060
3061         return 0;
3062 }
3063
3064 static int
3065 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3066                                  struct timespec *timestamp,
3067                                  uint32_t flags __rte_unused)
3068 {
3069         struct bnxt *bp = dev->data->dev_private;
3070         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3071         uint64_t rx_tstamp_cycles = 0;
3072         uint64_t ns;
3073
3074         if (!ptp)
3075                 return 0;
3076
3077         bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3078         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3079         *timestamp = rte_ns_to_timespec(ns);
3080         return  0;
3081 }
3082
3083 static int
3084 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3085                                  struct timespec *timestamp)
3086 {
3087         struct bnxt *bp = dev->data->dev_private;
3088         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3089         uint64_t tx_tstamp_cycles = 0;
3090         uint64_t ns;
3091
3092         if (!ptp)
3093                 return 0;
3094
3095         bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3096         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3097         *timestamp = rte_ns_to_timespec(ns);
3098
3099         return 0;
3100 }
3101
3102 static int
3103 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3104 {
3105         struct bnxt *bp = dev->data->dev_private;
3106         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3107
3108         if (!ptp)
3109                 return 0;
3110
3111         ptp->tc.nsec += delta;
3112
3113         return 0;
3114 }
3115
3116 static int
3117 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3118 {
3119         struct bnxt *bp = dev->data->dev_private;
3120         int rc;
3121         uint32_t dir_entries;
3122         uint32_t entry_length;
3123
3124         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3125                 bp->pdev->addr.domain, bp->pdev->addr.bus,
3126                 bp->pdev->addr.devid, bp->pdev->addr.function);
3127
3128         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3129         if (rc != 0)
3130                 return rc;
3131
3132         return dir_entries * entry_length;
3133 }
3134
3135 static int
3136 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3137                 struct rte_dev_eeprom_info *in_eeprom)
3138 {
3139         struct bnxt *bp = dev->data->dev_private;
3140         uint32_t index;
3141         uint32_t offset;
3142
3143         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3144                 "len = %d\n", bp->pdev->addr.domain,
3145                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3146                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3147
3148         if (in_eeprom->offset == 0) /* special offset value to get directory */
3149                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3150                                                 in_eeprom->data);
3151
3152         index = in_eeprom->offset >> 24;
3153         offset = in_eeprom->offset & 0xffffff;
3154
3155         if (index != 0)
3156                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3157                                            in_eeprom->length, in_eeprom->data);
3158
3159         return 0;
3160 }
3161
3162 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3163 {
3164         switch (dir_type) {
3165         case BNX_DIR_TYPE_CHIMP_PATCH:
3166         case BNX_DIR_TYPE_BOOTCODE:
3167         case BNX_DIR_TYPE_BOOTCODE_2:
3168         case BNX_DIR_TYPE_APE_FW:
3169         case BNX_DIR_TYPE_APE_PATCH:
3170         case BNX_DIR_TYPE_KONG_FW:
3171         case BNX_DIR_TYPE_KONG_PATCH:
3172         case BNX_DIR_TYPE_BONO_FW:
3173         case BNX_DIR_TYPE_BONO_PATCH:
3174                 /* FALLTHROUGH */
3175                 return true;
3176         }
3177
3178         return false;
3179 }
3180
3181 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3182 {
3183         switch (dir_type) {
3184         case BNX_DIR_TYPE_AVS:
3185         case BNX_DIR_TYPE_EXP_ROM_MBA:
3186         case BNX_DIR_TYPE_PCIE:
3187         case BNX_DIR_TYPE_TSCF_UCODE:
3188         case BNX_DIR_TYPE_EXT_PHY:
3189         case BNX_DIR_TYPE_CCM:
3190         case BNX_DIR_TYPE_ISCSI_BOOT:
3191         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3192         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3193                 /* FALLTHROUGH */
3194                 return true;
3195         }
3196
3197         return false;
3198 }
3199
3200 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3201 {
3202         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3203                 bnxt_dir_type_is_other_exec_format(dir_type);
3204 }
3205
3206 static int
3207 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3208                 struct rte_dev_eeprom_info *in_eeprom)
3209 {
3210         struct bnxt *bp = dev->data->dev_private;
3211         uint8_t index, dir_op;
3212         uint16_t type, ext, ordinal, attr;
3213
3214         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3215                 "len = %d\n", bp->pdev->addr.domain,
3216                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3217                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3218
3219         if (!BNXT_PF(bp)) {
3220                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3221                 return -EINVAL;
3222         }
3223
3224         type = in_eeprom->magic >> 16;
3225
3226         if (type == 0xffff) { /* special value for directory operations */
3227                 index = in_eeprom->magic & 0xff;
3228                 dir_op = in_eeprom->magic >> 8;
3229                 if (index == 0)
3230                         return -EINVAL;
3231                 switch (dir_op) {
3232                 case 0x0e: /* erase */
3233                         if (in_eeprom->offset != ~in_eeprom->magic)
3234                                 return -EINVAL;
3235                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3236                 default:
3237                         return -EINVAL;
3238                 }
3239         }
3240
3241         /* Create or re-write an NVM item: */
3242         if (bnxt_dir_type_is_executable(type) == true)
3243                 return -EOPNOTSUPP;
3244         ext = in_eeprom->magic & 0xffff;
3245         ordinal = in_eeprom->offset >> 16;
3246         attr = in_eeprom->offset & 0xffff;
3247
3248         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3249                                      in_eeprom->data, in_eeprom->length);
3250 }
3251
3252 /*
3253  * Initialization
3254  */
3255
3256 static const struct eth_dev_ops bnxt_dev_ops = {
3257         .dev_infos_get = bnxt_dev_info_get_op,
3258         .dev_close = bnxt_dev_close_op,
3259         .dev_configure = bnxt_dev_configure_op,
3260         .dev_start = bnxt_dev_start_op,
3261         .dev_stop = bnxt_dev_stop_op,
3262         .dev_set_link_up = bnxt_dev_set_link_up_op,
3263         .dev_set_link_down = bnxt_dev_set_link_down_op,
3264         .stats_get = bnxt_stats_get_op,
3265         .stats_reset = bnxt_stats_reset_op,
3266         .rx_queue_setup = bnxt_rx_queue_setup_op,
3267         .rx_queue_release = bnxt_rx_queue_release_op,
3268         .tx_queue_setup = bnxt_tx_queue_setup_op,
3269         .tx_queue_release = bnxt_tx_queue_release_op,
3270         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3271         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3272         .reta_update = bnxt_reta_update_op,
3273         .reta_query = bnxt_reta_query_op,
3274         .rss_hash_update = bnxt_rss_hash_update_op,
3275         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3276         .link_update = bnxt_link_update_op,
3277         .promiscuous_enable = bnxt_promiscuous_enable_op,
3278         .promiscuous_disable = bnxt_promiscuous_disable_op,
3279         .allmulticast_enable = bnxt_allmulticast_enable_op,
3280         .allmulticast_disable = bnxt_allmulticast_disable_op,
3281         .mac_addr_add = bnxt_mac_addr_add_op,
3282         .mac_addr_remove = bnxt_mac_addr_remove_op,
3283         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3284         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3285         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3286         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3287         .vlan_filter_set = bnxt_vlan_filter_set_op,
3288         .vlan_offload_set = bnxt_vlan_offload_set_op,
3289         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3290         .mtu_set = bnxt_mtu_set_op,
3291         .mac_addr_set = bnxt_set_default_mac_addr_op,
3292         .xstats_get = bnxt_dev_xstats_get_op,
3293         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3294         .xstats_reset = bnxt_dev_xstats_reset_op,
3295         .fw_version_get = bnxt_fw_version_get,
3296         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3297         .rxq_info_get = bnxt_rxq_info_get_op,
3298         .txq_info_get = bnxt_txq_info_get_op,
3299         .dev_led_on = bnxt_dev_led_on_op,
3300         .dev_led_off = bnxt_dev_led_off_op,
3301         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3302         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3303         .rx_queue_count = bnxt_rx_queue_count_op,
3304         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3305         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3306         .rx_queue_start = bnxt_rx_queue_start,
3307         .rx_queue_stop = bnxt_rx_queue_stop,
3308         .tx_queue_start = bnxt_tx_queue_start,
3309         .tx_queue_stop = bnxt_tx_queue_stop,
3310         .filter_ctrl = bnxt_filter_ctrl_op,
3311         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3312         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3313         .get_eeprom           = bnxt_get_eeprom_op,
3314         .set_eeprom           = bnxt_set_eeprom_op,
3315         .timesync_enable      = bnxt_timesync_enable,
3316         .timesync_disable     = bnxt_timesync_disable,
3317         .timesync_read_time   = bnxt_timesync_read_time,
3318         .timesync_write_time   = bnxt_timesync_write_time,
3319         .timesync_adjust_time = bnxt_timesync_adjust_time,
3320         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3321         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3322 };
3323
3324 static bool bnxt_vf_pciid(uint16_t id)
3325 {
3326         if (id == BROADCOM_DEV_ID_57304_VF ||
3327             id == BROADCOM_DEV_ID_57406_VF ||
3328             id == BROADCOM_DEV_ID_5731X_VF ||
3329             id == BROADCOM_DEV_ID_5741X_VF ||
3330             id == BROADCOM_DEV_ID_57414_VF ||
3331             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3332             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3333             id == BROADCOM_DEV_ID_58802_VF ||
3334             id == BROADCOM_DEV_ID_57500_VF1 ||
3335             id == BROADCOM_DEV_ID_57500_VF2)
3336                 return true;
3337         return false;
3338 }
3339
3340 bool bnxt_stratus_device(struct bnxt *bp)
3341 {
3342         uint16_t id = bp->pdev->id.device_id;
3343
3344         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3345             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3346             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3347                 return true;
3348         return false;
3349 }
3350
3351 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3352 {
3353         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3354         struct bnxt *bp = eth_dev->data->dev_private;
3355
3356         /* enable device (incl. PCI PM wakeup), and bus-mastering */
3357         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3358         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3359         if (!bp->bar0 || !bp->doorbell_base) {
3360                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
3361                 return -ENODEV;
3362         }
3363
3364         bp->eth_dev = eth_dev;
3365         bp->pdev = pci_dev;
3366
3367         return 0;
3368 }
3369
3370 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
3371                                   struct bnxt_ctx_pg_info *ctx_pg,
3372                                   uint32_t mem_size,
3373                                   const char *suffix,
3374                                   uint16_t idx)
3375 {
3376         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
3377         const struct rte_memzone *mz = NULL;
3378         char mz_name[RTE_MEMZONE_NAMESIZE];
3379         rte_iova_t mz_phys_addr;
3380         uint64_t valid_bits = 0;
3381         uint32_t sz;
3382         int i;
3383
3384         if (!mem_size)
3385                 return 0;
3386
3387         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
3388                          BNXT_PAGE_SIZE;
3389         rmem->page_size = BNXT_PAGE_SIZE;
3390         rmem->pg_arr = ctx_pg->ctx_pg_arr;
3391         rmem->dma_arr = ctx_pg->ctx_dma_arr;
3392         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
3393
3394         valid_bits = PTU_PTE_VALID;
3395
3396         if (rmem->nr_pages > 1) {
3397                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_pg_tbl%s_%x",
3398                          suffix, idx);
3399                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3400                 mz = rte_memzone_lookup(mz_name);
3401                 if (!mz) {
3402                         mz = rte_memzone_reserve_aligned(mz_name,
3403                                                 rmem->nr_pages * 8,
3404                                                 SOCKET_ID_ANY,
3405                                                 RTE_MEMZONE_2MB |
3406                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
3407                                                 RTE_MEMZONE_IOVA_CONTIG,
3408                                                 BNXT_PAGE_SIZE);
3409                         if (mz == NULL)
3410                                 return -ENOMEM;
3411                 }
3412
3413                 memset(mz->addr, 0, mz->len);
3414                 mz_phys_addr = mz->iova;
3415                 if ((unsigned long)mz->addr == mz_phys_addr) {
3416                         PMD_DRV_LOG(WARNING,
3417                                 "Memzone physical address same as virtual.\n");
3418                         PMD_DRV_LOG(WARNING,
3419                                     "Using rte_mem_virt2iova()\n");
3420                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3421                         if (mz_phys_addr == RTE_BAD_IOVA) {
3422                                 PMD_DRV_LOG(ERR,
3423                                         "unable to map addr to phys memory\n");
3424                                 return -ENOMEM;
3425                         }
3426                 }
3427                 rte_mem_lock_page(((char *)mz->addr));
3428
3429                 rmem->pg_tbl = mz->addr;
3430                 rmem->pg_tbl_map = mz_phys_addr;
3431                 rmem->pg_tbl_mz = mz;
3432         }
3433
3434         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x", suffix, idx);
3435         mz = rte_memzone_lookup(mz_name);
3436         if (!mz) {
3437                 mz = rte_memzone_reserve_aligned(mz_name,
3438                                                  mem_size,
3439                                                  SOCKET_ID_ANY,
3440                                                  RTE_MEMZONE_1GB |
3441                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
3442                                                  RTE_MEMZONE_IOVA_CONTIG,
3443                                                  BNXT_PAGE_SIZE);
3444                 if (mz == NULL)
3445                         return -ENOMEM;
3446         }
3447
3448         memset(mz->addr, 0, mz->len);
3449         mz_phys_addr = mz->iova;
3450         if ((unsigned long)mz->addr == mz_phys_addr) {
3451                 PMD_DRV_LOG(WARNING,
3452                             "Memzone physical address same as virtual.\n");
3453                 PMD_DRV_LOG(WARNING,
3454                             "Using rte_mem_virt2iova()\n");
3455                 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
3456                         rte_mem_lock_page(((char *)mz->addr) + sz);
3457                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3458                 if (mz_phys_addr == RTE_BAD_IOVA) {
3459                         PMD_DRV_LOG(ERR,
3460                                     "unable to map addr to phys memory\n");
3461                         return -ENOMEM;
3462                 }
3463         }
3464
3465         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
3466                 rte_mem_lock_page(((char *)mz->addr) + sz);
3467                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
3468                 rmem->dma_arr[i] = mz_phys_addr + sz;
3469
3470                 if (rmem->nr_pages > 1) {
3471                         if (i == rmem->nr_pages - 2 &&
3472                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3473                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
3474                         else if (i == rmem->nr_pages - 1 &&
3475                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3476                                 valid_bits |= PTU_PTE_LAST;
3477
3478                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
3479                                                            valid_bits);
3480                 }
3481         }
3482
3483         rmem->mz = mz;
3484         if (rmem->vmem_size)
3485                 rmem->vmem = (void **)mz->addr;
3486         rmem->dma_arr[0] = mz_phys_addr;
3487         return 0;
3488 }
3489
3490 static void bnxt_free_ctx_mem(struct bnxt *bp)
3491 {
3492         int i;
3493
3494         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
3495                 return;
3496
3497         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
3498         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
3499         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
3500         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
3501         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
3502         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
3503         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
3504         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
3505         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
3506         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
3507         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
3508
3509         for (i = 0; i < BNXT_MAX_Q; i++) {
3510                 if (bp->ctx->tqm_mem[i])
3511                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
3512         }
3513
3514         rte_free(bp->ctx);
3515         bp->ctx = NULL;
3516 }
3517
3518 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
3519
3520 #define min_t(type, x, y) ({                    \
3521         type __min1 = (x);                      \
3522         type __min2 = (y);                      \
3523         __min1 < __min2 ? __min1 : __min2; })
3524
3525 #define max_t(type, x, y) ({                    \
3526         type __max1 = (x);                      \
3527         type __max2 = (y);                      \
3528         __max1 > __max2 ? __max1 : __max2; })
3529
3530 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
3531
3532 int bnxt_alloc_ctx_mem(struct bnxt *bp)
3533 {
3534         struct bnxt_ctx_pg_info *ctx_pg;
3535         struct bnxt_ctx_mem_info *ctx;
3536         uint32_t mem_size, ena, entries;
3537         int i, rc;
3538
3539         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
3540         if (rc) {
3541                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
3542                 return rc;
3543         }
3544         ctx = bp->ctx;
3545         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
3546                 return 0;
3547
3548         ctx_pg = &ctx->qp_mem;
3549         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
3550         mem_size = ctx->qp_entry_size * ctx_pg->entries;
3551         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
3552         if (rc)
3553                 return rc;
3554
3555         ctx_pg = &ctx->srq_mem;
3556         ctx_pg->entries = ctx->srq_max_l2_entries;
3557         mem_size = ctx->srq_entry_size * ctx_pg->entries;
3558         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
3559         if (rc)
3560                 return rc;
3561
3562         ctx_pg = &ctx->cq_mem;
3563         ctx_pg->entries = ctx->cq_max_l2_entries;
3564         mem_size = ctx->cq_entry_size * ctx_pg->entries;
3565         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
3566         if (rc)
3567                 return rc;
3568
3569         ctx_pg = &ctx->vnic_mem;
3570         ctx_pg->entries = ctx->vnic_max_vnic_entries +
3571                 ctx->vnic_max_ring_table_entries;
3572         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
3573         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
3574         if (rc)
3575                 return rc;
3576
3577         ctx_pg = &ctx->stat_mem;
3578         ctx_pg->entries = ctx->stat_max_entries;
3579         mem_size = ctx->stat_entry_size * ctx_pg->entries;
3580         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
3581         if (rc)
3582                 return rc;
3583
3584         entries = ctx->qp_max_l2_entries;
3585         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
3586         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
3587                           ctx->tqm_max_entries_per_ring);
3588         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
3589                 ctx_pg = ctx->tqm_mem[i];
3590                 /* use min tqm entries for now. */
3591                 ctx_pg->entries = entries;
3592                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
3593                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
3594                 if (rc)
3595                         return rc;
3596                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
3597         }
3598
3599         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
3600         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
3601         if (rc)
3602                 PMD_DRV_LOG(ERR,
3603                             "Failed to configure context mem: rc = %d\n", rc);
3604         else
3605                 ctx->flags |= BNXT_CTX_FLAG_INITED;
3606
3607         return rc;
3608 }
3609
3610 static int bnxt_alloc_stats_mem(struct bnxt *bp)
3611 {
3612         struct rte_pci_device *pci_dev = bp->pdev;
3613         char mz_name[RTE_MEMZONE_NAMESIZE];
3614         const struct rte_memzone *mz = NULL;
3615         uint32_t total_alloc_len;
3616         rte_iova_t mz_phys_addr;
3617
3618         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
3619                 return 0;
3620
3621         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3622                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
3623                  pci_dev->addr.bus, pci_dev->addr.devid,
3624                  pci_dev->addr.function, "rx_port_stats");
3625         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3626         mz = rte_memzone_lookup(mz_name);
3627         total_alloc_len =
3628                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
3629                                        sizeof(struct rx_port_stats_ext) + 512);
3630         if (!mz) {
3631                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
3632                                          SOCKET_ID_ANY,
3633                                          RTE_MEMZONE_2MB |
3634                                          RTE_MEMZONE_SIZE_HINT_ONLY |
3635                                          RTE_MEMZONE_IOVA_CONTIG);
3636                 if (mz == NULL)
3637                         return -ENOMEM;
3638         }
3639         memset(mz->addr, 0, mz->len);
3640         mz_phys_addr = mz->iova;
3641         if ((unsigned long)mz->addr == mz_phys_addr) {
3642                 PMD_DRV_LOG(WARNING,
3643                             "Memzone physical address same as virtual.\n");
3644                 PMD_DRV_LOG(WARNING,
3645                             "Using rte_mem_virt2iova()\n");
3646                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3647                 if (mz_phys_addr == RTE_BAD_IOVA) {
3648                         PMD_DRV_LOG(ERR,
3649                                     "Can't map address to physical memory\n");
3650                         return -ENOMEM;
3651                 }
3652         }
3653
3654         bp->rx_mem_zone = (const void *)mz;
3655         bp->hw_rx_port_stats = mz->addr;
3656         bp->hw_rx_port_stats_map = mz_phys_addr;
3657
3658         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3659                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
3660                  pci_dev->addr.bus, pci_dev->addr.devid,
3661                  pci_dev->addr.function, "tx_port_stats");
3662         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3663         mz = rte_memzone_lookup(mz_name);
3664         total_alloc_len =
3665                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
3666                                        sizeof(struct tx_port_stats_ext) + 512);
3667         if (!mz) {
3668                 mz = rte_memzone_reserve(mz_name,
3669                                          total_alloc_len,
3670                                          SOCKET_ID_ANY,
3671                                          RTE_MEMZONE_2MB |
3672                                          RTE_MEMZONE_SIZE_HINT_ONLY |
3673                                          RTE_MEMZONE_IOVA_CONTIG);
3674                 if (mz == NULL)
3675                         return -ENOMEM;
3676         }
3677         memset(mz->addr, 0, mz->len);
3678         mz_phys_addr = mz->iova;
3679         if ((unsigned long)mz->addr == mz_phys_addr) {
3680                 PMD_DRV_LOG(WARNING,
3681                             "Memzone physical address same as virtual\n");
3682                 PMD_DRV_LOG(WARNING,
3683                             "Using rte_mem_virt2iova()\n");
3684                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3685                 if (mz_phys_addr == RTE_BAD_IOVA) {
3686                         PMD_DRV_LOG(ERR,
3687                                     "Can't map address to physical memory\n");
3688                         return -ENOMEM;
3689                 }
3690         }
3691
3692         bp->tx_mem_zone = (const void *)mz;
3693         bp->hw_tx_port_stats = mz->addr;
3694         bp->hw_tx_port_stats_map = mz_phys_addr;
3695         bp->flags |= BNXT_FLAG_PORT_STATS;
3696
3697         /* Display extended statistics if FW supports it */
3698         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
3699             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
3700             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
3701                 return 0;
3702
3703         bp->hw_rx_port_stats_ext = (void *)
3704                 ((uint8_t *)bp->hw_rx_port_stats +
3705                  sizeof(struct rx_port_stats));
3706         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
3707                 sizeof(struct rx_port_stats);
3708         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
3709
3710         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
3711             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
3712                 bp->hw_tx_port_stats_ext = (void *)
3713                         ((uint8_t *)bp->hw_tx_port_stats +
3714                          sizeof(struct tx_port_stats));
3715                 bp->hw_tx_port_stats_ext_map =
3716                         bp->hw_tx_port_stats_map +
3717                         sizeof(struct tx_port_stats);
3718                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
3719         }
3720
3721         return 0;
3722 }
3723
3724 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
3725 {
3726         struct bnxt *bp = eth_dev->data->dev_private;
3727         int rc = 0;
3728
3729         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3730                                                RTE_ETHER_ADDR_LEN *
3731                                                bp->max_l2_ctx,
3732                                                0);
3733         if (eth_dev->data->mac_addrs == NULL) {
3734                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
3735                 return -ENOMEM;
3736         }
3737
3738         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
3739                 if (BNXT_PF(bp))
3740                         return -EINVAL;
3741
3742                 /* Generate a random MAC address, if none was assigned by PF */
3743                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
3744                 bnxt_eth_hw_addr_random(bp->mac_addr);
3745                 PMD_DRV_LOG(INFO,
3746                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
3747                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
3748                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
3749
3750                 rc = bnxt_hwrm_set_mac(bp);
3751                 if (!rc)
3752                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
3753                                RTE_ETHER_ADDR_LEN);
3754                 return rc;
3755         }
3756
3757         /* Copy the permanent MAC from the FUNC_QCAPS response */
3758         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
3759         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
3760
3761         return rc;
3762 }
3763
3764 #define ALLOW_FUNC(x)   \
3765         { \
3766                 uint32_t arg = (x); \
3767                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3768                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3769         }
3770 static int
3771 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3772 {
3773         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3774         static int version_printed;
3775         struct bnxt *bp;
3776         uint16_t mtu;
3777         int rc;
3778
3779         if (version_printed++ == 0)
3780                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
3781
3782         rte_eth_copy_pci_info(eth_dev, pci_dev);
3783
3784         bp = eth_dev->data->dev_private;
3785
3786         bp->dev_stopped = 1;
3787
3788         eth_dev->dev_ops = &bnxt_dev_ops;
3789         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3790         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3791
3792         /*
3793          * For secondary processes, we don't initialise any further
3794          * as primary has already done this work.
3795          */
3796         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3797                 return 0;
3798
3799         if (bnxt_vf_pciid(pci_dev->id.device_id))
3800                 bp->flags |= BNXT_FLAG_VF;
3801
3802         if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
3803             pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
3804             pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
3805             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 ||
3806             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2)
3807                 bp->flags |= BNXT_FLAG_THOR_CHIP;
3808
3809         rc = bnxt_init_board(eth_dev);
3810         if (rc) {
3811                 PMD_DRV_LOG(ERR,
3812                         "Board initialization failed rc: %x\n", rc);
3813                 goto error;
3814         }
3815
3816         rc = bnxt_alloc_hwrm_resources(bp);
3817         if (rc) {
3818                 PMD_DRV_LOG(ERR,
3819                         "hwrm resource allocation failure rc: %x\n", rc);
3820                 goto error_free;
3821         }
3822         rc = bnxt_hwrm_ver_get(bp);
3823         if (rc)
3824                 goto error_free;
3825
3826         rc = bnxt_hwrm_func_reset(bp);
3827         if (rc) {
3828                 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc);
3829                 rc = -EIO;
3830                 goto error_free;
3831         }
3832
3833         rc = bnxt_hwrm_queue_qportcfg(bp);
3834         if (rc) {
3835                 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n");
3836                 goto error_free;
3837         }
3838         /* Get the MAX capabilities for this function */
3839         rc = bnxt_hwrm_func_qcaps(bp);
3840         if (rc) {
3841                 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc);
3842                 goto error_free;
3843         }
3844
3845         rc = bnxt_alloc_stats_mem(bp);
3846         if (rc)
3847                 goto error_free;
3848
3849         if (bp->max_tx_rings == 0) {
3850                 PMD_DRV_LOG(ERR, "No TX rings available!\n");
3851                 rc = -EBUSY;
3852                 goto error_free;
3853         }
3854
3855         rc = bnxt_setup_mac_addr(eth_dev);
3856         if (rc)
3857                 goto error_free;
3858
3859         /* THOR does not support ring groups.
3860          * But we will use the array to save RSS context IDs.
3861          */
3862         if (BNXT_CHIP_THOR(bp)) {
3863                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
3864         } else if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3865                 /* 1 ring is for default completion ring */
3866                 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
3867                 rc = -ENOSPC;
3868                 goto error_free;
3869         }
3870
3871         if (BNXT_HAS_RING_GRPS(bp)) {
3872                 bp->grp_info = rte_zmalloc("bnxt_grp_info",
3873                                         sizeof(*bp->grp_info) *
3874                                                 bp->max_ring_grps, 0);
3875                 if (!bp->grp_info) {
3876                         PMD_DRV_LOG(ERR,
3877                                 "Failed to alloc %zu bytes for grp info tbl.\n",
3878                                 sizeof(*bp->grp_info) * bp->max_ring_grps);
3879                         rc = -ENOMEM;
3880                         goto error_free;
3881                 }
3882         }
3883
3884         /* Forward all requests if firmware is new enough */
3885         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3886             (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3887             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3888                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3889         } else {
3890                 PMD_DRV_LOG(WARNING,
3891                         "Firmware too old for VF mailbox functionality\n");
3892                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3893         }
3894
3895         /*
3896          * The following are used for driver cleanup.  If we disallow these,
3897          * VF drivers can't clean up cleanly.
3898          */
3899         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3900         ALLOW_FUNC(HWRM_VNIC_FREE);
3901         ALLOW_FUNC(HWRM_RING_FREE);
3902         ALLOW_FUNC(HWRM_RING_GRP_FREE);
3903         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3904         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3905         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3906         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3907         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3908         rc = bnxt_hwrm_func_driver_register(bp);
3909         if (rc) {
3910                 PMD_DRV_LOG(ERR,
3911                         "Failed to register driver");
3912                 rc = -EBUSY;
3913                 goto error_free;
3914         }
3915
3916         PMD_DRV_LOG(INFO,
3917                 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3918                 pci_dev->mem_resource[0].phys_addr,
3919                 pci_dev->mem_resource[0].addr);
3920
3921         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
3922         if (rc) {
3923                 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n");
3924                 goto error_free;
3925         }
3926
3927         if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
3928             mtu != eth_dev->data->mtu)
3929                 eth_dev->data->mtu = mtu;
3930
3931         if (BNXT_PF(bp)) {
3932                 //if (bp->pf.active_vfs) {
3933                         // TODO: Deallocate VF resources?
3934                 //}
3935                 if (bp->pdev->max_vfs) {
3936                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
3937                         if (rc) {
3938                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
3939                                 goto error_free;
3940                         }
3941                 } else {
3942                         rc = bnxt_hwrm_allocate_pf_only(bp);
3943                         if (rc) {
3944                                 PMD_DRV_LOG(ERR,
3945                                         "Failed to allocate PF resources\n");
3946                                 goto error_free;
3947                         }
3948                 }
3949         }
3950
3951         bnxt_hwrm_port_led_qcaps(bp);
3952
3953         rc = bnxt_setup_int(bp);
3954         if (rc)
3955                 goto error_free;
3956
3957         rc = bnxt_alloc_mem(bp);
3958         if (rc)
3959                 goto error_free;
3960
3961         bnxt_init_nic(bp);
3962
3963         rc = bnxt_request_int(bp);
3964         if (rc)
3965                 goto error_free;
3966
3967         return 0;
3968
3969 error_free:
3970         bnxt_dev_uninit(eth_dev);
3971 error:
3972         return rc;
3973 }
3974
3975 static int
3976 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
3977 {
3978         struct bnxt *bp = eth_dev->data->dev_private;
3979         int rc;
3980
3981         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3982                 return -EPERM;
3983
3984         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
3985         bnxt_disable_int(bp);
3986         bnxt_free_int(bp);
3987         bnxt_free_mem(bp);
3988
3989         bnxt_hwrm_func_buf_unrgtr(bp);
3990
3991         if (bp->grp_info != NULL) {
3992                 rte_free(bp->grp_info);
3993                 bp->grp_info = NULL;
3994         }
3995         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
3996         bnxt_free_hwrm_resources(bp);
3997
3998         if (bp->tx_mem_zone) {
3999                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4000                 bp->tx_mem_zone = NULL;
4001         }
4002
4003         if (bp->rx_mem_zone) {
4004                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4005                 bp->rx_mem_zone = NULL;
4006         }
4007
4008         if (bp->dev_stopped == 0)
4009                 bnxt_dev_close_op(eth_dev);
4010         if (bp->pf.vf_info)
4011                 rte_free(bp->pf.vf_info);
4012         bnxt_free_ctx_mem(bp);
4013         eth_dev->dev_ops = NULL;
4014         eth_dev->rx_pkt_burst = NULL;
4015         eth_dev->tx_pkt_burst = NULL;
4016
4017         return rc;
4018 }
4019
4020 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4021         struct rte_pci_device *pci_dev)
4022 {
4023         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4024                 bnxt_dev_init);
4025 }
4026
4027 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4028 {
4029         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4030                 return rte_eth_dev_pci_generic_remove(pci_dev,
4031                                 bnxt_dev_uninit);
4032         else
4033                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4034 }
4035
4036 static struct rte_pci_driver bnxt_rte_pmd = {
4037         .id_table = bnxt_pci_id_map,
4038         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4039         .probe = bnxt_pci_probe,
4040         .remove = bnxt_pci_remove,
4041 };
4042
4043 static bool
4044 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4045 {
4046         if (strcmp(dev->device->driver->name, drv->driver.name))
4047                 return false;
4048
4049         return true;
4050 }
4051
4052 bool is_bnxt_supported(struct rte_eth_dev *dev)
4053 {
4054         return is_device_supported(dev, &bnxt_rte_pmd);
4055 }
4056
4057 RTE_INIT(bnxt_init_log)
4058 {
4059         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4060         if (bnxt_logtype_driver >= 0)
4061                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4062 }
4063
4064 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4065 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4066 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");