drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_cpr.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_rxq.h"
  23 #include "bnxt_rxr.h"
  24 #include "bnxt_stats.h"
  25 #include "bnxt_txq.h"
  26 #include "bnxt_txr.h"
  27 #include "bnxt_vnic.h"
  28 #include "hsi_struct_def_dpdk.h"
  29 #include "bnxt_nvm_defs.h"
  30 #include "bnxt_util.h"
  31
  32 #define DRV_MODULE_NAME         "bnxt"
  33 static const char bnxt_version[] =
  34         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  35 int bnxt_logtype_driver;
  36
  37 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  38
  39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  40 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  41 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
  42 #define BROADCOM_DEV_ID_57414_VF 0x16c1
  43 #define BROADCOM_DEV_ID_57301 0x16c8
  44 #define BROADCOM_DEV_ID_57302 0x16c9
  45 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  46 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  47 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  48 #define BROADCOM_DEV_ID_NS2 0x16cd
  49 #define BROADCOM_DEV_ID_57311 0x16ce
  50 #define BROADCOM_DEV_ID_57312 0x16cf
  51 #define BROADCOM_DEV_ID_57402 0x16d0
  52 #define BROADCOM_DEV_ID_57404 0x16d1
  53 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  54 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  55 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  56 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  57 #define BROADCOM_DEV_ID_57412 0x16d6
  58 #define BROADCOM_DEV_ID_57414 0x16d7
  59 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  60 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  61 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  62 #define BROADCOM_DEV_ID_57412_MF 0x16de
  63 #define BROADCOM_DEV_ID_57314 0x16df
  64 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  65 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  66 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  67 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  68 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  69 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  70 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  71 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  72 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  73 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  74 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  75 #define BROADCOM_DEV_ID_57508 0x1750
  76 #define BROADCOM_DEV_ID_57504 0x1751
  77 #define BROADCOM_DEV_ID_57502 0x1752
  78 #define BROADCOM_DEV_ID_57500_VF1 0x1806
  79 #define BROADCOM_DEV_ID_57500_VF2 0x1807
  80 #define BROADCOM_DEV_ID_58802 0xd802
  81 #define BROADCOM_DEV_ID_58804 0xd804
  82 #define BROADCOM_DEV_ID_58808 0x16f0
  83 #define BROADCOM_DEV_ID_58802_VF 0xd800
  84
  85 static const struct rte_pci_id bnxt_pci_id_map[] = {
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  87                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  89                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
 100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
 102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 119         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 121         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 122         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 123         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 124         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
 125         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
 126         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
 127         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
 128         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
 129         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
 130         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
 131         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
 132         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
 133         { .vendor_id = 0, /* sentinel */ },
 134 };
 135
 136 #define BNXT_ETH_RSS_SUPPORT (  \
 137         ETH_RSS_IPV4 |          \
 138         ETH_RSS_NONFRAG_IPV4_TCP |      \
 139         ETH_RSS_NONFRAG_IPV4_UDP |      \
 140         ETH_RSS_IPV6 |          \
 141         ETH_RSS_NONFRAG_IPV6_TCP |      \
 142         ETH_RSS_NONFRAG_IPV6_UDP)
 143
 144 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 145                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 146                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 147                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 148                                      DEV_TX_OFFLOAD_TCP_TSO | \
 149                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 150                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 151                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 152                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 153                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 154                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 155                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 156
 157 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 158                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 159                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 160                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 161                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 162                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 163                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 164                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 165                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 166                                      DEV_RX_OFFLOAD_TCP_LRO)
 167
 168 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 169 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 170 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 171 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 172 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 173 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 174 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 175
 176 int is_bnxt_in_error(struct bnxt *bp)
 177 {
 178         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 179                 return -EIO;
 180         if (bp->flags & BNXT_FLAG_FW_RESET)
 181                 return -EBUSY;
 182
 183         return 0;
 184 }
 185
 186 /***********************/
 187
 188 /*
 189  * High level utility functions
 190  */
 191
 192 uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 193 {
 194         if (!BNXT_CHIP_THOR(bp))
 195                 return 1;
 196
 197         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 198                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 199                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 200 }
 201
 202 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 203 {
 204         if (!BNXT_CHIP_THOR(bp))
 205                 return HW_HASH_INDEX_SIZE;
 206
 207         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 208 }
 209
 210 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 211 {
 212         bnxt_free_filter_mem(bp);
 213         bnxt_free_vnic_attributes(bp);
 214         bnxt_free_vnic_mem(bp);
 215
 216         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 217          * If the number of rings change across fw update,
 218          * we don't have much choice except to warn the user.
 219          */
 220         if (!reconfig) {
 221                 bnxt_free_stats(bp);
 222                 bnxt_free_tx_rings(bp);
 223                 bnxt_free_rx_rings(bp);
 224         }
 225         bnxt_free_async_cp_ring(bp);
 226         bnxt_free_rxtx_nq_ring(bp);
 227 }
 228
 229 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 230 {
 231         int rc;
 232
 233         rc = bnxt_alloc_ring_grps(bp);
 234         if (rc)
 235                 goto alloc_mem_err;
 236
 237         rc = bnxt_alloc_async_ring_struct(bp);
 238         if (rc)
 239                 goto alloc_mem_err;
 240
 241         rc = bnxt_alloc_vnic_mem(bp);
 242         if (rc)
 243                 goto alloc_mem_err;
 244
 245         rc = bnxt_alloc_vnic_attributes(bp);
 246         if (rc)
 247                 goto alloc_mem_err;
 248
 249         rc = bnxt_alloc_filter_mem(bp);
 250         if (rc)
 251                 goto alloc_mem_err;
 252
 253         rc = bnxt_alloc_async_cp_ring(bp);
 254         if (rc)
 255                 goto alloc_mem_err;
 256
 257         rc = bnxt_alloc_rxtx_nq_ring(bp);
 258         if (rc)
 259                 goto alloc_mem_err;
 260
 261         return 0;
 262
 263 alloc_mem_err:
 264         bnxt_free_mem(bp, reconfig);
 265         return rc;
 266 }
 267
 268 static int bnxt_init_chip(struct bnxt *bp)
 269 {
 270         struct bnxt_rx_queue *rxq;
 271         struct rte_eth_link new;
 272         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 273         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 274         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 275         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 276         uint32_t intr_vector = 0;
 277         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 278         uint32_t vec = BNXT_MISC_VEC_ID;
 279         unsigned int i, j;
 280         int rc;
 281
 282         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 283                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 284                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 285                 bp->flags |= BNXT_FLAG_JUMBO;
 286         } else {
 287                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 288                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 289                 bp->flags &= ~BNXT_FLAG_JUMBO;
 290         }
 291
 292         /* THOR does not support ring groups.
 293          * But we will use the array to save RSS context IDs.
 294          */
 295         if (BNXT_CHIP_THOR(bp))
 296                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 297
 298         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 299         if (rc) {
 300                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 301                 goto err_out;
 302         }
 303
 304         rc = bnxt_alloc_hwrm_rings(bp);
 305         if (rc) {
 306                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 307                 goto err_out;
 308         }
 309
 310         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 311         if (rc) {
 312                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 313                 goto err_out;
 314         }
 315
 316         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 317                 goto skip_cosq_cfg;
 318
 319         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 320                 if (bp->rx_cos_queue[i].id != 0xff) {
 321                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 322
 323                         if (!vnic) {
 324                                 PMD_DRV_LOG(ERR,
 325                                             "Num pools more than FW profile\n");
 326                                 rc = -EINVAL;
 327                                 goto err_out;
 328                         }
 329                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 330                         bp->rx_cosq_cnt++;
 331                 }
 332         }
 333
 334 skip_cosq_cfg:
 335         rc = bnxt_mq_rx_configure(bp);
 336         if (rc) {
 337                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 338                 goto err_out;
 339         }
 340
 341         /* VNIC configuration */
 342         for (i = 0; i < bp->nr_vnics; i++) {
 343                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 344                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 345
 346                 rc = bnxt_vnic_grp_alloc(bp, vnic);
 347                 if (rc)
 348                         goto err_out;
 349
 350                 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 351                             i, vnic, vnic->fw_grp_ids);
 352
 353                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 354                 if (rc) {
 355                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 356                                 i, rc);
 357                         goto err_out;
 358                 }
 359
 360                 /* Alloc RSS context only if RSS mode is enabled */
 361                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 362                         int j, nr_ctxs = bnxt_rss_ctxts(bp);
 363
 364                         rc = 0;
 365                         for (j = 0; j < nr_ctxs; j++) {
 366                                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 367                                 if (rc)
 368                                         break;
 369                         }
 370                         if (rc) {
 371                                 PMD_DRV_LOG(ERR,
 372                                   "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 373                                   i, j, rc);
 374                                 goto err_out;
 375                         }
 376                         vnic->num_lb_ctxts = nr_ctxs;
 377                 }
 378
 379                 /*
 380                  * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 381                  * setting is not available at this time, it will not be
 382                  * configured correctly in the CFA.
 383                  */
 384                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 385                         vnic->vlan_strip = true;
 386                 else
 387                         vnic->vlan_strip = false;
 388
 389                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 390                 if (rc) {
 391                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 392                                 i, rc);
 393                         goto err_out;
 394                 }
 395
 396                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 397                 if (rc) {
 398                         PMD_DRV_LOG(ERR,
 399                                 "HWRM vnic %d filter failure rc: %x\n",
 400                                 i, rc);
 401                         goto err_out;
 402                 }
 403
 404                 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 405                         rxq = bp->eth_dev->data->rx_queues[j];
 406
 407                         PMD_DRV_LOG(DEBUG,
 408                                     "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 409                                     j, rxq->vnic, rxq->vnic->fw_grp_ids);
 410
 411                         if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 412                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 413                 }
 414
 415                 rc = bnxt_vnic_rss_configure(bp, vnic);
 416                 if (rc) {
 417                         PMD_DRV_LOG(ERR,
 418                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 419                         goto err_out;
 420                 }
 421
 422                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 423
 424                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 425                     DEV_RX_OFFLOAD_TCP_LRO)
 426                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 427                 else
 428                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 429         }
 430         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 431         if (rc) {
 432                 PMD_DRV_LOG(ERR,
 433                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 434                 goto err_out;
 435         }
 436
 437         /* check and configure queue intr-vector mapping */
 438         if ((rte_intr_cap_multiple(intr_handle) ||
 439              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 440             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 441                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 442                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 443                 if (intr_vector > bp->rx_cp_nr_rings) {
 444                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 445                                         bp->rx_cp_nr_rings);
 446                         return -ENOTSUP;
 447                 }
 448                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 449                 if (rc)
 450                         return rc;
 451         }
 452
 453         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 454                 intr_handle->intr_vec =
 455                         rte_zmalloc("intr_vec",
 456                                     bp->eth_dev->data->nb_rx_queues *
 457                                     sizeof(int), 0);
 458                 if (intr_handle->intr_vec == NULL) {
 459                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 460                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 461                         rc = -ENOMEM;
 462                         goto err_disable;
 463                 }
 464                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 465                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 466                          intr_handle->intr_vec, intr_handle->nb_efd,
 467                         intr_handle->max_intr);
 468                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 469                      queue_id++) {
 470                         intr_handle->intr_vec[queue_id] =
 471                                                         vec + BNXT_RX_VEC_START;
 472                         if (vec < base + intr_handle->nb_efd - 1)
 473                                 vec++;
 474                 }
 475         }
 476
 477         /* enable uio/vfio intr/eventfd mapping */
 478         rc = rte_intr_enable(intr_handle);
 479         if (rc)
 480                 goto err_free;
 481
 482         rc = bnxt_get_hwrm_link_config(bp, &new);
 483         if (rc) {
 484                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 485                 goto err_free;
 486         }
 487
 488         if (!bp->link_info.link_up) {
 489                 rc = bnxt_set_hwrm_link_config(bp, true);
 490                 if (rc) {
 491                         PMD_DRV_LOG(ERR,
 492                                 "HWRM link config failure rc: %x\n", rc);
 493                         goto err_free;
 494                 }
 495         }
 496         bnxt_print_link_info(bp->eth_dev);
 497
 498         return 0;
 499
 500 err_free:
 501         rte_free(intr_handle->intr_vec);
 502 err_disable:
 503         rte_intr_efd_disable(intr_handle);
 504 err_out:
 505         /* Some of the error status returned by FW may not be from errno.h */
 506         if (rc > 0)
 507                 rc = -EIO;
 508
 509         return rc;
 510 }
 511
 512 static int bnxt_shutdown_nic(struct bnxt *bp)
 513 {
 514         bnxt_free_all_hwrm_resources(bp);
 515         bnxt_free_all_filters(bp);
 516         bnxt_free_all_vnics(bp);
 517         return 0;
 518 }
 519
 520 static int bnxt_init_nic(struct bnxt *bp)
 521 {
 522         int rc;
 523
 524         if (BNXT_HAS_RING_GRPS(bp)) {
 525                 rc = bnxt_init_ring_grps(bp);
 526                 if (rc)
 527                         return rc;
 528         }
 529
 530         bnxt_init_vnics(bp);
 531         bnxt_init_filters(bp);
 532
 533         return 0;
 534 }
 535
 536 /*
 537  * Device configuration and status function
 538  */
 539
 540 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 541                                 struct rte_eth_dev_info *dev_info)
 542 {
 543         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 544         struct bnxt *bp = eth_dev->data->dev_private;
 545         uint16_t max_vnics, i, j, vpool, vrxq;
 546         unsigned int max_rx_rings;
 547         int rc;
 548
 549         rc = is_bnxt_in_error(bp);
 550         if (rc)
 551                 return rc;
 552
 553         /* MAC Specifics */
 554         dev_info->max_mac_addrs = bp->max_l2_ctx;
 555         dev_info->max_hash_mac_addrs = 0;
 556
 557         /* PF/VF specifics */
 558         if (BNXT_PF(bp))
 559                 dev_info->max_vfs = pdev->max_vfs;
 560
 561         max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
 562         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 563         dev_info->max_rx_queues = max_rx_rings;
 564         dev_info->max_tx_queues = max_rx_rings;
 565         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 566         dev_info->hash_key_size = 40;
 567         max_vnics = bp->max_vnics;
 568
 569         /* MTU specifics */
 570         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 571         dev_info->max_mtu = BNXT_MAX_MTU;
 572
 573         /* Fast path specifics */
 574         dev_info->min_rx_bufsize = 1;
 575         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 576
 577         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 578         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 579                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 580         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 581         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 582
 583         /* *INDENT-OFF* */
 584         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 585                 .rx_thresh = {
 586                         .pthresh = 8,
 587                         .hthresh = 8,
 588                         .wthresh = 0,
 589                 },
 590                 .rx_free_thresh = 32,
 591                 /* If no descriptors available, pkts are dropped by default */
 592                 .rx_drop_en = 1,
 593         };
 594
 595         dev_info->default_txconf = (struct rte_eth_txconf) {
 596                 .tx_thresh = {
 597                         .pthresh = 32,
 598                         .hthresh = 0,
 599                         .wthresh = 0,
 600                 },
 601                 .tx_free_thresh = 32,
 602                 .tx_rs_thresh = 32,
 603         };
 604         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 605
 606         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 607         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 608         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 609         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 610         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 611
 612         /* *INDENT-ON* */
 613
 614         /*
 615          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 616          *       need further investigation.
 617          */
 618
 619         /* VMDq resources */
 620         vpool = 64; /* ETH_64_POOLS */
 621         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 622         for (i = 0; i < 4; vpool >>= 1, i++) {
 623                 if (max_vnics > vpool) {
 624                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 625                                 if (dev_info->max_rx_queues > vrxq) {
 626                                         if (vpool > vrxq)
 627                                                 vpool = vrxq;
 628                                         goto found;
 629                                 }
 630                         }
 631                         /* Not enough resources to support VMDq */
 632                         break;
 633                 }
 634         }
 635         /* Not enough resources to support VMDq */
 636         vpool = 0;
 637         vrxq = 0;
 638 found:
 639         dev_info->max_vmdq_pools = vpool;
 640         dev_info->vmdq_queue_num = vrxq;
 641
 642         dev_info->vmdq_pool_base = 0;
 643         dev_info->vmdq_queue_base = 0;
 644
 645         return 0;
 646 }
 647
 648 /* Configure the device based on the configuration provided */
 649 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 650 {
 651         struct bnxt *bp = eth_dev->data->dev_private;
 652         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 653         int rc;
 654
 655         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 656         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 657         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 658         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 659
 660         rc = is_bnxt_in_error(bp);
 661         if (rc)
 662                 return rc;
 663
 664         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 665                 rc = bnxt_hwrm_check_vf_rings(bp);
 666                 if (rc) {
 667                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 668                         return -ENOSPC;
 669                 }
 670
 671                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 672                 if (rc) {
 673                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 674                         return -ENOSPC;
 675                 }
 676         } else {
 677                 /* legacy driver needs to get updated values */
 678                 rc = bnxt_hwrm_func_qcaps(bp);
 679                 if (rc) {
 680                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 681                         return rc;
 682                 }
 683         }
 684
 685         /* Inherit new configurations */
 686         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 687             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 688             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 689                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 690             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 691             bp->max_stat_ctx)
 692                 goto resource_error;
 693
 694         if (BNXT_HAS_RING_GRPS(bp) &&
 695             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 696                 goto resource_error;
 697
 698         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 699             bp->max_vnics < eth_dev->data->nb_rx_queues)
 700                 goto resource_error;
 701
 702         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 703         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 704
 705         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 706                 eth_dev->data->mtu =
 707                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 708                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 709                         BNXT_NUM_VLANS;
 710                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 711         }
 712         return 0;
 713
 714 resource_error:
 715         PMD_DRV_LOG(ERR,
 716                     "Insufficient resources to support requested config\n");
 717         PMD_DRV_LOG(ERR,
 718                     "Num Queues Requested: Tx %d, Rx %d\n",
 719                     eth_dev->data->nb_tx_queues,
 720                     eth_dev->data->nb_rx_queues);
 721         PMD_DRV_LOG(ERR,
 722                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 723                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 724                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 725         return -ENOSPC;
 726 }
 727
 728 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 729 {
 730         struct rte_eth_link *link = &eth_dev->data->dev_link;
 731
 732         if (link->link_status)
 733                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 734                         eth_dev->data->port_id,
 735                         (uint32_t)link->link_speed,
 736                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 737                         ("full-duplex") : ("half-duplex\n"));
 738         else
 739                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 740                         eth_dev->data->port_id);
 741 }
 742
 743 /*
 744  * Determine whether the current configuration requires support for scattered
 745  * receive; return 1 if scattered receive is required and 0 if not.
 746  */
 747 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 748 {
 749         uint16_t buf_size;
 750         int i;
 751
 752         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 753                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 754
 755                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 756                                       RTE_PKTMBUF_HEADROOM);
 757                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 758                         return 1;
 759         }
 760         return 0;
 761 }
 762
 763 static eth_rx_burst_t
 764 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
 765 {
 766 #ifdef RTE_ARCH_X86
 767 #ifndef RTE_LIBRTE_IEEE1588
 768         /*
 769          * Vector mode receive can be enabled only if scatter rx is not
 770          * in use and rx offloads are limited to VLAN stripping and
 771          * CRC stripping.
 772          */
 773         if (!eth_dev->data->scattered_rx &&
 774             !(eth_dev->data->dev_conf.rxmode.offloads &
 775               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 776                 DEV_RX_OFFLOAD_KEEP_CRC |
 777                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 778                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 779                 DEV_RX_OFFLOAD_UDP_CKSUM |
 780                 DEV_RX_OFFLOAD_TCP_CKSUM |
 781                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 782                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 783                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 784                             eth_dev->data->port_id);
 785                 return bnxt_recv_pkts_vec;
 786         }
 787         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 788                     eth_dev->data->port_id);
 789         PMD_DRV_LOG(INFO,
 790                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 791                     eth_dev->data->port_id,
 792                     eth_dev->data->scattered_rx,
 793                     eth_dev->data->dev_conf.rxmode.offloads);
 794 #endif
 795 #endif
 796         return bnxt_recv_pkts;
 797 }
 798
 799 static eth_tx_burst_t
 800 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 801 {
 802 #ifdef RTE_ARCH_X86
 803 #ifndef RTE_LIBRTE_IEEE1588
 804         /*
 805          * Vector mode transmit can be enabled only if not using scatter rx
 806          * or tx offloads.
 807          */
 808         if (!eth_dev->data->scattered_rx &&
 809             !eth_dev->data->dev_conf.txmode.offloads) {
 810                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 811                             eth_dev->data->port_id);
 812                 return bnxt_xmit_pkts_vec;
 813         }
 814         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 815                     eth_dev->data->port_id);
 816         PMD_DRV_LOG(INFO,
 817                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 818                     eth_dev->data->port_id,
 819                     eth_dev->data->scattered_rx,
 820                     eth_dev->data->dev_conf.txmode.offloads);
 821 #endif
 822 #endif
 823         return bnxt_xmit_pkts;
 824 }
 825
 826 static int bnxt_handle_if_change_status(struct bnxt *bp)
 827 {
 828         int rc;
 829
 830         /* Since fw has undergone a reset and lost all contexts,
 831          * set fatal flag to not issue hwrm during cleanup
 832          */
 833         bp->flags |= BNXT_FLAG_FATAL_ERROR;
 834         bnxt_uninit_resources(bp, true);
 835
 836         /* clear fatal flag so that re-init happens */
 837         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
 838         rc = bnxt_init_resources(bp, true);
 839
 840         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
 841
 842         return rc;
 843 }
 844
 845 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 846 {
 847         struct bnxt *bp = eth_dev->data->dev_private;
 848         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 849         int vlan_mask = 0;
 850         int rc;
 851
 852         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 853                 PMD_DRV_LOG(ERR,
 854                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 855                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 856         }
 857
 858         bnxt_enable_int(bp);
 859         rc = bnxt_hwrm_if_change(bp, 1);
 860         if (!rc) {
 861                 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
 862                         rc = bnxt_handle_if_change_status(bp);
 863                         if (rc)
 864                                 return rc;
 865                 }
 866         }
 867
 868         rc = bnxt_init_chip(bp);
 869         if (rc)
 870                 goto error;
 871
 872         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 873
 874         bnxt_link_update_op(eth_dev, 1);
 875
 876         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 877                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 878         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 879                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 880         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 881         if (rc)
 882                 goto error;
 883
 884         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 885         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 886
 887         bp->flags |= BNXT_FLAG_INIT_DONE;
 888         eth_dev->data->dev_started = 1;
 889         bp->dev_stopped = 0;
 890         bnxt_schedule_fw_health_check(bp);
 891         return 0;
 892
 893 error:
 894         bnxt_hwrm_if_change(bp, 0);
 895         bnxt_shutdown_nic(bp);
 896         bnxt_free_tx_mbufs(bp);
 897         bnxt_free_rx_mbufs(bp);
 898         return rc;
 899 }
 900
 901 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 902 {
 903         struct bnxt *bp = eth_dev->data->dev_private;
 904         int rc = 0;
 905
 906         if (!bp->link_info.link_up)
 907                 rc = bnxt_set_hwrm_link_config(bp, true);
 908         if (!rc)
 909                 eth_dev->data->dev_link.link_status = 1;
 910
 911         bnxt_print_link_info(eth_dev);
 912         return 0;
 913 }
 914
 915 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 916 {
 917         struct bnxt *bp = eth_dev->data->dev_private;
 918
 919         eth_dev->data->dev_link.link_status = 0;
 920         bnxt_set_hwrm_link_config(bp, false);
 921         bp->link_info.link_up = 0;
 922
 923         return 0;
 924 }
 925
 926 /* Unload the driver, release resources */
 927 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 928 {
 929         struct bnxt *bp = eth_dev->data->dev_private;
 930         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 931         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 932
 933         eth_dev->data->dev_started = 0;
 934         /* Prevent crashes when queues are still in use */
 935         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
 936         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
 937
 938         bnxt_disable_int(bp);
 939
 940         /* disable uio/vfio intr/eventfd mapping */
 941         rte_intr_disable(intr_handle);
 942
 943         bnxt_cancel_fw_health_check(bp);
 944
 945         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 946         if (bp->eth_dev->data->dev_started) {
 947                 /* TBD: STOP HW queues DMA */
 948                 eth_dev->data->dev_link.link_status = 0;
 949         }
 950         bnxt_dev_set_link_down_op(eth_dev);
 951         /* Wait for link to be reset and the async notification to process. */
 952         rte_delay_ms(BNXT_LINK_WAIT_INTERVAL * 2);
 953
 954         /* Clean queue intr-vector mapping */
 955         rte_intr_efd_disable(intr_handle);
 956         if (intr_handle->intr_vec != NULL) {
 957                 rte_free(intr_handle->intr_vec);
 958                 intr_handle->intr_vec = NULL;
 959         }
 960
 961         bnxt_hwrm_port_clr_stats(bp);
 962         bnxt_free_tx_mbufs(bp);
 963         bnxt_free_rx_mbufs(bp);
 964         /* Process any remaining notifications in default completion queue */
 965         bnxt_int_handler(eth_dev);
 966         bnxt_shutdown_nic(bp);
 967         bnxt_hwrm_if_change(bp, 0);
 968         bp->dev_stopped = 1;
 969 }
 970
 971 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 972 {
 973         struct bnxt *bp = eth_dev->data->dev_private;
 974
 975         if (bp->dev_stopped == 0)
 976                 bnxt_dev_stop_op(eth_dev);
 977
 978         if (eth_dev->data->mac_addrs != NULL) {
 979                 rte_free(eth_dev->data->mac_addrs);
 980                 eth_dev->data->mac_addrs = NULL;
 981         }
 982         if (bp->grp_info != NULL) {
 983                 rte_free(bp->grp_info);
 984                 bp->grp_info = NULL;
 985         }
 986
 987         bnxt_dev_uninit(eth_dev);
 988 }
 989
 990 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 991                                     uint32_t index)
 992 {
 993         struct bnxt *bp = eth_dev->data->dev_private;
 994         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 995         struct bnxt_vnic_info *vnic;
 996         struct bnxt_filter_info *filter, *temp_filter;
 997         uint32_t i;
 998
 999         if (is_bnxt_in_error(bp))
1000                 return;
1001
1002         /*
1003          * Loop through all VNICs from the specified filter flow pools to
1004          * remove the corresponding MAC addr filter
1005          */
1006         for (i = 0; i < bp->nr_vnics; i++) {
1007                 if (!(pool_mask & (1ULL << i)))
1008                         continue;
1009
1010                 vnic = &bp->vnic_info[i];
1011                 filter = STAILQ_FIRST(&vnic->filter);
1012                 while (filter) {
1013                         temp_filter = STAILQ_NEXT(filter, next);
1014                         if (filter->mac_index == index) {
1015                                 STAILQ_REMOVE(&vnic->filter, filter,
1016                                                 bnxt_filter_info, next);
1017                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1018                                 filter->mac_index = INVALID_MAC_INDEX;
1019                                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1020                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1021                                                    filter, next);
1022                         }
1023                         filter = temp_filter;
1024                 }
1025         }
1026 }
1027
1028 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1029                                struct rte_ether_addr *mac_addr, uint32_t index)
1030 {
1031         struct bnxt_filter_info *filter;
1032         int rc = 0;
1033
1034         filter = STAILQ_FIRST(&vnic->filter);
1035         /* During bnxt_mac_addr_add_op, default MAC is
1036          * already programmed, so skip it. But, when
1037          * hw-vlan-filter is turned OFF from ON, default
1038          * MAC filter should be restored
1039          */
1040         if (filter->dflt)
1041                 return 0;
1042
1043         filter = bnxt_alloc_filter(bp);
1044         if (!filter) {
1045                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1046                 return -ENODEV;
1047         }
1048
1049         filter->mac_index = index;
1050         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1051          * if the MAC that's been programmed now is a different one, then,
1052          * copy that addr to filter->l2_addr
1053          */
1054         if (mac_addr)
1055                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1056         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1057
1058         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1059         if (!rc) {
1060                 if (filter->mac_index == 0) {
1061                         filter->dflt = true;
1062                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1063                 } else {
1064                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1065                 }
1066         } else {
1067                 filter->mac_index = INVALID_MAC_INDEX;
1068                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1069                 bnxt_free_filter(bp, filter);
1070         }
1071
1072         return rc;
1073 }
1074
1075 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1076                                 struct rte_ether_addr *mac_addr,
1077                                 uint32_t index, uint32_t pool)
1078 {
1079         struct bnxt *bp = eth_dev->data->dev_private;
1080         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1081         struct bnxt_filter_info *filter;
1082         int rc = 0;
1083
1084         rc = is_bnxt_in_error(bp);
1085         if (rc)
1086                 return rc;
1087
1088         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1089                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1090                 return -ENOTSUP;
1091         }
1092
1093         if (!vnic) {
1094                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1095                 return -EINVAL;
1096         }
1097         /* Attach requested MAC address to the new l2_filter */
1098         STAILQ_FOREACH(filter, &vnic->filter, next) {
1099                 if (filter->mac_index == index) {
1100                         PMD_DRV_LOG(ERR,
1101                                 "MAC addr already existed for pool %d\n", pool);
1102                         return 0;
1103                 }
1104         }
1105
1106         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index);
1107
1108         return rc;
1109 }
1110
1111 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1112 {
1113         int rc = 0;
1114         struct bnxt *bp = eth_dev->data->dev_private;
1115         struct rte_eth_link new;
1116         unsigned int cnt = BNXT_LINK_WAIT_CNT;
1117
1118         rc = is_bnxt_in_error(bp);
1119         if (rc)
1120                 return rc;
1121
1122         memset(&new, 0, sizeof(new));
1123         do {
1124                 /* Retrieve link info from hardware */
1125                 rc = bnxt_get_hwrm_link_config(bp, &new);
1126                 if (rc) {
1127                         new.link_speed = ETH_LINK_SPEED_100M;
1128                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1129                         PMD_DRV_LOG(ERR,
1130                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1131                         goto out;
1132                 }
1133
1134                 if (!wait_to_complete || new.link_status)
1135                         break;
1136
1137                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1138         } while (cnt--);
1139
1140 out:
1141         /* Timed out or success */
1142         if (new.link_status != eth_dev->data->dev_link.link_status ||
1143         new.link_speed != eth_dev->data->dev_link.link_speed) {
1144                 rte_eth_linkstatus_set(eth_dev, &new);
1145
1146                 _rte_eth_dev_callback_process(eth_dev,
1147                                               RTE_ETH_EVENT_INTR_LSC,
1148                                               NULL);
1149
1150                 bnxt_print_link_info(eth_dev);
1151         }
1152
1153         return rc;
1154 }
1155
1156 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1157 {
1158         struct bnxt *bp = eth_dev->data->dev_private;
1159         struct bnxt_vnic_info *vnic;
1160         uint32_t old_flags;
1161         int rc;
1162
1163         rc = is_bnxt_in_error(bp);
1164         if (rc)
1165                 return rc;
1166
1167         if (bp->vnic_info == NULL)
1168                 return 0;
1169
1170         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1171
1172         old_flags = vnic->flags;
1173         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1174         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1175         if (rc != 0)
1176                 vnic->flags = old_flags;
1177
1178         return rc;
1179 }
1180
1181 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1182 {
1183         struct bnxt *bp = eth_dev->data->dev_private;
1184         struct bnxt_vnic_info *vnic;
1185         uint32_t old_flags;
1186         int rc;
1187
1188         rc = is_bnxt_in_error(bp);
1189         if (rc)
1190                 return rc;
1191
1192         if (bp->vnic_info == NULL)
1193                 return 0;
1194
1195         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1196
1197         old_flags = vnic->flags;
1198         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1199         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1200         if (rc != 0)
1201                 vnic->flags = old_flags;
1202
1203         return rc;
1204 }
1205
1206 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1207 {
1208         struct bnxt *bp = eth_dev->data->dev_private;
1209         struct bnxt_vnic_info *vnic;
1210         uint32_t old_flags;
1211         int rc;
1212
1213         rc = is_bnxt_in_error(bp);
1214         if (rc)
1215                 return rc;
1216
1217         if (bp->vnic_info == NULL)
1218                 return 0;
1219
1220         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1221
1222         old_flags = vnic->flags;
1223         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1224         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1225         if (rc != 0)
1226                 vnic->flags = old_flags;
1227
1228         return rc;
1229 }
1230
1231 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1232 {
1233         struct bnxt *bp = eth_dev->data->dev_private;
1234         struct bnxt_vnic_info *vnic;
1235         uint32_t old_flags;
1236         int rc;
1237
1238         rc = is_bnxt_in_error(bp);
1239         if (rc)
1240                 return rc;
1241
1242         if (bp->vnic_info == NULL)
1243                 return 0;
1244
1245         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1246
1247         old_flags = vnic->flags;
1248         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1249         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1250         if (rc != 0)
1251                 vnic->flags = old_flags;
1252
1253         return rc;
1254 }
1255
1256 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1257 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1258 {
1259         if (qid >= bp->rx_nr_rings)
1260                 return NULL;
1261
1262         return bp->eth_dev->data->rx_queues[qid];
1263 }
1264
1265 /* Return rxq corresponding to a given rss table ring/group ID. */
1266 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1267 {
1268         struct bnxt_rx_queue *rxq;
1269         unsigned int i;
1270
1271         if (!BNXT_HAS_RING_GRPS(bp)) {
1272                 for (i = 0; i < bp->rx_nr_rings; i++) {
1273                         rxq = bp->eth_dev->data->rx_queues[i];
1274                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1275                                 return rxq->index;
1276                 }
1277         } else {
1278                 for (i = 0; i < bp->rx_nr_rings; i++) {
1279                         if (bp->grp_info[i].fw_grp_id == fwr)
1280                                 return i;
1281                 }
1282         }
1283
1284         return INVALID_HW_RING_ID;
1285 }
1286
1287 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1288                             struct rte_eth_rss_reta_entry64 *reta_conf,
1289                             uint16_t reta_size)
1290 {
1291         struct bnxt *bp = eth_dev->data->dev_private;
1292         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1293         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1294         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1295         uint16_t idx, sft;
1296         int i, rc;
1297
1298         rc = is_bnxt_in_error(bp);
1299         if (rc)
1300                 return rc;
1301
1302         if (!vnic->rss_table)
1303                 return -EINVAL;
1304
1305         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1306                 return -EINVAL;
1307
1308         if (reta_size != tbl_size) {
1309                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1310                         "(%d) must equal the size supported by the hardware "
1311                         "(%d)\n", reta_size, tbl_size);
1312                 return -EINVAL;
1313         }
1314
1315         for (i = 0; i < reta_size; i++) {
1316                 struct bnxt_rx_queue *rxq;
1317
1318                 idx = i / RTE_RETA_GROUP_SIZE;
1319                 sft = i % RTE_RETA_GROUP_SIZE;
1320
1321                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1322                         continue;
1323
1324                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1325                 if (!rxq) {
1326                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1327                         return -EINVAL;
1328                 }
1329
1330                 if (BNXT_CHIP_THOR(bp)) {
1331                         vnic->rss_table[i * 2] =
1332                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1333                         vnic->rss_table[i * 2 + 1] =
1334                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1335                 } else {
1336                         vnic->rss_table[i] =
1337                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1338                 }
1339
1340                 vnic->rss_table[i] =
1341                     vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1342         }
1343
1344         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1345         return 0;
1346 }
1347
1348 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1349                               struct rte_eth_rss_reta_entry64 *reta_conf,
1350                               uint16_t reta_size)
1351 {
1352         struct bnxt *bp = eth_dev->data->dev_private;
1353         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1354         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1355         uint16_t idx, sft, i;
1356         int rc;
1357
1358         rc = is_bnxt_in_error(bp);
1359         if (rc)
1360                 return rc;
1361
1362         /* Retrieve from the default VNIC */
1363         if (!vnic)
1364                 return -EINVAL;
1365         if (!vnic->rss_table)
1366                 return -EINVAL;
1367
1368         if (reta_size != tbl_size) {
1369                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1370                         "(%d) must equal the size supported by the hardware "
1371                         "(%d)\n", reta_size, tbl_size);
1372                 return -EINVAL;
1373         }
1374
1375         for (idx = 0, i = 0; i < reta_size; i++) {
1376                 idx = i / RTE_RETA_GROUP_SIZE;
1377                 sft = i % RTE_RETA_GROUP_SIZE;
1378
1379                 if (reta_conf[idx].mask & (1ULL << sft)) {
1380                         uint16_t qid;
1381
1382                         if (BNXT_CHIP_THOR(bp))
1383                                 qid = bnxt_rss_to_qid(bp,
1384                                                       vnic->rss_table[i * 2]);
1385                         else
1386                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1387
1388                         if (qid == INVALID_HW_RING_ID) {
1389                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1390                                 return -EINVAL;
1391                         }
1392                         reta_conf[idx].reta[sft] = qid;
1393                 }
1394         }
1395
1396         return 0;
1397 }
1398
1399 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1400                                    struct rte_eth_rss_conf *rss_conf)
1401 {
1402         struct bnxt *bp = eth_dev->data->dev_private;
1403         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1404         struct bnxt_vnic_info *vnic;
1405         int rc;
1406
1407         rc = is_bnxt_in_error(bp);
1408         if (rc)
1409                 return rc;
1410
1411         /*
1412          * If RSS enablement were different than dev_configure,
1413          * then return -EINVAL
1414          */
1415         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1416                 if (!rss_conf->rss_hf)
1417                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1418         } else {
1419                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1420                         return -EINVAL;
1421         }
1422
1423         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1424         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1425
1426         /* Update the default RSS VNIC(s) */
1427         vnic = &bp->vnic_info[0];
1428         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1429
1430         /*
1431          * If hashkey is not specified, use the previously configured
1432          * hashkey
1433          */
1434         if (!rss_conf->rss_key)
1435                 goto rss_config;
1436
1437         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1438                 PMD_DRV_LOG(ERR,
1439                             "Invalid hashkey length, should be 16 bytes\n");
1440                 return -EINVAL;
1441         }
1442         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1443
1444 rss_config:
1445         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1446         return 0;
1447 }
1448
1449 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1450                                      struct rte_eth_rss_conf *rss_conf)
1451 {
1452         struct bnxt *bp = eth_dev->data->dev_private;
1453         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1454         int len, rc;
1455         uint32_t hash_types;
1456
1457         rc = is_bnxt_in_error(bp);
1458         if (rc)
1459                 return rc;
1460
1461         /* RSS configuration is the same for all VNICs */
1462         if (vnic && vnic->rss_hash_key) {
1463                 if (rss_conf->rss_key) {
1464                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1465                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1466                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1467                 }
1468
1469                 hash_types = vnic->hash_type;
1470                 rss_conf->rss_hf = 0;
1471                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1472                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1473                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1474                 }
1475                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1476                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1477                         hash_types &=
1478                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1479                 }
1480                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1481                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1482                         hash_types &=
1483                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1484                 }
1485                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1486                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1487                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1488                 }
1489                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1490                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1491                         hash_types &=
1492                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1493                 }
1494                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1495                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1496                         hash_types &=
1497                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1498                 }
1499                 if (hash_types) {
1500                         PMD_DRV_LOG(ERR,
1501                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1502                                 vnic->hash_type);
1503                         return -ENOTSUP;
1504                 }
1505         } else {
1506                 rss_conf->rss_hf = 0;
1507         }
1508         return 0;
1509 }
1510
1511 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1512                                struct rte_eth_fc_conf *fc_conf)
1513 {
1514         struct bnxt *bp = dev->data->dev_private;
1515         struct rte_eth_link link_info;
1516         int rc;
1517
1518         rc = is_bnxt_in_error(bp);
1519         if (rc)
1520                 return rc;
1521
1522         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1523         if (rc)
1524                 return rc;
1525
1526         memset(fc_conf, 0, sizeof(*fc_conf));
1527         if (bp->link_info.auto_pause)
1528                 fc_conf->autoneg = 1;
1529         switch (bp->link_info.pause) {
1530         case 0:
1531                 fc_conf->mode = RTE_FC_NONE;
1532                 break;
1533         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1534                 fc_conf->mode = RTE_FC_TX_PAUSE;
1535                 break;
1536         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1537                 fc_conf->mode = RTE_FC_RX_PAUSE;
1538                 break;
1539         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1540                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1541                 fc_conf->mode = RTE_FC_FULL;
1542                 break;
1543         }
1544         return 0;
1545 }
1546
1547 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1548                                struct rte_eth_fc_conf *fc_conf)
1549 {
1550         struct bnxt *bp = dev->data->dev_private;
1551         int rc;
1552
1553         rc = is_bnxt_in_error(bp);
1554         if (rc)
1555                 return rc;
1556
1557         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1558                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1559                 return -ENOTSUP;
1560         }
1561
1562         switch (fc_conf->mode) {
1563         case RTE_FC_NONE:
1564                 bp->link_info.auto_pause = 0;
1565                 bp->link_info.force_pause = 0;
1566                 break;
1567         case RTE_FC_RX_PAUSE:
1568                 if (fc_conf->autoneg) {
1569                         bp->link_info.auto_pause =
1570                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1571                         bp->link_info.force_pause = 0;
1572                 } else {
1573                         bp->link_info.auto_pause = 0;
1574                         bp->link_info.force_pause =
1575                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1576                 }
1577                 break;
1578         case RTE_FC_TX_PAUSE:
1579                 if (fc_conf->autoneg) {
1580                         bp->link_info.auto_pause =
1581                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1582                         bp->link_info.force_pause = 0;
1583                 } else {
1584                         bp->link_info.auto_pause = 0;
1585                         bp->link_info.force_pause =
1586                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1587                 }
1588                 break;
1589         case RTE_FC_FULL:
1590                 if (fc_conf->autoneg) {
1591                         bp->link_info.auto_pause =
1592                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1593                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1594                         bp->link_info.force_pause = 0;
1595                 } else {
1596                         bp->link_info.auto_pause = 0;
1597                         bp->link_info.force_pause =
1598                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1599                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1600                 }
1601                 break;
1602         }
1603         return bnxt_set_hwrm_link_config(bp, true);
1604 }
1605
1606 /* Add UDP tunneling port */
1607 static int
1608 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1609                          struct rte_eth_udp_tunnel *udp_tunnel)
1610 {
1611         struct bnxt *bp = eth_dev->data->dev_private;
1612         uint16_t tunnel_type = 0;
1613         int rc = 0;
1614
1615         rc = is_bnxt_in_error(bp);
1616         if (rc)
1617                 return rc;
1618
1619         switch (udp_tunnel->prot_type) {
1620         case RTE_TUNNEL_TYPE_VXLAN:
1621                 if (bp->vxlan_port_cnt) {
1622                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1623                                 udp_tunnel->udp_port);
1624                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1625                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1626                                 return -ENOSPC;
1627                         }
1628                         bp->vxlan_port_cnt++;
1629                         return 0;
1630                 }
1631                 tunnel_type =
1632                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1633                 bp->vxlan_port_cnt++;
1634                 break;
1635         case RTE_TUNNEL_TYPE_GENEVE:
1636                 if (bp->geneve_port_cnt) {
1637                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1638                                 udp_tunnel->udp_port);
1639                         if (bp->geneve_port != udp_tunnel->udp_port) {
1640                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1641                                 return -ENOSPC;
1642                         }
1643                         bp->geneve_port_cnt++;
1644                         return 0;
1645                 }
1646                 tunnel_type =
1647                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1648                 bp->geneve_port_cnt++;
1649                 break;
1650         default:
1651                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1652                 return -ENOTSUP;
1653         }
1654         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1655                                              tunnel_type);
1656         return rc;
1657 }
1658
1659 static int
1660 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1661                          struct rte_eth_udp_tunnel *udp_tunnel)
1662 {
1663         struct bnxt *bp = eth_dev->data->dev_private;
1664         uint16_t tunnel_type = 0;
1665         uint16_t port = 0;
1666         int rc = 0;
1667
1668         rc = is_bnxt_in_error(bp);
1669         if (rc)
1670                 return rc;
1671
1672         switch (udp_tunnel->prot_type) {
1673         case RTE_TUNNEL_TYPE_VXLAN:
1674                 if (!bp->vxlan_port_cnt) {
1675                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1676                         return -EINVAL;
1677                 }
1678                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1679                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1680                                 udp_tunnel->udp_port, bp->vxlan_port);
1681                         return -EINVAL;
1682                 }
1683                 if (--bp->vxlan_port_cnt)
1684                         return 0;
1685
1686                 tunnel_type =
1687                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1688                 port = bp->vxlan_fw_dst_port_id;
1689                 break;
1690         case RTE_TUNNEL_TYPE_GENEVE:
1691                 if (!bp->geneve_port_cnt) {
1692                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1693                         return -EINVAL;
1694                 }
1695                 if (bp->geneve_port != udp_tunnel->udp_port) {
1696                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1697                                 udp_tunnel->udp_port, bp->geneve_port);
1698                         return -EINVAL;
1699                 }
1700                 if (--bp->geneve_port_cnt)
1701                         return 0;
1702
1703                 tunnel_type =
1704                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1705                 port = bp->geneve_fw_dst_port_id;
1706                 break;
1707         default:
1708                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1709                 return -ENOTSUP;
1710         }
1711
1712         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1713         if (!rc) {
1714                 if (tunnel_type ==
1715                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1716                         bp->vxlan_port = 0;
1717                 if (tunnel_type ==
1718                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1719                         bp->geneve_port = 0;
1720         }
1721         return rc;
1722 }
1723
1724 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1725 {
1726         struct bnxt_filter_info *filter;
1727         struct bnxt_vnic_info *vnic;
1728         int rc = 0;
1729         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1730
1731         /* if VLAN exists && VLAN matches vlan_id
1732          *      remove the MAC+VLAN filter
1733          *      add a new MAC only filter
1734          * else
1735          *      VLAN filter doesn't exist, just skip and continue
1736          */
1737         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1738         filter = STAILQ_FIRST(&vnic->filter);
1739         while (filter) {
1740                 /* Search for this matching MAC+VLAN filter */
1741                 if ((filter->enables & chk) &&
1742                     (filter->l2_ivlan == vlan_id &&
1743                      filter->l2_ivlan_mask != 0) &&
1744                     !memcmp(filter->l2_addr, bp->mac_addr,
1745                             RTE_ETHER_ADDR_LEN)) {
1746                         /* Delete the filter */
1747                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1748                         if (rc)
1749                                 return rc;
1750                         STAILQ_REMOVE(&vnic->filter, filter,
1751                                       bnxt_filter_info, next);
1752                         STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1753
1754                         PMD_DRV_LOG(INFO,
1755                                     "Del Vlan filter for %d\n",
1756                                     vlan_id);
1757                         return rc;
1758                 }
1759                 filter = STAILQ_NEXT(filter, next);
1760         }
1761         return -ENOENT;
1762 }
1763
1764 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1765 {
1766         struct bnxt_filter_info *filter;
1767         struct bnxt_vnic_info *vnic;
1768         int rc = 0;
1769         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1770                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1771         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1772
1773         /* Implementation notes on the use of VNIC in this command:
1774          *
1775          * By default, these filters belong to default vnic for the function.
1776          * Once these filters are set up, only destination VNIC can be modified.
1777          * If the destination VNIC is not specified in this command,
1778          * then the HWRM shall only create an l2 context id.
1779          */
1780
1781         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1782         filter = STAILQ_FIRST(&vnic->filter);
1783         /* Check if the VLAN has already been added */
1784         while (filter) {
1785                 if ((filter->enables & chk) &&
1786                     (filter->l2_ivlan == vlan_id &&
1787                      filter->l2_ivlan_mask == 0x0FFF) &&
1788                      !memcmp(filter->l2_addr, bp->mac_addr,
1789                              RTE_ETHER_ADDR_LEN))
1790                         return -EEXIST;
1791
1792                 filter = STAILQ_NEXT(filter, next);
1793         }
1794
1795         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1796          * command to create MAC+VLAN filter with the right flags, enables set.
1797          */
1798         filter = bnxt_alloc_filter(bp);
1799         if (!filter) {
1800                 PMD_DRV_LOG(ERR,
1801                             "MAC/VLAN filter alloc failed\n");
1802                 return -ENOMEM;
1803         }
1804         /* MAC + VLAN ID filter */
1805         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1806          * untagged packets are received
1807          *
1808          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
1809          * packets and only the programmed vlan's packets are received
1810          */
1811         filter->l2_ivlan = vlan_id;
1812         filter->l2_ivlan_mask = 0x0FFF;
1813         filter->enables |= en;
1814         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1815
1816         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1817         if (rc) {
1818                 /* Free the newly allocated filter as we were
1819                  * not able to create the filter in hardware.
1820                  */
1821                 filter->fw_l2_filter_id = UINT64_MAX;
1822                 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1823                 return rc;
1824         } else {
1825                 /* Add this new filter to the list */
1826                 if (vlan_id == 0) {
1827                         filter->dflt = true;
1828                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1829                 } else {
1830                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1831                 }
1832         }
1833
1834         PMD_DRV_LOG(INFO,
1835                     "Added Vlan filter for %d\n", vlan_id);
1836         return rc;
1837 }
1838
1839 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1840                 uint16_t vlan_id, int on)
1841 {
1842         struct bnxt *bp = eth_dev->data->dev_private;
1843         int rc;
1844
1845         rc = is_bnxt_in_error(bp);
1846         if (rc)
1847                 return rc;
1848
1849         /* These operations apply to ALL existing MAC/VLAN filters */
1850         if (on)
1851                 return bnxt_add_vlan_filter(bp, vlan_id);
1852         else
1853                 return bnxt_del_vlan_filter(bp, vlan_id);
1854 }
1855
1856 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
1857                                     struct bnxt_vnic_info *vnic)
1858 {
1859         struct bnxt_filter_info *filter;
1860         int rc;
1861
1862         filter = STAILQ_FIRST(&vnic->filter);
1863         while (filter) {
1864                 if (filter->dflt &&
1865                     !memcmp(filter->l2_addr, bp->mac_addr,
1866                             RTE_ETHER_ADDR_LEN)) {
1867                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1868                         if (rc)
1869                                 return rc;
1870                         filter->dflt = false;
1871                         STAILQ_REMOVE(&vnic->filter, filter,
1872                                       bnxt_filter_info, next);
1873                         STAILQ_INSERT_TAIL(&bp->free_filter_list,
1874                                            filter, next);
1875                         filter->fw_l2_filter_id = -1;
1876                         break;
1877                 }
1878                 filter = STAILQ_NEXT(filter, next);
1879         }
1880         return 0;
1881 }
1882
1883 static int
1884 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1885 {
1886         struct bnxt *bp = dev->data->dev_private;
1887         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1888         struct bnxt_vnic_info *vnic;
1889         unsigned int i;
1890         int rc;
1891
1892         rc = is_bnxt_in_error(bp);
1893         if (rc)
1894                 return rc;
1895
1896         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1897         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1898                 /* Remove any VLAN filters programmed */
1899                 for (i = 0; i < 4095; i++)
1900                         bnxt_del_vlan_filter(bp, i);
1901
1902                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0);
1903                 if (rc)
1904                         return rc;
1905         } else {
1906                 /* Default filter will allow packets that match the
1907                  * dest mac. So, it has to be deleted, otherwise, we
1908                  * will endup receiving vlan packets for which the
1909                  * filter is not programmed, when hw-vlan-filter
1910                  * configuration is ON
1911                  */
1912                 bnxt_del_dflt_mac_filter(bp, vnic);
1913                 /* This filter will allow only untagged packets */
1914                 bnxt_add_vlan_filter(bp, 0);
1915         }
1916         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1917                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1918
1919         if (mask & ETH_VLAN_STRIP_MASK) {
1920                 /* Enable or disable VLAN stripping */
1921                 for (i = 0; i < bp->nr_vnics; i++) {
1922                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1923                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1924                                 vnic->vlan_strip = true;
1925                         else
1926                                 vnic->vlan_strip = false;
1927                         bnxt_hwrm_vnic_cfg(bp, vnic);
1928                 }
1929                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1930                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1931         }
1932
1933         if (mask & ETH_VLAN_EXTEND_MASK) {
1934                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1935                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
1936                 else
1937                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
1938         }
1939
1940         return 0;
1941 }
1942
1943 static int
1944 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
1945                       uint16_t tpid)
1946 {
1947         struct bnxt *bp = dev->data->dev_private;
1948         int qinq = dev->data->dev_conf.rxmode.offloads &
1949                    DEV_RX_OFFLOAD_VLAN_EXTEND;
1950
1951         if (vlan_type != ETH_VLAN_TYPE_INNER &&
1952             vlan_type != ETH_VLAN_TYPE_OUTER) {
1953                 PMD_DRV_LOG(ERR,
1954                             "Unsupported vlan type.");
1955                 return -EINVAL;
1956         }
1957         if (!qinq) {
1958                 PMD_DRV_LOG(ERR,
1959                             "QinQ not enabled. Needs to be ON as we can "
1960                             "accelerate only outer vlan\n");
1961                 return -EINVAL;
1962         }
1963
1964         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
1965                 switch (tpid) {
1966                 case RTE_ETHER_TYPE_QINQ:
1967                         bp->outer_tpid_bd =
1968                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
1969                                 break;
1970                 case RTE_ETHER_TYPE_VLAN:
1971                         bp->outer_tpid_bd =
1972                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
1973                                 break;
1974                 case 0x9100:
1975                         bp->outer_tpid_bd =
1976                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
1977                                 break;
1978                 case 0x9200:
1979                         bp->outer_tpid_bd =
1980                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
1981                                 break;
1982                 case 0x9300:
1983                         bp->outer_tpid_bd =
1984                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
1985                                 break;
1986                 default:
1987                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
1988                         return -EINVAL;
1989                 }
1990                 bp->outer_tpid_bd |= tpid;
1991                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
1992         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
1993                 PMD_DRV_LOG(ERR,
1994                             "Can accelerate only outer vlan in QinQ\n");
1995                 return -EINVAL;
1996         }
1997
1998         return 0;
1999 }
2000
2001 static int
2002 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2003                              struct rte_ether_addr *addr)
2004 {
2005         struct bnxt *bp = dev->data->dev_private;
2006         /* Default Filter is tied to VNIC 0 */
2007         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
2008         struct bnxt_filter_info *filter;
2009         int rc;
2010
2011         rc = is_bnxt_in_error(bp);
2012         if (rc)
2013                 return rc;
2014
2015         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2016                 return -EPERM;
2017
2018         if (rte_is_zero_ether_addr(addr))
2019                 return -EINVAL;
2020
2021         STAILQ_FOREACH(filter, &vnic->filter, next) {
2022                 /* Default Filter is at Index 0 */
2023                 if (filter->mac_index != 0)
2024                         continue;
2025
2026                 memcpy(filter->l2_addr, addr, RTE_ETHER_ADDR_LEN);
2027                 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
2028                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX |
2029                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2030                 filter->enables |=
2031                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
2032                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
2033
2034                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2035                 if (rc) {
2036                         memcpy(filter->l2_addr, bp->mac_addr,
2037                                RTE_ETHER_ADDR_LEN);
2038                         return rc;
2039                 }
2040
2041                 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2042                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2043                 return 0;
2044         }
2045
2046         return 0;
2047 }
2048
2049 static int
2050 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2051                           struct rte_ether_addr *mc_addr_set,
2052                           uint32_t nb_mc_addr)
2053 {
2054         struct bnxt *bp = eth_dev->data->dev_private;
2055         char *mc_addr_list = (char *)mc_addr_set;
2056         struct bnxt_vnic_info *vnic;
2057         uint32_t off = 0, i = 0;
2058         int rc;
2059
2060         rc = is_bnxt_in_error(bp);
2061         if (rc)
2062                 return rc;
2063
2064         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2065
2066         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2067                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2068                 goto allmulti;
2069         }
2070
2071         /* TODO Check for Duplicate mcast addresses */
2072         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2073         for (i = 0; i < nb_mc_addr; i++) {
2074                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2075                         RTE_ETHER_ADDR_LEN);
2076                 off += RTE_ETHER_ADDR_LEN;
2077         }
2078
2079         vnic->mc_addr_cnt = i;
2080         if (vnic->mc_addr_cnt)
2081                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2082         else
2083                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2084
2085 allmulti:
2086         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2087 }
2088
2089 static int
2090 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2091 {
2092         struct bnxt *bp = dev->data->dev_private;
2093         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2094         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2095         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2096         int ret;
2097
2098         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2099                         fw_major, fw_minor, fw_updt);
2100
2101         ret += 1; /* add the size of '\0' */
2102         if (fw_size < (uint32_t)ret)
2103                 return ret;
2104         else
2105                 return 0;
2106 }
2107
2108 static void
2109 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2110         struct rte_eth_rxq_info *qinfo)
2111 {
2112         struct bnxt_rx_queue *rxq;
2113
2114         rxq = dev->data->rx_queues[queue_id];
2115
2116         qinfo->mp = rxq->mb_pool;
2117         qinfo->scattered_rx = dev->data->scattered_rx;
2118         qinfo->nb_desc = rxq->nb_rx_desc;
2119
2120         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2121         qinfo->conf.rx_drop_en = 0;
2122         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2123 }
2124
2125 static void
2126 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2127         struct rte_eth_txq_info *qinfo)
2128 {
2129         struct bnxt_tx_queue *txq;
2130
2131         txq = dev->data->tx_queues[queue_id];
2132
2133         qinfo->nb_desc = txq->nb_tx_desc;
2134
2135         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2136         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2137         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2138
2139         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2140         qinfo->conf.tx_rs_thresh = 0;
2141         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2142 }
2143
2144 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2145 {
2146         struct bnxt *bp = eth_dev->data->dev_private;
2147         uint32_t new_pkt_size;
2148         uint32_t rc = 0;
2149         uint32_t i;
2150
2151         rc = is_bnxt_in_error(bp);
2152         if (rc)
2153                 return rc;
2154
2155         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2156                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2157
2158 #ifdef RTE_ARCH_X86
2159         /*
2160          * If vector-mode tx/rx is active, disallow any MTU change that would
2161          * require scattered receive support.
2162          */
2163         if (eth_dev->data->dev_started &&
2164             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2165              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2166             (new_pkt_size >
2167              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2168                 PMD_DRV_LOG(ERR,
2169                             "MTU change would require scattered rx support. ");
2170                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2171                 return -EINVAL;
2172         }
2173 #endif
2174
2175         if (new_mtu > RTE_ETHER_MTU) {
2176                 bp->flags |= BNXT_FLAG_JUMBO;
2177                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2178                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2179         } else {
2180                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2181                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2182                 bp->flags &= ~BNXT_FLAG_JUMBO;
2183         }
2184
2185         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2186
2187         for (i = 0; i < bp->nr_vnics; i++) {
2188                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2189                 uint16_t size = 0;
2190
2191                 vnic->mru = new_mtu + RTE_ETHER_HDR_LEN +
2192                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
2193                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2194                 if (rc)
2195                         break;
2196
2197                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2198                 size -= RTE_PKTMBUF_HEADROOM;
2199
2200                 if (size < new_mtu) {
2201                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2202                         if (rc)
2203                                 return rc;
2204                 }
2205         }
2206
2207         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2208
2209         return rc;
2210 }
2211
2212 static int
2213 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2214 {
2215         struct bnxt *bp = dev->data->dev_private;
2216         uint16_t vlan = bp->vlan;
2217         int rc;
2218
2219         rc = is_bnxt_in_error(bp);
2220         if (rc)
2221                 return rc;
2222
2223         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2224                 PMD_DRV_LOG(ERR,
2225                         "PVID cannot be modified for this function\n");
2226                 return -ENOTSUP;
2227         }
2228         bp->vlan = on ? pvid : 0;
2229
2230         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2231         if (rc)
2232                 bp->vlan = vlan;
2233         return rc;
2234 }
2235
2236 static int
2237 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2238 {
2239         struct bnxt *bp = dev->data->dev_private;
2240         int rc;
2241
2242         rc = is_bnxt_in_error(bp);
2243         if (rc)
2244                 return rc;
2245
2246         return bnxt_hwrm_port_led_cfg(bp, true);
2247 }
2248
2249 static int
2250 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2251 {
2252         struct bnxt *bp = dev->data->dev_private;
2253         int rc;
2254
2255         rc = is_bnxt_in_error(bp);
2256         if (rc)
2257                 return rc;
2258
2259         return bnxt_hwrm_port_led_cfg(bp, false);
2260 }
2261
2262 static uint32_t
2263 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2264 {
2265         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2266         uint32_t desc = 0, raw_cons = 0, cons;
2267         struct bnxt_cp_ring_info *cpr;
2268         struct bnxt_rx_queue *rxq;
2269         struct rx_pkt_cmpl *rxcmp;
2270         int rc;
2271
2272         rc = is_bnxt_in_error(bp);
2273         if (rc)
2274                 return rc;
2275
2276         rxq = dev->data->rx_queues[rx_queue_id];
2277         cpr = rxq->cp_ring;
2278         raw_cons = cpr->cp_raw_cons;
2279
2280         while (1) {
2281                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2282                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2283                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2284
2285                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2286                         break;
2287                 } else {
2288                         raw_cons++;
2289                         desc++;
2290                 }
2291         }
2292
2293         return desc;
2294 }
2295
2296 static int
2297 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2298 {
2299         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2300         struct bnxt_rx_ring_info *rxr;
2301         struct bnxt_cp_ring_info *cpr;
2302         struct bnxt_sw_rx_bd *rx_buf;
2303         struct rx_pkt_cmpl *rxcmp;
2304         uint32_t cons, cp_cons;
2305         int rc;
2306
2307         if (!rxq)
2308                 return -EINVAL;
2309
2310         rc = is_bnxt_in_error(rxq->bp);
2311         if (rc)
2312                 return rc;
2313
2314         cpr = rxq->cp_ring;
2315         rxr = rxq->rx_ring;
2316
2317         if (offset >= rxq->nb_rx_desc)
2318                 return -EINVAL;
2319
2320         cons = RING_CMP(cpr->cp_ring_struct, offset);
2321         cp_cons = cpr->cp_raw_cons;
2322         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2323
2324         if (cons > cp_cons) {
2325                 if (CMPL_VALID(rxcmp, cpr->valid))
2326                         return RTE_ETH_RX_DESC_DONE;
2327         } else {
2328                 if (CMPL_VALID(rxcmp, !cpr->valid))
2329                         return RTE_ETH_RX_DESC_DONE;
2330         }
2331         rx_buf = &rxr->rx_buf_ring[cons];
2332         if (rx_buf->mbuf == NULL)
2333                 return RTE_ETH_RX_DESC_UNAVAIL;
2334
2335
2336         return RTE_ETH_RX_DESC_AVAIL;
2337 }
2338
2339 static int
2340 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2341 {
2342         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2343         struct bnxt_tx_ring_info *txr;
2344         struct bnxt_cp_ring_info *cpr;
2345         struct bnxt_sw_tx_bd *tx_buf;
2346         struct tx_pkt_cmpl *txcmp;
2347         uint32_t cons, cp_cons;
2348         int rc;
2349
2350         if (!txq)
2351                 return -EINVAL;
2352
2353         rc = is_bnxt_in_error(txq->bp);
2354         if (rc)
2355                 return rc;
2356
2357         cpr = txq->cp_ring;
2358         txr = txq->tx_ring;
2359
2360         if (offset >= txq->nb_tx_desc)
2361                 return -EINVAL;
2362
2363         cons = RING_CMP(cpr->cp_ring_struct, offset);
2364         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2365         cp_cons = cpr->cp_raw_cons;
2366
2367         if (cons > cp_cons) {
2368                 if (CMPL_VALID(txcmp, cpr->valid))
2369                         return RTE_ETH_TX_DESC_UNAVAIL;
2370         } else {
2371                 if (CMPL_VALID(txcmp, !cpr->valid))
2372                         return RTE_ETH_TX_DESC_UNAVAIL;
2373         }
2374         tx_buf = &txr->tx_buf_ring[cons];
2375         if (tx_buf->mbuf == NULL)
2376                 return RTE_ETH_TX_DESC_DONE;
2377
2378         return RTE_ETH_TX_DESC_FULL;
2379 }
2380
2381 static struct bnxt_filter_info *
2382 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2383                                 struct rte_eth_ethertype_filter *efilter,
2384                                 struct bnxt_vnic_info *vnic0,
2385                                 struct bnxt_vnic_info *vnic,
2386                                 int *ret)
2387 {
2388         struct bnxt_filter_info *mfilter = NULL;
2389         int match = 0;
2390         *ret = 0;
2391
2392         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2393                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2394                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2395                         " ethertype filter.", efilter->ether_type);
2396                 *ret = -EINVAL;
2397                 goto exit;
2398         }
2399         if (efilter->queue >= bp->rx_nr_rings) {
2400                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2401                 *ret = -EINVAL;
2402                 goto exit;
2403         }
2404
2405         vnic0 = &bp->vnic_info[0];
2406         vnic = &bp->vnic_info[efilter->queue];
2407         if (vnic == NULL) {
2408                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2409                 *ret = -EINVAL;
2410                 goto exit;
2411         }
2412
2413         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2414                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2415                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2416                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2417                              mfilter->flags ==
2418                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2419                              mfilter->ethertype == efilter->ether_type)) {
2420                                 match = 1;
2421                                 break;
2422                         }
2423                 }
2424         } else {
2425                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2426                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2427                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2428                              mfilter->ethertype == efilter->ether_type &&
2429                              mfilter->flags ==
2430                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2431                                 match = 1;
2432                                 break;
2433                         }
2434         }
2435
2436         if (match)
2437                 *ret = -EEXIST;
2438
2439 exit:
2440         return mfilter;
2441 }
2442
2443 static int
2444 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2445                         enum rte_filter_op filter_op,
2446                         void *arg)
2447 {
2448         struct bnxt *bp = dev->data->dev_private;
2449         struct rte_eth_ethertype_filter *efilter =
2450                         (struct rte_eth_ethertype_filter *)arg;
2451         struct bnxt_filter_info *bfilter, *filter1;
2452         struct bnxt_vnic_info *vnic, *vnic0;
2453         int ret;
2454
2455         if (filter_op == RTE_ETH_FILTER_NOP)
2456                 return 0;
2457
2458         if (arg == NULL) {
2459                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2460                             filter_op);
2461                 return -EINVAL;
2462         }
2463
2464         vnic0 = &bp->vnic_info[0];
2465         vnic = &bp->vnic_info[efilter->queue];
2466
2467         switch (filter_op) {
2468         case RTE_ETH_FILTER_ADD:
2469                 bnxt_match_and_validate_ether_filter(bp, efilter,
2470                                                         vnic0, vnic, &ret);
2471                 if (ret < 0)
2472                         return ret;
2473
2474                 bfilter = bnxt_get_unused_filter(bp);
2475                 if (bfilter == NULL) {
2476                         PMD_DRV_LOG(ERR,
2477                                 "Not enough resources for a new filter.\n");
2478                         return -ENOMEM;
2479                 }
2480                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2481                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2482                        RTE_ETHER_ADDR_LEN);
2483                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2484                        RTE_ETHER_ADDR_LEN);
2485                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2486                 bfilter->ethertype = efilter->ether_type;
2487                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2488
2489                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2490                 if (filter1 == NULL) {
2491                         ret = -EINVAL;
2492                         goto cleanup;
2493                 }
2494                 bfilter->enables |=
2495                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2496                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2497
2498                 bfilter->dst_id = vnic->fw_vnic_id;
2499
2500                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2501                         bfilter->flags =
2502                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2503                 }
2504
2505                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2506                 if (ret)
2507                         goto cleanup;
2508                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2509                 break;
2510         case RTE_ETH_FILTER_DELETE:
2511                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2512                                                         vnic0, vnic, &ret);
2513                 if (ret == -EEXIST) {
2514                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2515
2516                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2517                                       next);
2518                         bnxt_free_filter(bp, filter1);
2519                 } else if (ret == 0) {
2520                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2521                 }
2522                 break;
2523         default:
2524                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2525                 ret = -EINVAL;
2526                 goto error;
2527         }
2528         return ret;
2529 cleanup:
2530         bnxt_free_filter(bp, bfilter);
2531 error:
2532         return ret;
2533 }
2534
2535 static inline int
2536 parse_ntuple_filter(struct bnxt *bp,
2537                     struct rte_eth_ntuple_filter *nfilter,
2538                     struct bnxt_filter_info *bfilter)
2539 {
2540         uint32_t en = 0;
2541
2542         if (nfilter->queue >= bp->rx_nr_rings) {
2543                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2544                 return -EINVAL;
2545         }
2546
2547         switch (nfilter->dst_port_mask) {
2548         case UINT16_MAX:
2549                 bfilter->dst_port_mask = -1;
2550                 bfilter->dst_port = nfilter->dst_port;
2551                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2552                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2553                 break;
2554         default:
2555                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2556                 return -EINVAL;
2557         }
2558
2559         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2560         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2561
2562         switch (nfilter->proto_mask) {
2563         case UINT8_MAX:
2564                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2565                         bfilter->ip_protocol = 17;
2566                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2567                         bfilter->ip_protocol = 6;
2568                 else
2569                         return -EINVAL;
2570                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2571                 break;
2572         default:
2573                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2574                 return -EINVAL;
2575         }
2576
2577         switch (nfilter->dst_ip_mask) {
2578         case UINT32_MAX:
2579                 bfilter->dst_ipaddr_mask[0] = -1;
2580                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2581                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2582                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2583                 break;
2584         default:
2585                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2586                 return -EINVAL;
2587         }
2588
2589         switch (nfilter->src_ip_mask) {
2590         case UINT32_MAX:
2591                 bfilter->src_ipaddr_mask[0] = -1;
2592                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2593                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2594                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2595                 break;
2596         default:
2597                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2598                 return -EINVAL;
2599         }
2600
2601         switch (nfilter->src_port_mask) {
2602         case UINT16_MAX:
2603                 bfilter->src_port_mask = -1;
2604                 bfilter->src_port = nfilter->src_port;
2605                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2606                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2607                 break;
2608         default:
2609                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2610                 return -EINVAL;
2611         }
2612
2613         //TODO Priority
2614         //nfilter->priority = (uint8_t)filter->priority;
2615
2616         bfilter->enables = en;
2617         return 0;
2618 }
2619
2620 static struct bnxt_filter_info*
2621 bnxt_match_ntuple_filter(struct bnxt *bp,
2622                          struct bnxt_filter_info *bfilter,
2623                          struct bnxt_vnic_info **mvnic)
2624 {
2625         struct bnxt_filter_info *mfilter = NULL;
2626         int i;
2627
2628         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2629                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2630                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2631                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2632                             bfilter->src_ipaddr_mask[0] ==
2633                             mfilter->src_ipaddr_mask[0] &&
2634                             bfilter->src_port == mfilter->src_port &&
2635                             bfilter->src_port_mask == mfilter->src_port_mask &&
2636                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2637                             bfilter->dst_ipaddr_mask[0] ==
2638                             mfilter->dst_ipaddr_mask[0] &&
2639                             bfilter->dst_port == mfilter->dst_port &&
2640                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2641                             bfilter->flags == mfilter->flags &&
2642                             bfilter->enables == mfilter->enables) {
2643                                 if (mvnic)
2644                                         *mvnic = vnic;
2645                                 return mfilter;
2646                         }
2647                 }
2648         }
2649         return NULL;
2650 }
2651
2652 static int
2653 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2654                        struct rte_eth_ntuple_filter *nfilter,
2655                        enum rte_filter_op filter_op)
2656 {
2657         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2658         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2659         int ret;
2660
2661         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2662                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2663                 return -EINVAL;
2664         }
2665
2666         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2667                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2668                 return -EINVAL;
2669         }
2670
2671         bfilter = bnxt_get_unused_filter(bp);
2672         if (bfilter == NULL) {
2673                 PMD_DRV_LOG(ERR,
2674                         "Not enough resources for a new filter.\n");
2675                 return -ENOMEM;
2676         }
2677         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2678         if (ret < 0)
2679                 goto free_filter;
2680
2681         vnic = &bp->vnic_info[nfilter->queue];
2682         vnic0 = &bp->vnic_info[0];
2683         filter1 = STAILQ_FIRST(&vnic0->filter);
2684         if (filter1 == NULL) {
2685                 ret = -EINVAL;
2686                 goto free_filter;
2687         }
2688
2689         bfilter->dst_id = vnic->fw_vnic_id;
2690         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2691         bfilter->enables |=
2692                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2693         bfilter->ethertype = 0x800;
2694         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2695
2696         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2697
2698         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2699             bfilter->dst_id == mfilter->dst_id) {
2700                 PMD_DRV_LOG(ERR, "filter exists.\n");
2701                 ret = -EEXIST;
2702                 goto free_filter;
2703         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2704                    bfilter->dst_id != mfilter->dst_id) {
2705                 mfilter->dst_id = vnic->fw_vnic_id;
2706                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2707                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2708                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2709                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2710                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2711                 goto free_filter;
2712         }
2713         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2714                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2715                 ret = -ENOENT;
2716                 goto free_filter;
2717         }
2718
2719         if (filter_op == RTE_ETH_FILTER_ADD) {
2720                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2721                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2722                 if (ret)
2723                         goto free_filter;
2724                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2725         } else {
2726                 if (mfilter == NULL) {
2727                         /* This should not happen. But for Coverity! */
2728                         ret = -ENOENT;
2729                         goto free_filter;
2730                 }
2731                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2732
2733                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2734                 bnxt_free_filter(bp, mfilter);
2735                 mfilter->fw_l2_filter_id = -1;
2736                 bnxt_free_filter(bp, bfilter);
2737                 bfilter->fw_l2_filter_id = -1;
2738         }
2739
2740         return 0;
2741 free_filter:
2742         bfilter->fw_l2_filter_id = -1;
2743         bnxt_free_filter(bp, bfilter);
2744         return ret;
2745 }
2746
2747 static int
2748 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2749                         enum rte_filter_op filter_op,
2750                         void *arg)
2751 {
2752         struct bnxt *bp = dev->data->dev_private;
2753         int ret;
2754
2755         if (filter_op == RTE_ETH_FILTER_NOP)
2756                 return 0;
2757
2758         if (arg == NULL) {
2759                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2760                             filter_op);
2761                 return -EINVAL;
2762         }
2763
2764         switch (filter_op) {
2765         case RTE_ETH_FILTER_ADD:
2766                 ret = bnxt_cfg_ntuple_filter(bp,
2767                         (struct rte_eth_ntuple_filter *)arg,
2768                         filter_op);
2769                 break;
2770         case RTE_ETH_FILTER_DELETE:
2771                 ret = bnxt_cfg_ntuple_filter(bp,
2772                         (struct rte_eth_ntuple_filter *)arg,
2773                         filter_op);
2774                 break;
2775         default:
2776                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2777                 ret = -EINVAL;
2778                 break;
2779         }
2780         return ret;
2781 }
2782
2783 static int
2784 bnxt_parse_fdir_filter(struct bnxt *bp,
2785                        struct rte_eth_fdir_filter *fdir,
2786                        struct bnxt_filter_info *filter)
2787 {
2788         enum rte_fdir_mode fdir_mode =
2789                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2790         struct bnxt_vnic_info *vnic0, *vnic;
2791         struct bnxt_filter_info *filter1;
2792         uint32_t en = 0;
2793         int i;
2794
2795         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2796                 return -EINVAL;
2797
2798         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2799         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2800
2801         switch (fdir->input.flow_type) {
2802         case RTE_ETH_FLOW_IPV4:
2803         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2804                 /* FALLTHROUGH */
2805                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2806                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2807                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2808                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2809                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2810                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2811                 filter->ip_addr_type =
2812                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2813                 filter->src_ipaddr_mask[0] = 0xffffffff;
2814                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2815                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2816                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2817                 filter->ethertype = 0x800;
2818                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2819                 break;
2820         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2821                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2822                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2823                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2824                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2825                 filter->dst_port_mask = 0xffff;
2826                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2827                 filter->src_port_mask = 0xffff;
2828                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2829                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2830                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2831                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2832                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2833                 filter->ip_protocol = 6;
2834                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2835                 filter->ip_addr_type =
2836                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2837                 filter->src_ipaddr_mask[0] = 0xffffffff;
2838                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2839                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2840                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2841                 filter->ethertype = 0x800;
2842                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2843                 break;
2844         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2845                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2846                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2847                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2848                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2849                 filter->dst_port_mask = 0xffff;
2850                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2851                 filter->src_port_mask = 0xffff;
2852                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2853                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2854                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2855                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2856                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2857                 filter->ip_protocol = 17;
2858                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2859                 filter->ip_addr_type =
2860                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2861                 filter->src_ipaddr_mask[0] = 0xffffffff;
2862                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2863                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2864                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2865                 filter->ethertype = 0x800;
2866                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2867                 break;
2868         case RTE_ETH_FLOW_IPV6:
2869         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2870                 /* FALLTHROUGH */
2871                 filter->ip_addr_type =
2872                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2873                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2874                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2875                 rte_memcpy(filter->src_ipaddr,
2876                            fdir->input.flow.ipv6_flow.src_ip, 16);
2877                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2878                 rte_memcpy(filter->dst_ipaddr,
2879                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2880                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2881                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2882                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2883                 memset(filter->src_ipaddr_mask, 0xff, 16);
2884                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2885                 filter->ethertype = 0x86dd;
2886                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2887                 break;
2888         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2889                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2890                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2891                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2892                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2893                 filter->dst_port_mask = 0xffff;
2894                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2895                 filter->src_port_mask = 0xffff;
2896                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2897                 filter->ip_addr_type =
2898                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2899                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2900                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2901                 rte_memcpy(filter->src_ipaddr,
2902                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2903                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2904                 rte_memcpy(filter->dst_ipaddr,
2905                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2906                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2907                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2908                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2909                 memset(filter->src_ipaddr_mask, 0xff, 16);
2910                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2911                 filter->ethertype = 0x86dd;
2912                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2913                 break;
2914         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2915                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2916                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2917                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2918                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2919                 filter->dst_port_mask = 0xffff;
2920                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2921                 filter->src_port_mask = 0xffff;
2922                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2923                 filter->ip_addr_type =
2924                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2925                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2926                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2927                 rte_memcpy(filter->src_ipaddr,
2928                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2929                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2930                 rte_memcpy(filter->dst_ipaddr,
2931                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2932                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2933                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2934                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2935                 memset(filter->src_ipaddr_mask, 0xff, 16);
2936                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2937                 filter->ethertype = 0x86dd;
2938                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2939                 break;
2940         case RTE_ETH_FLOW_L2_PAYLOAD:
2941                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2942                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2943                 break;
2944         case RTE_ETH_FLOW_VXLAN:
2945                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2946                         return -EINVAL;
2947                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2948                 filter->tunnel_type =
2949                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2950                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2951                 break;
2952         case RTE_ETH_FLOW_NVGRE:
2953                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2954                         return -EINVAL;
2955                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2956                 filter->tunnel_type =
2957                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2958                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2959                 break;
2960         case RTE_ETH_FLOW_UNKNOWN:
2961         case RTE_ETH_FLOW_RAW:
2962         case RTE_ETH_FLOW_FRAG_IPV4:
2963         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2964         case RTE_ETH_FLOW_FRAG_IPV6:
2965         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2966         case RTE_ETH_FLOW_IPV6_EX:
2967         case RTE_ETH_FLOW_IPV6_TCP_EX:
2968         case RTE_ETH_FLOW_IPV6_UDP_EX:
2969         case RTE_ETH_FLOW_GENEVE:
2970                 /* FALLTHROUGH */
2971         default:
2972                 return -EINVAL;
2973         }
2974
2975         vnic0 = &bp->vnic_info[0];
2976         vnic = &bp->vnic_info[fdir->action.rx_queue];
2977         if (vnic == NULL) {
2978                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2979                 return -EINVAL;
2980         }
2981
2982
2983         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2984                 rte_memcpy(filter->dst_macaddr,
2985                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2986                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2987         }
2988
2989         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2990                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2991                 filter1 = STAILQ_FIRST(&vnic0->filter);
2992                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2993         } else {
2994                 filter->dst_id = vnic->fw_vnic_id;
2995                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2996                         if (filter->dst_macaddr[i] == 0x00)
2997                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2998                         else
2999                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3000         }
3001
3002         if (filter1 == NULL)
3003                 return -EINVAL;
3004
3005         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3006         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3007
3008         filter->enables = en;
3009
3010         return 0;
3011 }
3012
3013 static struct bnxt_filter_info *
3014 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3015                 struct bnxt_vnic_info **mvnic)
3016 {
3017         struct bnxt_filter_info *mf = NULL;
3018         int i;
3019
3020         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3021                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3022
3023                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3024                         if (mf->filter_type == nf->filter_type &&
3025                             mf->flags == nf->flags &&
3026                             mf->src_port == nf->src_port &&
3027                             mf->src_port_mask == nf->src_port_mask &&
3028                             mf->dst_port == nf->dst_port &&
3029                             mf->dst_port_mask == nf->dst_port_mask &&
3030                             mf->ip_protocol == nf->ip_protocol &&
3031                             mf->ip_addr_type == nf->ip_addr_type &&
3032                             mf->ethertype == nf->ethertype &&
3033                             mf->vni == nf->vni &&
3034                             mf->tunnel_type == nf->tunnel_type &&
3035                             mf->l2_ovlan == nf->l2_ovlan &&
3036                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3037                             mf->l2_ivlan == nf->l2_ivlan &&
3038                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3039                             !memcmp(mf->l2_addr, nf->l2_addr,
3040                                     RTE_ETHER_ADDR_LEN) &&
3041                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3042                                     RTE_ETHER_ADDR_LEN) &&
3043                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3044                                     RTE_ETHER_ADDR_LEN) &&
3045                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3046                                     RTE_ETHER_ADDR_LEN) &&
3047                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3048                                     sizeof(nf->src_ipaddr)) &&
3049                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3050                                     sizeof(nf->src_ipaddr_mask)) &&
3051                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3052                                     sizeof(nf->dst_ipaddr)) &&
3053                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3054                                     sizeof(nf->dst_ipaddr_mask))) {
3055                                 if (mvnic)
3056                                         *mvnic = vnic;
3057                                 return mf;
3058                         }
3059                 }
3060         }
3061         return NULL;
3062 }
3063
3064 static int
3065 bnxt_fdir_filter(struct rte_eth_dev *dev,
3066                  enum rte_filter_op filter_op,
3067                  void *arg)
3068 {
3069         struct bnxt *bp = dev->data->dev_private;
3070         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3071         struct bnxt_filter_info *filter, *match;
3072         struct bnxt_vnic_info *vnic, *mvnic;
3073         int ret = 0, i;
3074
3075         if (filter_op == RTE_ETH_FILTER_NOP)
3076                 return 0;
3077
3078         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3079                 return -EINVAL;
3080
3081         switch (filter_op) {
3082         case RTE_ETH_FILTER_ADD:
3083         case RTE_ETH_FILTER_DELETE:
3084                 /* FALLTHROUGH */
3085                 filter = bnxt_get_unused_filter(bp);
3086                 if (filter == NULL) {
3087                         PMD_DRV_LOG(ERR,
3088                                 "Not enough resources for a new flow.\n");
3089                         return -ENOMEM;
3090                 }
3091
3092                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3093                 if (ret != 0)
3094                         goto free_filter;
3095                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3096
3097                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3098                         vnic = &bp->vnic_info[0];
3099                 else
3100                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3101
3102                 match = bnxt_match_fdir(bp, filter, &mvnic);
3103                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3104                         if (match->dst_id == vnic->fw_vnic_id) {
3105                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3106                                 ret = -EEXIST;
3107                                 goto free_filter;
3108                         } else {
3109                                 match->dst_id = vnic->fw_vnic_id;
3110                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3111                                                                   match->dst_id,
3112                                                                   match);
3113                                 STAILQ_REMOVE(&mvnic->filter, match,
3114                                               bnxt_filter_info, next);
3115                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3116                                 PMD_DRV_LOG(ERR,
3117                                         "Filter with matching pattern exist\n");
3118                                 PMD_DRV_LOG(ERR,
3119                                         "Updated it to new destination q\n");
3120                                 goto free_filter;
3121                         }
3122                 }
3123                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3124                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3125                         ret = -ENOENT;
3126                         goto free_filter;
3127                 }
3128
3129                 if (filter_op == RTE_ETH_FILTER_ADD) {
3130                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3131                                                           filter->dst_id,
3132                                                           filter);
3133                         if (ret)
3134                                 goto free_filter;
3135                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3136                 } else {
3137                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3138                         STAILQ_REMOVE(&vnic->filter, match,
3139                                       bnxt_filter_info, next);
3140                         bnxt_free_filter(bp, match);
3141                         filter->fw_l2_filter_id = -1;
3142                         bnxt_free_filter(bp, filter);
3143                 }
3144                 break;
3145         case RTE_ETH_FILTER_FLUSH:
3146                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3147                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3148
3149                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3150                                 if (filter->filter_type ==
3151                                     HWRM_CFA_NTUPLE_FILTER) {
3152                                         ret =
3153                                         bnxt_hwrm_clear_ntuple_filter(bp,
3154                                                                       filter);
3155                                         STAILQ_REMOVE(&vnic->filter, filter,
3156                                                       bnxt_filter_info, next);
3157                                 }
3158                         }
3159                 }
3160                 return ret;
3161         case RTE_ETH_FILTER_UPDATE:
3162         case RTE_ETH_FILTER_STATS:
3163         case RTE_ETH_FILTER_INFO:
3164                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3165                 break;
3166         default:
3167                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3168                 ret = -EINVAL;
3169                 break;
3170         }
3171         return ret;
3172
3173 free_filter:
3174         filter->fw_l2_filter_id = -1;
3175         bnxt_free_filter(bp, filter);
3176         return ret;
3177 }
3178
3179 static int
3180 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
3181                     enum rte_filter_type filter_type,
3182                     enum rte_filter_op filter_op, void *arg)
3183 {
3184         int ret = 0;
3185
3186         ret = is_bnxt_in_error(dev->data->dev_private);
3187         if (ret)
3188                 return ret;
3189
3190         switch (filter_type) {
3191         case RTE_ETH_FILTER_TUNNEL:
3192                 PMD_DRV_LOG(ERR,
3193                         "filter type: %d: To be implemented\n", filter_type);
3194                 break;
3195         case RTE_ETH_FILTER_FDIR:
3196                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3197                 break;
3198         case RTE_ETH_FILTER_NTUPLE:
3199                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3200                 break;
3201         case RTE_ETH_FILTER_ETHERTYPE:
3202                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3203                 break;
3204         case RTE_ETH_FILTER_GENERIC:
3205                 if (filter_op != RTE_ETH_FILTER_GET)
3206                         return -EINVAL;
3207                 *(const void **)arg = &bnxt_flow_ops;
3208                 break;
3209         default:
3210                 PMD_DRV_LOG(ERR,
3211                         "Filter type (%d) not supported", filter_type);
3212                 ret = -EINVAL;
3213                 break;
3214         }
3215         return ret;
3216 }
3217
3218 static const uint32_t *
3219 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3220 {
3221         static const uint32_t ptypes[] = {
3222                 RTE_PTYPE_L2_ETHER_VLAN,
3223                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3224                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3225                 RTE_PTYPE_L4_ICMP,
3226                 RTE_PTYPE_L4_TCP,
3227                 RTE_PTYPE_L4_UDP,
3228                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3229                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3230                 RTE_PTYPE_INNER_L4_ICMP,
3231                 RTE_PTYPE_INNER_L4_TCP,
3232                 RTE_PTYPE_INNER_L4_UDP,
3233                 RTE_PTYPE_UNKNOWN
3234         };
3235
3236         if (!dev->rx_pkt_burst)
3237                 return NULL;
3238
3239         return ptypes;
3240 }
3241
3242 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3243                          int reg_win)
3244 {
3245         uint32_t reg_base = *reg_arr & 0xfffff000;
3246         uint32_t win_off;
3247         int i;
3248
3249         for (i = 0; i < count; i++) {
3250                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3251                         return -ERANGE;
3252         }
3253         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3254         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3255         return 0;
3256 }
3257
3258 static int bnxt_map_ptp_regs(struct bnxt *bp)
3259 {
3260         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3261         uint32_t *reg_arr;
3262         int rc, i;
3263
3264         reg_arr = ptp->rx_regs;
3265         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3266         if (rc)
3267                 return rc;
3268
3269         reg_arr = ptp->tx_regs;
3270         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3271         if (rc)
3272                 return rc;
3273
3274         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3275                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3276
3277         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3278                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3279
3280         return 0;
3281 }
3282
3283 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3284 {
3285         rte_write32(0, (uint8_t *)bp->bar0 +
3286                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3287         rte_write32(0, (uint8_t *)bp->bar0 +
3288                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3289 }
3290
3291 static uint64_t bnxt_cc_read(struct bnxt *bp)
3292 {
3293         uint64_t ns;
3294
3295         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3296                               BNXT_GRCPF_REG_SYNC_TIME));
3297         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3298                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3299         return ns;
3300 }
3301
3302 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3303 {
3304         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3305         uint32_t fifo;
3306
3307         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3308                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3309         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3310                 return -EAGAIN;
3311
3312         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3313                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3314         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3315                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3316         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3317                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3318
3319         return 0;
3320 }
3321
3322 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3323 {
3324         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3325         struct bnxt_pf_info *pf = &bp->pf;
3326         uint16_t port_id;
3327         uint32_t fifo;
3328
3329         if (!ptp)
3330                 return -ENODEV;
3331
3332         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3333                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3334         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3335                 return -EAGAIN;
3336
3337         port_id = pf->port_id;
3338         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3339                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3340
3341         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3342                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3343         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3344 /*              bnxt_clr_rx_ts(bp);       TBD  */
3345                 return -EBUSY;
3346         }
3347
3348         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3349                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3350         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3351                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3352
3353         return 0;
3354 }
3355
3356 static int
3357 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3358 {
3359         uint64_t ns;
3360         struct bnxt *bp = dev->data->dev_private;
3361         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3362
3363         if (!ptp)
3364                 return 0;
3365
3366         ns = rte_timespec_to_ns(ts);
3367         /* Set the timecounters to a new value. */
3368         ptp->tc.nsec = ns;
3369
3370         return 0;
3371 }
3372
3373 static int
3374 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3375 {
3376         struct bnxt *bp = dev->data->dev_private;
3377         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3378         uint64_t ns, systime_cycles = 0;
3379         int rc = 0;
3380
3381         if (!ptp)
3382                 return 0;
3383
3384         if (BNXT_CHIP_THOR(bp))
3385                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3386                                              &systime_cycles);
3387         else
3388                 systime_cycles = bnxt_cc_read(bp);
3389
3390         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3391         *ts = rte_ns_to_timespec(ns);
3392
3393         return rc;
3394 }
3395 static int
3396 bnxt_timesync_enable(struct rte_eth_dev *dev)
3397 {
3398         struct bnxt *bp = dev->data->dev_private;
3399         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3400         uint32_t shift = 0;
3401         int rc;
3402
3403         if (!ptp)
3404                 return 0;
3405
3406         ptp->rx_filter = 1;
3407         ptp->tx_tstamp_en = 1;
3408         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3409
3410         rc = bnxt_hwrm_ptp_cfg(bp);
3411         if (rc)
3412                 return rc;
3413
3414         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3415         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3416         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3417
3418         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3419         ptp->tc.cc_shift = shift;
3420         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3421
3422         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3423         ptp->rx_tstamp_tc.cc_shift = shift;
3424         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3425
3426         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3427         ptp->tx_tstamp_tc.cc_shift = shift;
3428         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3429
3430         if (!BNXT_CHIP_THOR(bp))
3431                 bnxt_map_ptp_regs(bp);
3432
3433         return 0;
3434 }
3435
3436 static int
3437 bnxt_timesync_disable(struct rte_eth_dev *dev)
3438 {
3439         struct bnxt *bp = dev->data->dev_private;
3440         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3441
3442         if (!ptp)
3443                 return 0;
3444
3445         ptp->rx_filter = 0;
3446         ptp->tx_tstamp_en = 0;
3447         ptp->rxctl = 0;
3448
3449         bnxt_hwrm_ptp_cfg(bp);
3450
3451         if (!BNXT_CHIP_THOR(bp))
3452                 bnxt_unmap_ptp_regs(bp);
3453
3454         return 0;
3455 }
3456
3457 static int
3458 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3459                                  struct timespec *timestamp,
3460                                  uint32_t flags __rte_unused)
3461 {
3462         struct bnxt *bp = dev->data->dev_private;
3463         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3464         uint64_t rx_tstamp_cycles = 0;
3465         uint64_t ns;
3466
3467         if (!ptp)
3468                 return 0;
3469
3470         if (BNXT_CHIP_THOR(bp))
3471                 rx_tstamp_cycles = ptp->rx_timestamp;
3472         else
3473                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3474
3475         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3476         *timestamp = rte_ns_to_timespec(ns);
3477         return  0;
3478 }
3479
3480 static int
3481 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3482                                  struct timespec *timestamp)
3483 {
3484         struct bnxt *bp = dev->data->dev_private;
3485         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3486         uint64_t tx_tstamp_cycles = 0;
3487         uint64_t ns;
3488         int rc = 0;
3489
3490         if (!ptp)
3491                 return 0;
3492
3493         if (BNXT_CHIP_THOR(bp))
3494                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3495                                              &tx_tstamp_cycles);
3496         else
3497                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3498
3499         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3500         *timestamp = rte_ns_to_timespec(ns);
3501
3502         return rc;
3503 }
3504
3505 static int
3506 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3507 {
3508         struct bnxt *bp = dev->data->dev_private;
3509         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3510
3511         if (!ptp)
3512                 return 0;
3513
3514         ptp->tc.nsec += delta;
3515
3516         return 0;
3517 }
3518
3519 static int
3520 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3521 {
3522         struct bnxt *bp = dev->data->dev_private;
3523         int rc;
3524         uint32_t dir_entries;
3525         uint32_t entry_length;
3526
3527         rc = is_bnxt_in_error(bp);
3528         if (rc)
3529                 return rc;
3530
3531         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3532                 bp->pdev->addr.domain, bp->pdev->addr.bus,
3533                 bp->pdev->addr.devid, bp->pdev->addr.function);
3534
3535         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3536         if (rc != 0)
3537                 return rc;
3538
3539         return dir_entries * entry_length;
3540 }
3541
3542 static int
3543 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3544                 struct rte_dev_eeprom_info *in_eeprom)
3545 {
3546         struct bnxt *bp = dev->data->dev_private;
3547         uint32_t index;
3548         uint32_t offset;
3549         int rc;
3550
3551         rc = is_bnxt_in_error(bp);
3552         if (rc)
3553                 return rc;
3554
3555         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3556                 "len = %d\n", bp->pdev->addr.domain,
3557                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3558                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3559
3560         if (in_eeprom->offset == 0) /* special offset value to get directory */
3561                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3562                                                 in_eeprom->data);
3563
3564         index = in_eeprom->offset >> 24;
3565         offset = in_eeprom->offset & 0xffffff;
3566
3567         if (index != 0)
3568                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3569                                            in_eeprom->length, in_eeprom->data);
3570
3571         return 0;
3572 }
3573
3574 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3575 {
3576         switch (dir_type) {
3577         case BNX_DIR_TYPE_CHIMP_PATCH:
3578         case BNX_DIR_TYPE_BOOTCODE:
3579         case BNX_DIR_TYPE_BOOTCODE_2:
3580         case BNX_DIR_TYPE_APE_FW:
3581         case BNX_DIR_TYPE_APE_PATCH:
3582         case BNX_DIR_TYPE_KONG_FW:
3583         case BNX_DIR_TYPE_KONG_PATCH:
3584         case BNX_DIR_TYPE_BONO_FW:
3585         case BNX_DIR_TYPE_BONO_PATCH:
3586                 /* FALLTHROUGH */
3587                 return true;
3588         }
3589
3590         return false;
3591 }
3592
3593 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3594 {
3595         switch (dir_type) {
3596         case BNX_DIR_TYPE_AVS:
3597         case BNX_DIR_TYPE_EXP_ROM_MBA:
3598         case BNX_DIR_TYPE_PCIE:
3599         case BNX_DIR_TYPE_TSCF_UCODE:
3600         case BNX_DIR_TYPE_EXT_PHY:
3601         case BNX_DIR_TYPE_CCM:
3602         case BNX_DIR_TYPE_ISCSI_BOOT:
3603         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3604         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3605                 /* FALLTHROUGH */
3606                 return true;
3607         }
3608
3609         return false;
3610 }
3611
3612 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3613 {
3614         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3615                 bnxt_dir_type_is_other_exec_format(dir_type);
3616 }
3617
3618 static int
3619 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3620                 struct rte_dev_eeprom_info *in_eeprom)
3621 {
3622         struct bnxt *bp = dev->data->dev_private;
3623         uint8_t index, dir_op;
3624         uint16_t type, ext, ordinal, attr;
3625         int rc;
3626
3627         rc = is_bnxt_in_error(bp);
3628         if (rc)
3629                 return rc;
3630
3631         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3632                 "len = %d\n", bp->pdev->addr.domain,
3633                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3634                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3635
3636         if (!BNXT_PF(bp)) {
3637                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3638                 return -EINVAL;
3639         }
3640
3641         type = in_eeprom->magic >> 16;
3642
3643         if (type == 0xffff) { /* special value for directory operations */
3644                 index = in_eeprom->magic & 0xff;
3645                 dir_op = in_eeprom->magic >> 8;
3646                 if (index == 0)
3647                         return -EINVAL;
3648                 switch (dir_op) {
3649                 case 0x0e: /* erase */
3650                         if (in_eeprom->offset != ~in_eeprom->magic)
3651                                 return -EINVAL;
3652                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3653                 default:
3654                         return -EINVAL;
3655                 }
3656         }
3657
3658         /* Create or re-write an NVM item: */
3659         if (bnxt_dir_type_is_executable(type) == true)
3660                 return -EOPNOTSUPP;
3661         ext = in_eeprom->magic & 0xffff;
3662         ordinal = in_eeprom->offset >> 16;
3663         attr = in_eeprom->offset & 0xffff;
3664
3665         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3666                                      in_eeprom->data, in_eeprom->length);
3667 }
3668
3669 /*
3670  * Initialization
3671  */
3672
3673 static const struct eth_dev_ops bnxt_dev_ops = {
3674         .dev_infos_get = bnxt_dev_info_get_op,
3675         .dev_close = bnxt_dev_close_op,
3676         .dev_configure = bnxt_dev_configure_op,
3677         .dev_start = bnxt_dev_start_op,
3678         .dev_stop = bnxt_dev_stop_op,
3679         .dev_set_link_up = bnxt_dev_set_link_up_op,
3680         .dev_set_link_down = bnxt_dev_set_link_down_op,
3681         .stats_get = bnxt_stats_get_op,
3682         .stats_reset = bnxt_stats_reset_op,
3683         .rx_queue_setup = bnxt_rx_queue_setup_op,
3684         .rx_queue_release = bnxt_rx_queue_release_op,
3685         .tx_queue_setup = bnxt_tx_queue_setup_op,
3686         .tx_queue_release = bnxt_tx_queue_release_op,
3687         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3688         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3689         .reta_update = bnxt_reta_update_op,
3690         .reta_query = bnxt_reta_query_op,
3691         .rss_hash_update = bnxt_rss_hash_update_op,
3692         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3693         .link_update = bnxt_link_update_op,
3694         .promiscuous_enable = bnxt_promiscuous_enable_op,
3695         .promiscuous_disable = bnxt_promiscuous_disable_op,
3696         .allmulticast_enable = bnxt_allmulticast_enable_op,
3697         .allmulticast_disable = bnxt_allmulticast_disable_op,
3698         .mac_addr_add = bnxt_mac_addr_add_op,
3699         .mac_addr_remove = bnxt_mac_addr_remove_op,
3700         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3701         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3702         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3703         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3704         .vlan_filter_set = bnxt_vlan_filter_set_op,
3705         .vlan_offload_set = bnxt_vlan_offload_set_op,
3706         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3707         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3708         .mtu_set = bnxt_mtu_set_op,
3709         .mac_addr_set = bnxt_set_default_mac_addr_op,
3710         .xstats_get = bnxt_dev_xstats_get_op,
3711         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3712         .xstats_reset = bnxt_dev_xstats_reset_op,
3713         .fw_version_get = bnxt_fw_version_get,
3714         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3715         .rxq_info_get = bnxt_rxq_info_get_op,
3716         .txq_info_get = bnxt_txq_info_get_op,
3717         .dev_led_on = bnxt_dev_led_on_op,
3718         .dev_led_off = bnxt_dev_led_off_op,
3719         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3720         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3721         .rx_queue_count = bnxt_rx_queue_count_op,
3722         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3723         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3724         .rx_queue_start = bnxt_rx_queue_start,
3725         .rx_queue_stop = bnxt_rx_queue_stop,
3726         .tx_queue_start = bnxt_tx_queue_start,
3727         .tx_queue_stop = bnxt_tx_queue_stop,
3728         .filter_ctrl = bnxt_filter_ctrl_op,
3729         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3730         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3731         .get_eeprom           = bnxt_get_eeprom_op,
3732         .set_eeprom           = bnxt_set_eeprom_op,
3733         .timesync_enable      = bnxt_timesync_enable,
3734         .timesync_disable     = bnxt_timesync_disable,
3735         .timesync_read_time   = bnxt_timesync_read_time,
3736         .timesync_write_time   = bnxt_timesync_write_time,
3737         .timesync_adjust_time = bnxt_timesync_adjust_time,
3738         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3739         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3740 };
3741
3742 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3743 {
3744         uint32_t offset;
3745
3746         /* Only pre-map the reset GRC registers using window 3 */
3747         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3748                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3749
3750         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3751
3752         return offset;
3753 }
3754
3755 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3756 {
3757         struct bnxt_error_recovery_info *info = bp->recovery_info;
3758         uint32_t reg_base = 0xffffffff;
3759         int i;
3760
3761         /* Only pre-map the monitoring GRC registers using window 2 */
3762         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3763                 uint32_t reg = info->status_regs[i];
3764
3765                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3766                         continue;
3767
3768                 if (reg_base == 0xffffffff)
3769                         reg_base = reg & 0xfffff000;
3770                 if ((reg & 0xfffff000) != reg_base)
3771                         return -ERANGE;
3772
3773                 /* Use mask 0xffc as the Lower 2 bits indicates
3774                  * address space location
3775                  */
3776                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3777                                                 (reg & 0xffc);
3778         }
3779
3780         if (reg_base == 0xffffffff)
3781                 return 0;
3782
3783         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3784                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3785
3786         return 0;
3787 }
3788
3789 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3790 {
3791         struct bnxt_error_recovery_info *info = bp->recovery_info;
3792         uint32_t delay = info->delay_after_reset[index];
3793         uint32_t val = info->reset_reg_val[index];
3794         uint32_t reg = info->reset_reg[index];
3795         uint32_t type, offset;
3796
3797         type = BNXT_FW_STATUS_REG_TYPE(reg);
3798         offset = BNXT_FW_STATUS_REG_OFF(reg);
3799
3800         switch (type) {
3801         case BNXT_FW_STATUS_REG_TYPE_CFG:
3802                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3803                 break;
3804         case BNXT_FW_STATUS_REG_TYPE_GRC:
3805                 offset = bnxt_map_reset_regs(bp, offset);
3806                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3807                 break;
3808         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3809                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3810                 break;
3811         }
3812         /* wait on a specific interval of time until core reset is complete */
3813         if (delay)
3814                 rte_delay_ms(delay);
3815 }
3816
3817 static void bnxt_dev_cleanup(struct bnxt *bp)
3818 {
3819         bnxt_set_hwrm_link_config(bp, false);
3820         bp->link_info.link_up = 0;
3821         if (bp->dev_stopped == 0)
3822                 bnxt_dev_stop_op(bp->eth_dev);
3823
3824         bnxt_uninit_resources(bp, true);
3825 }
3826
3827 static int bnxt_restore_filters(struct bnxt *bp)
3828 {
3829         struct rte_eth_dev *dev = bp->eth_dev;
3830         int ret = 0;
3831
3832         if (dev->data->all_multicast)
3833                 ret = bnxt_allmulticast_enable_op(dev);
3834         if (dev->data->promiscuous)
3835                 ret = bnxt_promiscuous_enable_op(dev);
3836
3837         /* TODO restore other filters as well */
3838         return ret;
3839 }
3840
3841 static void bnxt_dev_recover(void *arg)
3842 {
3843         struct bnxt *bp = arg;
3844         int timeout = bp->fw_reset_max_msecs;
3845         int rc = 0;
3846
3847         /* Clear Error flag so that device re-init should happen */
3848         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3849
3850         do {
3851                 rc = bnxt_hwrm_ver_get(bp);
3852                 if (rc == 0)
3853                         break;
3854                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3855                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3856         } while (rc && timeout);
3857
3858         if (rc) {
3859                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3860                 goto err;
3861         }
3862
3863         rc = bnxt_init_resources(bp, true);
3864         if (rc) {
3865                 PMD_DRV_LOG(ERR,
3866                             "Failed to initialize resources after reset\n");
3867                 goto err;
3868         }
3869         /* clear reset flag as the device is initialized now */
3870         bp->flags &= ~BNXT_FLAG_FW_RESET;
3871
3872         rc = bnxt_dev_start_op(bp->eth_dev);
3873         if (rc) {
3874                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3875                 goto err;
3876         }
3877
3878         rc = bnxt_restore_filters(bp);
3879         if (rc)
3880                 goto err;
3881
3882         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3883         return;
3884 err:
3885         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3886         bnxt_uninit_resources(bp, false);
3887         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3888 }
3889
3890 void bnxt_dev_reset_and_resume(void *arg)
3891 {
3892         struct bnxt *bp = arg;
3893         int rc;
3894
3895         bnxt_dev_cleanup(bp);
3896
3897         bnxt_wait_for_device_shutdown(bp);
3898
3899         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3900                                bnxt_dev_recover, (void *)bp);
3901         if (rc)
3902                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3903 }
3904
3905 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3906 {
3907         struct bnxt_error_recovery_info *info = bp->recovery_info;
3908         uint32_t reg = info->status_regs[index];
3909         uint32_t type, offset, val = 0;
3910
3911         type = BNXT_FW_STATUS_REG_TYPE(reg);
3912         offset = BNXT_FW_STATUS_REG_OFF(reg);
3913
3914         switch (type) {
3915         case BNXT_FW_STATUS_REG_TYPE_CFG:
3916                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3917                 break;
3918         case BNXT_FW_STATUS_REG_TYPE_GRC:
3919                 offset = info->mapped_status_regs[index];
3920                 /* FALLTHROUGH */
3921         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3922                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3923                                        offset));
3924                 break;
3925         }
3926
3927         return val;
3928 }
3929
3930 static int bnxt_fw_reset_all(struct bnxt *bp)
3931 {
3932         struct bnxt_error_recovery_info *info = bp->recovery_info;
3933         uint32_t i;
3934         int rc = 0;
3935
3936         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3937                 /* Reset through master function driver */
3938                 for (i = 0; i < info->reg_array_cnt; i++)
3939                         bnxt_write_fw_reset_reg(bp, i);
3940                 /* Wait for time specified by FW after triggering reset */
3941                 rte_delay_ms(info->master_func_wait_period_after_reset);
3942         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3943                 /* Reset with the help of Kong processor */
3944                 rc = bnxt_hwrm_fw_reset(bp);
3945                 if (rc)
3946                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3947         }
3948
3949         return rc;
3950 }
3951
3952 static void bnxt_fw_reset_cb(void *arg)
3953 {
3954         struct bnxt *bp = arg;
3955         struct bnxt_error_recovery_info *info = bp->recovery_info;
3956         int rc = 0;
3957
3958         /* Only Master function can do FW reset */
3959         if (bnxt_is_master_func(bp) &&
3960             bnxt_is_recovery_enabled(bp)) {
3961                 rc = bnxt_fw_reset_all(bp);
3962                 if (rc) {
3963                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3964                         return;
3965                 }
3966         }
3967
3968         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3969          * EXCEPTION_FATAL_ASYNC event to all the functions
3970          * (including MASTER FUNC). After receiving this Async, all the active
3971          * drivers should treat this case as FW initiated recovery
3972          */
3973         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3974                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3975                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3976
3977                 /* To recover from error */
3978                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3979                                   (void *)bp);
3980         }
3981 }
3982
3983 /* Driver should poll FW heartbeat, reset_counter with the frequency
3984  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3985  * When the driver detects heartbeat stop or change in reset_counter,
3986  * it has to trigger a reset to recover from the error condition.
3987  * A “master PF” is the function who will have the privilege to
3988  * initiate the chimp reset. The master PF will be elected by the
3989  * firmware and will be notified through async message.
3990  */
3991 static void bnxt_check_fw_health(void *arg)
3992 {
3993         struct bnxt *bp = arg;
3994         struct bnxt_error_recovery_info *info = bp->recovery_info;
3995         uint32_t val = 0, wait_msec;
3996
3997         if (!info || !bnxt_is_recovery_enabled(bp) ||
3998             is_bnxt_in_error(bp))
3999                 return;
4000
4001         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4002         if (val == info->last_heart_beat)
4003                 goto reset;
4004
4005         info->last_heart_beat = val;
4006
4007         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4008         if (val != info->last_reset_counter)
4009                 goto reset;
4010
4011         info->last_reset_counter = val;
4012
4013         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4014                           bnxt_check_fw_health, (void *)bp);
4015
4016         return;
4017 reset:
4018         /* Stop DMA to/from device */
4019         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4020         bp->flags |= BNXT_FLAG_FW_RESET;
4021
4022         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4023
4024         if (bnxt_is_master_func(bp))
4025                 wait_msec = info->master_func_wait_period;
4026         else
4027                 wait_msec = info->normal_func_wait_period;
4028
4029         rte_eal_alarm_set(US_PER_MS * wait_msec,
4030                           bnxt_fw_reset_cb, (void *)bp);
4031 }
4032
4033 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4034 {
4035         uint32_t polling_freq;
4036
4037         if (!bnxt_is_recovery_enabled(bp))
4038                 return;
4039
4040         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4041                 return;
4042
4043         polling_freq = bp->recovery_info->driver_polling_freq;
4044
4045         rte_eal_alarm_set(US_PER_MS * polling_freq,
4046                           bnxt_check_fw_health, (void *)bp);
4047         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4048 }
4049
4050 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4051 {
4052         if (!bnxt_is_recovery_enabled(bp))
4053                 return;
4054
4055         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4056         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4057 }
4058
4059 static bool bnxt_vf_pciid(uint16_t id)
4060 {
4061         if (id == BROADCOM_DEV_ID_57304_VF ||
4062             id == BROADCOM_DEV_ID_57406_VF ||
4063             id == BROADCOM_DEV_ID_5731X_VF ||
4064             id == BROADCOM_DEV_ID_5741X_VF ||
4065             id == BROADCOM_DEV_ID_57414_VF ||
4066             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
4067             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
4068             id == BROADCOM_DEV_ID_58802_VF ||
4069             id == BROADCOM_DEV_ID_57500_VF1 ||
4070             id == BROADCOM_DEV_ID_57500_VF2)
4071                 return true;
4072         return false;
4073 }
4074
4075 bool bnxt_stratus_device(struct bnxt *bp)
4076 {
4077         uint16_t id = bp->pdev->id.device_id;
4078
4079         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
4080             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
4081             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
4082                 return true;
4083         return false;
4084 }
4085
4086 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4087 {
4088         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4089         struct bnxt *bp = eth_dev->data->dev_private;
4090
4091         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4092         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4093         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4094         if (!bp->bar0 || !bp->doorbell_base) {
4095                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4096                 return -ENODEV;
4097         }
4098
4099         bp->eth_dev = eth_dev;
4100         bp->pdev = pci_dev;
4101
4102         return 0;
4103 }
4104
4105 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
4106                                   struct bnxt_ctx_pg_info *ctx_pg,
4107                                   uint32_t mem_size,
4108                                   const char *suffix,
4109                                   uint16_t idx)
4110 {
4111         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4112         const struct rte_memzone *mz = NULL;
4113         char mz_name[RTE_MEMZONE_NAMESIZE];
4114         rte_iova_t mz_phys_addr;
4115         uint64_t valid_bits = 0;
4116         uint32_t sz;
4117         int i;
4118
4119         if (!mem_size)
4120                 return 0;
4121
4122         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4123                          BNXT_PAGE_SIZE;
4124         rmem->page_size = BNXT_PAGE_SIZE;
4125         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4126         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4127         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4128
4129         valid_bits = PTU_PTE_VALID;
4130
4131         if (rmem->nr_pages > 1) {
4132                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4133                          "bnxt_ctx_pg_tbl%s_%x_%d",
4134                          suffix, idx, bp->eth_dev->data->port_id);
4135                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4136                 mz = rte_memzone_lookup(mz_name);
4137                 if (!mz) {
4138                         mz = rte_memzone_reserve_aligned(mz_name,
4139                                                 rmem->nr_pages * 8,
4140                                                 SOCKET_ID_ANY,
4141                                                 RTE_MEMZONE_2MB |
4142                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4143                                                 RTE_MEMZONE_IOVA_CONTIG,
4144                                                 BNXT_PAGE_SIZE);
4145                         if (mz == NULL)
4146                                 return -ENOMEM;
4147                 }
4148
4149                 memset(mz->addr, 0, mz->len);
4150                 mz_phys_addr = mz->iova;
4151                 if ((unsigned long)mz->addr == mz_phys_addr) {
4152                         PMD_DRV_LOG(DEBUG,
4153                                     "physical address same as virtual\n");
4154                         PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4155                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
4156                         if (mz_phys_addr == RTE_BAD_IOVA) {
4157                                 PMD_DRV_LOG(ERR,
4158                                         "unable to map addr to phys memory\n");
4159                                 return -ENOMEM;
4160                         }
4161                 }
4162                 rte_mem_lock_page(((char *)mz->addr));
4163
4164                 rmem->pg_tbl = mz->addr;
4165                 rmem->pg_tbl_map = mz_phys_addr;
4166                 rmem->pg_tbl_mz = mz;
4167         }
4168
4169         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4170                  suffix, idx, bp->eth_dev->data->port_id);
4171         mz = rte_memzone_lookup(mz_name);
4172         if (!mz) {
4173                 mz = rte_memzone_reserve_aligned(mz_name,
4174                                                  mem_size,
4175                                                  SOCKET_ID_ANY,
4176                                                  RTE_MEMZONE_1GB |
4177                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4178                                                  RTE_MEMZONE_IOVA_CONTIG,
4179                                                  BNXT_PAGE_SIZE);
4180                 if (mz == NULL)
4181                         return -ENOMEM;
4182         }
4183
4184         memset(mz->addr, 0, mz->len);
4185         mz_phys_addr = mz->iova;
4186         if ((unsigned long)mz->addr == mz_phys_addr) {
4187                 PMD_DRV_LOG(DEBUG,
4188                             "Memzone physical address same as virtual.\n");
4189                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4190                 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
4191                         rte_mem_lock_page(((char *)mz->addr) + sz);
4192                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4193                 if (mz_phys_addr == RTE_BAD_IOVA) {
4194                         PMD_DRV_LOG(ERR,
4195                                     "unable to map addr to phys memory\n");
4196                         return -ENOMEM;
4197                 }
4198         }
4199
4200         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4201                 rte_mem_lock_page(((char *)mz->addr) + sz);
4202                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4203                 rmem->dma_arr[i] = mz_phys_addr + sz;
4204
4205                 if (rmem->nr_pages > 1) {
4206                         if (i == rmem->nr_pages - 2 &&
4207                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4208                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4209                         else if (i == rmem->nr_pages - 1 &&
4210                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4211                                 valid_bits |= PTU_PTE_LAST;
4212
4213                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4214                                                            valid_bits);
4215                 }
4216         }
4217
4218         rmem->mz = mz;
4219         if (rmem->vmem_size)
4220                 rmem->vmem = (void **)mz->addr;
4221         rmem->dma_arr[0] = mz_phys_addr;
4222         return 0;
4223 }
4224
4225 static void bnxt_free_ctx_mem(struct bnxt *bp)
4226 {
4227         int i;
4228
4229         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4230                 return;
4231
4232         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4233         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4234         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4235         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4236         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4237         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4238         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4239         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4240         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4241         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4242         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4243
4244         for (i = 0; i < BNXT_MAX_Q; i++) {
4245                 if (bp->ctx->tqm_mem[i])
4246                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4247         }
4248
4249         rte_free(bp->ctx);
4250         bp->ctx = NULL;
4251 }
4252
4253 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4254
4255 #define min_t(type, x, y) ({                    \
4256         type __min1 = (x);                      \
4257         type __min2 = (y);                      \
4258         __min1 < __min2 ? __min1 : __min2; })
4259
4260 #define max_t(type, x, y) ({                    \
4261         type __max1 = (x);                      \
4262         type __max2 = (y);                      \
4263         __max1 > __max2 ? __max1 : __max2; })
4264
4265 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4266
4267 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4268 {
4269         struct bnxt_ctx_pg_info *ctx_pg;
4270         struct bnxt_ctx_mem_info *ctx;
4271         uint32_t mem_size, ena, entries;
4272         int i, rc;
4273
4274         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4275         if (rc) {
4276                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4277                 return rc;
4278         }
4279         ctx = bp->ctx;
4280         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4281                 return 0;
4282
4283         ctx_pg = &ctx->qp_mem;
4284         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4285         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4286         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4287         if (rc)
4288                 return rc;
4289
4290         ctx_pg = &ctx->srq_mem;
4291         ctx_pg->entries = ctx->srq_max_l2_entries;
4292         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4293         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4294         if (rc)
4295                 return rc;
4296
4297         ctx_pg = &ctx->cq_mem;
4298         ctx_pg->entries = ctx->cq_max_l2_entries;
4299         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4300         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4301         if (rc)
4302                 return rc;
4303
4304         ctx_pg = &ctx->vnic_mem;
4305         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4306                 ctx->vnic_max_ring_table_entries;
4307         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4308         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4309         if (rc)
4310                 return rc;
4311
4312         ctx_pg = &ctx->stat_mem;
4313         ctx_pg->entries = ctx->stat_max_entries;
4314         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4315         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4316         if (rc)
4317                 return rc;
4318
4319         entries = ctx->qp_max_l2_entries +
4320                   ctx->vnic_max_vnic_entries +
4321                   ctx->tqm_min_entries_per_ring;
4322         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4323         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4324                           ctx->tqm_max_entries_per_ring);
4325         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4326                 ctx_pg = ctx->tqm_mem[i];
4327                 /* use min tqm entries for now. */
4328                 ctx_pg->entries = entries;
4329                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4330                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4331                 if (rc)
4332                         return rc;
4333                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4334         }
4335
4336         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4337         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4338         if (rc)
4339                 PMD_DRV_LOG(ERR,
4340                             "Failed to configure context mem: rc = %d\n", rc);
4341         else
4342                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4343
4344         return rc;
4345 }
4346
4347 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4348 {
4349         struct rte_pci_device *pci_dev = bp->pdev;
4350         char mz_name[RTE_MEMZONE_NAMESIZE];
4351         const struct rte_memzone *mz = NULL;
4352         uint32_t total_alloc_len;
4353         rte_iova_t mz_phys_addr;
4354
4355         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4356                 return 0;
4357
4358         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4359                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4360                  pci_dev->addr.bus, pci_dev->addr.devid,
4361                  pci_dev->addr.function, "rx_port_stats");
4362         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4363         mz = rte_memzone_lookup(mz_name);
4364         total_alloc_len =
4365                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4366                                        sizeof(struct rx_port_stats_ext) + 512);
4367         if (!mz) {
4368                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4369                                          SOCKET_ID_ANY,
4370                                          RTE_MEMZONE_2MB |
4371                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4372                                          RTE_MEMZONE_IOVA_CONTIG);
4373                 if (mz == NULL)
4374                         return -ENOMEM;
4375         }
4376         memset(mz->addr, 0, mz->len);
4377         mz_phys_addr = mz->iova;
4378         if ((unsigned long)mz->addr == mz_phys_addr) {
4379                 PMD_DRV_LOG(DEBUG,
4380                             "Memzone physical address same as virtual.\n");
4381                 PMD_DRV_LOG(DEBUG,
4382                             "Using rte_mem_virt2iova()\n");
4383                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4384                 if (mz_phys_addr == RTE_BAD_IOVA) {
4385                         PMD_DRV_LOG(ERR,
4386                                     "Can't map address to physical memory\n");
4387                         return -ENOMEM;
4388                 }
4389         }
4390
4391         bp->rx_mem_zone = (const void *)mz;
4392         bp->hw_rx_port_stats = mz->addr;
4393         bp->hw_rx_port_stats_map = mz_phys_addr;
4394
4395         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4396                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4397                  pci_dev->addr.bus, pci_dev->addr.devid,
4398                  pci_dev->addr.function, "tx_port_stats");
4399         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4400         mz = rte_memzone_lookup(mz_name);
4401         total_alloc_len =
4402                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4403                                        sizeof(struct tx_port_stats_ext) + 512);
4404         if (!mz) {
4405                 mz = rte_memzone_reserve(mz_name,
4406                                          total_alloc_len,
4407                                          SOCKET_ID_ANY,
4408                                          RTE_MEMZONE_2MB |
4409                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4410                                          RTE_MEMZONE_IOVA_CONTIG);
4411                 if (mz == NULL)
4412                         return -ENOMEM;
4413         }
4414         memset(mz->addr, 0, mz->len);
4415         mz_phys_addr = mz->iova;
4416         if ((unsigned long)mz->addr == mz_phys_addr) {
4417                 PMD_DRV_LOG(DEBUG,
4418                             "Memzone physical address same as virtual\n");
4419                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4420                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4421                 if (mz_phys_addr == RTE_BAD_IOVA) {
4422                         PMD_DRV_LOG(ERR,
4423                                     "Can't map address to physical memory\n");
4424                         return -ENOMEM;
4425                 }
4426         }
4427
4428         bp->tx_mem_zone = (const void *)mz;
4429         bp->hw_tx_port_stats = mz->addr;
4430         bp->hw_tx_port_stats_map = mz_phys_addr;
4431         bp->flags |= BNXT_FLAG_PORT_STATS;
4432
4433         /* Display extended statistics if FW supports it */
4434         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4435             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4436             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4437                 return 0;
4438
4439         bp->hw_rx_port_stats_ext = (void *)
4440                 ((uint8_t *)bp->hw_rx_port_stats +
4441                  sizeof(struct rx_port_stats));
4442         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4443                 sizeof(struct rx_port_stats);
4444         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4445
4446         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4447             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4448                 bp->hw_tx_port_stats_ext = (void *)
4449                         ((uint8_t *)bp->hw_tx_port_stats +
4450                          sizeof(struct tx_port_stats));
4451                 bp->hw_tx_port_stats_ext_map =
4452                         bp->hw_tx_port_stats_map +
4453                         sizeof(struct tx_port_stats);
4454                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4455         }
4456
4457         return 0;
4458 }
4459
4460 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4461 {
4462         struct bnxt *bp = eth_dev->data->dev_private;
4463         int rc = 0;
4464
4465         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4466                                                RTE_ETHER_ADDR_LEN *
4467                                                bp->max_l2_ctx,
4468                                                0);
4469         if (eth_dev->data->mac_addrs == NULL) {
4470                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4471                 return -ENOMEM;
4472         }
4473
4474         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4475                 if (BNXT_PF(bp))
4476                         return -EINVAL;
4477
4478                 /* Generate a random MAC address, if none was assigned by PF */
4479                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4480                 bnxt_eth_hw_addr_random(bp->mac_addr);
4481                 PMD_DRV_LOG(INFO,
4482                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4483                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4484                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4485
4486                 rc = bnxt_hwrm_set_mac(bp);
4487                 if (!rc)
4488                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4489                                RTE_ETHER_ADDR_LEN);
4490                 return rc;
4491         }
4492
4493         /* Copy the permanent MAC from the FUNC_QCAPS response */
4494         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4495         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4496
4497         return rc;
4498 }
4499
4500 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4501 {
4502         int rc = 0;
4503
4504         /* MAC is already configured in FW */
4505         if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4506                 return 0;
4507
4508         /* Restore the old MAC configured */
4509         rc = bnxt_hwrm_set_mac(bp);
4510         if (rc)
4511                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4512
4513         return rc;
4514 }
4515
4516 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4517 {
4518         if (!BNXT_PF(bp))
4519                 return;
4520
4521 #define ALLOW_FUNC(x)   \
4522         { \
4523                 uint32_t arg = (x); \
4524                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4525                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4526         }
4527
4528         /* Forward all requests if firmware is new enough */
4529         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4530              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4531             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4532                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4533         } else {
4534                 PMD_DRV_LOG(WARNING,
4535                             "Firmware too old for VF mailbox functionality\n");
4536                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4537         }
4538
4539         /*
4540          * The following are used for driver cleanup. If we disallow these,
4541          * VF drivers can't clean up cleanly.
4542          */
4543         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4544         ALLOW_FUNC(HWRM_VNIC_FREE);
4545         ALLOW_FUNC(HWRM_RING_FREE);
4546         ALLOW_FUNC(HWRM_RING_GRP_FREE);
4547         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4548         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4549         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4550         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4551         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4552 }
4553
4554 static int bnxt_init_fw(struct bnxt *bp)
4555 {
4556         uint16_t mtu;
4557         int rc = 0;
4558
4559         rc = bnxt_hwrm_ver_get(bp);
4560         if (rc)
4561                 return rc;
4562
4563         rc = bnxt_hwrm_func_reset(bp);
4564         if (rc)
4565                 return -EIO;
4566
4567         rc = bnxt_hwrm_vnic_qcaps(bp);
4568         if (rc)
4569                 return rc;
4570
4571         rc = bnxt_hwrm_queue_qportcfg(bp);
4572         if (rc)
4573                 return rc;
4574
4575         /* Get the MAX capabilities for this function.
4576          * This function also allocates context memory for TQM rings and
4577          * informs the firmware about this allocated backing store memory.
4578          */
4579         rc = bnxt_hwrm_func_qcaps(bp);
4580         if (rc)
4581                 return rc;
4582
4583         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4584         if (rc)
4585                 return rc;
4586
4587         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4588         if (rc)
4589                 return rc;
4590
4591         /* Get the adapter error recovery support info */
4592         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4593         if (rc)
4594                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
4595
4596         if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
4597             mtu != bp->eth_dev->data->mtu)
4598                 bp->eth_dev->data->mtu = mtu;
4599
4600         bnxt_hwrm_port_led_qcaps(bp);
4601
4602         return 0;
4603 }
4604
4605 static int
4606 bnxt_init_locks(struct bnxt *bp)
4607 {
4608         int err;
4609
4610         err = pthread_mutex_init(&bp->flow_lock, NULL);
4611         if (err)
4612                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4613         return err;
4614 }
4615
4616 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4617 {
4618         int rc;
4619
4620         rc = bnxt_init_fw(bp);
4621         if (rc)
4622                 return rc;
4623
4624         if (!reconfig_dev) {
4625                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4626                 if (rc)
4627                         return rc;
4628         } else {
4629                 rc = bnxt_restore_dflt_mac(bp);
4630                 if (rc)
4631                         return rc;
4632         }
4633
4634         bnxt_config_vf_req_fwd(bp);
4635
4636         rc = bnxt_hwrm_func_driver_register(bp);
4637         if (rc) {
4638                 PMD_DRV_LOG(ERR, "Failed to register driver");
4639                 return -EBUSY;
4640         }
4641
4642         if (BNXT_PF(bp)) {
4643                 if (bp->pdev->max_vfs) {
4644                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4645                         if (rc) {
4646                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4647                                 return rc;
4648                         }
4649                 } else {
4650                         rc = bnxt_hwrm_allocate_pf_only(bp);
4651                         if (rc) {
4652                                 PMD_DRV_LOG(ERR,
4653                                             "Failed to allocate PF resources");
4654                                 return rc;
4655                         }
4656                 }
4657         }
4658
4659         rc = bnxt_alloc_mem(bp, reconfig_dev);
4660         if (rc)
4661                 return rc;
4662
4663         rc = bnxt_setup_int(bp);
4664         if (rc)
4665                 return rc;
4666
4667         bnxt_init_nic(bp);
4668
4669         rc = bnxt_request_int(bp);
4670         if (rc)
4671                 return rc;
4672
4673         rc = bnxt_init_locks(bp);
4674         if (rc)
4675                 return rc;
4676
4677         return 0;
4678 }
4679
4680 static int
4681 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4682 {
4683         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4684         static int version_printed;
4685         struct bnxt *bp;
4686         int rc;
4687
4688         if (version_printed++ == 0)
4689                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4690
4691         eth_dev->dev_ops = &bnxt_dev_ops;
4692         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4693         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4694
4695         /*
4696          * For secondary processes, we don't initialise any further
4697          * as primary has already done this work.
4698          */
4699         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4700                 return 0;
4701
4702         rte_eth_copy_pci_info(eth_dev, pci_dev);
4703
4704         bp = eth_dev->data->dev_private;
4705
4706         bp->dev_stopped = 1;
4707
4708         if (bnxt_vf_pciid(pci_dev->id.device_id))
4709                 bp->flags |= BNXT_FLAG_VF;
4710
4711         if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
4712             pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
4713             pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
4714             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 ||
4715             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2)
4716                 bp->flags |= BNXT_FLAG_THOR_CHIP;
4717
4718         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4719             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4720             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4721             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4722                 bp->flags |= BNXT_FLAG_STINGRAY;
4723
4724         rc = bnxt_init_board(eth_dev);
4725         if (rc) {
4726                 PMD_DRV_LOG(ERR,
4727                             "Failed to initialize board rc: %x\n", rc);
4728                 return rc;
4729         }
4730
4731         rc = bnxt_alloc_hwrm_resources(bp);
4732         if (rc) {
4733                 PMD_DRV_LOG(ERR,
4734                             "Failed to allocate hwrm resource rc: %x\n", rc);
4735                 goto error_free;
4736         }
4737         rc = bnxt_init_resources(bp, false);
4738         if (rc)
4739                 goto error_free;
4740
4741         rc = bnxt_alloc_stats_mem(bp);
4742         if (rc)
4743                 goto error_free;
4744
4745         PMD_DRV_LOG(INFO,
4746                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4747                     pci_dev->mem_resource[0].phys_addr,
4748                     pci_dev->mem_resource[0].addr);
4749
4750         return 0;
4751
4752 error_free:
4753         bnxt_dev_uninit(eth_dev);
4754         return rc;
4755 }
4756
4757 static void
4758 bnxt_uninit_locks(struct bnxt *bp)
4759 {
4760         pthread_mutex_destroy(&bp->flow_lock);
4761 }
4762
4763 static int
4764 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4765 {
4766         int rc;
4767
4768         bnxt_free_int(bp);
4769         bnxt_free_mem(bp, reconfig_dev);
4770         bnxt_hwrm_func_buf_unrgtr(bp);
4771         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4772         bp->flags &= ~BNXT_FLAG_REGISTERED;
4773         bnxt_free_ctx_mem(bp);
4774         if (!reconfig_dev) {
4775                 bnxt_free_hwrm_resources(bp);
4776
4777                 if (bp->recovery_info != NULL) {
4778                         rte_free(bp->recovery_info);
4779                         bp->recovery_info = NULL;
4780                 }
4781         }
4782
4783         rte_free(bp->ptp_cfg);
4784         bp->ptp_cfg = NULL;
4785         return rc;
4786 }
4787
4788 static int
4789 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4790 {
4791         struct bnxt *bp = eth_dev->data->dev_private;
4792         int rc;
4793
4794         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4795                 return -EPERM;
4796
4797         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4798
4799         rc = bnxt_uninit_resources(bp, false);
4800
4801         if (bp->grp_info != NULL) {
4802                 rte_free(bp->grp_info);
4803                 bp->grp_info = NULL;
4804         }
4805
4806         if (bp->tx_mem_zone) {
4807                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4808                 bp->tx_mem_zone = NULL;
4809         }
4810
4811         if (bp->rx_mem_zone) {
4812                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4813                 bp->rx_mem_zone = NULL;
4814         }
4815
4816         if (bp->dev_stopped == 0)
4817                 bnxt_dev_close_op(eth_dev);
4818         if (bp->pf.vf_info)
4819                 rte_free(bp->pf.vf_info);
4820         eth_dev->dev_ops = NULL;
4821         eth_dev->rx_pkt_burst = NULL;
4822         eth_dev->tx_pkt_burst = NULL;
4823
4824         bnxt_uninit_locks(bp);
4825
4826         return rc;
4827 }
4828
4829 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4830         struct rte_pci_device *pci_dev)
4831 {
4832         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4833                 bnxt_dev_init);
4834 }
4835
4836 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4837 {
4838         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4839                 return rte_eth_dev_pci_generic_remove(pci_dev,
4840                                 bnxt_dev_uninit);
4841         else
4842                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4843 }
4844
4845 static struct rte_pci_driver bnxt_rte_pmd = {
4846         .id_table = bnxt_pci_id_map,
4847         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4848         .probe = bnxt_pci_probe,
4849         .remove = bnxt_pci_remove,
4850 };
4851
4852 static bool
4853 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4854 {
4855         if (strcmp(dev->device->driver->name, drv->driver.name))
4856                 return false;
4857
4858         return true;
4859 }
4860
4861 bool is_bnxt_supported(struct rte_eth_dev *dev)
4862 {
4863         return is_device_supported(dev, &bnxt_rte_pmd);
4864 }
4865
4866 RTE_INIT(bnxt_init_log)
4867 {
4868         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4869         if (bnxt_logtype_driver >= 0)
4870                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4871 }
4872
4873 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4874 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4875 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");