drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <ethdev_driver.h>
  11 #include <ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16 #include <rte_vect.h>
  17
  18 #include "bnxt.h"
  19 #include "bnxt_filter.h"
  20 #include "bnxt_hwrm.h"
  21 #include "bnxt_irq.h"
  22 #include "bnxt_reps.h"
  23 #include "bnxt_ring.h"
  24 #include "bnxt_rxq.h"
  25 #include "bnxt_rxr.h"
  26 #include "bnxt_stats.h"
  27 #include "bnxt_txq.h"
  28 #include "bnxt_txr.h"
  29 #include "bnxt_vnic.h"
  30 #include "hsi_struct_def_dpdk.h"
  31 #include "bnxt_nvm_defs.h"
  32 #include "bnxt_tf_common.h"
  33 #include "ulp_flow_db.h"
  34 #include "rte_pmd_bnxt.h"
  35
  36 #define DRV_MODULE_NAME         "bnxt"
  37 static const char bnxt_version[] =
  38         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  39
  40 /*
  41  * The set of PCI devices this driver supports
  42  */
  43 static const struct rte_pci_id bnxt_pci_id_map[] = {
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  47                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
  87         { .vendor_id = 0, /* sentinel */ },
  88 };
  89
  90 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
  91 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
  92 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
  93 #define BNXT_DEVARG_REPRESENTOR "representor"
  94 #define BNXT_DEVARG_REP_BASED_PF  "rep-based-pf"
  95 #define BNXT_DEVARG_REP_IS_PF  "rep-is-pf"
  96 #define BNXT_DEVARG_REP_Q_R2F  "rep-q-r2f"
  97 #define BNXT_DEVARG_REP_Q_F2R  "rep-q-f2r"
  98 #define BNXT_DEVARG_REP_FC_R2F  "rep-fc-r2f"
  99 #define BNXT_DEVARG_REP_FC_F2R  "rep-fc-f2r"
 100
 101 static const char *const bnxt_dev_args[] = {
 102         BNXT_DEVARG_REPRESENTOR,
 103         BNXT_DEVARG_TRUFLOW,
 104         BNXT_DEVARG_FLOW_XSTAT,
 105         BNXT_DEVARG_MAX_NUM_KFLOWS,
 106         BNXT_DEVARG_REP_BASED_PF,
 107         BNXT_DEVARG_REP_IS_PF,
 108         BNXT_DEVARG_REP_Q_R2F,
 109         BNXT_DEVARG_REP_Q_F2R,
 110         BNXT_DEVARG_REP_FC_R2F,
 111         BNXT_DEVARG_REP_FC_F2R,
 112         NULL
 113 };
 114
 115 /*
 116  * truflow == false to disable the feature
 117  * truflow == true to enable the feature
 118  */
 119 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 120
 121 /*
 122  * flow_xstat == false to disable the feature
 123  * flow_xstat == true to enable the feature
 124  */
 125 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 126
 127 /*
 128  * rep_is_pf == false to indicate VF representor
 129  * rep_is_pf == true to indicate PF representor
 130  */
 131 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)        ((rep_is_pf) > 1)
 132
 133 /*
 134  * rep_based_pf == Physical index of the PF
 135  */
 136 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)  ((rep_based_pf) > 15)
 137 /*
 138  * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
 139  */
 140 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)        ((rep_q_r2f) > 3)
 141
 142 /*
 143  * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
 144  */
 145 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)        ((rep_q_f2r) > 3)
 146
 147 /*
 148  * rep_fc_r2f == Flow control for the representor to endpoint direction
 149  */
 150 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)      ((rep_fc_r2f) > 1)
 151
 152 /*
 153  * rep_fc_f2r == Flow control for the endpoint to representor direction
 154  */
 155 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)      ((rep_fc_f2r) > 1)
 156
 157 int bnxt_cfa_code_dynfield_offset = -1;
 158
 159 /*
 160  * max_num_kflows must be >= 32
 161  * and must be a power-of-2 supported value
 162  * return: 1 -> invalid
 163  *         0 -> valid
 164  */
 165 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 166 {
 167         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 168                 return 1;
 169         return 0;
 170 }
 171
 172 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 173 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 174 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 175 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 176 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 177 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 178 static void bnxt_dev_recover(void *arg);
 179 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 180 static void bnxt_free_rep_info(struct bnxt *bp);
 181
 182 int is_bnxt_in_error(struct bnxt *bp)
 183 {
 184         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 185                 return -EIO;
 186         if (bp->flags & BNXT_FLAG_FW_RESET)
 187                 return -EBUSY;
 188
 189         return 0;
 190 }
 191
 192 /***********************/
 193
 194 /*
 195  * High level utility functions
 196  */
 197
 198 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 199 {
 200         unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
 201                                              BNXT_RSS_TBL_SIZE_P5);
 202
 203         if (!BNXT_CHIP_P5(bp))
 204                 return 1;
 205
 206         return RTE_ALIGN_MUL_CEIL(num_rss_rings,
 207                                   BNXT_RSS_ENTRIES_PER_CTX_P5) /
 208                                   BNXT_RSS_ENTRIES_PER_CTX_P5;
 209 }
 210
 211 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 212 {
 213         if (!BNXT_CHIP_P5(bp))
 214                 return HW_HASH_INDEX_SIZE;
 215
 216         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
 217 }
 218
 219 static void bnxt_free_parent_info(struct bnxt *bp)
 220 {
 221         rte_free(bp->parent);
 222 }
 223
 224 static void bnxt_free_pf_info(struct bnxt *bp)
 225 {
 226         rte_free(bp->pf);
 227 }
 228
 229 static void bnxt_free_link_info(struct bnxt *bp)
 230 {
 231         rte_free(bp->link_info);
 232 }
 233
 234 static void bnxt_free_leds_info(struct bnxt *bp)
 235 {
 236         if (BNXT_VF(bp))
 237                 return;
 238
 239         rte_free(bp->leds);
 240         bp->leds = NULL;
 241 }
 242
 243 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 244 {
 245         rte_free(bp->flow_stat);
 246         bp->flow_stat = NULL;
 247 }
 248
 249 static void bnxt_free_cos_queues(struct bnxt *bp)
 250 {
 251         rte_free(bp->rx_cos_queue);
 252         rte_free(bp->tx_cos_queue);
 253 }
 254
 255 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 256 {
 257         bnxt_free_filter_mem(bp);
 258         bnxt_free_vnic_attributes(bp);
 259         bnxt_free_vnic_mem(bp);
 260
 261         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 262          * If the number of rings change across fw update,
 263          * we don't have much choice except to warn the user.
 264          */
 265         if (!reconfig) {
 266                 bnxt_free_stats(bp);
 267                 bnxt_free_tx_rings(bp);
 268                 bnxt_free_rx_rings(bp);
 269         }
 270         bnxt_free_async_cp_ring(bp);
 271         bnxt_free_rxtx_nq_ring(bp);
 272
 273         rte_free(bp->grp_info);
 274         bp->grp_info = NULL;
 275 }
 276
 277 static int bnxt_alloc_parent_info(struct bnxt *bp)
 278 {
 279         bp->parent = rte_zmalloc("bnxt_parent_info",
 280                                  sizeof(struct bnxt_parent_info), 0);
 281         if (bp->parent == NULL)
 282                 return -ENOMEM;
 283
 284         return 0;
 285 }
 286
 287 static int bnxt_alloc_pf_info(struct bnxt *bp)
 288 {
 289         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 290         if (bp->pf == NULL)
 291                 return -ENOMEM;
 292
 293         return 0;
 294 }
 295
 296 static int bnxt_alloc_link_info(struct bnxt *bp)
 297 {
 298         bp->link_info =
 299                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 300         if (bp->link_info == NULL)
 301                 return -ENOMEM;
 302
 303         return 0;
 304 }
 305
 306 static int bnxt_alloc_leds_info(struct bnxt *bp)
 307 {
 308         if (BNXT_VF(bp))
 309                 return 0;
 310
 311         bp->leds = rte_zmalloc("bnxt_leds",
 312                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 313                                0);
 314         if (bp->leds == NULL)
 315                 return -ENOMEM;
 316
 317         return 0;
 318 }
 319
 320 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 321 {
 322         bp->rx_cos_queue =
 323                 rte_zmalloc("bnxt_rx_cosq",
 324                             BNXT_COS_QUEUE_COUNT *
 325                             sizeof(struct bnxt_cos_queue_info),
 326                             0);
 327         if (bp->rx_cos_queue == NULL)
 328                 return -ENOMEM;
 329
 330         bp->tx_cos_queue =
 331                 rte_zmalloc("bnxt_tx_cosq",
 332                             BNXT_COS_QUEUE_COUNT *
 333                             sizeof(struct bnxt_cos_queue_info),
 334                             0);
 335         if (bp->tx_cos_queue == NULL)
 336                 return -ENOMEM;
 337
 338         return 0;
 339 }
 340
 341 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 342 {
 343         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 344                                     sizeof(struct bnxt_flow_stat_info), 0);
 345         if (bp->flow_stat == NULL)
 346                 return -ENOMEM;
 347
 348         return 0;
 349 }
 350
 351 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 352 {
 353         int rc;
 354
 355         rc = bnxt_alloc_ring_grps(bp);
 356         if (rc)
 357                 goto alloc_mem_err;
 358
 359         rc = bnxt_alloc_async_ring_struct(bp);
 360         if (rc)
 361                 goto alloc_mem_err;
 362
 363         rc = bnxt_alloc_vnic_mem(bp);
 364         if (rc)
 365                 goto alloc_mem_err;
 366
 367         rc = bnxt_alloc_vnic_attributes(bp);
 368         if (rc)
 369                 goto alloc_mem_err;
 370
 371         rc = bnxt_alloc_filter_mem(bp);
 372         if (rc)
 373                 goto alloc_mem_err;
 374
 375         rc = bnxt_alloc_async_cp_ring(bp);
 376         if (rc)
 377                 goto alloc_mem_err;
 378
 379         rc = bnxt_alloc_rxtx_nq_ring(bp);
 380         if (rc)
 381                 goto alloc_mem_err;
 382
 383         if (BNXT_FLOW_XSTATS_EN(bp)) {
 384                 rc = bnxt_alloc_flow_stats_info(bp);
 385                 if (rc)
 386                         goto alloc_mem_err;
 387         }
 388
 389         return 0;
 390
 391 alloc_mem_err:
 392         bnxt_free_mem(bp, reconfig);
 393         return rc;
 394 }
 395
 396 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 397 {
 398         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 399         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 400         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 401         struct bnxt_rx_queue *rxq;
 402         unsigned int j;
 403         int rc;
 404
 405         rc = bnxt_vnic_grp_alloc(bp, vnic);
 406         if (rc)
 407                 goto err_out;
 408
 409         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 410                     vnic_id, vnic, vnic->fw_grp_ids);
 411
 412         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 413         if (rc)
 414                 goto err_out;
 415
 416         /* Alloc RSS context only if RSS mode is enabled */
 417         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 418                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 419
 420                 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
 421                         PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
 422                                     bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
 423                         PMD_DRV_LOG(ERR,
 424                                     "Only queues 0-%d will be in RSS table\n",
 425                                     BNXT_RSS_TBL_SIZE_P5 - 1);
 426                 }
 427
 428                 rc = 0;
 429                 for (j = 0; j < nr_ctxs; j++) {
 430                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 431                         if (rc)
 432                                 break;
 433                 }
 434                 if (rc) {
 435                         PMD_DRV_LOG(ERR,
 436                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 437                                     vnic_id, j, rc);
 438                         goto err_out;
 439                 }
 440                 vnic->num_lb_ctxts = nr_ctxs;
 441         }
 442
 443         /*
 444          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 445          * setting is not available at this time, it will not be
 446          * configured correctly in the CFA.
 447          */
 448         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 449                 vnic->vlan_strip = true;
 450         else
 451                 vnic->vlan_strip = false;
 452
 453         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 454         if (rc)
 455                 goto err_out;
 456
 457         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 458         if (rc)
 459                 goto err_out;
 460
 461         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 462                 rxq = bp->eth_dev->data->rx_queues[j];
 463
 464                 PMD_DRV_LOG(DEBUG,
 465                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 466                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 467
 468                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 469                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 470                 else
 471                         vnic->rx_queue_cnt++;
 472         }
 473
 474         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 475
 476         rc = bnxt_vnic_rss_configure(bp, vnic);
 477         if (rc)
 478                 goto err_out;
 479
 480         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 481
 482         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 483                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 484         else
 485                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 486
 487         return 0;
 488 err_out:
 489         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 490                     vnic_id, rc);
 491         return rc;
 492 }
 493
 494 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 495 {
 496         int rc = 0;
 497
 498         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 499                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 500         if (rc)
 501                 return rc;
 502
 503         PMD_DRV_LOG(DEBUG,
 504                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 505                     " rx_fc_in_tbl.ctx_id = %d\n",
 506                     bp->flow_stat->rx_fc_in_tbl.va,
 507                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 508                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 509
 510         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 511                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 512         if (rc)
 513                 return rc;
 514
 515         PMD_DRV_LOG(DEBUG,
 516                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 517                     " rx_fc_out_tbl.ctx_id = %d\n",
 518                     bp->flow_stat->rx_fc_out_tbl.va,
 519                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 520                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 521
 522         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 523                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 524         if (rc)
 525                 return rc;
 526
 527         PMD_DRV_LOG(DEBUG,
 528                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 529                     " tx_fc_in_tbl.ctx_id = %d\n",
 530                     bp->flow_stat->tx_fc_in_tbl.va,
 531                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 532                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 533
 534         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 535                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 536         if (rc)
 537                 return rc;
 538
 539         PMD_DRV_LOG(DEBUG,
 540                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 541                     " tx_fc_out_tbl.ctx_id = %d\n",
 542                     bp->flow_stat->tx_fc_out_tbl.va,
 543                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 544                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 545
 546         memset(bp->flow_stat->rx_fc_out_tbl.va,
 547                0,
 548                bp->flow_stat->rx_fc_out_tbl.size);
 549         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 550                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 551                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 552                                        bp->flow_stat->max_fc,
 553                                        true);
 554         if (rc)
 555                 return rc;
 556
 557         memset(bp->flow_stat->tx_fc_out_tbl.va,
 558                0,
 559                bp->flow_stat->tx_fc_out_tbl.size);
 560         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 561                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 562                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 563                                        bp->flow_stat->max_fc,
 564                                        true);
 565
 566         return rc;
 567 }
 568
 569 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 570                                   struct bnxt_ctx_mem_buf_info *ctx)
 571 {
 572         if (!ctx)
 573                 return -EINVAL;
 574
 575         ctx->va = rte_zmalloc(type, size, 0);
 576         if (ctx->va == NULL)
 577                 return -ENOMEM;
 578         rte_mem_lock_page(ctx->va);
 579         ctx->size = size;
 580         ctx->dma = rte_mem_virt2iova(ctx->va);
 581         if (ctx->dma == RTE_BAD_IOVA)
 582                 return -ENOMEM;
 583
 584         return 0;
 585 }
 586
 587 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 588 {
 589         struct rte_pci_device *pdev = bp->pdev;
 590         char type[RTE_MEMZONE_NAMESIZE];
 591         uint16_t max_fc;
 592         int rc = 0;
 593
 594         max_fc = bp->flow_stat->max_fc;
 595
 596         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 597                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 598         /* 4 bytes for each counter-id */
 599         rc = bnxt_alloc_ctx_mem_buf(type,
 600                                     max_fc * 4,
 601                                     &bp->flow_stat->rx_fc_in_tbl);
 602         if (rc)
 603                 return rc;
 604
 605         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 606                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 607         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 608         rc = bnxt_alloc_ctx_mem_buf(type,
 609                                     max_fc * 16,
 610                                     &bp->flow_stat->rx_fc_out_tbl);
 611         if (rc)
 612                 return rc;
 613
 614         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 615                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 616         /* 4 bytes for each counter-id */
 617         rc = bnxt_alloc_ctx_mem_buf(type,
 618                                     max_fc * 4,
 619                                     &bp->flow_stat->tx_fc_in_tbl);
 620         if (rc)
 621                 return rc;
 622
 623         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 624                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 625         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 626         rc = bnxt_alloc_ctx_mem_buf(type,
 627                                     max_fc * 16,
 628                                     &bp->flow_stat->tx_fc_out_tbl);
 629         if (rc)
 630                 return rc;
 631
 632         rc = bnxt_register_fc_ctx_mem(bp);
 633
 634         return rc;
 635 }
 636
 637 static int bnxt_init_ctx_mem(struct bnxt *bp)
 638 {
 639         int rc = 0;
 640
 641         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 642             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 643             !BNXT_FLOW_XSTATS_EN(bp))
 644                 return 0;
 645
 646         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 647         if (rc)
 648                 return rc;
 649
 650         rc = bnxt_init_fc_ctx_mem(bp);
 651
 652         return rc;
 653 }
 654
 655 static int bnxt_update_phy_setting(struct bnxt *bp)
 656 {
 657         struct rte_eth_link new;
 658         int rc;
 659
 660         rc = bnxt_get_hwrm_link_config(bp, &new);
 661         if (rc) {
 662                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 663                 return rc;
 664         }
 665
 666         /*
 667          * On BCM957508-N2100 adapters, FW will not allow any user other
 668          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 669          * always returns link up. Force phy update always in that case.
 670          */
 671         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 672                 rc = bnxt_set_hwrm_link_config(bp, true);
 673                 if (rc) {
 674                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 675                         return rc;
 676                 }
 677         }
 678
 679         return rc;
 680 }
 681
 682 static int bnxt_start_nic(struct bnxt *bp)
 683 {
 684         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 685         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 686         uint32_t intr_vector = 0;
 687         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 688         uint32_t vec = BNXT_MISC_VEC_ID;
 689         unsigned int i, j;
 690         int rc;
 691
 692         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 693                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 694                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 695                 bp->flags |= BNXT_FLAG_JUMBO;
 696         } else {
 697                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 698                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 699                 bp->flags &= ~BNXT_FLAG_JUMBO;
 700         }
 701
 702         /* THOR does not support ring groups.
 703          * But we will use the array to save RSS context IDs.
 704          */
 705         if (BNXT_CHIP_P5(bp))
 706                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
 707
 708         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 709         if (rc) {
 710                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 711                 goto err_out;
 712         }
 713
 714         rc = bnxt_alloc_hwrm_rings(bp);
 715         if (rc) {
 716                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 717                 goto err_out;
 718         }
 719
 720         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 721         if (rc) {
 722                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 723                 goto err_out;
 724         }
 725
 726         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 727                 goto skip_cosq_cfg;
 728
 729         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 730                 if (bp->rx_cos_queue[i].id != 0xff) {
 731                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 732
 733                         if (!vnic) {
 734                                 PMD_DRV_LOG(ERR,
 735                                             "Num pools more than FW profile\n");
 736                                 rc = -EINVAL;
 737                                 goto err_out;
 738                         }
 739                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 740                         bp->rx_cosq_cnt++;
 741                 }
 742         }
 743
 744 skip_cosq_cfg:
 745         rc = bnxt_mq_rx_configure(bp);
 746         if (rc) {
 747                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 748                 goto err_out;
 749         }
 750
 751         /* default vnic 0 */
 752         rc = bnxt_setup_one_vnic(bp, 0);
 753         if (rc)
 754                 goto err_out;
 755         /* VNIC configuration */
 756         if (BNXT_RFS_NEEDS_VNIC(bp)) {
 757                 for (i = 1; i < bp->nr_vnics; i++) {
 758                         rc = bnxt_setup_one_vnic(bp, i);
 759                         if (rc)
 760                                 goto err_out;
 761                 }
 762         }
 763
 764         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 765         if (rc) {
 766                 PMD_DRV_LOG(ERR,
 767                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 768                 goto err_out;
 769         }
 770
 771         /* check and configure queue intr-vector mapping */
 772         if ((rte_intr_cap_multiple(intr_handle) ||
 773              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 774             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 775                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 776                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 777                 if (intr_vector > bp->rx_cp_nr_rings) {
 778                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 779                                         bp->rx_cp_nr_rings);
 780                         return -ENOTSUP;
 781                 }
 782                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 783                 if (rc)
 784                         return rc;
 785         }
 786
 787         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 788                 intr_handle->intr_vec =
 789                         rte_zmalloc("intr_vec",
 790                                     bp->eth_dev->data->nb_rx_queues *
 791                                     sizeof(int), 0);
 792                 if (intr_handle->intr_vec == NULL) {
 793                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 794                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 795                         rc = -ENOMEM;
 796                         goto err_disable;
 797                 }
 798                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 799                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 800                          intr_handle->intr_vec, intr_handle->nb_efd,
 801                         intr_handle->max_intr);
 802                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 803                      queue_id++) {
 804                         intr_handle->intr_vec[queue_id] =
 805                                                         vec + BNXT_RX_VEC_START;
 806                         if (vec < base + intr_handle->nb_efd - 1)
 807                                 vec++;
 808                 }
 809         }
 810
 811         /* enable uio/vfio intr/eventfd mapping */
 812         rc = rte_intr_enable(intr_handle);
 813 #ifndef RTE_EXEC_ENV_FREEBSD
 814         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 815         if (rc)
 816                 goto err_free;
 817 #endif
 818
 819         rc = bnxt_update_phy_setting(bp);
 820         if (rc)
 821                 goto err_free;
 822
 823         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 824         if (!bp->mark_table)
 825                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 826
 827         return 0;
 828
 829 err_free:
 830         rte_free(intr_handle->intr_vec);
 831 err_disable:
 832         rte_intr_efd_disable(intr_handle);
 833 err_out:
 834         /* Some of the error status returned by FW may not be from errno.h */
 835         if (rc > 0)
 836                 rc = -EIO;
 837
 838         return rc;
 839 }
 840
 841 static int bnxt_shutdown_nic(struct bnxt *bp)
 842 {
 843         bnxt_free_all_hwrm_resources(bp);
 844         bnxt_free_all_filters(bp);
 845         bnxt_free_all_vnics(bp);
 846         return 0;
 847 }
 848
 849 /*
 850  * Device configuration and status function
 851  */
 852
 853 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 854 {
 855         uint32_t link_speed = bp->link_info->support_speeds;
 856         uint32_t speed_capa = 0;
 857
 858         /* If PAM4 is configured, use PAM4 supported speed */
 859         if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
 860                 link_speed = bp->link_info->support_pam4_speeds;
 861
 862         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 863                 speed_capa |= ETH_LINK_SPEED_100M;
 864         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 865                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 866         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 867                 speed_capa |= ETH_LINK_SPEED_1G;
 868         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 869                 speed_capa |= ETH_LINK_SPEED_2_5G;
 870         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 871                 speed_capa |= ETH_LINK_SPEED_10G;
 872         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 873                 speed_capa |= ETH_LINK_SPEED_20G;
 874         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 875                 speed_capa |= ETH_LINK_SPEED_25G;
 876         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 877                 speed_capa |= ETH_LINK_SPEED_40G;
 878         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 879                 speed_capa |= ETH_LINK_SPEED_50G;
 880         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 881                 speed_capa |= ETH_LINK_SPEED_100G;
 882         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
 883                 speed_capa |= ETH_LINK_SPEED_50G;
 884         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
 885                 speed_capa |= ETH_LINK_SPEED_100G;
 886         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
 887                 speed_capa |= ETH_LINK_SPEED_200G;
 888
 889         if (bp->link_info->auto_mode ==
 890             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 891                 speed_capa |= ETH_LINK_SPEED_FIXED;
 892         else
 893                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 894
 895         return speed_capa;
 896 }
 897
 898 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 899                                 struct rte_eth_dev_info *dev_info)
 900 {
 901         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 902         struct bnxt *bp = eth_dev->data->dev_private;
 903         uint16_t max_vnics, i, j, vpool, vrxq;
 904         unsigned int max_rx_rings;
 905         int rc;
 906
 907         rc = is_bnxt_in_error(bp);
 908         if (rc)
 909                 return rc;
 910
 911         /* MAC Specifics */
 912         dev_info->max_mac_addrs = bp->max_l2_ctx;
 913         dev_info->max_hash_mac_addrs = 0;
 914
 915         /* PF/VF specifics */
 916         if (BNXT_PF(bp))
 917                 dev_info->max_vfs = pdev->max_vfs;
 918
 919         max_rx_rings = bnxt_max_rings(bp);
 920         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 921         dev_info->max_rx_queues = max_rx_rings;
 922         dev_info->max_tx_queues = max_rx_rings;
 923         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 924         dev_info->hash_key_size = 40;
 925         max_vnics = bp->max_vnics;
 926
 927         /* MTU specifics */
 928         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 929         dev_info->max_mtu = BNXT_MAX_MTU;
 930
 931         /* Fast path specifics */
 932         dev_info->min_rx_bufsize = 1;
 933         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 934
 935         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 936         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 937                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 938         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 939         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
 940                                     dev_info->tx_queue_offload_capa;
 941         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 942
 943         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 944
 945         /* *INDENT-OFF* */
 946         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 947                 .rx_thresh = {
 948                         .pthresh = 8,
 949                         .hthresh = 8,
 950                         .wthresh = 0,
 951                 },
 952                 .rx_free_thresh = 32,
 953                 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
 954         };
 955
 956         dev_info->default_txconf = (struct rte_eth_txconf) {
 957                 .tx_thresh = {
 958                         .pthresh = 32,
 959                         .hthresh = 0,
 960                         .wthresh = 0,
 961                 },
 962                 .tx_free_thresh = 32,
 963                 .tx_rs_thresh = 32,
 964         };
 965         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 966
 967         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 968         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 969         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 970         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 971         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 972
 973         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
 974                 dev_info->switch_info.name = eth_dev->device->name;
 975                 dev_info->switch_info.domain_id = bp->switch_domain_id;
 976                 dev_info->switch_info.port_id =
 977                                 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
 978                                     BNXT_SWITCH_PORT_ID_TRUSTED_VF;
 979         }
 980
 981         /* *INDENT-ON* */
 982
 983         /*
 984          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 985          *       need further investigation.
 986          */
 987
 988         /* VMDq resources */
 989         vpool = 64; /* ETH_64_POOLS */
 990         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 991         for (i = 0; i < 4; vpool >>= 1, i++) {
 992                 if (max_vnics > vpool) {
 993                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 994                                 if (dev_info->max_rx_queues > vrxq) {
 995                                         if (vpool > vrxq)
 996                                                 vpool = vrxq;
 997                                         goto found;
 998                                 }
 999                         }
1000                         /* Not enough resources to support VMDq */
1001                         break;
1002                 }
1003         }
1004         /* Not enough resources to support VMDq */
1005         vpool = 0;
1006         vrxq = 0;
1007 found:
1008         dev_info->max_vmdq_pools = vpool;
1009         dev_info->vmdq_queue_num = vrxq;
1010
1011         dev_info->vmdq_pool_base = 0;
1012         dev_info->vmdq_queue_base = 0;
1013
1014         return 0;
1015 }
1016
1017 /* Configure the device based on the configuration provided */
1018 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1019 {
1020         struct bnxt *bp = eth_dev->data->dev_private;
1021         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1022         int rc;
1023
1024         bp->rx_queues = (void *)eth_dev->data->rx_queues;
1025         bp->tx_queues = (void *)eth_dev->data->tx_queues;
1026         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1027         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1028
1029         rc = is_bnxt_in_error(bp);
1030         if (rc)
1031                 return rc;
1032
1033         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1034                 rc = bnxt_hwrm_check_vf_rings(bp);
1035                 if (rc) {
1036                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1037                         return -ENOSPC;
1038                 }
1039
1040                 /* If a resource has already been allocated - in this case
1041                  * it is the async completion ring, free it. Reallocate it after
1042                  * resource reservation. This will ensure the resource counts
1043                  * are calculated correctly.
1044                  */
1045
1046                 pthread_mutex_lock(&bp->def_cp_lock);
1047
1048                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1049                         bnxt_disable_int(bp);
1050                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
1051                 }
1052
1053                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1054                 if (rc) {
1055                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1056                         pthread_mutex_unlock(&bp->def_cp_lock);
1057                         return -ENOSPC;
1058                 }
1059
1060                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1061                         rc = bnxt_alloc_async_cp_ring(bp);
1062                         if (rc) {
1063                                 pthread_mutex_unlock(&bp->def_cp_lock);
1064                                 return rc;
1065                         }
1066                         bnxt_enable_int(bp);
1067                 }
1068
1069                 pthread_mutex_unlock(&bp->def_cp_lock);
1070         }
1071
1072         /* Inherit new configurations */
1073         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1074             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1075             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1076                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1077             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1078             bp->max_stat_ctx)
1079                 goto resource_error;
1080
1081         if (BNXT_HAS_RING_GRPS(bp) &&
1082             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1083                 goto resource_error;
1084
1085         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1086             bp->max_vnics < eth_dev->data->nb_rx_queues)
1087                 goto resource_error;
1088
1089         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1090         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1091
1092         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1093                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1094         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1095
1096         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1097                 eth_dev->data->mtu =
1098                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1099                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1100                         BNXT_NUM_VLANS;
1101                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1102         }
1103         return 0;
1104
1105 resource_error:
1106         PMD_DRV_LOG(ERR,
1107                     "Insufficient resources to support requested config\n");
1108         PMD_DRV_LOG(ERR,
1109                     "Num Queues Requested: Tx %d, Rx %d\n",
1110                     eth_dev->data->nb_tx_queues,
1111                     eth_dev->data->nb_rx_queues);
1112         PMD_DRV_LOG(ERR,
1113                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1114                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1115                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1116         return -ENOSPC;
1117 }
1118
1119 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1120 {
1121         struct rte_eth_link *link = &eth_dev->data->dev_link;
1122
1123         if (link->link_status)
1124                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1125                         eth_dev->data->port_id,
1126                         (uint32_t)link->link_speed,
1127                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1128                         ("full-duplex") : ("half-duplex\n"));
1129         else
1130                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1131                         eth_dev->data->port_id);
1132 }
1133
1134 /*
1135  * Determine whether the current configuration requires support for scattered
1136  * receive; return 1 if scattered receive is required and 0 if not.
1137  */
1138 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1139 {
1140         uint16_t buf_size;
1141         int i;
1142
1143         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1144                 return 1;
1145
1146         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO)
1147                 return 1;
1148
1149         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1150                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1151
1152                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1153                                       RTE_PKTMBUF_HEADROOM);
1154                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1155                         return 1;
1156         }
1157         return 0;
1158 }
1159
1160 static eth_rx_burst_t
1161 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1162 {
1163         struct bnxt *bp = eth_dev->data->dev_private;
1164
1165         /* Disable vector mode RX for Stingray2 for now */
1166         if (BNXT_CHIP_SR2(bp)) {
1167                 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1168                 return bnxt_recv_pkts;
1169         }
1170
1171 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1172 #ifndef RTE_LIBRTE_IEEE1588
1173         /*
1174          * Vector mode receive can be enabled only if scatter rx is not
1175          * in use and rx offloads are limited to VLAN stripping and
1176          * CRC stripping.
1177          */
1178         if (!eth_dev->data->scattered_rx &&
1179             !(eth_dev->data->dev_conf.rxmode.offloads &
1180               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1181                 DEV_RX_OFFLOAD_KEEP_CRC |
1182                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1183                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1184                 DEV_RX_OFFLOAD_UDP_CKSUM |
1185                 DEV_RX_OFFLOAD_TCP_CKSUM |
1186                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1187                 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1188                 DEV_RX_OFFLOAD_RSS_HASH |
1189                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1190             !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp) &&
1191             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1192                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1193                             eth_dev->data->port_id);
1194                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1195                 return bnxt_recv_pkts_vec;
1196         }
1197         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1198                     eth_dev->data->port_id);
1199         PMD_DRV_LOG(INFO,
1200                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1201                     eth_dev->data->port_id,
1202                     eth_dev->data->scattered_rx,
1203                     eth_dev->data->dev_conf.rxmode.offloads);
1204 #endif
1205 #endif
1206         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1207         return bnxt_recv_pkts;
1208 }
1209
1210 static eth_tx_burst_t
1211 bnxt_transmit_function(struct rte_eth_dev *eth_dev)
1212 {
1213         struct bnxt *bp = eth_dev->data->dev_private;
1214
1215         /* Disable vector mode TX for Stingray2 for now */
1216         if (BNXT_CHIP_SR2(bp))
1217                 return bnxt_xmit_pkts;
1218
1219 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1220 #ifndef RTE_LIBRTE_IEEE1588
1221         uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1222
1223         /*
1224          * Vector mode transmit can be enabled only if not using scatter rx
1225          * or tx offloads.
1226          */
1227         if (!eth_dev->data->scattered_rx &&
1228             !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
1229             !BNXT_TRUFLOW_EN(bp) &&
1230             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1231                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1232                             eth_dev->data->port_id);
1233                 return bnxt_xmit_pkts_vec;
1234         }
1235         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1236                     eth_dev->data->port_id);
1237         PMD_DRV_LOG(INFO,
1238                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1239                     eth_dev->data->port_id,
1240                     eth_dev->data->scattered_rx,
1241                     offloads);
1242 #endif
1243 #endif
1244         return bnxt_xmit_pkts;
1245 }
1246
1247 static int bnxt_handle_if_change_status(struct bnxt *bp)
1248 {
1249         int rc;
1250
1251         /* Since fw has undergone a reset and lost all contexts,
1252          * set fatal flag to not issue hwrm during cleanup
1253          */
1254         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1255         bnxt_uninit_resources(bp, true);
1256
1257         /* clear fatal flag so that re-init happens */
1258         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1259         rc = bnxt_init_resources(bp, true);
1260
1261         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1262
1263         return rc;
1264 }
1265
1266 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1267 {
1268         struct bnxt *bp = eth_dev->data->dev_private;
1269         int rc = 0;
1270
1271         if (!bp->link_info->link_up)
1272                 rc = bnxt_set_hwrm_link_config(bp, true);
1273         if (!rc)
1274                 eth_dev->data->dev_link.link_status = 1;
1275
1276         bnxt_print_link_info(eth_dev);
1277         return rc;
1278 }
1279
1280 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1281 {
1282         struct bnxt *bp = eth_dev->data->dev_private;
1283
1284         eth_dev->data->dev_link.link_status = 0;
1285         bnxt_set_hwrm_link_config(bp, false);
1286         bp->link_info->link_up = 0;
1287
1288         return 0;
1289 }
1290
1291 static void bnxt_free_switch_domain(struct bnxt *bp)
1292 {
1293         int rc = 0;
1294
1295         if (bp->switch_domain_id) {
1296                 rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1297                 if (rc)
1298                         PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1299                                     bp->switch_domain_id, rc);
1300         }
1301 }
1302
1303 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev)
1304 {
1305         struct bnxt *bp = eth_dev->data->dev_private;
1306         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1307         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1308         struct rte_eth_link link;
1309         int ret;
1310
1311         eth_dev->data->dev_started = 0;
1312         eth_dev->data->scattered_rx = 0;
1313
1314         /* Prevent crashes when queues are still in use */
1315         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1316         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1317
1318         bnxt_disable_int(bp);
1319
1320         /* disable uio/vfio intr/eventfd mapping */
1321         rte_intr_disable(intr_handle);
1322
1323         /* Stop the child representors for this device */
1324         ret = bnxt_rep_stop_all(bp);
1325         if (ret != 0)
1326                 return ret;
1327
1328         /* delete the bnxt ULP port details */
1329         bnxt_ulp_port_deinit(bp);
1330
1331         bnxt_cancel_fw_health_check(bp);
1332
1333         /* Do not bring link down during reset recovery */
1334         if (!is_bnxt_in_error(bp)) {
1335                 bnxt_dev_set_link_down_op(eth_dev);
1336                 /* Wait for link to be reset */
1337                 if (BNXT_SINGLE_PF(bp))
1338                         rte_delay_ms(500);
1339                 /* clear the recorded link status */
1340                 memset(&link, 0, sizeof(link));
1341                 rte_eth_linkstatus_set(eth_dev, &link);
1342         }
1343
1344         /* Clean queue intr-vector mapping */
1345         rte_intr_efd_disable(intr_handle);
1346         if (intr_handle->intr_vec != NULL) {
1347                 rte_free(intr_handle->intr_vec);
1348                 intr_handle->intr_vec = NULL;
1349         }
1350
1351         bnxt_hwrm_port_clr_stats(bp);
1352         bnxt_free_tx_mbufs(bp);
1353         bnxt_free_rx_mbufs(bp);
1354         /* Process any remaining notifications in default completion queue */
1355         bnxt_int_handler(eth_dev);
1356         bnxt_shutdown_nic(bp);
1357         bnxt_hwrm_if_change(bp, false);
1358
1359         rte_free(bp->mark_table);
1360         bp->mark_table = NULL;
1361
1362         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1363         bp->rx_cosq_cnt = 0;
1364         /* All filters are deleted on a port stop. */
1365         if (BNXT_FLOW_XSTATS_EN(bp))
1366                 bp->flow_stat->flow_count = 0;
1367
1368         return 0;
1369 }
1370
1371 /* Unload the driver, release resources */
1372 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1373 {
1374         struct bnxt *bp = eth_dev->data->dev_private;
1375
1376         pthread_mutex_lock(&bp->err_recovery_lock);
1377         if (bp->flags & BNXT_FLAG_FW_RESET) {
1378                 PMD_DRV_LOG(ERR,
1379                             "Adapter recovering from error..Please retry\n");
1380                 pthread_mutex_unlock(&bp->err_recovery_lock);
1381                 return -EAGAIN;
1382         }
1383         pthread_mutex_unlock(&bp->err_recovery_lock);
1384
1385         return bnxt_dev_stop(eth_dev);
1386 }
1387
1388 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1389 {
1390         struct bnxt *bp = eth_dev->data->dev_private;
1391         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1392         int vlan_mask = 0;
1393         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1394
1395         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1396                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1397                 return -EINVAL;
1398         }
1399
1400         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1401                 PMD_DRV_LOG(ERR,
1402                             "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1403                             bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1404
1405         do {
1406                 rc = bnxt_hwrm_if_change(bp, true);
1407                 if (rc == 0 || rc != -EAGAIN)
1408                         break;
1409
1410                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1411         } while (retry_cnt--);
1412
1413         if (rc)
1414                 return rc;
1415
1416         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1417                 rc = bnxt_handle_if_change_status(bp);
1418                 if (rc)
1419                         return rc;
1420         }
1421
1422         bnxt_enable_int(bp);
1423
1424         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1425
1426         rc = bnxt_start_nic(bp);
1427         if (rc)
1428                 goto error;
1429
1430         eth_dev->data->dev_started = 1;
1431
1432         bnxt_link_update_op(eth_dev, 1);
1433
1434         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1435                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1436         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1437                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1438         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1439         if (rc)
1440                 goto error;
1441
1442         /* Initialize bnxt ULP port details */
1443         rc = bnxt_ulp_port_init(bp);
1444         if (rc)
1445                 goto error;
1446
1447         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1448         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1449
1450         bnxt_schedule_fw_health_check(bp);
1451
1452         return 0;
1453
1454 error:
1455         bnxt_dev_stop(eth_dev);
1456         return rc;
1457 }
1458
1459 static void
1460 bnxt_uninit_locks(struct bnxt *bp)
1461 {
1462         pthread_mutex_destroy(&bp->flow_lock);
1463         pthread_mutex_destroy(&bp->def_cp_lock);
1464         pthread_mutex_destroy(&bp->health_check_lock);
1465         pthread_mutex_destroy(&bp->err_recovery_lock);
1466         if (bp->rep_info) {
1467                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
1468                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
1469         }
1470 }
1471
1472 static void bnxt_drv_uninit(struct bnxt *bp)
1473 {
1474         bnxt_free_switch_domain(bp);
1475         bnxt_free_leds_info(bp);
1476         bnxt_free_cos_queues(bp);
1477         bnxt_free_link_info(bp);
1478         bnxt_free_pf_info(bp);
1479         bnxt_free_parent_info(bp);
1480         bnxt_uninit_locks(bp);
1481
1482         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1483         bp->tx_mem_zone = NULL;
1484         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1485         bp->rx_mem_zone = NULL;
1486
1487         bnxt_hwrm_free_vf_info(bp);
1488
1489         rte_free(bp->grp_info);
1490         bp->grp_info = NULL;
1491 }
1492
1493 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1494 {
1495         struct bnxt *bp = eth_dev->data->dev_private;
1496         int ret = 0;
1497
1498         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1499                 return 0;
1500
1501         pthread_mutex_lock(&bp->err_recovery_lock);
1502         if (bp->flags & BNXT_FLAG_FW_RESET) {
1503                 PMD_DRV_LOG(ERR,
1504                             "Adapter recovering from error...Please retry\n");
1505                 pthread_mutex_unlock(&bp->err_recovery_lock);
1506                 return -EAGAIN;
1507         }
1508         pthread_mutex_unlock(&bp->err_recovery_lock);
1509
1510         /* cancel the recovery handler before remove dev */
1511         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1512         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1513         bnxt_cancel_fc_thread(bp);
1514
1515         if (eth_dev->data->dev_started)
1516                 ret = bnxt_dev_stop(eth_dev);
1517
1518         bnxt_uninit_resources(bp, false);
1519
1520         bnxt_drv_uninit(bp);
1521
1522         return ret;
1523 }
1524
1525 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1526                                     uint32_t index)
1527 {
1528         struct bnxt *bp = eth_dev->data->dev_private;
1529         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1530         struct bnxt_vnic_info *vnic;
1531         struct bnxt_filter_info *filter, *temp_filter;
1532         uint32_t i;
1533
1534         if (is_bnxt_in_error(bp))
1535                 return;
1536
1537         /*
1538          * Loop through all VNICs from the specified filter flow pools to
1539          * remove the corresponding MAC addr filter
1540          */
1541         for (i = 0; i < bp->nr_vnics; i++) {
1542                 if (!(pool_mask & (1ULL << i)))
1543                         continue;
1544
1545                 vnic = &bp->vnic_info[i];
1546                 filter = STAILQ_FIRST(&vnic->filter);
1547                 while (filter) {
1548                         temp_filter = STAILQ_NEXT(filter, next);
1549                         if (filter->mac_index == index) {
1550                                 STAILQ_REMOVE(&vnic->filter, filter,
1551                                                 bnxt_filter_info, next);
1552                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1553                                 bnxt_free_filter(bp, filter);
1554                         }
1555                         filter = temp_filter;
1556                 }
1557         }
1558 }
1559
1560 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1561                                struct rte_ether_addr *mac_addr, uint32_t index,
1562                                uint32_t pool)
1563 {
1564         struct bnxt_filter_info *filter;
1565         int rc = 0;
1566
1567         /* Attach requested MAC address to the new l2_filter */
1568         STAILQ_FOREACH(filter, &vnic->filter, next) {
1569                 if (filter->mac_index == index) {
1570                         PMD_DRV_LOG(DEBUG,
1571                                     "MAC addr already existed for pool %d\n",
1572                                     pool);
1573                         return 0;
1574                 }
1575         }
1576
1577         filter = bnxt_alloc_filter(bp);
1578         if (!filter) {
1579                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1580                 return -ENODEV;
1581         }
1582
1583         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1584          * if the MAC that's been programmed now is a different one, then,
1585          * copy that addr to filter->l2_addr
1586          */
1587         if (mac_addr)
1588                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1589         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1590
1591         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1592         if (!rc) {
1593                 filter->mac_index = index;
1594                 if (filter->mac_index == 0)
1595                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1596                 else
1597                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1598         } else {
1599                 bnxt_free_filter(bp, filter);
1600         }
1601
1602         return rc;
1603 }
1604
1605 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1606                                 struct rte_ether_addr *mac_addr,
1607                                 uint32_t index, uint32_t pool)
1608 {
1609         struct bnxt *bp = eth_dev->data->dev_private;
1610         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1611         int rc = 0;
1612
1613         rc = is_bnxt_in_error(bp);
1614         if (rc)
1615                 return rc;
1616
1617         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1618                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1619                 return -ENOTSUP;
1620         }
1621
1622         if (!vnic) {
1623                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1624                 return -EINVAL;
1625         }
1626
1627         /* Filter settings will get applied when port is started */
1628         if (!eth_dev->data->dev_started)
1629                 return 0;
1630
1631         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1632
1633         return rc;
1634 }
1635
1636 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1637 {
1638         int rc = 0;
1639         struct bnxt *bp = eth_dev->data->dev_private;
1640         struct rte_eth_link new;
1641         int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1642                         BNXT_MIN_LINK_WAIT_CNT;
1643
1644         rc = is_bnxt_in_error(bp);
1645         if (rc)
1646                 return rc;
1647
1648         memset(&new, 0, sizeof(new));
1649         do {
1650                 /* Retrieve link info from hardware */
1651                 rc = bnxt_get_hwrm_link_config(bp, &new);
1652                 if (rc) {
1653                         new.link_speed = ETH_LINK_SPEED_100M;
1654                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1655                         PMD_DRV_LOG(ERR,
1656                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1657                         goto out;
1658                 }
1659
1660                 if (!wait_to_complete || new.link_status)
1661                         break;
1662
1663                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1664         } while (cnt--);
1665
1666         /* Only single function PF can bring phy down.
1667          * When port is stopped, report link down for VF/MH/NPAR functions.
1668          */
1669         if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1670                 memset(&new, 0, sizeof(new));
1671
1672 out:
1673         /* Timed out or success */
1674         if (new.link_status != eth_dev->data->dev_link.link_status ||
1675             new.link_speed != eth_dev->data->dev_link.link_speed) {
1676                 rte_eth_linkstatus_set(eth_dev, &new);
1677
1678                 rte_eth_dev_callback_process(eth_dev,
1679                                              RTE_ETH_EVENT_INTR_LSC,
1680                                              NULL);
1681
1682                 bnxt_print_link_info(eth_dev);
1683         }
1684
1685         return rc;
1686 }
1687
1688 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1689 {
1690         struct bnxt *bp = eth_dev->data->dev_private;
1691         struct bnxt_vnic_info *vnic;
1692         uint32_t old_flags;
1693         int rc;
1694
1695         rc = is_bnxt_in_error(bp);
1696         if (rc)
1697                 return rc;
1698
1699         /* Filter settings will get applied when port is started */
1700         if (!eth_dev->data->dev_started)
1701                 return 0;
1702
1703         if (bp->vnic_info == NULL)
1704                 return 0;
1705
1706         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1707
1708         old_flags = vnic->flags;
1709         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1710         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1711         if (rc != 0)
1712                 vnic->flags = old_flags;
1713
1714         return rc;
1715 }
1716
1717 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1718 {
1719         struct bnxt *bp = eth_dev->data->dev_private;
1720         struct bnxt_vnic_info *vnic;
1721         uint32_t old_flags;
1722         int rc;
1723
1724         rc = is_bnxt_in_error(bp);
1725         if (rc)
1726                 return rc;
1727
1728         /* Filter settings will get applied when port is started */
1729         if (!eth_dev->data->dev_started)
1730                 return 0;
1731
1732         if (bp->vnic_info == NULL)
1733                 return 0;
1734
1735         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1736
1737         old_flags = vnic->flags;
1738         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1739         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1740         if (rc != 0)
1741                 vnic->flags = old_flags;
1742
1743         return rc;
1744 }
1745
1746 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1747 {
1748         struct bnxt *bp = eth_dev->data->dev_private;
1749         struct bnxt_vnic_info *vnic;
1750         uint32_t old_flags;
1751         int rc;
1752
1753         rc = is_bnxt_in_error(bp);
1754         if (rc)
1755                 return rc;
1756
1757         /* Filter settings will get applied when port is started */
1758         if (!eth_dev->data->dev_started)
1759                 return 0;
1760
1761         if (bp->vnic_info == NULL)
1762                 return 0;
1763
1764         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1765
1766         old_flags = vnic->flags;
1767         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1768         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1769         if (rc != 0)
1770                 vnic->flags = old_flags;
1771
1772         return rc;
1773 }
1774
1775 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1776 {
1777         struct bnxt *bp = eth_dev->data->dev_private;
1778         struct bnxt_vnic_info *vnic;
1779         uint32_t old_flags;
1780         int rc;
1781
1782         rc = is_bnxt_in_error(bp);
1783         if (rc)
1784                 return rc;
1785
1786         /* Filter settings will get applied when port is started */
1787         if (!eth_dev->data->dev_started)
1788                 return 0;
1789
1790         if (bp->vnic_info == NULL)
1791                 return 0;
1792
1793         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1794
1795         old_flags = vnic->flags;
1796         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1797         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1798         if (rc != 0)
1799                 vnic->flags = old_flags;
1800
1801         return rc;
1802 }
1803
1804 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1805 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1806 {
1807         if (qid >= bp->rx_nr_rings)
1808                 return NULL;
1809
1810         return bp->eth_dev->data->rx_queues[qid];
1811 }
1812
1813 /* Return rxq corresponding to a given rss table ring/group ID. */
1814 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1815 {
1816         struct bnxt_rx_queue *rxq;
1817         unsigned int i;
1818
1819         if (!BNXT_HAS_RING_GRPS(bp)) {
1820                 for (i = 0; i < bp->rx_nr_rings; i++) {
1821                         rxq = bp->eth_dev->data->rx_queues[i];
1822                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1823                                 return rxq->index;
1824                 }
1825         } else {
1826                 for (i = 0; i < bp->rx_nr_rings; i++) {
1827                         if (bp->grp_info[i].fw_grp_id == fwr)
1828                                 return i;
1829                 }
1830         }
1831
1832         return INVALID_HW_RING_ID;
1833 }
1834
1835 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1836                             struct rte_eth_rss_reta_entry64 *reta_conf,
1837                             uint16_t reta_size)
1838 {
1839         struct bnxt *bp = eth_dev->data->dev_private;
1840         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1841         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1842         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1843         uint16_t idx, sft;
1844         int i, rc;
1845
1846         rc = is_bnxt_in_error(bp);
1847         if (rc)
1848                 return rc;
1849
1850         if (!vnic->rss_table)
1851                 return -EINVAL;
1852
1853         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1854                 return -EINVAL;
1855
1856         if (reta_size != tbl_size) {
1857                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1858                         "(%d) must equal the size supported by the hardware "
1859                         "(%d)\n", reta_size, tbl_size);
1860                 return -EINVAL;
1861         }
1862
1863         for (i = 0; i < reta_size; i++) {
1864                 struct bnxt_rx_queue *rxq;
1865
1866                 idx = i / RTE_RETA_GROUP_SIZE;
1867                 sft = i % RTE_RETA_GROUP_SIZE;
1868
1869                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1870                         continue;
1871
1872                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1873                 if (!rxq) {
1874                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1875                         return -EINVAL;
1876                 }
1877
1878                 if (BNXT_CHIP_P5(bp)) {
1879                         vnic->rss_table[i * 2] =
1880                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1881                         vnic->rss_table[i * 2 + 1] =
1882                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1883                 } else {
1884                         vnic->rss_table[i] =
1885                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1886                 }
1887         }
1888
1889         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1890         return rc;
1891 }
1892
1893 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1894                               struct rte_eth_rss_reta_entry64 *reta_conf,
1895                               uint16_t reta_size)
1896 {
1897         struct bnxt *bp = eth_dev->data->dev_private;
1898         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1899         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1900         uint16_t idx, sft, i;
1901         int rc;
1902
1903         rc = is_bnxt_in_error(bp);
1904         if (rc)
1905                 return rc;
1906
1907         /* Retrieve from the default VNIC */
1908         if (!vnic)
1909                 return -EINVAL;
1910         if (!vnic->rss_table)
1911                 return -EINVAL;
1912
1913         if (reta_size != tbl_size) {
1914                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1915                         "(%d) must equal the size supported by the hardware "
1916                         "(%d)\n", reta_size, tbl_size);
1917                 return -EINVAL;
1918         }
1919
1920         for (idx = 0, i = 0; i < reta_size; i++) {
1921                 idx = i / RTE_RETA_GROUP_SIZE;
1922                 sft = i % RTE_RETA_GROUP_SIZE;
1923
1924                 if (reta_conf[idx].mask & (1ULL << sft)) {
1925                         uint16_t qid;
1926
1927                         if (BNXT_CHIP_P5(bp))
1928                                 qid = bnxt_rss_to_qid(bp,
1929                                                       vnic->rss_table[i * 2]);
1930                         else
1931                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1932
1933                         if (qid == INVALID_HW_RING_ID) {
1934                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1935                                 return -EINVAL;
1936                         }
1937                         reta_conf[idx].reta[sft] = qid;
1938                 }
1939         }
1940
1941         return 0;
1942 }
1943
1944 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1945                                    struct rte_eth_rss_conf *rss_conf)
1946 {
1947         struct bnxt *bp = eth_dev->data->dev_private;
1948         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1949         struct bnxt_vnic_info *vnic;
1950         int rc;
1951
1952         rc = is_bnxt_in_error(bp);
1953         if (rc)
1954                 return rc;
1955
1956         /*
1957          * If RSS enablement were different than dev_configure,
1958          * then return -EINVAL
1959          */
1960         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1961                 if (!rss_conf->rss_hf)
1962                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1963         } else {
1964                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1965                         return -EINVAL;
1966         }
1967
1968         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1969         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
1970                rss_conf,
1971                sizeof(*rss_conf));
1972
1973         /* Update the default RSS VNIC(s) */
1974         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1975         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1976         vnic->hash_mode =
1977                 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
1978                                             ETH_RSS_LEVEL(rss_conf->rss_hf));
1979
1980         /*
1981          * If hashkey is not specified, use the previously configured
1982          * hashkey
1983          */
1984         if (!rss_conf->rss_key)
1985                 goto rss_config;
1986
1987         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1988                 PMD_DRV_LOG(ERR,
1989                             "Invalid hashkey length, should be 16 bytes\n");
1990                 return -EINVAL;
1991         }
1992         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1993
1994 rss_config:
1995         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1996         return rc;
1997 }
1998
1999 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
2000                                      struct rte_eth_rss_conf *rss_conf)
2001 {
2002         struct bnxt *bp = eth_dev->data->dev_private;
2003         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2004         int len, rc;
2005         uint32_t hash_types;
2006
2007         rc = is_bnxt_in_error(bp);
2008         if (rc)
2009                 return rc;
2010
2011         /* RSS configuration is the same for all VNICs */
2012         if (vnic && vnic->rss_hash_key) {
2013                 if (rss_conf->rss_key) {
2014                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
2015                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
2016                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
2017                 }
2018
2019                 hash_types = vnic->hash_type;
2020                 rss_conf->rss_hf = 0;
2021                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
2022                         rss_conf->rss_hf |= ETH_RSS_IPV4;
2023                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
2024                 }
2025                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
2026                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2027                         hash_types &=
2028                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
2029                 }
2030                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
2031                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2032                         hash_types &=
2033                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
2034                 }
2035                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
2036                         rss_conf->rss_hf |= ETH_RSS_IPV6;
2037                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
2038                 }
2039                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
2040                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2041                         hash_types &=
2042                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
2043                 }
2044                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
2045                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2046                         hash_types &=
2047                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2048                 }
2049
2050                 rss_conf->rss_hf |=
2051                         bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2052
2053                 if (hash_types) {
2054                         PMD_DRV_LOG(ERR,
2055                                 "Unknown RSS config from firmware (%08x), RSS disabled",
2056                                 vnic->hash_type);
2057                         return -ENOTSUP;
2058                 }
2059         } else {
2060                 rss_conf->rss_hf = 0;
2061         }
2062         return 0;
2063 }
2064
2065 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2066                                struct rte_eth_fc_conf *fc_conf)
2067 {
2068         struct bnxt *bp = dev->data->dev_private;
2069         struct rte_eth_link link_info;
2070         int rc;
2071
2072         rc = is_bnxt_in_error(bp);
2073         if (rc)
2074                 return rc;
2075
2076         rc = bnxt_get_hwrm_link_config(bp, &link_info);
2077         if (rc)
2078                 return rc;
2079
2080         memset(fc_conf, 0, sizeof(*fc_conf));
2081         if (bp->link_info->auto_pause)
2082                 fc_conf->autoneg = 1;
2083         switch (bp->link_info->pause) {
2084         case 0:
2085                 fc_conf->mode = RTE_FC_NONE;
2086                 break;
2087         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2088                 fc_conf->mode = RTE_FC_TX_PAUSE;
2089                 break;
2090         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2091                 fc_conf->mode = RTE_FC_RX_PAUSE;
2092                 break;
2093         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2094                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2095                 fc_conf->mode = RTE_FC_FULL;
2096                 break;
2097         }
2098         return 0;
2099 }
2100
2101 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2102                                struct rte_eth_fc_conf *fc_conf)
2103 {
2104         struct bnxt *bp = dev->data->dev_private;
2105         int rc;
2106
2107         rc = is_bnxt_in_error(bp);
2108         if (rc)
2109                 return rc;
2110
2111         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2112                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2113                 return -ENOTSUP;
2114         }
2115
2116         switch (fc_conf->mode) {
2117         case RTE_FC_NONE:
2118                 bp->link_info->auto_pause = 0;
2119                 bp->link_info->force_pause = 0;
2120                 break;
2121         case RTE_FC_RX_PAUSE:
2122                 if (fc_conf->autoneg) {
2123                         bp->link_info->auto_pause =
2124                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2125                         bp->link_info->force_pause = 0;
2126                 } else {
2127                         bp->link_info->auto_pause = 0;
2128                         bp->link_info->force_pause =
2129                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2130                 }
2131                 break;
2132         case RTE_FC_TX_PAUSE:
2133                 if (fc_conf->autoneg) {
2134                         bp->link_info->auto_pause =
2135                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2136                         bp->link_info->force_pause = 0;
2137                 } else {
2138                         bp->link_info->auto_pause = 0;
2139                         bp->link_info->force_pause =
2140                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2141                 }
2142                 break;
2143         case RTE_FC_FULL:
2144                 if (fc_conf->autoneg) {
2145                         bp->link_info->auto_pause =
2146                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2147                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2148                         bp->link_info->force_pause = 0;
2149                 } else {
2150                         bp->link_info->auto_pause = 0;
2151                         bp->link_info->force_pause =
2152                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2153                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2154                 }
2155                 break;
2156         }
2157         return bnxt_set_hwrm_link_config(bp, true);
2158 }
2159
2160 /* Add UDP tunneling port */
2161 static int
2162 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2163                          struct rte_eth_udp_tunnel *udp_tunnel)
2164 {
2165         struct bnxt *bp = eth_dev->data->dev_private;
2166         uint16_t tunnel_type = 0;
2167         int rc = 0;
2168
2169         rc = is_bnxt_in_error(bp);
2170         if (rc)
2171                 return rc;
2172
2173         switch (udp_tunnel->prot_type) {
2174         case RTE_TUNNEL_TYPE_VXLAN:
2175                 if (bp->vxlan_port_cnt) {
2176                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2177                                 udp_tunnel->udp_port);
2178                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2179                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2180                                 return -ENOSPC;
2181                         }
2182                         bp->vxlan_port_cnt++;
2183                         return 0;
2184                 }
2185                 tunnel_type =
2186                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2187                 bp->vxlan_port_cnt++;
2188                 break;
2189         case RTE_TUNNEL_TYPE_GENEVE:
2190                 if (bp->geneve_port_cnt) {
2191                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2192                                 udp_tunnel->udp_port);
2193                         if (bp->geneve_port != udp_tunnel->udp_port) {
2194                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2195                                 return -ENOSPC;
2196                         }
2197                         bp->geneve_port_cnt++;
2198                         return 0;
2199                 }
2200                 tunnel_type =
2201                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2202                 bp->geneve_port_cnt++;
2203                 break;
2204         default:
2205                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2206                 return -ENOTSUP;
2207         }
2208         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2209                                              tunnel_type);
2210         return rc;
2211 }
2212
2213 static int
2214 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2215                          struct rte_eth_udp_tunnel *udp_tunnel)
2216 {
2217         struct bnxt *bp = eth_dev->data->dev_private;
2218         uint16_t tunnel_type = 0;
2219         uint16_t port = 0;
2220         int rc = 0;
2221
2222         rc = is_bnxt_in_error(bp);
2223         if (rc)
2224                 return rc;
2225
2226         switch (udp_tunnel->prot_type) {
2227         case RTE_TUNNEL_TYPE_VXLAN:
2228                 if (!bp->vxlan_port_cnt) {
2229                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2230                         return -EINVAL;
2231                 }
2232                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2233                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2234                                 udp_tunnel->udp_port, bp->vxlan_port);
2235                         return -EINVAL;
2236                 }
2237                 if (--bp->vxlan_port_cnt)
2238                         return 0;
2239
2240                 tunnel_type =
2241                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2242                 port = bp->vxlan_fw_dst_port_id;
2243                 break;
2244         case RTE_TUNNEL_TYPE_GENEVE:
2245                 if (!bp->geneve_port_cnt) {
2246                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2247                         return -EINVAL;
2248                 }
2249                 if (bp->geneve_port != udp_tunnel->udp_port) {
2250                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2251                                 udp_tunnel->udp_port, bp->geneve_port);
2252                         return -EINVAL;
2253                 }
2254                 if (--bp->geneve_port_cnt)
2255                         return 0;
2256
2257                 tunnel_type =
2258                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2259                 port = bp->geneve_fw_dst_port_id;
2260                 break;
2261         default:
2262                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2263                 return -ENOTSUP;
2264         }
2265
2266         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2267         return rc;
2268 }
2269
2270 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2271 {
2272         struct bnxt_filter_info *filter;
2273         struct bnxt_vnic_info *vnic;
2274         int rc = 0;
2275         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2276
2277         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2278         filter = STAILQ_FIRST(&vnic->filter);
2279         while (filter) {
2280                 /* Search for this matching MAC+VLAN filter */
2281                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2282                         /* Delete the filter */
2283                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2284                         if (rc)
2285                                 return rc;
2286                         STAILQ_REMOVE(&vnic->filter, filter,
2287                                       bnxt_filter_info, next);
2288                         bnxt_free_filter(bp, filter);
2289                         PMD_DRV_LOG(INFO,
2290                                     "Deleted vlan filter for %d\n",
2291                                     vlan_id);
2292                         return 0;
2293                 }
2294                 filter = STAILQ_NEXT(filter, next);
2295         }
2296         return -ENOENT;
2297 }
2298
2299 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2300 {
2301         struct bnxt_filter_info *filter;
2302         struct bnxt_vnic_info *vnic;
2303         int rc = 0;
2304         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2305                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2306         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2307
2308         /* Implementation notes on the use of VNIC in this command:
2309          *
2310          * By default, these filters belong to default vnic for the function.
2311          * Once these filters are set up, only destination VNIC can be modified.
2312          * If the destination VNIC is not specified in this command,
2313          * then the HWRM shall only create an l2 context id.
2314          */
2315
2316         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2317         filter = STAILQ_FIRST(&vnic->filter);
2318         /* Check if the VLAN has already been added */
2319         while (filter) {
2320                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2321                         return -EEXIST;
2322
2323                 filter = STAILQ_NEXT(filter, next);
2324         }
2325
2326         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2327          * command to create MAC+VLAN filter with the right flags, enables set.
2328          */
2329         filter = bnxt_alloc_filter(bp);
2330         if (!filter) {
2331                 PMD_DRV_LOG(ERR,
2332                             "MAC/VLAN filter alloc failed\n");
2333                 return -ENOMEM;
2334         }
2335         /* MAC + VLAN ID filter */
2336         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2337          * untagged packets are received
2338          *
2339          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2340          * packets and only the programmed vlan's packets are received
2341          */
2342         filter->l2_ivlan = vlan_id;
2343         filter->l2_ivlan_mask = 0x0FFF;
2344         filter->enables |= en;
2345         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2346
2347         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2348         if (rc) {
2349                 /* Free the newly allocated filter as we were
2350                  * not able to create the filter in hardware.
2351                  */
2352                 bnxt_free_filter(bp, filter);
2353                 return rc;
2354         }
2355
2356         filter->mac_index = 0;
2357         /* Add this new filter to the list */
2358         if (vlan_id == 0)
2359                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2360         else
2361                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2362
2363         PMD_DRV_LOG(INFO,
2364                     "Added Vlan filter for %d\n", vlan_id);
2365         return rc;
2366 }
2367
2368 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2369                 uint16_t vlan_id, int on)
2370 {
2371         struct bnxt *bp = eth_dev->data->dev_private;
2372         int rc;
2373
2374         rc = is_bnxt_in_error(bp);
2375         if (rc)
2376                 return rc;
2377
2378         if (!eth_dev->data->dev_started) {
2379                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2380                 return -EINVAL;
2381         }
2382
2383         /* These operations apply to ALL existing MAC/VLAN filters */
2384         if (on)
2385                 return bnxt_add_vlan_filter(bp, vlan_id);
2386         else
2387                 return bnxt_del_vlan_filter(bp, vlan_id);
2388 }
2389
2390 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2391                                     struct bnxt_vnic_info *vnic)
2392 {
2393         struct bnxt_filter_info *filter;
2394         int rc;
2395
2396         filter = STAILQ_FIRST(&vnic->filter);
2397         while (filter) {
2398                 if (filter->mac_index == 0 &&
2399                     !memcmp(filter->l2_addr, bp->mac_addr,
2400                             RTE_ETHER_ADDR_LEN)) {
2401                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2402                         if (!rc) {
2403                                 STAILQ_REMOVE(&vnic->filter, filter,
2404                                               bnxt_filter_info, next);
2405                                 bnxt_free_filter(bp, filter);
2406                         }
2407                         return rc;
2408                 }
2409                 filter = STAILQ_NEXT(filter, next);
2410         }
2411         return 0;
2412 }
2413
2414 static int
2415 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2416 {
2417         struct bnxt_vnic_info *vnic;
2418         unsigned int i;
2419         int rc;
2420
2421         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2422         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2423                 /* Remove any VLAN filters programmed */
2424                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2425                         bnxt_del_vlan_filter(bp, i);
2426
2427                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2428                 if (rc)
2429                         return rc;
2430         } else {
2431                 /* Default filter will allow packets that match the
2432                  * dest mac. So, it has to be deleted, otherwise, we
2433                  * will endup receiving vlan packets for which the
2434                  * filter is not programmed, when hw-vlan-filter
2435                  * configuration is ON
2436                  */
2437                 bnxt_del_dflt_mac_filter(bp, vnic);
2438                 /* This filter will allow only untagged packets */
2439                 bnxt_add_vlan_filter(bp, 0);
2440         }
2441         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2442                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2443
2444         return 0;
2445 }
2446
2447 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2448 {
2449         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2450         unsigned int i;
2451         int rc;
2452
2453         /* Destroy vnic filters and vnic */
2454         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2455             DEV_RX_OFFLOAD_VLAN_FILTER) {
2456                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2457                         bnxt_del_vlan_filter(bp, i);
2458         }
2459         bnxt_del_dflt_mac_filter(bp, vnic);
2460
2461         rc = bnxt_hwrm_vnic_free(bp, vnic);
2462         if (rc)
2463                 return rc;
2464
2465         rte_free(vnic->fw_grp_ids);
2466         vnic->fw_grp_ids = NULL;
2467
2468         vnic->rx_queue_cnt = 0;
2469
2470         return 0;
2471 }
2472
2473 static int
2474 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2475 {
2476         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2477         int rc;
2478
2479         /* Destroy, recreate and reconfigure the default vnic */
2480         rc = bnxt_free_one_vnic(bp, 0);
2481         if (rc)
2482                 return rc;
2483
2484         /* default vnic 0 */
2485         rc = bnxt_setup_one_vnic(bp, 0);
2486         if (rc)
2487                 return rc;
2488
2489         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2490             DEV_RX_OFFLOAD_VLAN_FILTER) {
2491                 rc = bnxt_add_vlan_filter(bp, 0);
2492                 if (rc)
2493                         return rc;
2494                 rc = bnxt_restore_vlan_filters(bp);
2495                 if (rc)
2496                         return rc;
2497         } else {
2498                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2499                 if (rc)
2500                         return rc;
2501         }
2502
2503         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2504         if (rc)
2505                 return rc;
2506
2507         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2508                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2509
2510         return rc;
2511 }
2512
2513 static int
2514 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2515 {
2516         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2517         struct bnxt *bp = dev->data->dev_private;
2518         int rc;
2519
2520         rc = is_bnxt_in_error(bp);
2521         if (rc)
2522                 return rc;
2523
2524         /* Filter settings will get applied when port is started */
2525         if (!dev->data->dev_started)
2526                 return 0;
2527
2528         if (mask & ETH_VLAN_FILTER_MASK) {
2529                 /* Enable or disable VLAN filtering */
2530                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2531                 if (rc)
2532                         return rc;
2533         }
2534
2535         if (mask & ETH_VLAN_STRIP_MASK) {
2536                 /* Enable or disable VLAN stripping */
2537                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2538                 if (rc)
2539                         return rc;
2540         }
2541
2542         if (mask & ETH_VLAN_EXTEND_MASK) {
2543                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2544                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2545                 else
2546                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2547         }
2548
2549         return 0;
2550 }
2551
2552 static int
2553 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2554                       uint16_t tpid)
2555 {
2556         struct bnxt *bp = dev->data->dev_private;
2557         int qinq = dev->data->dev_conf.rxmode.offloads &
2558                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2559
2560         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2561             vlan_type != ETH_VLAN_TYPE_OUTER) {
2562                 PMD_DRV_LOG(ERR,
2563                             "Unsupported vlan type.");
2564                 return -EINVAL;
2565         }
2566         if (!qinq) {
2567                 PMD_DRV_LOG(ERR,
2568                             "QinQ not enabled. Needs to be ON as we can "
2569                             "accelerate only outer vlan\n");
2570                 return -EINVAL;
2571         }
2572
2573         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2574                 switch (tpid) {
2575                 case RTE_ETHER_TYPE_QINQ:
2576                         bp->outer_tpid_bd =
2577                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2578                                 break;
2579                 case RTE_ETHER_TYPE_VLAN:
2580                         bp->outer_tpid_bd =
2581                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2582                                 break;
2583                 case RTE_ETHER_TYPE_QINQ1:
2584                         bp->outer_tpid_bd =
2585                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2586                                 break;
2587                 case RTE_ETHER_TYPE_QINQ2:
2588                         bp->outer_tpid_bd =
2589                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2590                                 break;
2591                 case RTE_ETHER_TYPE_QINQ3:
2592                         bp->outer_tpid_bd =
2593                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2594                                 break;
2595                 default:
2596                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2597                         return -EINVAL;
2598                 }
2599                 bp->outer_tpid_bd |= tpid;
2600                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2601         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2602                 PMD_DRV_LOG(ERR,
2603                             "Can accelerate only outer vlan in QinQ\n");
2604                 return -EINVAL;
2605         }
2606
2607         return 0;
2608 }
2609
2610 static int
2611 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2612                              struct rte_ether_addr *addr)
2613 {
2614         struct bnxt *bp = dev->data->dev_private;
2615         /* Default Filter is tied to VNIC 0 */
2616         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2617         int rc;
2618
2619         rc = is_bnxt_in_error(bp);
2620         if (rc)
2621                 return rc;
2622
2623         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2624                 return -EPERM;
2625
2626         if (rte_is_zero_ether_addr(addr))
2627                 return -EINVAL;
2628
2629         /* Filter settings will get applied when port is started */
2630         if (!dev->data->dev_started)
2631                 return 0;
2632
2633         /* Check if the requested MAC is already added */
2634         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2635                 return 0;
2636
2637         /* Destroy filter and re-create it */
2638         bnxt_del_dflt_mac_filter(bp, vnic);
2639
2640         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2641         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2642                 /* This filter will allow only untagged packets */
2643                 rc = bnxt_add_vlan_filter(bp, 0);
2644         } else {
2645                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2646         }
2647
2648         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2649         return rc;
2650 }
2651
2652 static int
2653 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2654                           struct rte_ether_addr *mc_addr_set,
2655                           uint32_t nb_mc_addr)
2656 {
2657         struct bnxt *bp = eth_dev->data->dev_private;
2658         char *mc_addr_list = (char *)mc_addr_set;
2659         struct bnxt_vnic_info *vnic;
2660         uint32_t off = 0, i = 0;
2661         int rc;
2662
2663         rc = is_bnxt_in_error(bp);
2664         if (rc)
2665                 return rc;
2666
2667         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2668
2669         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2670                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2671                 goto allmulti;
2672         }
2673
2674         /* TODO Check for Duplicate mcast addresses */
2675         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2676         for (i = 0; i < nb_mc_addr; i++) {
2677                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2678                         RTE_ETHER_ADDR_LEN);
2679                 off += RTE_ETHER_ADDR_LEN;
2680         }
2681
2682         vnic->mc_addr_cnt = i;
2683         if (vnic->mc_addr_cnt)
2684                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2685         else
2686                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2687
2688 allmulti:
2689         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2690 }
2691
2692 static int
2693 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2694 {
2695         struct bnxt *bp = dev->data->dev_private;
2696         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2697         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2698         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2699         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2700         int ret;
2701
2702         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2703                         fw_major, fw_minor, fw_updt, fw_rsvd);
2704
2705         ret += 1; /* add the size of '\0' */
2706         if (fw_size < (uint32_t)ret)
2707                 return ret;
2708         else
2709                 return 0;
2710 }
2711
2712 static void
2713 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2714         struct rte_eth_rxq_info *qinfo)
2715 {
2716         struct bnxt *bp = dev->data->dev_private;
2717         struct bnxt_rx_queue *rxq;
2718
2719         if (is_bnxt_in_error(bp))
2720                 return;
2721
2722         rxq = dev->data->rx_queues[queue_id];
2723
2724         qinfo->mp = rxq->mb_pool;
2725         qinfo->scattered_rx = dev->data->scattered_rx;
2726         qinfo->nb_desc = rxq->nb_rx_desc;
2727
2728         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2729         qinfo->conf.rx_drop_en = rxq->drop_en;
2730         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2731         qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2732 }
2733
2734 static void
2735 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2736         struct rte_eth_txq_info *qinfo)
2737 {
2738         struct bnxt *bp = dev->data->dev_private;
2739         struct bnxt_tx_queue *txq;
2740
2741         if (is_bnxt_in_error(bp))
2742                 return;
2743
2744         txq = dev->data->tx_queues[queue_id];
2745
2746         qinfo->nb_desc = txq->nb_tx_desc;
2747
2748         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2749         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2750         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2751
2752         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2753         qinfo->conf.tx_rs_thresh = 0;
2754         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2755         qinfo->conf.offloads = txq->offloads;
2756 }
2757
2758 static const struct {
2759         eth_rx_burst_t pkt_burst;
2760         const char *info;
2761 } bnxt_rx_burst_info[] = {
2762         {bnxt_recv_pkts,        "Scalar"},
2763 #if defined(RTE_ARCH_X86)
2764         {bnxt_recv_pkts_vec,    "Vector SSE"},
2765 #elif defined(RTE_ARCH_ARM64)
2766         {bnxt_recv_pkts_vec,    "Vector Neon"},
2767 #endif
2768 };
2769
2770 static int
2771 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2772                        struct rte_eth_burst_mode *mode)
2773 {
2774         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2775         size_t i;
2776
2777         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2778                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2779                         snprintf(mode->info, sizeof(mode->info), "%s",
2780                                  bnxt_rx_burst_info[i].info);
2781                         return 0;
2782                 }
2783         }
2784
2785         return -EINVAL;
2786 }
2787
2788 static const struct {
2789         eth_tx_burst_t pkt_burst;
2790         const char *info;
2791 } bnxt_tx_burst_info[] = {
2792         {bnxt_xmit_pkts,        "Scalar"},
2793 #if defined(RTE_ARCH_X86)
2794         {bnxt_xmit_pkts_vec,    "Vector SSE"},
2795 #elif defined(RTE_ARCH_ARM64)
2796         {bnxt_xmit_pkts_vec,    "Vector Neon"},
2797 #endif
2798 };
2799
2800 static int
2801 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2802                        struct rte_eth_burst_mode *mode)
2803 {
2804         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2805         size_t i;
2806
2807         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2808                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2809                         snprintf(mode->info, sizeof(mode->info), "%s",
2810                                  bnxt_tx_burst_info[i].info);
2811                         return 0;
2812                 }
2813         }
2814
2815         return -EINVAL;
2816 }
2817
2818 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2819 {
2820         struct bnxt *bp = eth_dev->data->dev_private;
2821         uint32_t new_pkt_size;
2822         uint32_t rc = 0;
2823         uint32_t i;
2824
2825         rc = is_bnxt_in_error(bp);
2826         if (rc)
2827                 return rc;
2828
2829         /* Exit if receive queues are not configured yet */
2830         if (!eth_dev->data->nb_rx_queues)
2831                 return rc;
2832
2833         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2834                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2835
2836         /*
2837          * Disallow any MTU change that would require scattered receive support
2838          * if it is not already enabled.
2839          */
2840         if (eth_dev->data->dev_started &&
2841             !eth_dev->data->scattered_rx &&
2842             (new_pkt_size >
2843              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2844                 PMD_DRV_LOG(ERR,
2845                             "MTU change would require scattered rx support. ");
2846                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2847                 return -EINVAL;
2848         }
2849
2850         if (new_mtu > RTE_ETHER_MTU) {
2851                 bp->flags |= BNXT_FLAG_JUMBO;
2852                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2853                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2854         } else {
2855                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2856                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2857                 bp->flags &= ~BNXT_FLAG_JUMBO;
2858         }
2859
2860         /* Is there a change in mtu setting? */
2861         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2862                 return rc;
2863
2864         for (i = 0; i < bp->nr_vnics; i++) {
2865                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2866                 uint16_t size = 0;
2867
2868                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2869                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2870                 if (rc)
2871                         break;
2872
2873                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2874                 size -= RTE_PKTMBUF_HEADROOM;
2875
2876                 if (size < new_mtu) {
2877                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2878                         if (rc)
2879                                 return rc;
2880                 }
2881         }
2882
2883         if (!rc)
2884                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2885
2886         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2887
2888         return rc;
2889 }
2890
2891 static int
2892 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2893 {
2894         struct bnxt *bp = dev->data->dev_private;
2895         uint16_t vlan = bp->vlan;
2896         int rc;
2897
2898         rc = is_bnxt_in_error(bp);
2899         if (rc)
2900                 return rc;
2901
2902         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2903                 PMD_DRV_LOG(ERR,
2904                         "PVID cannot be modified for this function\n");
2905                 return -ENOTSUP;
2906         }
2907         bp->vlan = on ? pvid : 0;
2908
2909         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2910         if (rc)
2911                 bp->vlan = vlan;
2912         return rc;
2913 }
2914
2915 static int
2916 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2917 {
2918         struct bnxt *bp = dev->data->dev_private;
2919         int rc;
2920
2921         rc = is_bnxt_in_error(bp);
2922         if (rc)
2923                 return rc;
2924
2925         return bnxt_hwrm_port_led_cfg(bp, true);
2926 }
2927
2928 static int
2929 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2930 {
2931         struct bnxt *bp = dev->data->dev_private;
2932         int rc;
2933
2934         rc = is_bnxt_in_error(bp);
2935         if (rc)
2936                 return rc;
2937
2938         return bnxt_hwrm_port_led_cfg(bp, false);
2939 }
2940
2941 static uint32_t
2942 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2943 {
2944         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2945         struct bnxt_cp_ring_info *cpr;
2946         uint32_t desc = 0, raw_cons;
2947         struct bnxt_rx_queue *rxq;
2948         struct rx_pkt_cmpl *rxcmp;
2949         int rc;
2950
2951         rc = is_bnxt_in_error(bp);
2952         if (rc)
2953                 return rc;
2954
2955         rxq = dev->data->rx_queues[rx_queue_id];
2956         cpr = rxq->cp_ring;
2957         raw_cons = cpr->cp_raw_cons;
2958
2959         while (1) {
2960                 uint32_t agg_cnt, cons, cmpl_type;
2961
2962                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2963                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2964
2965                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
2966                         break;
2967
2968                 cmpl_type = CMP_TYPE(rxcmp);
2969
2970                 switch (cmpl_type) {
2971                 case CMPL_BASE_TYPE_RX_L2:
2972                 case CMPL_BASE_TYPE_RX_L2_V2:
2973                         agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
2974                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
2975                         desc++;
2976                         break;
2977
2978                 case CMPL_BASE_TYPE_RX_TPA_END:
2979                         if (BNXT_CHIP_P5(rxq->bp)) {
2980                                 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
2981
2982                                 p5_tpa_end = (void *)rxcmp;
2983                                 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
2984                         } else {
2985                                 struct rx_tpa_end_cmpl *tpa_end;
2986
2987                                 tpa_end = (void *)rxcmp;
2988                                 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
2989                         }
2990
2991                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
2992                         desc++;
2993                         break;
2994
2995                 default:
2996                         raw_cons += CMP_LEN(cmpl_type);
2997                 }
2998         }
2999
3000         return desc;
3001 }
3002
3003 static int
3004 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
3005 {
3006         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
3007         struct bnxt_rx_ring_info *rxr;
3008         struct bnxt_cp_ring_info *cpr;
3009         struct rte_mbuf *rx_buf;
3010         struct rx_pkt_cmpl *rxcmp;
3011         uint32_t cons, cp_cons;
3012         int rc;
3013
3014         if (!rxq)
3015                 return -EINVAL;
3016
3017         rc = is_bnxt_in_error(rxq->bp);
3018         if (rc)
3019                 return rc;
3020
3021         cpr = rxq->cp_ring;
3022         rxr = rxq->rx_ring;
3023
3024         if (offset >= rxq->nb_rx_desc)
3025                 return -EINVAL;
3026
3027         cons = RING_CMP(cpr->cp_ring_struct, offset);
3028         cp_cons = cpr->cp_raw_cons;
3029         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3030
3031         if (cons > cp_cons) {
3032                 if (CMPL_VALID(rxcmp, cpr->valid))
3033                         return RTE_ETH_RX_DESC_DONE;
3034         } else {
3035                 if (CMPL_VALID(rxcmp, !cpr->valid))
3036                         return RTE_ETH_RX_DESC_DONE;
3037         }
3038         rx_buf = rxr->rx_buf_ring[cons];
3039         if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf)
3040                 return RTE_ETH_RX_DESC_UNAVAIL;
3041
3042
3043         return RTE_ETH_RX_DESC_AVAIL;
3044 }
3045
3046 static int
3047 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
3048 {
3049         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
3050         struct bnxt_tx_ring_info *txr;
3051         struct bnxt_cp_ring_info *cpr;
3052         struct bnxt_sw_tx_bd *tx_buf;
3053         struct tx_pkt_cmpl *txcmp;
3054         uint32_t cons, cp_cons;
3055         int rc;
3056
3057         if (!txq)
3058                 return -EINVAL;
3059
3060         rc = is_bnxt_in_error(txq->bp);
3061         if (rc)
3062                 return rc;
3063
3064         cpr = txq->cp_ring;
3065         txr = txq->tx_ring;
3066
3067         if (offset >= txq->nb_tx_desc)
3068                 return -EINVAL;
3069
3070         cons = RING_CMP(cpr->cp_ring_struct, offset);
3071         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3072         cp_cons = cpr->cp_raw_cons;
3073
3074         if (cons > cp_cons) {
3075                 if (CMPL_VALID(txcmp, cpr->valid))
3076                         return RTE_ETH_TX_DESC_UNAVAIL;
3077         } else {
3078                 if (CMPL_VALID(txcmp, !cpr->valid))
3079                         return RTE_ETH_TX_DESC_UNAVAIL;
3080         }
3081         tx_buf = &txr->tx_buf_ring[cons];
3082         if (tx_buf->mbuf == NULL)
3083                 return RTE_ETH_TX_DESC_DONE;
3084
3085         return RTE_ETH_TX_DESC_FULL;
3086 }
3087
3088 int
3089 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3090                     enum rte_filter_type filter_type,
3091                     enum rte_filter_op filter_op, void *arg)
3092 {
3093         struct bnxt *bp = dev->data->dev_private;
3094         int ret = 0;
3095
3096         if (!bp)
3097                 return -EIO;
3098
3099         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3100                 struct bnxt_representor *vfr = dev->data->dev_private;
3101                 bp = vfr->parent_dev->data->dev_private;
3102                 /* parent is deleted while children are still valid */
3103                 if (!bp) {
3104                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n",
3105                                     dev->data->port_id,
3106                                     filter_type,
3107                                     filter_op);
3108                         return -EIO;
3109                 }
3110         }
3111
3112         ret = is_bnxt_in_error(bp);
3113         if (ret)
3114                 return ret;
3115
3116         switch (filter_type) {
3117         case RTE_ETH_FILTER_GENERIC:
3118                 if (filter_op != RTE_ETH_FILTER_GET)
3119                         return -EINVAL;
3120
3121                 /* PMD supports thread-safe flow operations.  rte_flow API
3122                  * functions can avoid mutex for multi-thread safety.
3123                  */
3124                 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3125
3126                 if (BNXT_TRUFLOW_EN(bp))
3127                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3128                 else
3129                         *(const void **)arg = &bnxt_flow_ops;
3130                 break;
3131         default:
3132                 PMD_DRV_LOG(ERR,
3133                         "Filter type (%d) not supported", filter_type);
3134                 ret = -EINVAL;
3135                 break;
3136         }
3137         return ret;
3138 }
3139
3140 static const uint32_t *
3141 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3142 {
3143         static const uint32_t ptypes[] = {
3144                 RTE_PTYPE_L2_ETHER_VLAN,
3145                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3146                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3147                 RTE_PTYPE_L4_ICMP,
3148                 RTE_PTYPE_L4_TCP,
3149                 RTE_PTYPE_L4_UDP,
3150                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3151                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3152                 RTE_PTYPE_INNER_L4_ICMP,
3153                 RTE_PTYPE_INNER_L4_TCP,
3154                 RTE_PTYPE_INNER_L4_UDP,
3155                 RTE_PTYPE_UNKNOWN
3156         };
3157
3158         if (!dev->rx_pkt_burst)
3159                 return NULL;
3160
3161         return ptypes;
3162 }
3163
3164 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3165                          int reg_win)
3166 {
3167         uint32_t reg_base = *reg_arr & 0xfffff000;
3168         uint32_t win_off;
3169         int i;
3170
3171         for (i = 0; i < count; i++) {
3172                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3173                         return -ERANGE;
3174         }
3175         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3176         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3177         return 0;
3178 }
3179
3180 static int bnxt_map_ptp_regs(struct bnxt *bp)
3181 {
3182         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3183         uint32_t *reg_arr;
3184         int rc, i;
3185
3186         reg_arr = ptp->rx_regs;
3187         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3188         if (rc)
3189                 return rc;
3190
3191         reg_arr = ptp->tx_regs;
3192         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3193         if (rc)
3194                 return rc;
3195
3196         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3197                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3198
3199         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3200                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3201
3202         return 0;
3203 }
3204
3205 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3206 {
3207         rte_write32(0, (uint8_t *)bp->bar0 +
3208                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3209         rte_write32(0, (uint8_t *)bp->bar0 +
3210                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3211 }
3212
3213 static uint64_t bnxt_cc_read(struct bnxt *bp)
3214 {
3215         uint64_t ns;
3216
3217         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3218                               BNXT_GRCPF_REG_SYNC_TIME));
3219         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3220                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3221         return ns;
3222 }
3223
3224 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3225 {
3226         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3227         uint32_t fifo;
3228
3229         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3230                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3231         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3232                 return -EAGAIN;
3233
3234         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3235                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3236         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3237                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3238         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3239                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3240
3241         return 0;
3242 }
3243
3244 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3245 {
3246         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3247         struct bnxt_pf_info *pf = bp->pf;
3248         uint16_t port_id;
3249         uint32_t fifo;
3250
3251         if (!ptp)
3252                 return -ENODEV;
3253
3254         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3255                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3256         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3257                 return -EAGAIN;
3258
3259         port_id = pf->port_id;
3260         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3261                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3262
3263         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3264                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3265         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3266 /*              bnxt_clr_rx_ts(bp);       TBD  */
3267                 return -EBUSY;
3268         }
3269
3270         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3271                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3272         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3273                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3274
3275         return 0;
3276 }
3277
3278 static int
3279 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3280 {
3281         uint64_t ns;
3282         struct bnxt *bp = dev->data->dev_private;
3283         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3284
3285         if (!ptp)
3286                 return 0;
3287
3288         ns = rte_timespec_to_ns(ts);
3289         /* Set the timecounters to a new value. */
3290         ptp->tc.nsec = ns;
3291
3292         return 0;
3293 }
3294
3295 static int
3296 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3297 {
3298         struct bnxt *bp = dev->data->dev_private;
3299         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3300         uint64_t ns, systime_cycles = 0;
3301         int rc = 0;
3302
3303         if (!ptp)
3304                 return 0;
3305
3306         if (BNXT_CHIP_P5(bp))
3307                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3308                                              &systime_cycles);
3309         else
3310                 systime_cycles = bnxt_cc_read(bp);
3311
3312         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3313         *ts = rte_ns_to_timespec(ns);
3314
3315         return rc;
3316 }
3317 static int
3318 bnxt_timesync_enable(struct rte_eth_dev *dev)
3319 {
3320         struct bnxt *bp = dev->data->dev_private;
3321         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3322         uint32_t shift = 0;
3323         int rc;
3324
3325         if (!ptp)
3326                 return 0;
3327
3328         ptp->rx_filter = 1;
3329         ptp->tx_tstamp_en = 1;
3330         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3331
3332         rc = bnxt_hwrm_ptp_cfg(bp);
3333         if (rc)
3334                 return rc;
3335
3336         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3337         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3338         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3339
3340         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3341         ptp->tc.cc_shift = shift;
3342         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3343
3344         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3345         ptp->rx_tstamp_tc.cc_shift = shift;
3346         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3347
3348         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3349         ptp->tx_tstamp_tc.cc_shift = shift;
3350         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3351
3352         if (!BNXT_CHIP_P5(bp))
3353                 bnxt_map_ptp_regs(bp);
3354
3355         return 0;
3356 }
3357
3358 static int
3359 bnxt_timesync_disable(struct rte_eth_dev *dev)
3360 {
3361         struct bnxt *bp = dev->data->dev_private;
3362         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3363
3364         if (!ptp)
3365                 return 0;
3366
3367         ptp->rx_filter = 0;
3368         ptp->tx_tstamp_en = 0;
3369         ptp->rxctl = 0;
3370
3371         bnxt_hwrm_ptp_cfg(bp);
3372
3373         if (!BNXT_CHIP_P5(bp))
3374                 bnxt_unmap_ptp_regs(bp);
3375
3376         return 0;
3377 }
3378
3379 static int
3380 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3381                                  struct timespec *timestamp,
3382                                  uint32_t flags __rte_unused)
3383 {
3384         struct bnxt *bp = dev->data->dev_private;
3385         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3386         uint64_t rx_tstamp_cycles = 0;
3387         uint64_t ns;
3388
3389         if (!ptp)
3390                 return 0;
3391
3392         if (BNXT_CHIP_P5(bp))
3393                 rx_tstamp_cycles = ptp->rx_timestamp;
3394         else
3395                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3396
3397         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3398         *timestamp = rte_ns_to_timespec(ns);
3399         return  0;
3400 }
3401
3402 static int
3403 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3404                                  struct timespec *timestamp)
3405 {
3406         struct bnxt *bp = dev->data->dev_private;
3407         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3408         uint64_t tx_tstamp_cycles = 0;
3409         uint64_t ns;
3410         int rc = 0;
3411
3412         if (!ptp)
3413                 return 0;
3414
3415         if (BNXT_CHIP_P5(bp))
3416                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3417                                              &tx_tstamp_cycles);
3418         else
3419                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3420
3421         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3422         *timestamp = rte_ns_to_timespec(ns);
3423
3424         return rc;
3425 }
3426
3427 static int
3428 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3429 {
3430         struct bnxt *bp = dev->data->dev_private;
3431         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3432
3433         if (!ptp)
3434                 return 0;
3435
3436         ptp->tc.nsec += delta;
3437
3438         return 0;
3439 }
3440
3441 static int
3442 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3443 {
3444         struct bnxt *bp = dev->data->dev_private;
3445         int rc;
3446         uint32_t dir_entries;
3447         uint32_t entry_length;
3448
3449         rc = is_bnxt_in_error(bp);
3450         if (rc)
3451                 return rc;
3452
3453         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3454                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3455                     bp->pdev->addr.devid, bp->pdev->addr.function);
3456
3457         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3458         if (rc != 0)
3459                 return rc;
3460
3461         return dir_entries * entry_length;
3462 }
3463
3464 static int
3465 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3466                 struct rte_dev_eeprom_info *in_eeprom)
3467 {
3468         struct bnxt *bp = dev->data->dev_private;
3469         uint32_t index;
3470         uint32_t offset;
3471         int rc;
3472
3473         rc = is_bnxt_in_error(bp);
3474         if (rc)
3475                 return rc;
3476
3477         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3478                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3479                     bp->pdev->addr.devid, bp->pdev->addr.function,
3480                     in_eeprom->offset, in_eeprom->length);
3481
3482         if (in_eeprom->offset == 0) /* special offset value to get directory */
3483                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3484                                                 in_eeprom->data);
3485
3486         index = in_eeprom->offset >> 24;
3487         offset = in_eeprom->offset & 0xffffff;
3488
3489         if (index != 0)
3490                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3491                                            in_eeprom->length, in_eeprom->data);
3492
3493         return 0;
3494 }
3495
3496 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3497 {
3498         switch (dir_type) {
3499         case BNX_DIR_TYPE_CHIMP_PATCH:
3500         case BNX_DIR_TYPE_BOOTCODE:
3501         case BNX_DIR_TYPE_BOOTCODE_2:
3502         case BNX_DIR_TYPE_APE_FW:
3503         case BNX_DIR_TYPE_APE_PATCH:
3504         case BNX_DIR_TYPE_KONG_FW:
3505         case BNX_DIR_TYPE_KONG_PATCH:
3506         case BNX_DIR_TYPE_BONO_FW:
3507         case BNX_DIR_TYPE_BONO_PATCH:
3508                 /* FALLTHROUGH */
3509                 return true;
3510         }
3511
3512         return false;
3513 }
3514
3515 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3516 {
3517         switch (dir_type) {
3518         case BNX_DIR_TYPE_AVS:
3519         case BNX_DIR_TYPE_EXP_ROM_MBA:
3520         case BNX_DIR_TYPE_PCIE:
3521         case BNX_DIR_TYPE_TSCF_UCODE:
3522         case BNX_DIR_TYPE_EXT_PHY:
3523         case BNX_DIR_TYPE_CCM:
3524         case BNX_DIR_TYPE_ISCSI_BOOT:
3525         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3526         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3527                 /* FALLTHROUGH */
3528                 return true;
3529         }
3530
3531         return false;
3532 }
3533
3534 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3535 {
3536         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3537                 bnxt_dir_type_is_other_exec_format(dir_type);
3538 }
3539
3540 static int
3541 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3542                 struct rte_dev_eeprom_info *in_eeprom)
3543 {
3544         struct bnxt *bp = dev->data->dev_private;
3545         uint8_t index, dir_op;
3546         uint16_t type, ext, ordinal, attr;
3547         int rc;
3548
3549         rc = is_bnxt_in_error(bp);
3550         if (rc)
3551                 return rc;
3552
3553         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3554                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3555                     bp->pdev->addr.devid, bp->pdev->addr.function,
3556                     in_eeprom->offset, in_eeprom->length);
3557
3558         if (!BNXT_PF(bp)) {
3559                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3560                 return -EINVAL;
3561         }
3562
3563         type = in_eeprom->magic >> 16;
3564
3565         if (type == 0xffff) { /* special value for directory operations */
3566                 index = in_eeprom->magic & 0xff;
3567                 dir_op = in_eeprom->magic >> 8;
3568                 if (index == 0)
3569                         return -EINVAL;
3570                 switch (dir_op) {
3571                 case 0x0e: /* erase */
3572                         if (in_eeprom->offset != ~in_eeprom->magic)
3573                                 return -EINVAL;
3574                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3575                 default:
3576                         return -EINVAL;
3577                 }
3578         }
3579
3580         /* Create or re-write an NVM item: */
3581         if (bnxt_dir_type_is_executable(type) == true)
3582                 return -EOPNOTSUPP;
3583         ext = in_eeprom->magic & 0xffff;
3584         ordinal = in_eeprom->offset >> 16;
3585         attr = in_eeprom->offset & 0xffff;
3586
3587         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3588                                      in_eeprom->data, in_eeprom->length);
3589 }
3590
3591 /*
3592  * Initialization
3593  */
3594
3595 static const struct eth_dev_ops bnxt_dev_ops = {
3596         .dev_infos_get = bnxt_dev_info_get_op,
3597         .dev_close = bnxt_dev_close_op,
3598         .dev_configure = bnxt_dev_configure_op,
3599         .dev_start = bnxt_dev_start_op,
3600         .dev_stop = bnxt_dev_stop_op,
3601         .dev_set_link_up = bnxt_dev_set_link_up_op,
3602         .dev_set_link_down = bnxt_dev_set_link_down_op,
3603         .stats_get = bnxt_stats_get_op,
3604         .stats_reset = bnxt_stats_reset_op,
3605         .rx_queue_setup = bnxt_rx_queue_setup_op,
3606         .rx_queue_release = bnxt_rx_queue_release_op,
3607         .tx_queue_setup = bnxt_tx_queue_setup_op,
3608         .tx_queue_release = bnxt_tx_queue_release_op,
3609         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3610         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3611         .reta_update = bnxt_reta_update_op,
3612         .reta_query = bnxt_reta_query_op,
3613         .rss_hash_update = bnxt_rss_hash_update_op,
3614         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3615         .link_update = bnxt_link_update_op,
3616         .promiscuous_enable = bnxt_promiscuous_enable_op,
3617         .promiscuous_disable = bnxt_promiscuous_disable_op,
3618         .allmulticast_enable = bnxt_allmulticast_enable_op,
3619         .allmulticast_disable = bnxt_allmulticast_disable_op,
3620         .mac_addr_add = bnxt_mac_addr_add_op,
3621         .mac_addr_remove = bnxt_mac_addr_remove_op,
3622         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3623         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3624         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3625         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3626         .vlan_filter_set = bnxt_vlan_filter_set_op,
3627         .vlan_offload_set = bnxt_vlan_offload_set_op,
3628         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3629         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3630         .mtu_set = bnxt_mtu_set_op,
3631         .mac_addr_set = bnxt_set_default_mac_addr_op,
3632         .xstats_get = bnxt_dev_xstats_get_op,
3633         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3634         .xstats_reset = bnxt_dev_xstats_reset_op,
3635         .fw_version_get = bnxt_fw_version_get,
3636         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3637         .rxq_info_get = bnxt_rxq_info_get_op,
3638         .txq_info_get = bnxt_txq_info_get_op,
3639         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
3640         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
3641         .dev_led_on = bnxt_dev_led_on_op,
3642         .dev_led_off = bnxt_dev_led_off_op,
3643         .rx_queue_start = bnxt_rx_queue_start,
3644         .rx_queue_stop = bnxt_rx_queue_stop,
3645         .tx_queue_start = bnxt_tx_queue_start,
3646         .tx_queue_stop = bnxt_tx_queue_stop,
3647         .filter_ctrl = bnxt_filter_ctrl_op,
3648         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3649         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3650         .get_eeprom           = bnxt_get_eeprom_op,
3651         .set_eeprom           = bnxt_set_eeprom_op,
3652         .timesync_enable      = bnxt_timesync_enable,
3653         .timesync_disable     = bnxt_timesync_disable,
3654         .timesync_read_time   = bnxt_timesync_read_time,
3655         .timesync_write_time   = bnxt_timesync_write_time,
3656         .timesync_adjust_time = bnxt_timesync_adjust_time,
3657         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3658         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3659 };
3660
3661 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3662 {
3663         uint32_t offset;
3664
3665         /* Only pre-map the reset GRC registers using window 3 */
3666         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3667                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3668
3669         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3670
3671         return offset;
3672 }
3673
3674 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3675 {
3676         struct bnxt_error_recovery_info *info = bp->recovery_info;
3677         uint32_t reg_base = 0xffffffff;
3678         int i;
3679
3680         /* Only pre-map the monitoring GRC registers using window 2 */
3681         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3682                 uint32_t reg = info->status_regs[i];
3683
3684                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3685                         continue;
3686
3687                 if (reg_base == 0xffffffff)
3688                         reg_base = reg & 0xfffff000;
3689                 if ((reg & 0xfffff000) != reg_base)
3690                         return -ERANGE;
3691
3692                 /* Use mask 0xffc as the Lower 2 bits indicates
3693                  * address space location
3694                  */
3695                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3696                                                 (reg & 0xffc);
3697         }
3698
3699         if (reg_base == 0xffffffff)
3700                 return 0;
3701
3702         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3703                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3704
3705         return 0;
3706 }
3707
3708 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3709 {
3710         struct bnxt_error_recovery_info *info = bp->recovery_info;
3711         uint32_t delay = info->delay_after_reset[index];
3712         uint32_t val = info->reset_reg_val[index];
3713         uint32_t reg = info->reset_reg[index];
3714         uint32_t type, offset;
3715
3716         type = BNXT_FW_STATUS_REG_TYPE(reg);
3717         offset = BNXT_FW_STATUS_REG_OFF(reg);
3718
3719         switch (type) {
3720         case BNXT_FW_STATUS_REG_TYPE_CFG:
3721                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3722                 break;
3723         case BNXT_FW_STATUS_REG_TYPE_GRC:
3724                 offset = bnxt_map_reset_regs(bp, offset);
3725                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3726                 break;
3727         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3728                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3729                 break;
3730         }
3731         /* wait on a specific interval of time until core reset is complete */
3732         if (delay)
3733                 rte_delay_ms(delay);
3734 }
3735
3736 static void bnxt_dev_cleanup(struct bnxt *bp)
3737 {
3738         bp->eth_dev->data->dev_link.link_status = 0;
3739         bp->link_info->link_up = 0;
3740         if (bp->eth_dev->data->dev_started)
3741                 bnxt_dev_stop(bp->eth_dev);
3742
3743         bnxt_uninit_resources(bp, true);
3744 }
3745
3746 static int
3747 bnxt_check_fw_reset_done(struct bnxt *bp)
3748 {
3749         int timeout = bp->fw_reset_max_msecs;
3750         uint16_t val = 0;
3751         int rc;
3752
3753         do {
3754                 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
3755                 if (rc < 0) {
3756                         PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
3757                         return rc;
3758                 }
3759                 if (val != 0xffff)
3760                         break;
3761                 rte_delay_ms(1);
3762         } while (timeout--);
3763
3764         if (val == 0xffff) {
3765                 PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n");
3766                 return -1;
3767         }
3768
3769         return 0;
3770 }
3771
3772 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3773 {
3774         struct rte_eth_dev *dev = bp->eth_dev;
3775         struct rte_vlan_filter_conf *vfc;
3776         int vidx, vbit, rc;
3777         uint16_t vlan_id;
3778
3779         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3780                 vfc = &dev->data->vlan_filter_conf;
3781                 vidx = vlan_id / 64;
3782                 vbit = vlan_id % 64;
3783
3784                 /* Each bit corresponds to a VLAN id */
3785                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3786                         rc = bnxt_add_vlan_filter(bp, vlan_id);
3787                         if (rc)
3788                                 return rc;
3789                 }
3790         }
3791
3792         return 0;
3793 }
3794
3795 static int bnxt_restore_mac_filters(struct bnxt *bp)
3796 {
3797         struct rte_eth_dev *dev = bp->eth_dev;
3798         struct rte_eth_dev_info dev_info;
3799         struct rte_ether_addr *addr;
3800         uint64_t pool_mask;
3801         uint32_t pool = 0;
3802         uint16_t i;
3803         int rc;
3804
3805         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3806                 return 0;
3807
3808         rc = bnxt_dev_info_get_op(dev, &dev_info);
3809         if (rc)
3810                 return rc;
3811
3812         /* replay MAC address configuration */
3813         for (i = 1; i < dev_info.max_mac_addrs; i++) {
3814                 addr = &dev->data->mac_addrs[i];
3815
3816                 /* skip zero address */
3817                 if (rte_is_zero_ether_addr(addr))
3818                         continue;
3819
3820                 pool = 0;
3821                 pool_mask = dev->data->mac_pool_sel[i];
3822
3823                 do {
3824                         if (pool_mask & 1ULL) {
3825                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3826                                 if (rc)
3827                                         return rc;
3828                         }
3829                         pool_mask >>= 1;
3830                         pool++;
3831                 } while (pool_mask);
3832         }
3833
3834         return 0;
3835 }
3836
3837 static int bnxt_restore_filters(struct bnxt *bp)
3838 {
3839         struct rte_eth_dev *dev = bp->eth_dev;
3840         int ret = 0;
3841
3842         if (dev->data->all_multicast) {
3843                 ret = bnxt_allmulticast_enable_op(dev);
3844                 if (ret)
3845                         return ret;
3846         }
3847         if (dev->data->promiscuous) {
3848                 ret = bnxt_promiscuous_enable_op(dev);
3849                 if (ret)
3850                         return ret;
3851         }
3852
3853         ret = bnxt_restore_mac_filters(bp);
3854         if (ret)
3855                 return ret;
3856
3857         ret = bnxt_restore_vlan_filters(bp);
3858         /* TODO restore other filters as well */
3859         return ret;
3860 }
3861
3862 static int bnxt_check_fw_ready(struct bnxt *bp)
3863 {
3864         int timeout = bp->fw_reset_max_msecs;
3865         int rc = 0;
3866
3867         do {
3868                 rc = bnxt_hwrm_poll_ver_get(bp);
3869                 if (rc == 0)
3870                         break;
3871                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3872                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3873         } while (rc && timeout > 0);
3874
3875         if (rc)
3876                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3877
3878         return rc;
3879 }
3880
3881 static void bnxt_dev_recover(void *arg)
3882 {
3883         struct bnxt *bp = arg;
3884         int rc = 0;
3885
3886         pthread_mutex_lock(&bp->err_recovery_lock);
3887
3888         if (!bp->fw_reset_min_msecs) {
3889                 rc = bnxt_check_fw_reset_done(bp);
3890                 if (rc)
3891                         goto err;
3892         }
3893
3894         /* Clear Error flag so that device re-init should happen */
3895         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3896
3897         rc = bnxt_check_fw_ready(bp);
3898         if (rc)
3899                 goto err;
3900
3901         rc = bnxt_init_resources(bp, true);
3902         if (rc) {
3903                 PMD_DRV_LOG(ERR,
3904                             "Failed to initialize resources after reset\n");
3905                 goto err;
3906         }
3907         /* clear reset flag as the device is initialized now */
3908         bp->flags &= ~BNXT_FLAG_FW_RESET;
3909
3910         rc = bnxt_dev_start_op(bp->eth_dev);
3911         if (rc) {
3912                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3913                 goto err_start;
3914         }
3915
3916         rc = bnxt_restore_filters(bp);
3917         if (rc)
3918                 goto err_start;
3919
3920         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3921         pthread_mutex_unlock(&bp->err_recovery_lock);
3922
3923         return;
3924 err_start:
3925         bnxt_dev_stop(bp->eth_dev);
3926 err:
3927         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3928         bnxt_uninit_resources(bp, false);
3929         pthread_mutex_unlock(&bp->err_recovery_lock);
3930         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3931 }
3932
3933 void bnxt_dev_reset_and_resume(void *arg)
3934 {
3935         struct bnxt *bp = arg;
3936         uint32_t us = US_PER_MS * bp->fw_reset_min_msecs;
3937         uint16_t val = 0;
3938         int rc;
3939
3940         bnxt_dev_cleanup(bp);
3941
3942         bnxt_wait_for_device_shutdown(bp);
3943
3944         /* During some fatal firmware error conditions, the PCI config space
3945          * register 0x2e which normally contains the subsystem ID will become
3946          * 0xffff. This register will revert back to the normal value after
3947          * the chip has completed core reset. If we detect this condition,
3948          * we can poll this config register immediately for the value to revert.
3949          */
3950         if (bp->flags & BNXT_FLAG_FATAL_ERROR) {
3951                 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
3952                 if (rc < 0) {
3953                         PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
3954                         return;
3955                 }
3956                 if (val == 0xffff) {
3957                         bp->fw_reset_min_msecs = 0;
3958                         us = 1;
3959                 }
3960         }
3961
3962         rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp);
3963         if (rc)
3964                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3965 }
3966
3967 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3968 {
3969         struct bnxt_error_recovery_info *info = bp->recovery_info;
3970         uint32_t reg = info->status_regs[index];
3971         uint32_t type, offset, val = 0;
3972
3973         type = BNXT_FW_STATUS_REG_TYPE(reg);
3974         offset = BNXT_FW_STATUS_REG_OFF(reg);
3975
3976         switch (type) {
3977         case BNXT_FW_STATUS_REG_TYPE_CFG:
3978                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3979                 break;
3980         case BNXT_FW_STATUS_REG_TYPE_GRC:
3981                 offset = info->mapped_status_regs[index];
3982                 /* FALLTHROUGH */
3983         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3984                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3985                                        offset));
3986                 break;
3987         }
3988
3989         return val;
3990 }
3991
3992 static int bnxt_fw_reset_all(struct bnxt *bp)
3993 {
3994         struct bnxt_error_recovery_info *info = bp->recovery_info;
3995         uint32_t i;
3996         int rc = 0;
3997
3998         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3999                 /* Reset through master function driver */
4000                 for (i = 0; i < info->reg_array_cnt; i++)
4001                         bnxt_write_fw_reset_reg(bp, i);
4002                 /* Wait for time specified by FW after triggering reset */
4003                 rte_delay_ms(info->master_func_wait_period_after_reset);
4004         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4005                 /* Reset with the help of Kong processor */
4006                 rc = bnxt_hwrm_fw_reset(bp);
4007                 if (rc)
4008                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4009         }
4010
4011         return rc;
4012 }
4013
4014 static void bnxt_fw_reset_cb(void *arg)
4015 {
4016         struct bnxt *bp = arg;
4017         struct bnxt_error_recovery_info *info = bp->recovery_info;
4018         int rc = 0;
4019
4020         /* Only Master function can do FW reset */
4021         if (bnxt_is_master_func(bp) &&
4022             bnxt_is_recovery_enabled(bp)) {
4023                 rc = bnxt_fw_reset_all(bp);
4024                 if (rc) {
4025                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4026                         return;
4027                 }
4028         }
4029
4030         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4031          * EXCEPTION_FATAL_ASYNC event to all the functions
4032          * (including MASTER FUNC). After receiving this Async, all the active
4033          * drivers should treat this case as FW initiated recovery
4034          */
4035         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4036                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4037                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4038
4039                 /* To recover from error */
4040                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4041                                   (void *)bp);
4042         }
4043 }
4044
4045 /* Driver should poll FW heartbeat, reset_counter with the frequency
4046  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4047  * When the driver detects heartbeat stop or change in reset_counter,
4048  * it has to trigger a reset to recover from the error condition.
4049  * A “master PF” is the function who will have the privilege to
4050  * initiate the chimp reset. The master PF will be elected by the
4051  * firmware and will be notified through async message.
4052  */
4053 static void bnxt_check_fw_health(void *arg)
4054 {
4055         struct bnxt *bp = arg;
4056         struct bnxt_error_recovery_info *info = bp->recovery_info;
4057         uint32_t val = 0, wait_msec;
4058
4059         if (!info || !bnxt_is_recovery_enabled(bp) ||
4060             is_bnxt_in_error(bp))
4061                 return;
4062
4063         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4064         if (val == info->last_heart_beat)
4065                 goto reset;
4066
4067         info->last_heart_beat = val;
4068
4069         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4070         if (val != info->last_reset_counter)
4071                 goto reset;
4072
4073         info->last_reset_counter = val;
4074
4075         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4076                           bnxt_check_fw_health, (void *)bp);
4077
4078         return;
4079 reset:
4080         /* Stop DMA to/from device */
4081         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4082         bp->flags |= BNXT_FLAG_FW_RESET;
4083
4084         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4085
4086         if (bnxt_is_master_func(bp))
4087                 wait_msec = info->master_func_wait_period;
4088         else
4089                 wait_msec = info->normal_func_wait_period;
4090
4091         rte_eal_alarm_set(US_PER_MS * wait_msec,
4092                           bnxt_fw_reset_cb, (void *)bp);
4093 }
4094
4095 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4096 {
4097         uint32_t polling_freq;
4098
4099         pthread_mutex_lock(&bp->health_check_lock);
4100
4101         if (!bnxt_is_recovery_enabled(bp))
4102                 goto done;
4103
4104         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4105                 goto done;
4106
4107         polling_freq = bp->recovery_info->driver_polling_freq;
4108
4109         rte_eal_alarm_set(US_PER_MS * polling_freq,
4110                           bnxt_check_fw_health, (void *)bp);
4111         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4112
4113 done:
4114         pthread_mutex_unlock(&bp->health_check_lock);
4115 }
4116
4117 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4118 {
4119         if (!bnxt_is_recovery_enabled(bp))
4120                 return;
4121
4122         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4123         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4124 }
4125
4126 static bool bnxt_vf_pciid(uint16_t device_id)
4127 {
4128         switch (device_id) {
4129         case BROADCOM_DEV_ID_57304_VF:
4130         case BROADCOM_DEV_ID_57406_VF:
4131         case BROADCOM_DEV_ID_5731X_VF:
4132         case BROADCOM_DEV_ID_5741X_VF:
4133         case BROADCOM_DEV_ID_57414_VF:
4134         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4135         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4136         case BROADCOM_DEV_ID_58802_VF:
4137         case BROADCOM_DEV_ID_57500_VF1:
4138         case BROADCOM_DEV_ID_57500_VF2:
4139         case BROADCOM_DEV_ID_58818_VF:
4140                 /* FALLTHROUGH */
4141                 return true;
4142         default:
4143                 return false;
4144         }
4145 }
4146
4147 /* Phase 5 device */
4148 static bool bnxt_p5_device(uint16_t device_id)
4149 {
4150         switch (device_id) {
4151         case BROADCOM_DEV_ID_57508:
4152         case BROADCOM_DEV_ID_57504:
4153         case BROADCOM_DEV_ID_57502:
4154         case BROADCOM_DEV_ID_57508_MF1:
4155         case BROADCOM_DEV_ID_57504_MF1:
4156         case BROADCOM_DEV_ID_57502_MF1:
4157         case BROADCOM_DEV_ID_57508_MF2:
4158         case BROADCOM_DEV_ID_57504_MF2:
4159         case BROADCOM_DEV_ID_57502_MF2:
4160         case BROADCOM_DEV_ID_57500_VF1:
4161         case BROADCOM_DEV_ID_57500_VF2:
4162         case BROADCOM_DEV_ID_58812:
4163         case BROADCOM_DEV_ID_58814:
4164         case BROADCOM_DEV_ID_58818:
4165         case BROADCOM_DEV_ID_58818_VF:
4166                 /* FALLTHROUGH */
4167                 return true;
4168         default:
4169                 return false;
4170         }
4171 }
4172
4173 bool bnxt_stratus_device(struct bnxt *bp)
4174 {
4175         uint16_t device_id = bp->pdev->id.device_id;
4176
4177         switch (device_id) {
4178         case BROADCOM_DEV_ID_STRATUS_NIC:
4179         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4180         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4181                 /* FALLTHROUGH */
4182                 return true;
4183         default:
4184                 return false;
4185         }
4186 }
4187
4188 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev)
4189 {
4190         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4191         struct bnxt *bp = eth_dev->data->dev_private;
4192
4193         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4194         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4195         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4196         if (!bp->bar0 || !bp->doorbell_base) {
4197                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4198                 return -ENODEV;
4199         }
4200
4201         bp->eth_dev = eth_dev;
4202         bp->pdev = pci_dev;
4203
4204         return 0;
4205 }
4206
4207 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4208                                   struct bnxt_ctx_pg_info *ctx_pg,
4209                                   uint32_t mem_size,
4210                                   const char *suffix,
4211                                   uint16_t idx)
4212 {
4213         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4214         const struct rte_memzone *mz = NULL;
4215         char mz_name[RTE_MEMZONE_NAMESIZE];
4216         rte_iova_t mz_phys_addr;
4217         uint64_t valid_bits = 0;
4218         uint32_t sz;
4219         int i;
4220
4221         if (!mem_size)
4222                 return 0;
4223
4224         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4225                          BNXT_PAGE_SIZE;
4226         rmem->page_size = BNXT_PAGE_SIZE;
4227         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4228         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4229         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4230
4231         valid_bits = PTU_PTE_VALID;
4232
4233         if (rmem->nr_pages > 1) {
4234                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4235                          "bnxt_ctx_pg_tbl%s_%x_%d",
4236                          suffix, idx, bp->eth_dev->data->port_id);
4237                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4238                 mz = rte_memzone_lookup(mz_name);
4239                 if (!mz) {
4240                         mz = rte_memzone_reserve_aligned(mz_name,
4241                                                 rmem->nr_pages * 8,
4242                                                 SOCKET_ID_ANY,
4243                                                 RTE_MEMZONE_2MB |
4244                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4245                                                 RTE_MEMZONE_IOVA_CONTIG,
4246                                                 BNXT_PAGE_SIZE);
4247                         if (mz == NULL)
4248                                 return -ENOMEM;
4249                 }
4250
4251                 memset(mz->addr, 0, mz->len);
4252                 mz_phys_addr = mz->iova;
4253
4254                 rmem->pg_tbl = mz->addr;
4255                 rmem->pg_tbl_map = mz_phys_addr;
4256                 rmem->pg_tbl_mz = mz;
4257         }
4258
4259         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4260                  suffix, idx, bp->eth_dev->data->port_id);
4261         mz = rte_memzone_lookup(mz_name);
4262         if (!mz) {
4263                 mz = rte_memzone_reserve_aligned(mz_name,
4264                                                  mem_size,
4265                                                  SOCKET_ID_ANY,
4266                                                  RTE_MEMZONE_1GB |
4267                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4268                                                  RTE_MEMZONE_IOVA_CONTIG,
4269                                                  BNXT_PAGE_SIZE);
4270                 if (mz == NULL)
4271                         return -ENOMEM;
4272         }
4273
4274         memset(mz->addr, 0, mz->len);
4275         mz_phys_addr = mz->iova;
4276
4277         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4278                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4279                 rmem->dma_arr[i] = mz_phys_addr + sz;
4280
4281                 if (rmem->nr_pages > 1) {
4282                         if (i == rmem->nr_pages - 2 &&
4283                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4284                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4285                         else if (i == rmem->nr_pages - 1 &&
4286                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4287                                 valid_bits |= PTU_PTE_LAST;
4288
4289                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4290                                                            valid_bits);
4291                 }
4292         }
4293
4294         rmem->mz = mz;
4295         if (rmem->vmem_size)
4296                 rmem->vmem = (void **)mz->addr;
4297         rmem->dma_arr[0] = mz_phys_addr;
4298         return 0;
4299 }
4300
4301 static void bnxt_free_ctx_mem(struct bnxt *bp)
4302 {
4303         int i;
4304
4305         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4306                 return;
4307
4308         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4309         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4310         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4311         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4312         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4313         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4314         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4315         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4316         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4317         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4318         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4319
4320         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4321                 if (bp->ctx->tqm_mem[i])
4322                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4323         }
4324
4325         rte_free(bp->ctx);
4326         bp->ctx = NULL;
4327 }
4328
4329 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4330
4331 #define min_t(type, x, y) ({                    \
4332         type __min1 = (x);                      \
4333         type __min2 = (y);                      \
4334         __min1 < __min2 ? __min1 : __min2; })
4335
4336 #define max_t(type, x, y) ({                    \
4337         type __max1 = (x);                      \
4338         type __max2 = (y);                      \
4339         __max1 > __max2 ? __max1 : __max2; })
4340
4341 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4342
4343 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4344 {
4345         struct bnxt_ctx_pg_info *ctx_pg;
4346         struct bnxt_ctx_mem_info *ctx;
4347         uint32_t mem_size, ena, entries;
4348         uint32_t entries_sp, min;
4349         int i, rc;
4350
4351         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4352         if (rc) {
4353                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4354                 return rc;
4355         }
4356         ctx = bp->ctx;
4357         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4358                 return 0;
4359
4360         ctx_pg = &ctx->qp_mem;
4361         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4362         if (ctx->qp_entry_size) {
4363                 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4364                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4365                 if (rc)
4366                         return rc;
4367         }
4368
4369         ctx_pg = &ctx->srq_mem;
4370         ctx_pg->entries = ctx->srq_max_l2_entries;
4371         if (ctx->srq_entry_size) {
4372                 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4373                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4374                 if (rc)
4375                         return rc;
4376         }
4377
4378         ctx_pg = &ctx->cq_mem;
4379         ctx_pg->entries = ctx->cq_max_l2_entries;
4380         if (ctx->cq_entry_size) {
4381                 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4382                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4383                 if (rc)
4384                         return rc;
4385         }
4386
4387         ctx_pg = &ctx->vnic_mem;
4388         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4389                 ctx->vnic_max_ring_table_entries;
4390         if (ctx->vnic_entry_size) {
4391                 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4392                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4393                 if (rc)
4394                         return rc;
4395         }
4396
4397         ctx_pg = &ctx->stat_mem;
4398         ctx_pg->entries = ctx->stat_max_entries;
4399         if (ctx->stat_entry_size) {
4400                 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4401                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4402                 if (rc)
4403                         return rc;
4404         }
4405
4406         min = ctx->tqm_min_entries_per_ring;
4407
4408         entries_sp = ctx->qp_max_l2_entries +
4409                      ctx->vnic_max_vnic_entries +
4410                      2 * ctx->qp_min_qp1_entries + min;
4411         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4412
4413         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4414         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4415         entries = clamp_t(uint32_t, entries, min,
4416                           ctx->tqm_max_entries_per_ring);
4417         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4418                 /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7.
4419                  * i > 8 is other ext rings.
4420                  */
4421                 ctx_pg = ctx->tqm_mem[i];
4422                 ctx_pg->entries = i ? entries : entries_sp;
4423                 if (ctx->tqm_entry_size) {
4424                         mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4425                         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size,
4426                                                     "tqm_mem", i);
4427                         if (rc)
4428                                 return rc;
4429                 }
4430                 if (i < BNXT_MAX_TQM_LEGACY_RINGS)
4431                         ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4432                 else
4433                         ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8;
4434         }
4435
4436         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4437         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4438         if (rc)
4439                 PMD_DRV_LOG(ERR,
4440                             "Failed to configure context mem: rc = %d\n", rc);
4441         else
4442                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4443
4444         return rc;
4445 }
4446
4447 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4448 {
4449         struct rte_pci_device *pci_dev = bp->pdev;
4450         char mz_name[RTE_MEMZONE_NAMESIZE];
4451         const struct rte_memzone *mz = NULL;
4452         uint32_t total_alloc_len;
4453         rte_iova_t mz_phys_addr;
4454
4455         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4456                 return 0;
4457
4458         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4459                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4460                  pci_dev->addr.bus, pci_dev->addr.devid,
4461                  pci_dev->addr.function, "rx_port_stats");
4462         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4463         mz = rte_memzone_lookup(mz_name);
4464         total_alloc_len =
4465                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4466                                        sizeof(struct rx_port_stats_ext) + 512);
4467         if (!mz) {
4468                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4469                                          SOCKET_ID_ANY,
4470                                          RTE_MEMZONE_2MB |
4471                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4472                                          RTE_MEMZONE_IOVA_CONTIG);
4473                 if (mz == NULL)
4474                         return -ENOMEM;
4475         }
4476         memset(mz->addr, 0, mz->len);
4477         mz_phys_addr = mz->iova;
4478
4479         bp->rx_mem_zone = (const void *)mz;
4480         bp->hw_rx_port_stats = mz->addr;
4481         bp->hw_rx_port_stats_map = mz_phys_addr;
4482
4483         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4484                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4485                  pci_dev->addr.bus, pci_dev->addr.devid,
4486                  pci_dev->addr.function, "tx_port_stats");
4487         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4488         mz = rte_memzone_lookup(mz_name);
4489         total_alloc_len =
4490                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4491                                        sizeof(struct tx_port_stats_ext) + 512);
4492         if (!mz) {
4493                 mz = rte_memzone_reserve(mz_name,
4494                                          total_alloc_len,
4495                                          SOCKET_ID_ANY,
4496                                          RTE_MEMZONE_2MB |
4497                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4498                                          RTE_MEMZONE_IOVA_CONTIG);
4499                 if (mz == NULL)
4500                         return -ENOMEM;
4501         }
4502         memset(mz->addr, 0, mz->len);
4503         mz_phys_addr = mz->iova;
4504
4505         bp->tx_mem_zone = (const void *)mz;
4506         bp->hw_tx_port_stats = mz->addr;
4507         bp->hw_tx_port_stats_map = mz_phys_addr;
4508         bp->flags |= BNXT_FLAG_PORT_STATS;
4509
4510         /* Display extended statistics if FW supports it */
4511         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4512             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4513             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4514                 return 0;
4515
4516         bp->hw_rx_port_stats_ext = (void *)
4517                 ((uint8_t *)bp->hw_rx_port_stats +
4518                  sizeof(struct rx_port_stats));
4519         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4520                 sizeof(struct rx_port_stats);
4521         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4522
4523         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4524             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4525                 bp->hw_tx_port_stats_ext = (void *)
4526                         ((uint8_t *)bp->hw_tx_port_stats +
4527                          sizeof(struct tx_port_stats));
4528                 bp->hw_tx_port_stats_ext_map =
4529                         bp->hw_tx_port_stats_map +
4530                         sizeof(struct tx_port_stats);
4531                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4532         }
4533
4534         return 0;
4535 }
4536
4537 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4538 {
4539         struct bnxt *bp = eth_dev->data->dev_private;
4540         int rc = 0;
4541
4542         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4543                                                RTE_ETHER_ADDR_LEN *
4544                                                bp->max_l2_ctx,
4545                                                0);
4546         if (eth_dev->data->mac_addrs == NULL) {
4547                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4548                 return -ENOMEM;
4549         }
4550
4551         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4552                 if (BNXT_PF(bp))
4553                         return -EINVAL;
4554
4555                 /* Generate a random MAC address, if none was assigned by PF */
4556                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4557                 bnxt_eth_hw_addr_random(bp->mac_addr);
4558                 PMD_DRV_LOG(INFO,
4559                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4560                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4561                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4562
4563                 rc = bnxt_hwrm_set_mac(bp);
4564                 if (rc)
4565                         return rc;
4566         }
4567
4568         /* Copy the permanent MAC from the FUNC_QCAPS response */
4569         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4570
4571         return rc;
4572 }
4573
4574 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4575 {
4576         int rc = 0;
4577
4578         /* MAC is already configured in FW */
4579         if (BNXT_HAS_DFLT_MAC_SET(bp))
4580                 return 0;
4581
4582         /* Restore the old MAC configured */
4583         rc = bnxt_hwrm_set_mac(bp);
4584         if (rc)
4585                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4586
4587         return rc;
4588 }
4589
4590 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4591 {
4592         if (!BNXT_PF(bp))
4593                 return;
4594
4595         memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
4596
4597         if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
4598                 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
4599         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
4600         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
4601         BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
4602         BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
4603 }
4604
4605 uint16_t
4606 bnxt_get_svif(uint16_t port_id, bool func_svif,
4607               enum bnxt_ulp_intf_type type)
4608 {
4609         struct rte_eth_dev *eth_dev;
4610         struct bnxt *bp;
4611
4612         eth_dev = &rte_eth_devices[port_id];
4613         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4614                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4615                 if (!vfr)
4616                         return 0;
4617
4618                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4619                         return vfr->svif;
4620
4621                 eth_dev = vfr->parent_dev;
4622         }
4623
4624         bp = eth_dev->data->dev_private;
4625
4626         return func_svif ? bp->func_svif : bp->port_svif;
4627 }
4628
4629 uint16_t
4630 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
4631 {
4632         struct rte_eth_dev *eth_dev;
4633         struct bnxt_vnic_info *vnic;
4634         struct bnxt *bp;
4635
4636         eth_dev = &rte_eth_devices[port];
4637         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4638                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4639                 if (!vfr)
4640                         return 0;
4641
4642                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4643                         return vfr->dflt_vnic_id;
4644
4645                 eth_dev = vfr->parent_dev;
4646         }
4647
4648         bp = eth_dev->data->dev_private;
4649
4650         vnic = BNXT_GET_DEFAULT_VNIC(bp);
4651
4652         return vnic->fw_vnic_id;
4653 }
4654
4655 uint16_t
4656 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
4657 {
4658         struct rte_eth_dev *eth_dev;
4659         struct bnxt *bp;
4660
4661         eth_dev = &rte_eth_devices[port];
4662         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4663                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4664                 if (!vfr)
4665                         return 0;
4666
4667                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4668                         return vfr->fw_fid;
4669
4670                 eth_dev = vfr->parent_dev;
4671         }
4672
4673         bp = eth_dev->data->dev_private;
4674
4675         return bp->fw_fid;
4676 }
4677
4678 enum bnxt_ulp_intf_type
4679 bnxt_get_interface_type(uint16_t port)
4680 {
4681         struct rte_eth_dev *eth_dev;
4682         struct bnxt *bp;
4683
4684         eth_dev = &rte_eth_devices[port];
4685         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
4686                 return BNXT_ULP_INTF_TYPE_VF_REP;
4687
4688         bp = eth_dev->data->dev_private;
4689         if (BNXT_PF(bp))
4690                 return BNXT_ULP_INTF_TYPE_PF;
4691         else if (BNXT_VF_IS_TRUSTED(bp))
4692                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
4693         else if (BNXT_VF(bp))
4694                 return BNXT_ULP_INTF_TYPE_VF;
4695
4696         return BNXT_ULP_INTF_TYPE_INVALID;
4697 }
4698
4699 uint16_t
4700 bnxt_get_phy_port_id(uint16_t port_id)
4701 {
4702         struct bnxt_representor *vfr;
4703         struct rte_eth_dev *eth_dev;
4704         struct bnxt *bp;
4705
4706         eth_dev = &rte_eth_devices[port_id];
4707         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4708                 vfr = eth_dev->data->dev_private;
4709                 if (!vfr)
4710                         return 0;
4711
4712                 eth_dev = vfr->parent_dev;
4713         }
4714
4715         bp = eth_dev->data->dev_private;
4716
4717         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
4718 }
4719
4720 uint16_t
4721 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
4722 {
4723         struct rte_eth_dev *eth_dev;
4724         struct bnxt *bp;
4725
4726         eth_dev = &rte_eth_devices[port_id];
4727         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4728                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4729                 if (!vfr)
4730                         return 0;
4731
4732                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4733                         return vfr->fw_fid - 1;
4734
4735                 eth_dev = vfr->parent_dev;
4736         }
4737
4738         bp = eth_dev->data->dev_private;
4739
4740         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
4741 }
4742
4743 uint16_t
4744 bnxt_get_vport(uint16_t port_id)
4745 {
4746         return (1 << bnxt_get_phy_port_id(port_id));
4747 }
4748
4749 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
4750 {
4751         struct bnxt_error_recovery_info *info = bp->recovery_info;
4752
4753         if (info) {
4754                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
4755                         memset(info, 0, sizeof(*info));
4756                 return;
4757         }
4758
4759         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4760                 return;
4761
4762         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4763                            sizeof(*info), 0);
4764         if (!info)
4765                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4766
4767         bp->recovery_info = info;
4768 }
4769
4770 static void bnxt_check_fw_status(struct bnxt *bp)
4771 {
4772         uint32_t fw_status;
4773
4774         if (!(bp->recovery_info &&
4775               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
4776                 return;
4777
4778         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
4779         if (fw_status != BNXT_FW_STATUS_HEALTHY)
4780                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
4781                             fw_status);
4782 }
4783
4784 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
4785 {
4786         struct bnxt_error_recovery_info *info = bp->recovery_info;
4787         uint32_t status_loc;
4788         uint32_t sig_ver;
4789
4790         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
4791                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4792         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4793                                    BNXT_GRCP_WINDOW_2_BASE +
4794                                    offsetof(struct hcomm_status,
4795                                             sig_ver)));
4796         /* If the signature is absent, then FW does not support this feature */
4797         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
4798             HCOMM_STATUS_SIGNATURE_VAL)
4799                 return 0;
4800
4801         if (!info) {
4802                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4803                                    sizeof(*info), 0);
4804                 if (!info)
4805                         return -ENOMEM;
4806                 bp->recovery_info = info;
4807         } else {
4808                 memset(info, 0, sizeof(*info));
4809         }
4810
4811         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4812                                       BNXT_GRCP_WINDOW_2_BASE +
4813                                       offsetof(struct hcomm_status,
4814                                                fw_status_loc)));
4815
4816         /* Only pre-map the FW health status GRC register */
4817         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
4818                 return 0;
4819
4820         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
4821         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
4822                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
4823
4824         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
4825                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4826
4827         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
4828
4829         return 0;
4830 }
4831
4832 /* This function gets the FW version along with the
4833  * capabilities(MAX and current) of the function, vnic,
4834  * error recovery, phy and other chip related info
4835  */
4836 static int bnxt_get_config(struct bnxt *bp)
4837 {
4838         uint16_t mtu;
4839         int rc = 0;
4840
4841         bp->fw_cap = 0;
4842
4843         rc = bnxt_map_hcomm_fw_status_reg(bp);
4844         if (rc)
4845                 return rc;
4846
4847         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
4848         if (rc) {
4849                 bnxt_check_fw_status(bp);
4850                 return rc;
4851         }
4852
4853         rc = bnxt_hwrm_func_reset(bp);
4854         if (rc)
4855                 return -EIO;
4856
4857         rc = bnxt_hwrm_vnic_qcaps(bp);
4858         if (rc)
4859                 return rc;
4860
4861         rc = bnxt_hwrm_queue_qportcfg(bp);
4862         if (rc)
4863                 return rc;
4864
4865         /* Get the MAX capabilities for this function.
4866          * This function also allocates context memory for TQM rings and
4867          * informs the firmware about this allocated backing store memory.
4868          */
4869         rc = bnxt_hwrm_func_qcaps(bp);
4870         if (rc)
4871                 return rc;
4872
4873         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4874         if (rc)
4875                 return rc;
4876
4877         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4878         if (rc)
4879                 return rc;
4880
4881         bnxt_hwrm_port_mac_qcfg(bp);
4882
4883         bnxt_hwrm_parent_pf_qcfg(bp);
4884
4885         bnxt_hwrm_port_phy_qcaps(bp);
4886
4887         bnxt_alloc_error_recovery_info(bp);
4888         /* Get the adapter error recovery support info */
4889         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4890         if (rc)
4891                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4892
4893         bnxt_hwrm_port_led_qcaps(bp);
4894
4895         return 0;
4896 }
4897
4898 static int
4899 bnxt_init_locks(struct bnxt *bp)
4900 {
4901         int err;
4902
4903         err = pthread_mutex_init(&bp->flow_lock, NULL);
4904         if (err) {
4905                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4906                 return err;
4907         }
4908
4909         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4910         if (err) {
4911                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4912                 return err;
4913         }
4914
4915         err = pthread_mutex_init(&bp->health_check_lock, NULL);
4916         if (err) {
4917                 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
4918                 return err;
4919         }
4920
4921         err = pthread_mutex_init(&bp->err_recovery_lock, NULL);
4922         if (err)
4923                 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n");
4924
4925         return err;
4926 }
4927
4928 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4929 {
4930         int rc = 0;
4931
4932         rc = bnxt_get_config(bp);
4933         if (rc)
4934                 return rc;
4935
4936         if (!reconfig_dev) {
4937                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4938                 if (rc)
4939                         return rc;
4940         } else {
4941                 rc = bnxt_restore_dflt_mac(bp);
4942                 if (rc)
4943                         return rc;
4944         }
4945
4946         bnxt_config_vf_req_fwd(bp);
4947
4948         rc = bnxt_hwrm_func_driver_register(bp);
4949         if (rc) {
4950                 PMD_DRV_LOG(ERR, "Failed to register driver");
4951                 return -EBUSY;
4952         }
4953
4954         if (BNXT_PF(bp)) {
4955                 if (bp->pdev->max_vfs) {
4956                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4957                         if (rc) {
4958                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4959                                 return rc;
4960                         }
4961                 } else {
4962                         rc = bnxt_hwrm_allocate_pf_only(bp);
4963                         if (rc) {
4964                                 PMD_DRV_LOG(ERR,
4965                                             "Failed to allocate PF resources");
4966                                 return rc;
4967                         }
4968                 }
4969         }
4970
4971         rc = bnxt_alloc_mem(bp, reconfig_dev);
4972         if (rc)
4973                 return rc;
4974
4975         rc = bnxt_setup_int(bp);
4976         if (rc)
4977                 return rc;
4978
4979         rc = bnxt_request_int(bp);
4980         if (rc)
4981                 return rc;
4982
4983         rc = bnxt_init_ctx_mem(bp);
4984         if (rc) {
4985                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
4986                 return rc;
4987         }
4988
4989         return 0;
4990 }
4991
4992 static int
4993 bnxt_parse_devarg_truflow(__rte_unused const char *key,
4994                           const char *value, void *opaque_arg)
4995 {
4996         struct bnxt *bp = opaque_arg;
4997         unsigned long truflow;
4998         char *end = NULL;
4999
5000         if (!value || !opaque_arg) {
5001                 PMD_DRV_LOG(ERR,
5002                             "Invalid parameter passed to truflow devargs.\n");
5003                 return -EINVAL;
5004         }
5005
5006         truflow = strtoul(value, &end, 10);
5007         if (end == NULL || *end != '\0' ||
5008             (truflow == ULONG_MAX && errno == ERANGE)) {
5009                 PMD_DRV_LOG(ERR,
5010                             "Invalid parameter passed to truflow devargs.\n");
5011                 return -EINVAL;
5012         }
5013
5014         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5015                 PMD_DRV_LOG(ERR,
5016                             "Invalid value passed to truflow devargs.\n");
5017                 return -EINVAL;
5018         }
5019
5020         if (truflow) {
5021                 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5022                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5023         } else {
5024                 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
5025                 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
5026         }
5027
5028         return 0;
5029 }
5030
5031 static int
5032 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5033                              const char *value, void *opaque_arg)
5034 {
5035         struct bnxt *bp = opaque_arg;
5036         unsigned long flow_xstat;
5037         char *end = NULL;
5038
5039         if (!value || !opaque_arg) {
5040                 PMD_DRV_LOG(ERR,
5041                             "Invalid parameter passed to flow_xstat devarg.\n");
5042                 return -EINVAL;
5043         }
5044
5045         flow_xstat = strtoul(value, &end, 10);
5046         if (end == NULL || *end != '\0' ||
5047             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5048                 PMD_DRV_LOG(ERR,
5049                             "Invalid parameter passed to flow_xstat devarg.\n");
5050                 return -EINVAL;
5051         }
5052
5053         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5054                 PMD_DRV_LOG(ERR,
5055                             "Invalid value passed to flow_xstat devarg.\n");
5056                 return -EINVAL;
5057         }
5058
5059         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5060         if (BNXT_FLOW_XSTATS_EN(bp))
5061                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5062
5063         return 0;
5064 }
5065
5066 static int
5067 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5068                                         const char *value, void *opaque_arg)
5069 {
5070         struct bnxt *bp = opaque_arg;
5071         unsigned long max_num_kflows;
5072         char *end = NULL;
5073
5074         if (!value || !opaque_arg) {
5075                 PMD_DRV_LOG(ERR,
5076                         "Invalid parameter passed to max_num_kflows devarg.\n");
5077                 return -EINVAL;
5078         }
5079
5080         max_num_kflows = strtoul(value, &end, 10);
5081         if (end == NULL || *end != '\0' ||
5082                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5083                 PMD_DRV_LOG(ERR,
5084                         "Invalid parameter passed to max_num_kflows devarg.\n");
5085                 return -EINVAL;
5086         }
5087
5088         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5089                 PMD_DRV_LOG(ERR,
5090                         "Invalid value passed to max_num_kflows devarg.\n");
5091                 return -EINVAL;
5092         }
5093
5094         bp->max_num_kflows = max_num_kflows;
5095         if (bp->max_num_kflows)
5096                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5097                                 max_num_kflows);
5098
5099         return 0;
5100 }
5101
5102 static int
5103 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5104                             const char *value, void *opaque_arg)
5105 {
5106         struct bnxt_representor *vfr_bp = opaque_arg;
5107         unsigned long rep_is_pf;
5108         char *end = NULL;
5109
5110         if (!value || !opaque_arg) {
5111                 PMD_DRV_LOG(ERR,
5112                             "Invalid parameter passed to rep_is_pf devargs.\n");
5113                 return -EINVAL;
5114         }
5115
5116         rep_is_pf = strtoul(value, &end, 10);
5117         if (end == NULL || *end != '\0' ||
5118             (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5119                 PMD_DRV_LOG(ERR,
5120                             "Invalid parameter passed to rep_is_pf devargs.\n");
5121                 return -EINVAL;
5122         }
5123
5124         if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5125                 PMD_DRV_LOG(ERR,
5126                             "Invalid value passed to rep_is_pf devargs.\n");
5127                 return -EINVAL;
5128         }
5129
5130         vfr_bp->flags |= rep_is_pf;
5131         if (BNXT_REP_PF(vfr_bp))
5132                 PMD_DRV_LOG(INFO, "PF representor\n");
5133         else
5134                 PMD_DRV_LOG(INFO, "VF representor\n");
5135
5136         return 0;
5137 }
5138
5139 static int
5140 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5141                                const char *value, void *opaque_arg)
5142 {
5143         struct bnxt_representor *vfr_bp = opaque_arg;
5144         unsigned long rep_based_pf;
5145         char *end = NULL;
5146
5147         if (!value || !opaque_arg) {
5148                 PMD_DRV_LOG(ERR,
5149                             "Invalid parameter passed to rep_based_pf "
5150                             "devargs.\n");
5151                 return -EINVAL;
5152         }
5153
5154         rep_based_pf = strtoul(value, &end, 10);
5155         if (end == NULL || *end != '\0' ||
5156             (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5157                 PMD_DRV_LOG(ERR,
5158                             "Invalid parameter passed to rep_based_pf "
5159                             "devargs.\n");
5160                 return -EINVAL;
5161         }
5162
5163         if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5164                 PMD_DRV_LOG(ERR,
5165                             "Invalid value passed to rep_based_pf devargs.\n");
5166                 return -EINVAL;
5167         }
5168
5169         vfr_bp->rep_based_pf = rep_based_pf;
5170         vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
5171
5172         PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5173
5174         return 0;
5175 }
5176
5177 static int
5178 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5179                             const char *value, void *opaque_arg)
5180 {
5181         struct bnxt_representor *vfr_bp = opaque_arg;
5182         unsigned long rep_q_r2f;
5183         char *end = NULL;
5184
5185         if (!value || !opaque_arg) {
5186                 PMD_DRV_LOG(ERR,
5187                             "Invalid parameter passed to rep_q_r2f "
5188                             "devargs.\n");
5189                 return -EINVAL;
5190         }
5191
5192         rep_q_r2f = strtoul(value, &end, 10);
5193         if (end == NULL || *end != '\0' ||
5194             (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5195                 PMD_DRV_LOG(ERR,
5196                             "Invalid parameter passed to rep_q_r2f "
5197                             "devargs.\n");
5198                 return -EINVAL;
5199         }
5200
5201         if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5202                 PMD_DRV_LOG(ERR,
5203                             "Invalid value passed to rep_q_r2f devargs.\n");
5204                 return -EINVAL;
5205         }
5206
5207         vfr_bp->rep_q_r2f = rep_q_r2f;
5208         vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5209         PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5210
5211         return 0;
5212 }
5213
5214 static int
5215 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5216                             const char *value, void *opaque_arg)
5217 {
5218         struct bnxt_representor *vfr_bp = opaque_arg;
5219         unsigned long rep_q_f2r;
5220         char *end = NULL;
5221
5222         if (!value || !opaque_arg) {
5223                 PMD_DRV_LOG(ERR,
5224                             "Invalid parameter passed to rep_q_f2r "
5225                             "devargs.\n");
5226                 return -EINVAL;
5227         }
5228
5229         rep_q_f2r = strtoul(value, &end, 10);
5230         if (end == NULL || *end != '\0' ||
5231             (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5232                 PMD_DRV_LOG(ERR,
5233                             "Invalid parameter passed to rep_q_f2r "
5234                             "devargs.\n");
5235                 return -EINVAL;
5236         }
5237
5238         if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5239                 PMD_DRV_LOG(ERR,
5240                             "Invalid value passed to rep_q_f2r devargs.\n");
5241                 return -EINVAL;
5242         }
5243
5244         vfr_bp->rep_q_f2r = rep_q_f2r;
5245         vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5246         PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5247
5248         return 0;
5249 }
5250
5251 static int
5252 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5253                              const char *value, void *opaque_arg)
5254 {
5255         struct bnxt_representor *vfr_bp = opaque_arg;
5256         unsigned long rep_fc_r2f;
5257         char *end = NULL;
5258
5259         if (!value || !opaque_arg) {
5260                 PMD_DRV_LOG(ERR,
5261                             "Invalid parameter passed to rep_fc_r2f "
5262                             "devargs.\n");
5263                 return -EINVAL;
5264         }
5265
5266         rep_fc_r2f = strtoul(value, &end, 10);
5267         if (end == NULL || *end != '\0' ||
5268             (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5269                 PMD_DRV_LOG(ERR,
5270                             "Invalid parameter passed to rep_fc_r2f "
5271                             "devargs.\n");
5272                 return -EINVAL;
5273         }
5274
5275         if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5276                 PMD_DRV_LOG(ERR,
5277                             "Invalid value passed to rep_fc_r2f devargs.\n");
5278                 return -EINVAL;
5279         }
5280
5281         vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5282         vfr_bp->rep_fc_r2f = rep_fc_r2f;
5283         PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5284
5285         return 0;
5286 }
5287
5288 static int
5289 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5290                              const char *value, void *opaque_arg)
5291 {
5292         struct bnxt_representor *vfr_bp = opaque_arg;
5293         unsigned long rep_fc_f2r;
5294         char *end = NULL;
5295
5296         if (!value || !opaque_arg) {
5297                 PMD_DRV_LOG(ERR,
5298                             "Invalid parameter passed to rep_fc_f2r "
5299                             "devargs.\n");
5300                 return -EINVAL;
5301         }
5302
5303         rep_fc_f2r = strtoul(value, &end, 10);
5304         if (end == NULL || *end != '\0' ||
5305             (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5306                 PMD_DRV_LOG(ERR,
5307                             "Invalid parameter passed to rep_fc_f2r "
5308                             "devargs.\n");
5309                 return -EINVAL;
5310         }
5311
5312         if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5313                 PMD_DRV_LOG(ERR,
5314                             "Invalid value passed to rep_fc_f2r devargs.\n");
5315                 return -EINVAL;
5316         }
5317
5318         vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5319         vfr_bp->rep_fc_f2r = rep_fc_f2r;
5320         PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5321
5322         return 0;
5323 }
5324
5325 static void
5326 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5327 {
5328         struct rte_kvargs *kvlist;
5329
5330         if (devargs == NULL)
5331                 return;
5332
5333         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5334         if (kvlist == NULL)
5335                 return;
5336
5337         /*
5338          * Handler for "truflow" devarg.
5339          * Invoked as for ex: "-a 0000:00:0d.0,host-based-truflow=1"
5340          */
5341         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5342                            bnxt_parse_devarg_truflow, bp);
5343
5344         /*
5345          * Handler for "flow_xstat" devarg.
5346          * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5347          */
5348         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5349                            bnxt_parse_devarg_flow_xstat, bp);
5350
5351         /*
5352          * Handler for "max_num_kflows" devarg.
5353          * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5354          */
5355         rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5356                            bnxt_parse_devarg_max_num_kflows, bp);
5357
5358         rte_kvargs_free(kvlist);
5359 }
5360
5361 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5362 {
5363         int rc = 0;
5364
5365         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5366                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5367                 if (rc)
5368                         PMD_DRV_LOG(ERR,
5369                                     "Failed to alloc switch domain: %d\n", rc);
5370                 else
5371                         PMD_DRV_LOG(INFO,
5372                                     "Switch domain allocated %d\n",
5373                                     bp->switch_domain_id);
5374         }
5375
5376         return rc;
5377 }
5378
5379 /* Allocate and initialize various fields in bnxt struct that
5380  * need to be allocated/destroyed only once in the lifetime of the driver
5381  */
5382 static int bnxt_drv_init(struct rte_eth_dev *eth_dev)
5383 {
5384         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5385         struct bnxt *bp = eth_dev->data->dev_private;
5386         int rc = 0;
5387
5388         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5389
5390         if (bnxt_vf_pciid(pci_dev->id.device_id))
5391                 bp->flags |= BNXT_FLAG_VF;
5392
5393         if (bnxt_p5_device(pci_dev->id.device_id))
5394                 bp->flags |= BNXT_FLAG_CHIP_P5;
5395
5396         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5397             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5398             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5399             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5400                 bp->flags |= BNXT_FLAG_STINGRAY;
5401
5402         if (BNXT_TRUFLOW_EN(bp)) {
5403                 /* extra mbuf field is required to store CFA code from mark */
5404                 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5405                         .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5406                         .size = sizeof(bnxt_cfa_code_dynfield_t),
5407                         .align = __alignof__(bnxt_cfa_code_dynfield_t),
5408                 };
5409                 bnxt_cfa_code_dynfield_offset =
5410                         rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5411                 if (bnxt_cfa_code_dynfield_offset < 0) {
5412                         PMD_DRV_LOG(ERR,
5413                             "Failed to register mbuf field for TruFlow mark\n");
5414                         return -rte_errno;
5415                 }
5416         }
5417
5418         rc = bnxt_map_pci_bars(eth_dev);
5419         if (rc) {
5420                 PMD_DRV_LOG(ERR,
5421                             "Failed to initialize board rc: %x\n", rc);
5422                 return rc;
5423         }
5424
5425         rc = bnxt_alloc_pf_info(bp);
5426         if (rc)
5427                 return rc;
5428
5429         rc = bnxt_alloc_link_info(bp);
5430         if (rc)
5431                 return rc;
5432
5433         rc = bnxt_alloc_parent_info(bp);
5434         if (rc)
5435                 return rc;
5436
5437         rc = bnxt_alloc_hwrm_resources(bp);
5438         if (rc) {
5439                 PMD_DRV_LOG(ERR,
5440                             "Failed to allocate hwrm resource rc: %x\n", rc);
5441                 return rc;
5442         }
5443         rc = bnxt_alloc_leds_info(bp);
5444         if (rc)
5445                 return rc;
5446
5447         rc = bnxt_alloc_cos_queues(bp);
5448         if (rc)
5449                 return rc;
5450
5451         rc = bnxt_init_locks(bp);
5452         if (rc)
5453                 return rc;
5454
5455         rc = bnxt_alloc_switch_domain(bp);
5456         if (rc)
5457                 return rc;
5458
5459         return rc;
5460 }
5461
5462 static int
5463 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5464 {
5465         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5466         static int version_printed;
5467         struct bnxt *bp;
5468         int rc;
5469
5470         if (version_printed++ == 0)
5471                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5472
5473         eth_dev->dev_ops = &bnxt_dev_ops;
5474         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5475         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5476         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5477         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5478         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5479
5480         /*
5481          * For secondary processes, we don't initialise any further
5482          * as primary has already done this work.
5483          */
5484         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5485                 return 0;
5486
5487         rte_eth_copy_pci_info(eth_dev, pci_dev);
5488         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
5489
5490         bp = eth_dev->data->dev_private;
5491
5492         /* Parse dev arguments passed on when starting the DPDK application. */
5493         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5494
5495         rc = bnxt_drv_init(eth_dev);
5496         if (rc)
5497                 goto error_free;
5498
5499         rc = bnxt_init_resources(bp, false);
5500         if (rc)
5501                 goto error_free;
5502
5503         rc = bnxt_alloc_stats_mem(bp);
5504         if (rc)
5505                 goto error_free;
5506
5507         PMD_DRV_LOG(INFO,
5508                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5509                     pci_dev->mem_resource[0].phys_addr,
5510                     pci_dev->mem_resource[0].addr);
5511
5512         return 0;
5513
5514 error_free:
5515         bnxt_dev_uninit(eth_dev);
5516         return rc;
5517 }
5518
5519
5520 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5521 {
5522         if (!ctx)
5523                 return;
5524
5525         if (ctx->va)
5526                 rte_free(ctx->va);
5527
5528         ctx->va = NULL;
5529         ctx->dma = RTE_BAD_IOVA;
5530         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5531 }
5532
5533 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5534 {
5535         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5536                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5537                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
5538                                   bp->flow_stat->max_fc,
5539                                   false);
5540
5541         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5542                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5543                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
5544                                   bp->flow_stat->max_fc,
5545                                   false);
5546
5547         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5548                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5549         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5550
5551         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5552                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5553         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5554
5555         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5556                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5557         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5558
5559         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5560                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5561         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5562 }
5563
5564 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5565 {
5566         bnxt_unregister_fc_ctx_mem(bp);
5567
5568         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5569         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5570         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5571         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5572 }
5573
5574 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5575 {
5576         if (BNXT_FLOW_XSTATS_EN(bp))
5577                 bnxt_uninit_fc_ctx_mem(bp);
5578 }
5579
5580 static void
5581 bnxt_free_error_recovery_info(struct bnxt *bp)
5582 {
5583         rte_free(bp->recovery_info);
5584         bp->recovery_info = NULL;
5585         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5586 }
5587
5588 static int
5589 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5590 {
5591         int rc;
5592
5593         bnxt_free_int(bp);
5594         bnxt_free_mem(bp, reconfig_dev);
5595
5596         bnxt_hwrm_func_buf_unrgtr(bp);
5597         rte_free(bp->pf->vf_req_buf);
5598
5599         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5600         bp->flags &= ~BNXT_FLAG_REGISTERED;
5601         bnxt_free_ctx_mem(bp);
5602         if (!reconfig_dev) {
5603                 bnxt_free_hwrm_resources(bp);
5604                 bnxt_free_error_recovery_info(bp);
5605         }
5606
5607         bnxt_uninit_ctx_mem(bp);
5608
5609         bnxt_free_flow_stats_info(bp);
5610         bnxt_free_rep_info(bp);
5611         rte_free(bp->ptp_cfg);
5612         bp->ptp_cfg = NULL;
5613         return rc;
5614 }
5615
5616 static int
5617 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5618 {
5619         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5620                 return -EPERM;
5621
5622         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5623
5624         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5625                 bnxt_dev_close_op(eth_dev);
5626
5627         return 0;
5628 }
5629
5630 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5631 {
5632         struct bnxt *bp = eth_dev->data->dev_private;
5633         struct rte_eth_dev *vf_rep_eth_dev;
5634         int ret = 0, i;
5635
5636         if (!bp)
5637                 return -EINVAL;
5638
5639         for (i = 0; i < bp->num_reps; i++) {
5640                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5641                 if (!vf_rep_eth_dev)
5642                         continue;
5643                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
5644                             vf_rep_eth_dev->data->port_id);
5645                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
5646         }
5647         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
5648                     eth_dev->data->port_id);
5649         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5650
5651         return ret;
5652 }
5653
5654 static void bnxt_free_rep_info(struct bnxt *bp)
5655 {
5656         rte_free(bp->rep_info);
5657         bp->rep_info = NULL;
5658         rte_free(bp->cfa_code_map);
5659         bp->cfa_code_map = NULL;
5660 }
5661
5662 static int bnxt_init_rep_info(struct bnxt *bp)
5663 {
5664         int i = 0, rc;
5665
5666         if (bp->rep_info)
5667                 return 0;
5668
5669         bp->rep_info = rte_zmalloc("bnxt_rep_info",
5670                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5671                                    0);
5672         if (!bp->rep_info) {
5673                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5674                 return -ENOMEM;
5675         }
5676         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5677                                        sizeof(*bp->cfa_code_map) *
5678                                        BNXT_MAX_CFA_CODE, 0);
5679         if (!bp->cfa_code_map) {
5680                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5681                 bnxt_free_rep_info(bp);
5682                 return -ENOMEM;
5683         }
5684
5685         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5686                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5687
5688         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5689         if (rc) {
5690                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5691                 bnxt_free_rep_info(bp);
5692                 return rc;
5693         }
5694
5695         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
5696         if (rc) {
5697                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
5698                 bnxt_free_rep_info(bp);
5699                 return rc;
5700         }
5701
5702         return rc;
5703 }
5704
5705 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5706                                struct rte_eth_devargs *eth_da,
5707                                struct rte_eth_dev *backing_eth_dev,
5708                                const char *dev_args)
5709 {
5710         struct rte_eth_dev *vf_rep_eth_dev;
5711         char name[RTE_ETH_NAME_MAX_LEN];
5712         struct bnxt *backing_bp;
5713         uint16_t num_rep;
5714         int i, ret = 0;
5715         struct rte_kvargs *kvlist = NULL;
5716
5717         num_rep = eth_da->nb_representor_ports;
5718         if (num_rep > BNXT_MAX_VF_REPS) {
5719                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5720                             num_rep, BNXT_MAX_VF_REPS);
5721                 return -EINVAL;
5722         }
5723
5724         if (num_rep >= RTE_MAX_ETHPORTS) {
5725                 PMD_DRV_LOG(ERR,
5726                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
5727                             num_rep, RTE_MAX_ETHPORTS);
5728                 return -EINVAL;
5729         }
5730
5731         backing_bp = backing_eth_dev->data->dev_private;
5732
5733         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
5734                 PMD_DRV_LOG(ERR,
5735                             "Not a PF or trusted VF. No Representor support\n");
5736                 /* Returning an error is not an option.
5737                  * Applications are not handling this correctly
5738                  */
5739                 return 0;
5740         }
5741
5742         if (bnxt_init_rep_info(backing_bp))
5743                 return 0;
5744
5745         for (i = 0; i < num_rep; i++) {
5746                 struct bnxt_representor representor = {
5747                         .vf_id = eth_da->representor_ports[i],
5748                         .switch_domain_id = backing_bp->switch_domain_id,
5749                         .parent_dev = backing_eth_dev
5750                 };
5751
5752                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
5753                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
5754                                     representor.vf_id, BNXT_MAX_VF_REPS);
5755                         continue;
5756                 }
5757
5758                 /* representor port net_bdf_port */
5759                 snprintf(name, sizeof(name), "net_%s_representor_%d",
5760                          pci_dev->device.name, eth_da->representor_ports[i]);
5761
5762                 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
5763                 if (kvlist) {
5764                         /*
5765                          * Handler for "rep_is_pf" devarg.
5766                          * Invoked as for ex: "-a 000:00:0d.0,
5767                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5768                          */
5769                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
5770                                                  bnxt_parse_devarg_rep_is_pf,
5771                                                  (void *)&representor);
5772                         if (ret) {
5773                                 ret = -EINVAL;
5774                                 goto err;
5775                         }
5776                         /*
5777                          * Handler for "rep_based_pf" devarg.
5778                          * Invoked as for ex: "-a 000:00:0d.0,
5779                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5780                          */
5781                         ret = rte_kvargs_process(kvlist,
5782                                                  BNXT_DEVARG_REP_BASED_PF,
5783                                                  bnxt_parse_devarg_rep_based_pf,
5784                                                  (void *)&representor);
5785                         if (ret) {
5786                                 ret = -EINVAL;
5787                                 goto err;
5788                         }
5789                         /*
5790                          * Handler for "rep_based_pf" devarg.
5791                          * Invoked as for ex: "-a 000:00:0d.0,
5792                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5793                          */
5794                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
5795                                                  bnxt_parse_devarg_rep_q_r2f,
5796                                                  (void *)&representor);
5797                         if (ret) {
5798                                 ret = -EINVAL;
5799                                 goto err;
5800                         }
5801                         /*
5802                          * Handler for "rep_based_pf" devarg.
5803                          * Invoked as for ex: "-a 000:00:0d.0,
5804                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5805                          */
5806                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
5807                                                  bnxt_parse_devarg_rep_q_f2r,
5808                                                  (void *)&representor);
5809                         if (ret) {
5810                                 ret = -EINVAL;
5811                                 goto err;
5812                         }
5813                         /*
5814                          * Handler for "rep_based_pf" devarg.
5815                          * Invoked as for ex: "-a 000:00:0d.0,
5816                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5817                          */
5818                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
5819                                                  bnxt_parse_devarg_rep_fc_r2f,
5820                                                  (void *)&representor);
5821                         if (ret) {
5822                                 ret = -EINVAL;
5823                                 goto err;
5824                         }
5825                         /*
5826                          * Handler for "rep_based_pf" devarg.
5827                          * Invoked as for ex: "-a 000:00:0d.0,
5828                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5829                          */
5830                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
5831                                                  bnxt_parse_devarg_rep_fc_f2r,
5832                                                  (void *)&representor);
5833                         if (ret) {
5834                                 ret = -EINVAL;
5835                                 goto err;
5836                         }
5837                 }
5838
5839                 ret = rte_eth_dev_create(&pci_dev->device, name,
5840                                          sizeof(struct bnxt_representor),
5841                                          NULL, NULL,
5842                                          bnxt_representor_init,
5843                                          &representor);
5844                 if (ret) {
5845                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
5846                                     "representor %s.", name);
5847                         goto err;
5848                 }
5849
5850                 vf_rep_eth_dev = rte_eth_dev_allocated(name);
5851                 if (!vf_rep_eth_dev) {
5852                         PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
5853                                     " for VF-Rep: %s.", name);
5854                         ret = -ENODEV;
5855                         goto err;
5856                 }
5857
5858                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
5859                             backing_eth_dev->data->port_id);
5860                 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
5861                                                          vf_rep_eth_dev;
5862                 backing_bp->num_reps++;
5863
5864         }
5865
5866         rte_kvargs_free(kvlist);
5867         return 0;
5868
5869 err:
5870         /* If num_rep > 1, then rollback already created
5871          * ports, since we'll be failing the probe anyway
5872          */
5873         if (num_rep > 1)
5874                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
5875         rte_errno = -ret;
5876         rte_kvargs_free(kvlist);
5877
5878         return ret;
5879 }
5880
5881 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5882                           struct rte_pci_device *pci_dev)
5883 {
5884         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
5885         struct rte_eth_dev *backing_eth_dev;
5886         uint16_t num_rep;
5887         int ret = 0;
5888
5889         if (pci_dev->device.devargs) {
5890                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
5891                                             &eth_da);
5892                 if (ret)
5893                         return ret;
5894         }
5895
5896         num_rep = eth_da.nb_representor_ports;
5897         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
5898                     num_rep);
5899
5900         /* We could come here after first level of probe is already invoked
5901          * as part of an application bringup(OVS-DPDK vswitchd), so first check
5902          * for already allocated eth_dev for the backing device (PF/Trusted VF)
5903          */
5904         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5905         if (backing_eth_dev == NULL) {
5906                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
5907                                          sizeof(struct bnxt),
5908                                          eth_dev_pci_specific_init, pci_dev,
5909                                          bnxt_dev_init, NULL);
5910
5911                 if (ret || !num_rep)
5912                         return ret;
5913
5914                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5915         }
5916         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
5917                     backing_eth_dev->data->port_id);
5918
5919         if (!num_rep)
5920                 return ret;
5921
5922         /* probe representor ports now */
5923         ret = bnxt_rep_port_probe(pci_dev, &eth_da, backing_eth_dev,
5924                                   pci_dev->device.devargs->args);
5925
5926         return ret;
5927 }
5928
5929 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5930 {
5931         struct rte_eth_dev *eth_dev;
5932
5933         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5934         if (!eth_dev)
5935                 return 0; /* Invoked typically only by OVS-DPDK, by the
5936                            * time it comes here the eth_dev is already
5937                            * deleted by rte_eth_dev_close(), so returning
5938                            * +ve value will at least help in proper cleanup
5939                            */
5940
5941         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
5942         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
5943                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
5944                         return rte_eth_dev_destroy(eth_dev,
5945                                                    bnxt_representor_uninit);
5946                 else
5947                         return rte_eth_dev_destroy(eth_dev,
5948                                                    bnxt_dev_uninit);
5949         } else {
5950                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5951         }
5952 }
5953
5954 static struct rte_pci_driver bnxt_rte_pmd = {
5955         .id_table = bnxt_pci_id_map,
5956         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
5957                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
5958                                                   * and OVS-DPDK
5959                                                   */
5960         .probe = bnxt_pci_probe,
5961         .remove = bnxt_pci_remove,
5962 };
5963
5964 static bool
5965 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5966 {
5967         if (strcmp(dev->device->driver->name, drv->driver.name))
5968                 return false;
5969
5970         return true;
5971 }
5972
5973 bool is_bnxt_supported(struct rte_eth_dev *dev)
5974 {
5975         return is_device_supported(dev, &bnxt_rte_pmd);
5976 }
5977
5978 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
5979 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5980 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5981 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");