1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
18 #include "bnxt_filter.h"
19 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_stats.h"
27 #include "bnxt_vnic.h"
28 #include "hsi_struct_def_dpdk.h"
29 #include "bnxt_nvm_defs.h"
30 #include "bnxt_util.h"
32 #define DRV_MODULE_NAME "bnxt"
33 static const char bnxt_version[] =
34 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
35 int bnxt_logtype_driver;
37 #define PCI_VENDOR_ID_BROADCOM 0x14E4
39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
40 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
41 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
42 #define BROADCOM_DEV_ID_57414_VF 0x16c1
43 #define BROADCOM_DEV_ID_57301 0x16c8
44 #define BROADCOM_DEV_ID_57302 0x16c9
45 #define BROADCOM_DEV_ID_57304_PF 0x16ca
46 #define BROADCOM_DEV_ID_57304_VF 0x16cb
47 #define BROADCOM_DEV_ID_57417_MF 0x16cc
48 #define BROADCOM_DEV_ID_NS2 0x16cd
49 #define BROADCOM_DEV_ID_57311 0x16ce
50 #define BROADCOM_DEV_ID_57312 0x16cf
51 #define BROADCOM_DEV_ID_57402 0x16d0
52 #define BROADCOM_DEV_ID_57404 0x16d1
53 #define BROADCOM_DEV_ID_57406_PF 0x16d2
54 #define BROADCOM_DEV_ID_57406_VF 0x16d3
55 #define BROADCOM_DEV_ID_57402_MF 0x16d4
56 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
57 #define BROADCOM_DEV_ID_57412 0x16d6
58 #define BROADCOM_DEV_ID_57414 0x16d7
59 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
60 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
61 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
62 #define BROADCOM_DEV_ID_57412_MF 0x16de
63 #define BROADCOM_DEV_ID_57314 0x16df
64 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
65 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
66 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
67 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
68 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
69 #define BROADCOM_DEV_ID_57404_MF 0x16e7
70 #define BROADCOM_DEV_ID_57406_MF 0x16e8
71 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
72 #define BROADCOM_DEV_ID_57407_MF 0x16ea
73 #define BROADCOM_DEV_ID_57414_MF 0x16ec
74 #define BROADCOM_DEV_ID_57416_MF 0x16ee
75 #define BROADCOM_DEV_ID_57508 0x1750
76 #define BROADCOM_DEV_ID_57504 0x1751
77 #define BROADCOM_DEV_ID_57502 0x1752
78 #define BROADCOM_DEV_ID_57500_VF1 0x1806
79 #define BROADCOM_DEV_ID_57500_VF2 0x1807
80 #define BROADCOM_DEV_ID_58802 0xd802
81 #define BROADCOM_DEV_ID_58804 0xd804
82 #define BROADCOM_DEV_ID_58808 0x16f0
83 #define BROADCOM_DEV_ID_58802_VF 0xd800
85 static const struct rte_pci_id bnxt_pci_id_map[] = {
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
87 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
89 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
98 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
122 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
123 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
124 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
125 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
126 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
127 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
128 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
129 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
130 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
131 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
132 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
133 { .vendor_id = 0, /* sentinel */ },
136 #define BNXT_ETH_RSS_SUPPORT ( \
138 ETH_RSS_NONFRAG_IPV4_TCP | \
139 ETH_RSS_NONFRAG_IPV4_UDP | \
141 ETH_RSS_NONFRAG_IPV6_TCP | \
142 ETH_RSS_NONFRAG_IPV6_UDP)
144 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
145 DEV_TX_OFFLOAD_IPV4_CKSUM | \
146 DEV_TX_OFFLOAD_TCP_CKSUM | \
147 DEV_TX_OFFLOAD_UDP_CKSUM | \
148 DEV_TX_OFFLOAD_TCP_TSO | \
149 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
150 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
151 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
152 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
153 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
154 DEV_TX_OFFLOAD_QINQ_INSERT | \
155 DEV_TX_OFFLOAD_MULTI_SEGS)
157 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
158 DEV_RX_OFFLOAD_VLAN_STRIP | \
159 DEV_RX_OFFLOAD_IPV4_CKSUM | \
160 DEV_RX_OFFLOAD_UDP_CKSUM | \
161 DEV_RX_OFFLOAD_TCP_CKSUM | \
162 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
163 DEV_RX_OFFLOAD_JUMBO_FRAME | \
164 DEV_RX_OFFLOAD_KEEP_CRC | \
165 DEV_RX_OFFLOAD_VLAN_EXTEND | \
166 DEV_RX_OFFLOAD_TCP_LRO)
168 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
169 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
170 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
171 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
172 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
173 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
174 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
176 int is_bnxt_in_error(struct bnxt *bp)
178 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
180 if (bp->flags & BNXT_FLAG_FW_RESET)
186 /***********************/
189 * High level utility functions
192 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
194 if (!BNXT_CHIP_THOR(bp))
197 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
198 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
199 BNXT_RSS_ENTRIES_PER_CTX_THOR;
202 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
204 if (!BNXT_CHIP_THOR(bp))
205 return HW_HASH_INDEX_SIZE;
207 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
210 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
212 bnxt_free_filter_mem(bp);
213 bnxt_free_vnic_attributes(bp);
214 bnxt_free_vnic_mem(bp);
216 /* tx/rx rings are configured as part of *_queue_setup callbacks.
217 * If the number of rings change across fw update,
218 * we don't have much choice except to warn the user.
222 bnxt_free_tx_rings(bp);
223 bnxt_free_rx_rings(bp);
225 bnxt_free_async_cp_ring(bp);
228 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
232 rc = bnxt_alloc_ring_grps(bp);
236 rc = bnxt_alloc_async_ring_struct(bp);
240 rc = bnxt_alloc_vnic_mem(bp);
244 rc = bnxt_alloc_vnic_attributes(bp);
248 rc = bnxt_alloc_filter_mem(bp);
252 rc = bnxt_alloc_async_cp_ring(bp);
259 bnxt_free_mem(bp, reconfig);
263 static int bnxt_init_chip(struct bnxt *bp)
265 struct bnxt_rx_queue *rxq;
266 struct rte_eth_link new;
267 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
268 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
269 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
270 uint64_t rx_offloads = dev_conf->rxmode.offloads;
271 uint32_t intr_vector = 0;
272 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
273 uint32_t vec = BNXT_MISC_VEC_ID;
277 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
278 bp->eth_dev->data->dev_conf.rxmode.offloads |=
279 DEV_RX_OFFLOAD_JUMBO_FRAME;
280 bp->flags |= BNXT_FLAG_JUMBO;
282 bp->eth_dev->data->dev_conf.rxmode.offloads &=
283 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
284 bp->flags &= ~BNXT_FLAG_JUMBO;
287 /* THOR does not support ring groups.
288 * But we will use the array to save RSS context IDs.
290 if (BNXT_CHIP_THOR(bp))
291 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
293 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
295 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
299 rc = bnxt_alloc_hwrm_rings(bp);
301 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
305 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
307 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
311 rc = bnxt_mq_rx_configure(bp);
313 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
317 /* VNIC configuration */
318 for (i = 0; i < bp->nr_vnics; i++) {
319 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
320 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
321 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
323 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
324 if (!vnic->fw_grp_ids) {
326 "Failed to alloc %d bytes for group ids\n",
331 memset(vnic->fw_grp_ids, -1, size);
333 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
334 i, vnic, vnic->fw_grp_ids);
336 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
338 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
343 /* Alloc RSS context only if RSS mode is enabled */
344 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
345 int j, nr_ctxs = bnxt_rss_ctxts(bp);
348 for (j = 0; j < nr_ctxs; j++) {
349 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
355 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
359 vnic->num_lb_ctxts = nr_ctxs;
363 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
364 * setting is not available at this time, it will not be
365 * configured correctly in the CFA.
367 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
368 vnic->vlan_strip = true;
370 vnic->vlan_strip = false;
372 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
374 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
379 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
382 "HWRM vnic %d filter failure rc: %x\n",
387 for (j = 0; j < bp->rx_nr_rings; j++) {
388 rxq = bp->eth_dev->data->rx_queues[j];
391 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
392 j, rxq->vnic, rxq->vnic->fw_grp_ids);
394 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
395 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
398 rc = bnxt_vnic_rss_configure(bp, vnic);
401 "HWRM vnic set RSS failure rc: %x\n", rc);
405 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
407 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
408 DEV_RX_OFFLOAD_TCP_LRO)
409 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
411 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
413 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
416 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
420 /* check and configure queue intr-vector mapping */
421 if ((rte_intr_cap_multiple(intr_handle) ||
422 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
423 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
424 intr_vector = bp->eth_dev->data->nb_rx_queues;
425 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
426 if (intr_vector > bp->rx_cp_nr_rings) {
427 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
431 rc = rte_intr_efd_enable(intr_handle, intr_vector);
436 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
437 intr_handle->intr_vec =
438 rte_zmalloc("intr_vec",
439 bp->eth_dev->data->nb_rx_queues *
441 if (intr_handle->intr_vec == NULL) {
442 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
443 " intr_vec", bp->eth_dev->data->nb_rx_queues);
447 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
448 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
449 intr_handle->intr_vec, intr_handle->nb_efd,
450 intr_handle->max_intr);
451 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
453 intr_handle->intr_vec[queue_id] =
454 vec + BNXT_RX_VEC_START;
455 if (vec < base + intr_handle->nb_efd - 1)
460 /* enable uio/vfio intr/eventfd mapping */
461 rc = rte_intr_enable(intr_handle);
465 rc = bnxt_get_hwrm_link_config(bp, &new);
467 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
471 if (!bp->link_info.link_up) {
472 rc = bnxt_set_hwrm_link_config(bp, true);
475 "HWRM link config failure rc: %x\n", rc);
479 bnxt_print_link_info(bp->eth_dev);
484 rte_free(intr_handle->intr_vec);
486 rte_intr_efd_disable(intr_handle);
488 /* Some of the error status returned by FW may not be from errno.h */
495 static int bnxt_shutdown_nic(struct bnxt *bp)
497 bnxt_free_all_hwrm_resources(bp);
498 bnxt_free_all_filters(bp);
499 bnxt_free_all_vnics(bp);
503 static int bnxt_init_nic(struct bnxt *bp)
507 if (BNXT_HAS_RING_GRPS(bp)) {
508 rc = bnxt_init_ring_grps(bp);
514 bnxt_init_filters(bp);
520 * Device configuration and status function
523 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
524 struct rte_eth_dev_info *dev_info)
526 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
527 struct bnxt *bp = eth_dev->data->dev_private;
528 uint16_t max_vnics, i, j, vpool, vrxq;
529 unsigned int max_rx_rings;
532 rc = is_bnxt_in_error(bp);
537 dev_info->max_mac_addrs = bp->max_l2_ctx;
538 dev_info->max_hash_mac_addrs = 0;
540 /* PF/VF specifics */
542 dev_info->max_vfs = pdev->max_vfs;
544 max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
545 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
546 dev_info->max_rx_queues = max_rx_rings;
547 dev_info->max_tx_queues = max_rx_rings;
548 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
549 dev_info->hash_key_size = 40;
550 max_vnics = bp->max_vnics;
553 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
554 dev_info->max_mtu = BNXT_MAX_MTU;
556 /* Fast path specifics */
557 dev_info->min_rx_bufsize = 1;
558 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
560 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
561 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
562 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
563 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
564 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
567 dev_info->default_rxconf = (struct rte_eth_rxconf) {
573 .rx_free_thresh = 32,
574 /* If no descriptors available, pkts are dropped by default */
578 dev_info->default_txconf = (struct rte_eth_txconf) {
584 .tx_free_thresh = 32,
587 eth_dev->data->dev_conf.intr_conf.lsc = 1;
589 eth_dev->data->dev_conf.intr_conf.rxq = 1;
590 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
591 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
592 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
593 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
598 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
599 * need further investigation.
603 vpool = 64; /* ETH_64_POOLS */
604 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
605 for (i = 0; i < 4; vpool >>= 1, i++) {
606 if (max_vnics > vpool) {
607 for (j = 0; j < 5; vrxq >>= 1, j++) {
608 if (dev_info->max_rx_queues > vrxq) {
614 /* Not enough resources to support VMDq */
618 /* Not enough resources to support VMDq */
622 dev_info->max_vmdq_pools = vpool;
623 dev_info->vmdq_queue_num = vrxq;
625 dev_info->vmdq_pool_base = 0;
626 dev_info->vmdq_queue_base = 0;
631 /* Configure the device based on the configuration provided */
632 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
634 struct bnxt *bp = eth_dev->data->dev_private;
635 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
638 bp->rx_queues = (void *)eth_dev->data->rx_queues;
639 bp->tx_queues = (void *)eth_dev->data->tx_queues;
640 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
641 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
643 rc = is_bnxt_in_error(bp);
647 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
648 rc = bnxt_hwrm_check_vf_rings(bp);
650 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
654 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
656 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
660 /* legacy driver needs to get updated values */
661 rc = bnxt_hwrm_func_qcaps(bp);
663 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
668 /* Inherit new configurations */
669 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
670 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
671 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
672 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
673 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
677 if (BNXT_HAS_RING_GRPS(bp) &&
678 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
681 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
682 bp->max_vnics < eth_dev->data->nb_rx_queues)
685 bp->rx_cp_nr_rings = bp->rx_nr_rings;
686 bp->tx_cp_nr_rings = bp->tx_nr_rings;
688 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
690 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
691 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
693 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
699 "Insufficient resources to support requested config\n");
701 "Num Queues Requested: Tx %d, Rx %d\n",
702 eth_dev->data->nb_tx_queues,
703 eth_dev->data->nb_rx_queues);
705 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
706 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
707 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
711 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
713 struct rte_eth_link *link = ð_dev->data->dev_link;
715 if (link->link_status)
716 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
717 eth_dev->data->port_id,
718 (uint32_t)link->link_speed,
719 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
720 ("full-duplex") : ("half-duplex\n"));
722 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
723 eth_dev->data->port_id);
727 * Determine whether the current configuration requires support for scattered
728 * receive; return 1 if scattered receive is required and 0 if not.
730 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
735 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
736 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
738 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
739 RTE_PKTMBUF_HEADROOM);
740 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
746 static eth_rx_burst_t
747 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
750 #ifndef RTE_LIBRTE_IEEE1588
752 * Vector mode receive can be enabled only if scatter rx is not
753 * in use and rx offloads are limited to VLAN stripping and
756 if (!eth_dev->data->scattered_rx &&
757 !(eth_dev->data->dev_conf.rxmode.offloads &
758 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
759 DEV_RX_OFFLOAD_KEEP_CRC |
760 DEV_RX_OFFLOAD_JUMBO_FRAME |
761 DEV_RX_OFFLOAD_IPV4_CKSUM |
762 DEV_RX_OFFLOAD_UDP_CKSUM |
763 DEV_RX_OFFLOAD_TCP_CKSUM |
764 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
765 DEV_RX_OFFLOAD_VLAN_FILTER))) {
766 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
767 eth_dev->data->port_id);
768 return bnxt_recv_pkts_vec;
770 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
771 eth_dev->data->port_id);
773 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
774 eth_dev->data->port_id,
775 eth_dev->data->scattered_rx,
776 eth_dev->data->dev_conf.rxmode.offloads);
779 return bnxt_recv_pkts;
782 static eth_tx_burst_t
783 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
786 #ifndef RTE_LIBRTE_IEEE1588
788 * Vector mode transmit can be enabled only if not using scatter rx
791 if (!eth_dev->data->scattered_rx &&
792 !eth_dev->data->dev_conf.txmode.offloads) {
793 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
794 eth_dev->data->port_id);
795 return bnxt_xmit_pkts_vec;
797 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
798 eth_dev->data->port_id);
800 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
801 eth_dev->data->port_id,
802 eth_dev->data->scattered_rx,
803 eth_dev->data->dev_conf.txmode.offloads);
806 return bnxt_xmit_pkts;
809 static int bnxt_handle_if_change_status(struct bnxt *bp)
813 /* Since fw has undergone a reset and lost all contexts,
814 * set fatal flag to not issue hwrm during cleanup
816 bp->flags |= BNXT_FLAG_FATAL_ERROR;
817 bnxt_uninit_resources(bp, true);
819 /* clear fatal flag so that re-init happens */
820 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
821 rc = bnxt_init_resources(bp, true);
823 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
828 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
830 struct bnxt *bp = eth_dev->data->dev_private;
831 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
835 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
837 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
838 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
842 rc = bnxt_hwrm_if_change(bp, 1);
844 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
845 rc = bnxt_handle_if_change_status(bp);
851 rc = bnxt_init_chip(bp);
855 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
857 bnxt_link_update_op(eth_dev, 1);
859 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
860 vlan_mask |= ETH_VLAN_FILTER_MASK;
861 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
862 vlan_mask |= ETH_VLAN_STRIP_MASK;
863 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
867 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
868 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
870 bp->flags |= BNXT_FLAG_INIT_DONE;
871 eth_dev->data->dev_started = 1;
873 bnxt_schedule_fw_health_check(bp);
877 bnxt_hwrm_if_change(bp, 0);
878 bnxt_shutdown_nic(bp);
879 bnxt_free_tx_mbufs(bp);
880 bnxt_free_rx_mbufs(bp);
884 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
886 struct bnxt *bp = eth_dev->data->dev_private;
889 if (!bp->link_info.link_up)
890 rc = bnxt_set_hwrm_link_config(bp, true);
892 eth_dev->data->dev_link.link_status = 1;
894 bnxt_print_link_info(eth_dev);
898 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
900 struct bnxt *bp = eth_dev->data->dev_private;
902 eth_dev->data->dev_link.link_status = 0;
903 bnxt_set_hwrm_link_config(bp, false);
904 bp->link_info.link_up = 0;
909 /* Unload the driver, release resources */
910 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
912 struct bnxt *bp = eth_dev->data->dev_private;
913 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
914 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
916 eth_dev->data->dev_started = 0;
917 /* Prevent crashes when queues are still in use */
918 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
919 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
921 bnxt_disable_int(bp);
923 /* disable uio/vfio intr/eventfd mapping */
924 rte_intr_disable(intr_handle);
926 bnxt_cancel_fw_health_check(bp);
928 bp->flags &= ~BNXT_FLAG_INIT_DONE;
929 if (bp->eth_dev->data->dev_started) {
930 /* TBD: STOP HW queues DMA */
931 eth_dev->data->dev_link.link_status = 0;
933 bnxt_dev_set_link_down_op(eth_dev);
934 /* Wait for link to be reset and the async notification to process. */
935 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL * 2);
937 /* Clean queue intr-vector mapping */
938 rte_intr_efd_disable(intr_handle);
939 if (intr_handle->intr_vec != NULL) {
940 rte_free(intr_handle->intr_vec);
941 intr_handle->intr_vec = NULL;
944 bnxt_hwrm_port_clr_stats(bp);
945 bnxt_free_tx_mbufs(bp);
946 bnxt_free_rx_mbufs(bp);
947 /* Process any remaining notifications in default completion queue */
948 bnxt_int_handler(eth_dev);
949 bnxt_shutdown_nic(bp);
950 bnxt_hwrm_if_change(bp, 0);
954 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
956 struct bnxt *bp = eth_dev->data->dev_private;
958 if (bp->dev_stopped == 0)
959 bnxt_dev_stop_op(eth_dev);
961 if (eth_dev->data->mac_addrs != NULL) {
962 rte_free(eth_dev->data->mac_addrs);
963 eth_dev->data->mac_addrs = NULL;
965 if (bp->grp_info != NULL) {
966 rte_free(bp->grp_info);
970 bnxt_dev_uninit(eth_dev);
973 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
976 struct bnxt *bp = eth_dev->data->dev_private;
977 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
978 struct bnxt_vnic_info *vnic;
979 struct bnxt_filter_info *filter, *temp_filter;
982 if (is_bnxt_in_error(bp))
986 * Loop through all VNICs from the specified filter flow pools to
987 * remove the corresponding MAC addr filter
989 for (i = 0; i < bp->nr_vnics; i++) {
990 if (!(pool_mask & (1ULL << i)))
993 vnic = &bp->vnic_info[i];
994 filter = STAILQ_FIRST(&vnic->filter);
996 temp_filter = STAILQ_NEXT(filter, next);
997 if (filter->mac_index == index) {
998 STAILQ_REMOVE(&vnic->filter, filter,
999 bnxt_filter_info, next);
1000 bnxt_hwrm_clear_l2_filter(bp, filter);
1001 filter->mac_index = INVALID_MAC_INDEX;
1002 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1003 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1006 filter = temp_filter;
1011 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1012 struct rte_ether_addr *mac_addr,
1013 uint32_t index, uint32_t pool)
1015 struct bnxt *bp = eth_dev->data->dev_private;
1016 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1017 struct bnxt_filter_info *filter;
1020 rc = is_bnxt_in_error(bp);
1024 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1025 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1030 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1033 /* Attach requested MAC address to the new l2_filter */
1034 STAILQ_FOREACH(filter, &vnic->filter, next) {
1035 if (filter->mac_index == index) {
1037 "MAC addr already existed for pool %d\n", pool);
1041 filter = bnxt_alloc_filter(bp);
1043 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1047 filter->mac_index = index;
1048 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1050 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1052 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1054 filter->mac_index = INVALID_MAC_INDEX;
1055 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1056 bnxt_free_filter(bp, filter);
1062 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1065 struct bnxt *bp = eth_dev->data->dev_private;
1066 struct rte_eth_link new;
1067 unsigned int cnt = BNXT_LINK_WAIT_CNT;
1069 rc = is_bnxt_in_error(bp);
1073 memset(&new, 0, sizeof(new));
1075 /* Retrieve link info from hardware */
1076 rc = bnxt_get_hwrm_link_config(bp, &new);
1078 new.link_speed = ETH_LINK_SPEED_100M;
1079 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1081 "Failed to retrieve link rc = 0x%x!\n", rc);
1085 if (!wait_to_complete || new.link_status)
1088 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1092 /* Timed out or success */
1093 if (new.link_status != eth_dev->data->dev_link.link_status ||
1094 new.link_speed != eth_dev->data->dev_link.link_speed) {
1095 rte_eth_linkstatus_set(eth_dev, &new);
1097 _rte_eth_dev_callback_process(eth_dev,
1098 RTE_ETH_EVENT_INTR_LSC,
1101 bnxt_print_link_info(eth_dev);
1107 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1109 struct bnxt *bp = eth_dev->data->dev_private;
1110 struct bnxt_vnic_info *vnic;
1114 rc = is_bnxt_in_error(bp);
1118 if (bp->vnic_info == NULL)
1121 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1123 old_flags = vnic->flags;
1124 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1125 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1127 vnic->flags = old_flags;
1132 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1134 struct bnxt *bp = eth_dev->data->dev_private;
1135 struct bnxt_vnic_info *vnic;
1139 rc = is_bnxt_in_error(bp);
1143 if (bp->vnic_info == NULL)
1146 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1148 old_flags = vnic->flags;
1149 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1150 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1152 vnic->flags = old_flags;
1157 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1159 struct bnxt *bp = eth_dev->data->dev_private;
1160 struct bnxt_vnic_info *vnic;
1164 rc = is_bnxt_in_error(bp);
1168 if (bp->vnic_info == NULL)
1171 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1173 old_flags = vnic->flags;
1174 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1175 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1177 vnic->flags = old_flags;
1182 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1184 struct bnxt *bp = eth_dev->data->dev_private;
1185 struct bnxt_vnic_info *vnic;
1189 rc = is_bnxt_in_error(bp);
1193 if (bp->vnic_info == NULL)
1196 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1198 old_flags = vnic->flags;
1199 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1200 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1202 vnic->flags = old_flags;
1207 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1208 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1210 if (qid >= bp->rx_nr_rings)
1213 return bp->eth_dev->data->rx_queues[qid];
1216 /* Return rxq corresponding to a given rss table ring/group ID. */
1217 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1219 struct bnxt_rx_queue *rxq;
1222 if (!BNXT_HAS_RING_GRPS(bp)) {
1223 for (i = 0; i < bp->rx_nr_rings; i++) {
1224 rxq = bp->eth_dev->data->rx_queues[i];
1225 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1229 for (i = 0; i < bp->rx_nr_rings; i++) {
1230 if (bp->grp_info[i].fw_grp_id == fwr)
1235 return INVALID_HW_RING_ID;
1238 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1239 struct rte_eth_rss_reta_entry64 *reta_conf,
1242 struct bnxt *bp = eth_dev->data->dev_private;
1243 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1244 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1245 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1249 rc = is_bnxt_in_error(bp);
1253 if (!vnic->rss_table)
1256 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1259 if (reta_size != tbl_size) {
1260 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1261 "(%d) must equal the size supported by the hardware "
1262 "(%d)\n", reta_size, tbl_size);
1266 for (i = 0; i < reta_size; i++) {
1267 struct bnxt_rx_queue *rxq;
1269 idx = i / RTE_RETA_GROUP_SIZE;
1270 sft = i % RTE_RETA_GROUP_SIZE;
1272 if (!(reta_conf[idx].mask & (1ULL << sft)))
1275 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1277 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1281 if (BNXT_CHIP_THOR(bp)) {
1282 vnic->rss_table[i * 2] =
1283 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1284 vnic->rss_table[i * 2 + 1] =
1285 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1287 vnic->rss_table[i] =
1288 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1291 vnic->rss_table[i] =
1292 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1295 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1299 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1300 struct rte_eth_rss_reta_entry64 *reta_conf,
1303 struct bnxt *bp = eth_dev->data->dev_private;
1304 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1305 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1306 uint16_t idx, sft, i;
1309 rc = is_bnxt_in_error(bp);
1313 /* Retrieve from the default VNIC */
1316 if (!vnic->rss_table)
1319 if (reta_size != tbl_size) {
1320 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1321 "(%d) must equal the size supported by the hardware "
1322 "(%d)\n", reta_size, tbl_size);
1326 for (idx = 0, i = 0; i < reta_size; i++) {
1327 idx = i / RTE_RETA_GROUP_SIZE;
1328 sft = i % RTE_RETA_GROUP_SIZE;
1330 if (reta_conf[idx].mask & (1ULL << sft)) {
1333 if (BNXT_CHIP_THOR(bp))
1334 qid = bnxt_rss_to_qid(bp,
1335 vnic->rss_table[i * 2]);
1337 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1339 if (qid == INVALID_HW_RING_ID) {
1340 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1343 reta_conf[idx].reta[sft] = qid;
1350 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1351 struct rte_eth_rss_conf *rss_conf)
1353 struct bnxt *bp = eth_dev->data->dev_private;
1354 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1355 struct bnxt_vnic_info *vnic;
1356 uint16_t hash_type = 0;
1360 rc = is_bnxt_in_error(bp);
1365 * If RSS enablement were different than dev_configure,
1366 * then return -EINVAL
1368 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1369 if (!rss_conf->rss_hf)
1370 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1372 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1376 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1377 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1379 if (rss_conf->rss_hf & ETH_RSS_IPV4)
1380 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1381 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1382 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1383 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1384 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1385 if (rss_conf->rss_hf & ETH_RSS_IPV6)
1386 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1387 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1388 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1389 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1390 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1392 /* Update the RSS VNIC(s) */
1393 for (i = 0; i < bp->nr_vnics; i++) {
1394 vnic = &bp->vnic_info[i];
1395 vnic->hash_type = hash_type;
1398 * Use the supplied key if the key length is
1399 * acceptable and the rss_key is not NULL
1401 if (rss_conf->rss_key &&
1402 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1403 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
1404 rss_conf->rss_key_len);
1406 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1411 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1412 struct rte_eth_rss_conf *rss_conf)
1414 struct bnxt *bp = eth_dev->data->dev_private;
1415 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1417 uint32_t hash_types;
1419 rc = is_bnxt_in_error(bp);
1423 /* RSS configuration is the same for all VNICs */
1424 if (vnic && vnic->rss_hash_key) {
1425 if (rss_conf->rss_key) {
1426 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1427 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1428 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1431 hash_types = vnic->hash_type;
1432 rss_conf->rss_hf = 0;
1433 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1434 rss_conf->rss_hf |= ETH_RSS_IPV4;
1435 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1437 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1438 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1440 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1442 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1443 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1445 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1447 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1448 rss_conf->rss_hf |= ETH_RSS_IPV6;
1449 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1451 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1452 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1454 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1456 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1457 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1459 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1463 "Unknwon RSS config from firmware (%08x), RSS disabled",
1468 rss_conf->rss_hf = 0;
1473 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1474 struct rte_eth_fc_conf *fc_conf)
1476 struct bnxt *bp = dev->data->dev_private;
1477 struct rte_eth_link link_info;
1480 rc = is_bnxt_in_error(bp);
1484 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1488 memset(fc_conf, 0, sizeof(*fc_conf));
1489 if (bp->link_info.auto_pause)
1490 fc_conf->autoneg = 1;
1491 switch (bp->link_info.pause) {
1493 fc_conf->mode = RTE_FC_NONE;
1495 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1496 fc_conf->mode = RTE_FC_TX_PAUSE;
1498 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1499 fc_conf->mode = RTE_FC_RX_PAUSE;
1501 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1502 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1503 fc_conf->mode = RTE_FC_FULL;
1509 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1510 struct rte_eth_fc_conf *fc_conf)
1512 struct bnxt *bp = dev->data->dev_private;
1515 rc = is_bnxt_in_error(bp);
1519 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1520 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1524 switch (fc_conf->mode) {
1526 bp->link_info.auto_pause = 0;
1527 bp->link_info.force_pause = 0;
1529 case RTE_FC_RX_PAUSE:
1530 if (fc_conf->autoneg) {
1531 bp->link_info.auto_pause =
1532 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1533 bp->link_info.force_pause = 0;
1535 bp->link_info.auto_pause = 0;
1536 bp->link_info.force_pause =
1537 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1540 case RTE_FC_TX_PAUSE:
1541 if (fc_conf->autoneg) {
1542 bp->link_info.auto_pause =
1543 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1544 bp->link_info.force_pause = 0;
1546 bp->link_info.auto_pause = 0;
1547 bp->link_info.force_pause =
1548 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1552 if (fc_conf->autoneg) {
1553 bp->link_info.auto_pause =
1554 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1555 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1556 bp->link_info.force_pause = 0;
1558 bp->link_info.auto_pause = 0;
1559 bp->link_info.force_pause =
1560 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1561 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1565 return bnxt_set_hwrm_link_config(bp, true);
1568 /* Add UDP tunneling port */
1570 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1571 struct rte_eth_udp_tunnel *udp_tunnel)
1573 struct bnxt *bp = eth_dev->data->dev_private;
1574 uint16_t tunnel_type = 0;
1577 rc = is_bnxt_in_error(bp);
1581 switch (udp_tunnel->prot_type) {
1582 case RTE_TUNNEL_TYPE_VXLAN:
1583 if (bp->vxlan_port_cnt) {
1584 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1585 udp_tunnel->udp_port);
1586 if (bp->vxlan_port != udp_tunnel->udp_port) {
1587 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1590 bp->vxlan_port_cnt++;
1594 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1595 bp->vxlan_port_cnt++;
1597 case RTE_TUNNEL_TYPE_GENEVE:
1598 if (bp->geneve_port_cnt) {
1599 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1600 udp_tunnel->udp_port);
1601 if (bp->geneve_port != udp_tunnel->udp_port) {
1602 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1605 bp->geneve_port_cnt++;
1609 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1610 bp->geneve_port_cnt++;
1613 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1616 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1622 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1623 struct rte_eth_udp_tunnel *udp_tunnel)
1625 struct bnxt *bp = eth_dev->data->dev_private;
1626 uint16_t tunnel_type = 0;
1630 rc = is_bnxt_in_error(bp);
1634 switch (udp_tunnel->prot_type) {
1635 case RTE_TUNNEL_TYPE_VXLAN:
1636 if (!bp->vxlan_port_cnt) {
1637 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1640 if (bp->vxlan_port != udp_tunnel->udp_port) {
1641 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1642 udp_tunnel->udp_port, bp->vxlan_port);
1645 if (--bp->vxlan_port_cnt)
1649 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1650 port = bp->vxlan_fw_dst_port_id;
1652 case RTE_TUNNEL_TYPE_GENEVE:
1653 if (!bp->geneve_port_cnt) {
1654 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1657 if (bp->geneve_port != udp_tunnel->udp_port) {
1658 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1659 udp_tunnel->udp_port, bp->geneve_port);
1662 if (--bp->geneve_port_cnt)
1666 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1667 port = bp->geneve_fw_dst_port_id;
1670 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1674 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1677 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1680 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1681 bp->geneve_port = 0;
1686 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1688 struct bnxt_filter_info *filter;
1689 struct bnxt_vnic_info *vnic;
1691 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1693 /* if VLAN exists && VLAN matches vlan_id
1694 * remove the MAC+VLAN filter
1695 * add a new MAC only filter
1697 * VLAN filter doesn't exist, just skip and continue
1699 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1700 filter = STAILQ_FIRST(&vnic->filter);
1702 /* Search for this matching MAC+VLAN filter */
1703 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1704 !memcmp(filter->l2_addr,
1706 RTE_ETHER_ADDR_LEN)) {
1707 /* Delete the filter */
1708 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1711 STAILQ_REMOVE(&vnic->filter, filter,
1712 bnxt_filter_info, next);
1713 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1716 "Del Vlan filter for %d\n",
1720 filter = STAILQ_NEXT(filter, next);
1725 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1727 struct bnxt_filter_info *filter;
1728 struct bnxt_vnic_info *vnic;
1730 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1731 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1732 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1734 /* Implementation notes on the use of VNIC in this command:
1736 * By default, these filters belong to default vnic for the function.
1737 * Once these filters are set up, only destination VNIC can be modified.
1738 * If the destination VNIC is not specified in this command,
1739 * then the HWRM shall only create an l2 context id.
1742 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1743 filter = STAILQ_FIRST(&vnic->filter);
1744 /* Check if the VLAN has already been added */
1746 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1747 !memcmp(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN))
1750 filter = STAILQ_NEXT(filter, next);
1753 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1754 * command to create MAC+VLAN filter with the right flags, enables set.
1756 filter = bnxt_alloc_filter(bp);
1759 "MAC/VLAN filter alloc failed\n");
1762 /* MAC + VLAN ID filter */
1763 filter->l2_ivlan = vlan_id;
1764 filter->l2_ivlan_mask = 0x0FFF;
1765 filter->enables |= en;
1766 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1768 /* Free the newly allocated filter as we were
1769 * not able to create the filter in hardware.
1771 filter->fw_l2_filter_id = UINT64_MAX;
1772 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1776 /* Add this new filter to the list */
1777 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1779 "Added Vlan filter for %d\n", vlan_id);
1783 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1784 uint16_t vlan_id, int on)
1786 struct bnxt *bp = eth_dev->data->dev_private;
1789 rc = is_bnxt_in_error(bp);
1793 /* These operations apply to ALL existing MAC/VLAN filters */
1795 return bnxt_add_vlan_filter(bp, vlan_id);
1797 return bnxt_del_vlan_filter(bp, vlan_id);
1801 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1803 struct bnxt *bp = dev->data->dev_private;
1804 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1808 rc = is_bnxt_in_error(bp);
1812 if (mask & ETH_VLAN_FILTER_MASK) {
1813 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1814 /* Remove any VLAN filters programmed */
1815 for (i = 0; i < 4095; i++)
1816 bnxt_del_vlan_filter(bp, i);
1818 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1819 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1822 if (mask & ETH_VLAN_STRIP_MASK) {
1823 /* Enable or disable VLAN stripping */
1824 for (i = 0; i < bp->nr_vnics; i++) {
1825 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1826 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1827 vnic->vlan_strip = true;
1829 vnic->vlan_strip = false;
1830 bnxt_hwrm_vnic_cfg(bp, vnic);
1832 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1833 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1836 if (mask & ETH_VLAN_EXTEND_MASK) {
1837 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1838 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
1840 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
1847 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
1850 struct bnxt *bp = dev->data->dev_private;
1851 int qinq = dev->data->dev_conf.rxmode.offloads &
1852 DEV_RX_OFFLOAD_VLAN_EXTEND;
1854 if (vlan_type != ETH_VLAN_TYPE_INNER &&
1855 vlan_type != ETH_VLAN_TYPE_OUTER) {
1857 "Unsupported vlan type.");
1862 "QinQ not enabled. Needs to be ON as we can "
1863 "accelerate only outer vlan\n");
1867 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
1869 case RTE_ETHER_TYPE_QINQ:
1871 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
1873 case RTE_ETHER_TYPE_VLAN:
1875 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
1879 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
1883 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
1887 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
1890 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
1893 bp->outer_tpid_bd |= tpid;
1894 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
1895 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
1897 "Can accelerate only outer vlan in QinQ\n");
1905 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1906 struct rte_ether_addr *addr)
1908 struct bnxt *bp = dev->data->dev_private;
1909 /* Default Filter is tied to VNIC 0 */
1910 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1911 struct bnxt_filter_info *filter;
1914 rc = is_bnxt_in_error(bp);
1918 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1921 if (rte_is_zero_ether_addr(addr))
1924 STAILQ_FOREACH(filter, &vnic->filter, next) {
1925 /* Default Filter is at Index 0 */
1926 if (filter->mac_index != 0)
1929 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
1930 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1931 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1933 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1934 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1936 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1940 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
1941 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1949 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1950 struct rte_ether_addr *mc_addr_set,
1951 uint32_t nb_mc_addr)
1953 struct bnxt *bp = eth_dev->data->dev_private;
1954 char *mc_addr_list = (char *)mc_addr_set;
1955 struct bnxt_vnic_info *vnic;
1956 uint32_t off = 0, i = 0;
1959 rc = is_bnxt_in_error(bp);
1963 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1965 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1966 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1970 /* TODO Check for Duplicate mcast addresses */
1971 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1972 for (i = 0; i < nb_mc_addr; i++) {
1973 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1974 RTE_ETHER_ADDR_LEN);
1975 off += RTE_ETHER_ADDR_LEN;
1978 vnic->mc_addr_cnt = i;
1981 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1985 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1987 struct bnxt *bp = dev->data->dev_private;
1988 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1989 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1990 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1993 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1994 fw_major, fw_minor, fw_updt);
1996 ret += 1; /* add the size of '\0' */
1997 if (fw_size < (uint32_t)ret)
2004 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2005 struct rte_eth_rxq_info *qinfo)
2007 struct bnxt_rx_queue *rxq;
2009 rxq = dev->data->rx_queues[queue_id];
2011 qinfo->mp = rxq->mb_pool;
2012 qinfo->scattered_rx = dev->data->scattered_rx;
2013 qinfo->nb_desc = rxq->nb_rx_desc;
2015 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2016 qinfo->conf.rx_drop_en = 0;
2017 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2021 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2022 struct rte_eth_txq_info *qinfo)
2024 struct bnxt_tx_queue *txq;
2026 txq = dev->data->tx_queues[queue_id];
2028 qinfo->nb_desc = txq->nb_tx_desc;
2030 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2031 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2032 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2034 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2035 qinfo->conf.tx_rs_thresh = 0;
2036 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2039 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2041 struct bnxt *bp = eth_dev->data->dev_private;
2042 uint32_t new_pkt_size;
2046 rc = is_bnxt_in_error(bp);
2050 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2051 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2055 * If vector-mode tx/rx is active, disallow any MTU change that would
2056 * require scattered receive support.
2058 if (eth_dev->data->dev_started &&
2059 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2060 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2062 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2064 "MTU change would require scattered rx support. ");
2065 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2070 if (new_mtu > RTE_ETHER_MTU) {
2071 bp->flags |= BNXT_FLAG_JUMBO;
2072 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2073 DEV_RX_OFFLOAD_JUMBO_FRAME;
2075 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2076 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2077 bp->flags &= ~BNXT_FLAG_JUMBO;
2080 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2082 for (i = 0; i < bp->nr_vnics; i++) {
2083 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2086 vnic->mru = new_mtu + RTE_ETHER_HDR_LEN +
2087 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
2088 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2092 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2093 size -= RTE_PKTMBUF_HEADROOM;
2095 if (size < new_mtu) {
2096 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2102 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2108 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2110 struct bnxt *bp = dev->data->dev_private;
2111 uint16_t vlan = bp->vlan;
2114 rc = is_bnxt_in_error(bp);
2118 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2120 "PVID cannot be modified for this function\n");
2123 bp->vlan = on ? pvid : 0;
2125 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2132 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2134 struct bnxt *bp = dev->data->dev_private;
2137 rc = is_bnxt_in_error(bp);
2141 return bnxt_hwrm_port_led_cfg(bp, true);
2145 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2147 struct bnxt *bp = dev->data->dev_private;
2150 rc = is_bnxt_in_error(bp);
2154 return bnxt_hwrm_port_led_cfg(bp, false);
2158 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2160 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2161 uint32_t desc = 0, raw_cons = 0, cons;
2162 struct bnxt_cp_ring_info *cpr;
2163 struct bnxt_rx_queue *rxq;
2164 struct rx_pkt_cmpl *rxcmp;
2167 rc = is_bnxt_in_error(bp);
2171 rxq = dev->data->rx_queues[rx_queue_id];
2173 raw_cons = cpr->cp_raw_cons;
2176 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2177 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2178 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2180 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2192 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2194 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2195 struct bnxt_rx_ring_info *rxr;
2196 struct bnxt_cp_ring_info *cpr;
2197 struct bnxt_sw_rx_bd *rx_buf;
2198 struct rx_pkt_cmpl *rxcmp;
2199 uint32_t cons, cp_cons;
2205 rc = is_bnxt_in_error(rxq->bp);
2212 if (offset >= rxq->nb_rx_desc)
2215 cons = RING_CMP(cpr->cp_ring_struct, offset);
2216 cp_cons = cpr->cp_raw_cons;
2217 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2219 if (cons > cp_cons) {
2220 if (CMPL_VALID(rxcmp, cpr->valid))
2221 return RTE_ETH_RX_DESC_DONE;
2223 if (CMPL_VALID(rxcmp, !cpr->valid))
2224 return RTE_ETH_RX_DESC_DONE;
2226 rx_buf = &rxr->rx_buf_ring[cons];
2227 if (rx_buf->mbuf == NULL)
2228 return RTE_ETH_RX_DESC_UNAVAIL;
2231 return RTE_ETH_RX_DESC_AVAIL;
2235 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2237 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2238 struct bnxt_tx_ring_info *txr;
2239 struct bnxt_cp_ring_info *cpr;
2240 struct bnxt_sw_tx_bd *tx_buf;
2241 struct tx_pkt_cmpl *txcmp;
2242 uint32_t cons, cp_cons;
2248 rc = is_bnxt_in_error(txq->bp);
2255 if (offset >= txq->nb_tx_desc)
2258 cons = RING_CMP(cpr->cp_ring_struct, offset);
2259 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2260 cp_cons = cpr->cp_raw_cons;
2262 if (cons > cp_cons) {
2263 if (CMPL_VALID(txcmp, cpr->valid))
2264 return RTE_ETH_TX_DESC_UNAVAIL;
2266 if (CMPL_VALID(txcmp, !cpr->valid))
2267 return RTE_ETH_TX_DESC_UNAVAIL;
2269 tx_buf = &txr->tx_buf_ring[cons];
2270 if (tx_buf->mbuf == NULL)
2271 return RTE_ETH_TX_DESC_DONE;
2273 return RTE_ETH_TX_DESC_FULL;
2276 static struct bnxt_filter_info *
2277 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2278 struct rte_eth_ethertype_filter *efilter,
2279 struct bnxt_vnic_info *vnic0,
2280 struct bnxt_vnic_info *vnic,
2283 struct bnxt_filter_info *mfilter = NULL;
2287 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2288 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2289 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2290 " ethertype filter.", efilter->ether_type);
2294 if (efilter->queue >= bp->rx_nr_rings) {
2295 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2300 vnic0 = &bp->vnic_info[0];
2301 vnic = &bp->vnic_info[efilter->queue];
2303 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2308 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2309 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2310 if ((!memcmp(efilter->mac_addr.addr_bytes,
2311 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2313 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2314 mfilter->ethertype == efilter->ether_type)) {
2320 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2321 if ((!memcmp(efilter->mac_addr.addr_bytes,
2322 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2323 mfilter->ethertype == efilter->ether_type &&
2325 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2339 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2340 enum rte_filter_op filter_op,
2343 struct bnxt *bp = dev->data->dev_private;
2344 struct rte_eth_ethertype_filter *efilter =
2345 (struct rte_eth_ethertype_filter *)arg;
2346 struct bnxt_filter_info *bfilter, *filter1;
2347 struct bnxt_vnic_info *vnic, *vnic0;
2350 if (filter_op == RTE_ETH_FILTER_NOP)
2354 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2359 vnic0 = &bp->vnic_info[0];
2360 vnic = &bp->vnic_info[efilter->queue];
2362 switch (filter_op) {
2363 case RTE_ETH_FILTER_ADD:
2364 bnxt_match_and_validate_ether_filter(bp, efilter,
2369 bfilter = bnxt_get_unused_filter(bp);
2370 if (bfilter == NULL) {
2372 "Not enough resources for a new filter.\n");
2375 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2376 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2377 RTE_ETHER_ADDR_LEN);
2378 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2379 RTE_ETHER_ADDR_LEN);
2380 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2381 bfilter->ethertype = efilter->ether_type;
2382 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2384 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2385 if (filter1 == NULL) {
2390 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2391 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2393 bfilter->dst_id = vnic->fw_vnic_id;
2395 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2397 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2400 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2403 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2405 case RTE_ETH_FILTER_DELETE:
2406 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2408 if (ret == -EEXIST) {
2409 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2411 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2413 bnxt_free_filter(bp, filter1);
2414 } else if (ret == 0) {
2415 PMD_DRV_LOG(ERR, "No matching filter found\n");
2419 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2425 bnxt_free_filter(bp, bfilter);
2431 parse_ntuple_filter(struct bnxt *bp,
2432 struct rte_eth_ntuple_filter *nfilter,
2433 struct bnxt_filter_info *bfilter)
2437 if (nfilter->queue >= bp->rx_nr_rings) {
2438 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2442 switch (nfilter->dst_port_mask) {
2444 bfilter->dst_port_mask = -1;
2445 bfilter->dst_port = nfilter->dst_port;
2446 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2447 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2450 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2454 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2455 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2457 switch (nfilter->proto_mask) {
2459 if (nfilter->proto == 17) /* IPPROTO_UDP */
2460 bfilter->ip_protocol = 17;
2461 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2462 bfilter->ip_protocol = 6;
2465 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2468 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2472 switch (nfilter->dst_ip_mask) {
2474 bfilter->dst_ipaddr_mask[0] = -1;
2475 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2476 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2477 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2480 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2484 switch (nfilter->src_ip_mask) {
2486 bfilter->src_ipaddr_mask[0] = -1;
2487 bfilter->src_ipaddr[0] = nfilter->src_ip;
2488 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2489 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2492 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2496 switch (nfilter->src_port_mask) {
2498 bfilter->src_port_mask = -1;
2499 bfilter->src_port = nfilter->src_port;
2500 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2501 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2504 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2509 //nfilter->priority = (uint8_t)filter->priority;
2511 bfilter->enables = en;
2515 static struct bnxt_filter_info*
2516 bnxt_match_ntuple_filter(struct bnxt *bp,
2517 struct bnxt_filter_info *bfilter,
2518 struct bnxt_vnic_info **mvnic)
2520 struct bnxt_filter_info *mfilter = NULL;
2523 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2524 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2525 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2526 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2527 bfilter->src_ipaddr_mask[0] ==
2528 mfilter->src_ipaddr_mask[0] &&
2529 bfilter->src_port == mfilter->src_port &&
2530 bfilter->src_port_mask == mfilter->src_port_mask &&
2531 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2532 bfilter->dst_ipaddr_mask[0] ==
2533 mfilter->dst_ipaddr_mask[0] &&
2534 bfilter->dst_port == mfilter->dst_port &&
2535 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2536 bfilter->flags == mfilter->flags &&
2537 bfilter->enables == mfilter->enables) {
2548 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2549 struct rte_eth_ntuple_filter *nfilter,
2550 enum rte_filter_op filter_op)
2552 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2553 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2556 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2557 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2561 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2562 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2566 bfilter = bnxt_get_unused_filter(bp);
2567 if (bfilter == NULL) {
2569 "Not enough resources for a new filter.\n");
2572 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2576 vnic = &bp->vnic_info[nfilter->queue];
2577 vnic0 = &bp->vnic_info[0];
2578 filter1 = STAILQ_FIRST(&vnic0->filter);
2579 if (filter1 == NULL) {
2584 bfilter->dst_id = vnic->fw_vnic_id;
2585 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2587 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2588 bfilter->ethertype = 0x800;
2589 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2591 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2593 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2594 bfilter->dst_id == mfilter->dst_id) {
2595 PMD_DRV_LOG(ERR, "filter exists.\n");
2598 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2599 bfilter->dst_id != mfilter->dst_id) {
2600 mfilter->dst_id = vnic->fw_vnic_id;
2601 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2602 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2603 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2604 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2605 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2608 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2609 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2614 if (filter_op == RTE_ETH_FILTER_ADD) {
2615 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2616 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2619 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2621 if (mfilter == NULL) {
2622 /* This should not happen. But for Coverity! */
2626 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2628 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2629 bnxt_free_filter(bp, mfilter);
2630 mfilter->fw_l2_filter_id = -1;
2631 bnxt_free_filter(bp, bfilter);
2632 bfilter->fw_l2_filter_id = -1;
2637 bfilter->fw_l2_filter_id = -1;
2638 bnxt_free_filter(bp, bfilter);
2643 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2644 enum rte_filter_op filter_op,
2647 struct bnxt *bp = dev->data->dev_private;
2650 if (filter_op == RTE_ETH_FILTER_NOP)
2654 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2659 switch (filter_op) {
2660 case RTE_ETH_FILTER_ADD:
2661 ret = bnxt_cfg_ntuple_filter(bp,
2662 (struct rte_eth_ntuple_filter *)arg,
2665 case RTE_ETH_FILTER_DELETE:
2666 ret = bnxt_cfg_ntuple_filter(bp,
2667 (struct rte_eth_ntuple_filter *)arg,
2671 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2679 bnxt_parse_fdir_filter(struct bnxt *bp,
2680 struct rte_eth_fdir_filter *fdir,
2681 struct bnxt_filter_info *filter)
2683 enum rte_fdir_mode fdir_mode =
2684 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2685 struct bnxt_vnic_info *vnic0, *vnic;
2686 struct bnxt_filter_info *filter1;
2690 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2693 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2694 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2696 switch (fdir->input.flow_type) {
2697 case RTE_ETH_FLOW_IPV4:
2698 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2700 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2701 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2702 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2703 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2704 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2705 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2706 filter->ip_addr_type =
2707 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2708 filter->src_ipaddr_mask[0] = 0xffffffff;
2709 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2710 filter->dst_ipaddr_mask[0] = 0xffffffff;
2711 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2712 filter->ethertype = 0x800;
2713 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2715 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2716 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2717 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2718 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2719 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2720 filter->dst_port_mask = 0xffff;
2721 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2722 filter->src_port_mask = 0xffff;
2723 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2724 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2725 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2726 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2727 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2728 filter->ip_protocol = 6;
2729 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2730 filter->ip_addr_type =
2731 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2732 filter->src_ipaddr_mask[0] = 0xffffffff;
2733 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2734 filter->dst_ipaddr_mask[0] = 0xffffffff;
2735 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2736 filter->ethertype = 0x800;
2737 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2739 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2740 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2741 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2742 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2743 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2744 filter->dst_port_mask = 0xffff;
2745 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2746 filter->src_port_mask = 0xffff;
2747 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2748 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2749 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2750 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2751 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2752 filter->ip_protocol = 17;
2753 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2754 filter->ip_addr_type =
2755 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2756 filter->src_ipaddr_mask[0] = 0xffffffff;
2757 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2758 filter->dst_ipaddr_mask[0] = 0xffffffff;
2759 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2760 filter->ethertype = 0x800;
2761 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2763 case RTE_ETH_FLOW_IPV6:
2764 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2766 filter->ip_addr_type =
2767 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2768 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2769 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2770 rte_memcpy(filter->src_ipaddr,
2771 fdir->input.flow.ipv6_flow.src_ip, 16);
2772 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2773 rte_memcpy(filter->dst_ipaddr,
2774 fdir->input.flow.ipv6_flow.dst_ip, 16);
2775 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2776 memset(filter->dst_ipaddr_mask, 0xff, 16);
2777 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2778 memset(filter->src_ipaddr_mask, 0xff, 16);
2779 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2780 filter->ethertype = 0x86dd;
2781 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2783 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2784 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2785 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2786 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2787 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2788 filter->dst_port_mask = 0xffff;
2789 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2790 filter->src_port_mask = 0xffff;
2791 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2792 filter->ip_addr_type =
2793 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2794 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2795 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2796 rte_memcpy(filter->src_ipaddr,
2797 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2798 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2799 rte_memcpy(filter->dst_ipaddr,
2800 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2801 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2802 memset(filter->dst_ipaddr_mask, 0xff, 16);
2803 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2804 memset(filter->src_ipaddr_mask, 0xff, 16);
2805 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2806 filter->ethertype = 0x86dd;
2807 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2809 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2810 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2811 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2812 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2813 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2814 filter->dst_port_mask = 0xffff;
2815 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2816 filter->src_port_mask = 0xffff;
2817 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2818 filter->ip_addr_type =
2819 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2820 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2821 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2822 rte_memcpy(filter->src_ipaddr,
2823 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2824 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2825 rte_memcpy(filter->dst_ipaddr,
2826 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2827 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2828 memset(filter->dst_ipaddr_mask, 0xff, 16);
2829 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2830 memset(filter->src_ipaddr_mask, 0xff, 16);
2831 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2832 filter->ethertype = 0x86dd;
2833 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2835 case RTE_ETH_FLOW_L2_PAYLOAD:
2836 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2837 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2839 case RTE_ETH_FLOW_VXLAN:
2840 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2842 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2843 filter->tunnel_type =
2844 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2845 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2847 case RTE_ETH_FLOW_NVGRE:
2848 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2850 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2851 filter->tunnel_type =
2852 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2853 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2855 case RTE_ETH_FLOW_UNKNOWN:
2856 case RTE_ETH_FLOW_RAW:
2857 case RTE_ETH_FLOW_FRAG_IPV4:
2858 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2859 case RTE_ETH_FLOW_FRAG_IPV6:
2860 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2861 case RTE_ETH_FLOW_IPV6_EX:
2862 case RTE_ETH_FLOW_IPV6_TCP_EX:
2863 case RTE_ETH_FLOW_IPV6_UDP_EX:
2864 case RTE_ETH_FLOW_GENEVE:
2870 vnic0 = &bp->vnic_info[0];
2871 vnic = &bp->vnic_info[fdir->action.rx_queue];
2873 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2878 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2879 rte_memcpy(filter->dst_macaddr,
2880 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2881 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2884 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2885 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2886 filter1 = STAILQ_FIRST(&vnic0->filter);
2887 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2889 filter->dst_id = vnic->fw_vnic_id;
2890 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2891 if (filter->dst_macaddr[i] == 0x00)
2892 filter1 = STAILQ_FIRST(&vnic0->filter);
2894 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2897 if (filter1 == NULL)
2900 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2901 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2903 filter->enables = en;
2908 static struct bnxt_filter_info *
2909 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2910 struct bnxt_vnic_info **mvnic)
2912 struct bnxt_filter_info *mf = NULL;
2915 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2916 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2918 STAILQ_FOREACH(mf, &vnic->filter, next) {
2919 if (mf->filter_type == nf->filter_type &&
2920 mf->flags == nf->flags &&
2921 mf->src_port == nf->src_port &&
2922 mf->src_port_mask == nf->src_port_mask &&
2923 mf->dst_port == nf->dst_port &&
2924 mf->dst_port_mask == nf->dst_port_mask &&
2925 mf->ip_protocol == nf->ip_protocol &&
2926 mf->ip_addr_type == nf->ip_addr_type &&
2927 mf->ethertype == nf->ethertype &&
2928 mf->vni == nf->vni &&
2929 mf->tunnel_type == nf->tunnel_type &&
2930 mf->l2_ovlan == nf->l2_ovlan &&
2931 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2932 mf->l2_ivlan == nf->l2_ivlan &&
2933 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2934 !memcmp(mf->l2_addr, nf->l2_addr,
2935 RTE_ETHER_ADDR_LEN) &&
2936 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2937 RTE_ETHER_ADDR_LEN) &&
2938 !memcmp(mf->src_macaddr, nf->src_macaddr,
2939 RTE_ETHER_ADDR_LEN) &&
2940 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2941 RTE_ETHER_ADDR_LEN) &&
2942 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2943 sizeof(nf->src_ipaddr)) &&
2944 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2945 sizeof(nf->src_ipaddr_mask)) &&
2946 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2947 sizeof(nf->dst_ipaddr)) &&
2948 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2949 sizeof(nf->dst_ipaddr_mask))) {
2960 bnxt_fdir_filter(struct rte_eth_dev *dev,
2961 enum rte_filter_op filter_op,
2964 struct bnxt *bp = dev->data->dev_private;
2965 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
2966 struct bnxt_filter_info *filter, *match;
2967 struct bnxt_vnic_info *vnic, *mvnic;
2970 if (filter_op == RTE_ETH_FILTER_NOP)
2973 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2976 switch (filter_op) {
2977 case RTE_ETH_FILTER_ADD:
2978 case RTE_ETH_FILTER_DELETE:
2980 filter = bnxt_get_unused_filter(bp);
2981 if (filter == NULL) {
2983 "Not enough resources for a new flow.\n");
2987 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2990 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2992 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2993 vnic = &bp->vnic_info[0];
2995 vnic = &bp->vnic_info[fdir->action.rx_queue];
2997 match = bnxt_match_fdir(bp, filter, &mvnic);
2998 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2999 if (match->dst_id == vnic->fw_vnic_id) {
3000 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3004 match->dst_id = vnic->fw_vnic_id;
3005 ret = bnxt_hwrm_set_ntuple_filter(bp,
3008 STAILQ_REMOVE(&mvnic->filter, match,
3009 bnxt_filter_info, next);
3010 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3012 "Filter with matching pattern exist\n");
3014 "Updated it to new destination q\n");
3018 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3019 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3024 if (filter_op == RTE_ETH_FILTER_ADD) {
3025 ret = bnxt_hwrm_set_ntuple_filter(bp,
3030 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3032 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3033 STAILQ_REMOVE(&vnic->filter, match,
3034 bnxt_filter_info, next);
3035 bnxt_free_filter(bp, match);
3036 filter->fw_l2_filter_id = -1;
3037 bnxt_free_filter(bp, filter);
3040 case RTE_ETH_FILTER_FLUSH:
3041 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3042 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3044 STAILQ_FOREACH(filter, &vnic->filter, next) {
3045 if (filter->filter_type ==
3046 HWRM_CFA_NTUPLE_FILTER) {
3048 bnxt_hwrm_clear_ntuple_filter(bp,
3050 STAILQ_REMOVE(&vnic->filter, filter,
3051 bnxt_filter_info, next);
3056 case RTE_ETH_FILTER_UPDATE:
3057 case RTE_ETH_FILTER_STATS:
3058 case RTE_ETH_FILTER_INFO:
3059 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3062 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3069 filter->fw_l2_filter_id = -1;
3070 bnxt_free_filter(bp, filter);
3075 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
3076 enum rte_filter_type filter_type,
3077 enum rte_filter_op filter_op, void *arg)
3081 ret = is_bnxt_in_error(dev->data->dev_private);
3085 switch (filter_type) {
3086 case RTE_ETH_FILTER_TUNNEL:
3088 "filter type: %d: To be implemented\n", filter_type);
3090 case RTE_ETH_FILTER_FDIR:
3091 ret = bnxt_fdir_filter(dev, filter_op, arg);
3093 case RTE_ETH_FILTER_NTUPLE:
3094 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3096 case RTE_ETH_FILTER_ETHERTYPE:
3097 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3099 case RTE_ETH_FILTER_GENERIC:
3100 if (filter_op != RTE_ETH_FILTER_GET)
3102 *(const void **)arg = &bnxt_flow_ops;
3106 "Filter type (%d) not supported", filter_type);
3113 static const uint32_t *
3114 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3116 static const uint32_t ptypes[] = {
3117 RTE_PTYPE_L2_ETHER_VLAN,
3118 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3119 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3123 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3124 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3125 RTE_PTYPE_INNER_L4_ICMP,
3126 RTE_PTYPE_INNER_L4_TCP,
3127 RTE_PTYPE_INNER_L4_UDP,
3131 if (!dev->rx_pkt_burst)
3137 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3140 uint32_t reg_base = *reg_arr & 0xfffff000;
3144 for (i = 0; i < count; i++) {
3145 if ((reg_arr[i] & 0xfffff000) != reg_base)
3148 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3149 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3153 static int bnxt_map_ptp_regs(struct bnxt *bp)
3155 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3159 reg_arr = ptp->rx_regs;
3160 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3164 reg_arr = ptp->tx_regs;
3165 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3169 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3170 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3172 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3173 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3178 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3180 rte_write32(0, (uint8_t *)bp->bar0 +
3181 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3182 rte_write32(0, (uint8_t *)bp->bar0 +
3183 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3186 static uint64_t bnxt_cc_read(struct bnxt *bp)
3190 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3191 BNXT_GRCPF_REG_SYNC_TIME));
3192 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3193 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3197 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3199 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3202 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3203 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3204 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3207 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3208 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3209 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3210 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3211 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3212 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3217 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3219 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3220 struct bnxt_pf_info *pf = &bp->pf;
3227 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3228 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3229 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3232 port_id = pf->port_id;
3233 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3234 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3236 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3237 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3238 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3239 /* bnxt_clr_rx_ts(bp); TBD */
3243 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3244 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3245 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3246 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3252 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3255 struct bnxt *bp = dev->data->dev_private;
3256 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3261 ns = rte_timespec_to_ns(ts);
3262 /* Set the timecounters to a new value. */
3269 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3271 struct bnxt *bp = dev->data->dev_private;
3272 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3273 uint64_t ns, systime_cycles = 0;
3279 if (BNXT_CHIP_THOR(bp))
3280 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3283 systime_cycles = bnxt_cc_read(bp);
3285 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3286 *ts = rte_ns_to_timespec(ns);
3291 bnxt_timesync_enable(struct rte_eth_dev *dev)
3293 struct bnxt *bp = dev->data->dev_private;
3294 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3302 ptp->tx_tstamp_en = 1;
3303 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3305 rc = bnxt_hwrm_ptp_cfg(bp);
3309 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3310 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3311 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3313 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3314 ptp->tc.cc_shift = shift;
3315 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3317 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3318 ptp->rx_tstamp_tc.cc_shift = shift;
3319 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3321 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3322 ptp->tx_tstamp_tc.cc_shift = shift;
3323 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3325 if (!BNXT_CHIP_THOR(bp))
3326 bnxt_map_ptp_regs(bp);
3332 bnxt_timesync_disable(struct rte_eth_dev *dev)
3334 struct bnxt *bp = dev->data->dev_private;
3335 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3341 ptp->tx_tstamp_en = 0;
3344 bnxt_hwrm_ptp_cfg(bp);
3346 if (!BNXT_CHIP_THOR(bp))
3347 bnxt_unmap_ptp_regs(bp);
3353 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3354 struct timespec *timestamp,
3355 uint32_t flags __rte_unused)
3357 struct bnxt *bp = dev->data->dev_private;
3358 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3359 uint64_t rx_tstamp_cycles = 0;
3365 if (BNXT_CHIP_THOR(bp))
3366 rx_tstamp_cycles = ptp->rx_timestamp;
3368 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3370 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3371 *timestamp = rte_ns_to_timespec(ns);
3376 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3377 struct timespec *timestamp)
3379 struct bnxt *bp = dev->data->dev_private;
3380 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3381 uint64_t tx_tstamp_cycles = 0;
3388 if (BNXT_CHIP_THOR(bp))
3389 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3392 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3394 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3395 *timestamp = rte_ns_to_timespec(ns);
3401 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3403 struct bnxt *bp = dev->data->dev_private;
3404 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3409 ptp->tc.nsec += delta;
3415 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3417 struct bnxt *bp = dev->data->dev_private;
3419 uint32_t dir_entries;
3420 uint32_t entry_length;
3422 rc = is_bnxt_in_error(bp);
3426 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3427 bp->pdev->addr.domain, bp->pdev->addr.bus,
3428 bp->pdev->addr.devid, bp->pdev->addr.function);
3430 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3434 return dir_entries * entry_length;
3438 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3439 struct rte_dev_eeprom_info *in_eeprom)
3441 struct bnxt *bp = dev->data->dev_private;
3446 rc = is_bnxt_in_error(bp);
3450 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3451 "len = %d\n", bp->pdev->addr.domain,
3452 bp->pdev->addr.bus, bp->pdev->addr.devid,
3453 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3455 if (in_eeprom->offset == 0) /* special offset value to get directory */
3456 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3459 index = in_eeprom->offset >> 24;
3460 offset = in_eeprom->offset & 0xffffff;
3463 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3464 in_eeprom->length, in_eeprom->data);
3469 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3472 case BNX_DIR_TYPE_CHIMP_PATCH:
3473 case BNX_DIR_TYPE_BOOTCODE:
3474 case BNX_DIR_TYPE_BOOTCODE_2:
3475 case BNX_DIR_TYPE_APE_FW:
3476 case BNX_DIR_TYPE_APE_PATCH:
3477 case BNX_DIR_TYPE_KONG_FW:
3478 case BNX_DIR_TYPE_KONG_PATCH:
3479 case BNX_DIR_TYPE_BONO_FW:
3480 case BNX_DIR_TYPE_BONO_PATCH:
3488 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3491 case BNX_DIR_TYPE_AVS:
3492 case BNX_DIR_TYPE_EXP_ROM_MBA:
3493 case BNX_DIR_TYPE_PCIE:
3494 case BNX_DIR_TYPE_TSCF_UCODE:
3495 case BNX_DIR_TYPE_EXT_PHY:
3496 case BNX_DIR_TYPE_CCM:
3497 case BNX_DIR_TYPE_ISCSI_BOOT:
3498 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3499 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3507 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3509 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3510 bnxt_dir_type_is_other_exec_format(dir_type);
3514 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3515 struct rte_dev_eeprom_info *in_eeprom)
3517 struct bnxt *bp = dev->data->dev_private;
3518 uint8_t index, dir_op;
3519 uint16_t type, ext, ordinal, attr;
3522 rc = is_bnxt_in_error(bp);
3526 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3527 "len = %d\n", bp->pdev->addr.domain,
3528 bp->pdev->addr.bus, bp->pdev->addr.devid,
3529 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3532 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3536 type = in_eeprom->magic >> 16;
3538 if (type == 0xffff) { /* special value for directory operations */
3539 index = in_eeprom->magic & 0xff;
3540 dir_op = in_eeprom->magic >> 8;
3544 case 0x0e: /* erase */
3545 if (in_eeprom->offset != ~in_eeprom->magic)
3547 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3553 /* Create or re-write an NVM item: */
3554 if (bnxt_dir_type_is_executable(type) == true)
3556 ext = in_eeprom->magic & 0xffff;
3557 ordinal = in_eeprom->offset >> 16;
3558 attr = in_eeprom->offset & 0xffff;
3560 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3561 in_eeprom->data, in_eeprom->length);
3568 static const struct eth_dev_ops bnxt_dev_ops = {
3569 .dev_infos_get = bnxt_dev_info_get_op,
3570 .dev_close = bnxt_dev_close_op,
3571 .dev_configure = bnxt_dev_configure_op,
3572 .dev_start = bnxt_dev_start_op,
3573 .dev_stop = bnxt_dev_stop_op,
3574 .dev_set_link_up = bnxt_dev_set_link_up_op,
3575 .dev_set_link_down = bnxt_dev_set_link_down_op,
3576 .stats_get = bnxt_stats_get_op,
3577 .stats_reset = bnxt_stats_reset_op,
3578 .rx_queue_setup = bnxt_rx_queue_setup_op,
3579 .rx_queue_release = bnxt_rx_queue_release_op,
3580 .tx_queue_setup = bnxt_tx_queue_setup_op,
3581 .tx_queue_release = bnxt_tx_queue_release_op,
3582 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3583 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3584 .reta_update = bnxt_reta_update_op,
3585 .reta_query = bnxt_reta_query_op,
3586 .rss_hash_update = bnxt_rss_hash_update_op,
3587 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3588 .link_update = bnxt_link_update_op,
3589 .promiscuous_enable = bnxt_promiscuous_enable_op,
3590 .promiscuous_disable = bnxt_promiscuous_disable_op,
3591 .allmulticast_enable = bnxt_allmulticast_enable_op,
3592 .allmulticast_disable = bnxt_allmulticast_disable_op,
3593 .mac_addr_add = bnxt_mac_addr_add_op,
3594 .mac_addr_remove = bnxt_mac_addr_remove_op,
3595 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3596 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3597 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3598 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3599 .vlan_filter_set = bnxt_vlan_filter_set_op,
3600 .vlan_offload_set = bnxt_vlan_offload_set_op,
3601 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3602 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3603 .mtu_set = bnxt_mtu_set_op,
3604 .mac_addr_set = bnxt_set_default_mac_addr_op,
3605 .xstats_get = bnxt_dev_xstats_get_op,
3606 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3607 .xstats_reset = bnxt_dev_xstats_reset_op,
3608 .fw_version_get = bnxt_fw_version_get,
3609 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3610 .rxq_info_get = bnxt_rxq_info_get_op,
3611 .txq_info_get = bnxt_txq_info_get_op,
3612 .dev_led_on = bnxt_dev_led_on_op,
3613 .dev_led_off = bnxt_dev_led_off_op,
3614 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3615 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3616 .rx_queue_count = bnxt_rx_queue_count_op,
3617 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3618 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3619 .rx_queue_start = bnxt_rx_queue_start,
3620 .rx_queue_stop = bnxt_rx_queue_stop,
3621 .tx_queue_start = bnxt_tx_queue_start,
3622 .tx_queue_stop = bnxt_tx_queue_stop,
3623 .filter_ctrl = bnxt_filter_ctrl_op,
3624 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3625 .get_eeprom_length = bnxt_get_eeprom_length_op,
3626 .get_eeprom = bnxt_get_eeprom_op,
3627 .set_eeprom = bnxt_set_eeprom_op,
3628 .timesync_enable = bnxt_timesync_enable,
3629 .timesync_disable = bnxt_timesync_disable,
3630 .timesync_read_time = bnxt_timesync_read_time,
3631 .timesync_write_time = bnxt_timesync_write_time,
3632 .timesync_adjust_time = bnxt_timesync_adjust_time,
3633 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3634 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3637 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3641 /* Only pre-map the reset GRC registers using window 3 */
3642 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3643 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3645 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3650 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3652 struct bnxt_error_recovery_info *info = bp->recovery_info;
3653 uint32_t reg_base = 0xffffffff;
3656 /* Only pre-map the monitoring GRC registers using window 2 */
3657 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3658 uint32_t reg = info->status_regs[i];
3660 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3663 if (reg_base == 0xffffffff)
3664 reg_base = reg & 0xfffff000;
3665 if ((reg & 0xfffff000) != reg_base)
3668 /* Use mask 0xffc as the Lower 2 bits indicates
3669 * address space location
3671 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3675 if (reg_base == 0xffffffff)
3678 rte_write32(reg_base, (uint8_t *)bp->bar0 +
3679 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3684 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3686 struct bnxt_error_recovery_info *info = bp->recovery_info;
3687 uint32_t delay = info->delay_after_reset[index];
3688 uint32_t val = info->reset_reg_val[index];
3689 uint32_t reg = info->reset_reg[index];
3690 uint32_t type, offset;
3692 type = BNXT_FW_STATUS_REG_TYPE(reg);
3693 offset = BNXT_FW_STATUS_REG_OFF(reg);
3696 case BNXT_FW_STATUS_REG_TYPE_CFG:
3697 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3699 case BNXT_FW_STATUS_REG_TYPE_GRC:
3700 offset = bnxt_map_reset_regs(bp, offset);
3701 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3703 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3704 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3707 /* wait on a specific interval of time until core reset is complete */
3709 rte_delay_ms(delay);
3712 static void bnxt_dev_cleanup(struct bnxt *bp)
3714 bnxt_set_hwrm_link_config(bp, false);
3715 bp->link_info.link_up = 0;
3716 if (bp->dev_stopped == 0)
3717 bnxt_dev_stop_op(bp->eth_dev);
3719 bnxt_uninit_resources(bp, true);
3722 static int bnxt_restore_filters(struct bnxt *bp)
3724 struct rte_eth_dev *dev = bp->eth_dev;
3727 if (dev->data->all_multicast)
3728 ret = bnxt_allmulticast_enable_op(dev);
3729 if (dev->data->promiscuous)
3730 ret = bnxt_promiscuous_enable_op(dev);
3732 /* TODO restore other filters as well */
3736 static void bnxt_dev_recover(void *arg)
3738 struct bnxt *bp = arg;
3739 int timeout = bp->fw_reset_max_msecs;
3742 /* Clear Error flag so that device re-init should happen */
3743 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3746 rc = bnxt_hwrm_ver_get(bp);
3749 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3750 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3751 } while (rc && timeout);
3754 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3758 rc = bnxt_init_resources(bp, true);
3761 "Failed to initialize resources after reset\n");
3764 /* clear reset flag as the device is initialized now */
3765 bp->flags &= ~BNXT_FLAG_FW_RESET;
3767 rc = bnxt_dev_start_op(bp->eth_dev);
3769 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3773 rc = bnxt_restore_filters(bp);
3777 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3780 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3781 bnxt_uninit_resources(bp, false);
3782 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3785 void bnxt_dev_reset_and_resume(void *arg)
3787 struct bnxt *bp = arg;
3790 bnxt_dev_cleanup(bp);
3792 bnxt_wait_for_device_shutdown(bp);
3794 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3795 bnxt_dev_recover, (void *)bp);
3797 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3800 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3802 struct bnxt_error_recovery_info *info = bp->recovery_info;
3803 uint32_t reg = info->status_regs[index];
3804 uint32_t type, offset, val = 0;
3806 type = BNXT_FW_STATUS_REG_TYPE(reg);
3807 offset = BNXT_FW_STATUS_REG_OFF(reg);
3810 case BNXT_FW_STATUS_REG_TYPE_CFG:
3811 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3813 case BNXT_FW_STATUS_REG_TYPE_GRC:
3814 offset = info->mapped_status_regs[index];
3816 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3817 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3825 static int bnxt_fw_reset_all(struct bnxt *bp)
3827 struct bnxt_error_recovery_info *info = bp->recovery_info;
3831 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3832 /* Reset through master function driver */
3833 for (i = 0; i < info->reg_array_cnt; i++)
3834 bnxt_write_fw_reset_reg(bp, i);
3835 /* Wait for time specified by FW after triggering reset */
3836 rte_delay_ms(info->master_func_wait_period_after_reset);
3837 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3838 /* Reset with the help of Kong processor */
3839 rc = bnxt_hwrm_fw_reset(bp);
3841 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3847 static void bnxt_fw_reset_cb(void *arg)
3849 struct bnxt *bp = arg;
3850 struct bnxt_error_recovery_info *info = bp->recovery_info;
3853 /* Only Master function can do FW reset */
3854 if (bnxt_is_master_func(bp) &&
3855 bnxt_is_recovery_enabled(bp)) {
3856 rc = bnxt_fw_reset_all(bp);
3858 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3863 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3864 * EXCEPTION_FATAL_ASYNC event to all the functions
3865 * (including MASTER FUNC). After receiving this Async, all the active
3866 * drivers should treat this case as FW initiated recovery
3868 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3869 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3870 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3872 /* To recover from error */
3873 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3878 /* Driver should poll FW heartbeat, reset_counter with the frequency
3879 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3880 * When the driver detects heartbeat stop or change in reset_counter,
3881 * it has to trigger a reset to recover from the error condition.
3882 * A “master PF” is the function who will have the privilege to
3883 * initiate the chimp reset. The master PF will be elected by the
3884 * firmware and will be notified through async message.
3886 static void bnxt_check_fw_health(void *arg)
3888 struct bnxt *bp = arg;
3889 struct bnxt_error_recovery_info *info = bp->recovery_info;
3890 uint32_t val = 0, wait_msec;
3892 if (!info || !bnxt_is_recovery_enabled(bp) ||
3893 is_bnxt_in_error(bp))
3896 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3897 if (val == info->last_heart_beat)
3900 info->last_heart_beat = val;
3902 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3903 if (val != info->last_reset_counter)
3906 info->last_reset_counter = val;
3908 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3909 bnxt_check_fw_health, (void *)bp);
3913 /* Stop DMA to/from device */
3914 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3915 bp->flags |= BNXT_FLAG_FW_RESET;
3917 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
3919 if (bnxt_is_master_func(bp))
3920 wait_msec = info->master_func_wait_period;
3922 wait_msec = info->normal_func_wait_period;
3924 rte_eal_alarm_set(US_PER_MS * wait_msec,
3925 bnxt_fw_reset_cb, (void *)bp);
3928 void bnxt_schedule_fw_health_check(struct bnxt *bp)
3930 uint32_t polling_freq;
3932 if (!bnxt_is_recovery_enabled(bp))
3935 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
3938 polling_freq = bp->recovery_info->driver_polling_freq;
3940 rte_eal_alarm_set(US_PER_MS * polling_freq,
3941 bnxt_check_fw_health, (void *)bp);
3942 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3945 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
3947 if (!bnxt_is_recovery_enabled(bp))
3950 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
3951 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3954 static bool bnxt_vf_pciid(uint16_t id)
3956 if (id == BROADCOM_DEV_ID_57304_VF ||
3957 id == BROADCOM_DEV_ID_57406_VF ||
3958 id == BROADCOM_DEV_ID_5731X_VF ||
3959 id == BROADCOM_DEV_ID_5741X_VF ||
3960 id == BROADCOM_DEV_ID_57414_VF ||
3961 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3962 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3963 id == BROADCOM_DEV_ID_58802_VF ||
3964 id == BROADCOM_DEV_ID_57500_VF1 ||
3965 id == BROADCOM_DEV_ID_57500_VF2)
3970 bool bnxt_stratus_device(struct bnxt *bp)
3972 uint16_t id = bp->pdev->id.device_id;
3974 if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3975 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3976 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3981 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3983 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3984 struct bnxt *bp = eth_dev->data->dev_private;
3986 /* enable device (incl. PCI PM wakeup), and bus-mastering */
3987 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3988 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3989 if (!bp->bar0 || !bp->doorbell_base) {
3990 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
3994 bp->eth_dev = eth_dev;
4000 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
4001 struct bnxt_ctx_pg_info *ctx_pg,
4006 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4007 const struct rte_memzone *mz = NULL;
4008 char mz_name[RTE_MEMZONE_NAMESIZE];
4009 rte_iova_t mz_phys_addr;
4010 uint64_t valid_bits = 0;
4017 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4019 rmem->page_size = BNXT_PAGE_SIZE;
4020 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4021 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4022 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4024 valid_bits = PTU_PTE_VALID;
4026 if (rmem->nr_pages > 1) {
4027 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4028 "bnxt_ctx_pg_tbl%s_%x_%d",
4029 suffix, idx, bp->eth_dev->data->port_id);
4030 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4031 mz = rte_memzone_lookup(mz_name);
4033 mz = rte_memzone_reserve_aligned(mz_name,
4037 RTE_MEMZONE_SIZE_HINT_ONLY |
4038 RTE_MEMZONE_IOVA_CONTIG,
4044 memset(mz->addr, 0, mz->len);
4045 mz_phys_addr = mz->iova;
4046 if ((unsigned long)mz->addr == mz_phys_addr) {
4048 "physical address same as virtual\n");
4049 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4050 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4051 if (mz_phys_addr == RTE_BAD_IOVA) {
4053 "unable to map addr to phys memory\n");
4057 rte_mem_lock_page(((char *)mz->addr));
4059 rmem->pg_tbl = mz->addr;
4060 rmem->pg_tbl_map = mz_phys_addr;
4061 rmem->pg_tbl_mz = mz;
4064 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4065 suffix, idx, bp->eth_dev->data->port_id);
4066 mz = rte_memzone_lookup(mz_name);
4068 mz = rte_memzone_reserve_aligned(mz_name,
4072 RTE_MEMZONE_SIZE_HINT_ONLY |
4073 RTE_MEMZONE_IOVA_CONTIG,
4079 memset(mz->addr, 0, mz->len);
4080 mz_phys_addr = mz->iova;
4081 if ((unsigned long)mz->addr == mz_phys_addr) {
4083 "Memzone physical address same as virtual.\n");
4084 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4085 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
4086 rte_mem_lock_page(((char *)mz->addr) + sz);
4087 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4088 if (mz_phys_addr == RTE_BAD_IOVA) {
4090 "unable to map addr to phys memory\n");
4095 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4096 rte_mem_lock_page(((char *)mz->addr) + sz);
4097 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4098 rmem->dma_arr[i] = mz_phys_addr + sz;
4100 if (rmem->nr_pages > 1) {
4101 if (i == rmem->nr_pages - 2 &&
4102 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4103 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4104 else if (i == rmem->nr_pages - 1 &&
4105 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4106 valid_bits |= PTU_PTE_LAST;
4108 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4114 if (rmem->vmem_size)
4115 rmem->vmem = (void **)mz->addr;
4116 rmem->dma_arr[0] = mz_phys_addr;
4120 static void bnxt_free_ctx_mem(struct bnxt *bp)
4124 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4127 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4128 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4129 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4130 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4131 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4132 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4133 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4134 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4135 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4136 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4137 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4139 for (i = 0; i < BNXT_MAX_Q; i++) {
4140 if (bp->ctx->tqm_mem[i])
4141 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4148 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4150 #define min_t(type, x, y) ({ \
4151 type __min1 = (x); \
4152 type __min2 = (y); \
4153 __min1 < __min2 ? __min1 : __min2; })
4155 #define max_t(type, x, y) ({ \
4156 type __max1 = (x); \
4157 type __max2 = (y); \
4158 __max1 > __max2 ? __max1 : __max2; })
4160 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4162 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4164 struct bnxt_ctx_pg_info *ctx_pg;
4165 struct bnxt_ctx_mem_info *ctx;
4166 uint32_t mem_size, ena, entries;
4169 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4171 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4175 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4178 ctx_pg = &ctx->qp_mem;
4179 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4180 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4181 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4185 ctx_pg = &ctx->srq_mem;
4186 ctx_pg->entries = ctx->srq_max_l2_entries;
4187 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4188 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4192 ctx_pg = &ctx->cq_mem;
4193 ctx_pg->entries = ctx->cq_max_l2_entries;
4194 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4195 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4199 ctx_pg = &ctx->vnic_mem;
4200 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4201 ctx->vnic_max_ring_table_entries;
4202 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4203 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4207 ctx_pg = &ctx->stat_mem;
4208 ctx_pg->entries = ctx->stat_max_entries;
4209 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4210 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4214 entries = ctx->qp_max_l2_entries;
4215 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4216 entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4217 ctx->tqm_max_entries_per_ring);
4218 for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4219 ctx_pg = ctx->tqm_mem[i];
4220 /* use min tqm entries for now. */
4221 ctx_pg->entries = entries;
4222 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4223 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4226 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4229 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4230 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4233 "Failed to configure context mem: rc = %d\n", rc);
4235 ctx->flags |= BNXT_CTX_FLAG_INITED;
4240 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4242 struct rte_pci_device *pci_dev = bp->pdev;
4243 char mz_name[RTE_MEMZONE_NAMESIZE];
4244 const struct rte_memzone *mz = NULL;
4245 uint32_t total_alloc_len;
4246 rte_iova_t mz_phys_addr;
4248 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4251 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4252 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4253 pci_dev->addr.bus, pci_dev->addr.devid,
4254 pci_dev->addr.function, "rx_port_stats");
4255 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4256 mz = rte_memzone_lookup(mz_name);
4258 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4259 sizeof(struct rx_port_stats_ext) + 512);
4261 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4264 RTE_MEMZONE_SIZE_HINT_ONLY |
4265 RTE_MEMZONE_IOVA_CONTIG);
4269 memset(mz->addr, 0, mz->len);
4270 mz_phys_addr = mz->iova;
4271 if ((unsigned long)mz->addr == mz_phys_addr) {
4273 "Memzone physical address same as virtual.\n");
4275 "Using rte_mem_virt2iova()\n");
4276 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4277 if (mz_phys_addr == RTE_BAD_IOVA) {
4279 "Can't map address to physical memory\n");
4284 bp->rx_mem_zone = (const void *)mz;
4285 bp->hw_rx_port_stats = mz->addr;
4286 bp->hw_rx_port_stats_map = mz_phys_addr;
4288 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4289 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4290 pci_dev->addr.bus, pci_dev->addr.devid,
4291 pci_dev->addr.function, "tx_port_stats");
4292 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4293 mz = rte_memzone_lookup(mz_name);
4295 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4296 sizeof(struct tx_port_stats_ext) + 512);
4298 mz = rte_memzone_reserve(mz_name,
4302 RTE_MEMZONE_SIZE_HINT_ONLY |
4303 RTE_MEMZONE_IOVA_CONTIG);
4307 memset(mz->addr, 0, mz->len);
4308 mz_phys_addr = mz->iova;
4309 if ((unsigned long)mz->addr == mz_phys_addr) {
4311 "Memzone physical address same as virtual\n");
4312 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4313 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4314 if (mz_phys_addr == RTE_BAD_IOVA) {
4316 "Can't map address to physical memory\n");
4321 bp->tx_mem_zone = (const void *)mz;
4322 bp->hw_tx_port_stats = mz->addr;
4323 bp->hw_tx_port_stats_map = mz_phys_addr;
4324 bp->flags |= BNXT_FLAG_PORT_STATS;
4326 /* Display extended statistics if FW supports it */
4327 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4328 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4329 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4332 bp->hw_rx_port_stats_ext = (void *)
4333 ((uint8_t *)bp->hw_rx_port_stats +
4334 sizeof(struct rx_port_stats));
4335 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4336 sizeof(struct rx_port_stats);
4337 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4339 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4340 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4341 bp->hw_tx_port_stats_ext = (void *)
4342 ((uint8_t *)bp->hw_tx_port_stats +
4343 sizeof(struct tx_port_stats));
4344 bp->hw_tx_port_stats_ext_map =
4345 bp->hw_tx_port_stats_map +
4346 sizeof(struct tx_port_stats);
4347 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4353 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4355 struct bnxt *bp = eth_dev->data->dev_private;
4358 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4359 RTE_ETHER_ADDR_LEN *
4362 if (eth_dev->data->mac_addrs == NULL) {
4363 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4367 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4371 /* Generate a random MAC address, if none was assigned by PF */
4372 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4373 bnxt_eth_hw_addr_random(bp->mac_addr);
4375 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4376 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4377 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4379 rc = bnxt_hwrm_set_mac(bp);
4381 memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4382 RTE_ETHER_ADDR_LEN);
4386 /* Copy the permanent MAC from the FUNC_QCAPS response */
4387 memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4388 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4393 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4397 /* MAC is already configured in FW */
4398 if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4401 /* Restore the old MAC configured */
4402 rc = bnxt_hwrm_set_mac(bp);
4404 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4409 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4414 #define ALLOW_FUNC(x) \
4416 uint32_t arg = (x); \
4417 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4418 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4421 /* Forward all requests if firmware is new enough */
4422 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4423 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4424 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4425 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4427 PMD_DRV_LOG(WARNING,
4428 "Firmware too old for VF mailbox functionality\n");
4429 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4433 * The following are used for driver cleanup. If we disallow these,
4434 * VF drivers can't clean up cleanly.
4436 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4437 ALLOW_FUNC(HWRM_VNIC_FREE);
4438 ALLOW_FUNC(HWRM_RING_FREE);
4439 ALLOW_FUNC(HWRM_RING_GRP_FREE);
4440 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4441 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4442 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4443 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4444 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4447 static int bnxt_init_fw(struct bnxt *bp)
4452 rc = bnxt_hwrm_ver_get(bp);
4456 rc = bnxt_hwrm_func_reset(bp);
4460 rc = bnxt_hwrm_queue_qportcfg(bp);
4464 /* Get the MAX capabilities for this function */
4465 rc = bnxt_hwrm_func_qcaps(bp);
4469 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4473 /* Get the adapter error recovery support info */
4474 rc = bnxt_hwrm_error_recovery_qcfg(bp);
4476 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
4478 if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
4479 mtu != bp->eth_dev->data->mtu)
4480 bp->eth_dev->data->mtu = mtu;
4482 bnxt_hwrm_port_led_qcaps(bp);
4487 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4491 rc = bnxt_init_fw(bp);
4495 if (!reconfig_dev) {
4496 rc = bnxt_setup_mac_addr(bp->eth_dev);
4500 rc = bnxt_restore_dflt_mac(bp);
4505 bnxt_config_vf_req_fwd(bp);
4507 rc = bnxt_hwrm_func_driver_register(bp);
4509 PMD_DRV_LOG(ERR, "Failed to register driver");
4514 if (bp->pdev->max_vfs) {
4515 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4517 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4521 rc = bnxt_hwrm_allocate_pf_only(bp);
4524 "Failed to allocate PF resources");
4530 rc = bnxt_alloc_mem(bp, reconfig_dev);
4534 rc = bnxt_setup_int(bp);
4540 rc = bnxt_request_int(bp);
4548 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4550 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4551 static int version_printed;
4555 if (version_printed++ == 0)
4556 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4558 eth_dev->dev_ops = &bnxt_dev_ops;
4559 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4560 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4563 * For secondary processes, we don't initialise any further
4564 * as primary has already done this work.
4566 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4569 rte_eth_copy_pci_info(eth_dev, pci_dev);
4571 bp = eth_dev->data->dev_private;
4573 bp->dev_stopped = 1;
4575 if (bnxt_vf_pciid(pci_dev->id.device_id))
4576 bp->flags |= BNXT_FLAG_VF;
4578 if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
4579 pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
4580 pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
4581 pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 ||
4582 pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2)
4583 bp->flags |= BNXT_FLAG_THOR_CHIP;
4585 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4586 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4587 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4588 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4589 bp->flags |= BNXT_FLAG_STINGRAY;
4591 rc = bnxt_init_board(eth_dev);
4594 "Failed to initialize board rc: %x\n", rc);
4598 rc = bnxt_alloc_hwrm_resources(bp);
4601 "Failed to allocate hwrm resource rc: %x\n", rc);
4604 rc = bnxt_init_resources(bp, false);
4608 rc = bnxt_alloc_stats_mem(bp);
4613 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4614 pci_dev->mem_resource[0].phys_addr,
4615 pci_dev->mem_resource[0].addr);
4620 bnxt_dev_uninit(eth_dev);
4625 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4630 bnxt_free_mem(bp, reconfig_dev);
4631 bnxt_hwrm_func_buf_unrgtr(bp);
4632 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4633 bp->flags &= ~BNXT_FLAG_REGISTERED;
4634 bnxt_free_ctx_mem(bp);
4635 if (!reconfig_dev) {
4636 bnxt_free_hwrm_resources(bp);
4638 if (bp->recovery_info != NULL) {
4639 rte_free(bp->recovery_info);
4640 bp->recovery_info = NULL;
4644 rte_free(bp->ptp_cfg);
4650 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4652 struct bnxt *bp = eth_dev->data->dev_private;
4655 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4658 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4660 rc = bnxt_uninit_resources(bp, false);
4662 if (bp->grp_info != NULL) {
4663 rte_free(bp->grp_info);
4664 bp->grp_info = NULL;
4667 if (bp->tx_mem_zone) {
4668 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4669 bp->tx_mem_zone = NULL;
4672 if (bp->rx_mem_zone) {
4673 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4674 bp->rx_mem_zone = NULL;
4677 if (bp->dev_stopped == 0)
4678 bnxt_dev_close_op(eth_dev);
4680 rte_free(bp->pf.vf_info);
4681 eth_dev->dev_ops = NULL;
4682 eth_dev->rx_pkt_burst = NULL;
4683 eth_dev->tx_pkt_burst = NULL;
4688 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4689 struct rte_pci_device *pci_dev)
4691 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4695 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4697 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4698 return rte_eth_dev_pci_generic_remove(pci_dev,
4701 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4704 static struct rte_pci_driver bnxt_rte_pmd = {
4705 .id_table = bnxt_pci_id_map,
4706 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4707 .probe = bnxt_pci_probe,
4708 .remove = bnxt_pci_remove,
4712 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4714 if (strcmp(dev->device->driver->name, drv->driver.name))
4720 bool is_bnxt_supported(struct rte_eth_dev *dev)
4722 return is_device_supported(dev, &bnxt_rte_pmd);
4725 RTE_INIT(bnxt_init_log)
4727 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4728 if (bnxt_logtype_driver >= 0)
4729 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4732 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4733 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4734 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");