1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
20 #include "bnxt_ring.h"
23 #include "bnxt_stats.h"
26 #include "bnxt_vnic.h"
27 #include "hsi_struct_def_dpdk.h"
28 #include "bnxt_nvm_defs.h"
29 #include "bnxt_util.h"
31 #define DRV_MODULE_NAME "bnxt"
32 static const char bnxt_version[] =
33 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
34 int bnxt_logtype_driver;
36 #define PCI_VENDOR_ID_BROADCOM 0x14E4
38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
40 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
41 #define BROADCOM_DEV_ID_57414_VF 0x16c1
42 #define BROADCOM_DEV_ID_57301 0x16c8
43 #define BROADCOM_DEV_ID_57302 0x16c9
44 #define BROADCOM_DEV_ID_57304_PF 0x16ca
45 #define BROADCOM_DEV_ID_57304_VF 0x16cb
46 #define BROADCOM_DEV_ID_57417_MF 0x16cc
47 #define BROADCOM_DEV_ID_NS2 0x16cd
48 #define BROADCOM_DEV_ID_57311 0x16ce
49 #define BROADCOM_DEV_ID_57312 0x16cf
50 #define BROADCOM_DEV_ID_57402 0x16d0
51 #define BROADCOM_DEV_ID_57404 0x16d1
52 #define BROADCOM_DEV_ID_57406_PF 0x16d2
53 #define BROADCOM_DEV_ID_57406_VF 0x16d3
54 #define BROADCOM_DEV_ID_57402_MF 0x16d4
55 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
56 #define BROADCOM_DEV_ID_57412 0x16d6
57 #define BROADCOM_DEV_ID_57414 0x16d7
58 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
59 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
60 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
61 #define BROADCOM_DEV_ID_57412_MF 0x16de
62 #define BROADCOM_DEV_ID_57314 0x16df
63 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
64 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
65 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
66 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
67 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
68 #define BROADCOM_DEV_ID_57404_MF 0x16e7
69 #define BROADCOM_DEV_ID_57406_MF 0x16e8
70 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
71 #define BROADCOM_DEV_ID_57407_MF 0x16ea
72 #define BROADCOM_DEV_ID_57414_MF 0x16ec
73 #define BROADCOM_DEV_ID_57416_MF 0x16ee
74 #define BROADCOM_DEV_ID_57508 0x1750
75 #define BROADCOM_DEV_ID_57504 0x1751
76 #define BROADCOM_DEV_ID_57502 0x1752
77 #define BROADCOM_DEV_ID_57500_VF 0x1807
78 #define BROADCOM_DEV_ID_58802 0xd802
79 #define BROADCOM_DEV_ID_58804 0xd804
80 #define BROADCOM_DEV_ID_58808 0x16f0
81 #define BROADCOM_DEV_ID_58802_VF 0xd800
83 static const struct rte_pci_id bnxt_pci_id_map[] = {
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
85 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
87 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
98 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
122 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
123 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
124 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
125 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
126 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
127 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
128 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
129 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF) },
130 { .vendor_id = 0, /* sentinel */ },
133 #define BNXT_ETH_RSS_SUPPORT ( \
135 ETH_RSS_NONFRAG_IPV4_TCP | \
136 ETH_RSS_NONFRAG_IPV4_UDP | \
138 ETH_RSS_NONFRAG_IPV6_TCP | \
139 ETH_RSS_NONFRAG_IPV6_UDP)
141 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
142 DEV_TX_OFFLOAD_IPV4_CKSUM | \
143 DEV_TX_OFFLOAD_TCP_CKSUM | \
144 DEV_TX_OFFLOAD_UDP_CKSUM | \
145 DEV_TX_OFFLOAD_TCP_TSO | \
146 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
147 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
148 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
149 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
150 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
151 DEV_TX_OFFLOAD_MULTI_SEGS)
153 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
154 DEV_RX_OFFLOAD_VLAN_STRIP | \
155 DEV_RX_OFFLOAD_IPV4_CKSUM | \
156 DEV_RX_OFFLOAD_UDP_CKSUM | \
157 DEV_RX_OFFLOAD_TCP_CKSUM | \
158 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
159 DEV_RX_OFFLOAD_JUMBO_FRAME | \
160 DEV_RX_OFFLOAD_KEEP_CRC | \
161 DEV_RX_OFFLOAD_TCP_LRO)
163 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
164 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
165 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
166 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
168 /***********************/
171 * High level utility functions
174 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
176 if (!BNXT_CHIP_THOR(bp))
179 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
180 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
181 BNXT_RSS_ENTRIES_PER_CTX_THOR;
184 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
186 if (!BNXT_CHIP_THOR(bp))
187 return HW_HASH_INDEX_SIZE;
189 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
192 static void bnxt_free_mem(struct bnxt *bp)
194 bnxt_free_filter_mem(bp);
195 bnxt_free_vnic_attributes(bp);
196 bnxt_free_vnic_mem(bp);
199 bnxt_free_tx_rings(bp);
200 bnxt_free_rx_rings(bp);
203 static int bnxt_alloc_mem(struct bnxt *bp)
207 rc = bnxt_alloc_vnic_mem(bp);
211 rc = bnxt_alloc_vnic_attributes(bp);
215 rc = bnxt_alloc_filter_mem(bp);
226 static int bnxt_init_chip(struct bnxt *bp)
228 struct bnxt_rx_queue *rxq;
229 struct rte_eth_link new;
230 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
231 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
232 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
233 uint64_t rx_offloads = dev_conf->rxmode.offloads;
234 uint32_t intr_vector = 0;
235 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
236 uint32_t vec = BNXT_MISC_VEC_ID;
240 /* disable uio/vfio intr/eventfd mapping */
241 rte_intr_disable(intr_handle);
243 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
244 bp->eth_dev->data->dev_conf.rxmode.offloads |=
245 DEV_RX_OFFLOAD_JUMBO_FRAME;
246 bp->flags |= BNXT_FLAG_JUMBO;
248 bp->eth_dev->data->dev_conf.rxmode.offloads &=
249 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
250 bp->flags &= ~BNXT_FLAG_JUMBO;
253 /* THOR does not support ring groups.
254 * But we will use the array to save RSS context IDs.
256 if (BNXT_CHIP_THOR(bp))
257 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
259 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
261 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
265 rc = bnxt_alloc_hwrm_rings(bp);
267 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
271 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
273 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
277 rc = bnxt_mq_rx_configure(bp);
279 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
283 /* VNIC configuration */
284 for (i = 0; i < bp->nr_vnics; i++) {
285 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
286 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
287 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
289 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
290 if (!vnic->fw_grp_ids) {
292 "Failed to alloc %d bytes for group ids\n",
297 memset(vnic->fw_grp_ids, -1, size);
299 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
300 i, vnic, vnic->fw_grp_ids);
302 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
304 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
309 /* Alloc RSS context only if RSS mode is enabled */
310 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
311 int j, nr_ctxs = bnxt_rss_ctxts(bp);
314 for (j = 0; j < nr_ctxs; j++) {
315 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
321 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
325 vnic->num_lb_ctxts = nr_ctxs;
329 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
330 * setting is not available at this time, it will not be
331 * configured correctly in the CFA.
333 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
334 vnic->vlan_strip = true;
336 vnic->vlan_strip = false;
338 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
340 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
345 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
348 "HWRM vnic %d filter failure rc: %x\n",
353 for (j = 0; j < bp->rx_nr_rings; j++) {
354 rxq = bp->eth_dev->data->rx_queues[j];
357 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
358 j, rxq->vnic, rxq->vnic->fw_grp_ids);
360 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
361 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
364 rc = bnxt_vnic_rss_configure(bp, vnic);
367 "HWRM vnic set RSS failure rc: %x\n", rc);
371 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
373 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
374 DEV_RX_OFFLOAD_TCP_LRO)
375 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
377 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
379 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
382 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
386 /* check and configure queue intr-vector mapping */
387 if ((rte_intr_cap_multiple(intr_handle) ||
388 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
389 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
390 intr_vector = bp->eth_dev->data->nb_rx_queues;
391 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
392 if (intr_vector > bp->rx_cp_nr_rings) {
393 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
397 if (rte_intr_efd_enable(intr_handle, intr_vector))
401 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
402 intr_handle->intr_vec =
403 rte_zmalloc("intr_vec",
404 bp->eth_dev->data->nb_rx_queues *
406 if (intr_handle->intr_vec == NULL) {
407 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
408 " intr_vec", bp->eth_dev->data->nb_rx_queues);
411 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
412 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
413 intr_handle->intr_vec, intr_handle->nb_efd,
414 intr_handle->max_intr);
415 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
417 intr_handle->intr_vec[queue_id] = vec;
418 if (vec < base + intr_handle->nb_efd - 1)
423 /* enable uio/vfio intr/eventfd mapping */
424 rte_intr_enable(intr_handle);
426 rc = bnxt_get_hwrm_link_config(bp, &new);
428 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
432 if (!bp->link_info.link_up) {
433 rc = bnxt_set_hwrm_link_config(bp, true);
436 "HWRM link config failure rc: %x\n", rc);
440 bnxt_print_link_info(bp->eth_dev);
445 bnxt_free_all_hwrm_resources(bp);
447 /* Some of the error status returned by FW may not be from errno.h */
454 static int bnxt_shutdown_nic(struct bnxt *bp)
456 bnxt_free_all_hwrm_resources(bp);
457 bnxt_free_all_filters(bp);
458 bnxt_free_all_vnics(bp);
462 static int bnxt_init_nic(struct bnxt *bp)
466 if (BNXT_HAS_RING_GRPS(bp)) {
467 rc = bnxt_init_ring_grps(bp);
473 bnxt_init_filters(bp);
479 * Device configuration and status function
482 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
483 struct rte_eth_dev_info *dev_info)
485 struct bnxt *bp = eth_dev->data->dev_private;
486 uint16_t max_vnics, i, j, vpool, vrxq;
487 unsigned int max_rx_rings;
490 dev_info->max_mac_addrs = bp->max_l2_ctx;
491 dev_info->max_hash_mac_addrs = 0;
493 /* PF/VF specifics */
495 dev_info->max_vfs = bp->pdev->max_vfs;
496 max_rx_rings = RTE_MIN(bp->max_vnics, bp->max_stat_ctx);
497 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
498 dev_info->max_rx_queues = max_rx_rings;
499 dev_info->max_tx_queues = max_rx_rings;
500 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
501 dev_info->hash_key_size = 40;
502 max_vnics = bp->max_vnics;
504 /* Fast path specifics */
505 dev_info->min_rx_bufsize = 1;
506 dev_info->max_rx_pktlen = BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +
507 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
509 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
510 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
511 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
512 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
513 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
516 dev_info->default_rxconf = (struct rte_eth_rxconf) {
522 .rx_free_thresh = 32,
523 /* If no descriptors available, pkts are dropped by default */
527 dev_info->default_txconf = (struct rte_eth_txconf) {
533 .tx_free_thresh = 32,
536 eth_dev->data->dev_conf.intr_conf.lsc = 1;
538 eth_dev->data->dev_conf.intr_conf.rxq = 1;
539 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
540 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
541 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
542 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
547 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
548 * need further investigation.
552 vpool = 64; /* ETH_64_POOLS */
553 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
554 for (i = 0; i < 4; vpool >>= 1, i++) {
555 if (max_vnics > vpool) {
556 for (j = 0; j < 5; vrxq >>= 1, j++) {
557 if (dev_info->max_rx_queues > vrxq) {
563 /* Not enough resources to support VMDq */
567 /* Not enough resources to support VMDq */
571 dev_info->max_vmdq_pools = vpool;
572 dev_info->vmdq_queue_num = vrxq;
574 dev_info->vmdq_pool_base = 0;
575 dev_info->vmdq_queue_base = 0;
578 /* Configure the device based on the configuration provided */
579 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
581 struct bnxt *bp = eth_dev->data->dev_private;
582 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
585 bp->rx_queues = (void *)eth_dev->data->rx_queues;
586 bp->tx_queues = (void *)eth_dev->data->tx_queues;
587 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
588 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
590 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
591 rc = bnxt_hwrm_check_vf_rings(bp);
593 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
597 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
599 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
603 /* legacy driver needs to get updated values */
604 rc = bnxt_hwrm_func_qcaps(bp);
606 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
611 /* Inherit new configurations */
612 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
613 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
614 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
616 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
620 if (BNXT_HAS_RING_GRPS(bp) &&
621 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
624 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
625 bp->max_vnics < eth_dev->data->nb_rx_queues)
628 bp->rx_cp_nr_rings = bp->rx_nr_rings;
629 bp->tx_cp_nr_rings = bp->tx_nr_rings;
631 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
633 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
634 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
636 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
642 "Insufficient resources to support requested config\n");
644 "Num Queues Requested: Tx %d, Rx %d\n",
645 eth_dev->data->nb_tx_queues,
646 eth_dev->data->nb_rx_queues);
648 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
649 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
650 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
654 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
656 struct rte_eth_link *link = ð_dev->data->dev_link;
658 if (link->link_status)
659 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
660 eth_dev->data->port_id,
661 (uint32_t)link->link_speed,
662 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
663 ("full-duplex") : ("half-duplex\n"));
665 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
666 eth_dev->data->port_id);
670 * Determine whether the current configuration requires support for scattered
671 * receive; return 1 if scattered receive is required and 0 if not.
673 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
678 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
679 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
681 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
682 RTE_PKTMBUF_HEADROOM);
683 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
689 static eth_rx_burst_t
690 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
694 * Vector mode receive can be enabled only if scatter rx is not
695 * in use and rx offloads are limited to VLAN stripping and
698 if (!eth_dev->data->scattered_rx &&
699 !(eth_dev->data->dev_conf.rxmode.offloads &
700 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
701 DEV_RX_OFFLOAD_KEEP_CRC |
702 DEV_RX_OFFLOAD_JUMBO_FRAME |
703 DEV_RX_OFFLOAD_IPV4_CKSUM |
704 DEV_RX_OFFLOAD_UDP_CKSUM |
705 DEV_RX_OFFLOAD_TCP_CKSUM |
706 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
707 DEV_RX_OFFLOAD_VLAN_FILTER))) {
708 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
709 eth_dev->data->port_id);
710 return bnxt_recv_pkts_vec;
712 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
713 eth_dev->data->port_id);
715 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
716 eth_dev->data->port_id,
717 eth_dev->data->scattered_rx,
718 eth_dev->data->dev_conf.rxmode.offloads);
720 return bnxt_recv_pkts;
723 static eth_tx_burst_t
724 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
728 * Vector mode receive can be enabled only if scatter tx is not
729 * in use and tx offloads other than VLAN insertion are not
732 if (!eth_dev->data->scattered_rx &&
733 !(eth_dev->data->dev_conf.txmode.offloads &
734 ~DEV_TX_OFFLOAD_VLAN_INSERT)) {
735 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
736 eth_dev->data->port_id);
737 return bnxt_xmit_pkts_vec;
739 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
740 eth_dev->data->port_id);
742 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
743 eth_dev->data->port_id,
744 eth_dev->data->scattered_rx,
745 eth_dev->data->dev_conf.txmode.offloads);
747 return bnxt_xmit_pkts;
750 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
752 struct bnxt *bp = eth_dev->data->dev_private;
753 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
757 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
759 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
760 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
764 rc = bnxt_init_chip(bp);
768 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
770 bnxt_link_update_op(eth_dev, 1);
772 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
773 vlan_mask |= ETH_VLAN_FILTER_MASK;
774 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
775 vlan_mask |= ETH_VLAN_STRIP_MASK;
776 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
780 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
781 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
782 bp->flags |= BNXT_FLAG_INIT_DONE;
786 bnxt_shutdown_nic(bp);
787 bnxt_free_tx_mbufs(bp);
788 bnxt_free_rx_mbufs(bp);
792 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
794 struct bnxt *bp = eth_dev->data->dev_private;
797 if (!bp->link_info.link_up)
798 rc = bnxt_set_hwrm_link_config(bp, true);
800 eth_dev->data->dev_link.link_status = 1;
802 bnxt_print_link_info(eth_dev);
806 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
808 struct bnxt *bp = eth_dev->data->dev_private;
810 eth_dev->data->dev_link.link_status = 0;
811 bnxt_set_hwrm_link_config(bp, false);
812 bp->link_info.link_up = 0;
817 /* Unload the driver, release resources */
818 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
820 struct bnxt *bp = eth_dev->data->dev_private;
822 bp->flags &= ~BNXT_FLAG_INIT_DONE;
823 if (bp->eth_dev->data->dev_started) {
824 /* TBD: STOP HW queues DMA */
825 eth_dev->data->dev_link.link_status = 0;
827 bnxt_set_hwrm_link_config(bp, false);
828 bnxt_hwrm_port_clr_stats(bp);
829 bnxt_free_tx_mbufs(bp);
830 bnxt_free_rx_mbufs(bp);
831 bnxt_shutdown_nic(bp);
835 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
837 struct bnxt *bp = eth_dev->data->dev_private;
839 if (bp->dev_stopped == 0)
840 bnxt_dev_stop_op(eth_dev);
842 if (eth_dev->data->mac_addrs != NULL) {
843 rte_free(eth_dev->data->mac_addrs);
844 eth_dev->data->mac_addrs = NULL;
846 if (bp->grp_info != NULL) {
847 rte_free(bp->grp_info);
851 bnxt_dev_uninit(eth_dev);
854 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
857 struct bnxt *bp = eth_dev->data->dev_private;
858 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
859 struct bnxt_vnic_info *vnic;
860 struct bnxt_filter_info *filter, *temp_filter;
864 * Loop through all VNICs from the specified filter flow pools to
865 * remove the corresponding MAC addr filter
867 for (i = 0; i < bp->nr_vnics; i++) {
868 if (!(pool_mask & (1ULL << i)))
871 vnic = &bp->vnic_info[i];
872 filter = STAILQ_FIRST(&vnic->filter);
874 temp_filter = STAILQ_NEXT(filter, next);
875 if (filter->mac_index == index) {
876 STAILQ_REMOVE(&vnic->filter, filter,
877 bnxt_filter_info, next);
878 bnxt_hwrm_clear_l2_filter(bp, filter);
879 filter->mac_index = INVALID_MAC_INDEX;
880 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
881 STAILQ_INSERT_TAIL(&bp->free_filter_list,
884 filter = temp_filter;
889 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
890 struct rte_ether_addr *mac_addr,
891 uint32_t index, uint32_t pool)
893 struct bnxt *bp = eth_dev->data->dev_private;
894 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
895 struct bnxt_filter_info *filter;
897 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
898 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
903 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
906 /* Attach requested MAC address to the new l2_filter */
907 STAILQ_FOREACH(filter, &vnic->filter, next) {
908 if (filter->mac_index == index) {
910 "MAC addr already existed for pool %d\n", pool);
914 filter = bnxt_alloc_filter(bp);
916 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
919 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
920 filter->mac_index = index;
921 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
922 return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
925 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
928 struct bnxt *bp = eth_dev->data->dev_private;
929 struct rte_eth_link new;
930 unsigned int cnt = BNXT_LINK_WAIT_CNT;
932 memset(&new, 0, sizeof(new));
934 /* Retrieve link info from hardware */
935 rc = bnxt_get_hwrm_link_config(bp, &new);
937 new.link_speed = ETH_LINK_SPEED_100M;
938 new.link_duplex = ETH_LINK_FULL_DUPLEX;
940 "Failed to retrieve link rc = 0x%x!\n", rc);
943 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
945 if (!wait_to_complete)
947 } while (!new.link_status && cnt--);
950 /* Timed out or success */
951 if (new.link_status != eth_dev->data->dev_link.link_status ||
952 new.link_speed != eth_dev->data->dev_link.link_speed) {
953 memcpy(ð_dev->data->dev_link, &new,
954 sizeof(struct rte_eth_link));
956 _rte_eth_dev_callback_process(eth_dev,
957 RTE_ETH_EVENT_INTR_LSC,
960 bnxt_print_link_info(eth_dev);
966 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
968 struct bnxt *bp = eth_dev->data->dev_private;
969 struct bnxt_vnic_info *vnic;
971 if (bp->vnic_info == NULL)
974 vnic = &bp->vnic_info[0];
976 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
977 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
980 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
982 struct bnxt *bp = eth_dev->data->dev_private;
983 struct bnxt_vnic_info *vnic;
985 if (bp->vnic_info == NULL)
988 vnic = &bp->vnic_info[0];
990 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
991 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
994 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
996 struct bnxt *bp = eth_dev->data->dev_private;
997 struct bnxt_vnic_info *vnic;
999 if (bp->vnic_info == NULL)
1002 vnic = &bp->vnic_info[0];
1004 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1005 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1008 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1010 struct bnxt *bp = eth_dev->data->dev_private;
1011 struct bnxt_vnic_info *vnic;
1013 if (bp->vnic_info == NULL)
1016 vnic = &bp->vnic_info[0];
1018 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1019 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1022 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1023 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1025 if (qid >= bp->rx_nr_rings)
1028 return bp->eth_dev->data->rx_queues[qid];
1031 /* Return rxq corresponding to a given rss table ring/group ID. */
1032 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1034 struct bnxt_rx_queue *rxq;
1037 if (!BNXT_HAS_RING_GRPS(bp)) {
1038 for (i = 0; i < bp->rx_nr_rings; i++) {
1039 rxq = bp->eth_dev->data->rx_queues[i];
1040 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1044 for (i = 0; i < bp->rx_nr_rings; i++) {
1045 if (bp->grp_info[i].fw_grp_id == fwr)
1050 return INVALID_HW_RING_ID;
1053 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1054 struct rte_eth_rss_reta_entry64 *reta_conf,
1057 struct bnxt *bp = eth_dev->data->dev_private;
1058 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1059 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1060 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1064 if (!vnic->rss_table)
1067 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1070 if (reta_size != tbl_size) {
1071 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1072 "(%d) must equal the size supported by the hardware "
1073 "(%d)\n", reta_size, tbl_size);
1077 for (i = 0; i < reta_size; i++) {
1078 struct bnxt_rx_queue *rxq;
1080 idx = i / RTE_RETA_GROUP_SIZE;
1081 sft = i % RTE_RETA_GROUP_SIZE;
1083 if (!(reta_conf[idx].mask & (1ULL << sft)))
1086 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1088 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1092 if (BNXT_CHIP_THOR(bp)) {
1093 vnic->rss_table[i * 2] =
1094 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1095 vnic->rss_table[i * 2 + 1] =
1096 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1098 vnic->rss_table[i] =
1099 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1102 vnic->rss_table[i] =
1103 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1106 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1110 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1111 struct rte_eth_rss_reta_entry64 *reta_conf,
1114 struct bnxt *bp = eth_dev->data->dev_private;
1115 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1116 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1117 uint16_t idx, sft, i;
1119 /* Retrieve from the default VNIC */
1122 if (!vnic->rss_table)
1125 if (reta_size != tbl_size) {
1126 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1127 "(%d) must equal the size supported by the hardware "
1128 "(%d)\n", reta_size, tbl_size);
1132 for (idx = 0, i = 0; i < reta_size; i++) {
1133 idx = i / RTE_RETA_GROUP_SIZE;
1134 sft = i % RTE_RETA_GROUP_SIZE;
1136 if (reta_conf[idx].mask & (1ULL << sft)) {
1139 if (BNXT_CHIP_THOR(bp))
1140 qid = bnxt_rss_to_qid(bp,
1141 vnic->rss_table[i * 2]);
1143 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1145 if (qid == INVALID_HW_RING_ID) {
1146 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1149 reta_conf[idx].reta[sft] = qid;
1156 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1157 struct rte_eth_rss_conf *rss_conf)
1159 struct bnxt *bp = eth_dev->data->dev_private;
1160 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1161 struct bnxt_vnic_info *vnic;
1162 uint16_t hash_type = 0;
1166 * If RSS enablement were different than dev_configure,
1167 * then return -EINVAL
1169 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1170 if (!rss_conf->rss_hf)
1171 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1173 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1177 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1178 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1180 if (rss_conf->rss_hf & ETH_RSS_IPV4)
1181 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1182 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1183 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1184 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1185 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1186 if (rss_conf->rss_hf & ETH_RSS_IPV6)
1187 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1188 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1189 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1190 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1191 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1193 /* Update the RSS VNIC(s) */
1194 for (i = 0; i < bp->nr_vnics; i++) {
1195 vnic = &bp->vnic_info[i];
1196 vnic->hash_type = hash_type;
1199 * Use the supplied key if the key length is
1200 * acceptable and the rss_key is not NULL
1202 if (rss_conf->rss_key &&
1203 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1204 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
1205 rss_conf->rss_key_len);
1207 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1212 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1213 struct rte_eth_rss_conf *rss_conf)
1215 struct bnxt *bp = eth_dev->data->dev_private;
1216 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1218 uint32_t hash_types;
1220 /* RSS configuration is the same for all VNICs */
1221 if (vnic && vnic->rss_hash_key) {
1222 if (rss_conf->rss_key) {
1223 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1224 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1225 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1228 hash_types = vnic->hash_type;
1229 rss_conf->rss_hf = 0;
1230 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1231 rss_conf->rss_hf |= ETH_RSS_IPV4;
1232 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1234 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1235 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1237 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1239 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1240 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1242 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1244 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1245 rss_conf->rss_hf |= ETH_RSS_IPV6;
1246 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1248 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1249 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1251 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1253 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1254 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1256 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1260 "Unknwon RSS config from firmware (%08x), RSS disabled",
1265 rss_conf->rss_hf = 0;
1270 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1271 struct rte_eth_fc_conf *fc_conf)
1273 struct bnxt *bp = dev->data->dev_private;
1274 struct rte_eth_link link_info;
1277 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1281 memset(fc_conf, 0, sizeof(*fc_conf));
1282 if (bp->link_info.auto_pause)
1283 fc_conf->autoneg = 1;
1284 switch (bp->link_info.pause) {
1286 fc_conf->mode = RTE_FC_NONE;
1288 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1289 fc_conf->mode = RTE_FC_TX_PAUSE;
1291 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1292 fc_conf->mode = RTE_FC_RX_PAUSE;
1294 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1295 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1296 fc_conf->mode = RTE_FC_FULL;
1302 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1303 struct rte_eth_fc_conf *fc_conf)
1305 struct bnxt *bp = dev->data->dev_private;
1307 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1308 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1312 switch (fc_conf->mode) {
1314 bp->link_info.auto_pause = 0;
1315 bp->link_info.force_pause = 0;
1317 case RTE_FC_RX_PAUSE:
1318 if (fc_conf->autoneg) {
1319 bp->link_info.auto_pause =
1320 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1321 bp->link_info.force_pause = 0;
1323 bp->link_info.auto_pause = 0;
1324 bp->link_info.force_pause =
1325 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1328 case RTE_FC_TX_PAUSE:
1329 if (fc_conf->autoneg) {
1330 bp->link_info.auto_pause =
1331 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1332 bp->link_info.force_pause = 0;
1334 bp->link_info.auto_pause = 0;
1335 bp->link_info.force_pause =
1336 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1340 if (fc_conf->autoneg) {
1341 bp->link_info.auto_pause =
1342 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1343 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1344 bp->link_info.force_pause = 0;
1346 bp->link_info.auto_pause = 0;
1347 bp->link_info.force_pause =
1348 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1349 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1353 return bnxt_set_hwrm_link_config(bp, true);
1356 /* Add UDP tunneling port */
1358 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1359 struct rte_eth_udp_tunnel *udp_tunnel)
1361 struct bnxt *bp = eth_dev->data->dev_private;
1362 uint16_t tunnel_type = 0;
1365 switch (udp_tunnel->prot_type) {
1366 case RTE_TUNNEL_TYPE_VXLAN:
1367 if (bp->vxlan_port_cnt) {
1368 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1369 udp_tunnel->udp_port);
1370 if (bp->vxlan_port != udp_tunnel->udp_port) {
1371 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1374 bp->vxlan_port_cnt++;
1378 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1379 bp->vxlan_port_cnt++;
1381 case RTE_TUNNEL_TYPE_GENEVE:
1382 if (bp->geneve_port_cnt) {
1383 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1384 udp_tunnel->udp_port);
1385 if (bp->geneve_port != udp_tunnel->udp_port) {
1386 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1389 bp->geneve_port_cnt++;
1393 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1394 bp->geneve_port_cnt++;
1397 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1400 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1406 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1407 struct rte_eth_udp_tunnel *udp_tunnel)
1409 struct bnxt *bp = eth_dev->data->dev_private;
1410 uint16_t tunnel_type = 0;
1414 switch (udp_tunnel->prot_type) {
1415 case RTE_TUNNEL_TYPE_VXLAN:
1416 if (!bp->vxlan_port_cnt) {
1417 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1420 if (bp->vxlan_port != udp_tunnel->udp_port) {
1421 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1422 udp_tunnel->udp_port, bp->vxlan_port);
1425 if (--bp->vxlan_port_cnt)
1429 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1430 port = bp->vxlan_fw_dst_port_id;
1432 case RTE_TUNNEL_TYPE_GENEVE:
1433 if (!bp->geneve_port_cnt) {
1434 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1437 if (bp->geneve_port != udp_tunnel->udp_port) {
1438 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1439 udp_tunnel->udp_port, bp->geneve_port);
1442 if (--bp->geneve_port_cnt)
1446 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1447 port = bp->geneve_fw_dst_port_id;
1450 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1454 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1457 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1460 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1461 bp->geneve_port = 0;
1466 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1468 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1469 struct bnxt_vnic_info *vnic;
1472 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1474 /* Cycle through all VNICs */
1475 for (i = 0; i < bp->nr_vnics; i++) {
1477 * For each VNIC and each associated filter(s)
1478 * if VLAN exists && VLAN matches vlan_id
1479 * remove the MAC+VLAN filter
1480 * add a new MAC only filter
1482 * VLAN filter doesn't exist, just skip and continue
1484 vnic = &bp->vnic_info[i];
1485 filter = STAILQ_FIRST(&vnic->filter);
1487 temp_filter = STAILQ_NEXT(filter, next);
1489 if (filter->enables & chk &&
1490 filter->l2_ovlan == vlan_id) {
1491 /* Must delete the filter */
1492 STAILQ_REMOVE(&vnic->filter, filter,
1493 bnxt_filter_info, next);
1494 bnxt_hwrm_clear_l2_filter(bp, filter);
1495 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1499 * Need to examine to see if the MAC
1500 * filter already existed or not before
1501 * allocating a new one
1504 new_filter = bnxt_alloc_filter(bp);
1507 "MAC/VLAN filter alloc failed\n");
1511 STAILQ_INSERT_TAIL(&vnic->filter,
1513 /* Inherit MAC from previous filter */
1514 new_filter->mac_index =
1516 memcpy(new_filter->l2_addr, filter->l2_addr,
1517 RTE_ETHER_ADDR_LEN);
1518 /* MAC only filter */
1519 rc = bnxt_hwrm_set_l2_filter(bp,
1525 "Del Vlan filter for %d\n",
1528 filter = temp_filter;
1535 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1537 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1538 struct bnxt_vnic_info *vnic;
1541 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1542 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1543 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1545 /* Cycle through all VNICs */
1546 for (i = 0; i < bp->nr_vnics; i++) {
1548 * For each VNIC and each associated filter(s)
1550 * if VLAN matches vlan_id
1551 * VLAN filter already exists, just skip and continue
1553 * add a new MAC+VLAN filter
1555 * Remove the old MAC only filter
1556 * Add a new MAC+VLAN filter
1558 vnic = &bp->vnic_info[i];
1559 filter = STAILQ_FIRST(&vnic->filter);
1561 temp_filter = STAILQ_NEXT(filter, next);
1563 if (filter->enables & chk) {
1564 if (filter->l2_ivlan == vlan_id)
1567 /* Must delete the MAC filter */
1568 STAILQ_REMOVE(&vnic->filter, filter,
1569 bnxt_filter_info, next);
1570 bnxt_hwrm_clear_l2_filter(bp, filter);
1571 filter->l2_ovlan = 0;
1572 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1575 new_filter = bnxt_alloc_filter(bp);
1578 "MAC/VLAN filter alloc failed\n");
1582 STAILQ_INSERT_TAIL(&vnic->filter, new_filter, next);
1583 /* Inherit MAC from the previous filter */
1584 new_filter->mac_index = filter->mac_index;
1585 memcpy(new_filter->l2_addr, filter->l2_addr,
1586 RTE_ETHER_ADDR_LEN);
1587 /* MAC + VLAN ID filter */
1588 new_filter->l2_ivlan = vlan_id;
1589 new_filter->l2_ivlan_mask = 0xF000;
1590 new_filter->enables |= en;
1591 rc = bnxt_hwrm_set_l2_filter(bp,
1597 "Added Vlan filter for %d\n", vlan_id);
1599 filter = temp_filter;
1606 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1607 uint16_t vlan_id, int on)
1609 struct bnxt *bp = eth_dev->data->dev_private;
1611 /* These operations apply to ALL existing MAC/VLAN filters */
1613 return bnxt_add_vlan_filter(bp, vlan_id);
1615 return bnxt_del_vlan_filter(bp, vlan_id);
1619 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1621 struct bnxt *bp = dev->data->dev_private;
1622 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1625 if (mask & ETH_VLAN_FILTER_MASK) {
1626 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1627 /* Remove any VLAN filters programmed */
1628 for (i = 0; i < 4095; i++)
1629 bnxt_del_vlan_filter(bp, i);
1631 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1632 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1635 if (mask & ETH_VLAN_STRIP_MASK) {
1636 /* Enable or disable VLAN stripping */
1637 for (i = 0; i < bp->nr_vnics; i++) {
1638 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1639 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1640 vnic->vlan_strip = true;
1642 vnic->vlan_strip = false;
1643 bnxt_hwrm_vnic_cfg(bp, vnic);
1645 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1646 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1649 if (mask & ETH_VLAN_EXTEND_MASK)
1650 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1656 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1657 struct rte_ether_addr *addr)
1659 struct bnxt *bp = dev->data->dev_private;
1660 /* Default Filter is tied to VNIC 0 */
1661 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1662 struct bnxt_filter_info *filter;
1665 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1668 memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1670 STAILQ_FOREACH(filter, &vnic->filter, next) {
1671 /* Default Filter is at Index 0 */
1672 if (filter->mac_index != 0)
1674 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1677 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
1678 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1679 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1681 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1682 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1683 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1686 filter->mac_index = 0;
1687 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1694 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1695 struct rte_ether_addr *mc_addr_set,
1696 uint32_t nb_mc_addr)
1698 struct bnxt *bp = eth_dev->data->dev_private;
1699 char *mc_addr_list = (char *)mc_addr_set;
1700 struct bnxt_vnic_info *vnic;
1701 uint32_t off = 0, i = 0;
1703 vnic = &bp->vnic_info[0];
1705 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1706 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1710 /* TODO Check for Duplicate mcast addresses */
1711 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1712 for (i = 0; i < nb_mc_addr; i++) {
1713 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1714 RTE_ETHER_ADDR_LEN);
1715 off += RTE_ETHER_ADDR_LEN;
1718 vnic->mc_addr_cnt = i;
1721 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1725 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1727 struct bnxt *bp = dev->data->dev_private;
1728 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1729 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1730 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1733 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1734 fw_major, fw_minor, fw_updt);
1736 ret += 1; /* add the size of '\0' */
1737 if (fw_size < (uint32_t)ret)
1744 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1745 struct rte_eth_rxq_info *qinfo)
1747 struct bnxt_rx_queue *rxq;
1749 rxq = dev->data->rx_queues[queue_id];
1751 qinfo->mp = rxq->mb_pool;
1752 qinfo->scattered_rx = dev->data->scattered_rx;
1753 qinfo->nb_desc = rxq->nb_rx_desc;
1755 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1756 qinfo->conf.rx_drop_en = 0;
1757 qinfo->conf.rx_deferred_start = 0;
1761 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1762 struct rte_eth_txq_info *qinfo)
1764 struct bnxt_tx_queue *txq;
1766 txq = dev->data->tx_queues[queue_id];
1768 qinfo->nb_desc = txq->nb_tx_desc;
1770 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1771 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1772 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1774 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1775 qinfo->conf.tx_rs_thresh = 0;
1776 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1779 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1781 struct bnxt *bp = eth_dev->data->dev_private;
1782 struct rte_eth_dev_info dev_info;
1783 uint32_t new_pkt_size;
1787 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1788 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
1790 bnxt_dev_info_get_op(eth_dev, &dev_info);
1792 if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > BNXT_MAX_MTU) {
1793 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1794 RTE_ETHER_MIN_MTU, BNXT_MAX_MTU);
1800 * If vector-mode tx/rx is active, disallow any MTU change that would
1801 * require scattered receive support.
1803 if (eth_dev->data->dev_started &&
1804 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
1805 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
1807 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
1809 "MTU change would require scattered rx support. ");
1810 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
1815 if (new_mtu > RTE_ETHER_MTU) {
1816 bp->flags |= BNXT_FLAG_JUMBO;
1817 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1818 DEV_RX_OFFLOAD_JUMBO_FRAME;
1820 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1821 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1822 bp->flags &= ~BNXT_FLAG_JUMBO;
1825 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
1827 eth_dev->data->mtu = new_mtu;
1828 PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1830 for (i = 0; i < bp->nr_vnics; i++) {
1831 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1834 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1835 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1836 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1840 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1841 size -= RTE_PKTMBUF_HEADROOM;
1843 if (size < new_mtu) {
1844 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1854 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1856 struct bnxt *bp = dev->data->dev_private;
1857 uint16_t vlan = bp->vlan;
1860 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1862 "PVID cannot be modified for this function\n");
1865 bp->vlan = on ? pvid : 0;
1867 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1874 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1876 struct bnxt *bp = dev->data->dev_private;
1878 return bnxt_hwrm_port_led_cfg(bp, true);
1882 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1884 struct bnxt *bp = dev->data->dev_private;
1886 return bnxt_hwrm_port_led_cfg(bp, false);
1890 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1892 uint32_t desc = 0, raw_cons = 0, cons;
1893 struct bnxt_cp_ring_info *cpr;
1894 struct bnxt_rx_queue *rxq;
1895 struct rx_pkt_cmpl *rxcmp;
1900 rxq = dev->data->rx_queues[rx_queue_id];
1904 while (raw_cons < rxq->nb_rx_desc) {
1905 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1906 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1908 if (!CMPL_VALID(rxcmp, valid))
1910 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1911 cmp_type = CMP_TYPE(rxcmp);
1912 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1913 cmp = (rte_le_to_cpu_32(
1914 ((struct rx_tpa_end_cmpl *)
1915 (rxcmp))->agg_bufs_v1) &
1916 RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1917 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1919 } else if (cmp_type == 0x11) {
1921 cmp = (rxcmp->agg_bufs_v1 &
1922 RX_PKT_CMPL_AGG_BUFS_MASK) >>
1923 RX_PKT_CMPL_AGG_BUFS_SFT;
1928 raw_cons += cmp ? cmp : 2;
1935 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1937 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1938 struct bnxt_rx_ring_info *rxr;
1939 struct bnxt_cp_ring_info *cpr;
1940 struct bnxt_sw_rx_bd *rx_buf;
1941 struct rx_pkt_cmpl *rxcmp;
1942 uint32_t cons, cp_cons;
1950 if (offset >= rxq->nb_rx_desc)
1953 cons = RING_CMP(cpr->cp_ring_struct, offset);
1954 cp_cons = cpr->cp_raw_cons;
1955 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1957 if (cons > cp_cons) {
1958 if (CMPL_VALID(rxcmp, cpr->valid))
1959 return RTE_ETH_RX_DESC_DONE;
1961 if (CMPL_VALID(rxcmp, !cpr->valid))
1962 return RTE_ETH_RX_DESC_DONE;
1964 rx_buf = &rxr->rx_buf_ring[cons];
1965 if (rx_buf->mbuf == NULL)
1966 return RTE_ETH_RX_DESC_UNAVAIL;
1969 return RTE_ETH_RX_DESC_AVAIL;
1973 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1975 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1976 struct bnxt_tx_ring_info *txr;
1977 struct bnxt_cp_ring_info *cpr;
1978 struct bnxt_sw_tx_bd *tx_buf;
1979 struct tx_pkt_cmpl *txcmp;
1980 uint32_t cons, cp_cons;
1988 if (offset >= txq->nb_tx_desc)
1991 cons = RING_CMP(cpr->cp_ring_struct, offset);
1992 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1993 cp_cons = cpr->cp_raw_cons;
1995 if (cons > cp_cons) {
1996 if (CMPL_VALID(txcmp, cpr->valid))
1997 return RTE_ETH_TX_DESC_UNAVAIL;
1999 if (CMPL_VALID(txcmp, !cpr->valid))
2000 return RTE_ETH_TX_DESC_UNAVAIL;
2002 tx_buf = &txr->tx_buf_ring[cons];
2003 if (tx_buf->mbuf == NULL)
2004 return RTE_ETH_TX_DESC_DONE;
2006 return RTE_ETH_TX_DESC_FULL;
2009 static struct bnxt_filter_info *
2010 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2011 struct rte_eth_ethertype_filter *efilter,
2012 struct bnxt_vnic_info *vnic0,
2013 struct bnxt_vnic_info *vnic,
2016 struct bnxt_filter_info *mfilter = NULL;
2020 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2021 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2022 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2023 " ethertype filter.", efilter->ether_type);
2027 if (efilter->queue >= bp->rx_nr_rings) {
2028 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2033 vnic0 = &bp->vnic_info[0];
2034 vnic = &bp->vnic_info[efilter->queue];
2036 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2041 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2042 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2043 if ((!memcmp(efilter->mac_addr.addr_bytes,
2044 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2046 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2047 mfilter->ethertype == efilter->ether_type)) {
2053 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2054 if ((!memcmp(efilter->mac_addr.addr_bytes,
2055 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2056 mfilter->ethertype == efilter->ether_type &&
2058 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2072 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2073 enum rte_filter_op filter_op,
2076 struct bnxt *bp = dev->data->dev_private;
2077 struct rte_eth_ethertype_filter *efilter =
2078 (struct rte_eth_ethertype_filter *)arg;
2079 struct bnxt_filter_info *bfilter, *filter1;
2080 struct bnxt_vnic_info *vnic, *vnic0;
2083 if (filter_op == RTE_ETH_FILTER_NOP)
2087 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2092 vnic0 = &bp->vnic_info[0];
2093 vnic = &bp->vnic_info[efilter->queue];
2095 switch (filter_op) {
2096 case RTE_ETH_FILTER_ADD:
2097 bnxt_match_and_validate_ether_filter(bp, efilter,
2102 bfilter = bnxt_get_unused_filter(bp);
2103 if (bfilter == NULL) {
2105 "Not enough resources for a new filter.\n");
2108 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2109 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2110 RTE_ETHER_ADDR_LEN);
2111 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2112 RTE_ETHER_ADDR_LEN);
2113 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2114 bfilter->ethertype = efilter->ether_type;
2115 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2117 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2118 if (filter1 == NULL) {
2123 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2124 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2126 bfilter->dst_id = vnic->fw_vnic_id;
2128 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2130 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2133 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2136 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2138 case RTE_ETH_FILTER_DELETE:
2139 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2141 if (ret == -EEXIST) {
2142 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2144 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2146 bnxt_free_filter(bp, filter1);
2147 } else if (ret == 0) {
2148 PMD_DRV_LOG(ERR, "No matching filter found\n");
2152 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2158 bnxt_free_filter(bp, bfilter);
2164 parse_ntuple_filter(struct bnxt *bp,
2165 struct rte_eth_ntuple_filter *nfilter,
2166 struct bnxt_filter_info *bfilter)
2170 if (nfilter->queue >= bp->rx_nr_rings) {
2171 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2175 switch (nfilter->dst_port_mask) {
2177 bfilter->dst_port_mask = -1;
2178 bfilter->dst_port = nfilter->dst_port;
2179 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2180 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2183 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2187 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2188 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2190 switch (nfilter->proto_mask) {
2192 if (nfilter->proto == 17) /* IPPROTO_UDP */
2193 bfilter->ip_protocol = 17;
2194 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2195 bfilter->ip_protocol = 6;
2198 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2201 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2205 switch (nfilter->dst_ip_mask) {
2207 bfilter->dst_ipaddr_mask[0] = -1;
2208 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2209 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2210 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2213 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2217 switch (nfilter->src_ip_mask) {
2219 bfilter->src_ipaddr_mask[0] = -1;
2220 bfilter->src_ipaddr[0] = nfilter->src_ip;
2221 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2222 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2225 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2229 switch (nfilter->src_port_mask) {
2231 bfilter->src_port_mask = -1;
2232 bfilter->src_port = nfilter->src_port;
2233 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2234 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2237 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2242 //nfilter->priority = (uint8_t)filter->priority;
2244 bfilter->enables = en;
2248 static struct bnxt_filter_info*
2249 bnxt_match_ntuple_filter(struct bnxt *bp,
2250 struct bnxt_filter_info *bfilter,
2251 struct bnxt_vnic_info **mvnic)
2253 struct bnxt_filter_info *mfilter = NULL;
2256 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2257 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2258 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2259 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2260 bfilter->src_ipaddr_mask[0] ==
2261 mfilter->src_ipaddr_mask[0] &&
2262 bfilter->src_port == mfilter->src_port &&
2263 bfilter->src_port_mask == mfilter->src_port_mask &&
2264 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2265 bfilter->dst_ipaddr_mask[0] ==
2266 mfilter->dst_ipaddr_mask[0] &&
2267 bfilter->dst_port == mfilter->dst_port &&
2268 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2269 bfilter->flags == mfilter->flags &&
2270 bfilter->enables == mfilter->enables) {
2281 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2282 struct rte_eth_ntuple_filter *nfilter,
2283 enum rte_filter_op filter_op)
2285 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2286 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2289 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2290 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2294 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2295 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2299 bfilter = bnxt_get_unused_filter(bp);
2300 if (bfilter == NULL) {
2302 "Not enough resources for a new filter.\n");
2305 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2309 vnic = &bp->vnic_info[nfilter->queue];
2310 vnic0 = &bp->vnic_info[0];
2311 filter1 = STAILQ_FIRST(&vnic0->filter);
2312 if (filter1 == NULL) {
2317 bfilter->dst_id = vnic->fw_vnic_id;
2318 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2320 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2321 bfilter->ethertype = 0x800;
2322 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2324 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2326 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2327 bfilter->dst_id == mfilter->dst_id) {
2328 PMD_DRV_LOG(ERR, "filter exists.\n");
2331 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2332 bfilter->dst_id != mfilter->dst_id) {
2333 mfilter->dst_id = vnic->fw_vnic_id;
2334 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2335 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2336 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2337 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2338 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2341 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2342 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2347 if (filter_op == RTE_ETH_FILTER_ADD) {
2348 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2349 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2352 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2354 if (mfilter == NULL) {
2355 /* This should not happen. But for Coverity! */
2359 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2361 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2362 bnxt_free_filter(bp, mfilter);
2363 mfilter->fw_l2_filter_id = -1;
2364 bnxt_free_filter(bp, bfilter);
2365 bfilter->fw_l2_filter_id = -1;
2370 bfilter->fw_l2_filter_id = -1;
2371 bnxt_free_filter(bp, bfilter);
2376 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2377 enum rte_filter_op filter_op,
2380 struct bnxt *bp = dev->data->dev_private;
2383 if (filter_op == RTE_ETH_FILTER_NOP)
2387 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2392 switch (filter_op) {
2393 case RTE_ETH_FILTER_ADD:
2394 ret = bnxt_cfg_ntuple_filter(bp,
2395 (struct rte_eth_ntuple_filter *)arg,
2398 case RTE_ETH_FILTER_DELETE:
2399 ret = bnxt_cfg_ntuple_filter(bp,
2400 (struct rte_eth_ntuple_filter *)arg,
2404 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2412 bnxt_parse_fdir_filter(struct bnxt *bp,
2413 struct rte_eth_fdir_filter *fdir,
2414 struct bnxt_filter_info *filter)
2416 enum rte_fdir_mode fdir_mode =
2417 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2418 struct bnxt_vnic_info *vnic0, *vnic;
2419 struct bnxt_filter_info *filter1;
2423 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2426 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2427 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2429 switch (fdir->input.flow_type) {
2430 case RTE_ETH_FLOW_IPV4:
2431 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2433 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2434 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2435 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2436 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2437 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2438 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2439 filter->ip_addr_type =
2440 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2441 filter->src_ipaddr_mask[0] = 0xffffffff;
2442 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2443 filter->dst_ipaddr_mask[0] = 0xffffffff;
2444 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2445 filter->ethertype = 0x800;
2446 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2448 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2449 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2450 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2451 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2452 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2453 filter->dst_port_mask = 0xffff;
2454 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2455 filter->src_port_mask = 0xffff;
2456 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2457 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2458 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2459 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2460 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2461 filter->ip_protocol = 6;
2462 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2463 filter->ip_addr_type =
2464 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2465 filter->src_ipaddr_mask[0] = 0xffffffff;
2466 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2467 filter->dst_ipaddr_mask[0] = 0xffffffff;
2468 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2469 filter->ethertype = 0x800;
2470 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2472 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2473 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2474 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2475 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2476 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2477 filter->dst_port_mask = 0xffff;
2478 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2479 filter->src_port_mask = 0xffff;
2480 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2481 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2482 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2483 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2484 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2485 filter->ip_protocol = 17;
2486 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2487 filter->ip_addr_type =
2488 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2489 filter->src_ipaddr_mask[0] = 0xffffffff;
2490 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2491 filter->dst_ipaddr_mask[0] = 0xffffffff;
2492 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2493 filter->ethertype = 0x800;
2494 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2496 case RTE_ETH_FLOW_IPV6:
2497 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2499 filter->ip_addr_type =
2500 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2501 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2502 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2503 rte_memcpy(filter->src_ipaddr,
2504 fdir->input.flow.ipv6_flow.src_ip, 16);
2505 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2506 rte_memcpy(filter->dst_ipaddr,
2507 fdir->input.flow.ipv6_flow.dst_ip, 16);
2508 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2509 memset(filter->dst_ipaddr_mask, 0xff, 16);
2510 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2511 memset(filter->src_ipaddr_mask, 0xff, 16);
2512 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2513 filter->ethertype = 0x86dd;
2514 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2516 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2517 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2518 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2519 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2520 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2521 filter->dst_port_mask = 0xffff;
2522 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2523 filter->src_port_mask = 0xffff;
2524 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2525 filter->ip_addr_type =
2526 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2527 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2528 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2529 rte_memcpy(filter->src_ipaddr,
2530 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2531 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2532 rte_memcpy(filter->dst_ipaddr,
2533 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2534 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2535 memset(filter->dst_ipaddr_mask, 0xff, 16);
2536 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2537 memset(filter->src_ipaddr_mask, 0xff, 16);
2538 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2539 filter->ethertype = 0x86dd;
2540 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2542 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2543 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2544 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2545 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2546 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2547 filter->dst_port_mask = 0xffff;
2548 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2549 filter->src_port_mask = 0xffff;
2550 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2551 filter->ip_addr_type =
2552 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2553 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2554 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2555 rte_memcpy(filter->src_ipaddr,
2556 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2557 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2558 rte_memcpy(filter->dst_ipaddr,
2559 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2560 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2561 memset(filter->dst_ipaddr_mask, 0xff, 16);
2562 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2563 memset(filter->src_ipaddr_mask, 0xff, 16);
2564 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2565 filter->ethertype = 0x86dd;
2566 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2568 case RTE_ETH_FLOW_L2_PAYLOAD:
2569 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2570 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2572 case RTE_ETH_FLOW_VXLAN:
2573 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2575 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2576 filter->tunnel_type =
2577 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2578 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2580 case RTE_ETH_FLOW_NVGRE:
2581 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2583 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2584 filter->tunnel_type =
2585 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2586 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2588 case RTE_ETH_FLOW_UNKNOWN:
2589 case RTE_ETH_FLOW_RAW:
2590 case RTE_ETH_FLOW_FRAG_IPV4:
2591 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2592 case RTE_ETH_FLOW_FRAG_IPV6:
2593 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2594 case RTE_ETH_FLOW_IPV6_EX:
2595 case RTE_ETH_FLOW_IPV6_TCP_EX:
2596 case RTE_ETH_FLOW_IPV6_UDP_EX:
2597 case RTE_ETH_FLOW_GENEVE:
2603 vnic0 = &bp->vnic_info[0];
2604 vnic = &bp->vnic_info[fdir->action.rx_queue];
2606 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2611 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2612 rte_memcpy(filter->dst_macaddr,
2613 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2614 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2617 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2618 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2619 filter1 = STAILQ_FIRST(&vnic0->filter);
2620 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2622 filter->dst_id = vnic->fw_vnic_id;
2623 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2624 if (filter->dst_macaddr[i] == 0x00)
2625 filter1 = STAILQ_FIRST(&vnic0->filter);
2627 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2630 if (filter1 == NULL)
2633 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2634 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2636 filter->enables = en;
2641 static struct bnxt_filter_info *
2642 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2643 struct bnxt_vnic_info **mvnic)
2645 struct bnxt_filter_info *mf = NULL;
2648 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2649 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2651 STAILQ_FOREACH(mf, &vnic->filter, next) {
2652 if (mf->filter_type == nf->filter_type &&
2653 mf->flags == nf->flags &&
2654 mf->src_port == nf->src_port &&
2655 mf->src_port_mask == nf->src_port_mask &&
2656 mf->dst_port == nf->dst_port &&
2657 mf->dst_port_mask == nf->dst_port_mask &&
2658 mf->ip_protocol == nf->ip_protocol &&
2659 mf->ip_addr_type == nf->ip_addr_type &&
2660 mf->ethertype == nf->ethertype &&
2661 mf->vni == nf->vni &&
2662 mf->tunnel_type == nf->tunnel_type &&
2663 mf->l2_ovlan == nf->l2_ovlan &&
2664 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2665 mf->l2_ivlan == nf->l2_ivlan &&
2666 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2667 !memcmp(mf->l2_addr, nf->l2_addr,
2668 RTE_ETHER_ADDR_LEN) &&
2669 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2670 RTE_ETHER_ADDR_LEN) &&
2671 !memcmp(mf->src_macaddr, nf->src_macaddr,
2672 RTE_ETHER_ADDR_LEN) &&
2673 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2674 RTE_ETHER_ADDR_LEN) &&
2675 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2676 sizeof(nf->src_ipaddr)) &&
2677 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2678 sizeof(nf->src_ipaddr_mask)) &&
2679 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2680 sizeof(nf->dst_ipaddr)) &&
2681 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2682 sizeof(nf->dst_ipaddr_mask))) {
2693 bnxt_fdir_filter(struct rte_eth_dev *dev,
2694 enum rte_filter_op filter_op,
2697 struct bnxt *bp = dev->data->dev_private;
2698 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
2699 struct bnxt_filter_info *filter, *match;
2700 struct bnxt_vnic_info *vnic, *mvnic;
2703 if (filter_op == RTE_ETH_FILTER_NOP)
2706 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2709 switch (filter_op) {
2710 case RTE_ETH_FILTER_ADD:
2711 case RTE_ETH_FILTER_DELETE:
2713 filter = bnxt_get_unused_filter(bp);
2714 if (filter == NULL) {
2716 "Not enough resources for a new flow.\n");
2720 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2723 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2725 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2726 vnic = &bp->vnic_info[0];
2728 vnic = &bp->vnic_info[fdir->action.rx_queue];
2730 match = bnxt_match_fdir(bp, filter, &mvnic);
2731 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2732 if (match->dst_id == vnic->fw_vnic_id) {
2733 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2737 match->dst_id = vnic->fw_vnic_id;
2738 ret = bnxt_hwrm_set_ntuple_filter(bp,
2741 STAILQ_REMOVE(&mvnic->filter, match,
2742 bnxt_filter_info, next);
2743 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2745 "Filter with matching pattern exist\n");
2747 "Updated it to new destination q\n");
2751 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2752 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2757 if (filter_op == RTE_ETH_FILTER_ADD) {
2758 ret = bnxt_hwrm_set_ntuple_filter(bp,
2763 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2765 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2766 STAILQ_REMOVE(&vnic->filter, match,
2767 bnxt_filter_info, next);
2768 bnxt_free_filter(bp, match);
2769 filter->fw_l2_filter_id = -1;
2770 bnxt_free_filter(bp, filter);
2773 case RTE_ETH_FILTER_FLUSH:
2774 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2775 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2777 STAILQ_FOREACH(filter, &vnic->filter, next) {
2778 if (filter->filter_type ==
2779 HWRM_CFA_NTUPLE_FILTER) {
2781 bnxt_hwrm_clear_ntuple_filter(bp,
2783 STAILQ_REMOVE(&vnic->filter, filter,
2784 bnxt_filter_info, next);
2789 case RTE_ETH_FILTER_UPDATE:
2790 case RTE_ETH_FILTER_STATS:
2791 case RTE_ETH_FILTER_INFO:
2792 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2795 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2802 filter->fw_l2_filter_id = -1;
2803 bnxt_free_filter(bp, filter);
2808 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2809 enum rte_filter_type filter_type,
2810 enum rte_filter_op filter_op, void *arg)
2814 switch (filter_type) {
2815 case RTE_ETH_FILTER_TUNNEL:
2817 "filter type: %d: To be implemented\n", filter_type);
2819 case RTE_ETH_FILTER_FDIR:
2820 ret = bnxt_fdir_filter(dev, filter_op, arg);
2822 case RTE_ETH_FILTER_NTUPLE:
2823 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2825 case RTE_ETH_FILTER_ETHERTYPE:
2826 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2828 case RTE_ETH_FILTER_GENERIC:
2829 if (filter_op != RTE_ETH_FILTER_GET)
2831 *(const void **)arg = &bnxt_flow_ops;
2835 "Filter type (%d) not supported", filter_type);
2842 static const uint32_t *
2843 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2845 static const uint32_t ptypes[] = {
2846 RTE_PTYPE_L2_ETHER_VLAN,
2847 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2848 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2852 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2853 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2854 RTE_PTYPE_INNER_L4_ICMP,
2855 RTE_PTYPE_INNER_L4_TCP,
2856 RTE_PTYPE_INNER_L4_UDP,
2860 if (!dev->rx_pkt_burst)
2866 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2869 uint32_t reg_base = *reg_arr & 0xfffff000;
2873 for (i = 0; i < count; i++) {
2874 if ((reg_arr[i] & 0xfffff000) != reg_base)
2877 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2878 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
2882 static int bnxt_map_ptp_regs(struct bnxt *bp)
2884 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2888 reg_arr = ptp->rx_regs;
2889 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2893 reg_arr = ptp->tx_regs;
2894 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2898 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2899 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2901 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2902 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2907 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2909 rte_write32(0, (uint8_t *)bp->bar0 +
2910 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
2911 rte_write32(0, (uint8_t *)bp->bar0 +
2912 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
2915 static uint64_t bnxt_cc_read(struct bnxt *bp)
2919 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2920 BNXT_GRCPF_REG_SYNC_TIME));
2921 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2922 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2926 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2928 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2931 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2932 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2933 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2936 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2937 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2938 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2939 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2940 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2941 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2946 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2948 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2949 struct bnxt_pf_info *pf = &bp->pf;
2956 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2957 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2958 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2961 port_id = pf->port_id;
2962 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2963 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
2965 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2966 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2967 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
2968 /* bnxt_clr_rx_ts(bp); TBD */
2972 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2973 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
2974 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2975 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
2981 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
2984 struct bnxt *bp = dev->data->dev_private;
2985 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2990 ns = rte_timespec_to_ns(ts);
2991 /* Set the timecounters to a new value. */
2998 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3000 uint64_t ns, systime_cycles;
3001 struct bnxt *bp = dev->data->dev_private;
3002 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3007 systime_cycles = bnxt_cc_read(bp);
3008 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3009 *ts = rte_ns_to_timespec(ns);
3014 bnxt_timesync_enable(struct rte_eth_dev *dev)
3016 struct bnxt *bp = dev->data->dev_private;
3017 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3024 ptp->tx_tstamp_en = 1;
3025 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3027 if (!bnxt_hwrm_ptp_cfg(bp))
3028 bnxt_map_ptp_regs(bp);
3030 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3031 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3032 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3034 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3035 ptp->tc.cc_shift = shift;
3036 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3038 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3039 ptp->rx_tstamp_tc.cc_shift = shift;
3040 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3042 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3043 ptp->tx_tstamp_tc.cc_shift = shift;
3044 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3050 bnxt_timesync_disable(struct rte_eth_dev *dev)
3052 struct bnxt *bp = dev->data->dev_private;
3053 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3059 ptp->tx_tstamp_en = 0;
3062 bnxt_hwrm_ptp_cfg(bp);
3064 bnxt_unmap_ptp_regs(bp);
3070 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3071 struct timespec *timestamp,
3072 uint32_t flags __rte_unused)
3074 struct bnxt *bp = dev->data->dev_private;
3075 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3076 uint64_t rx_tstamp_cycles = 0;
3082 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3083 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3084 *timestamp = rte_ns_to_timespec(ns);
3089 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3090 struct timespec *timestamp)
3092 struct bnxt *bp = dev->data->dev_private;
3093 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3094 uint64_t tx_tstamp_cycles = 0;
3100 bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3101 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3102 *timestamp = rte_ns_to_timespec(ns);
3108 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3110 struct bnxt *bp = dev->data->dev_private;
3111 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3116 ptp->tc.nsec += delta;
3122 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3124 struct bnxt *bp = dev->data->dev_private;
3126 uint32_t dir_entries;
3127 uint32_t entry_length;
3129 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3130 bp->pdev->addr.domain, bp->pdev->addr.bus,
3131 bp->pdev->addr.devid, bp->pdev->addr.function);
3133 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3137 return dir_entries * entry_length;
3141 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3142 struct rte_dev_eeprom_info *in_eeprom)
3144 struct bnxt *bp = dev->data->dev_private;
3148 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3149 "len = %d\n", bp->pdev->addr.domain,
3150 bp->pdev->addr.bus, bp->pdev->addr.devid,
3151 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3153 if (in_eeprom->offset == 0) /* special offset value to get directory */
3154 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3157 index = in_eeprom->offset >> 24;
3158 offset = in_eeprom->offset & 0xffffff;
3161 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3162 in_eeprom->length, in_eeprom->data);
3167 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3170 case BNX_DIR_TYPE_CHIMP_PATCH:
3171 case BNX_DIR_TYPE_BOOTCODE:
3172 case BNX_DIR_TYPE_BOOTCODE_2:
3173 case BNX_DIR_TYPE_APE_FW:
3174 case BNX_DIR_TYPE_APE_PATCH:
3175 case BNX_DIR_TYPE_KONG_FW:
3176 case BNX_DIR_TYPE_KONG_PATCH:
3177 case BNX_DIR_TYPE_BONO_FW:
3178 case BNX_DIR_TYPE_BONO_PATCH:
3186 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3189 case BNX_DIR_TYPE_AVS:
3190 case BNX_DIR_TYPE_EXP_ROM_MBA:
3191 case BNX_DIR_TYPE_PCIE:
3192 case BNX_DIR_TYPE_TSCF_UCODE:
3193 case BNX_DIR_TYPE_EXT_PHY:
3194 case BNX_DIR_TYPE_CCM:
3195 case BNX_DIR_TYPE_ISCSI_BOOT:
3196 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3197 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3205 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3207 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3208 bnxt_dir_type_is_other_exec_format(dir_type);
3212 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3213 struct rte_dev_eeprom_info *in_eeprom)
3215 struct bnxt *bp = dev->data->dev_private;
3216 uint8_t index, dir_op;
3217 uint16_t type, ext, ordinal, attr;
3219 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3220 "len = %d\n", bp->pdev->addr.domain,
3221 bp->pdev->addr.bus, bp->pdev->addr.devid,
3222 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3225 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3229 type = in_eeprom->magic >> 16;
3231 if (type == 0xffff) { /* special value for directory operations */
3232 index = in_eeprom->magic & 0xff;
3233 dir_op = in_eeprom->magic >> 8;
3237 case 0x0e: /* erase */
3238 if (in_eeprom->offset != ~in_eeprom->magic)
3240 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3246 /* Create or re-write an NVM item: */
3247 if (bnxt_dir_type_is_executable(type) == true)
3249 ext = in_eeprom->magic & 0xffff;
3250 ordinal = in_eeprom->offset >> 16;
3251 attr = in_eeprom->offset & 0xffff;
3253 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3254 in_eeprom->data, in_eeprom->length);
3262 static const struct eth_dev_ops bnxt_dev_ops = {
3263 .dev_infos_get = bnxt_dev_info_get_op,
3264 .dev_close = bnxt_dev_close_op,
3265 .dev_configure = bnxt_dev_configure_op,
3266 .dev_start = bnxt_dev_start_op,
3267 .dev_stop = bnxt_dev_stop_op,
3268 .dev_set_link_up = bnxt_dev_set_link_up_op,
3269 .dev_set_link_down = bnxt_dev_set_link_down_op,
3270 .stats_get = bnxt_stats_get_op,
3271 .stats_reset = bnxt_stats_reset_op,
3272 .rx_queue_setup = bnxt_rx_queue_setup_op,
3273 .rx_queue_release = bnxt_rx_queue_release_op,
3274 .tx_queue_setup = bnxt_tx_queue_setup_op,
3275 .tx_queue_release = bnxt_tx_queue_release_op,
3276 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3277 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3278 .reta_update = bnxt_reta_update_op,
3279 .reta_query = bnxt_reta_query_op,
3280 .rss_hash_update = bnxt_rss_hash_update_op,
3281 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3282 .link_update = bnxt_link_update_op,
3283 .promiscuous_enable = bnxt_promiscuous_enable_op,
3284 .promiscuous_disable = bnxt_promiscuous_disable_op,
3285 .allmulticast_enable = bnxt_allmulticast_enable_op,
3286 .allmulticast_disable = bnxt_allmulticast_disable_op,
3287 .mac_addr_add = bnxt_mac_addr_add_op,
3288 .mac_addr_remove = bnxt_mac_addr_remove_op,
3289 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3290 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3291 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3292 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3293 .vlan_filter_set = bnxt_vlan_filter_set_op,
3294 .vlan_offload_set = bnxt_vlan_offload_set_op,
3295 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3296 .mtu_set = bnxt_mtu_set_op,
3297 .mac_addr_set = bnxt_set_default_mac_addr_op,
3298 .xstats_get = bnxt_dev_xstats_get_op,
3299 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3300 .xstats_reset = bnxt_dev_xstats_reset_op,
3301 .fw_version_get = bnxt_fw_version_get,
3302 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3303 .rxq_info_get = bnxt_rxq_info_get_op,
3304 .txq_info_get = bnxt_txq_info_get_op,
3305 .dev_led_on = bnxt_dev_led_on_op,
3306 .dev_led_off = bnxt_dev_led_off_op,
3307 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3308 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3309 .rx_queue_count = bnxt_rx_queue_count_op,
3310 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3311 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3312 .rx_queue_start = bnxt_rx_queue_start,
3313 .rx_queue_stop = bnxt_rx_queue_stop,
3314 .tx_queue_start = bnxt_tx_queue_start,
3315 .tx_queue_stop = bnxt_tx_queue_stop,
3316 .filter_ctrl = bnxt_filter_ctrl_op,
3317 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3318 .get_eeprom_length = bnxt_get_eeprom_length_op,
3319 .get_eeprom = bnxt_get_eeprom_op,
3320 .set_eeprom = bnxt_set_eeprom_op,
3321 .timesync_enable = bnxt_timesync_enable,
3322 .timesync_disable = bnxt_timesync_disable,
3323 .timesync_read_time = bnxt_timesync_read_time,
3324 .timesync_write_time = bnxt_timesync_write_time,
3325 .timesync_adjust_time = bnxt_timesync_adjust_time,
3326 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3327 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3330 static bool bnxt_vf_pciid(uint16_t id)
3332 if (id == BROADCOM_DEV_ID_57304_VF ||
3333 id == BROADCOM_DEV_ID_57406_VF ||
3334 id == BROADCOM_DEV_ID_5731X_VF ||
3335 id == BROADCOM_DEV_ID_5741X_VF ||
3336 id == BROADCOM_DEV_ID_57414_VF ||
3337 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3338 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3339 id == BROADCOM_DEV_ID_58802_VF ||
3340 id == BROADCOM_DEV_ID_57500_VF)
3345 bool bnxt_stratus_device(struct bnxt *bp)
3347 uint16_t id = bp->pdev->id.device_id;
3349 if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3350 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3351 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3356 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3358 struct bnxt *bp = eth_dev->data->dev_private;
3359 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3362 /* enable device (incl. PCI PM wakeup), and bus-mastering */
3363 if (!pci_dev->mem_resource[0].addr) {
3365 "Cannot find PCI device base address, aborting\n");
3367 goto init_err_disable;
3370 bp->eth_dev = eth_dev;
3373 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3375 PMD_DRV_LOG(ERR, "Cannot map device registers, aborting\n");
3377 goto init_err_release;
3380 if (!pci_dev->mem_resource[2].addr) {
3382 "Cannot find PCI device BAR 2 address, aborting\n");
3384 goto init_err_release;
3386 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3394 if (bp->doorbell_base)
3395 bp->doorbell_base = NULL;
3402 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
3403 struct bnxt_ctx_pg_info *ctx_pg,
3408 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
3409 const struct rte_memzone *mz = NULL;
3410 char mz_name[RTE_MEMZONE_NAMESIZE];
3411 rte_iova_t mz_phys_addr;
3412 uint64_t valid_bits = 0;
3419 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
3421 rmem->page_size = BNXT_PAGE_SIZE;
3422 rmem->pg_arr = ctx_pg->ctx_pg_arr;
3423 rmem->dma_arr = ctx_pg->ctx_dma_arr;
3424 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
3426 valid_bits = PTU_PTE_VALID;
3428 if (rmem->nr_pages > 1) {
3429 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_pg_tbl%s_%x",
3431 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3432 mz = rte_memzone_lookup(mz_name);
3434 mz = rte_memzone_reserve_aligned(mz_name,
3438 RTE_MEMZONE_SIZE_HINT_ONLY |
3439 RTE_MEMZONE_IOVA_CONTIG,
3445 memset(mz->addr, 0, mz->len);
3446 mz_phys_addr = mz->iova;
3447 if ((unsigned long)mz->addr == mz_phys_addr) {
3448 PMD_DRV_LOG(WARNING,
3449 "Memzone physical address same as virtual.\n");
3450 PMD_DRV_LOG(WARNING,
3451 "Using rte_mem_virt2iova()\n");
3452 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3453 if (mz_phys_addr == 0) {
3455 "unable to map addr to phys memory\n");
3459 rte_mem_lock_page(((char *)mz->addr));
3461 rmem->pg_tbl = mz->addr;
3462 rmem->pg_tbl_map = mz_phys_addr;
3463 rmem->pg_tbl_mz = mz;
3466 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x", suffix, idx);
3467 mz = rte_memzone_lookup(mz_name);
3469 mz = rte_memzone_reserve_aligned(mz_name,
3473 RTE_MEMZONE_SIZE_HINT_ONLY |
3474 RTE_MEMZONE_IOVA_CONTIG,
3480 memset(mz->addr, 0, mz->len);
3481 mz_phys_addr = mz->iova;
3482 if ((unsigned long)mz->addr == mz_phys_addr) {
3483 PMD_DRV_LOG(WARNING,
3484 "Memzone physical address same as virtual.\n");
3485 PMD_DRV_LOG(WARNING,
3486 "Using rte_mem_virt2iova()\n");
3487 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
3488 rte_mem_lock_page(((char *)mz->addr) + sz);
3489 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3490 if (mz_phys_addr == RTE_BAD_IOVA) {
3492 "unable to map addr to phys memory\n");
3497 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
3498 rte_mem_lock_page(((char *)mz->addr) + sz);
3499 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
3500 rmem->dma_arr[i] = mz_phys_addr + sz;
3502 if (rmem->nr_pages > 1) {
3503 if (i == rmem->nr_pages - 2 &&
3504 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3505 valid_bits |= PTU_PTE_NEXT_TO_LAST;
3506 else if (i == rmem->nr_pages - 1 &&
3507 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3508 valid_bits |= PTU_PTE_LAST;
3510 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
3516 if (rmem->vmem_size)
3517 rmem->vmem = (void **)mz->addr;
3518 rmem->dma_arr[0] = mz_phys_addr;
3522 static void bnxt_free_ctx_mem(struct bnxt *bp)
3526 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
3529 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
3530 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
3531 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
3532 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
3533 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
3534 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
3535 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
3536 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
3537 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
3538 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
3539 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
3541 for (i = 0; i < BNXT_MAX_Q; i++) {
3542 if (bp->ctx->tqm_mem[i])
3543 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
3550 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
3552 #define min_t(type, x, y) ({ \
3553 type __min1 = (x); \
3554 type __min2 = (y); \
3555 __min1 < __min2 ? __min1 : __min2; })
3557 #define max_t(type, x, y) ({ \
3558 type __max1 = (x); \
3559 type __max2 = (y); \
3560 __max1 > __max2 ? __max1 : __max2; })
3562 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
3564 int bnxt_alloc_ctx_mem(struct bnxt *bp)
3566 struct bnxt_ctx_pg_info *ctx_pg;
3567 struct bnxt_ctx_mem_info *ctx;
3568 uint32_t mem_size, ena, entries;
3571 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
3573 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
3577 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
3580 ctx_pg = &ctx->qp_mem;
3581 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
3582 mem_size = ctx->qp_entry_size * ctx_pg->entries;
3583 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
3587 ctx_pg = &ctx->srq_mem;
3588 ctx_pg->entries = ctx->srq_max_l2_entries;
3589 mem_size = ctx->srq_entry_size * ctx_pg->entries;
3590 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
3594 ctx_pg = &ctx->cq_mem;
3595 ctx_pg->entries = ctx->cq_max_l2_entries;
3596 mem_size = ctx->cq_entry_size * ctx_pg->entries;
3597 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
3601 ctx_pg = &ctx->vnic_mem;
3602 ctx_pg->entries = ctx->vnic_max_vnic_entries +
3603 ctx->vnic_max_ring_table_entries;
3604 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
3605 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
3609 ctx_pg = &ctx->stat_mem;
3610 ctx_pg->entries = ctx->stat_max_entries;
3611 mem_size = ctx->stat_entry_size * ctx_pg->entries;
3612 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
3616 entries = ctx->qp_max_l2_entries;
3617 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
3618 entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
3619 ctx->tqm_max_entries_per_ring);
3620 for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
3621 ctx_pg = ctx->tqm_mem[i];
3622 /* use min tqm entries for now. */
3623 ctx_pg->entries = entries;
3624 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
3625 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
3628 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
3631 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
3632 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
3635 "Failed to configure context mem: rc = %d\n", rc);
3637 ctx->flags |= BNXT_CTX_FLAG_INITED;
3642 static int bnxt_alloc_stats_mem(struct bnxt *bp)
3644 struct rte_pci_device *pci_dev = bp->pdev;
3645 char mz_name[RTE_MEMZONE_NAMESIZE];
3646 const struct rte_memzone *mz = NULL;
3647 uint32_t total_alloc_len;
3648 rte_iova_t mz_phys_addr;
3650 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
3653 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3654 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
3655 pci_dev->addr.bus, pci_dev->addr.devid,
3656 pci_dev->addr.function, "rx_port_stats");
3657 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3658 mz = rte_memzone_lookup(mz_name);
3660 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
3661 sizeof(struct rx_port_stats_ext) + 512);
3663 mz = rte_memzone_reserve(mz_name, total_alloc_len,
3666 RTE_MEMZONE_SIZE_HINT_ONLY |
3667 RTE_MEMZONE_IOVA_CONTIG);
3671 memset(mz->addr, 0, mz->len);
3672 mz_phys_addr = mz->iova;
3673 if ((unsigned long)mz->addr == mz_phys_addr) {
3674 PMD_DRV_LOG(WARNING,
3675 "Memzone physical address same as virtual.\n");
3676 PMD_DRV_LOG(WARNING,
3677 "Using rte_mem_virt2iova()\n");
3678 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3679 if (mz_phys_addr == 0) {
3681 "Can't map address to physical memory\n");
3686 bp->rx_mem_zone = (const void *)mz;
3687 bp->hw_rx_port_stats = mz->addr;
3688 bp->hw_rx_port_stats_map = mz_phys_addr;
3690 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3691 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
3692 pci_dev->addr.bus, pci_dev->addr.devid,
3693 pci_dev->addr.function, "tx_port_stats");
3694 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3695 mz = rte_memzone_lookup(mz_name);
3697 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
3698 sizeof(struct tx_port_stats_ext) + 512);
3700 mz = rte_memzone_reserve(mz_name,
3704 RTE_MEMZONE_SIZE_HINT_ONLY |
3705 RTE_MEMZONE_IOVA_CONTIG);
3709 memset(mz->addr, 0, mz->len);
3710 mz_phys_addr = mz->iova;
3711 if ((unsigned long)mz->addr == mz_phys_addr) {
3712 PMD_DRV_LOG(WARNING,
3713 "Memzone physical address same as virtual\n");
3714 PMD_DRV_LOG(WARNING,
3715 "Using rte_mem_virt2iova()\n");
3716 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3717 if (mz_phys_addr == 0) {
3719 "Can't map address to physical memory\n");
3724 bp->tx_mem_zone = (const void *)mz;
3725 bp->hw_tx_port_stats = mz->addr;
3726 bp->hw_tx_port_stats_map = mz_phys_addr;
3727 bp->flags |= BNXT_FLAG_PORT_STATS;
3729 /* Display extended statistics if FW supports it */
3730 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
3731 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
3732 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
3735 bp->hw_rx_port_stats_ext = (void *)
3736 ((uint8_t *)bp->hw_rx_port_stats +
3737 sizeof(struct rx_port_stats));
3738 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
3739 sizeof(struct rx_port_stats);
3740 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
3742 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
3743 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
3744 bp->hw_tx_port_stats_ext = (void *)
3745 ((uint8_t *)bp->hw_tx_port_stats +
3746 sizeof(struct tx_port_stats));
3747 bp->hw_tx_port_stats_ext_map =
3748 bp->hw_tx_port_stats_map +
3749 sizeof(struct tx_port_stats);
3750 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
3756 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
3758 struct bnxt *bp = eth_dev->data->dev_private;
3761 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3762 RTE_ETHER_ADDR_LEN *
3765 if (eth_dev->data->mac_addrs == NULL) {
3766 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
3770 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
3774 /* Generate a random MAC address, if none was assigned by PF */
3775 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
3776 bnxt_eth_hw_addr_random(bp->mac_addr);
3778 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
3779 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
3780 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
3782 rc = bnxt_hwrm_set_mac(bp);
3784 memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
3785 RTE_ETHER_ADDR_LEN);
3789 /* Copy the permanent MAC from the FUNC_QCAPS response */
3790 memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
3791 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
3796 #define ALLOW_FUNC(x) \
3798 uint32_t arg = (x); \
3799 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3800 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3803 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3805 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3806 static int version_printed;
3811 if (version_printed++ == 0)
3812 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
3814 rte_eth_copy_pci_info(eth_dev, pci_dev);
3816 bp = eth_dev->data->dev_private;
3818 bp->dev_stopped = 1;
3820 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3823 if (bnxt_vf_pciid(pci_dev->id.device_id))
3824 bp->flags |= BNXT_FLAG_VF;
3826 if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
3827 pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
3828 pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
3829 pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF)
3830 bp->flags |= BNXT_FLAG_THOR_CHIP;
3832 rc = bnxt_init_board(eth_dev);
3835 "Board initialization failed rc: %x\n", rc);
3839 eth_dev->dev_ops = &bnxt_dev_ops;
3840 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3841 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3842 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3845 rc = bnxt_alloc_hwrm_resources(bp);
3848 "hwrm resource allocation failure rc: %x\n", rc);
3851 rc = bnxt_hwrm_ver_get(bp);
3855 rc = bnxt_hwrm_func_reset(bp);
3857 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc);
3862 rc = bnxt_hwrm_queue_qportcfg(bp);
3864 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n");
3867 /* Get the MAX capabilities for this function */
3868 rc = bnxt_hwrm_func_qcaps(bp);
3870 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc);
3874 rc = bnxt_alloc_stats_mem(bp);
3878 if (bp->max_tx_rings == 0) {
3879 PMD_DRV_LOG(ERR, "No TX rings available!\n");
3884 rc = bnxt_setup_mac_addr(eth_dev);
3888 /* THOR does not support ring groups.
3889 * But we will use the array to save RSS context IDs.
3891 if (BNXT_CHIP_THOR(bp)) {
3892 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
3893 } else if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3894 /* 1 ring is for default completion ring */
3895 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
3900 if (BNXT_HAS_RING_GRPS(bp)) {
3901 bp->grp_info = rte_zmalloc("bnxt_grp_info",
3902 sizeof(*bp->grp_info) *
3903 bp->max_ring_grps, 0);
3904 if (!bp->grp_info) {
3906 "Failed to alloc %zu bytes for grp info tbl.\n",
3907 sizeof(*bp->grp_info) * bp->max_ring_grps);
3913 /* Forward all requests if firmware is new enough */
3914 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3915 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3916 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3917 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3919 PMD_DRV_LOG(WARNING,
3920 "Firmware too old for VF mailbox functionality\n");
3921 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3925 * The following are used for driver cleanup. If we disallow these,
3926 * VF drivers can't clean up cleanly.
3928 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3929 ALLOW_FUNC(HWRM_VNIC_FREE);
3930 ALLOW_FUNC(HWRM_RING_FREE);
3931 ALLOW_FUNC(HWRM_RING_GRP_FREE);
3932 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3933 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3934 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3935 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3936 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3937 rc = bnxt_hwrm_func_driver_register(bp);
3940 "Failed to register driver");
3946 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3947 pci_dev->mem_resource[0].phys_addr,
3948 pci_dev->mem_resource[0].addr);
3950 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
3952 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n");
3956 if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
3957 mtu != eth_dev->data->mtu)
3958 eth_dev->data->mtu = mtu;
3961 //if (bp->pf.active_vfs) {
3962 // TODO: Deallocate VF resources?
3964 if (bp->pdev->max_vfs) {
3965 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
3967 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
3971 rc = bnxt_hwrm_allocate_pf_only(bp);
3974 "Failed to allocate PF resources\n");
3980 bnxt_hwrm_port_led_qcaps(bp);
3982 rc = bnxt_setup_int(bp);
3986 rc = bnxt_alloc_mem(bp);
3988 goto error_free_int;
3990 rc = bnxt_request_int(bp);
3992 goto error_free_int;
3994 bnxt_enable_int(bp);
4000 bnxt_disable_int(bp);
4001 bnxt_hwrm_func_buf_unrgtr(bp);
4005 bnxt_dev_uninit(eth_dev);
4011 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4013 struct bnxt *bp = eth_dev->data->dev_private;
4016 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4019 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4020 bnxt_disable_int(bp);
4023 if (bp->grp_info != NULL) {
4024 rte_free(bp->grp_info);
4025 bp->grp_info = NULL;
4027 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4028 bnxt_free_hwrm_resources(bp);
4030 if (bp->tx_mem_zone) {
4031 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4032 bp->tx_mem_zone = NULL;
4035 if (bp->rx_mem_zone) {
4036 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4037 bp->rx_mem_zone = NULL;
4040 if (bp->dev_stopped == 0)
4041 bnxt_dev_close_op(eth_dev);
4043 rte_free(bp->pf.vf_info);
4044 bnxt_free_ctx_mem(bp);
4045 eth_dev->dev_ops = NULL;
4046 eth_dev->rx_pkt_burst = NULL;
4047 eth_dev->tx_pkt_burst = NULL;
4052 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4053 struct rte_pci_device *pci_dev)
4055 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4059 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4061 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4062 return rte_eth_dev_pci_generic_remove(pci_dev,
4065 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4068 static struct rte_pci_driver bnxt_rte_pmd = {
4069 .id_table = bnxt_pci_id_map,
4070 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4071 .probe = bnxt_pci_probe,
4072 .remove = bnxt_pci_remove,
4076 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4078 if (strcmp(dev->device->driver->name, drv->driver.name))
4084 bool is_bnxt_supported(struct rte_eth_dev *dev)
4086 return is_device_supported(dev, &bnxt_rte_pmd);
4089 RTE_INIT(bnxt_init_log)
4091 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4092 if (bnxt_logtype_driver >= 0)
4093 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4096 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4097 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4098 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");