1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
15 #include <rte_kvargs.h>
18 #include "bnxt_filter.h"
19 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_stats.h"
27 #include "bnxt_vnic.h"
28 #include "hsi_struct_def_dpdk.h"
29 #include "bnxt_nvm_defs.h"
31 #define DRV_MODULE_NAME "bnxt"
32 static const char bnxt_version[] =
33 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
34 int bnxt_logtype_driver;
37 * The set of PCI devices this driver supports
39 static const struct rte_pci_id bnxt_pci_id_map[] = {
40 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
41 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
42 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
43 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
45 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
47 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
93 { .vendor_id = 0, /* sentinel */ },
96 #define BNXT_ETH_RSS_SUPPORT ( \
98 ETH_RSS_NONFRAG_IPV4_TCP | \
99 ETH_RSS_NONFRAG_IPV4_UDP | \
101 ETH_RSS_NONFRAG_IPV6_TCP | \
102 ETH_RSS_NONFRAG_IPV6_UDP)
104 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
105 DEV_TX_OFFLOAD_IPV4_CKSUM | \
106 DEV_TX_OFFLOAD_TCP_CKSUM | \
107 DEV_TX_OFFLOAD_UDP_CKSUM | \
108 DEV_TX_OFFLOAD_TCP_TSO | \
109 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
110 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
111 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
112 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
113 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
114 DEV_TX_OFFLOAD_QINQ_INSERT | \
115 DEV_TX_OFFLOAD_MULTI_SEGS)
117 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
118 DEV_RX_OFFLOAD_VLAN_STRIP | \
119 DEV_RX_OFFLOAD_IPV4_CKSUM | \
120 DEV_RX_OFFLOAD_UDP_CKSUM | \
121 DEV_RX_OFFLOAD_TCP_CKSUM | \
122 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
123 DEV_RX_OFFLOAD_JUMBO_FRAME | \
124 DEV_RX_OFFLOAD_KEEP_CRC | \
125 DEV_RX_OFFLOAD_VLAN_EXTEND | \
126 DEV_RX_OFFLOAD_TCP_LRO | \
127 DEV_RX_OFFLOAD_SCATTER | \
128 DEV_RX_OFFLOAD_RSS_HASH)
130 #define BNXT_DEVARG_TRUFLOW "host-based-truflow"
131 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat"
132 static const char *const bnxt_dev_args[] = {
134 BNXT_DEVARG_FLOW_XSTAT,
139 * truflow == false to disable the feature
140 * truflow == true to enable the feature
142 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1)
145 * flow_xstat == false to disable the feature
146 * flow_xstat == true to enable the feature
148 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1)
150 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
151 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
152 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
153 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
154 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
155 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
156 static int bnxt_restore_vlan_filters(struct bnxt *bp);
157 static void bnxt_dev_recover(void *arg);
159 int is_bnxt_in_error(struct bnxt *bp)
161 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
163 if (bp->flags & BNXT_FLAG_FW_RESET)
169 /***********************/
172 * High level utility functions
175 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
177 if (!BNXT_CHIP_THOR(bp))
180 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
181 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
182 BNXT_RSS_ENTRIES_PER_CTX_THOR;
185 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
187 if (!BNXT_CHIP_THOR(bp))
188 return HW_HASH_INDEX_SIZE;
190 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
193 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
195 bnxt_free_filter_mem(bp);
196 bnxt_free_vnic_attributes(bp);
197 bnxt_free_vnic_mem(bp);
199 /* tx/rx rings are configured as part of *_queue_setup callbacks.
200 * If the number of rings change across fw update,
201 * we don't have much choice except to warn the user.
205 bnxt_free_tx_rings(bp);
206 bnxt_free_rx_rings(bp);
208 bnxt_free_async_cp_ring(bp);
209 bnxt_free_rxtx_nq_ring(bp);
211 rte_free(bp->grp_info);
215 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
219 rc = bnxt_alloc_ring_grps(bp);
223 rc = bnxt_alloc_async_ring_struct(bp);
227 rc = bnxt_alloc_vnic_mem(bp);
231 rc = bnxt_alloc_vnic_attributes(bp);
235 rc = bnxt_alloc_filter_mem(bp);
239 rc = bnxt_alloc_async_cp_ring(bp);
243 rc = bnxt_alloc_rxtx_nq_ring(bp);
250 bnxt_free_mem(bp, reconfig);
254 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
256 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
257 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
258 uint64_t rx_offloads = dev_conf->rxmode.offloads;
259 struct bnxt_rx_queue *rxq;
263 rc = bnxt_vnic_grp_alloc(bp, vnic);
267 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
268 vnic_id, vnic, vnic->fw_grp_ids);
270 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
274 /* Alloc RSS context only if RSS mode is enabled */
275 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
276 int j, nr_ctxs = bnxt_rss_ctxts(bp);
279 for (j = 0; j < nr_ctxs; j++) {
280 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
286 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
290 vnic->num_lb_ctxts = nr_ctxs;
294 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
295 * setting is not available at this time, it will not be
296 * configured correctly in the CFA.
298 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
299 vnic->vlan_strip = true;
301 vnic->vlan_strip = false;
303 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
307 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
311 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
312 rxq = bp->eth_dev->data->rx_queues[j];
315 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
316 j, rxq->vnic, rxq->vnic->fw_grp_ids);
318 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
319 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
321 vnic->rx_queue_cnt++;
324 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
326 rc = bnxt_vnic_rss_configure(bp, vnic);
330 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
332 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
333 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
335 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
339 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
344 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
348 rc = bnxt_hwrm_ctx_rgtr(bp, bp->rx_fc_in_tbl.dma,
349 &bp->rx_fc_in_tbl.ctx_id);
354 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
355 " rx_fc_in_tbl.ctx_id = %d\n",
357 (void *)((uintptr_t)bp->rx_fc_in_tbl.dma),
358 bp->rx_fc_in_tbl.ctx_id);
360 rc = bnxt_hwrm_ctx_rgtr(bp, bp->rx_fc_out_tbl.dma,
361 &bp->rx_fc_out_tbl.ctx_id);
366 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
367 " rx_fc_out_tbl.ctx_id = %d\n",
368 bp->rx_fc_out_tbl.va,
369 (void *)((uintptr_t)bp->rx_fc_out_tbl.dma),
370 bp->rx_fc_out_tbl.ctx_id);
372 rc = bnxt_hwrm_ctx_rgtr(bp, bp->tx_fc_in_tbl.dma,
373 &bp->tx_fc_in_tbl.ctx_id);
378 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
379 " tx_fc_in_tbl.ctx_id = %d\n",
381 (void *)((uintptr_t)bp->tx_fc_in_tbl.dma),
382 bp->tx_fc_in_tbl.ctx_id);
384 rc = bnxt_hwrm_ctx_rgtr(bp, bp->tx_fc_out_tbl.dma,
385 &bp->tx_fc_out_tbl.ctx_id);
390 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
391 " tx_fc_out_tbl.ctx_id = %d\n",
392 bp->tx_fc_out_tbl.va,
393 (void *)((uintptr_t)bp->tx_fc_out_tbl.dma),
394 bp->tx_fc_out_tbl.ctx_id);
396 memset(bp->rx_fc_out_tbl.va, 0, bp->rx_fc_out_tbl.size);
397 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
398 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
399 bp->rx_fc_out_tbl.ctx_id,
405 memset(bp->tx_fc_out_tbl.va, 0, bp->tx_fc_out_tbl.size);
406 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
407 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
408 bp->tx_fc_out_tbl.ctx_id,
415 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
416 struct bnxt_ctx_mem_buf_info *ctx)
421 ctx->va = rte_zmalloc(type, size, 0);
424 rte_mem_lock_page(ctx->va);
426 ctx->dma = rte_mem_virt2iova(ctx->va);
427 if (ctx->dma == RTE_BAD_IOVA)
433 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
435 struct rte_pci_device *pdev = bp->pdev;
436 char type[RTE_MEMZONE_NAMESIZE];
442 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
443 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
444 /* 4 bytes for each counter-id */
445 rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 4, &bp->rx_fc_in_tbl);
449 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
450 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
451 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
452 rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 16, &bp->rx_fc_out_tbl);
456 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
457 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
458 /* 4 bytes for each counter-id */
459 rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 4, &bp->tx_fc_in_tbl);
463 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
464 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
465 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
466 rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 16, &bp->tx_fc_out_tbl);
470 rc = bnxt_register_fc_ctx_mem(bp);
475 static int bnxt_init_ctx_mem(struct bnxt *bp)
479 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
480 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)))
483 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->max_fc);
487 rc = bnxt_init_fc_ctx_mem(bp);
492 static int bnxt_init_chip(struct bnxt *bp)
494 struct rte_eth_link new;
495 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
496 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
497 uint32_t intr_vector = 0;
498 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
499 uint32_t vec = BNXT_MISC_VEC_ID;
503 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
504 bp->eth_dev->data->dev_conf.rxmode.offloads |=
505 DEV_RX_OFFLOAD_JUMBO_FRAME;
506 bp->flags |= BNXT_FLAG_JUMBO;
508 bp->eth_dev->data->dev_conf.rxmode.offloads &=
509 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
510 bp->flags &= ~BNXT_FLAG_JUMBO;
513 /* THOR does not support ring groups.
514 * But we will use the array to save RSS context IDs.
516 if (BNXT_CHIP_THOR(bp))
517 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
519 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
521 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
525 rc = bnxt_alloc_hwrm_rings(bp);
527 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
531 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
533 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
537 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
540 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
541 if (bp->rx_cos_queue[i].id != 0xff) {
542 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
546 "Num pools more than FW profile\n");
550 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
556 rc = bnxt_mq_rx_configure(bp);
558 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
562 /* VNIC configuration */
563 for (i = 0; i < bp->nr_vnics; i++) {
564 rc = bnxt_setup_one_vnic(bp, i);
569 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
572 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
576 /* check and configure queue intr-vector mapping */
577 if ((rte_intr_cap_multiple(intr_handle) ||
578 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
579 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
580 intr_vector = bp->eth_dev->data->nb_rx_queues;
581 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
582 if (intr_vector > bp->rx_cp_nr_rings) {
583 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
587 rc = rte_intr_efd_enable(intr_handle, intr_vector);
592 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
593 intr_handle->intr_vec =
594 rte_zmalloc("intr_vec",
595 bp->eth_dev->data->nb_rx_queues *
597 if (intr_handle->intr_vec == NULL) {
598 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
599 " intr_vec", bp->eth_dev->data->nb_rx_queues);
603 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
604 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
605 intr_handle->intr_vec, intr_handle->nb_efd,
606 intr_handle->max_intr);
607 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
609 intr_handle->intr_vec[queue_id] =
610 vec + BNXT_RX_VEC_START;
611 if (vec < base + intr_handle->nb_efd - 1)
616 /* enable uio/vfio intr/eventfd mapping */
617 rc = rte_intr_enable(intr_handle);
618 #ifndef RTE_EXEC_ENV_FREEBSD
619 /* In FreeBSD OS, nic_uio driver does not support interrupts */
624 rc = bnxt_get_hwrm_link_config(bp, &new);
626 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
630 if (!bp->link_info.link_up) {
631 rc = bnxt_set_hwrm_link_config(bp, true);
634 "HWRM link config failure rc: %x\n", rc);
638 bnxt_print_link_info(bp->eth_dev);
640 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
642 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
647 rte_free(intr_handle->intr_vec);
649 rte_intr_efd_disable(intr_handle);
651 /* Some of the error status returned by FW may not be from errno.h */
658 static int bnxt_shutdown_nic(struct bnxt *bp)
660 bnxt_free_all_hwrm_resources(bp);
661 bnxt_free_all_filters(bp);
662 bnxt_free_all_vnics(bp);
667 * Device configuration and status function
670 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
671 struct rte_eth_dev_info *dev_info)
673 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
674 struct bnxt *bp = eth_dev->data->dev_private;
675 uint16_t max_vnics, i, j, vpool, vrxq;
676 unsigned int max_rx_rings;
679 rc = is_bnxt_in_error(bp);
684 dev_info->max_mac_addrs = bp->max_l2_ctx;
685 dev_info->max_hash_mac_addrs = 0;
687 /* PF/VF specifics */
689 dev_info->max_vfs = pdev->max_vfs;
691 max_rx_rings = BNXT_MAX_RINGS(bp);
692 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
693 dev_info->max_rx_queues = max_rx_rings;
694 dev_info->max_tx_queues = max_rx_rings;
695 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
696 dev_info->hash_key_size = 40;
697 max_vnics = bp->max_vnics;
700 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
701 dev_info->max_mtu = BNXT_MAX_MTU;
703 /* Fast path specifics */
704 dev_info->min_rx_bufsize = 1;
705 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
707 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
708 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
709 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
710 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
711 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
714 dev_info->default_rxconf = (struct rte_eth_rxconf) {
720 .rx_free_thresh = 32,
721 /* If no descriptors available, pkts are dropped by default */
725 dev_info->default_txconf = (struct rte_eth_txconf) {
731 .tx_free_thresh = 32,
734 eth_dev->data->dev_conf.intr_conf.lsc = 1;
736 eth_dev->data->dev_conf.intr_conf.rxq = 1;
737 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
738 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
739 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
740 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
745 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
746 * need further investigation.
750 vpool = 64; /* ETH_64_POOLS */
751 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
752 for (i = 0; i < 4; vpool >>= 1, i++) {
753 if (max_vnics > vpool) {
754 for (j = 0; j < 5; vrxq >>= 1, j++) {
755 if (dev_info->max_rx_queues > vrxq) {
761 /* Not enough resources to support VMDq */
765 /* Not enough resources to support VMDq */
769 dev_info->max_vmdq_pools = vpool;
770 dev_info->vmdq_queue_num = vrxq;
772 dev_info->vmdq_pool_base = 0;
773 dev_info->vmdq_queue_base = 0;
778 /* Configure the device based on the configuration provided */
779 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
781 struct bnxt *bp = eth_dev->data->dev_private;
782 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
785 bp->rx_queues = (void *)eth_dev->data->rx_queues;
786 bp->tx_queues = (void *)eth_dev->data->tx_queues;
787 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
788 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
790 rc = is_bnxt_in_error(bp);
794 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
795 rc = bnxt_hwrm_check_vf_rings(bp);
797 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
801 /* If a resource has already been allocated - in this case
802 * it is the async completion ring, free it. Reallocate it after
803 * resource reservation. This will ensure the resource counts
804 * are calculated correctly.
807 pthread_mutex_lock(&bp->def_cp_lock);
809 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
810 bnxt_disable_int(bp);
811 bnxt_free_cp_ring(bp, bp->async_cp_ring);
814 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
816 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
817 pthread_mutex_unlock(&bp->def_cp_lock);
821 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
822 rc = bnxt_alloc_async_cp_ring(bp);
824 pthread_mutex_unlock(&bp->def_cp_lock);
830 pthread_mutex_unlock(&bp->def_cp_lock);
832 /* legacy driver needs to get updated values */
833 rc = bnxt_hwrm_func_qcaps(bp);
835 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
840 /* Inherit new configurations */
841 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
842 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
843 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
844 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
845 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
849 if (BNXT_HAS_RING_GRPS(bp) &&
850 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
853 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
854 bp->max_vnics < eth_dev->data->nb_rx_queues)
857 bp->rx_cp_nr_rings = bp->rx_nr_rings;
858 bp->tx_cp_nr_rings = bp->tx_nr_rings;
860 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
861 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
862 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
864 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
866 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
867 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
869 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
875 "Insufficient resources to support requested config\n");
877 "Num Queues Requested: Tx %d, Rx %d\n",
878 eth_dev->data->nb_tx_queues,
879 eth_dev->data->nb_rx_queues);
881 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
882 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
883 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
887 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
889 struct rte_eth_link *link = ð_dev->data->dev_link;
891 if (link->link_status)
892 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
893 eth_dev->data->port_id,
894 (uint32_t)link->link_speed,
895 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
896 ("full-duplex") : ("half-duplex\n"));
898 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
899 eth_dev->data->port_id);
903 * Determine whether the current configuration requires support for scattered
904 * receive; return 1 if scattered receive is required and 0 if not.
906 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
911 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
914 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
915 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
917 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
918 RTE_PKTMBUF_HEADROOM);
919 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
925 static eth_rx_burst_t
926 bnxt_receive_function(struct rte_eth_dev *eth_dev)
928 struct bnxt *bp = eth_dev->data->dev_private;
931 #ifndef RTE_LIBRTE_IEEE1588
933 * Vector mode receive can be enabled only if scatter rx is not
934 * in use and rx offloads are limited to VLAN stripping and
937 if (!eth_dev->data->scattered_rx &&
938 !(eth_dev->data->dev_conf.rxmode.offloads &
939 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
940 DEV_RX_OFFLOAD_KEEP_CRC |
941 DEV_RX_OFFLOAD_JUMBO_FRAME |
942 DEV_RX_OFFLOAD_IPV4_CKSUM |
943 DEV_RX_OFFLOAD_UDP_CKSUM |
944 DEV_RX_OFFLOAD_TCP_CKSUM |
945 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
946 DEV_RX_OFFLOAD_RSS_HASH |
947 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
949 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
950 eth_dev->data->port_id);
951 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
952 return bnxt_recv_pkts_vec;
954 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
955 eth_dev->data->port_id);
957 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
958 eth_dev->data->port_id,
959 eth_dev->data->scattered_rx,
960 eth_dev->data->dev_conf.rxmode.offloads);
963 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
964 return bnxt_recv_pkts;
967 static eth_tx_burst_t
968 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
971 #ifndef RTE_LIBRTE_IEEE1588
973 * Vector mode transmit can be enabled only if not using scatter rx
976 if (!eth_dev->data->scattered_rx &&
977 !eth_dev->data->dev_conf.txmode.offloads) {
978 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
979 eth_dev->data->port_id);
980 return bnxt_xmit_pkts_vec;
982 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
983 eth_dev->data->port_id);
985 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
986 eth_dev->data->port_id,
987 eth_dev->data->scattered_rx,
988 eth_dev->data->dev_conf.txmode.offloads);
991 return bnxt_xmit_pkts;
994 static int bnxt_handle_if_change_status(struct bnxt *bp)
998 /* Since fw has undergone a reset and lost all contexts,
999 * set fatal flag to not issue hwrm during cleanup
1001 bp->flags |= BNXT_FLAG_FATAL_ERROR;
1002 bnxt_uninit_resources(bp, true);
1004 /* clear fatal flag so that re-init happens */
1005 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1006 rc = bnxt_init_resources(bp, true);
1008 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1013 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1015 struct bnxt *bp = eth_dev->data->dev_private;
1016 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1020 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1021 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1025 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1027 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1028 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1031 rc = bnxt_hwrm_if_change(bp, 1);
1033 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1034 rc = bnxt_handle_if_change_status(bp);
1039 bnxt_enable_int(bp);
1041 rc = bnxt_init_chip(bp);
1045 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1046 eth_dev->data->dev_started = 1;
1048 bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1050 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1051 vlan_mask |= ETH_VLAN_FILTER_MASK;
1052 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1053 vlan_mask |= ETH_VLAN_STRIP_MASK;
1054 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1058 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1059 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1061 pthread_mutex_lock(&bp->def_cp_lock);
1062 bnxt_schedule_fw_health_check(bp);
1063 pthread_mutex_unlock(&bp->def_cp_lock);
1071 bnxt_hwrm_if_change(bp, 0);
1072 bnxt_shutdown_nic(bp);
1073 bnxt_free_tx_mbufs(bp);
1074 bnxt_free_rx_mbufs(bp);
1075 eth_dev->data->dev_started = 0;
1079 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1081 struct bnxt *bp = eth_dev->data->dev_private;
1084 if (!bp->link_info.link_up)
1085 rc = bnxt_set_hwrm_link_config(bp, true);
1087 eth_dev->data->dev_link.link_status = 1;
1089 bnxt_print_link_info(eth_dev);
1093 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1095 struct bnxt *bp = eth_dev->data->dev_private;
1097 eth_dev->data->dev_link.link_status = 0;
1098 bnxt_set_hwrm_link_config(bp, false);
1099 bp->link_info.link_up = 0;
1104 /* Unload the driver, release resources */
1105 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1107 struct bnxt *bp = eth_dev->data->dev_private;
1108 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1109 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1112 bnxt_ulp_deinit(bp);
1114 eth_dev->data->dev_started = 0;
1115 /* Prevent crashes when queues are still in use */
1116 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1117 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1119 bnxt_disable_int(bp);
1121 /* disable uio/vfio intr/eventfd mapping */
1122 rte_intr_disable(intr_handle);
1124 bnxt_cancel_fw_health_check(bp);
1126 bnxt_dev_set_link_down_op(eth_dev);
1128 /* Wait for link to be reset and the async notification to process.
1129 * During reset recovery, there is no need to wait and
1130 * VF/NPAR functions do not have privilege to change PHY config.
1132 if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1133 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1135 /* Clean queue intr-vector mapping */
1136 rte_intr_efd_disable(intr_handle);
1137 if (intr_handle->intr_vec != NULL) {
1138 rte_free(intr_handle->intr_vec);
1139 intr_handle->intr_vec = NULL;
1142 bnxt_hwrm_port_clr_stats(bp);
1143 bnxt_free_tx_mbufs(bp);
1144 bnxt_free_rx_mbufs(bp);
1145 /* Process any remaining notifications in default completion queue */
1146 bnxt_int_handler(eth_dev);
1147 bnxt_shutdown_nic(bp);
1148 bnxt_hwrm_if_change(bp, 0);
1150 rte_free(bp->mark_table);
1151 bp->mark_table = NULL;
1153 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1154 bp->rx_cosq_cnt = 0;
1157 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1159 struct bnxt *bp = eth_dev->data->dev_private;
1161 /* cancel the recovery handler before remove dev */
1162 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1163 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1164 bnxt_cancel_fc_thread(bp);
1166 if (eth_dev->data->dev_started)
1167 bnxt_dev_stop_op(eth_dev);
1169 bnxt_uninit_resources(bp, false);
1171 eth_dev->dev_ops = NULL;
1172 eth_dev->rx_pkt_burst = NULL;
1173 eth_dev->tx_pkt_burst = NULL;
1175 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1176 bp->tx_mem_zone = NULL;
1177 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1178 bp->rx_mem_zone = NULL;
1180 rte_free(bp->pf.vf_info);
1181 bp->pf.vf_info = NULL;
1183 rte_free(bp->grp_info);
1184 bp->grp_info = NULL;
1187 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1190 struct bnxt *bp = eth_dev->data->dev_private;
1191 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1192 struct bnxt_vnic_info *vnic;
1193 struct bnxt_filter_info *filter, *temp_filter;
1196 if (is_bnxt_in_error(bp))
1200 * Loop through all VNICs from the specified filter flow pools to
1201 * remove the corresponding MAC addr filter
1203 for (i = 0; i < bp->nr_vnics; i++) {
1204 if (!(pool_mask & (1ULL << i)))
1207 vnic = &bp->vnic_info[i];
1208 filter = STAILQ_FIRST(&vnic->filter);
1210 temp_filter = STAILQ_NEXT(filter, next);
1211 if (filter->mac_index == index) {
1212 STAILQ_REMOVE(&vnic->filter, filter,
1213 bnxt_filter_info, next);
1214 bnxt_hwrm_clear_l2_filter(bp, filter);
1215 bnxt_free_filter(bp, filter);
1217 filter = temp_filter;
1222 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1223 struct rte_ether_addr *mac_addr, uint32_t index,
1226 struct bnxt_filter_info *filter;
1229 /* Attach requested MAC address to the new l2_filter */
1230 STAILQ_FOREACH(filter, &vnic->filter, next) {
1231 if (filter->mac_index == index) {
1233 "MAC addr already existed for pool %d\n",
1239 filter = bnxt_alloc_filter(bp);
1241 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1245 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1246 * if the MAC that's been programmed now is a different one, then,
1247 * copy that addr to filter->l2_addr
1250 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1251 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1253 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1255 filter->mac_index = index;
1256 if (filter->mac_index == 0)
1257 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1259 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1261 bnxt_free_filter(bp, filter);
1267 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1268 struct rte_ether_addr *mac_addr,
1269 uint32_t index, uint32_t pool)
1271 struct bnxt *bp = eth_dev->data->dev_private;
1272 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1275 rc = is_bnxt_in_error(bp);
1279 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1280 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1285 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1289 /* Filter settings will get applied when port is started */
1290 if (!eth_dev->data->dev_started)
1293 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1298 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1299 bool exp_link_status)
1302 struct bnxt *bp = eth_dev->data->dev_private;
1303 struct rte_eth_link new;
1304 int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1305 BNXT_LINK_DOWN_WAIT_CNT;
1307 rc = is_bnxt_in_error(bp);
1311 memset(&new, 0, sizeof(new));
1313 /* Retrieve link info from hardware */
1314 rc = bnxt_get_hwrm_link_config(bp, &new);
1316 new.link_speed = ETH_LINK_SPEED_100M;
1317 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1319 "Failed to retrieve link rc = 0x%x!\n", rc);
1323 if (!wait_to_complete || new.link_status == exp_link_status)
1326 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1330 /* Timed out or success */
1331 if (new.link_status != eth_dev->data->dev_link.link_status ||
1332 new.link_speed != eth_dev->data->dev_link.link_speed) {
1333 rte_eth_linkstatus_set(eth_dev, &new);
1335 _rte_eth_dev_callback_process(eth_dev,
1336 RTE_ETH_EVENT_INTR_LSC,
1339 bnxt_print_link_info(eth_dev);
1345 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1346 int wait_to_complete)
1348 return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1351 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1353 struct bnxt *bp = eth_dev->data->dev_private;
1354 struct bnxt_vnic_info *vnic;
1358 rc = is_bnxt_in_error(bp);
1362 /* Filter settings will get applied when port is started */
1363 if (!eth_dev->data->dev_started)
1366 if (bp->vnic_info == NULL)
1369 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1371 old_flags = vnic->flags;
1372 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1373 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1375 vnic->flags = old_flags;
1380 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1382 struct bnxt *bp = eth_dev->data->dev_private;
1383 struct bnxt_vnic_info *vnic;
1387 rc = is_bnxt_in_error(bp);
1391 /* Filter settings will get applied when port is started */
1392 if (!eth_dev->data->dev_started)
1395 if (bp->vnic_info == NULL)
1398 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1400 old_flags = vnic->flags;
1401 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1402 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1404 vnic->flags = old_flags;
1409 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1411 struct bnxt *bp = eth_dev->data->dev_private;
1412 struct bnxt_vnic_info *vnic;
1416 rc = is_bnxt_in_error(bp);
1420 /* Filter settings will get applied when port is started */
1421 if (!eth_dev->data->dev_started)
1424 if (bp->vnic_info == NULL)
1427 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1429 old_flags = vnic->flags;
1430 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1431 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1433 vnic->flags = old_flags;
1438 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1440 struct bnxt *bp = eth_dev->data->dev_private;
1441 struct bnxt_vnic_info *vnic;
1445 rc = is_bnxt_in_error(bp);
1449 /* Filter settings will get applied when port is started */
1450 if (!eth_dev->data->dev_started)
1453 if (bp->vnic_info == NULL)
1456 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1458 old_flags = vnic->flags;
1459 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1460 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1462 vnic->flags = old_flags;
1467 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1468 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1470 if (qid >= bp->rx_nr_rings)
1473 return bp->eth_dev->data->rx_queues[qid];
1476 /* Return rxq corresponding to a given rss table ring/group ID. */
1477 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1479 struct bnxt_rx_queue *rxq;
1482 if (!BNXT_HAS_RING_GRPS(bp)) {
1483 for (i = 0; i < bp->rx_nr_rings; i++) {
1484 rxq = bp->eth_dev->data->rx_queues[i];
1485 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1489 for (i = 0; i < bp->rx_nr_rings; i++) {
1490 if (bp->grp_info[i].fw_grp_id == fwr)
1495 return INVALID_HW_RING_ID;
1498 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1499 struct rte_eth_rss_reta_entry64 *reta_conf,
1502 struct bnxt *bp = eth_dev->data->dev_private;
1503 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1504 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1505 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1509 rc = is_bnxt_in_error(bp);
1513 if (!vnic->rss_table)
1516 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1519 if (reta_size != tbl_size) {
1520 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1521 "(%d) must equal the size supported by the hardware "
1522 "(%d)\n", reta_size, tbl_size);
1526 for (i = 0; i < reta_size; i++) {
1527 struct bnxt_rx_queue *rxq;
1529 idx = i / RTE_RETA_GROUP_SIZE;
1530 sft = i % RTE_RETA_GROUP_SIZE;
1532 if (!(reta_conf[idx].mask & (1ULL << sft)))
1535 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1537 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1541 if (BNXT_CHIP_THOR(bp)) {
1542 vnic->rss_table[i * 2] =
1543 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1544 vnic->rss_table[i * 2 + 1] =
1545 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1547 vnic->rss_table[i] =
1548 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1552 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1556 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1557 struct rte_eth_rss_reta_entry64 *reta_conf,
1560 struct bnxt *bp = eth_dev->data->dev_private;
1561 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1562 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1563 uint16_t idx, sft, i;
1566 rc = is_bnxt_in_error(bp);
1570 /* Retrieve from the default VNIC */
1573 if (!vnic->rss_table)
1576 if (reta_size != tbl_size) {
1577 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1578 "(%d) must equal the size supported by the hardware "
1579 "(%d)\n", reta_size, tbl_size);
1583 for (idx = 0, i = 0; i < reta_size; i++) {
1584 idx = i / RTE_RETA_GROUP_SIZE;
1585 sft = i % RTE_RETA_GROUP_SIZE;
1587 if (reta_conf[idx].mask & (1ULL << sft)) {
1590 if (BNXT_CHIP_THOR(bp))
1591 qid = bnxt_rss_to_qid(bp,
1592 vnic->rss_table[i * 2]);
1594 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1596 if (qid == INVALID_HW_RING_ID) {
1597 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1600 reta_conf[idx].reta[sft] = qid;
1607 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1608 struct rte_eth_rss_conf *rss_conf)
1610 struct bnxt *bp = eth_dev->data->dev_private;
1611 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1612 struct bnxt_vnic_info *vnic;
1615 rc = is_bnxt_in_error(bp);
1620 * If RSS enablement were different than dev_configure,
1621 * then return -EINVAL
1623 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1624 if (!rss_conf->rss_hf)
1625 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1627 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1631 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1632 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1634 /* Update the default RSS VNIC(s) */
1635 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1636 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1639 * If hashkey is not specified, use the previously configured
1642 if (!rss_conf->rss_key)
1645 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1647 "Invalid hashkey length, should be 16 bytes\n");
1650 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1653 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1657 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1658 struct rte_eth_rss_conf *rss_conf)
1660 struct bnxt *bp = eth_dev->data->dev_private;
1661 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1663 uint32_t hash_types;
1665 rc = is_bnxt_in_error(bp);
1669 /* RSS configuration is the same for all VNICs */
1670 if (vnic && vnic->rss_hash_key) {
1671 if (rss_conf->rss_key) {
1672 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1673 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1674 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1677 hash_types = vnic->hash_type;
1678 rss_conf->rss_hf = 0;
1679 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1680 rss_conf->rss_hf |= ETH_RSS_IPV4;
1681 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1683 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1684 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1686 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1688 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1689 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1691 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1693 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1694 rss_conf->rss_hf |= ETH_RSS_IPV6;
1695 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1697 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1698 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1700 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1702 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1703 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1705 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1709 "Unknwon RSS config from firmware (%08x), RSS disabled",
1714 rss_conf->rss_hf = 0;
1719 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1720 struct rte_eth_fc_conf *fc_conf)
1722 struct bnxt *bp = dev->data->dev_private;
1723 struct rte_eth_link link_info;
1726 rc = is_bnxt_in_error(bp);
1730 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1734 memset(fc_conf, 0, sizeof(*fc_conf));
1735 if (bp->link_info.auto_pause)
1736 fc_conf->autoneg = 1;
1737 switch (bp->link_info.pause) {
1739 fc_conf->mode = RTE_FC_NONE;
1741 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1742 fc_conf->mode = RTE_FC_TX_PAUSE;
1744 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1745 fc_conf->mode = RTE_FC_RX_PAUSE;
1747 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1748 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1749 fc_conf->mode = RTE_FC_FULL;
1755 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1756 struct rte_eth_fc_conf *fc_conf)
1758 struct bnxt *bp = dev->data->dev_private;
1761 rc = is_bnxt_in_error(bp);
1765 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1766 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1770 switch (fc_conf->mode) {
1772 bp->link_info.auto_pause = 0;
1773 bp->link_info.force_pause = 0;
1775 case RTE_FC_RX_PAUSE:
1776 if (fc_conf->autoneg) {
1777 bp->link_info.auto_pause =
1778 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1779 bp->link_info.force_pause = 0;
1781 bp->link_info.auto_pause = 0;
1782 bp->link_info.force_pause =
1783 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1786 case RTE_FC_TX_PAUSE:
1787 if (fc_conf->autoneg) {
1788 bp->link_info.auto_pause =
1789 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1790 bp->link_info.force_pause = 0;
1792 bp->link_info.auto_pause = 0;
1793 bp->link_info.force_pause =
1794 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1798 if (fc_conf->autoneg) {
1799 bp->link_info.auto_pause =
1800 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1801 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1802 bp->link_info.force_pause = 0;
1804 bp->link_info.auto_pause = 0;
1805 bp->link_info.force_pause =
1806 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1807 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1811 return bnxt_set_hwrm_link_config(bp, true);
1814 /* Add UDP tunneling port */
1816 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1817 struct rte_eth_udp_tunnel *udp_tunnel)
1819 struct bnxt *bp = eth_dev->data->dev_private;
1820 uint16_t tunnel_type = 0;
1823 rc = is_bnxt_in_error(bp);
1827 switch (udp_tunnel->prot_type) {
1828 case RTE_TUNNEL_TYPE_VXLAN:
1829 if (bp->vxlan_port_cnt) {
1830 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1831 udp_tunnel->udp_port);
1832 if (bp->vxlan_port != udp_tunnel->udp_port) {
1833 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1836 bp->vxlan_port_cnt++;
1840 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1841 bp->vxlan_port_cnt++;
1843 case RTE_TUNNEL_TYPE_GENEVE:
1844 if (bp->geneve_port_cnt) {
1845 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1846 udp_tunnel->udp_port);
1847 if (bp->geneve_port != udp_tunnel->udp_port) {
1848 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1851 bp->geneve_port_cnt++;
1855 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1856 bp->geneve_port_cnt++;
1859 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1862 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1868 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1869 struct rte_eth_udp_tunnel *udp_tunnel)
1871 struct bnxt *bp = eth_dev->data->dev_private;
1872 uint16_t tunnel_type = 0;
1876 rc = is_bnxt_in_error(bp);
1880 switch (udp_tunnel->prot_type) {
1881 case RTE_TUNNEL_TYPE_VXLAN:
1882 if (!bp->vxlan_port_cnt) {
1883 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1886 if (bp->vxlan_port != udp_tunnel->udp_port) {
1887 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1888 udp_tunnel->udp_port, bp->vxlan_port);
1891 if (--bp->vxlan_port_cnt)
1895 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1896 port = bp->vxlan_fw_dst_port_id;
1898 case RTE_TUNNEL_TYPE_GENEVE:
1899 if (!bp->geneve_port_cnt) {
1900 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1903 if (bp->geneve_port != udp_tunnel->udp_port) {
1904 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1905 udp_tunnel->udp_port, bp->geneve_port);
1908 if (--bp->geneve_port_cnt)
1912 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1913 port = bp->geneve_fw_dst_port_id;
1916 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1920 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1923 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1926 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1927 bp->geneve_port = 0;
1932 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1934 struct bnxt_filter_info *filter;
1935 struct bnxt_vnic_info *vnic;
1937 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1939 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1940 filter = STAILQ_FIRST(&vnic->filter);
1942 /* Search for this matching MAC+VLAN filter */
1943 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
1944 /* Delete the filter */
1945 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1948 STAILQ_REMOVE(&vnic->filter, filter,
1949 bnxt_filter_info, next);
1950 bnxt_free_filter(bp, filter);
1952 "Deleted vlan filter for %d\n",
1956 filter = STAILQ_NEXT(filter, next);
1961 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1963 struct bnxt_filter_info *filter;
1964 struct bnxt_vnic_info *vnic;
1966 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1967 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1968 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1970 /* Implementation notes on the use of VNIC in this command:
1972 * By default, these filters belong to default vnic for the function.
1973 * Once these filters are set up, only destination VNIC can be modified.
1974 * If the destination VNIC is not specified in this command,
1975 * then the HWRM shall only create an l2 context id.
1978 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1979 filter = STAILQ_FIRST(&vnic->filter);
1980 /* Check if the VLAN has already been added */
1982 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
1985 filter = STAILQ_NEXT(filter, next);
1988 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1989 * command to create MAC+VLAN filter with the right flags, enables set.
1991 filter = bnxt_alloc_filter(bp);
1994 "MAC/VLAN filter alloc failed\n");
1997 /* MAC + VLAN ID filter */
1998 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1999 * untagged packets are received
2001 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2002 * packets and only the programmed vlan's packets are received
2004 filter->l2_ivlan = vlan_id;
2005 filter->l2_ivlan_mask = 0x0FFF;
2006 filter->enables |= en;
2007 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2009 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2011 /* Free the newly allocated filter as we were
2012 * not able to create the filter in hardware.
2014 bnxt_free_filter(bp, filter);
2018 filter->mac_index = 0;
2019 /* Add this new filter to the list */
2021 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2023 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2026 "Added Vlan filter for %d\n", vlan_id);
2030 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2031 uint16_t vlan_id, int on)
2033 struct bnxt *bp = eth_dev->data->dev_private;
2036 rc = is_bnxt_in_error(bp);
2040 /* These operations apply to ALL existing MAC/VLAN filters */
2042 return bnxt_add_vlan_filter(bp, vlan_id);
2044 return bnxt_del_vlan_filter(bp, vlan_id);
2047 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2048 struct bnxt_vnic_info *vnic)
2050 struct bnxt_filter_info *filter;
2053 filter = STAILQ_FIRST(&vnic->filter);
2055 if (filter->mac_index == 0 &&
2056 !memcmp(filter->l2_addr, bp->mac_addr,
2057 RTE_ETHER_ADDR_LEN)) {
2058 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2060 STAILQ_REMOVE(&vnic->filter, filter,
2061 bnxt_filter_info, next);
2062 bnxt_free_filter(bp, filter);
2066 filter = STAILQ_NEXT(filter, next);
2072 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2074 struct bnxt_vnic_info *vnic;
2078 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2079 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2080 /* Remove any VLAN filters programmed */
2081 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2082 bnxt_del_vlan_filter(bp, i);
2084 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2088 /* Default filter will allow packets that match the
2089 * dest mac. So, it has to be deleted, otherwise, we
2090 * will endup receiving vlan packets for which the
2091 * filter is not programmed, when hw-vlan-filter
2092 * configuration is ON
2094 bnxt_del_dflt_mac_filter(bp, vnic);
2095 /* This filter will allow only untagged packets */
2096 bnxt_add_vlan_filter(bp, 0);
2098 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2099 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2104 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2106 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2110 /* Destroy vnic filters and vnic */
2111 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2112 DEV_RX_OFFLOAD_VLAN_FILTER) {
2113 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2114 bnxt_del_vlan_filter(bp, i);
2116 bnxt_del_dflt_mac_filter(bp, vnic);
2118 rc = bnxt_hwrm_vnic_free(bp, vnic);
2122 rte_free(vnic->fw_grp_ids);
2123 vnic->fw_grp_ids = NULL;
2129 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2131 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2134 /* Destroy, recreate and reconfigure the default vnic */
2135 rc = bnxt_free_one_vnic(bp, 0);
2139 /* default vnic 0 */
2140 rc = bnxt_setup_one_vnic(bp, 0);
2144 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2145 DEV_RX_OFFLOAD_VLAN_FILTER) {
2146 rc = bnxt_add_vlan_filter(bp, 0);
2149 rc = bnxt_restore_vlan_filters(bp);
2153 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2158 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2162 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2163 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2169 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2171 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2172 struct bnxt *bp = dev->data->dev_private;
2175 rc = is_bnxt_in_error(bp);
2179 /* Filter settings will get applied when port is started */
2180 if (!dev->data->dev_started)
2183 if (mask & ETH_VLAN_FILTER_MASK) {
2184 /* Enable or disable VLAN filtering */
2185 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2190 if (mask & ETH_VLAN_STRIP_MASK) {
2191 /* Enable or disable VLAN stripping */
2192 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2197 if (mask & ETH_VLAN_EXTEND_MASK) {
2198 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2199 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2201 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2208 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2211 struct bnxt *bp = dev->data->dev_private;
2212 int qinq = dev->data->dev_conf.rxmode.offloads &
2213 DEV_RX_OFFLOAD_VLAN_EXTEND;
2215 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2216 vlan_type != ETH_VLAN_TYPE_OUTER) {
2218 "Unsupported vlan type.");
2223 "QinQ not enabled. Needs to be ON as we can "
2224 "accelerate only outer vlan\n");
2228 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2230 case RTE_ETHER_TYPE_QINQ:
2232 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2234 case RTE_ETHER_TYPE_VLAN:
2236 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2240 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2244 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2248 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2251 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2254 bp->outer_tpid_bd |= tpid;
2255 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2256 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2258 "Can accelerate only outer vlan in QinQ\n");
2266 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2267 struct rte_ether_addr *addr)
2269 struct bnxt *bp = dev->data->dev_private;
2270 /* Default Filter is tied to VNIC 0 */
2271 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2274 rc = is_bnxt_in_error(bp);
2278 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2281 if (rte_is_zero_ether_addr(addr))
2284 /* Filter settings will get applied when port is started */
2285 if (!dev->data->dev_started)
2288 /* Check if the requested MAC is already added */
2289 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2292 /* Destroy filter and re-create it */
2293 bnxt_del_dflt_mac_filter(bp, vnic);
2295 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2296 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2297 /* This filter will allow only untagged packets */
2298 rc = bnxt_add_vlan_filter(bp, 0);
2300 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2303 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2308 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2309 struct rte_ether_addr *mc_addr_set,
2310 uint32_t nb_mc_addr)
2312 struct bnxt *bp = eth_dev->data->dev_private;
2313 char *mc_addr_list = (char *)mc_addr_set;
2314 struct bnxt_vnic_info *vnic;
2315 uint32_t off = 0, i = 0;
2318 rc = is_bnxt_in_error(bp);
2322 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2324 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2325 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2329 /* TODO Check for Duplicate mcast addresses */
2330 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2331 for (i = 0; i < nb_mc_addr; i++) {
2332 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2333 RTE_ETHER_ADDR_LEN);
2334 off += RTE_ETHER_ADDR_LEN;
2337 vnic->mc_addr_cnt = i;
2338 if (vnic->mc_addr_cnt)
2339 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2341 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2344 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2348 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2350 struct bnxt *bp = dev->data->dev_private;
2351 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2352 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2353 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2356 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2357 fw_major, fw_minor, fw_updt);
2359 ret += 1; /* add the size of '\0' */
2360 if (fw_size < (uint32_t)ret)
2367 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2368 struct rte_eth_rxq_info *qinfo)
2370 struct bnxt *bp = dev->data->dev_private;
2371 struct bnxt_rx_queue *rxq;
2373 if (is_bnxt_in_error(bp))
2376 rxq = dev->data->rx_queues[queue_id];
2378 qinfo->mp = rxq->mb_pool;
2379 qinfo->scattered_rx = dev->data->scattered_rx;
2380 qinfo->nb_desc = rxq->nb_rx_desc;
2382 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2383 qinfo->conf.rx_drop_en = 0;
2384 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2388 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2389 struct rte_eth_txq_info *qinfo)
2391 struct bnxt *bp = dev->data->dev_private;
2392 struct bnxt_tx_queue *txq;
2394 if (is_bnxt_in_error(bp))
2397 txq = dev->data->tx_queues[queue_id];
2399 qinfo->nb_desc = txq->nb_tx_desc;
2401 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2402 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2403 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2405 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2406 qinfo->conf.tx_rs_thresh = 0;
2407 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2410 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2412 struct bnxt *bp = eth_dev->data->dev_private;
2413 uint32_t new_pkt_size;
2417 rc = is_bnxt_in_error(bp);
2421 /* Exit if receive queues are not configured yet */
2422 if (!eth_dev->data->nb_rx_queues)
2425 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2426 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2430 * If vector-mode tx/rx is active, disallow any MTU change that would
2431 * require scattered receive support.
2433 if (eth_dev->data->dev_started &&
2434 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2435 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2437 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2439 "MTU change would require scattered rx support. ");
2440 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2445 if (new_mtu > RTE_ETHER_MTU) {
2446 bp->flags |= BNXT_FLAG_JUMBO;
2447 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2448 DEV_RX_OFFLOAD_JUMBO_FRAME;
2450 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2451 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2452 bp->flags &= ~BNXT_FLAG_JUMBO;
2455 /* Is there a change in mtu setting? */
2456 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2459 for (i = 0; i < bp->nr_vnics; i++) {
2460 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2463 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2464 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2468 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2469 size -= RTE_PKTMBUF_HEADROOM;
2471 if (size < new_mtu) {
2472 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2479 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2481 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2487 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2489 struct bnxt *bp = dev->data->dev_private;
2490 uint16_t vlan = bp->vlan;
2493 rc = is_bnxt_in_error(bp);
2497 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2499 "PVID cannot be modified for this function\n");
2502 bp->vlan = on ? pvid : 0;
2504 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2511 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2513 struct bnxt *bp = dev->data->dev_private;
2516 rc = is_bnxt_in_error(bp);
2520 return bnxt_hwrm_port_led_cfg(bp, true);
2524 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2526 struct bnxt *bp = dev->data->dev_private;
2529 rc = is_bnxt_in_error(bp);
2533 return bnxt_hwrm_port_led_cfg(bp, false);
2537 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2539 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2540 uint32_t desc = 0, raw_cons = 0, cons;
2541 struct bnxt_cp_ring_info *cpr;
2542 struct bnxt_rx_queue *rxq;
2543 struct rx_pkt_cmpl *rxcmp;
2546 rc = is_bnxt_in_error(bp);
2550 rxq = dev->data->rx_queues[rx_queue_id];
2552 raw_cons = cpr->cp_raw_cons;
2555 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2556 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2557 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2559 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2571 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2573 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2574 struct bnxt_rx_ring_info *rxr;
2575 struct bnxt_cp_ring_info *cpr;
2576 struct bnxt_sw_rx_bd *rx_buf;
2577 struct rx_pkt_cmpl *rxcmp;
2578 uint32_t cons, cp_cons;
2584 rc = is_bnxt_in_error(rxq->bp);
2591 if (offset >= rxq->nb_rx_desc)
2594 cons = RING_CMP(cpr->cp_ring_struct, offset);
2595 cp_cons = cpr->cp_raw_cons;
2596 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2598 if (cons > cp_cons) {
2599 if (CMPL_VALID(rxcmp, cpr->valid))
2600 return RTE_ETH_RX_DESC_DONE;
2602 if (CMPL_VALID(rxcmp, !cpr->valid))
2603 return RTE_ETH_RX_DESC_DONE;
2605 rx_buf = &rxr->rx_buf_ring[cons];
2606 if (rx_buf->mbuf == NULL)
2607 return RTE_ETH_RX_DESC_UNAVAIL;
2610 return RTE_ETH_RX_DESC_AVAIL;
2614 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2616 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2617 struct bnxt_tx_ring_info *txr;
2618 struct bnxt_cp_ring_info *cpr;
2619 struct bnxt_sw_tx_bd *tx_buf;
2620 struct tx_pkt_cmpl *txcmp;
2621 uint32_t cons, cp_cons;
2627 rc = is_bnxt_in_error(txq->bp);
2634 if (offset >= txq->nb_tx_desc)
2637 cons = RING_CMP(cpr->cp_ring_struct, offset);
2638 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2639 cp_cons = cpr->cp_raw_cons;
2641 if (cons > cp_cons) {
2642 if (CMPL_VALID(txcmp, cpr->valid))
2643 return RTE_ETH_TX_DESC_UNAVAIL;
2645 if (CMPL_VALID(txcmp, !cpr->valid))
2646 return RTE_ETH_TX_DESC_UNAVAIL;
2648 tx_buf = &txr->tx_buf_ring[cons];
2649 if (tx_buf->mbuf == NULL)
2650 return RTE_ETH_TX_DESC_DONE;
2652 return RTE_ETH_TX_DESC_FULL;
2655 static struct bnxt_filter_info *
2656 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2657 struct rte_eth_ethertype_filter *efilter,
2658 struct bnxt_vnic_info *vnic0,
2659 struct bnxt_vnic_info *vnic,
2662 struct bnxt_filter_info *mfilter = NULL;
2666 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2667 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2668 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2669 " ethertype filter.", efilter->ether_type);
2673 if (efilter->queue >= bp->rx_nr_rings) {
2674 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2679 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2680 vnic = &bp->vnic_info[efilter->queue];
2682 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2687 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2688 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2689 if ((!memcmp(efilter->mac_addr.addr_bytes,
2690 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2692 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2693 mfilter->ethertype == efilter->ether_type)) {
2699 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2700 if ((!memcmp(efilter->mac_addr.addr_bytes,
2701 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2702 mfilter->ethertype == efilter->ether_type &&
2704 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2718 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2719 enum rte_filter_op filter_op,
2722 struct bnxt *bp = dev->data->dev_private;
2723 struct rte_eth_ethertype_filter *efilter =
2724 (struct rte_eth_ethertype_filter *)arg;
2725 struct bnxt_filter_info *bfilter, *filter1;
2726 struct bnxt_vnic_info *vnic, *vnic0;
2729 if (filter_op == RTE_ETH_FILTER_NOP)
2733 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2738 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2739 vnic = &bp->vnic_info[efilter->queue];
2741 switch (filter_op) {
2742 case RTE_ETH_FILTER_ADD:
2743 bnxt_match_and_validate_ether_filter(bp, efilter,
2748 bfilter = bnxt_get_unused_filter(bp);
2749 if (bfilter == NULL) {
2751 "Not enough resources for a new filter.\n");
2754 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2755 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2756 RTE_ETHER_ADDR_LEN);
2757 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2758 RTE_ETHER_ADDR_LEN);
2759 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2760 bfilter->ethertype = efilter->ether_type;
2761 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2763 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2764 if (filter1 == NULL) {
2769 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2770 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2772 bfilter->dst_id = vnic->fw_vnic_id;
2774 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2776 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2779 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2782 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2784 case RTE_ETH_FILTER_DELETE:
2785 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2787 if (ret == -EEXIST) {
2788 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2790 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2792 bnxt_free_filter(bp, filter1);
2793 } else if (ret == 0) {
2794 PMD_DRV_LOG(ERR, "No matching filter found\n");
2798 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2804 bnxt_free_filter(bp, bfilter);
2810 parse_ntuple_filter(struct bnxt *bp,
2811 struct rte_eth_ntuple_filter *nfilter,
2812 struct bnxt_filter_info *bfilter)
2816 if (nfilter->queue >= bp->rx_nr_rings) {
2817 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2821 switch (nfilter->dst_port_mask) {
2823 bfilter->dst_port_mask = -1;
2824 bfilter->dst_port = nfilter->dst_port;
2825 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2826 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2829 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2833 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2834 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2836 switch (nfilter->proto_mask) {
2838 if (nfilter->proto == 17) /* IPPROTO_UDP */
2839 bfilter->ip_protocol = 17;
2840 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2841 bfilter->ip_protocol = 6;
2844 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2847 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2851 switch (nfilter->dst_ip_mask) {
2853 bfilter->dst_ipaddr_mask[0] = -1;
2854 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2855 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2856 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2859 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2863 switch (nfilter->src_ip_mask) {
2865 bfilter->src_ipaddr_mask[0] = -1;
2866 bfilter->src_ipaddr[0] = nfilter->src_ip;
2867 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2868 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2871 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2875 switch (nfilter->src_port_mask) {
2877 bfilter->src_port_mask = -1;
2878 bfilter->src_port = nfilter->src_port;
2879 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2880 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2883 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2887 bfilter->enables = en;
2891 static struct bnxt_filter_info*
2892 bnxt_match_ntuple_filter(struct bnxt *bp,
2893 struct bnxt_filter_info *bfilter,
2894 struct bnxt_vnic_info **mvnic)
2896 struct bnxt_filter_info *mfilter = NULL;
2899 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2900 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2901 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2902 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2903 bfilter->src_ipaddr_mask[0] ==
2904 mfilter->src_ipaddr_mask[0] &&
2905 bfilter->src_port == mfilter->src_port &&
2906 bfilter->src_port_mask == mfilter->src_port_mask &&
2907 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2908 bfilter->dst_ipaddr_mask[0] ==
2909 mfilter->dst_ipaddr_mask[0] &&
2910 bfilter->dst_port == mfilter->dst_port &&
2911 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2912 bfilter->flags == mfilter->flags &&
2913 bfilter->enables == mfilter->enables) {
2924 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2925 struct rte_eth_ntuple_filter *nfilter,
2926 enum rte_filter_op filter_op)
2928 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2929 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2932 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2933 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2937 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2938 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2942 bfilter = bnxt_get_unused_filter(bp);
2943 if (bfilter == NULL) {
2945 "Not enough resources for a new filter.\n");
2948 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2952 vnic = &bp->vnic_info[nfilter->queue];
2953 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2954 filter1 = STAILQ_FIRST(&vnic0->filter);
2955 if (filter1 == NULL) {
2960 bfilter->dst_id = vnic->fw_vnic_id;
2961 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2963 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2964 bfilter->ethertype = 0x800;
2965 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2967 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2969 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2970 bfilter->dst_id == mfilter->dst_id) {
2971 PMD_DRV_LOG(ERR, "filter exists.\n");
2974 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2975 bfilter->dst_id != mfilter->dst_id) {
2976 mfilter->dst_id = vnic->fw_vnic_id;
2977 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2978 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2979 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2980 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2981 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2984 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2985 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2990 if (filter_op == RTE_ETH_FILTER_ADD) {
2991 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2992 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2995 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2997 if (mfilter == NULL) {
2998 /* This should not happen. But for Coverity! */
3002 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3004 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3005 bnxt_free_filter(bp, mfilter);
3006 bnxt_free_filter(bp, bfilter);
3011 bnxt_free_filter(bp, bfilter);
3016 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3017 enum rte_filter_op filter_op,
3020 struct bnxt *bp = dev->data->dev_private;
3023 if (filter_op == RTE_ETH_FILTER_NOP)
3027 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3032 switch (filter_op) {
3033 case RTE_ETH_FILTER_ADD:
3034 ret = bnxt_cfg_ntuple_filter(bp,
3035 (struct rte_eth_ntuple_filter *)arg,
3038 case RTE_ETH_FILTER_DELETE:
3039 ret = bnxt_cfg_ntuple_filter(bp,
3040 (struct rte_eth_ntuple_filter *)arg,
3044 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3052 bnxt_parse_fdir_filter(struct bnxt *bp,
3053 struct rte_eth_fdir_filter *fdir,
3054 struct bnxt_filter_info *filter)
3056 enum rte_fdir_mode fdir_mode =
3057 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3058 struct bnxt_vnic_info *vnic0, *vnic;
3059 struct bnxt_filter_info *filter1;
3063 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3066 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3067 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3069 switch (fdir->input.flow_type) {
3070 case RTE_ETH_FLOW_IPV4:
3071 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3073 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3074 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3075 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3076 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3077 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3078 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3079 filter->ip_addr_type =
3080 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3081 filter->src_ipaddr_mask[0] = 0xffffffff;
3082 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3083 filter->dst_ipaddr_mask[0] = 0xffffffff;
3084 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3085 filter->ethertype = 0x800;
3086 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3088 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3089 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3090 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3091 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3092 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3093 filter->dst_port_mask = 0xffff;
3094 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3095 filter->src_port_mask = 0xffff;
3096 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3097 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3098 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3099 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3100 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3101 filter->ip_protocol = 6;
3102 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3103 filter->ip_addr_type =
3104 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3105 filter->src_ipaddr_mask[0] = 0xffffffff;
3106 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3107 filter->dst_ipaddr_mask[0] = 0xffffffff;
3108 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3109 filter->ethertype = 0x800;
3110 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3112 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3113 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3114 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3115 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3116 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3117 filter->dst_port_mask = 0xffff;
3118 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3119 filter->src_port_mask = 0xffff;
3120 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3121 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3122 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3123 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3124 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3125 filter->ip_protocol = 17;
3126 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3127 filter->ip_addr_type =
3128 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3129 filter->src_ipaddr_mask[0] = 0xffffffff;
3130 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3131 filter->dst_ipaddr_mask[0] = 0xffffffff;
3132 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3133 filter->ethertype = 0x800;
3134 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3136 case RTE_ETH_FLOW_IPV6:
3137 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3139 filter->ip_addr_type =
3140 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3141 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3142 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3143 rte_memcpy(filter->src_ipaddr,
3144 fdir->input.flow.ipv6_flow.src_ip, 16);
3145 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3146 rte_memcpy(filter->dst_ipaddr,
3147 fdir->input.flow.ipv6_flow.dst_ip, 16);
3148 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3149 memset(filter->dst_ipaddr_mask, 0xff, 16);
3150 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3151 memset(filter->src_ipaddr_mask, 0xff, 16);
3152 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3153 filter->ethertype = 0x86dd;
3154 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3156 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3157 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3158 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3159 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3160 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3161 filter->dst_port_mask = 0xffff;
3162 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3163 filter->src_port_mask = 0xffff;
3164 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3165 filter->ip_addr_type =
3166 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3167 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3168 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3169 rte_memcpy(filter->src_ipaddr,
3170 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3171 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3172 rte_memcpy(filter->dst_ipaddr,
3173 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3174 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3175 memset(filter->dst_ipaddr_mask, 0xff, 16);
3176 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3177 memset(filter->src_ipaddr_mask, 0xff, 16);
3178 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3179 filter->ethertype = 0x86dd;
3180 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3182 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3183 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3184 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3185 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3186 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3187 filter->dst_port_mask = 0xffff;
3188 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3189 filter->src_port_mask = 0xffff;
3190 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3191 filter->ip_addr_type =
3192 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3193 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3194 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3195 rte_memcpy(filter->src_ipaddr,
3196 fdir->input.flow.udp6_flow.ip.src_ip, 16);
3197 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3198 rte_memcpy(filter->dst_ipaddr,
3199 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3200 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3201 memset(filter->dst_ipaddr_mask, 0xff, 16);
3202 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3203 memset(filter->src_ipaddr_mask, 0xff, 16);
3204 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3205 filter->ethertype = 0x86dd;
3206 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3208 case RTE_ETH_FLOW_L2_PAYLOAD:
3209 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3210 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3212 case RTE_ETH_FLOW_VXLAN:
3213 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3215 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3216 filter->tunnel_type =
3217 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3218 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3220 case RTE_ETH_FLOW_NVGRE:
3221 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3223 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3224 filter->tunnel_type =
3225 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3226 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3228 case RTE_ETH_FLOW_UNKNOWN:
3229 case RTE_ETH_FLOW_RAW:
3230 case RTE_ETH_FLOW_FRAG_IPV4:
3231 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3232 case RTE_ETH_FLOW_FRAG_IPV6:
3233 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3234 case RTE_ETH_FLOW_IPV6_EX:
3235 case RTE_ETH_FLOW_IPV6_TCP_EX:
3236 case RTE_ETH_FLOW_IPV6_UDP_EX:
3237 case RTE_ETH_FLOW_GENEVE:
3243 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3244 vnic = &bp->vnic_info[fdir->action.rx_queue];
3246 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3250 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3251 rte_memcpy(filter->dst_macaddr,
3252 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3253 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3256 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3257 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3258 filter1 = STAILQ_FIRST(&vnic0->filter);
3259 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3261 filter->dst_id = vnic->fw_vnic_id;
3262 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3263 if (filter->dst_macaddr[i] == 0x00)
3264 filter1 = STAILQ_FIRST(&vnic0->filter);
3266 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3269 if (filter1 == NULL)
3272 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3273 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3275 filter->enables = en;
3280 static struct bnxt_filter_info *
3281 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3282 struct bnxt_vnic_info **mvnic)
3284 struct bnxt_filter_info *mf = NULL;
3287 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3288 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3290 STAILQ_FOREACH(mf, &vnic->filter, next) {
3291 if (mf->filter_type == nf->filter_type &&
3292 mf->flags == nf->flags &&
3293 mf->src_port == nf->src_port &&
3294 mf->src_port_mask == nf->src_port_mask &&
3295 mf->dst_port == nf->dst_port &&
3296 mf->dst_port_mask == nf->dst_port_mask &&
3297 mf->ip_protocol == nf->ip_protocol &&
3298 mf->ip_addr_type == nf->ip_addr_type &&
3299 mf->ethertype == nf->ethertype &&
3300 mf->vni == nf->vni &&
3301 mf->tunnel_type == nf->tunnel_type &&
3302 mf->l2_ovlan == nf->l2_ovlan &&
3303 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3304 mf->l2_ivlan == nf->l2_ivlan &&
3305 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3306 !memcmp(mf->l2_addr, nf->l2_addr,
3307 RTE_ETHER_ADDR_LEN) &&
3308 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3309 RTE_ETHER_ADDR_LEN) &&
3310 !memcmp(mf->src_macaddr, nf->src_macaddr,
3311 RTE_ETHER_ADDR_LEN) &&
3312 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3313 RTE_ETHER_ADDR_LEN) &&
3314 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3315 sizeof(nf->src_ipaddr)) &&
3316 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3317 sizeof(nf->src_ipaddr_mask)) &&
3318 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3319 sizeof(nf->dst_ipaddr)) &&
3320 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3321 sizeof(nf->dst_ipaddr_mask))) {
3332 bnxt_fdir_filter(struct rte_eth_dev *dev,
3333 enum rte_filter_op filter_op,
3336 struct bnxt *bp = dev->data->dev_private;
3337 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
3338 struct bnxt_filter_info *filter, *match;
3339 struct bnxt_vnic_info *vnic, *mvnic;
3342 if (filter_op == RTE_ETH_FILTER_NOP)
3345 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3348 switch (filter_op) {
3349 case RTE_ETH_FILTER_ADD:
3350 case RTE_ETH_FILTER_DELETE:
3352 filter = bnxt_get_unused_filter(bp);
3353 if (filter == NULL) {
3355 "Not enough resources for a new flow.\n");
3359 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3362 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3364 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3365 vnic = &bp->vnic_info[0];
3367 vnic = &bp->vnic_info[fdir->action.rx_queue];
3369 match = bnxt_match_fdir(bp, filter, &mvnic);
3370 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3371 if (match->dst_id == vnic->fw_vnic_id) {
3372 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3376 match->dst_id = vnic->fw_vnic_id;
3377 ret = bnxt_hwrm_set_ntuple_filter(bp,
3380 STAILQ_REMOVE(&mvnic->filter, match,
3381 bnxt_filter_info, next);
3382 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3384 "Filter with matching pattern exist\n");
3386 "Updated it to new destination q\n");
3390 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3391 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3396 if (filter_op == RTE_ETH_FILTER_ADD) {
3397 ret = bnxt_hwrm_set_ntuple_filter(bp,
3402 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3404 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3405 STAILQ_REMOVE(&vnic->filter, match,
3406 bnxt_filter_info, next);
3407 bnxt_free_filter(bp, match);
3408 bnxt_free_filter(bp, filter);
3411 case RTE_ETH_FILTER_FLUSH:
3412 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3413 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3415 STAILQ_FOREACH(filter, &vnic->filter, next) {
3416 if (filter->filter_type ==
3417 HWRM_CFA_NTUPLE_FILTER) {
3419 bnxt_hwrm_clear_ntuple_filter(bp,
3421 STAILQ_REMOVE(&vnic->filter, filter,
3422 bnxt_filter_info, next);
3427 case RTE_ETH_FILTER_UPDATE:
3428 case RTE_ETH_FILTER_STATS:
3429 case RTE_ETH_FILTER_INFO:
3430 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3433 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3440 bnxt_free_filter(bp, filter);
3445 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3446 enum rte_filter_type filter_type,
3447 enum rte_filter_op filter_op, void *arg)
3449 struct bnxt *bp = dev->data->dev_private;
3452 ret = is_bnxt_in_error(dev->data->dev_private);
3456 switch (filter_type) {
3457 case RTE_ETH_FILTER_TUNNEL:
3459 "filter type: %d: To be implemented\n", filter_type);
3461 case RTE_ETH_FILTER_FDIR:
3462 ret = bnxt_fdir_filter(dev, filter_op, arg);
3464 case RTE_ETH_FILTER_NTUPLE:
3465 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3467 case RTE_ETH_FILTER_ETHERTYPE:
3468 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3470 case RTE_ETH_FILTER_GENERIC:
3471 if (filter_op != RTE_ETH_FILTER_GET)
3474 *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3476 *(const void **)arg = &bnxt_flow_ops;
3480 "Filter type (%d) not supported", filter_type);
3487 static const uint32_t *
3488 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3490 static const uint32_t ptypes[] = {
3491 RTE_PTYPE_L2_ETHER_VLAN,
3492 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3493 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3497 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3498 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3499 RTE_PTYPE_INNER_L4_ICMP,
3500 RTE_PTYPE_INNER_L4_TCP,
3501 RTE_PTYPE_INNER_L4_UDP,
3505 if (!dev->rx_pkt_burst)
3511 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3514 uint32_t reg_base = *reg_arr & 0xfffff000;
3518 for (i = 0; i < count; i++) {
3519 if ((reg_arr[i] & 0xfffff000) != reg_base)
3522 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3523 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3527 static int bnxt_map_ptp_regs(struct bnxt *bp)
3529 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3533 reg_arr = ptp->rx_regs;
3534 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3538 reg_arr = ptp->tx_regs;
3539 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3543 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3544 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3546 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3547 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3552 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3554 rte_write32(0, (uint8_t *)bp->bar0 +
3555 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3556 rte_write32(0, (uint8_t *)bp->bar0 +
3557 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3560 static uint64_t bnxt_cc_read(struct bnxt *bp)
3564 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3565 BNXT_GRCPF_REG_SYNC_TIME));
3566 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3567 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3571 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3573 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3576 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3577 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3578 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3581 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3582 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3583 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3584 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3585 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3586 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3591 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3593 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3594 struct bnxt_pf_info *pf = &bp->pf;
3601 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3602 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3603 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3606 port_id = pf->port_id;
3607 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3608 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3610 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3611 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3612 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3613 /* bnxt_clr_rx_ts(bp); TBD */
3617 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3618 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3619 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3620 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3626 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3629 struct bnxt *bp = dev->data->dev_private;
3630 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3635 ns = rte_timespec_to_ns(ts);
3636 /* Set the timecounters to a new value. */
3643 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3645 struct bnxt *bp = dev->data->dev_private;
3646 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3647 uint64_t ns, systime_cycles = 0;
3653 if (BNXT_CHIP_THOR(bp))
3654 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3657 systime_cycles = bnxt_cc_read(bp);
3659 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3660 *ts = rte_ns_to_timespec(ns);
3665 bnxt_timesync_enable(struct rte_eth_dev *dev)
3667 struct bnxt *bp = dev->data->dev_private;
3668 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3676 ptp->tx_tstamp_en = 1;
3677 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3679 rc = bnxt_hwrm_ptp_cfg(bp);
3683 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3684 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3685 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3687 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3688 ptp->tc.cc_shift = shift;
3689 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3691 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3692 ptp->rx_tstamp_tc.cc_shift = shift;
3693 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3695 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3696 ptp->tx_tstamp_tc.cc_shift = shift;
3697 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3699 if (!BNXT_CHIP_THOR(bp))
3700 bnxt_map_ptp_regs(bp);
3706 bnxt_timesync_disable(struct rte_eth_dev *dev)
3708 struct bnxt *bp = dev->data->dev_private;
3709 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3715 ptp->tx_tstamp_en = 0;
3718 bnxt_hwrm_ptp_cfg(bp);
3720 if (!BNXT_CHIP_THOR(bp))
3721 bnxt_unmap_ptp_regs(bp);
3727 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3728 struct timespec *timestamp,
3729 uint32_t flags __rte_unused)
3731 struct bnxt *bp = dev->data->dev_private;
3732 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3733 uint64_t rx_tstamp_cycles = 0;
3739 if (BNXT_CHIP_THOR(bp))
3740 rx_tstamp_cycles = ptp->rx_timestamp;
3742 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3744 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3745 *timestamp = rte_ns_to_timespec(ns);
3750 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3751 struct timespec *timestamp)
3753 struct bnxt *bp = dev->data->dev_private;
3754 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3755 uint64_t tx_tstamp_cycles = 0;
3762 if (BNXT_CHIP_THOR(bp))
3763 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3766 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3768 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3769 *timestamp = rte_ns_to_timespec(ns);
3775 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3777 struct bnxt *bp = dev->data->dev_private;
3778 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3783 ptp->tc.nsec += delta;
3789 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3791 struct bnxt *bp = dev->data->dev_private;
3793 uint32_t dir_entries;
3794 uint32_t entry_length;
3796 rc = is_bnxt_in_error(bp);
3800 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3801 bp->pdev->addr.domain, bp->pdev->addr.bus,
3802 bp->pdev->addr.devid, bp->pdev->addr.function);
3804 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3808 return dir_entries * entry_length;
3812 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3813 struct rte_dev_eeprom_info *in_eeprom)
3815 struct bnxt *bp = dev->data->dev_private;
3820 rc = is_bnxt_in_error(bp);
3824 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3825 bp->pdev->addr.domain, bp->pdev->addr.bus,
3826 bp->pdev->addr.devid, bp->pdev->addr.function,
3827 in_eeprom->offset, in_eeprom->length);
3829 if (in_eeprom->offset == 0) /* special offset value to get directory */
3830 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3833 index = in_eeprom->offset >> 24;
3834 offset = in_eeprom->offset & 0xffffff;
3837 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3838 in_eeprom->length, in_eeprom->data);
3843 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3846 case BNX_DIR_TYPE_CHIMP_PATCH:
3847 case BNX_DIR_TYPE_BOOTCODE:
3848 case BNX_DIR_TYPE_BOOTCODE_2:
3849 case BNX_DIR_TYPE_APE_FW:
3850 case BNX_DIR_TYPE_APE_PATCH:
3851 case BNX_DIR_TYPE_KONG_FW:
3852 case BNX_DIR_TYPE_KONG_PATCH:
3853 case BNX_DIR_TYPE_BONO_FW:
3854 case BNX_DIR_TYPE_BONO_PATCH:
3862 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3865 case BNX_DIR_TYPE_AVS:
3866 case BNX_DIR_TYPE_EXP_ROM_MBA:
3867 case BNX_DIR_TYPE_PCIE:
3868 case BNX_DIR_TYPE_TSCF_UCODE:
3869 case BNX_DIR_TYPE_EXT_PHY:
3870 case BNX_DIR_TYPE_CCM:
3871 case BNX_DIR_TYPE_ISCSI_BOOT:
3872 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3873 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3881 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3883 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3884 bnxt_dir_type_is_other_exec_format(dir_type);
3888 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3889 struct rte_dev_eeprom_info *in_eeprom)
3891 struct bnxt *bp = dev->data->dev_private;
3892 uint8_t index, dir_op;
3893 uint16_t type, ext, ordinal, attr;
3896 rc = is_bnxt_in_error(bp);
3900 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3901 bp->pdev->addr.domain, bp->pdev->addr.bus,
3902 bp->pdev->addr.devid, bp->pdev->addr.function,
3903 in_eeprom->offset, in_eeprom->length);
3906 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3910 type = in_eeprom->magic >> 16;
3912 if (type == 0xffff) { /* special value for directory operations */
3913 index = in_eeprom->magic & 0xff;
3914 dir_op = in_eeprom->magic >> 8;
3918 case 0x0e: /* erase */
3919 if (in_eeprom->offset != ~in_eeprom->magic)
3921 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3927 /* Create or re-write an NVM item: */
3928 if (bnxt_dir_type_is_executable(type) == true)
3930 ext = in_eeprom->magic & 0xffff;
3931 ordinal = in_eeprom->offset >> 16;
3932 attr = in_eeprom->offset & 0xffff;
3934 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3935 in_eeprom->data, in_eeprom->length);
3942 static const struct eth_dev_ops bnxt_dev_ops = {
3943 .dev_infos_get = bnxt_dev_info_get_op,
3944 .dev_close = bnxt_dev_close_op,
3945 .dev_configure = bnxt_dev_configure_op,
3946 .dev_start = bnxt_dev_start_op,
3947 .dev_stop = bnxt_dev_stop_op,
3948 .dev_set_link_up = bnxt_dev_set_link_up_op,
3949 .dev_set_link_down = bnxt_dev_set_link_down_op,
3950 .stats_get = bnxt_stats_get_op,
3951 .stats_reset = bnxt_stats_reset_op,
3952 .rx_queue_setup = bnxt_rx_queue_setup_op,
3953 .rx_queue_release = bnxt_rx_queue_release_op,
3954 .tx_queue_setup = bnxt_tx_queue_setup_op,
3955 .tx_queue_release = bnxt_tx_queue_release_op,
3956 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3957 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3958 .reta_update = bnxt_reta_update_op,
3959 .reta_query = bnxt_reta_query_op,
3960 .rss_hash_update = bnxt_rss_hash_update_op,
3961 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3962 .link_update = bnxt_link_update_op,
3963 .promiscuous_enable = bnxt_promiscuous_enable_op,
3964 .promiscuous_disable = bnxt_promiscuous_disable_op,
3965 .allmulticast_enable = bnxt_allmulticast_enable_op,
3966 .allmulticast_disable = bnxt_allmulticast_disable_op,
3967 .mac_addr_add = bnxt_mac_addr_add_op,
3968 .mac_addr_remove = bnxt_mac_addr_remove_op,
3969 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3970 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3971 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3972 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3973 .vlan_filter_set = bnxt_vlan_filter_set_op,
3974 .vlan_offload_set = bnxt_vlan_offload_set_op,
3975 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3976 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3977 .mtu_set = bnxt_mtu_set_op,
3978 .mac_addr_set = bnxt_set_default_mac_addr_op,
3979 .xstats_get = bnxt_dev_xstats_get_op,
3980 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3981 .xstats_reset = bnxt_dev_xstats_reset_op,
3982 .fw_version_get = bnxt_fw_version_get,
3983 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3984 .rxq_info_get = bnxt_rxq_info_get_op,
3985 .txq_info_get = bnxt_txq_info_get_op,
3986 .dev_led_on = bnxt_dev_led_on_op,
3987 .dev_led_off = bnxt_dev_led_off_op,
3988 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3989 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3990 .rx_queue_count = bnxt_rx_queue_count_op,
3991 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3992 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3993 .rx_queue_start = bnxt_rx_queue_start,
3994 .rx_queue_stop = bnxt_rx_queue_stop,
3995 .tx_queue_start = bnxt_tx_queue_start,
3996 .tx_queue_stop = bnxt_tx_queue_stop,
3997 .filter_ctrl = bnxt_filter_ctrl_op,
3998 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3999 .get_eeprom_length = bnxt_get_eeprom_length_op,
4000 .get_eeprom = bnxt_get_eeprom_op,
4001 .set_eeprom = bnxt_set_eeprom_op,
4002 .timesync_enable = bnxt_timesync_enable,
4003 .timesync_disable = bnxt_timesync_disable,
4004 .timesync_read_time = bnxt_timesync_read_time,
4005 .timesync_write_time = bnxt_timesync_write_time,
4006 .timesync_adjust_time = bnxt_timesync_adjust_time,
4007 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4008 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4011 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4015 /* Only pre-map the reset GRC registers using window 3 */
4016 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4017 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4019 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4024 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4026 struct bnxt_error_recovery_info *info = bp->recovery_info;
4027 uint32_t reg_base = 0xffffffff;
4030 /* Only pre-map the monitoring GRC registers using window 2 */
4031 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4032 uint32_t reg = info->status_regs[i];
4034 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4037 if (reg_base == 0xffffffff)
4038 reg_base = reg & 0xfffff000;
4039 if ((reg & 0xfffff000) != reg_base)
4042 /* Use mask 0xffc as the Lower 2 bits indicates
4043 * address space location
4045 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4049 if (reg_base == 0xffffffff)
4052 rte_write32(reg_base, (uint8_t *)bp->bar0 +
4053 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4058 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4060 struct bnxt_error_recovery_info *info = bp->recovery_info;
4061 uint32_t delay = info->delay_after_reset[index];
4062 uint32_t val = info->reset_reg_val[index];
4063 uint32_t reg = info->reset_reg[index];
4064 uint32_t type, offset;
4066 type = BNXT_FW_STATUS_REG_TYPE(reg);
4067 offset = BNXT_FW_STATUS_REG_OFF(reg);
4070 case BNXT_FW_STATUS_REG_TYPE_CFG:
4071 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4073 case BNXT_FW_STATUS_REG_TYPE_GRC:
4074 offset = bnxt_map_reset_regs(bp, offset);
4075 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4077 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4078 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4081 /* wait on a specific interval of time until core reset is complete */
4083 rte_delay_ms(delay);
4086 static void bnxt_dev_cleanup(struct bnxt *bp)
4088 bnxt_set_hwrm_link_config(bp, false);
4089 bp->link_info.link_up = 0;
4090 if (bp->eth_dev->data->dev_started)
4091 bnxt_dev_stop_op(bp->eth_dev);
4093 bnxt_uninit_resources(bp, true);
4096 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4098 struct rte_eth_dev *dev = bp->eth_dev;
4099 struct rte_vlan_filter_conf *vfc;
4103 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4104 vfc = &dev->data->vlan_filter_conf;
4105 vidx = vlan_id / 64;
4106 vbit = vlan_id % 64;
4108 /* Each bit corresponds to a VLAN id */
4109 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4110 rc = bnxt_add_vlan_filter(bp, vlan_id);
4119 static int bnxt_restore_mac_filters(struct bnxt *bp)
4121 struct rte_eth_dev *dev = bp->eth_dev;
4122 struct rte_eth_dev_info dev_info;
4123 struct rte_ether_addr *addr;
4129 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
4132 rc = bnxt_dev_info_get_op(dev, &dev_info);
4136 /* replay MAC address configuration */
4137 for (i = 1; i < dev_info.max_mac_addrs; i++) {
4138 addr = &dev->data->mac_addrs[i];
4140 /* skip zero address */
4141 if (rte_is_zero_ether_addr(addr))
4145 pool_mask = dev->data->mac_pool_sel[i];
4148 if (pool_mask & 1ULL) {
4149 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4155 } while (pool_mask);
4161 static int bnxt_restore_filters(struct bnxt *bp)
4163 struct rte_eth_dev *dev = bp->eth_dev;
4166 if (dev->data->all_multicast) {
4167 ret = bnxt_allmulticast_enable_op(dev);
4171 if (dev->data->promiscuous) {
4172 ret = bnxt_promiscuous_enable_op(dev);
4177 ret = bnxt_restore_mac_filters(bp);
4181 ret = bnxt_restore_vlan_filters(bp);
4182 /* TODO restore other filters as well */
4186 static void bnxt_dev_recover(void *arg)
4188 struct bnxt *bp = arg;
4189 int timeout = bp->fw_reset_max_msecs;
4192 /* Clear Error flag so that device re-init should happen */
4193 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4196 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4199 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4200 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4201 } while (rc && timeout);
4204 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4208 rc = bnxt_init_resources(bp, true);
4211 "Failed to initialize resources after reset\n");
4214 /* clear reset flag as the device is initialized now */
4215 bp->flags &= ~BNXT_FLAG_FW_RESET;
4217 rc = bnxt_dev_start_op(bp->eth_dev);
4219 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4223 rc = bnxt_restore_filters(bp);
4227 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4230 bnxt_dev_stop_op(bp->eth_dev);
4232 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4233 bnxt_uninit_resources(bp, false);
4234 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4237 void bnxt_dev_reset_and_resume(void *arg)
4239 struct bnxt *bp = arg;
4242 bnxt_dev_cleanup(bp);
4244 bnxt_wait_for_device_shutdown(bp);
4246 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4247 bnxt_dev_recover, (void *)bp);
4249 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4252 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4254 struct bnxt_error_recovery_info *info = bp->recovery_info;
4255 uint32_t reg = info->status_regs[index];
4256 uint32_t type, offset, val = 0;
4258 type = BNXT_FW_STATUS_REG_TYPE(reg);
4259 offset = BNXT_FW_STATUS_REG_OFF(reg);
4262 case BNXT_FW_STATUS_REG_TYPE_CFG:
4263 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4265 case BNXT_FW_STATUS_REG_TYPE_GRC:
4266 offset = info->mapped_status_regs[index];
4268 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4269 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4277 static int bnxt_fw_reset_all(struct bnxt *bp)
4279 struct bnxt_error_recovery_info *info = bp->recovery_info;
4283 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4284 /* Reset through master function driver */
4285 for (i = 0; i < info->reg_array_cnt; i++)
4286 bnxt_write_fw_reset_reg(bp, i);
4287 /* Wait for time specified by FW after triggering reset */
4288 rte_delay_ms(info->master_func_wait_period_after_reset);
4289 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4290 /* Reset with the help of Kong processor */
4291 rc = bnxt_hwrm_fw_reset(bp);
4293 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4299 static void bnxt_fw_reset_cb(void *arg)
4301 struct bnxt *bp = arg;
4302 struct bnxt_error_recovery_info *info = bp->recovery_info;
4305 /* Only Master function can do FW reset */
4306 if (bnxt_is_master_func(bp) &&
4307 bnxt_is_recovery_enabled(bp)) {
4308 rc = bnxt_fw_reset_all(bp);
4310 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4315 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4316 * EXCEPTION_FATAL_ASYNC event to all the functions
4317 * (including MASTER FUNC). After receiving this Async, all the active
4318 * drivers should treat this case as FW initiated recovery
4320 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4321 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4322 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4324 /* To recover from error */
4325 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4330 /* Driver should poll FW heartbeat, reset_counter with the frequency
4331 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4332 * When the driver detects heartbeat stop or change in reset_counter,
4333 * it has to trigger a reset to recover from the error condition.
4334 * A “master PF” is the function who will have the privilege to
4335 * initiate the chimp reset. The master PF will be elected by the
4336 * firmware and will be notified through async message.
4338 static void bnxt_check_fw_health(void *arg)
4340 struct bnxt *bp = arg;
4341 struct bnxt_error_recovery_info *info = bp->recovery_info;
4342 uint32_t val = 0, wait_msec;
4344 if (!info || !bnxt_is_recovery_enabled(bp) ||
4345 is_bnxt_in_error(bp))
4348 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4349 if (val == info->last_heart_beat)
4352 info->last_heart_beat = val;
4354 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4355 if (val != info->last_reset_counter)
4358 info->last_reset_counter = val;
4360 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4361 bnxt_check_fw_health, (void *)bp);
4365 /* Stop DMA to/from device */
4366 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4367 bp->flags |= BNXT_FLAG_FW_RESET;
4369 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4371 if (bnxt_is_master_func(bp))
4372 wait_msec = info->master_func_wait_period;
4374 wait_msec = info->normal_func_wait_period;
4376 rte_eal_alarm_set(US_PER_MS * wait_msec,
4377 bnxt_fw_reset_cb, (void *)bp);
4380 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4382 uint32_t polling_freq;
4384 if (!bnxt_is_recovery_enabled(bp))
4387 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4390 polling_freq = bp->recovery_info->driver_polling_freq;
4392 rte_eal_alarm_set(US_PER_MS * polling_freq,
4393 bnxt_check_fw_health, (void *)bp);
4394 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4397 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4399 if (!bnxt_is_recovery_enabled(bp))
4402 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4403 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4406 static bool bnxt_vf_pciid(uint16_t device_id)
4408 switch (device_id) {
4409 case BROADCOM_DEV_ID_57304_VF:
4410 case BROADCOM_DEV_ID_57406_VF:
4411 case BROADCOM_DEV_ID_5731X_VF:
4412 case BROADCOM_DEV_ID_5741X_VF:
4413 case BROADCOM_DEV_ID_57414_VF:
4414 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4415 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4416 case BROADCOM_DEV_ID_58802_VF:
4417 case BROADCOM_DEV_ID_57500_VF1:
4418 case BROADCOM_DEV_ID_57500_VF2:
4426 static bool bnxt_thor_device(uint16_t device_id)
4428 switch (device_id) {
4429 case BROADCOM_DEV_ID_57508:
4430 case BROADCOM_DEV_ID_57504:
4431 case BROADCOM_DEV_ID_57502:
4432 case BROADCOM_DEV_ID_57508_MF1:
4433 case BROADCOM_DEV_ID_57504_MF1:
4434 case BROADCOM_DEV_ID_57502_MF1:
4435 case BROADCOM_DEV_ID_57508_MF2:
4436 case BROADCOM_DEV_ID_57504_MF2:
4437 case BROADCOM_DEV_ID_57502_MF2:
4438 case BROADCOM_DEV_ID_57500_VF1:
4439 case BROADCOM_DEV_ID_57500_VF2:
4447 bool bnxt_stratus_device(struct bnxt *bp)
4449 uint16_t device_id = bp->pdev->id.device_id;
4451 switch (device_id) {
4452 case BROADCOM_DEV_ID_STRATUS_NIC:
4453 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4454 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4462 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4464 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4465 struct bnxt *bp = eth_dev->data->dev_private;
4467 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4468 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4469 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4470 if (!bp->bar0 || !bp->doorbell_base) {
4471 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4475 bp->eth_dev = eth_dev;
4481 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4482 struct bnxt_ctx_pg_info *ctx_pg,
4487 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4488 const struct rte_memzone *mz = NULL;
4489 char mz_name[RTE_MEMZONE_NAMESIZE];
4490 rte_iova_t mz_phys_addr;
4491 uint64_t valid_bits = 0;
4498 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4500 rmem->page_size = BNXT_PAGE_SIZE;
4501 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4502 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4503 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4505 valid_bits = PTU_PTE_VALID;
4507 if (rmem->nr_pages > 1) {
4508 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4509 "bnxt_ctx_pg_tbl%s_%x_%d",
4510 suffix, idx, bp->eth_dev->data->port_id);
4511 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4512 mz = rte_memzone_lookup(mz_name);
4514 mz = rte_memzone_reserve_aligned(mz_name,
4518 RTE_MEMZONE_SIZE_HINT_ONLY |
4519 RTE_MEMZONE_IOVA_CONTIG,
4525 memset(mz->addr, 0, mz->len);
4526 mz_phys_addr = mz->iova;
4528 rmem->pg_tbl = mz->addr;
4529 rmem->pg_tbl_map = mz_phys_addr;
4530 rmem->pg_tbl_mz = mz;
4533 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4534 suffix, idx, bp->eth_dev->data->port_id);
4535 mz = rte_memzone_lookup(mz_name);
4537 mz = rte_memzone_reserve_aligned(mz_name,
4541 RTE_MEMZONE_SIZE_HINT_ONLY |
4542 RTE_MEMZONE_IOVA_CONTIG,
4548 memset(mz->addr, 0, mz->len);
4549 mz_phys_addr = mz->iova;
4551 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4552 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4553 rmem->dma_arr[i] = mz_phys_addr + sz;
4555 if (rmem->nr_pages > 1) {
4556 if (i == rmem->nr_pages - 2 &&
4557 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4558 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4559 else if (i == rmem->nr_pages - 1 &&
4560 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4561 valid_bits |= PTU_PTE_LAST;
4563 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4569 if (rmem->vmem_size)
4570 rmem->vmem = (void **)mz->addr;
4571 rmem->dma_arr[0] = mz_phys_addr;
4575 static void bnxt_free_ctx_mem(struct bnxt *bp)
4579 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4582 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4583 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4584 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4585 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4586 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4587 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4588 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4589 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4590 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4591 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4592 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4594 for (i = 0; i < BNXT_MAX_Q; i++) {
4595 if (bp->ctx->tqm_mem[i])
4596 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4603 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4605 #define min_t(type, x, y) ({ \
4606 type __min1 = (x); \
4607 type __min2 = (y); \
4608 __min1 < __min2 ? __min1 : __min2; })
4610 #define max_t(type, x, y) ({ \
4611 type __max1 = (x); \
4612 type __max2 = (y); \
4613 __max1 > __max2 ? __max1 : __max2; })
4615 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4617 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4619 struct bnxt_ctx_pg_info *ctx_pg;
4620 struct bnxt_ctx_mem_info *ctx;
4621 uint32_t mem_size, ena, entries;
4624 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4626 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4630 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4633 ctx_pg = &ctx->qp_mem;
4634 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4635 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4636 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4640 ctx_pg = &ctx->srq_mem;
4641 ctx_pg->entries = ctx->srq_max_l2_entries;
4642 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4643 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4647 ctx_pg = &ctx->cq_mem;
4648 ctx_pg->entries = ctx->cq_max_l2_entries;
4649 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4650 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4654 ctx_pg = &ctx->vnic_mem;
4655 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4656 ctx->vnic_max_ring_table_entries;
4657 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4658 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4662 ctx_pg = &ctx->stat_mem;
4663 ctx_pg->entries = ctx->stat_max_entries;
4664 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4665 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4669 entries = ctx->qp_max_l2_entries +
4670 ctx->vnic_max_vnic_entries +
4671 ctx->tqm_min_entries_per_ring;
4672 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4673 entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4674 ctx->tqm_max_entries_per_ring);
4675 for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4676 ctx_pg = ctx->tqm_mem[i];
4677 /* use min tqm entries for now. */
4678 ctx_pg->entries = entries;
4679 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4680 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4683 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4686 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4687 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4690 "Failed to configure context mem: rc = %d\n", rc);
4692 ctx->flags |= BNXT_CTX_FLAG_INITED;
4697 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4699 struct rte_pci_device *pci_dev = bp->pdev;
4700 char mz_name[RTE_MEMZONE_NAMESIZE];
4701 const struct rte_memzone *mz = NULL;
4702 uint32_t total_alloc_len;
4703 rte_iova_t mz_phys_addr;
4705 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4708 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4709 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4710 pci_dev->addr.bus, pci_dev->addr.devid,
4711 pci_dev->addr.function, "rx_port_stats");
4712 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4713 mz = rte_memzone_lookup(mz_name);
4715 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4716 sizeof(struct rx_port_stats_ext) + 512);
4718 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4721 RTE_MEMZONE_SIZE_HINT_ONLY |
4722 RTE_MEMZONE_IOVA_CONTIG);
4726 memset(mz->addr, 0, mz->len);
4727 mz_phys_addr = mz->iova;
4729 bp->rx_mem_zone = (const void *)mz;
4730 bp->hw_rx_port_stats = mz->addr;
4731 bp->hw_rx_port_stats_map = mz_phys_addr;
4733 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4734 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4735 pci_dev->addr.bus, pci_dev->addr.devid,
4736 pci_dev->addr.function, "tx_port_stats");
4737 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4738 mz = rte_memzone_lookup(mz_name);
4740 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4741 sizeof(struct tx_port_stats_ext) + 512);
4743 mz = rte_memzone_reserve(mz_name,
4747 RTE_MEMZONE_SIZE_HINT_ONLY |
4748 RTE_MEMZONE_IOVA_CONTIG);
4752 memset(mz->addr, 0, mz->len);
4753 mz_phys_addr = mz->iova;
4755 bp->tx_mem_zone = (const void *)mz;
4756 bp->hw_tx_port_stats = mz->addr;
4757 bp->hw_tx_port_stats_map = mz_phys_addr;
4758 bp->flags |= BNXT_FLAG_PORT_STATS;
4760 /* Display extended statistics if FW supports it */
4761 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4762 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4763 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4766 bp->hw_rx_port_stats_ext = (void *)
4767 ((uint8_t *)bp->hw_rx_port_stats +
4768 sizeof(struct rx_port_stats));
4769 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4770 sizeof(struct rx_port_stats);
4771 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4773 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4774 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4775 bp->hw_tx_port_stats_ext = (void *)
4776 ((uint8_t *)bp->hw_tx_port_stats +
4777 sizeof(struct tx_port_stats));
4778 bp->hw_tx_port_stats_ext_map =
4779 bp->hw_tx_port_stats_map +
4780 sizeof(struct tx_port_stats);
4781 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4787 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4789 struct bnxt *bp = eth_dev->data->dev_private;
4792 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4793 RTE_ETHER_ADDR_LEN *
4796 if (eth_dev->data->mac_addrs == NULL) {
4797 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4801 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4805 /* Generate a random MAC address, if none was assigned by PF */
4806 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4807 bnxt_eth_hw_addr_random(bp->mac_addr);
4809 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4810 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4811 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4813 rc = bnxt_hwrm_set_mac(bp);
4815 memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4816 RTE_ETHER_ADDR_LEN);
4820 /* Copy the permanent MAC from the FUNC_QCAPS response */
4821 memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4822 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4827 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4831 /* MAC is already configured in FW */
4832 if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4835 /* Restore the old MAC configured */
4836 rc = bnxt_hwrm_set_mac(bp);
4838 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4843 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4848 #define ALLOW_FUNC(x) \
4850 uint32_t arg = (x); \
4851 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4852 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4855 /* Forward all requests if firmware is new enough */
4856 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4857 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4858 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4859 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4861 PMD_DRV_LOG(WARNING,
4862 "Firmware too old for VF mailbox functionality\n");
4863 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4867 * The following are used for driver cleanup. If we disallow these,
4868 * VF drivers can't clean up cleanly.
4870 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4871 ALLOW_FUNC(HWRM_VNIC_FREE);
4872 ALLOW_FUNC(HWRM_RING_FREE);
4873 ALLOW_FUNC(HWRM_RING_GRP_FREE);
4874 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4875 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4876 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4877 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4878 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4882 bnxt_get_svif(uint16_t port_id, bool func_svif)
4884 struct rte_eth_dev *eth_dev;
4887 eth_dev = &rte_eth_devices[port_id];
4888 bp = eth_dev->data->dev_private;
4890 return func_svif ? bp->func_svif : bp->port_svif;
4894 bnxt_get_vnic_id(uint16_t port)
4896 struct rte_eth_dev *eth_dev;
4897 struct bnxt_vnic_info *vnic;
4900 eth_dev = &rte_eth_devices[port];
4901 bp = eth_dev->data->dev_private;
4903 vnic = BNXT_GET_DEFAULT_VNIC(bp);
4905 return vnic->fw_vnic_id;
4909 bnxt_get_fw_func_id(uint16_t port)
4911 struct rte_eth_dev *eth_dev;
4914 eth_dev = &rte_eth_devices[port];
4915 bp = eth_dev->data->dev_private;
4920 static int bnxt_init_fw(struct bnxt *bp)
4927 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
4931 rc = bnxt_hwrm_func_reset(bp);
4935 rc = bnxt_hwrm_vnic_qcaps(bp);
4939 rc = bnxt_hwrm_queue_qportcfg(bp);
4943 /* Get the MAX capabilities for this function.
4944 * This function also allocates context memory for TQM rings and
4945 * informs the firmware about this allocated backing store memory.
4947 rc = bnxt_hwrm_func_qcaps(bp);
4951 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4955 bnxt_hwrm_port_mac_qcfg(bp);
4957 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4961 /* Get the adapter error recovery support info */
4962 rc = bnxt_hwrm_error_recovery_qcfg(bp);
4964 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4966 bnxt_hwrm_port_led_qcaps(bp);
4972 bnxt_init_locks(struct bnxt *bp)
4976 err = pthread_mutex_init(&bp->flow_lock, NULL);
4978 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4982 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4984 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4988 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4992 rc = bnxt_init_fw(bp);
4996 if (!reconfig_dev) {
4997 rc = bnxt_setup_mac_addr(bp->eth_dev);
5001 rc = bnxt_restore_dflt_mac(bp);
5006 bnxt_config_vf_req_fwd(bp);
5008 rc = bnxt_hwrm_func_driver_register(bp);
5010 PMD_DRV_LOG(ERR, "Failed to register driver");
5015 if (bp->pdev->max_vfs) {
5016 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5018 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5022 rc = bnxt_hwrm_allocate_pf_only(bp);
5025 "Failed to allocate PF resources");
5031 rc = bnxt_alloc_mem(bp, reconfig_dev);
5035 rc = bnxt_setup_int(bp);
5039 rc = bnxt_request_int(bp);
5043 rc = bnxt_init_ctx_mem(bp);
5045 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5049 rc = bnxt_init_locks(bp);
5057 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5058 const char *value, void *opaque_arg)
5060 struct bnxt *bp = opaque_arg;
5061 unsigned long truflow;
5064 if (!value || !opaque_arg) {
5066 "Invalid parameter passed to truflow devargs.\n");
5070 truflow = strtoul(value, &end, 10);
5071 if (end == NULL || *end != '\0' ||
5072 (truflow == ULONG_MAX && errno == ERANGE)) {
5074 "Invalid parameter passed to truflow devargs.\n");
5078 if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5080 "Invalid value passed to truflow devargs.\n");
5084 bp->truflow = truflow;
5086 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5092 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5093 const char *value, void *opaque_arg)
5095 struct bnxt *bp = opaque_arg;
5096 unsigned long flow_xstat;
5099 if (!value || !opaque_arg) {
5101 "Invalid parameter passed to flow_xstat devarg.\n");
5105 flow_xstat = strtoul(value, &end, 10);
5106 if (end == NULL || *end != '\0' ||
5107 (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5109 "Invalid parameter passed to flow_xstat devarg.\n");
5113 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5115 "Invalid value passed to flow_xstat devarg.\n");
5119 bp->flow_xstat = flow_xstat;
5121 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5127 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5129 struct rte_kvargs *kvlist;
5131 if (devargs == NULL)
5134 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5139 * Handler for "truflow" devarg.
5140 * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1”
5142 rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5143 bnxt_parse_devarg_truflow, bp);
5146 * Handler for "flow_xstat" devarg.
5147 * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1”
5149 rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5150 bnxt_parse_devarg_flow_xstat, bp);
5152 rte_kvargs_free(kvlist);
5156 bnxt_dev_init(struct rte_eth_dev *eth_dev)
5158 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5159 static int version_printed;
5163 if (version_printed++ == 0)
5164 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5166 eth_dev->dev_ops = &bnxt_dev_ops;
5167 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5168 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5171 * For secondary processes, we don't initialise any further
5172 * as primary has already done this work.
5174 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5177 rte_eth_copy_pci_info(eth_dev, pci_dev);
5179 bp = eth_dev->data->dev_private;
5181 /* Parse dev arguments passed on when starting the DPDK application. */
5182 bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5184 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5186 if (bnxt_vf_pciid(pci_dev->id.device_id))
5187 bp->flags |= BNXT_FLAG_VF;
5189 if (bnxt_thor_device(pci_dev->id.device_id))
5190 bp->flags |= BNXT_FLAG_THOR_CHIP;
5192 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5193 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5194 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5195 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5196 bp->flags |= BNXT_FLAG_STINGRAY;
5198 rc = bnxt_init_board(eth_dev);
5201 "Failed to initialize board rc: %x\n", rc);
5205 rc = bnxt_alloc_hwrm_resources(bp);
5208 "Failed to allocate hwrm resource rc: %x\n", rc);
5211 rc = bnxt_init_resources(bp, false);
5215 rc = bnxt_alloc_stats_mem(bp);
5219 /* Pass the information to the rte_eth_dev_close() that it should also
5220 * release the private port resources.
5222 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5225 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5226 pci_dev->mem_resource[0].phys_addr,
5227 pci_dev->mem_resource[0].addr);
5232 bnxt_dev_uninit(eth_dev);
5237 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5246 ctx->dma = RTE_BAD_IOVA;
5247 ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5250 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5252 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5253 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5254 bp->rx_fc_out_tbl.ctx_id,
5258 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5259 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5260 bp->tx_fc_out_tbl.ctx_id,
5264 if (bp->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5265 bnxt_hwrm_ctx_unrgtr(bp, bp->rx_fc_in_tbl.ctx_id);
5266 bp->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5268 if (bp->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5269 bnxt_hwrm_ctx_unrgtr(bp, bp->rx_fc_out_tbl.ctx_id);
5270 bp->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5272 if (bp->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5273 bnxt_hwrm_ctx_unrgtr(bp, bp->tx_fc_in_tbl.ctx_id);
5274 bp->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5276 if (bp->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5277 bnxt_hwrm_ctx_unrgtr(bp, bp->tx_fc_out_tbl.ctx_id);
5278 bp->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5281 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5283 bnxt_unregister_fc_ctx_mem(bp);
5285 bnxt_free_ctx_mem_buf(&bp->rx_fc_in_tbl);
5286 bnxt_free_ctx_mem_buf(&bp->rx_fc_out_tbl);
5287 bnxt_free_ctx_mem_buf(&bp->tx_fc_in_tbl);
5288 bnxt_free_ctx_mem_buf(&bp->tx_fc_out_tbl);
5291 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5293 bnxt_uninit_fc_ctx_mem(bp);
5297 bnxt_uninit_locks(struct bnxt *bp)
5299 pthread_mutex_destroy(&bp->flow_lock);
5300 pthread_mutex_destroy(&bp->def_cp_lock);
5304 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5309 bnxt_free_mem(bp, reconfig_dev);
5310 bnxt_hwrm_func_buf_unrgtr(bp);
5311 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5312 bp->flags &= ~BNXT_FLAG_REGISTERED;
5313 bnxt_free_ctx_mem(bp);
5314 if (!reconfig_dev) {
5315 bnxt_free_hwrm_resources(bp);
5317 if (bp->recovery_info != NULL) {
5318 rte_free(bp->recovery_info);
5319 bp->recovery_info = NULL;
5323 bnxt_uninit_ctx_mem(bp);
5325 bnxt_uninit_locks(bp);
5326 rte_free(bp->ptp_cfg);
5332 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5334 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5337 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5339 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5340 bnxt_dev_close_op(eth_dev);
5345 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5346 struct rte_pci_device *pci_dev)
5348 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
5352 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5354 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
5355 return rte_eth_dev_pci_generic_remove(pci_dev,
5358 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5361 static struct rte_pci_driver bnxt_rte_pmd = {
5362 .id_table = bnxt_pci_id_map,
5363 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5364 .probe = bnxt_pci_probe,
5365 .remove = bnxt_pci_remove,
5369 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5371 if (strcmp(dev->device->driver->name, drv->driver.name))
5377 bool is_bnxt_supported(struct rte_eth_dev *dev)
5379 return is_device_supported(dev, &bnxt_rte_pmd);
5382 RTE_INIT(bnxt_init_log)
5384 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
5385 if (bnxt_logtype_driver >= 0)
5386 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
5389 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5390 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5391 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");