drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16
  17 #include "bnxt.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_reps.h"
  22 #include "bnxt_ring.h"
  23 #include "bnxt_rxq.h"
  24 #include "bnxt_rxr.h"
  25 #include "bnxt_stats.h"
  26 #include "bnxt_txq.h"
  27 #include "bnxt_txr.h"
  28 #include "bnxt_vnic.h"
  29 #include "hsi_struct_def_dpdk.h"
  30 #include "bnxt_nvm_defs.h"
  31 #include "bnxt_tf_common.h"
  32 #include "ulp_flow_db.h"
  33
  34 #define DRV_MODULE_NAME         "bnxt"
  35 static const char bnxt_version[] =
  36         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  37
  38 /*
  39  * The set of PCI devices this driver supports
  40  */
  41 static const struct rte_pci_id bnxt_pci_id_map[] = {
  42         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  43                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  95         { .vendor_id = 0, /* sentinel */ },
  96 };
  97
  98 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
  99 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
 100 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
 101 #define BNXT_DEVARG_REPRESENTOR "representor"
 102 #define BNXT_DEVARG_REP_BASED_PF  "rep-based-pf"
 103 #define BNXT_DEVARG_REP_IS_PF  "rep-is-pf"
 104 #define BNXT_DEVARG_REP_Q_R2F  "rep-q-r2f"
 105 #define BNXT_DEVARG_REP_Q_F2R  "rep-q-f2r"
 106 #define BNXT_DEVARG_REP_FC_R2F  "rep-fc-r2f"
 107 #define BNXT_DEVARG_REP_FC_F2R  "rep-fc-f2r"
 108
 109 static const char *const bnxt_dev_args[] = {
 110         BNXT_DEVARG_REPRESENTOR,
 111         BNXT_DEVARG_TRUFLOW,
 112         BNXT_DEVARG_FLOW_XSTAT,
 113         BNXT_DEVARG_MAX_NUM_KFLOWS,
 114         BNXT_DEVARG_REP_BASED_PF,
 115         BNXT_DEVARG_REP_IS_PF,
 116         BNXT_DEVARG_REP_Q_R2F,
 117         BNXT_DEVARG_REP_Q_F2R,
 118         BNXT_DEVARG_REP_FC_R2F,
 119         BNXT_DEVARG_REP_FC_F2R,
 120         NULL
 121 };
 122
 123 /*
 124  * truflow == false to disable the feature
 125  * truflow == true to enable the feature
 126  */
 127 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 128
 129 /*
 130  * flow_xstat == false to disable the feature
 131  * flow_xstat == true to enable the feature
 132  */
 133 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 134
 135 /*
 136  * rep_is_pf == false to indicate VF representor
 137  * rep_is_pf == true to indicate PF representor
 138  */
 139 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)        ((rep_is_pf) > 1)
 140
 141 /*
 142  * rep_based_pf == Physical index of the PF
 143  */
 144 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)  ((rep_based_pf) > 15)
 145 /*
 146  * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
 147  */
 148 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)        ((rep_q_r2f) > 3)
 149
 150 /*
 151  * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
 152  */
 153 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)        ((rep_q_f2r) > 3)
 154
 155 /*
 156  * rep_fc_r2f == Flow control for the representor to endpoint direction
 157  */
 158 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)      ((rep_fc_r2f) > 1)
 159
 160 /*
 161  * rep_fc_f2r == Flow control for the endpoint to representor direction
 162  */
 163 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)      ((rep_fc_f2r) > 1)
 164
 165 /*
 166  * max_num_kflows must be >= 32
 167  * and must be a power-of-2 supported value
 168  * return: 1 -> invalid
 169  *         0 -> valid
 170  */
 171 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 172 {
 173         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 174                 return 1;
 175         return 0;
 176 }
 177
 178 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 179 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 180 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 181 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 182 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 183 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 184 static void bnxt_dev_recover(void *arg);
 185 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 186 static void bnxt_free_rep_info(struct bnxt *bp);
 187
 188 int is_bnxt_in_error(struct bnxt *bp)
 189 {
 190         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 191                 return -EIO;
 192         if (bp->flags & BNXT_FLAG_FW_RESET)
 193                 return -EBUSY;
 194
 195         return 0;
 196 }
 197
 198 /***********************/
 199
 200 /*
 201  * High level utility functions
 202  */
 203
 204 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 205 {
 206         if (!BNXT_CHIP_THOR(bp))
 207                 return 1;
 208
 209         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 210                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 211                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 212 }
 213
 214 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 215 {
 216         if (!BNXT_CHIP_THOR(bp))
 217                 return HW_HASH_INDEX_SIZE;
 218
 219         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 220 }
 221
 222 static void bnxt_free_parent_info(struct bnxt *bp)
 223 {
 224         rte_free(bp->parent);
 225 }
 226
 227 static void bnxt_free_pf_info(struct bnxt *bp)
 228 {
 229         rte_free(bp->pf);
 230 }
 231
 232 static void bnxt_free_link_info(struct bnxt *bp)
 233 {
 234         rte_free(bp->link_info);
 235 }
 236
 237 static void bnxt_free_leds_info(struct bnxt *bp)
 238 {
 239         if (BNXT_VF(bp))
 240                 return;
 241
 242         rte_free(bp->leds);
 243         bp->leds = NULL;
 244 }
 245
 246 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 247 {
 248         rte_free(bp->flow_stat);
 249         bp->flow_stat = NULL;
 250 }
 251
 252 static void bnxt_free_cos_queues(struct bnxt *bp)
 253 {
 254         rte_free(bp->rx_cos_queue);
 255         rte_free(bp->tx_cos_queue);
 256 }
 257
 258 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 259 {
 260         bnxt_free_filter_mem(bp);
 261         bnxt_free_vnic_attributes(bp);
 262         bnxt_free_vnic_mem(bp);
 263
 264         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 265          * If the number of rings change across fw update,
 266          * we don't have much choice except to warn the user.
 267          */
 268         if (!reconfig) {
 269                 bnxt_free_stats(bp);
 270                 bnxt_free_tx_rings(bp);
 271                 bnxt_free_rx_rings(bp);
 272         }
 273         bnxt_free_async_cp_ring(bp);
 274         bnxt_free_rxtx_nq_ring(bp);
 275
 276         rte_free(bp->grp_info);
 277         bp->grp_info = NULL;
 278 }
 279
 280 static int bnxt_alloc_parent_info(struct bnxt *bp)
 281 {
 282         bp->parent = rte_zmalloc("bnxt_parent_info",
 283                                  sizeof(struct bnxt_parent_info), 0);
 284         if (bp->parent == NULL)
 285                 return -ENOMEM;
 286
 287         return 0;
 288 }
 289
 290 static int bnxt_alloc_pf_info(struct bnxt *bp)
 291 {
 292         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 293         if (bp->pf == NULL)
 294                 return -ENOMEM;
 295
 296         return 0;
 297 }
 298
 299 static int bnxt_alloc_link_info(struct bnxt *bp)
 300 {
 301         bp->link_info =
 302                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 303         if (bp->link_info == NULL)
 304                 return -ENOMEM;
 305
 306         return 0;
 307 }
 308
 309 static int bnxt_alloc_leds_info(struct bnxt *bp)
 310 {
 311         if (BNXT_VF(bp))
 312                 return 0;
 313
 314         bp->leds = rte_zmalloc("bnxt_leds",
 315                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 316                                0);
 317         if (bp->leds == NULL)
 318                 return -ENOMEM;
 319
 320         return 0;
 321 }
 322
 323 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 324 {
 325         bp->rx_cos_queue =
 326                 rte_zmalloc("bnxt_rx_cosq",
 327                             BNXT_COS_QUEUE_COUNT *
 328                             sizeof(struct bnxt_cos_queue_info),
 329                             0);
 330         if (bp->rx_cos_queue == NULL)
 331                 return -ENOMEM;
 332
 333         bp->tx_cos_queue =
 334                 rte_zmalloc("bnxt_tx_cosq",
 335                             BNXT_COS_QUEUE_COUNT *
 336                             sizeof(struct bnxt_cos_queue_info),
 337                             0);
 338         if (bp->tx_cos_queue == NULL)
 339                 return -ENOMEM;
 340
 341         return 0;
 342 }
 343
 344 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 345 {
 346         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 347                                     sizeof(struct bnxt_flow_stat_info), 0);
 348         if (bp->flow_stat == NULL)
 349                 return -ENOMEM;
 350
 351         return 0;
 352 }
 353
 354 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 355 {
 356         int rc;
 357
 358         rc = bnxt_alloc_ring_grps(bp);
 359         if (rc)
 360                 goto alloc_mem_err;
 361
 362         rc = bnxt_alloc_async_ring_struct(bp);
 363         if (rc)
 364                 goto alloc_mem_err;
 365
 366         rc = bnxt_alloc_vnic_mem(bp);
 367         if (rc)
 368                 goto alloc_mem_err;
 369
 370         rc = bnxt_alloc_vnic_attributes(bp);
 371         if (rc)
 372                 goto alloc_mem_err;
 373
 374         rc = bnxt_alloc_filter_mem(bp);
 375         if (rc)
 376                 goto alloc_mem_err;
 377
 378         rc = bnxt_alloc_async_cp_ring(bp);
 379         if (rc)
 380                 goto alloc_mem_err;
 381
 382         rc = bnxt_alloc_rxtx_nq_ring(bp);
 383         if (rc)
 384                 goto alloc_mem_err;
 385
 386         if (BNXT_FLOW_XSTATS_EN(bp)) {
 387                 rc = bnxt_alloc_flow_stats_info(bp);
 388                 if (rc)
 389                         goto alloc_mem_err;
 390         }
 391
 392         return 0;
 393
 394 alloc_mem_err:
 395         bnxt_free_mem(bp, reconfig);
 396         return rc;
 397 }
 398
 399 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 400 {
 401         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 402         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 403         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 404         struct bnxt_rx_queue *rxq;
 405         unsigned int j;
 406         int rc;
 407
 408         rc = bnxt_vnic_grp_alloc(bp, vnic);
 409         if (rc)
 410                 goto err_out;
 411
 412         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 413                     vnic_id, vnic, vnic->fw_grp_ids);
 414
 415         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 416         if (rc)
 417                 goto err_out;
 418
 419         /* Alloc RSS context only if RSS mode is enabled */
 420         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 421                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 422
 423                 rc = 0;
 424                 for (j = 0; j < nr_ctxs; j++) {
 425                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 426                         if (rc)
 427                                 break;
 428                 }
 429                 if (rc) {
 430                         PMD_DRV_LOG(ERR,
 431                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 432                                     vnic_id, j, rc);
 433                         goto err_out;
 434                 }
 435                 vnic->num_lb_ctxts = nr_ctxs;
 436         }
 437
 438         /*
 439          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 440          * setting is not available at this time, it will not be
 441          * configured correctly in the CFA.
 442          */
 443         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 444                 vnic->vlan_strip = true;
 445         else
 446                 vnic->vlan_strip = false;
 447
 448         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 449         if (rc)
 450                 goto err_out;
 451
 452         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 453         if (rc)
 454                 goto err_out;
 455
 456         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 457                 rxq = bp->eth_dev->data->rx_queues[j];
 458
 459                 PMD_DRV_LOG(DEBUG,
 460                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 461                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 462
 463                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 464                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 465                 else
 466                         vnic->rx_queue_cnt++;
 467         }
 468
 469         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 470
 471         rc = bnxt_vnic_rss_configure(bp, vnic);
 472         if (rc)
 473                 goto err_out;
 474
 475         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 476
 477         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 478                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 479         else
 480                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 481
 482         return 0;
 483 err_out:
 484         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 485                     vnic_id, rc);
 486         return rc;
 487 }
 488
 489 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 490 {
 491         int rc = 0;
 492
 493         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 494                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 495         if (rc)
 496                 return rc;
 497
 498         PMD_DRV_LOG(DEBUG,
 499                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 500                     " rx_fc_in_tbl.ctx_id = %d\n",
 501                     bp->flow_stat->rx_fc_in_tbl.va,
 502                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 503                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 504
 505         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 506                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 507         if (rc)
 508                 return rc;
 509
 510         PMD_DRV_LOG(DEBUG,
 511                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 512                     " rx_fc_out_tbl.ctx_id = %d\n",
 513                     bp->flow_stat->rx_fc_out_tbl.va,
 514                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 515                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 516
 517         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 518                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 519         if (rc)
 520                 return rc;
 521
 522         PMD_DRV_LOG(DEBUG,
 523                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 524                     " tx_fc_in_tbl.ctx_id = %d\n",
 525                     bp->flow_stat->tx_fc_in_tbl.va,
 526                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 527                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 528
 529         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 530                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 531         if (rc)
 532                 return rc;
 533
 534         PMD_DRV_LOG(DEBUG,
 535                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 536                     " tx_fc_out_tbl.ctx_id = %d\n",
 537                     bp->flow_stat->tx_fc_out_tbl.va,
 538                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 539                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 540
 541         memset(bp->flow_stat->rx_fc_out_tbl.va,
 542                0,
 543                bp->flow_stat->rx_fc_out_tbl.size);
 544         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 545                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 546                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 547                                        bp->flow_stat->max_fc,
 548                                        true);
 549         if (rc)
 550                 return rc;
 551
 552         memset(bp->flow_stat->tx_fc_out_tbl.va,
 553                0,
 554                bp->flow_stat->tx_fc_out_tbl.size);
 555         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 556                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 557                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 558                                        bp->flow_stat->max_fc,
 559                                        true);
 560
 561         return rc;
 562 }
 563
 564 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 565                                   struct bnxt_ctx_mem_buf_info *ctx)
 566 {
 567         if (!ctx)
 568                 return -EINVAL;
 569
 570         ctx->va = rte_zmalloc(type, size, 0);
 571         if (ctx->va == NULL)
 572                 return -ENOMEM;
 573         rte_mem_lock_page(ctx->va);
 574         ctx->size = size;
 575         ctx->dma = rte_mem_virt2iova(ctx->va);
 576         if (ctx->dma == RTE_BAD_IOVA)
 577                 return -ENOMEM;
 578
 579         return 0;
 580 }
 581
 582 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 583 {
 584         struct rte_pci_device *pdev = bp->pdev;
 585         char type[RTE_MEMZONE_NAMESIZE];
 586         uint16_t max_fc;
 587         int rc = 0;
 588
 589         max_fc = bp->flow_stat->max_fc;
 590
 591         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 592                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 593         /* 4 bytes for each counter-id */
 594         rc = bnxt_alloc_ctx_mem_buf(type,
 595                                     max_fc * 4,
 596                                     &bp->flow_stat->rx_fc_in_tbl);
 597         if (rc)
 598                 return rc;
 599
 600         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 601                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 602         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 603         rc = bnxt_alloc_ctx_mem_buf(type,
 604                                     max_fc * 16,
 605                                     &bp->flow_stat->rx_fc_out_tbl);
 606         if (rc)
 607                 return rc;
 608
 609         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 610                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 611         /* 4 bytes for each counter-id */
 612         rc = bnxt_alloc_ctx_mem_buf(type,
 613                                     max_fc * 4,
 614                                     &bp->flow_stat->tx_fc_in_tbl);
 615         if (rc)
 616                 return rc;
 617
 618         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 619                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 620         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 621         rc = bnxt_alloc_ctx_mem_buf(type,
 622                                     max_fc * 16,
 623                                     &bp->flow_stat->tx_fc_out_tbl);
 624         if (rc)
 625                 return rc;
 626
 627         rc = bnxt_register_fc_ctx_mem(bp);
 628
 629         return rc;
 630 }
 631
 632 static int bnxt_init_ctx_mem(struct bnxt *bp)
 633 {
 634         int rc = 0;
 635
 636         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 637             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 638             !BNXT_FLOW_XSTATS_EN(bp))
 639                 return 0;
 640
 641         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 642         if (rc)
 643                 return rc;
 644
 645         rc = bnxt_init_fc_ctx_mem(bp);
 646
 647         return rc;
 648 }
 649
 650 static int bnxt_update_phy_setting(struct bnxt *bp)
 651 {
 652         struct rte_eth_link new;
 653         int rc;
 654
 655         rc = bnxt_get_hwrm_link_config(bp, &new);
 656         if (rc) {
 657                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 658                 return rc;
 659         }
 660
 661         /*
 662          * On BCM957508-N2100 adapters, FW will not allow any user other
 663          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 664          * always returns link up. Force phy update always in that case.
 665          */
 666         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 667                 rc = bnxt_set_hwrm_link_config(bp, true);
 668                 if (rc) {
 669                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 670                         return rc;
 671                 }
 672         }
 673
 674         return rc;
 675 }
 676
 677 static int bnxt_init_chip(struct bnxt *bp)
 678 {
 679         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 680         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 681         uint32_t intr_vector = 0;
 682         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 683         uint32_t vec = BNXT_MISC_VEC_ID;
 684         unsigned int i, j;
 685         int rc;
 686
 687         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 688                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 689                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 690                 bp->flags |= BNXT_FLAG_JUMBO;
 691         } else {
 692                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 693                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 694                 bp->flags &= ~BNXT_FLAG_JUMBO;
 695         }
 696
 697         /* THOR does not support ring groups.
 698          * But we will use the array to save RSS context IDs.
 699          */
 700         if (BNXT_CHIP_THOR(bp))
 701                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 702
 703         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 704         if (rc) {
 705                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 706                 goto err_out;
 707         }
 708
 709         rc = bnxt_alloc_hwrm_rings(bp);
 710         if (rc) {
 711                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 712                 goto err_out;
 713         }
 714
 715         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 716         if (rc) {
 717                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 718                 goto err_out;
 719         }
 720
 721         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 722                 goto skip_cosq_cfg;
 723
 724         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 725                 if (bp->rx_cos_queue[i].id != 0xff) {
 726                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 727
 728                         if (!vnic) {
 729                                 PMD_DRV_LOG(ERR,
 730                                             "Num pools more than FW profile\n");
 731                                 rc = -EINVAL;
 732                                 goto err_out;
 733                         }
 734                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 735                         bp->rx_cosq_cnt++;
 736                 }
 737         }
 738
 739 skip_cosq_cfg:
 740         rc = bnxt_mq_rx_configure(bp);
 741         if (rc) {
 742                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 743                 goto err_out;
 744         }
 745
 746         /* VNIC configuration */
 747         for (i = 0; i < bp->nr_vnics; i++) {
 748                 rc = bnxt_setup_one_vnic(bp, i);
 749                 if (rc)
 750                         goto err_out;
 751         }
 752
 753         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 754         if (rc) {
 755                 PMD_DRV_LOG(ERR,
 756                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 757                 goto err_out;
 758         }
 759
 760         /* check and configure queue intr-vector mapping */
 761         if ((rte_intr_cap_multiple(intr_handle) ||
 762              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 763             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 764                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 765                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 766                 if (intr_vector > bp->rx_cp_nr_rings) {
 767                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 768                                         bp->rx_cp_nr_rings);
 769                         return -ENOTSUP;
 770                 }
 771                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 772                 if (rc)
 773                         return rc;
 774         }
 775
 776         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 777                 intr_handle->intr_vec =
 778                         rte_zmalloc("intr_vec",
 779                                     bp->eth_dev->data->nb_rx_queues *
 780                                     sizeof(int), 0);
 781                 if (intr_handle->intr_vec == NULL) {
 782                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 783                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 784                         rc = -ENOMEM;
 785                         goto err_disable;
 786                 }
 787                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 788                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 789                          intr_handle->intr_vec, intr_handle->nb_efd,
 790                         intr_handle->max_intr);
 791                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 792                      queue_id++) {
 793                         intr_handle->intr_vec[queue_id] =
 794                                                         vec + BNXT_RX_VEC_START;
 795                         if (vec < base + intr_handle->nb_efd - 1)
 796                                 vec++;
 797                 }
 798         }
 799
 800         /* enable uio/vfio intr/eventfd mapping */
 801         rc = rte_intr_enable(intr_handle);
 802 #ifndef RTE_EXEC_ENV_FREEBSD
 803         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 804         if (rc)
 805                 goto err_free;
 806 #endif
 807
 808         rc = bnxt_update_phy_setting(bp);
 809         if (rc)
 810                 goto err_free;
 811
 812         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 813         if (!bp->mark_table)
 814                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 815
 816         return 0;
 817
 818 err_free:
 819         rte_free(intr_handle->intr_vec);
 820 err_disable:
 821         rte_intr_efd_disable(intr_handle);
 822 err_out:
 823         /* Some of the error status returned by FW may not be from errno.h */
 824         if (rc > 0)
 825                 rc = -EIO;
 826
 827         return rc;
 828 }
 829
 830 static int bnxt_shutdown_nic(struct bnxt *bp)
 831 {
 832         bnxt_free_all_hwrm_resources(bp);
 833         bnxt_free_all_filters(bp);
 834         bnxt_free_all_vnics(bp);
 835         return 0;
 836 }
 837
 838 /*
 839  * Device configuration and status function
 840  */
 841
 842 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 843 {
 844         uint32_t link_speed = bp->link_info->support_speeds;
 845         uint32_t speed_capa = 0;
 846
 847         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 848                 speed_capa |= ETH_LINK_SPEED_100M;
 849         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 850                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 851         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 852                 speed_capa |= ETH_LINK_SPEED_1G;
 853         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 854                 speed_capa |= ETH_LINK_SPEED_2_5G;
 855         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 856                 speed_capa |= ETH_LINK_SPEED_10G;
 857         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 858                 speed_capa |= ETH_LINK_SPEED_20G;
 859         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 860                 speed_capa |= ETH_LINK_SPEED_25G;
 861         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 862                 speed_capa |= ETH_LINK_SPEED_40G;
 863         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 864                 speed_capa |= ETH_LINK_SPEED_50G;
 865         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 866                 speed_capa |= ETH_LINK_SPEED_100G;
 867         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
 868                 speed_capa |= ETH_LINK_SPEED_50G;
 869         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
 870                 speed_capa |= ETH_LINK_SPEED_100G;
 871         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
 872                 speed_capa |= ETH_LINK_SPEED_200G;
 873
 874         if (bp->link_info->auto_mode ==
 875             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 876                 speed_capa |= ETH_LINK_SPEED_FIXED;
 877         else
 878                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 879
 880         return speed_capa;
 881 }
 882
 883 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 884                                 struct rte_eth_dev_info *dev_info)
 885 {
 886         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 887         struct bnxt *bp = eth_dev->data->dev_private;
 888         uint16_t max_vnics, i, j, vpool, vrxq;
 889         unsigned int max_rx_rings;
 890         int rc;
 891
 892         rc = is_bnxt_in_error(bp);
 893         if (rc)
 894                 return rc;
 895
 896         /* MAC Specifics */
 897         dev_info->max_mac_addrs = bp->max_l2_ctx;
 898         dev_info->max_hash_mac_addrs = 0;
 899
 900         /* PF/VF specifics */
 901         if (BNXT_PF(bp))
 902                 dev_info->max_vfs = pdev->max_vfs;
 903
 904         max_rx_rings = BNXT_MAX_RINGS(bp);
 905         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 906         dev_info->max_rx_queues = max_rx_rings;
 907         dev_info->max_tx_queues = max_rx_rings;
 908         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 909         dev_info->hash_key_size = 40;
 910         max_vnics = bp->max_vnics;
 911
 912         /* MTU specifics */
 913         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 914         dev_info->max_mtu = BNXT_MAX_MTU;
 915
 916         /* Fast path specifics */
 917         dev_info->min_rx_bufsize = 1;
 918         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 919
 920         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 921         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 922                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 923         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 924         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 925
 926         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 927
 928         /* *INDENT-OFF* */
 929         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 930                 .rx_thresh = {
 931                         .pthresh = 8,
 932                         .hthresh = 8,
 933                         .wthresh = 0,
 934                 },
 935                 .rx_free_thresh = 32,
 936                 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
 937         };
 938
 939         dev_info->default_txconf = (struct rte_eth_txconf) {
 940                 .tx_thresh = {
 941                         .pthresh = 32,
 942                         .hthresh = 0,
 943                         .wthresh = 0,
 944                 },
 945                 .tx_free_thresh = 32,
 946                 .tx_rs_thresh = 32,
 947         };
 948         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 949
 950         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 951         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 952         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 953         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 954         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 955
 956         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
 957                 dev_info->switch_info.name = eth_dev->device->name;
 958                 dev_info->switch_info.domain_id = bp->switch_domain_id;
 959                 dev_info->switch_info.port_id =
 960                                 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
 961                                     BNXT_SWITCH_PORT_ID_TRUSTED_VF;
 962         }
 963
 964         /* *INDENT-ON* */
 965
 966         /*
 967          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 968          *       need further investigation.
 969          */
 970
 971         /* VMDq resources */
 972         vpool = 64; /* ETH_64_POOLS */
 973         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 974         for (i = 0; i < 4; vpool >>= 1, i++) {
 975                 if (max_vnics > vpool) {
 976                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 977                                 if (dev_info->max_rx_queues > vrxq) {
 978                                         if (vpool > vrxq)
 979                                                 vpool = vrxq;
 980                                         goto found;
 981                                 }
 982                         }
 983                         /* Not enough resources to support VMDq */
 984                         break;
 985                 }
 986         }
 987         /* Not enough resources to support VMDq */
 988         vpool = 0;
 989         vrxq = 0;
 990 found:
 991         dev_info->max_vmdq_pools = vpool;
 992         dev_info->vmdq_queue_num = vrxq;
 993
 994         dev_info->vmdq_pool_base = 0;
 995         dev_info->vmdq_queue_base = 0;
 996
 997         return 0;
 998 }
 999
1000 /* Configure the device based on the configuration provided */
1001 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1002 {
1003         struct bnxt *bp = eth_dev->data->dev_private;
1004         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1005         int rc;
1006
1007         bp->rx_queues = (void *)eth_dev->data->rx_queues;
1008         bp->tx_queues = (void *)eth_dev->data->tx_queues;
1009         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1010         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1011
1012         rc = is_bnxt_in_error(bp);
1013         if (rc)
1014                 return rc;
1015
1016         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1017                 rc = bnxt_hwrm_check_vf_rings(bp);
1018                 if (rc) {
1019                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1020                         return -ENOSPC;
1021                 }
1022
1023                 /* If a resource has already been allocated - in this case
1024                  * it is the async completion ring, free it. Reallocate it after
1025                  * resource reservation. This will ensure the resource counts
1026                  * are calculated correctly.
1027                  */
1028
1029                 pthread_mutex_lock(&bp->def_cp_lock);
1030
1031                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1032                         bnxt_disable_int(bp);
1033                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
1034                 }
1035
1036                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1037                 if (rc) {
1038                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1039                         pthread_mutex_unlock(&bp->def_cp_lock);
1040                         return -ENOSPC;
1041                 }
1042
1043                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1044                         rc = bnxt_alloc_async_cp_ring(bp);
1045                         if (rc) {
1046                                 pthread_mutex_unlock(&bp->def_cp_lock);
1047                                 return rc;
1048                         }
1049                         bnxt_enable_int(bp);
1050                 }
1051
1052                 pthread_mutex_unlock(&bp->def_cp_lock);
1053         } else {
1054                 /* legacy driver needs to get updated values */
1055                 rc = bnxt_hwrm_func_qcaps(bp);
1056                 if (rc) {
1057                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
1058                         return rc;
1059                 }
1060         }
1061
1062         /* Inherit new configurations */
1063         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1064             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1065             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1066                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1067             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1068             bp->max_stat_ctx)
1069                 goto resource_error;
1070
1071         if (BNXT_HAS_RING_GRPS(bp) &&
1072             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1073                 goto resource_error;
1074
1075         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1076             bp->max_vnics < eth_dev->data->nb_rx_queues)
1077                 goto resource_error;
1078
1079         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1080         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1081
1082         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1083                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1084         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1085
1086         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1087                 eth_dev->data->mtu =
1088                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1089                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1090                         BNXT_NUM_VLANS;
1091                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1092         }
1093         return 0;
1094
1095 resource_error:
1096         PMD_DRV_LOG(ERR,
1097                     "Insufficient resources to support requested config\n");
1098         PMD_DRV_LOG(ERR,
1099                     "Num Queues Requested: Tx %d, Rx %d\n",
1100                     eth_dev->data->nb_tx_queues,
1101                     eth_dev->data->nb_rx_queues);
1102         PMD_DRV_LOG(ERR,
1103                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1104                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1105                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1106         return -ENOSPC;
1107 }
1108
1109 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1110 {
1111         struct rte_eth_link *link = &eth_dev->data->dev_link;
1112
1113         if (link->link_status)
1114                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1115                         eth_dev->data->port_id,
1116                         (uint32_t)link->link_speed,
1117                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1118                         ("full-duplex") : ("half-duplex\n"));
1119         else
1120                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1121                         eth_dev->data->port_id);
1122 }
1123
1124 /*
1125  * Determine whether the current configuration requires support for scattered
1126  * receive; return 1 if scattered receive is required and 0 if not.
1127  */
1128 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1129 {
1130         uint16_t buf_size;
1131         int i;
1132
1133         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1134                 return 1;
1135
1136         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1137                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1138
1139                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1140                                       RTE_PKTMBUF_HEADROOM);
1141                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1142                         return 1;
1143         }
1144         return 0;
1145 }
1146
1147 static eth_rx_burst_t
1148 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1149 {
1150         struct bnxt *bp = eth_dev->data->dev_private;
1151
1152 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1153 #ifndef RTE_LIBRTE_IEEE1588
1154         /*
1155          * Vector mode receive can be enabled only if scatter rx is not
1156          * in use and rx offloads are limited to VLAN stripping and
1157          * CRC stripping.
1158          */
1159         if (!eth_dev->data->scattered_rx &&
1160             !(eth_dev->data->dev_conf.rxmode.offloads &
1161               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1162                 DEV_RX_OFFLOAD_KEEP_CRC |
1163                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1164                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1165                 DEV_RX_OFFLOAD_UDP_CKSUM |
1166                 DEV_RX_OFFLOAD_TCP_CKSUM |
1167                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1168                 DEV_RX_OFFLOAD_RSS_HASH |
1169                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1170             !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp)) {
1171                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1172                             eth_dev->data->port_id);
1173                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1174                 return bnxt_recv_pkts_vec;
1175         }
1176         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1177                     eth_dev->data->port_id);
1178         PMD_DRV_LOG(INFO,
1179                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1180                     eth_dev->data->port_id,
1181                     eth_dev->data->scattered_rx,
1182                     eth_dev->data->dev_conf.rxmode.offloads);
1183 #endif
1184 #endif
1185         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1186         return bnxt_recv_pkts;
1187 }
1188
1189 static eth_tx_burst_t
1190 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1191 {
1192 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1193 #ifndef RTE_LIBRTE_IEEE1588
1194         struct bnxt *bp = eth_dev->data->dev_private;
1195
1196         /*
1197          * Vector mode transmit can be enabled only if not using scatter rx
1198          * or tx offloads.
1199          */
1200         if (!eth_dev->data->scattered_rx &&
1201             !eth_dev->data->dev_conf.txmode.offloads &&
1202             !BNXT_TRUFLOW_EN(bp)) {
1203                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1204                             eth_dev->data->port_id);
1205                 return bnxt_xmit_pkts_vec;
1206         }
1207         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1208                     eth_dev->data->port_id);
1209         PMD_DRV_LOG(INFO,
1210                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1211                     eth_dev->data->port_id,
1212                     eth_dev->data->scattered_rx,
1213                     eth_dev->data->dev_conf.txmode.offloads);
1214 #endif
1215 #endif
1216         return bnxt_xmit_pkts;
1217 }
1218
1219 static int bnxt_handle_if_change_status(struct bnxt *bp)
1220 {
1221         int rc;
1222
1223         /* Since fw has undergone a reset and lost all contexts,
1224          * set fatal flag to not issue hwrm during cleanup
1225          */
1226         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1227         bnxt_uninit_resources(bp, true);
1228
1229         /* clear fatal flag so that re-init happens */
1230         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1231         rc = bnxt_init_resources(bp, true);
1232
1233         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1234
1235         return rc;
1236 }
1237
1238 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1239 {
1240         struct bnxt *bp = eth_dev->data->dev_private;
1241         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1242         int vlan_mask = 0;
1243         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1244
1245         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1246                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1247                 return -EINVAL;
1248         }
1249
1250         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1251                 PMD_DRV_LOG(ERR,
1252                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1253                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1254         }
1255
1256         do {
1257                 rc = bnxt_hwrm_if_change(bp, true);
1258                 if (rc == 0 || rc != -EAGAIN)
1259                         break;
1260
1261                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1262         } while (retry_cnt--);
1263
1264         if (rc)
1265                 return rc;
1266
1267         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1268                 rc = bnxt_handle_if_change_status(bp);
1269                 if (rc)
1270                         return rc;
1271         }
1272
1273         bnxt_enable_int(bp);
1274
1275         rc = bnxt_init_chip(bp);
1276         if (rc)
1277                 goto error;
1278
1279         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1280         eth_dev->data->dev_started = 1;
1281
1282         bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1283
1284         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1285                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1286         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1287                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1288         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1289         if (rc)
1290                 goto error;
1291
1292         /* Initialize bnxt ULP port details */
1293         rc = bnxt_ulp_port_init(bp);
1294         if (rc)
1295                 goto error;
1296
1297         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1298         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1299
1300         bnxt_schedule_fw_health_check(bp);
1301
1302         return 0;
1303
1304 error:
1305         bnxt_shutdown_nic(bp);
1306         bnxt_free_tx_mbufs(bp);
1307         bnxt_free_rx_mbufs(bp);
1308         bnxt_hwrm_if_change(bp, false);
1309         eth_dev->data->dev_started = 0;
1310         return rc;
1311 }
1312
1313 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1314 {
1315         struct bnxt *bp = eth_dev->data->dev_private;
1316         int rc = 0;
1317
1318         if (!bp->link_info->link_up)
1319                 rc = bnxt_set_hwrm_link_config(bp, true);
1320         if (!rc)
1321                 eth_dev->data->dev_link.link_status = 1;
1322
1323         bnxt_print_link_info(eth_dev);
1324         return rc;
1325 }
1326
1327 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1328 {
1329         struct bnxt *bp = eth_dev->data->dev_private;
1330
1331         eth_dev->data->dev_link.link_status = 0;
1332         bnxt_set_hwrm_link_config(bp, false);
1333         bp->link_info->link_up = 0;
1334
1335         return 0;
1336 }
1337
1338 static void bnxt_free_switch_domain(struct bnxt *bp)
1339 {
1340         if (bp->switch_domain_id)
1341                 rte_eth_switch_domain_free(bp->switch_domain_id);
1342 }
1343
1344 /* Unload the driver, release resources */
1345 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1346 {
1347         struct bnxt *bp = eth_dev->data->dev_private;
1348         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1349         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1350
1351         eth_dev->data->dev_started = 0;
1352         eth_dev->data->scattered_rx = 0;
1353
1354         /* Prevent crashes when queues are still in use */
1355         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1356         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1357
1358         bnxt_disable_int(bp);
1359
1360         /* disable uio/vfio intr/eventfd mapping */
1361         rte_intr_disable(intr_handle);
1362
1363         /* Stop the child representors for this device */
1364         bnxt_rep_stop_all(bp);
1365
1366         /* delete the bnxt ULP port details */
1367         bnxt_ulp_port_deinit(bp);
1368
1369         bnxt_cancel_fw_health_check(bp);
1370
1371         /* Do not bring link down during reset recovery */
1372         if (!is_bnxt_in_error(bp))
1373                 bnxt_dev_set_link_down_op(eth_dev);
1374
1375         /* Wait for link to be reset and the async notification to process.
1376          * During reset recovery, there is no need to wait and
1377          * VF/NPAR functions do not have privilege to change PHY config.
1378          */
1379         if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1380                 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1381
1382         /* Clean queue intr-vector mapping */
1383         rte_intr_efd_disable(intr_handle);
1384         if (intr_handle->intr_vec != NULL) {
1385                 rte_free(intr_handle->intr_vec);
1386                 intr_handle->intr_vec = NULL;
1387         }
1388
1389         bnxt_hwrm_port_clr_stats(bp);
1390         bnxt_free_tx_mbufs(bp);
1391         bnxt_free_rx_mbufs(bp);
1392         /* Process any remaining notifications in default completion queue */
1393         bnxt_int_handler(eth_dev);
1394         bnxt_shutdown_nic(bp);
1395         bnxt_hwrm_if_change(bp, false);
1396
1397         rte_free(bp->mark_table);
1398         bp->mark_table = NULL;
1399
1400         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1401         bp->rx_cosq_cnt = 0;
1402         /* All filters are deleted on a port stop. */
1403         if (BNXT_FLOW_XSTATS_EN(bp))
1404                 bp->flow_stat->flow_count = 0;
1405 }
1406
1407 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1408 {
1409         struct bnxt *bp = eth_dev->data->dev_private;
1410
1411         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1412                 return 0;
1413
1414         /* cancel the recovery handler before remove dev */
1415         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1416         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1417         bnxt_cancel_fc_thread(bp);
1418
1419         if (eth_dev->data->dev_started)
1420                 bnxt_dev_stop_op(eth_dev);
1421
1422         bnxt_free_switch_domain(bp);
1423
1424         bnxt_uninit_resources(bp, false);
1425
1426         bnxt_free_leds_info(bp);
1427         bnxt_free_cos_queues(bp);
1428         bnxt_free_link_info(bp);
1429         bnxt_free_pf_info(bp);
1430         bnxt_free_parent_info(bp);
1431
1432         eth_dev->dev_ops = NULL;
1433         eth_dev->rx_pkt_burst = NULL;
1434         eth_dev->tx_pkt_burst = NULL;
1435
1436         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1437         bp->tx_mem_zone = NULL;
1438         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1439         bp->rx_mem_zone = NULL;
1440
1441         bnxt_hwrm_free_vf_info(bp);
1442
1443         rte_free(bp->grp_info);
1444         bp->grp_info = NULL;
1445
1446         return 0;
1447 }
1448
1449 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1450                                     uint32_t index)
1451 {
1452         struct bnxt *bp = eth_dev->data->dev_private;
1453         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1454         struct bnxt_vnic_info *vnic;
1455         struct bnxt_filter_info *filter, *temp_filter;
1456         uint32_t i;
1457
1458         if (is_bnxt_in_error(bp))
1459                 return;
1460
1461         /*
1462          * Loop through all VNICs from the specified filter flow pools to
1463          * remove the corresponding MAC addr filter
1464          */
1465         for (i = 0; i < bp->nr_vnics; i++) {
1466                 if (!(pool_mask & (1ULL << i)))
1467                         continue;
1468
1469                 vnic = &bp->vnic_info[i];
1470                 filter = STAILQ_FIRST(&vnic->filter);
1471                 while (filter) {
1472                         temp_filter = STAILQ_NEXT(filter, next);
1473                         if (filter->mac_index == index) {
1474                                 STAILQ_REMOVE(&vnic->filter, filter,
1475                                                 bnxt_filter_info, next);
1476                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1477                                 bnxt_free_filter(bp, filter);
1478                         }
1479                         filter = temp_filter;
1480                 }
1481         }
1482 }
1483
1484 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1485                                struct rte_ether_addr *mac_addr, uint32_t index,
1486                                uint32_t pool)
1487 {
1488         struct bnxt_filter_info *filter;
1489         int rc = 0;
1490
1491         /* Attach requested MAC address to the new l2_filter */
1492         STAILQ_FOREACH(filter, &vnic->filter, next) {
1493                 if (filter->mac_index == index) {
1494                         PMD_DRV_LOG(DEBUG,
1495                                     "MAC addr already existed for pool %d\n",
1496                                     pool);
1497                         return 0;
1498                 }
1499         }
1500
1501         filter = bnxt_alloc_filter(bp);
1502         if (!filter) {
1503                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1504                 return -ENODEV;
1505         }
1506
1507         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1508          * if the MAC that's been programmed now is a different one, then,
1509          * copy that addr to filter->l2_addr
1510          */
1511         if (mac_addr)
1512                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1513         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1514
1515         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1516         if (!rc) {
1517                 filter->mac_index = index;
1518                 if (filter->mac_index == 0)
1519                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1520                 else
1521                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1522         } else {
1523                 bnxt_free_filter(bp, filter);
1524         }
1525
1526         return rc;
1527 }
1528
1529 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1530                                 struct rte_ether_addr *mac_addr,
1531                                 uint32_t index, uint32_t pool)
1532 {
1533         struct bnxt *bp = eth_dev->data->dev_private;
1534         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1535         int rc = 0;
1536
1537         rc = is_bnxt_in_error(bp);
1538         if (rc)
1539                 return rc;
1540
1541         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1542                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1543                 return -ENOTSUP;
1544         }
1545
1546         if (!vnic) {
1547                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1548                 return -EINVAL;
1549         }
1550
1551         /* Filter settings will get applied when port is started */
1552         if (!eth_dev->data->dev_started)
1553                 return 0;
1554
1555         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1556
1557         return rc;
1558 }
1559
1560 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1561                      bool exp_link_status)
1562 {
1563         int rc = 0;
1564         struct bnxt *bp = eth_dev->data->dev_private;
1565         struct rte_eth_link new;
1566         int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1567                   BNXT_LINK_DOWN_WAIT_CNT;
1568
1569         rc = is_bnxt_in_error(bp);
1570         if (rc)
1571                 return rc;
1572
1573         memset(&new, 0, sizeof(new));
1574         do {
1575                 /* Retrieve link info from hardware */
1576                 rc = bnxt_get_hwrm_link_config(bp, &new);
1577                 if (rc) {
1578                         new.link_speed = ETH_LINK_SPEED_100M;
1579                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1580                         PMD_DRV_LOG(ERR,
1581                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1582                         goto out;
1583                 }
1584
1585                 if (!wait_to_complete || new.link_status == exp_link_status)
1586                         break;
1587
1588                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1589         } while (cnt--);
1590
1591 out:
1592         /* Timed out or success */
1593         if (new.link_status != eth_dev->data->dev_link.link_status ||
1594         new.link_speed != eth_dev->data->dev_link.link_speed) {
1595                 rte_eth_linkstatus_set(eth_dev, &new);
1596
1597                 rte_eth_dev_callback_process(eth_dev,
1598                                              RTE_ETH_EVENT_INTR_LSC,
1599                                              NULL);
1600
1601                 bnxt_print_link_info(eth_dev);
1602         }
1603
1604         return rc;
1605 }
1606
1607 int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1608                         int wait_to_complete)
1609 {
1610         return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1611 }
1612
1613 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1614 {
1615         struct bnxt *bp = eth_dev->data->dev_private;
1616         struct bnxt_vnic_info *vnic;
1617         uint32_t old_flags;
1618         int rc;
1619
1620         rc = is_bnxt_in_error(bp);
1621         if (rc)
1622                 return rc;
1623
1624         /* Filter settings will get applied when port is started */
1625         if (!eth_dev->data->dev_started)
1626                 return 0;
1627
1628         if (bp->vnic_info == NULL)
1629                 return 0;
1630
1631         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1632
1633         old_flags = vnic->flags;
1634         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1635         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1636         if (rc != 0)
1637                 vnic->flags = old_flags;
1638
1639         return rc;
1640 }
1641
1642 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1643 {
1644         struct bnxt *bp = eth_dev->data->dev_private;
1645         struct bnxt_vnic_info *vnic;
1646         uint32_t old_flags;
1647         int rc;
1648
1649         rc = is_bnxt_in_error(bp);
1650         if (rc)
1651                 return rc;
1652
1653         /* Filter settings will get applied when port is started */
1654         if (!eth_dev->data->dev_started)
1655                 return 0;
1656
1657         if (bp->vnic_info == NULL)
1658                 return 0;
1659
1660         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1661
1662         old_flags = vnic->flags;
1663         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1664         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1665         if (rc != 0)
1666                 vnic->flags = old_flags;
1667
1668         return rc;
1669 }
1670
1671 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1672 {
1673         struct bnxt *bp = eth_dev->data->dev_private;
1674         struct bnxt_vnic_info *vnic;
1675         uint32_t old_flags;
1676         int rc;
1677
1678         rc = is_bnxt_in_error(bp);
1679         if (rc)
1680                 return rc;
1681
1682         /* Filter settings will get applied when port is started */
1683         if (!eth_dev->data->dev_started)
1684                 return 0;
1685
1686         if (bp->vnic_info == NULL)
1687                 return 0;
1688
1689         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1690
1691         old_flags = vnic->flags;
1692         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1693         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1694         if (rc != 0)
1695                 vnic->flags = old_flags;
1696
1697         return rc;
1698 }
1699
1700 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1701 {
1702         struct bnxt *bp = eth_dev->data->dev_private;
1703         struct bnxt_vnic_info *vnic;
1704         uint32_t old_flags;
1705         int rc;
1706
1707         rc = is_bnxt_in_error(bp);
1708         if (rc)
1709                 return rc;
1710
1711         /* Filter settings will get applied when port is started */
1712         if (!eth_dev->data->dev_started)
1713                 return 0;
1714
1715         if (bp->vnic_info == NULL)
1716                 return 0;
1717
1718         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1719
1720         old_flags = vnic->flags;
1721         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1722         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1723         if (rc != 0)
1724                 vnic->flags = old_flags;
1725
1726         return rc;
1727 }
1728
1729 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1730 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1731 {
1732         if (qid >= bp->rx_nr_rings)
1733                 return NULL;
1734
1735         return bp->eth_dev->data->rx_queues[qid];
1736 }
1737
1738 /* Return rxq corresponding to a given rss table ring/group ID. */
1739 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1740 {
1741         struct bnxt_rx_queue *rxq;
1742         unsigned int i;
1743
1744         if (!BNXT_HAS_RING_GRPS(bp)) {
1745                 for (i = 0; i < bp->rx_nr_rings; i++) {
1746                         rxq = bp->eth_dev->data->rx_queues[i];
1747                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1748                                 return rxq->index;
1749                 }
1750         } else {
1751                 for (i = 0; i < bp->rx_nr_rings; i++) {
1752                         if (bp->grp_info[i].fw_grp_id == fwr)
1753                                 return i;
1754                 }
1755         }
1756
1757         return INVALID_HW_RING_ID;
1758 }
1759
1760 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1761                             struct rte_eth_rss_reta_entry64 *reta_conf,
1762                             uint16_t reta_size)
1763 {
1764         struct bnxt *bp = eth_dev->data->dev_private;
1765         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1766         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1767         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1768         uint16_t idx, sft;
1769         int i, rc;
1770
1771         rc = is_bnxt_in_error(bp);
1772         if (rc)
1773                 return rc;
1774
1775         if (!vnic->rss_table)
1776                 return -EINVAL;
1777
1778         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1779                 return -EINVAL;
1780
1781         if (reta_size != tbl_size) {
1782                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1783                         "(%d) must equal the size supported by the hardware "
1784                         "(%d)\n", reta_size, tbl_size);
1785                 return -EINVAL;
1786         }
1787
1788         for (i = 0; i < reta_size; i++) {
1789                 struct bnxt_rx_queue *rxq;
1790
1791                 idx = i / RTE_RETA_GROUP_SIZE;
1792                 sft = i % RTE_RETA_GROUP_SIZE;
1793
1794                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1795                         continue;
1796
1797                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1798                 if (!rxq) {
1799                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1800                         return -EINVAL;
1801                 }
1802
1803                 if (BNXT_CHIP_THOR(bp)) {
1804                         vnic->rss_table[i * 2] =
1805                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1806                         vnic->rss_table[i * 2 + 1] =
1807                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1808                 } else {
1809                         vnic->rss_table[i] =
1810                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1811                 }
1812         }
1813
1814         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1815         return 0;
1816 }
1817
1818 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1819                               struct rte_eth_rss_reta_entry64 *reta_conf,
1820                               uint16_t reta_size)
1821 {
1822         struct bnxt *bp = eth_dev->data->dev_private;
1823         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1824         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1825         uint16_t idx, sft, i;
1826         int rc;
1827
1828         rc = is_bnxt_in_error(bp);
1829         if (rc)
1830                 return rc;
1831
1832         /* Retrieve from the default VNIC */
1833         if (!vnic)
1834                 return -EINVAL;
1835         if (!vnic->rss_table)
1836                 return -EINVAL;
1837
1838         if (reta_size != tbl_size) {
1839                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1840                         "(%d) must equal the size supported by the hardware "
1841                         "(%d)\n", reta_size, tbl_size);
1842                 return -EINVAL;
1843         }
1844
1845         for (idx = 0, i = 0; i < reta_size; i++) {
1846                 idx = i / RTE_RETA_GROUP_SIZE;
1847                 sft = i % RTE_RETA_GROUP_SIZE;
1848
1849                 if (reta_conf[idx].mask & (1ULL << sft)) {
1850                         uint16_t qid;
1851
1852                         if (BNXT_CHIP_THOR(bp))
1853                                 qid = bnxt_rss_to_qid(bp,
1854                                                       vnic->rss_table[i * 2]);
1855                         else
1856                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1857
1858                         if (qid == INVALID_HW_RING_ID) {
1859                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1860                                 return -EINVAL;
1861                         }
1862                         reta_conf[idx].reta[sft] = qid;
1863                 }
1864         }
1865
1866         return 0;
1867 }
1868
1869 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1870                                    struct rte_eth_rss_conf *rss_conf)
1871 {
1872         struct bnxt *bp = eth_dev->data->dev_private;
1873         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1874         struct bnxt_vnic_info *vnic;
1875         int rc;
1876
1877         rc = is_bnxt_in_error(bp);
1878         if (rc)
1879                 return rc;
1880
1881         /*
1882          * If RSS enablement were different than dev_configure,
1883          * then return -EINVAL
1884          */
1885         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1886                 if (!rss_conf->rss_hf)
1887                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1888         } else {
1889                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1890                         return -EINVAL;
1891         }
1892
1893         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1894         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
1895                rss_conf,
1896                sizeof(*rss_conf));
1897
1898         /* Update the default RSS VNIC(s) */
1899         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1900         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1901         vnic->hash_mode =
1902                 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
1903                                             ETH_RSS_LEVEL(rss_conf->rss_hf));
1904
1905         /*
1906          * If hashkey is not specified, use the previously configured
1907          * hashkey
1908          */
1909         if (!rss_conf->rss_key)
1910                 goto rss_config;
1911
1912         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1913                 PMD_DRV_LOG(ERR,
1914                             "Invalid hashkey length, should be 16 bytes\n");
1915                 return -EINVAL;
1916         }
1917         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1918
1919 rss_config:
1920         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1921         return 0;
1922 }
1923
1924 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1925                                      struct rte_eth_rss_conf *rss_conf)
1926 {
1927         struct bnxt *bp = eth_dev->data->dev_private;
1928         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1929         int len, rc;
1930         uint32_t hash_types;
1931
1932         rc = is_bnxt_in_error(bp);
1933         if (rc)
1934                 return rc;
1935
1936         /* RSS configuration is the same for all VNICs */
1937         if (vnic && vnic->rss_hash_key) {
1938                 if (rss_conf->rss_key) {
1939                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1940                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1941                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1942                 }
1943
1944                 hash_types = vnic->hash_type;
1945                 rss_conf->rss_hf = 0;
1946                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1947                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1948                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1949                 }
1950                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1951                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1952                         hash_types &=
1953                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1954                 }
1955                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1956                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1957                         hash_types &=
1958                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1959                 }
1960                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1961                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1962                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1963                 }
1964                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1965                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1966                         hash_types &=
1967                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1968                 }
1969                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1970                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1971                         hash_types &=
1972                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1973                 }
1974
1975                 rss_conf->rss_hf |=
1976                         bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
1977
1978                 if (hash_types) {
1979                         PMD_DRV_LOG(ERR,
1980                                 "Unknown RSS config from firmware (%08x), RSS disabled",
1981                                 vnic->hash_type);
1982                         return -ENOTSUP;
1983                 }
1984         } else {
1985                 rss_conf->rss_hf = 0;
1986         }
1987         return 0;
1988 }
1989
1990 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1991                                struct rte_eth_fc_conf *fc_conf)
1992 {
1993         struct bnxt *bp = dev->data->dev_private;
1994         struct rte_eth_link link_info;
1995         int rc;
1996
1997         rc = is_bnxt_in_error(bp);
1998         if (rc)
1999                 return rc;
2000
2001         rc = bnxt_get_hwrm_link_config(bp, &link_info);
2002         if (rc)
2003                 return rc;
2004
2005         memset(fc_conf, 0, sizeof(*fc_conf));
2006         if (bp->link_info->auto_pause)
2007                 fc_conf->autoneg = 1;
2008         switch (bp->link_info->pause) {
2009         case 0:
2010                 fc_conf->mode = RTE_FC_NONE;
2011                 break;
2012         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2013                 fc_conf->mode = RTE_FC_TX_PAUSE;
2014                 break;
2015         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2016                 fc_conf->mode = RTE_FC_RX_PAUSE;
2017                 break;
2018         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2019                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2020                 fc_conf->mode = RTE_FC_FULL;
2021                 break;
2022         }
2023         return 0;
2024 }
2025
2026 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2027                                struct rte_eth_fc_conf *fc_conf)
2028 {
2029         struct bnxt *bp = dev->data->dev_private;
2030         int rc;
2031
2032         rc = is_bnxt_in_error(bp);
2033         if (rc)
2034                 return rc;
2035
2036         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2037                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2038                 return -ENOTSUP;
2039         }
2040
2041         switch (fc_conf->mode) {
2042         case RTE_FC_NONE:
2043                 bp->link_info->auto_pause = 0;
2044                 bp->link_info->force_pause = 0;
2045                 break;
2046         case RTE_FC_RX_PAUSE:
2047                 if (fc_conf->autoneg) {
2048                         bp->link_info->auto_pause =
2049                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2050                         bp->link_info->force_pause = 0;
2051                 } else {
2052                         bp->link_info->auto_pause = 0;
2053                         bp->link_info->force_pause =
2054                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2055                 }
2056                 break;
2057         case RTE_FC_TX_PAUSE:
2058                 if (fc_conf->autoneg) {
2059                         bp->link_info->auto_pause =
2060                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2061                         bp->link_info->force_pause = 0;
2062                 } else {
2063                         bp->link_info->auto_pause = 0;
2064                         bp->link_info->force_pause =
2065                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2066                 }
2067                 break;
2068         case RTE_FC_FULL:
2069                 if (fc_conf->autoneg) {
2070                         bp->link_info->auto_pause =
2071                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2072                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2073                         bp->link_info->force_pause = 0;
2074                 } else {
2075                         bp->link_info->auto_pause = 0;
2076                         bp->link_info->force_pause =
2077                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2078                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2079                 }
2080                 break;
2081         }
2082         return bnxt_set_hwrm_link_config(bp, true);
2083 }
2084
2085 /* Add UDP tunneling port */
2086 static int
2087 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2088                          struct rte_eth_udp_tunnel *udp_tunnel)
2089 {
2090         struct bnxt *bp = eth_dev->data->dev_private;
2091         uint16_t tunnel_type = 0;
2092         int rc = 0;
2093
2094         rc = is_bnxt_in_error(bp);
2095         if (rc)
2096                 return rc;
2097
2098         switch (udp_tunnel->prot_type) {
2099         case RTE_TUNNEL_TYPE_VXLAN:
2100                 if (bp->vxlan_port_cnt) {
2101                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2102                                 udp_tunnel->udp_port);
2103                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2104                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2105                                 return -ENOSPC;
2106                         }
2107                         bp->vxlan_port_cnt++;
2108                         return 0;
2109                 }
2110                 tunnel_type =
2111                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2112                 bp->vxlan_port_cnt++;
2113                 break;
2114         case RTE_TUNNEL_TYPE_GENEVE:
2115                 if (bp->geneve_port_cnt) {
2116                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2117                                 udp_tunnel->udp_port);
2118                         if (bp->geneve_port != udp_tunnel->udp_port) {
2119                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2120                                 return -ENOSPC;
2121                         }
2122                         bp->geneve_port_cnt++;
2123                         return 0;
2124                 }
2125                 tunnel_type =
2126                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2127                 bp->geneve_port_cnt++;
2128                 break;
2129         default:
2130                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2131                 return -ENOTSUP;
2132         }
2133         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2134                                              tunnel_type);
2135         return rc;
2136 }
2137
2138 static int
2139 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2140                          struct rte_eth_udp_tunnel *udp_tunnel)
2141 {
2142         struct bnxt *bp = eth_dev->data->dev_private;
2143         uint16_t tunnel_type = 0;
2144         uint16_t port = 0;
2145         int rc = 0;
2146
2147         rc = is_bnxt_in_error(bp);
2148         if (rc)
2149                 return rc;
2150
2151         switch (udp_tunnel->prot_type) {
2152         case RTE_TUNNEL_TYPE_VXLAN:
2153                 if (!bp->vxlan_port_cnt) {
2154                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2155                         return -EINVAL;
2156                 }
2157                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2158                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2159                                 udp_tunnel->udp_port, bp->vxlan_port);
2160                         return -EINVAL;
2161                 }
2162                 if (--bp->vxlan_port_cnt)
2163                         return 0;
2164
2165                 tunnel_type =
2166                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2167                 port = bp->vxlan_fw_dst_port_id;
2168                 break;
2169         case RTE_TUNNEL_TYPE_GENEVE:
2170                 if (!bp->geneve_port_cnt) {
2171                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2172                         return -EINVAL;
2173                 }
2174                 if (bp->geneve_port != udp_tunnel->udp_port) {
2175                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2176                                 udp_tunnel->udp_port, bp->geneve_port);
2177                         return -EINVAL;
2178                 }
2179                 if (--bp->geneve_port_cnt)
2180                         return 0;
2181
2182                 tunnel_type =
2183                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2184                 port = bp->geneve_fw_dst_port_id;
2185                 break;
2186         default:
2187                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2188                 return -ENOTSUP;
2189         }
2190
2191         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2192         if (!rc) {
2193                 if (tunnel_type ==
2194                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
2195                         bp->vxlan_port = 0;
2196                 if (tunnel_type ==
2197                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
2198                         bp->geneve_port = 0;
2199         }
2200         return rc;
2201 }
2202
2203 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2204 {
2205         struct bnxt_filter_info *filter;
2206         struct bnxt_vnic_info *vnic;
2207         int rc = 0;
2208         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2209
2210         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2211         filter = STAILQ_FIRST(&vnic->filter);
2212         while (filter) {
2213                 /* Search for this matching MAC+VLAN filter */
2214                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2215                         /* Delete the filter */
2216                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2217                         if (rc)
2218                                 return rc;
2219                         STAILQ_REMOVE(&vnic->filter, filter,
2220                                       bnxt_filter_info, next);
2221                         bnxt_free_filter(bp, filter);
2222                         PMD_DRV_LOG(INFO,
2223                                     "Deleted vlan filter for %d\n",
2224                                     vlan_id);
2225                         return 0;
2226                 }
2227                 filter = STAILQ_NEXT(filter, next);
2228         }
2229         return -ENOENT;
2230 }
2231
2232 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2233 {
2234         struct bnxt_filter_info *filter;
2235         struct bnxt_vnic_info *vnic;
2236         int rc = 0;
2237         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2238                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2239         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2240
2241         /* Implementation notes on the use of VNIC in this command:
2242          *
2243          * By default, these filters belong to default vnic for the function.
2244          * Once these filters are set up, only destination VNIC can be modified.
2245          * If the destination VNIC is not specified in this command,
2246          * then the HWRM shall only create an l2 context id.
2247          */
2248
2249         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2250         filter = STAILQ_FIRST(&vnic->filter);
2251         /* Check if the VLAN has already been added */
2252         while (filter) {
2253                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2254                         return -EEXIST;
2255
2256                 filter = STAILQ_NEXT(filter, next);
2257         }
2258
2259         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2260          * command to create MAC+VLAN filter with the right flags, enables set.
2261          */
2262         filter = bnxt_alloc_filter(bp);
2263         if (!filter) {
2264                 PMD_DRV_LOG(ERR,
2265                             "MAC/VLAN filter alloc failed\n");
2266                 return -ENOMEM;
2267         }
2268         /* MAC + VLAN ID filter */
2269         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2270          * untagged packets are received
2271          *
2272          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2273          * packets and only the programmed vlan's packets are received
2274          */
2275         filter->l2_ivlan = vlan_id;
2276         filter->l2_ivlan_mask = 0x0FFF;
2277         filter->enables |= en;
2278         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2279
2280         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2281         if (rc) {
2282                 /* Free the newly allocated filter as we were
2283                  * not able to create the filter in hardware.
2284                  */
2285                 bnxt_free_filter(bp, filter);
2286                 return rc;
2287         }
2288
2289         filter->mac_index = 0;
2290         /* Add this new filter to the list */
2291         if (vlan_id == 0)
2292                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2293         else
2294                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2295
2296         PMD_DRV_LOG(INFO,
2297                     "Added Vlan filter for %d\n", vlan_id);
2298         return rc;
2299 }
2300
2301 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2302                 uint16_t vlan_id, int on)
2303 {
2304         struct bnxt *bp = eth_dev->data->dev_private;
2305         int rc;
2306
2307         rc = is_bnxt_in_error(bp);
2308         if (rc)
2309                 return rc;
2310
2311         if (!eth_dev->data->dev_started) {
2312                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2313                 return -EINVAL;
2314         }
2315
2316         /* These operations apply to ALL existing MAC/VLAN filters */
2317         if (on)
2318                 return bnxt_add_vlan_filter(bp, vlan_id);
2319         else
2320                 return bnxt_del_vlan_filter(bp, vlan_id);
2321 }
2322
2323 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2324                                     struct bnxt_vnic_info *vnic)
2325 {
2326         struct bnxt_filter_info *filter;
2327         int rc;
2328
2329         filter = STAILQ_FIRST(&vnic->filter);
2330         while (filter) {
2331                 if (filter->mac_index == 0 &&
2332                     !memcmp(filter->l2_addr, bp->mac_addr,
2333                             RTE_ETHER_ADDR_LEN)) {
2334                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2335                         if (!rc) {
2336                                 STAILQ_REMOVE(&vnic->filter, filter,
2337                                               bnxt_filter_info, next);
2338                                 bnxt_free_filter(bp, filter);
2339                         }
2340                         return rc;
2341                 }
2342                 filter = STAILQ_NEXT(filter, next);
2343         }
2344         return 0;
2345 }
2346
2347 static int
2348 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2349 {
2350         struct bnxt_vnic_info *vnic;
2351         unsigned int i;
2352         int rc;
2353
2354         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2355         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2356                 /* Remove any VLAN filters programmed */
2357                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2358                         bnxt_del_vlan_filter(bp, i);
2359
2360                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2361                 if (rc)
2362                         return rc;
2363         } else {
2364                 /* Default filter will allow packets that match the
2365                  * dest mac. So, it has to be deleted, otherwise, we
2366                  * will endup receiving vlan packets for which the
2367                  * filter is not programmed, when hw-vlan-filter
2368                  * configuration is ON
2369                  */
2370                 bnxt_del_dflt_mac_filter(bp, vnic);
2371                 /* This filter will allow only untagged packets */
2372                 bnxt_add_vlan_filter(bp, 0);
2373         }
2374         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2375                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2376
2377         return 0;
2378 }
2379
2380 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2381 {
2382         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2383         unsigned int i;
2384         int rc;
2385
2386         /* Destroy vnic filters and vnic */
2387         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2388             DEV_RX_OFFLOAD_VLAN_FILTER) {
2389                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2390                         bnxt_del_vlan_filter(bp, i);
2391         }
2392         bnxt_del_dflt_mac_filter(bp, vnic);
2393
2394         rc = bnxt_hwrm_vnic_free(bp, vnic);
2395         if (rc)
2396                 return rc;
2397
2398         rte_free(vnic->fw_grp_ids);
2399         vnic->fw_grp_ids = NULL;
2400
2401         vnic->rx_queue_cnt = 0;
2402
2403         return 0;
2404 }
2405
2406 static int
2407 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2408 {
2409         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2410         int rc;
2411
2412         /* Destroy, recreate and reconfigure the default vnic */
2413         rc = bnxt_free_one_vnic(bp, 0);
2414         if (rc)
2415                 return rc;
2416
2417         /* default vnic 0 */
2418         rc = bnxt_setup_one_vnic(bp, 0);
2419         if (rc)
2420                 return rc;
2421
2422         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2423             DEV_RX_OFFLOAD_VLAN_FILTER) {
2424                 rc = bnxt_add_vlan_filter(bp, 0);
2425                 if (rc)
2426                         return rc;
2427                 rc = bnxt_restore_vlan_filters(bp);
2428                 if (rc)
2429                         return rc;
2430         } else {
2431                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2432                 if (rc)
2433                         return rc;
2434         }
2435
2436         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2437         if (rc)
2438                 return rc;
2439
2440         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2441                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2442
2443         return rc;
2444 }
2445
2446 static int
2447 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2448 {
2449         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2450         struct bnxt *bp = dev->data->dev_private;
2451         int rc;
2452
2453         rc = is_bnxt_in_error(bp);
2454         if (rc)
2455                 return rc;
2456
2457         /* Filter settings will get applied when port is started */
2458         if (!dev->data->dev_started)
2459                 return 0;
2460
2461         if (mask & ETH_VLAN_FILTER_MASK) {
2462                 /* Enable or disable VLAN filtering */
2463                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2464                 if (rc)
2465                         return rc;
2466         }
2467
2468         if (mask & ETH_VLAN_STRIP_MASK) {
2469                 /* Enable or disable VLAN stripping */
2470                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2471                 if (rc)
2472                         return rc;
2473         }
2474
2475         if (mask & ETH_VLAN_EXTEND_MASK) {
2476                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2477                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2478                 else
2479                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2480         }
2481
2482         return 0;
2483 }
2484
2485 static int
2486 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2487                       uint16_t tpid)
2488 {
2489         struct bnxt *bp = dev->data->dev_private;
2490         int qinq = dev->data->dev_conf.rxmode.offloads &
2491                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2492
2493         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2494             vlan_type != ETH_VLAN_TYPE_OUTER) {
2495                 PMD_DRV_LOG(ERR,
2496                             "Unsupported vlan type.");
2497                 return -EINVAL;
2498         }
2499         if (!qinq) {
2500                 PMD_DRV_LOG(ERR,
2501                             "QinQ not enabled. Needs to be ON as we can "
2502                             "accelerate only outer vlan\n");
2503                 return -EINVAL;
2504         }
2505
2506         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2507                 switch (tpid) {
2508                 case RTE_ETHER_TYPE_QINQ:
2509                         bp->outer_tpid_bd =
2510                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2511                                 break;
2512                 case RTE_ETHER_TYPE_VLAN:
2513                         bp->outer_tpid_bd =
2514                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2515                                 break;
2516                 case RTE_ETHER_TYPE_QINQ1:
2517                         bp->outer_tpid_bd =
2518                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2519                                 break;
2520                 case RTE_ETHER_TYPE_QINQ2:
2521                         bp->outer_tpid_bd =
2522                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2523                                 break;
2524                 case RTE_ETHER_TYPE_QINQ3:
2525                         bp->outer_tpid_bd =
2526                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2527                                 break;
2528                 default:
2529                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2530                         return -EINVAL;
2531                 }
2532                 bp->outer_tpid_bd |= tpid;
2533                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2534         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2535                 PMD_DRV_LOG(ERR,
2536                             "Can accelerate only outer vlan in QinQ\n");
2537                 return -EINVAL;
2538         }
2539
2540         return 0;
2541 }
2542
2543 static int
2544 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2545                              struct rte_ether_addr *addr)
2546 {
2547         struct bnxt *bp = dev->data->dev_private;
2548         /* Default Filter is tied to VNIC 0 */
2549         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2550         int rc;
2551
2552         rc = is_bnxt_in_error(bp);
2553         if (rc)
2554                 return rc;
2555
2556         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2557                 return -EPERM;
2558
2559         if (rte_is_zero_ether_addr(addr))
2560                 return -EINVAL;
2561
2562         /* Filter settings will get applied when port is started */
2563         if (!dev->data->dev_started)
2564                 return 0;
2565
2566         /* Check if the requested MAC is already added */
2567         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2568                 return 0;
2569
2570         /* Destroy filter and re-create it */
2571         bnxt_del_dflt_mac_filter(bp, vnic);
2572
2573         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2574         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2575                 /* This filter will allow only untagged packets */
2576                 rc = bnxt_add_vlan_filter(bp, 0);
2577         } else {
2578                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2579         }
2580
2581         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2582         return rc;
2583 }
2584
2585 static int
2586 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2587                           struct rte_ether_addr *mc_addr_set,
2588                           uint32_t nb_mc_addr)
2589 {
2590         struct bnxt *bp = eth_dev->data->dev_private;
2591         char *mc_addr_list = (char *)mc_addr_set;
2592         struct bnxt_vnic_info *vnic;
2593         uint32_t off = 0, i = 0;
2594         int rc;
2595
2596         rc = is_bnxt_in_error(bp);
2597         if (rc)
2598                 return rc;
2599
2600         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2601
2602         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2603                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2604                 goto allmulti;
2605         }
2606
2607         /* TODO Check for Duplicate mcast addresses */
2608         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2609         for (i = 0; i < nb_mc_addr; i++) {
2610                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2611                         RTE_ETHER_ADDR_LEN);
2612                 off += RTE_ETHER_ADDR_LEN;
2613         }
2614
2615         vnic->mc_addr_cnt = i;
2616         if (vnic->mc_addr_cnt)
2617                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2618         else
2619                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2620
2621 allmulti:
2622         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2623 }
2624
2625 static int
2626 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2627 {
2628         struct bnxt *bp = dev->data->dev_private;
2629         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2630         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2631         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2632         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2633         int ret;
2634
2635         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2636                         fw_major, fw_minor, fw_updt, fw_rsvd);
2637
2638         ret += 1; /* add the size of '\0' */
2639         if (fw_size < (uint32_t)ret)
2640                 return ret;
2641         else
2642                 return 0;
2643 }
2644
2645 static void
2646 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2647         struct rte_eth_rxq_info *qinfo)
2648 {
2649         struct bnxt *bp = dev->data->dev_private;
2650         struct bnxt_rx_queue *rxq;
2651
2652         if (is_bnxt_in_error(bp))
2653                 return;
2654
2655         rxq = dev->data->rx_queues[queue_id];
2656
2657         qinfo->mp = rxq->mb_pool;
2658         qinfo->scattered_rx = dev->data->scattered_rx;
2659         qinfo->nb_desc = rxq->nb_rx_desc;
2660
2661         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2662         qinfo->conf.rx_drop_en = rxq->drop_en;
2663         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2664         qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2665 }
2666
2667 static void
2668 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2669         struct rte_eth_txq_info *qinfo)
2670 {
2671         struct bnxt *bp = dev->data->dev_private;
2672         struct bnxt_tx_queue *txq;
2673
2674         if (is_bnxt_in_error(bp))
2675                 return;
2676
2677         txq = dev->data->tx_queues[queue_id];
2678
2679         qinfo->nb_desc = txq->nb_tx_desc;
2680
2681         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2682         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2683         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2684
2685         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2686         qinfo->conf.tx_rs_thresh = 0;
2687         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2688         qinfo->conf.offloads = dev->data->dev_conf.txmode.offloads;
2689 }
2690
2691 static const struct {
2692         eth_rx_burst_t pkt_burst;
2693         const char *info;
2694 } bnxt_rx_burst_info[] = {
2695         {bnxt_recv_pkts,        "Scalar"},
2696 #if defined(RTE_ARCH_X86)
2697         {bnxt_recv_pkts_vec,    "Vector SSE"},
2698 #elif defined(RTE_ARCH_ARM64)
2699         {bnxt_recv_pkts_vec,    "Vector Neon"},
2700 #endif
2701 };
2702
2703 static int
2704 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2705                        struct rte_eth_burst_mode *mode)
2706 {
2707         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2708         size_t i;
2709
2710         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2711                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2712                         snprintf(mode->info, sizeof(mode->info), "%s",
2713                                  bnxt_rx_burst_info[i].info);
2714                         return 0;
2715                 }
2716         }
2717
2718         return -EINVAL;
2719 }
2720
2721 static const struct {
2722         eth_tx_burst_t pkt_burst;
2723         const char *info;
2724 } bnxt_tx_burst_info[] = {
2725         {bnxt_xmit_pkts,        "Scalar"},
2726 #if defined(RTE_ARCH_X86)
2727         {bnxt_xmit_pkts_vec,    "Vector SSE"},
2728 #elif defined(RTE_ARCH_ARM64)
2729         {bnxt_xmit_pkts_vec,    "Vector Neon"},
2730 #endif
2731 };
2732
2733 static int
2734 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2735                        struct rte_eth_burst_mode *mode)
2736 {
2737         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2738         size_t i;
2739
2740         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2741                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2742                         snprintf(mode->info, sizeof(mode->info), "%s",
2743                                  bnxt_tx_burst_info[i].info);
2744                         return 0;
2745                 }
2746         }
2747
2748         return -EINVAL;
2749 }
2750
2751 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2752 {
2753         struct bnxt *bp = eth_dev->data->dev_private;
2754         uint32_t new_pkt_size;
2755         uint32_t rc = 0;
2756         uint32_t i;
2757
2758         rc = is_bnxt_in_error(bp);
2759         if (rc)
2760                 return rc;
2761
2762         /* Exit if receive queues are not configured yet */
2763         if (!eth_dev->data->nb_rx_queues)
2764                 return rc;
2765
2766         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2767                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2768
2769         /*
2770          * Disallow any MTU change that would require scattered receive support
2771          * if it is not already enabled.
2772          */
2773         if (eth_dev->data->dev_started &&
2774             !eth_dev->data->scattered_rx &&
2775             (new_pkt_size >
2776              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2777                 PMD_DRV_LOG(ERR,
2778                             "MTU change would require scattered rx support. ");
2779                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2780                 return -EINVAL;
2781         }
2782
2783         if (new_mtu > RTE_ETHER_MTU) {
2784                 bp->flags |= BNXT_FLAG_JUMBO;
2785                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2786                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2787         } else {
2788                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2789                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2790                 bp->flags &= ~BNXT_FLAG_JUMBO;
2791         }
2792
2793         /* Is there a change in mtu setting? */
2794         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2795                 return rc;
2796
2797         for (i = 0; i < bp->nr_vnics; i++) {
2798                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2799                 uint16_t size = 0;
2800
2801                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2802                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2803                 if (rc)
2804                         break;
2805
2806                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2807                 size -= RTE_PKTMBUF_HEADROOM;
2808
2809                 if (size < new_mtu) {
2810                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2811                         if (rc)
2812                                 return rc;
2813                 }
2814         }
2815
2816         if (!rc)
2817                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2818
2819         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2820
2821         return rc;
2822 }
2823
2824 static int
2825 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2826 {
2827         struct bnxt *bp = dev->data->dev_private;
2828         uint16_t vlan = bp->vlan;
2829         int rc;
2830
2831         rc = is_bnxt_in_error(bp);
2832         if (rc)
2833                 return rc;
2834
2835         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2836                 PMD_DRV_LOG(ERR,
2837                         "PVID cannot be modified for this function\n");
2838                 return -ENOTSUP;
2839         }
2840         bp->vlan = on ? pvid : 0;
2841
2842         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2843         if (rc)
2844                 bp->vlan = vlan;
2845         return rc;
2846 }
2847
2848 static int
2849 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2850 {
2851         struct bnxt *bp = dev->data->dev_private;
2852         int rc;
2853
2854         rc = is_bnxt_in_error(bp);
2855         if (rc)
2856                 return rc;
2857
2858         return bnxt_hwrm_port_led_cfg(bp, true);
2859 }
2860
2861 static int
2862 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2863 {
2864         struct bnxt *bp = dev->data->dev_private;
2865         int rc;
2866
2867         rc = is_bnxt_in_error(bp);
2868         if (rc)
2869                 return rc;
2870
2871         return bnxt_hwrm_port_led_cfg(bp, false);
2872 }
2873
2874 static uint32_t
2875 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2876 {
2877         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2878         uint32_t desc = 0, raw_cons = 0, cons;
2879         struct bnxt_cp_ring_info *cpr;
2880         struct bnxt_rx_queue *rxq;
2881         struct rx_pkt_cmpl *rxcmp;
2882         int rc;
2883
2884         rc = is_bnxt_in_error(bp);
2885         if (rc)
2886                 return rc;
2887
2888         rxq = dev->data->rx_queues[rx_queue_id];
2889         cpr = rxq->cp_ring;
2890         raw_cons = cpr->cp_raw_cons;
2891
2892         while (1) {
2893                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2894                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2895                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2896
2897                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2898                         break;
2899                 } else {
2900                         raw_cons++;
2901                         desc++;
2902                 }
2903         }
2904
2905         return desc;
2906 }
2907
2908 static int
2909 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2910 {
2911         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2912         struct bnxt_rx_ring_info *rxr;
2913         struct bnxt_cp_ring_info *cpr;
2914         struct rte_mbuf *rx_buf;
2915         struct rx_pkt_cmpl *rxcmp;
2916         uint32_t cons, cp_cons;
2917         int rc;
2918
2919         if (!rxq)
2920                 return -EINVAL;
2921
2922         rc = is_bnxt_in_error(rxq->bp);
2923         if (rc)
2924                 return rc;
2925
2926         cpr = rxq->cp_ring;
2927         rxr = rxq->rx_ring;
2928
2929         if (offset >= rxq->nb_rx_desc)
2930                 return -EINVAL;
2931
2932         cons = RING_CMP(cpr->cp_ring_struct, offset);
2933         cp_cons = cpr->cp_raw_cons;
2934         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2935
2936         if (cons > cp_cons) {
2937                 if (CMPL_VALID(rxcmp, cpr->valid))
2938                         return RTE_ETH_RX_DESC_DONE;
2939         } else {
2940                 if (CMPL_VALID(rxcmp, !cpr->valid))
2941                         return RTE_ETH_RX_DESC_DONE;
2942         }
2943         rx_buf = rxr->rx_buf_ring[cons];
2944         if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf)
2945                 return RTE_ETH_RX_DESC_UNAVAIL;
2946
2947
2948         return RTE_ETH_RX_DESC_AVAIL;
2949 }
2950
2951 static int
2952 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2953 {
2954         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2955         struct bnxt_tx_ring_info *txr;
2956         struct bnxt_cp_ring_info *cpr;
2957         struct bnxt_sw_tx_bd *tx_buf;
2958         struct tx_pkt_cmpl *txcmp;
2959         uint32_t cons, cp_cons;
2960         int rc;
2961
2962         if (!txq)
2963                 return -EINVAL;
2964
2965         rc = is_bnxt_in_error(txq->bp);
2966         if (rc)
2967                 return rc;
2968
2969         cpr = txq->cp_ring;
2970         txr = txq->tx_ring;
2971
2972         if (offset >= txq->nb_tx_desc)
2973                 return -EINVAL;
2974
2975         cons = RING_CMP(cpr->cp_ring_struct, offset);
2976         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2977         cp_cons = cpr->cp_raw_cons;
2978
2979         if (cons > cp_cons) {
2980                 if (CMPL_VALID(txcmp, cpr->valid))
2981                         return RTE_ETH_TX_DESC_UNAVAIL;
2982         } else {
2983                 if (CMPL_VALID(txcmp, !cpr->valid))
2984                         return RTE_ETH_TX_DESC_UNAVAIL;
2985         }
2986         tx_buf = &txr->tx_buf_ring[cons];
2987         if (tx_buf->mbuf == NULL)
2988                 return RTE_ETH_TX_DESC_DONE;
2989
2990         return RTE_ETH_TX_DESC_FULL;
2991 }
2992
2993 static struct bnxt_filter_info *
2994 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2995                                 struct rte_eth_ethertype_filter *efilter,
2996                                 struct bnxt_vnic_info *vnic0,
2997                                 struct bnxt_vnic_info *vnic,
2998                                 int *ret)
2999 {
3000         struct bnxt_filter_info *mfilter = NULL;
3001         int match = 0;
3002         *ret = 0;
3003
3004         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
3005                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
3006                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
3007                         " ethertype filter.", efilter->ether_type);
3008                 *ret = -EINVAL;
3009                 goto exit;
3010         }
3011         if (efilter->queue >= bp->rx_nr_rings) {
3012                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
3013                 *ret = -EINVAL;
3014                 goto exit;
3015         }
3016
3017         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3018         vnic = &bp->vnic_info[efilter->queue];
3019         if (vnic == NULL) {
3020                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
3021                 *ret = -EINVAL;
3022                 goto exit;
3023         }
3024
3025         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3026                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
3027                         if ((!memcmp(efilter->mac_addr.addr_bytes,
3028                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
3029                              mfilter->flags ==
3030                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
3031                              mfilter->ethertype == efilter->ether_type)) {
3032                                 match = 1;
3033                                 break;
3034                         }
3035                 }
3036         } else {
3037                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
3038                         if ((!memcmp(efilter->mac_addr.addr_bytes,
3039                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
3040                              mfilter->ethertype == efilter->ether_type &&
3041                              mfilter->flags ==
3042                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
3043                                 match = 1;
3044                                 break;
3045                         }
3046         }
3047
3048         if (match)
3049                 *ret = -EEXIST;
3050
3051 exit:
3052         return mfilter;
3053 }
3054
3055 static int
3056 bnxt_ethertype_filter(struct rte_eth_dev *dev,
3057                         enum rte_filter_op filter_op,
3058                         void *arg)
3059 {
3060         struct bnxt *bp = dev->data->dev_private;
3061         struct rte_eth_ethertype_filter *efilter =
3062                         (struct rte_eth_ethertype_filter *)arg;
3063         struct bnxt_filter_info *bfilter, *filter1;
3064         struct bnxt_vnic_info *vnic, *vnic0;
3065         int ret;
3066
3067         if (filter_op == RTE_ETH_FILTER_NOP)
3068                 return 0;
3069
3070         if (arg == NULL) {
3071                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3072                             filter_op);
3073                 return -EINVAL;
3074         }
3075
3076         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3077         vnic = &bp->vnic_info[efilter->queue];
3078
3079         switch (filter_op) {
3080         case RTE_ETH_FILTER_ADD:
3081                 bnxt_match_and_validate_ether_filter(bp, efilter,
3082                                                         vnic0, vnic, &ret);
3083                 if (ret < 0)
3084                         return ret;
3085
3086                 bfilter = bnxt_get_unused_filter(bp);
3087                 if (bfilter == NULL) {
3088                         PMD_DRV_LOG(ERR,
3089                                 "Not enough resources for a new filter.\n");
3090                         return -ENOMEM;
3091                 }
3092                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3093                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
3094                        RTE_ETHER_ADDR_LEN);
3095                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
3096                        RTE_ETHER_ADDR_LEN);
3097                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3098                 bfilter->ethertype = efilter->ether_type;
3099                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3100
3101                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
3102                 if (filter1 == NULL) {
3103                         ret = -EINVAL;
3104                         goto cleanup;
3105                 }
3106                 bfilter->enables |=
3107                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3108                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3109
3110                 bfilter->dst_id = vnic->fw_vnic_id;
3111
3112                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3113                         bfilter->flags =
3114                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3115                 }
3116
3117                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3118                 if (ret)
3119                         goto cleanup;
3120                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3121                 break;
3122         case RTE_ETH_FILTER_DELETE:
3123                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
3124                                                         vnic0, vnic, &ret);
3125                 if (ret == -EEXIST) {
3126                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
3127
3128                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
3129                                       next);
3130                         bnxt_free_filter(bp, filter1);
3131                 } else if (ret == 0) {
3132                         PMD_DRV_LOG(ERR, "No matching filter found\n");
3133                 }
3134                 break;
3135         default:
3136                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3137                 ret = -EINVAL;
3138                 goto error;
3139         }
3140         return ret;
3141 cleanup:
3142         bnxt_free_filter(bp, bfilter);
3143 error:
3144         return ret;
3145 }
3146
3147 static inline int
3148 parse_ntuple_filter(struct bnxt *bp,
3149                     struct rte_eth_ntuple_filter *nfilter,
3150                     struct bnxt_filter_info *bfilter)
3151 {
3152         uint32_t en = 0;
3153
3154         if (nfilter->queue >= bp->rx_nr_rings) {
3155                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
3156                 return -EINVAL;
3157         }
3158
3159         switch (nfilter->dst_port_mask) {
3160         case UINT16_MAX:
3161                 bfilter->dst_port_mask = -1;
3162                 bfilter->dst_port = nfilter->dst_port;
3163                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
3164                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3165                 break;
3166         default:
3167                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3168                 return -EINVAL;
3169         }
3170
3171         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3172         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3173
3174         switch (nfilter->proto_mask) {
3175         case UINT8_MAX:
3176                 if (nfilter->proto == 17) /* IPPROTO_UDP */
3177                         bfilter->ip_protocol = 17;
3178                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
3179                         bfilter->ip_protocol = 6;
3180                 else
3181                         return -EINVAL;
3182                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3183                 break;
3184         default:
3185                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3186                 return -EINVAL;
3187         }
3188
3189         switch (nfilter->dst_ip_mask) {
3190         case UINT32_MAX:
3191                 bfilter->dst_ipaddr_mask[0] = -1;
3192                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
3193                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
3194                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3195                 break;
3196         default:
3197                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3198                 return -EINVAL;
3199         }
3200
3201         switch (nfilter->src_ip_mask) {
3202         case UINT32_MAX:
3203                 bfilter->src_ipaddr_mask[0] = -1;
3204                 bfilter->src_ipaddr[0] = nfilter->src_ip;
3205                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
3206                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3207                 break;
3208         default:
3209                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3210                 return -EINVAL;
3211         }
3212
3213         switch (nfilter->src_port_mask) {
3214         case UINT16_MAX:
3215                 bfilter->src_port_mask = -1;
3216                 bfilter->src_port = nfilter->src_port;
3217                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
3218                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3219                 break;
3220         default:
3221                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3222                 return -EINVAL;
3223         }
3224
3225         bfilter->enables = en;
3226         return 0;
3227 }
3228
3229 static struct bnxt_filter_info*
3230 bnxt_match_ntuple_filter(struct bnxt *bp,
3231                          struct bnxt_filter_info *bfilter,
3232                          struct bnxt_vnic_info **mvnic)
3233 {
3234         struct bnxt_filter_info *mfilter = NULL;
3235         int i;
3236
3237         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3238                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3239                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
3240                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
3241                             bfilter->src_ipaddr_mask[0] ==
3242                             mfilter->src_ipaddr_mask[0] &&
3243                             bfilter->src_port == mfilter->src_port &&
3244                             bfilter->src_port_mask == mfilter->src_port_mask &&
3245                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
3246                             bfilter->dst_ipaddr_mask[0] ==
3247                             mfilter->dst_ipaddr_mask[0] &&
3248                             bfilter->dst_port == mfilter->dst_port &&
3249                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
3250                             bfilter->flags == mfilter->flags &&
3251                             bfilter->enables == mfilter->enables) {
3252                                 if (mvnic)
3253                                         *mvnic = vnic;
3254                                 return mfilter;
3255                         }
3256                 }
3257         }
3258         return NULL;
3259 }
3260
3261 static int
3262 bnxt_cfg_ntuple_filter(struct bnxt *bp,
3263                        struct rte_eth_ntuple_filter *nfilter,
3264                        enum rte_filter_op filter_op)
3265 {
3266         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
3267         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
3268         int ret;
3269
3270         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
3271                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3272                 return -EINVAL;
3273         }
3274
3275         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
3276                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
3277                 return -EINVAL;
3278         }
3279
3280         bfilter = bnxt_get_unused_filter(bp);
3281         if (bfilter == NULL) {
3282                 PMD_DRV_LOG(ERR,
3283                         "Not enough resources for a new filter.\n");
3284                 return -ENOMEM;
3285         }
3286         ret = parse_ntuple_filter(bp, nfilter, bfilter);
3287         if (ret < 0)
3288                 goto free_filter;
3289
3290         vnic = &bp->vnic_info[nfilter->queue];
3291         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3292         filter1 = STAILQ_FIRST(&vnic0->filter);
3293         if (filter1 == NULL) {
3294                 ret = -EINVAL;
3295                 goto free_filter;
3296         }
3297
3298         bfilter->dst_id = vnic->fw_vnic_id;
3299         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3300         bfilter->enables |=
3301                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3302         bfilter->ethertype = 0x800;
3303         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3304
3305         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3306
3307         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3308             bfilter->dst_id == mfilter->dst_id) {
3309                 PMD_DRV_LOG(ERR, "filter exists.\n");
3310                 ret = -EEXIST;
3311                 goto free_filter;
3312         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3313                    bfilter->dst_id != mfilter->dst_id) {
3314                 mfilter->dst_id = vnic->fw_vnic_id;
3315                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3316                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3317                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3318                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3319                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3320                 goto free_filter;
3321         }
3322         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3323                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3324                 ret = -ENOENT;
3325                 goto free_filter;
3326         }
3327
3328         if (filter_op == RTE_ETH_FILTER_ADD) {
3329                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3330                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3331                 if (ret)
3332                         goto free_filter;
3333                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3334         } else {
3335                 if (mfilter == NULL) {
3336                         /* This should not happen. But for Coverity! */
3337                         ret = -ENOENT;
3338                         goto free_filter;
3339                 }
3340                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3341
3342                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3343                 bnxt_free_filter(bp, mfilter);
3344                 bnxt_free_filter(bp, bfilter);
3345         }
3346
3347         return 0;
3348 free_filter:
3349         bnxt_free_filter(bp, bfilter);
3350         return ret;
3351 }
3352
3353 static int
3354 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3355                         enum rte_filter_op filter_op,
3356                         void *arg)
3357 {
3358         struct bnxt *bp = dev->data->dev_private;
3359         int ret;
3360
3361         if (filter_op == RTE_ETH_FILTER_NOP)
3362                 return 0;
3363
3364         if (arg == NULL) {
3365                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3366                             filter_op);
3367                 return -EINVAL;
3368         }
3369
3370         switch (filter_op) {
3371         case RTE_ETH_FILTER_ADD:
3372                 ret = bnxt_cfg_ntuple_filter(bp,
3373                         (struct rte_eth_ntuple_filter *)arg,
3374                         filter_op);
3375                 break;
3376         case RTE_ETH_FILTER_DELETE:
3377                 ret = bnxt_cfg_ntuple_filter(bp,
3378                         (struct rte_eth_ntuple_filter *)arg,
3379                         filter_op);
3380                 break;
3381         default:
3382                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3383                 ret = -EINVAL;
3384                 break;
3385         }
3386         return ret;
3387 }
3388
3389 static int
3390 bnxt_parse_fdir_filter(struct bnxt *bp,
3391                        struct rte_eth_fdir_filter *fdir,
3392                        struct bnxt_filter_info *filter)
3393 {
3394         enum rte_fdir_mode fdir_mode =
3395                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3396         struct bnxt_vnic_info *vnic0, *vnic;
3397         struct bnxt_filter_info *filter1;
3398         uint32_t en = 0;
3399         int i;
3400
3401         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3402                 return -EINVAL;
3403
3404         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3405         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3406
3407         switch (fdir->input.flow_type) {
3408         case RTE_ETH_FLOW_IPV4:
3409         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3410                 /* FALLTHROUGH */
3411                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3412                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3413                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3414                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3415                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3416                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3417                 filter->ip_addr_type =
3418                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3419                 filter->src_ipaddr_mask[0] = 0xffffffff;
3420                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3421                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3422                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3423                 filter->ethertype = 0x800;
3424                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3425                 break;
3426         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3427                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3428                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3429                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3430                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3431                 filter->dst_port_mask = 0xffff;
3432                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3433                 filter->src_port_mask = 0xffff;
3434                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3435                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3436                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3437                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3438                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3439                 filter->ip_protocol = 6;
3440                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3441                 filter->ip_addr_type =
3442                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3443                 filter->src_ipaddr_mask[0] = 0xffffffff;
3444                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3445                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3446                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3447                 filter->ethertype = 0x800;
3448                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3449                 break;
3450         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3451                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3452                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3453                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3454                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3455                 filter->dst_port_mask = 0xffff;
3456                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3457                 filter->src_port_mask = 0xffff;
3458                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3459                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3460                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3461                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3462                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3463                 filter->ip_protocol = 17;
3464                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3465                 filter->ip_addr_type =
3466                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3467                 filter->src_ipaddr_mask[0] = 0xffffffff;
3468                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3469                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3470                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3471                 filter->ethertype = 0x800;
3472                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3473                 break;
3474         case RTE_ETH_FLOW_IPV6:
3475         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3476                 /* FALLTHROUGH */
3477                 filter->ip_addr_type =
3478                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3479                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3480                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3481                 rte_memcpy(filter->src_ipaddr,
3482                            fdir->input.flow.ipv6_flow.src_ip, 16);
3483                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3484                 rte_memcpy(filter->dst_ipaddr,
3485                            fdir->input.flow.ipv6_flow.dst_ip, 16);
3486                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3487                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3488                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3489                 memset(filter->src_ipaddr_mask, 0xff, 16);
3490                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3491                 filter->ethertype = 0x86dd;
3492                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3493                 break;
3494         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3495                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3496                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3497                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3498                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3499                 filter->dst_port_mask = 0xffff;
3500                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3501                 filter->src_port_mask = 0xffff;
3502                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3503                 filter->ip_addr_type =
3504                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3505                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3506                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3507                 rte_memcpy(filter->src_ipaddr,
3508                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3509                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3510                 rte_memcpy(filter->dst_ipaddr,
3511                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3512                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3513                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3514                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3515                 memset(filter->src_ipaddr_mask, 0xff, 16);
3516                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3517                 filter->ethertype = 0x86dd;
3518                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3519                 break;
3520         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3521                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3522                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3523                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3524                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3525                 filter->dst_port_mask = 0xffff;
3526                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3527                 filter->src_port_mask = 0xffff;
3528                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3529                 filter->ip_addr_type =
3530                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3531                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3532                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3533                 rte_memcpy(filter->src_ipaddr,
3534                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3535                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3536                 rte_memcpy(filter->dst_ipaddr,
3537                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3538                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3539                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3540                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3541                 memset(filter->src_ipaddr_mask, 0xff, 16);
3542                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3543                 filter->ethertype = 0x86dd;
3544                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3545                 break;
3546         case RTE_ETH_FLOW_L2_PAYLOAD:
3547                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3548                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3549                 break;
3550         case RTE_ETH_FLOW_VXLAN:
3551                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3552                         return -EINVAL;
3553                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3554                 filter->tunnel_type =
3555                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3556                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3557                 break;
3558         case RTE_ETH_FLOW_NVGRE:
3559                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3560                         return -EINVAL;
3561                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3562                 filter->tunnel_type =
3563                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3564                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3565                 break;
3566         case RTE_ETH_FLOW_UNKNOWN:
3567         case RTE_ETH_FLOW_RAW:
3568         case RTE_ETH_FLOW_FRAG_IPV4:
3569         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3570         case RTE_ETH_FLOW_FRAG_IPV6:
3571         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3572         case RTE_ETH_FLOW_IPV6_EX:
3573         case RTE_ETH_FLOW_IPV6_TCP_EX:
3574         case RTE_ETH_FLOW_IPV6_UDP_EX:
3575         case RTE_ETH_FLOW_GENEVE:
3576                 /* FALLTHROUGH */
3577         default:
3578                 return -EINVAL;
3579         }
3580
3581         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3582         vnic = &bp->vnic_info[fdir->action.rx_queue];
3583         if (vnic == NULL) {
3584                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3585                 return -EINVAL;
3586         }
3587
3588         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3589                 rte_memcpy(filter->dst_macaddr,
3590                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3591                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3592         }
3593
3594         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3595                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3596                 filter1 = STAILQ_FIRST(&vnic0->filter);
3597                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3598         } else {
3599                 filter->dst_id = vnic->fw_vnic_id;
3600                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3601                         if (filter->dst_macaddr[i] == 0x00)
3602                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3603                         else
3604                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3605         }
3606
3607         if (filter1 == NULL)
3608                 return -EINVAL;
3609
3610         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3611         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3612
3613         filter->enables = en;
3614
3615         return 0;
3616 }
3617
3618 static struct bnxt_filter_info *
3619 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3620                 struct bnxt_vnic_info **mvnic)
3621 {
3622         struct bnxt_filter_info *mf = NULL;
3623         int i;
3624
3625         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3626                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3627
3628                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3629                         if (mf->filter_type == nf->filter_type &&
3630                             mf->flags == nf->flags &&
3631                             mf->src_port == nf->src_port &&
3632                             mf->src_port_mask == nf->src_port_mask &&
3633                             mf->dst_port == nf->dst_port &&
3634                             mf->dst_port_mask == nf->dst_port_mask &&
3635                             mf->ip_protocol == nf->ip_protocol &&
3636                             mf->ip_addr_type == nf->ip_addr_type &&
3637                             mf->ethertype == nf->ethertype &&
3638                             mf->vni == nf->vni &&
3639                             mf->tunnel_type == nf->tunnel_type &&
3640                             mf->l2_ovlan == nf->l2_ovlan &&
3641                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3642                             mf->l2_ivlan == nf->l2_ivlan &&
3643                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3644                             !memcmp(mf->l2_addr, nf->l2_addr,
3645                                     RTE_ETHER_ADDR_LEN) &&
3646                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3647                                     RTE_ETHER_ADDR_LEN) &&
3648                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3649                                     RTE_ETHER_ADDR_LEN) &&
3650                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3651                                     RTE_ETHER_ADDR_LEN) &&
3652                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3653                                     sizeof(nf->src_ipaddr)) &&
3654                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3655                                     sizeof(nf->src_ipaddr_mask)) &&
3656                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3657                                     sizeof(nf->dst_ipaddr)) &&
3658                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3659                                     sizeof(nf->dst_ipaddr_mask))) {
3660                                 if (mvnic)
3661                                         *mvnic = vnic;
3662                                 return mf;
3663                         }
3664                 }
3665         }
3666         return NULL;
3667 }
3668
3669 static int
3670 bnxt_fdir_filter(struct rte_eth_dev *dev,
3671                  enum rte_filter_op filter_op,
3672                  void *arg)
3673 {
3674         struct bnxt *bp = dev->data->dev_private;
3675         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3676         struct bnxt_filter_info *filter, *match;
3677         struct bnxt_vnic_info *vnic, *mvnic;
3678         int ret = 0, i;
3679
3680         if (filter_op == RTE_ETH_FILTER_NOP)
3681                 return 0;
3682
3683         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3684                 return -EINVAL;
3685
3686         switch (filter_op) {
3687         case RTE_ETH_FILTER_ADD:
3688         case RTE_ETH_FILTER_DELETE:
3689                 /* FALLTHROUGH */
3690                 filter = bnxt_get_unused_filter(bp);
3691                 if (filter == NULL) {
3692                         PMD_DRV_LOG(ERR,
3693                                 "Not enough resources for a new flow.\n");
3694                         return -ENOMEM;
3695                 }
3696
3697                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3698                 if (ret != 0)
3699                         goto free_filter;
3700                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3701
3702                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3703                         vnic = &bp->vnic_info[0];
3704                 else
3705                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3706
3707                 match = bnxt_match_fdir(bp, filter, &mvnic);
3708                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3709                         if (match->dst_id == vnic->fw_vnic_id) {
3710                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3711                                 ret = -EEXIST;
3712                                 goto free_filter;
3713                         } else {
3714                                 match->dst_id = vnic->fw_vnic_id;
3715                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3716                                                                   match->dst_id,
3717                                                                   match);
3718                                 STAILQ_REMOVE(&mvnic->filter, match,
3719                                               bnxt_filter_info, next);
3720                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3721                                 PMD_DRV_LOG(ERR,
3722                                         "Filter with matching pattern exist\n");
3723                                 PMD_DRV_LOG(ERR,
3724                                         "Updated it to new destination q\n");
3725                                 goto free_filter;
3726                         }
3727                 }
3728                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3729                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3730                         ret = -ENOENT;
3731                         goto free_filter;
3732                 }
3733
3734                 if (filter_op == RTE_ETH_FILTER_ADD) {
3735                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3736                                                           filter->dst_id,
3737                                                           filter);
3738                         if (ret)
3739                                 goto free_filter;
3740                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3741                 } else {
3742                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3743                         STAILQ_REMOVE(&vnic->filter, match,
3744                                       bnxt_filter_info, next);
3745                         bnxt_free_filter(bp, match);
3746                         bnxt_free_filter(bp, filter);
3747                 }
3748                 break;
3749         case RTE_ETH_FILTER_FLUSH:
3750                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3751                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3752
3753                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3754                                 if (filter->filter_type ==
3755                                     HWRM_CFA_NTUPLE_FILTER) {
3756                                         ret =
3757                                         bnxt_hwrm_clear_ntuple_filter(bp,
3758                                                                       filter);
3759                                         STAILQ_REMOVE(&vnic->filter, filter,
3760                                                       bnxt_filter_info, next);
3761                                 }
3762                         }
3763                 }
3764                 return ret;
3765         case RTE_ETH_FILTER_UPDATE:
3766         case RTE_ETH_FILTER_STATS:
3767         case RTE_ETH_FILTER_INFO:
3768                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3769                 break;
3770         default:
3771                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3772                 ret = -EINVAL;
3773                 break;
3774         }
3775         return ret;
3776
3777 free_filter:
3778         bnxt_free_filter(bp, filter);
3779         return ret;
3780 }
3781
3782 int
3783 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3784                     enum rte_filter_type filter_type,
3785                     enum rte_filter_op filter_op, void *arg)
3786 {
3787         struct bnxt *bp = dev->data->dev_private;
3788         int ret = 0;
3789
3790         if (!bp)
3791                 return -EIO;
3792
3793         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3794                 struct bnxt_representor *vfr = dev->data->dev_private;
3795                 bp = vfr->parent_dev->data->dev_private;
3796                 /* parent is deleted while children are still valid */
3797                 if (!bp) {
3798                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n",
3799                                     dev->data->port_id,
3800                                     filter_type,
3801                                     filter_op);
3802                         return -EIO;
3803                 }
3804         }
3805
3806         ret = is_bnxt_in_error(bp);
3807         if (ret)
3808                 return ret;
3809
3810         switch (filter_type) {
3811         case RTE_ETH_FILTER_TUNNEL:
3812                 PMD_DRV_LOG(ERR,
3813                         "filter type: %d: To be implemented\n", filter_type);
3814                 break;
3815         case RTE_ETH_FILTER_FDIR:
3816                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3817                 break;
3818         case RTE_ETH_FILTER_NTUPLE:
3819                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3820                 break;
3821         case RTE_ETH_FILTER_ETHERTYPE:
3822                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3823                 break;
3824         case RTE_ETH_FILTER_GENERIC:
3825                 if (filter_op != RTE_ETH_FILTER_GET)
3826                         return -EINVAL;
3827                 if (BNXT_TRUFLOW_EN(bp))
3828                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3829                 else
3830                         *(const void **)arg = &bnxt_flow_ops;
3831                 break;
3832         default:
3833                 PMD_DRV_LOG(ERR,
3834                         "Filter type (%d) not supported", filter_type);
3835                 ret = -EINVAL;
3836                 break;
3837         }
3838         return ret;
3839 }
3840
3841 static const uint32_t *
3842 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3843 {
3844         static const uint32_t ptypes[] = {
3845                 RTE_PTYPE_L2_ETHER_VLAN,
3846                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3847                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3848                 RTE_PTYPE_L4_ICMP,
3849                 RTE_PTYPE_L4_TCP,
3850                 RTE_PTYPE_L4_UDP,
3851                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3852                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3853                 RTE_PTYPE_INNER_L4_ICMP,
3854                 RTE_PTYPE_INNER_L4_TCP,
3855                 RTE_PTYPE_INNER_L4_UDP,
3856                 RTE_PTYPE_UNKNOWN
3857         };
3858
3859         if (!dev->rx_pkt_burst)
3860                 return NULL;
3861
3862         return ptypes;
3863 }
3864
3865 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3866                          int reg_win)
3867 {
3868         uint32_t reg_base = *reg_arr & 0xfffff000;
3869         uint32_t win_off;
3870         int i;
3871
3872         for (i = 0; i < count; i++) {
3873                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3874                         return -ERANGE;
3875         }
3876         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3877         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3878         return 0;
3879 }
3880
3881 static int bnxt_map_ptp_regs(struct bnxt *bp)
3882 {
3883         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3884         uint32_t *reg_arr;
3885         int rc, i;
3886
3887         reg_arr = ptp->rx_regs;
3888         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3889         if (rc)
3890                 return rc;
3891
3892         reg_arr = ptp->tx_regs;
3893         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3894         if (rc)
3895                 return rc;
3896
3897         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3898                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3899
3900         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3901                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3902
3903         return 0;
3904 }
3905
3906 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3907 {
3908         rte_write32(0, (uint8_t *)bp->bar0 +
3909                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3910         rte_write32(0, (uint8_t *)bp->bar0 +
3911                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3912 }
3913
3914 static uint64_t bnxt_cc_read(struct bnxt *bp)
3915 {
3916         uint64_t ns;
3917
3918         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3919                               BNXT_GRCPF_REG_SYNC_TIME));
3920         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3921                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3922         return ns;
3923 }
3924
3925 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3926 {
3927         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3928         uint32_t fifo;
3929
3930         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3931                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3932         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3933                 return -EAGAIN;
3934
3935         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3936                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3937         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3938                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3939         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3940                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3941
3942         return 0;
3943 }
3944
3945 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3946 {
3947         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3948         struct bnxt_pf_info *pf = bp->pf;
3949         uint16_t port_id;
3950         uint32_t fifo;
3951
3952         if (!ptp)
3953                 return -ENODEV;
3954
3955         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3956                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3957         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3958                 return -EAGAIN;
3959
3960         port_id = pf->port_id;
3961         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3962                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3963
3964         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3965                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3966         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3967 /*              bnxt_clr_rx_ts(bp);       TBD  */
3968                 return -EBUSY;
3969         }
3970
3971         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3972                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3973         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3974                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3975
3976         return 0;
3977 }
3978
3979 static int
3980 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3981 {
3982         uint64_t ns;
3983         struct bnxt *bp = dev->data->dev_private;
3984         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3985
3986         if (!ptp)
3987                 return 0;
3988
3989         ns = rte_timespec_to_ns(ts);
3990         /* Set the timecounters to a new value. */
3991         ptp->tc.nsec = ns;
3992
3993         return 0;
3994 }
3995
3996 static int
3997 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3998 {
3999         struct bnxt *bp = dev->data->dev_private;
4000         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4001         uint64_t ns, systime_cycles = 0;
4002         int rc = 0;
4003
4004         if (!ptp)
4005                 return 0;
4006
4007         if (BNXT_CHIP_THOR(bp))
4008                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
4009                                              &systime_cycles);
4010         else
4011                 systime_cycles = bnxt_cc_read(bp);
4012
4013         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
4014         *ts = rte_ns_to_timespec(ns);
4015
4016         return rc;
4017 }
4018 static int
4019 bnxt_timesync_enable(struct rte_eth_dev *dev)
4020 {
4021         struct bnxt *bp = dev->data->dev_private;
4022         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4023         uint32_t shift = 0;
4024         int rc;
4025
4026         if (!ptp)
4027                 return 0;
4028
4029         ptp->rx_filter = 1;
4030         ptp->tx_tstamp_en = 1;
4031         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
4032
4033         rc = bnxt_hwrm_ptp_cfg(bp);
4034         if (rc)
4035                 return rc;
4036
4037         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
4038         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4039         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4040
4041         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4042         ptp->tc.cc_shift = shift;
4043         ptp->tc.nsec_mask = (1ULL << shift) - 1;
4044
4045         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4046         ptp->rx_tstamp_tc.cc_shift = shift;
4047         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4048
4049         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4050         ptp->tx_tstamp_tc.cc_shift = shift;
4051         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4052
4053         if (!BNXT_CHIP_THOR(bp))
4054                 bnxt_map_ptp_regs(bp);
4055
4056         return 0;
4057 }
4058
4059 static int
4060 bnxt_timesync_disable(struct rte_eth_dev *dev)
4061 {
4062         struct bnxt *bp = dev->data->dev_private;
4063         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4064
4065         if (!ptp)
4066                 return 0;
4067
4068         ptp->rx_filter = 0;
4069         ptp->tx_tstamp_en = 0;
4070         ptp->rxctl = 0;
4071
4072         bnxt_hwrm_ptp_cfg(bp);
4073
4074         if (!BNXT_CHIP_THOR(bp))
4075                 bnxt_unmap_ptp_regs(bp);
4076
4077         return 0;
4078 }
4079
4080 static int
4081 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4082                                  struct timespec *timestamp,
4083                                  uint32_t flags __rte_unused)
4084 {
4085         struct bnxt *bp = dev->data->dev_private;
4086         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4087         uint64_t rx_tstamp_cycles = 0;
4088         uint64_t ns;
4089
4090         if (!ptp)
4091                 return 0;
4092
4093         if (BNXT_CHIP_THOR(bp))
4094                 rx_tstamp_cycles = ptp->rx_timestamp;
4095         else
4096                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
4097
4098         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
4099         *timestamp = rte_ns_to_timespec(ns);
4100         return  0;
4101 }
4102
4103 static int
4104 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4105                                  struct timespec *timestamp)
4106 {
4107         struct bnxt *bp = dev->data->dev_private;
4108         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4109         uint64_t tx_tstamp_cycles = 0;
4110         uint64_t ns;
4111         int rc = 0;
4112
4113         if (!ptp)
4114                 return 0;
4115
4116         if (BNXT_CHIP_THOR(bp))
4117                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
4118                                              &tx_tstamp_cycles);
4119         else
4120                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
4121
4122         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
4123         *timestamp = rte_ns_to_timespec(ns);
4124
4125         return rc;
4126 }
4127
4128 static int
4129 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4130 {
4131         struct bnxt *bp = dev->data->dev_private;
4132         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4133
4134         if (!ptp)
4135                 return 0;
4136
4137         ptp->tc.nsec += delta;
4138
4139         return 0;
4140 }
4141
4142 static int
4143 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
4144 {
4145         struct bnxt *bp = dev->data->dev_private;
4146         int rc;
4147         uint32_t dir_entries;
4148         uint32_t entry_length;
4149
4150         rc = is_bnxt_in_error(bp);
4151         if (rc)
4152                 return rc;
4153
4154         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
4155                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4156                     bp->pdev->addr.devid, bp->pdev->addr.function);
4157
4158         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4159         if (rc != 0)
4160                 return rc;
4161
4162         return dir_entries * entry_length;
4163 }
4164
4165 static int
4166 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
4167                 struct rte_dev_eeprom_info *in_eeprom)
4168 {
4169         struct bnxt *bp = dev->data->dev_private;
4170         uint32_t index;
4171         uint32_t offset;
4172         int rc;
4173
4174         rc = is_bnxt_in_error(bp);
4175         if (rc)
4176                 return rc;
4177
4178         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4179                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4180                     bp->pdev->addr.devid, bp->pdev->addr.function,
4181                     in_eeprom->offset, in_eeprom->length);
4182
4183         if (in_eeprom->offset == 0) /* special offset value to get directory */
4184                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
4185                                                 in_eeprom->data);
4186
4187         index = in_eeprom->offset >> 24;
4188         offset = in_eeprom->offset & 0xffffff;
4189
4190         if (index != 0)
4191                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
4192                                            in_eeprom->length, in_eeprom->data);
4193
4194         return 0;
4195 }
4196
4197 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
4198 {
4199         switch (dir_type) {
4200         case BNX_DIR_TYPE_CHIMP_PATCH:
4201         case BNX_DIR_TYPE_BOOTCODE:
4202         case BNX_DIR_TYPE_BOOTCODE_2:
4203         case BNX_DIR_TYPE_APE_FW:
4204         case BNX_DIR_TYPE_APE_PATCH:
4205         case BNX_DIR_TYPE_KONG_FW:
4206         case BNX_DIR_TYPE_KONG_PATCH:
4207         case BNX_DIR_TYPE_BONO_FW:
4208         case BNX_DIR_TYPE_BONO_PATCH:
4209                 /* FALLTHROUGH */
4210                 return true;
4211         }
4212
4213         return false;
4214 }
4215
4216 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
4217 {
4218         switch (dir_type) {
4219         case BNX_DIR_TYPE_AVS:
4220         case BNX_DIR_TYPE_EXP_ROM_MBA:
4221         case BNX_DIR_TYPE_PCIE:
4222         case BNX_DIR_TYPE_TSCF_UCODE:
4223         case BNX_DIR_TYPE_EXT_PHY:
4224         case BNX_DIR_TYPE_CCM:
4225         case BNX_DIR_TYPE_ISCSI_BOOT:
4226         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
4227         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
4228                 /* FALLTHROUGH */
4229                 return true;
4230         }
4231
4232         return false;
4233 }
4234
4235 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
4236 {
4237         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
4238                 bnxt_dir_type_is_other_exec_format(dir_type);
4239 }
4240
4241 static int
4242 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
4243                 struct rte_dev_eeprom_info *in_eeprom)
4244 {
4245         struct bnxt *bp = dev->data->dev_private;
4246         uint8_t index, dir_op;
4247         uint16_t type, ext, ordinal, attr;
4248         int rc;
4249
4250         rc = is_bnxt_in_error(bp);
4251         if (rc)
4252                 return rc;
4253
4254         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4255                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4256                     bp->pdev->addr.devid, bp->pdev->addr.function,
4257                     in_eeprom->offset, in_eeprom->length);
4258
4259         if (!BNXT_PF(bp)) {
4260                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
4261                 return -EINVAL;
4262         }
4263
4264         type = in_eeprom->magic >> 16;
4265
4266         if (type == 0xffff) { /* special value for directory operations */
4267                 index = in_eeprom->magic & 0xff;
4268                 dir_op = in_eeprom->magic >> 8;
4269                 if (index == 0)
4270                         return -EINVAL;
4271                 switch (dir_op) {
4272                 case 0x0e: /* erase */
4273                         if (in_eeprom->offset != ~in_eeprom->magic)
4274                                 return -EINVAL;
4275                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
4276                 default:
4277                         return -EINVAL;
4278                 }
4279         }
4280
4281         /* Create or re-write an NVM item: */
4282         if (bnxt_dir_type_is_executable(type) == true)
4283                 return -EOPNOTSUPP;
4284         ext = in_eeprom->magic & 0xffff;
4285         ordinal = in_eeprom->offset >> 16;
4286         attr = in_eeprom->offset & 0xffff;
4287
4288         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
4289                                      in_eeprom->data, in_eeprom->length);
4290 }
4291
4292 /*
4293  * Initialization
4294  */
4295
4296 static const struct eth_dev_ops bnxt_dev_ops = {
4297         .dev_infos_get = bnxt_dev_info_get_op,
4298         .dev_close = bnxt_dev_close_op,
4299         .dev_configure = bnxt_dev_configure_op,
4300         .dev_start = bnxt_dev_start_op,
4301         .dev_stop = bnxt_dev_stop_op,
4302         .dev_set_link_up = bnxt_dev_set_link_up_op,
4303         .dev_set_link_down = bnxt_dev_set_link_down_op,
4304         .stats_get = bnxt_stats_get_op,
4305         .stats_reset = bnxt_stats_reset_op,
4306         .rx_queue_setup = bnxt_rx_queue_setup_op,
4307         .rx_queue_release = bnxt_rx_queue_release_op,
4308         .tx_queue_setup = bnxt_tx_queue_setup_op,
4309         .tx_queue_release = bnxt_tx_queue_release_op,
4310         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4311         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4312         .reta_update = bnxt_reta_update_op,
4313         .reta_query = bnxt_reta_query_op,
4314         .rss_hash_update = bnxt_rss_hash_update_op,
4315         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4316         .link_update = bnxt_link_update_op,
4317         .promiscuous_enable = bnxt_promiscuous_enable_op,
4318         .promiscuous_disable = bnxt_promiscuous_disable_op,
4319         .allmulticast_enable = bnxt_allmulticast_enable_op,
4320         .allmulticast_disable = bnxt_allmulticast_disable_op,
4321         .mac_addr_add = bnxt_mac_addr_add_op,
4322         .mac_addr_remove = bnxt_mac_addr_remove_op,
4323         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4324         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4325         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4326         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4327         .vlan_filter_set = bnxt_vlan_filter_set_op,
4328         .vlan_offload_set = bnxt_vlan_offload_set_op,
4329         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4330         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4331         .mtu_set = bnxt_mtu_set_op,
4332         .mac_addr_set = bnxt_set_default_mac_addr_op,
4333         .xstats_get = bnxt_dev_xstats_get_op,
4334         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4335         .xstats_reset = bnxt_dev_xstats_reset_op,
4336         .fw_version_get = bnxt_fw_version_get,
4337         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4338         .rxq_info_get = bnxt_rxq_info_get_op,
4339         .txq_info_get = bnxt_txq_info_get_op,
4340         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4341         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4342         .dev_led_on = bnxt_dev_led_on_op,
4343         .dev_led_off = bnxt_dev_led_off_op,
4344         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4345         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4346         .rx_queue_start = bnxt_rx_queue_start,
4347         .rx_queue_stop = bnxt_rx_queue_stop,
4348         .tx_queue_start = bnxt_tx_queue_start,
4349         .tx_queue_stop = bnxt_tx_queue_stop,
4350         .filter_ctrl = bnxt_filter_ctrl_op,
4351         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4352         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4353         .get_eeprom           = bnxt_get_eeprom_op,
4354         .set_eeprom           = bnxt_set_eeprom_op,
4355         .timesync_enable      = bnxt_timesync_enable,
4356         .timesync_disable     = bnxt_timesync_disable,
4357         .timesync_read_time   = bnxt_timesync_read_time,
4358         .timesync_write_time   = bnxt_timesync_write_time,
4359         .timesync_adjust_time = bnxt_timesync_adjust_time,
4360         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4361         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4362 };
4363
4364 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4365 {
4366         uint32_t offset;
4367
4368         /* Only pre-map the reset GRC registers using window 3 */
4369         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4370                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4371
4372         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4373
4374         return offset;
4375 }
4376
4377 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4378 {
4379         struct bnxt_error_recovery_info *info = bp->recovery_info;
4380         uint32_t reg_base = 0xffffffff;
4381         int i;
4382
4383         /* Only pre-map the monitoring GRC registers using window 2 */
4384         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4385                 uint32_t reg = info->status_regs[i];
4386
4387                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4388                         continue;
4389
4390                 if (reg_base == 0xffffffff)
4391                         reg_base = reg & 0xfffff000;
4392                 if ((reg & 0xfffff000) != reg_base)
4393                         return -ERANGE;
4394
4395                 /* Use mask 0xffc as the Lower 2 bits indicates
4396                  * address space location
4397                  */
4398                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4399                                                 (reg & 0xffc);
4400         }
4401
4402         if (reg_base == 0xffffffff)
4403                 return 0;
4404
4405         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4406                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4407
4408         return 0;
4409 }
4410
4411 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4412 {
4413         struct bnxt_error_recovery_info *info = bp->recovery_info;
4414         uint32_t delay = info->delay_after_reset[index];
4415         uint32_t val = info->reset_reg_val[index];
4416         uint32_t reg = info->reset_reg[index];
4417         uint32_t type, offset;
4418
4419         type = BNXT_FW_STATUS_REG_TYPE(reg);
4420         offset = BNXT_FW_STATUS_REG_OFF(reg);
4421
4422         switch (type) {
4423         case BNXT_FW_STATUS_REG_TYPE_CFG:
4424                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4425                 break;
4426         case BNXT_FW_STATUS_REG_TYPE_GRC:
4427                 offset = bnxt_map_reset_regs(bp, offset);
4428                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4429                 break;
4430         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4431                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4432                 break;
4433         }
4434         /* wait on a specific interval of time until core reset is complete */
4435         if (delay)
4436                 rte_delay_ms(delay);
4437 }
4438
4439 static void bnxt_dev_cleanup(struct bnxt *bp)
4440 {
4441         bp->eth_dev->data->dev_link.link_status = 0;
4442         bp->link_info->link_up = 0;
4443         if (bp->eth_dev->data->dev_started)
4444                 bnxt_dev_stop_op(bp->eth_dev);
4445
4446         bnxt_uninit_resources(bp, true);
4447 }
4448
4449 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4450 {
4451         struct rte_eth_dev *dev = bp->eth_dev;
4452         struct rte_vlan_filter_conf *vfc;
4453         int vidx, vbit, rc;
4454         uint16_t vlan_id;
4455
4456         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4457                 vfc = &dev->data->vlan_filter_conf;
4458                 vidx = vlan_id / 64;
4459                 vbit = vlan_id % 64;
4460
4461                 /* Each bit corresponds to a VLAN id */
4462                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4463                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4464                         if (rc)
4465                                 return rc;
4466                 }
4467         }
4468
4469         return 0;
4470 }
4471
4472 static int bnxt_restore_mac_filters(struct bnxt *bp)
4473 {
4474         struct rte_eth_dev *dev = bp->eth_dev;
4475         struct rte_eth_dev_info dev_info;
4476         struct rte_ether_addr *addr;
4477         uint64_t pool_mask;
4478         uint32_t pool = 0;
4479         uint16_t i;
4480         int rc;
4481
4482         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4483                 return 0;
4484
4485         rc = bnxt_dev_info_get_op(dev, &dev_info);
4486         if (rc)
4487                 return rc;
4488
4489         /* replay MAC address configuration */
4490         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4491                 addr = &dev->data->mac_addrs[i];
4492
4493                 /* skip zero address */
4494                 if (rte_is_zero_ether_addr(addr))
4495                         continue;
4496
4497                 pool = 0;
4498                 pool_mask = dev->data->mac_pool_sel[i];
4499
4500                 do {
4501                         if (pool_mask & 1ULL) {
4502                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4503                                 if (rc)
4504                                         return rc;
4505                         }
4506                         pool_mask >>= 1;
4507                         pool++;
4508                 } while (pool_mask);
4509         }
4510
4511         return 0;
4512 }
4513
4514 static int bnxt_restore_filters(struct bnxt *bp)
4515 {
4516         struct rte_eth_dev *dev = bp->eth_dev;
4517         int ret = 0;
4518
4519         if (dev->data->all_multicast) {
4520                 ret = bnxt_allmulticast_enable_op(dev);
4521                 if (ret)
4522                         return ret;
4523         }
4524         if (dev->data->promiscuous) {
4525                 ret = bnxt_promiscuous_enable_op(dev);
4526                 if (ret)
4527                         return ret;
4528         }
4529
4530         ret = bnxt_restore_mac_filters(bp);
4531         if (ret)
4532                 return ret;
4533
4534         ret = bnxt_restore_vlan_filters(bp);
4535         /* TODO restore other filters as well */
4536         return ret;
4537 }
4538
4539 static void bnxt_dev_recover(void *arg)
4540 {
4541         struct bnxt *bp = arg;
4542         int timeout = bp->fw_reset_max_msecs;
4543         int rc = 0;
4544
4545         /* Clear Error flag so that device re-init should happen */
4546         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4547
4548         do {
4549                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4550                 if (rc == 0)
4551                         break;
4552                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4553                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4554         } while (rc && timeout);
4555
4556         if (rc) {
4557                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4558                 goto err;
4559         }
4560
4561         rc = bnxt_init_resources(bp, true);
4562         if (rc) {
4563                 PMD_DRV_LOG(ERR,
4564                             "Failed to initialize resources after reset\n");
4565                 goto err;
4566         }
4567         /* clear reset flag as the device is initialized now */
4568         bp->flags &= ~BNXT_FLAG_FW_RESET;
4569
4570         rc = bnxt_dev_start_op(bp->eth_dev);
4571         if (rc) {
4572                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4573                 goto err_start;
4574         }
4575
4576         rc = bnxt_restore_filters(bp);
4577         if (rc)
4578                 goto err_start;
4579
4580         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4581         return;
4582 err_start:
4583         bnxt_dev_stop_op(bp->eth_dev);
4584 err:
4585         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4586         bnxt_uninit_resources(bp, false);
4587         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4588 }
4589
4590 void bnxt_dev_reset_and_resume(void *arg)
4591 {
4592         struct bnxt *bp = arg;
4593         int rc;
4594
4595         bnxt_dev_cleanup(bp);
4596
4597         bnxt_wait_for_device_shutdown(bp);
4598
4599         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4600                                bnxt_dev_recover, (void *)bp);
4601         if (rc)
4602                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4603 }
4604
4605 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4606 {
4607         struct bnxt_error_recovery_info *info = bp->recovery_info;
4608         uint32_t reg = info->status_regs[index];
4609         uint32_t type, offset, val = 0;
4610
4611         type = BNXT_FW_STATUS_REG_TYPE(reg);
4612         offset = BNXT_FW_STATUS_REG_OFF(reg);
4613
4614         switch (type) {
4615         case BNXT_FW_STATUS_REG_TYPE_CFG:
4616                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4617                 break;
4618         case BNXT_FW_STATUS_REG_TYPE_GRC:
4619                 offset = info->mapped_status_regs[index];
4620                 /* FALLTHROUGH */
4621         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4622                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4623                                        offset));
4624                 break;
4625         }
4626
4627         return val;
4628 }
4629
4630 static int bnxt_fw_reset_all(struct bnxt *bp)
4631 {
4632         struct bnxt_error_recovery_info *info = bp->recovery_info;
4633         uint32_t i;
4634         int rc = 0;
4635
4636         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4637                 /* Reset through master function driver */
4638                 for (i = 0; i < info->reg_array_cnt; i++)
4639                         bnxt_write_fw_reset_reg(bp, i);
4640                 /* Wait for time specified by FW after triggering reset */
4641                 rte_delay_ms(info->master_func_wait_period_after_reset);
4642         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4643                 /* Reset with the help of Kong processor */
4644                 rc = bnxt_hwrm_fw_reset(bp);
4645                 if (rc)
4646                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4647         }
4648
4649         return rc;
4650 }
4651
4652 static void bnxt_fw_reset_cb(void *arg)
4653 {
4654         struct bnxt *bp = arg;
4655         struct bnxt_error_recovery_info *info = bp->recovery_info;
4656         int rc = 0;
4657
4658         /* Only Master function can do FW reset */
4659         if (bnxt_is_master_func(bp) &&
4660             bnxt_is_recovery_enabled(bp)) {
4661                 rc = bnxt_fw_reset_all(bp);
4662                 if (rc) {
4663                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4664                         return;
4665                 }
4666         }
4667
4668         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4669          * EXCEPTION_FATAL_ASYNC event to all the functions
4670          * (including MASTER FUNC). After receiving this Async, all the active
4671          * drivers should treat this case as FW initiated recovery
4672          */
4673         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4674                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4675                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4676
4677                 /* To recover from error */
4678                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4679                                   (void *)bp);
4680         }
4681 }
4682
4683 /* Driver should poll FW heartbeat, reset_counter with the frequency
4684  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4685  * When the driver detects heartbeat stop or change in reset_counter,
4686  * it has to trigger a reset to recover from the error condition.
4687  * A “master PF” is the function who will have the privilege to
4688  * initiate the chimp reset. The master PF will be elected by the
4689  * firmware and will be notified through async message.
4690  */
4691 static void bnxt_check_fw_health(void *arg)
4692 {
4693         struct bnxt *bp = arg;
4694         struct bnxt_error_recovery_info *info = bp->recovery_info;
4695         uint32_t val = 0, wait_msec;
4696
4697         if (!info || !bnxt_is_recovery_enabled(bp) ||
4698             is_bnxt_in_error(bp))
4699                 return;
4700
4701         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4702         if (val == info->last_heart_beat)
4703                 goto reset;
4704
4705         info->last_heart_beat = val;
4706
4707         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4708         if (val != info->last_reset_counter)
4709                 goto reset;
4710
4711         info->last_reset_counter = val;
4712
4713         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4714                           bnxt_check_fw_health, (void *)bp);
4715
4716         return;
4717 reset:
4718         /* Stop DMA to/from device */
4719         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4720         bp->flags |= BNXT_FLAG_FW_RESET;
4721
4722         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4723
4724         if (bnxt_is_master_func(bp))
4725                 wait_msec = info->master_func_wait_period;
4726         else
4727                 wait_msec = info->normal_func_wait_period;
4728
4729         rte_eal_alarm_set(US_PER_MS * wait_msec,
4730                           bnxt_fw_reset_cb, (void *)bp);
4731 }
4732
4733 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4734 {
4735         uint32_t polling_freq;
4736
4737         pthread_mutex_lock(&bp->health_check_lock);
4738
4739         if (!bnxt_is_recovery_enabled(bp))
4740                 goto done;
4741
4742         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4743                 goto done;
4744
4745         polling_freq = bp->recovery_info->driver_polling_freq;
4746
4747         rte_eal_alarm_set(US_PER_MS * polling_freq,
4748                           bnxt_check_fw_health, (void *)bp);
4749         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4750
4751 done:
4752         pthread_mutex_unlock(&bp->health_check_lock);
4753 }
4754
4755 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4756 {
4757         if (!bnxt_is_recovery_enabled(bp))
4758                 return;
4759
4760         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4761         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4762 }
4763
4764 static bool bnxt_vf_pciid(uint16_t device_id)
4765 {
4766         switch (device_id) {
4767         case BROADCOM_DEV_ID_57304_VF:
4768         case BROADCOM_DEV_ID_57406_VF:
4769         case BROADCOM_DEV_ID_5731X_VF:
4770         case BROADCOM_DEV_ID_5741X_VF:
4771         case BROADCOM_DEV_ID_57414_VF:
4772         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4773         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4774         case BROADCOM_DEV_ID_58802_VF:
4775         case BROADCOM_DEV_ID_57500_VF1:
4776         case BROADCOM_DEV_ID_57500_VF2:
4777                 /* FALLTHROUGH */
4778                 return true;
4779         default:
4780                 return false;
4781         }
4782 }
4783
4784 static bool bnxt_thor_device(uint16_t device_id)
4785 {
4786         switch (device_id) {
4787         case BROADCOM_DEV_ID_57508:
4788         case BROADCOM_DEV_ID_57504:
4789         case BROADCOM_DEV_ID_57502:
4790         case BROADCOM_DEV_ID_57508_MF1:
4791         case BROADCOM_DEV_ID_57504_MF1:
4792         case BROADCOM_DEV_ID_57502_MF1:
4793         case BROADCOM_DEV_ID_57508_MF2:
4794         case BROADCOM_DEV_ID_57504_MF2:
4795         case BROADCOM_DEV_ID_57502_MF2:
4796         case BROADCOM_DEV_ID_57500_VF1:
4797         case BROADCOM_DEV_ID_57500_VF2:
4798                 /* FALLTHROUGH */
4799                 return true;
4800         default:
4801                 return false;
4802         }
4803 }
4804
4805 bool bnxt_stratus_device(struct bnxt *bp)
4806 {
4807         uint16_t device_id = bp->pdev->id.device_id;
4808
4809         switch (device_id) {
4810         case BROADCOM_DEV_ID_STRATUS_NIC:
4811         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4812         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4813                 /* FALLTHROUGH */
4814                 return true;
4815         default:
4816                 return false;
4817         }
4818 }
4819
4820 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4821 {
4822         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4823         struct bnxt *bp = eth_dev->data->dev_private;
4824
4825         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4826         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4827         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4828         if (!bp->bar0 || !bp->doorbell_base) {
4829                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4830                 return -ENODEV;
4831         }
4832
4833         bp->eth_dev = eth_dev;
4834         bp->pdev = pci_dev;
4835
4836         return 0;
4837 }
4838
4839 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4840                                   struct bnxt_ctx_pg_info *ctx_pg,
4841                                   uint32_t mem_size,
4842                                   const char *suffix,
4843                                   uint16_t idx)
4844 {
4845         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4846         const struct rte_memzone *mz = NULL;
4847         char mz_name[RTE_MEMZONE_NAMESIZE];
4848         rte_iova_t mz_phys_addr;
4849         uint64_t valid_bits = 0;
4850         uint32_t sz;
4851         int i;
4852
4853         if (!mem_size)
4854                 return 0;
4855
4856         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4857                          BNXT_PAGE_SIZE;
4858         rmem->page_size = BNXT_PAGE_SIZE;
4859         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4860         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4861         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4862
4863         valid_bits = PTU_PTE_VALID;
4864
4865         if (rmem->nr_pages > 1) {
4866                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4867                          "bnxt_ctx_pg_tbl%s_%x_%d",
4868                          suffix, idx, bp->eth_dev->data->port_id);
4869                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4870                 mz = rte_memzone_lookup(mz_name);
4871                 if (!mz) {
4872                         mz = rte_memzone_reserve_aligned(mz_name,
4873                                                 rmem->nr_pages * 8,
4874                                                 SOCKET_ID_ANY,
4875                                                 RTE_MEMZONE_2MB |
4876                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4877                                                 RTE_MEMZONE_IOVA_CONTIG,
4878                                                 BNXT_PAGE_SIZE);
4879                         if (mz == NULL)
4880                                 return -ENOMEM;
4881                 }
4882
4883                 memset(mz->addr, 0, mz->len);
4884                 mz_phys_addr = mz->iova;
4885
4886                 rmem->pg_tbl = mz->addr;
4887                 rmem->pg_tbl_map = mz_phys_addr;
4888                 rmem->pg_tbl_mz = mz;
4889         }
4890
4891         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4892                  suffix, idx, bp->eth_dev->data->port_id);
4893         mz = rte_memzone_lookup(mz_name);
4894         if (!mz) {
4895                 mz = rte_memzone_reserve_aligned(mz_name,
4896                                                  mem_size,
4897                                                  SOCKET_ID_ANY,
4898                                                  RTE_MEMZONE_1GB |
4899                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4900                                                  RTE_MEMZONE_IOVA_CONTIG,
4901                                                  BNXT_PAGE_SIZE);
4902                 if (mz == NULL)
4903                         return -ENOMEM;
4904         }
4905
4906         memset(mz->addr, 0, mz->len);
4907         mz_phys_addr = mz->iova;
4908
4909         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4910                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4911                 rmem->dma_arr[i] = mz_phys_addr + sz;
4912
4913                 if (rmem->nr_pages > 1) {
4914                         if (i == rmem->nr_pages - 2 &&
4915                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4916                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4917                         else if (i == rmem->nr_pages - 1 &&
4918                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4919                                 valid_bits |= PTU_PTE_LAST;
4920
4921                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4922                                                            valid_bits);
4923                 }
4924         }
4925
4926         rmem->mz = mz;
4927         if (rmem->vmem_size)
4928                 rmem->vmem = (void **)mz->addr;
4929         rmem->dma_arr[0] = mz_phys_addr;
4930         return 0;
4931 }
4932
4933 static void bnxt_free_ctx_mem(struct bnxt *bp)
4934 {
4935         int i;
4936
4937         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4938                 return;
4939
4940         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4941         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4942         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4943         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4944         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4945         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4946         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4947         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4948         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4949         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4950         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4951
4952         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4953                 if (bp->ctx->tqm_mem[i])
4954                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4955         }
4956
4957         rte_free(bp->ctx);
4958         bp->ctx = NULL;
4959 }
4960
4961 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4962
4963 #define min_t(type, x, y) ({                    \
4964         type __min1 = (x);                      \
4965         type __min2 = (y);                      \
4966         __min1 < __min2 ? __min1 : __min2; })
4967
4968 #define max_t(type, x, y) ({                    \
4969         type __max1 = (x);                      \
4970         type __max2 = (y);                      \
4971         __max1 > __max2 ? __max1 : __max2; })
4972
4973 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4974
4975 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4976 {
4977         struct bnxt_ctx_pg_info *ctx_pg;
4978         struct bnxt_ctx_mem_info *ctx;
4979         uint32_t mem_size, ena, entries;
4980         uint32_t entries_sp, min;
4981         int i, rc;
4982
4983         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4984         if (rc) {
4985                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4986                 return rc;
4987         }
4988         ctx = bp->ctx;
4989         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4990                 return 0;
4991
4992         ctx_pg = &ctx->qp_mem;
4993         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4994         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4995         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4996         if (rc)
4997                 return rc;
4998
4999         ctx_pg = &ctx->srq_mem;
5000         ctx_pg->entries = ctx->srq_max_l2_entries;
5001         mem_size = ctx->srq_entry_size * ctx_pg->entries;
5002         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
5003         if (rc)
5004                 return rc;
5005
5006         ctx_pg = &ctx->cq_mem;
5007         ctx_pg->entries = ctx->cq_max_l2_entries;
5008         mem_size = ctx->cq_entry_size * ctx_pg->entries;
5009         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
5010         if (rc)
5011                 return rc;
5012
5013         ctx_pg = &ctx->vnic_mem;
5014         ctx_pg->entries = ctx->vnic_max_vnic_entries +
5015                 ctx->vnic_max_ring_table_entries;
5016         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
5017         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
5018         if (rc)
5019                 return rc;
5020
5021         ctx_pg = &ctx->stat_mem;
5022         ctx_pg->entries = ctx->stat_max_entries;
5023         mem_size = ctx->stat_entry_size * ctx_pg->entries;
5024         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
5025         if (rc)
5026                 return rc;
5027
5028         min = ctx->tqm_min_entries_per_ring;
5029
5030         entries_sp = ctx->qp_max_l2_entries +
5031                      ctx->vnic_max_vnic_entries +
5032                      2 * ctx->qp_min_qp1_entries + min;
5033         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
5034
5035         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
5036         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
5037         entries = clamp_t(uint32_t, entries, min,
5038                           ctx->tqm_max_entries_per_ring);
5039         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
5040                 ctx_pg = ctx->tqm_mem[i];
5041                 ctx_pg->entries = i ? entries : entries_sp;
5042                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
5043                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
5044                 if (rc)
5045                         return rc;
5046                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
5047         }
5048
5049         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
5050         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
5051         if (rc)
5052                 PMD_DRV_LOG(ERR,
5053                             "Failed to configure context mem: rc = %d\n", rc);
5054         else
5055                 ctx->flags |= BNXT_CTX_FLAG_INITED;
5056
5057         return rc;
5058 }
5059
5060 static int bnxt_alloc_stats_mem(struct bnxt *bp)
5061 {
5062         struct rte_pci_device *pci_dev = bp->pdev;
5063         char mz_name[RTE_MEMZONE_NAMESIZE];
5064         const struct rte_memzone *mz = NULL;
5065         uint32_t total_alloc_len;
5066         rte_iova_t mz_phys_addr;
5067
5068         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
5069                 return 0;
5070
5071         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5072                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5073                  pci_dev->addr.bus, pci_dev->addr.devid,
5074                  pci_dev->addr.function, "rx_port_stats");
5075         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5076         mz = rte_memzone_lookup(mz_name);
5077         total_alloc_len =
5078                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
5079                                        sizeof(struct rx_port_stats_ext) + 512);
5080         if (!mz) {
5081                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
5082                                          SOCKET_ID_ANY,
5083                                          RTE_MEMZONE_2MB |
5084                                          RTE_MEMZONE_SIZE_HINT_ONLY |
5085                                          RTE_MEMZONE_IOVA_CONTIG);
5086                 if (mz == NULL)
5087                         return -ENOMEM;
5088         }
5089         memset(mz->addr, 0, mz->len);
5090         mz_phys_addr = mz->iova;
5091
5092         bp->rx_mem_zone = (const void *)mz;
5093         bp->hw_rx_port_stats = mz->addr;
5094         bp->hw_rx_port_stats_map = mz_phys_addr;
5095
5096         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5097                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5098                  pci_dev->addr.bus, pci_dev->addr.devid,
5099                  pci_dev->addr.function, "tx_port_stats");
5100         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5101         mz = rte_memzone_lookup(mz_name);
5102         total_alloc_len =
5103                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
5104                                        sizeof(struct tx_port_stats_ext) + 512);
5105         if (!mz) {
5106                 mz = rte_memzone_reserve(mz_name,
5107                                          total_alloc_len,
5108                                          SOCKET_ID_ANY,
5109                                          RTE_MEMZONE_2MB |
5110                                          RTE_MEMZONE_SIZE_HINT_ONLY |
5111                                          RTE_MEMZONE_IOVA_CONTIG);
5112                 if (mz == NULL)
5113                         return -ENOMEM;
5114         }
5115         memset(mz->addr, 0, mz->len);
5116         mz_phys_addr = mz->iova;
5117
5118         bp->tx_mem_zone = (const void *)mz;
5119         bp->hw_tx_port_stats = mz->addr;
5120         bp->hw_tx_port_stats_map = mz_phys_addr;
5121         bp->flags |= BNXT_FLAG_PORT_STATS;
5122
5123         /* Display extended statistics if FW supports it */
5124         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
5125             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
5126             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
5127                 return 0;
5128
5129         bp->hw_rx_port_stats_ext = (void *)
5130                 ((uint8_t *)bp->hw_rx_port_stats +
5131                  sizeof(struct rx_port_stats));
5132         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
5133                 sizeof(struct rx_port_stats);
5134         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
5135
5136         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
5137             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
5138                 bp->hw_tx_port_stats_ext = (void *)
5139                         ((uint8_t *)bp->hw_tx_port_stats +
5140                          sizeof(struct tx_port_stats));
5141                 bp->hw_tx_port_stats_ext_map =
5142                         bp->hw_tx_port_stats_map +
5143                         sizeof(struct tx_port_stats);
5144                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
5145         }
5146
5147         return 0;
5148 }
5149
5150 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
5151 {
5152         struct bnxt *bp = eth_dev->data->dev_private;
5153         int rc = 0;
5154
5155         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
5156                                                RTE_ETHER_ADDR_LEN *
5157                                                bp->max_l2_ctx,
5158                                                0);
5159         if (eth_dev->data->mac_addrs == NULL) {
5160                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
5161                 return -ENOMEM;
5162         }
5163
5164         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
5165                 if (BNXT_PF(bp))
5166                         return -EINVAL;
5167
5168                 /* Generate a random MAC address, if none was assigned by PF */
5169                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5170                 bnxt_eth_hw_addr_random(bp->mac_addr);
5171                 PMD_DRV_LOG(INFO,
5172                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
5173                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5174                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5175
5176                 rc = bnxt_hwrm_set_mac(bp);
5177                 if (rc)
5178                         return rc;
5179         }
5180
5181         /* Copy the permanent MAC from the FUNC_QCAPS response */
5182         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5183
5184         return rc;
5185 }
5186
5187 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5188 {
5189         int rc = 0;
5190
5191         /* MAC is already configured in FW */
5192         if (BNXT_HAS_DFLT_MAC_SET(bp))
5193                 return 0;
5194
5195         /* Restore the old MAC configured */
5196         rc = bnxt_hwrm_set_mac(bp);
5197         if (rc)
5198                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5199
5200         return rc;
5201 }
5202
5203 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5204 {
5205         if (!BNXT_PF(bp))
5206                 return;
5207
5208 #define ALLOW_FUNC(x)   \
5209         { \
5210                 uint32_t arg = (x); \
5211                 bp->pf->vf_req_fwd[((arg) >> 5)] &= \
5212                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
5213         }
5214
5215         /* Forward all requests if firmware is new enough */
5216         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
5217              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
5218             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
5219                 memset(bp->pf->vf_req_fwd, 0xff, sizeof(bp->pf->vf_req_fwd));
5220         } else {
5221                 PMD_DRV_LOG(WARNING,
5222                             "Firmware too old for VF mailbox functionality\n");
5223                 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5224         }
5225
5226         /*
5227          * The following are used for driver cleanup. If we disallow these,
5228          * VF drivers can't clean up cleanly.
5229          */
5230         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
5231         ALLOW_FUNC(HWRM_VNIC_FREE);
5232         ALLOW_FUNC(HWRM_RING_FREE);
5233         ALLOW_FUNC(HWRM_RING_GRP_FREE);
5234         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
5235         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
5236         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
5237         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
5238         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
5239 }
5240
5241 uint16_t
5242 bnxt_get_svif(uint16_t port_id, bool func_svif,
5243               enum bnxt_ulp_intf_type type)
5244 {
5245         struct rte_eth_dev *eth_dev;
5246         struct bnxt *bp;
5247
5248         eth_dev = &rte_eth_devices[port_id];
5249         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5250                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5251                 if (!vfr)
5252                         return 0;
5253
5254                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5255                         return vfr->svif;
5256
5257                 eth_dev = vfr->parent_dev;
5258         }
5259
5260         bp = eth_dev->data->dev_private;
5261
5262         return func_svif ? bp->func_svif : bp->port_svif;
5263 }
5264
5265 uint16_t
5266 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5267 {
5268         struct rte_eth_dev *eth_dev;
5269         struct bnxt_vnic_info *vnic;
5270         struct bnxt *bp;
5271
5272         eth_dev = &rte_eth_devices[port];
5273         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5274                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5275                 if (!vfr)
5276                         return 0;
5277
5278                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5279                         return vfr->dflt_vnic_id;
5280
5281                 eth_dev = vfr->parent_dev;
5282         }
5283
5284         bp = eth_dev->data->dev_private;
5285
5286         vnic = BNXT_GET_DEFAULT_VNIC(bp);
5287
5288         return vnic->fw_vnic_id;
5289 }
5290
5291 uint16_t
5292 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5293 {
5294         struct rte_eth_dev *eth_dev;
5295         struct bnxt *bp;
5296
5297         eth_dev = &rte_eth_devices[port];
5298         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5299                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5300                 if (!vfr)
5301                         return 0;
5302
5303                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5304                         return vfr->fw_fid;
5305
5306                 eth_dev = vfr->parent_dev;
5307         }
5308
5309         bp = eth_dev->data->dev_private;
5310
5311         return bp->fw_fid;
5312 }
5313
5314 enum bnxt_ulp_intf_type
5315 bnxt_get_interface_type(uint16_t port)
5316 {
5317         struct rte_eth_dev *eth_dev;
5318         struct bnxt *bp;
5319
5320         eth_dev = &rte_eth_devices[port];
5321         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5322                 return BNXT_ULP_INTF_TYPE_VF_REP;
5323
5324         bp = eth_dev->data->dev_private;
5325         if (BNXT_PF(bp))
5326                 return BNXT_ULP_INTF_TYPE_PF;
5327         else if (BNXT_VF_IS_TRUSTED(bp))
5328                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5329         else if (BNXT_VF(bp))
5330                 return BNXT_ULP_INTF_TYPE_VF;
5331
5332         return BNXT_ULP_INTF_TYPE_INVALID;
5333 }
5334
5335 uint16_t
5336 bnxt_get_phy_port_id(uint16_t port_id)
5337 {
5338         struct bnxt_representor *vfr;
5339         struct rte_eth_dev *eth_dev;
5340         struct bnxt *bp;
5341
5342         eth_dev = &rte_eth_devices[port_id];
5343         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5344                 vfr = eth_dev->data->dev_private;
5345                 if (!vfr)
5346                         return 0;
5347
5348                 eth_dev = vfr->parent_dev;
5349         }
5350
5351         bp = eth_dev->data->dev_private;
5352
5353         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5354 }
5355
5356 uint16_t
5357 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5358 {
5359         struct rte_eth_dev *eth_dev;
5360         struct bnxt *bp;
5361
5362         eth_dev = &rte_eth_devices[port_id];
5363         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5364                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5365                 if (!vfr)
5366                         return 0;
5367
5368                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5369                         return vfr->fw_fid - 1;
5370
5371                 eth_dev = vfr->parent_dev;
5372         }
5373
5374         bp = eth_dev->data->dev_private;
5375
5376         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5377 }
5378
5379 uint16_t
5380 bnxt_get_vport(uint16_t port_id)
5381 {
5382         return (1 << bnxt_get_phy_port_id(port_id));
5383 }
5384
5385 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5386 {
5387         struct bnxt_error_recovery_info *info = bp->recovery_info;
5388
5389         if (info) {
5390                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5391                         memset(info, 0, sizeof(*info));
5392                 return;
5393         }
5394
5395         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5396                 return;
5397
5398         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5399                            sizeof(*info), 0);
5400         if (!info)
5401                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5402
5403         bp->recovery_info = info;
5404 }
5405
5406 static void bnxt_check_fw_status(struct bnxt *bp)
5407 {
5408         uint32_t fw_status;
5409
5410         if (!(bp->recovery_info &&
5411               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5412                 return;
5413
5414         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5415         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5416                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5417                             fw_status);
5418 }
5419
5420 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5421 {
5422         struct bnxt_error_recovery_info *info = bp->recovery_info;
5423         uint32_t status_loc;
5424         uint32_t sig_ver;
5425
5426         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5427                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5428         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5429                                    BNXT_GRCP_WINDOW_2_BASE +
5430                                    offsetof(struct hcomm_status,
5431                                             sig_ver)));
5432         /* If the signature is absent, then FW does not support this feature */
5433         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5434             HCOMM_STATUS_SIGNATURE_VAL)
5435                 return 0;
5436
5437         if (!info) {
5438                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5439                                    sizeof(*info), 0);
5440                 if (!info)
5441                         return -ENOMEM;
5442                 bp->recovery_info = info;
5443         } else {
5444                 memset(info, 0, sizeof(*info));
5445         }
5446
5447         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5448                                       BNXT_GRCP_WINDOW_2_BASE +
5449                                       offsetof(struct hcomm_status,
5450                                                fw_status_loc)));
5451
5452         /* Only pre-map the FW health status GRC register */
5453         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5454                 return 0;
5455
5456         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5457         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5458                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5459
5460         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5461                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5462
5463         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5464
5465         return 0;
5466 }
5467
5468 static int bnxt_init_fw(struct bnxt *bp)
5469 {
5470         uint16_t mtu;
5471         int rc = 0;
5472
5473         bp->fw_cap = 0;
5474
5475         rc = bnxt_map_hcomm_fw_status_reg(bp);
5476         if (rc)
5477                 return rc;
5478
5479         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5480         if (rc) {
5481                 bnxt_check_fw_status(bp);
5482                 return rc;
5483         }
5484
5485         rc = bnxt_hwrm_func_reset(bp);
5486         if (rc)
5487                 return -EIO;
5488
5489         rc = bnxt_hwrm_vnic_qcaps(bp);
5490         if (rc)
5491                 return rc;
5492
5493         rc = bnxt_hwrm_queue_qportcfg(bp);
5494         if (rc)
5495                 return rc;
5496
5497         /* Get the MAX capabilities for this function.
5498          * This function also allocates context memory for TQM rings and
5499          * informs the firmware about this allocated backing store memory.
5500          */
5501         rc = bnxt_hwrm_func_qcaps(bp);
5502         if (rc)
5503                 return rc;
5504
5505         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5506         if (rc)
5507                 return rc;
5508
5509         bnxt_hwrm_port_mac_qcfg(bp);
5510
5511         bnxt_hwrm_parent_pf_qcfg(bp);
5512
5513         bnxt_hwrm_port_phy_qcaps(bp);
5514
5515         bnxt_alloc_error_recovery_info(bp);
5516         /* Get the adapter error recovery support info */
5517         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5518         if (rc)
5519                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5520
5521         bnxt_hwrm_port_led_qcaps(bp);
5522
5523         return 0;
5524 }
5525
5526 static int
5527 bnxt_init_locks(struct bnxt *bp)
5528 {
5529         int err;
5530
5531         err = pthread_mutex_init(&bp->flow_lock, NULL);
5532         if (err) {
5533                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5534                 return err;
5535         }
5536
5537         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5538         if (err)
5539                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5540
5541         err = pthread_mutex_init(&bp->health_check_lock, NULL);
5542         if (err)
5543                 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5544         return err;
5545 }
5546
5547 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5548 {
5549         int rc = 0;
5550
5551         rc = bnxt_init_fw(bp);
5552         if (rc)
5553                 return rc;
5554
5555         if (!reconfig_dev) {
5556                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5557                 if (rc)
5558                         return rc;
5559         } else {
5560                 rc = bnxt_restore_dflt_mac(bp);
5561                 if (rc)
5562                         return rc;
5563         }
5564
5565         bnxt_config_vf_req_fwd(bp);
5566
5567         rc = bnxt_hwrm_func_driver_register(bp);
5568         if (rc) {
5569                 PMD_DRV_LOG(ERR, "Failed to register driver");
5570                 return -EBUSY;
5571         }
5572
5573         if (BNXT_PF(bp)) {
5574                 if (bp->pdev->max_vfs) {
5575                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5576                         if (rc) {
5577                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5578                                 return rc;
5579                         }
5580                 } else {
5581                         rc = bnxt_hwrm_allocate_pf_only(bp);
5582                         if (rc) {
5583                                 PMD_DRV_LOG(ERR,
5584                                             "Failed to allocate PF resources");
5585                                 return rc;
5586                         }
5587                 }
5588         }
5589
5590         rc = bnxt_alloc_mem(bp, reconfig_dev);
5591         if (rc)
5592                 return rc;
5593
5594         rc = bnxt_setup_int(bp);
5595         if (rc)
5596                 return rc;
5597
5598         rc = bnxt_request_int(bp);
5599         if (rc)
5600                 return rc;
5601
5602         rc = bnxt_init_ctx_mem(bp);
5603         if (rc) {
5604                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5605                 return rc;
5606         }
5607
5608         rc = bnxt_init_locks(bp);
5609         if (rc)
5610                 return rc;
5611
5612         return 0;
5613 }
5614
5615 static int
5616 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5617                           const char *value, void *opaque_arg)
5618 {
5619         struct bnxt *bp = opaque_arg;
5620         unsigned long truflow;
5621         char *end = NULL;
5622
5623         if (!value || !opaque_arg) {
5624                 PMD_DRV_LOG(ERR,
5625                             "Invalid parameter passed to truflow devargs.\n");
5626                 return -EINVAL;
5627         }
5628
5629         truflow = strtoul(value, &end, 10);
5630         if (end == NULL || *end != '\0' ||
5631             (truflow == ULONG_MAX && errno == ERANGE)) {
5632                 PMD_DRV_LOG(ERR,
5633                             "Invalid parameter passed to truflow devargs.\n");
5634                 return -EINVAL;
5635         }
5636
5637         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5638                 PMD_DRV_LOG(ERR,
5639                             "Invalid value passed to truflow devargs.\n");
5640                 return -EINVAL;
5641         }
5642
5643         if (truflow) {
5644                 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5645                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5646         } else {
5647                 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
5648                 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
5649         }
5650
5651         return 0;
5652 }
5653
5654 static int
5655 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5656                              const char *value, void *opaque_arg)
5657 {
5658         struct bnxt *bp = opaque_arg;
5659         unsigned long flow_xstat;
5660         char *end = NULL;
5661
5662         if (!value || !opaque_arg) {
5663                 PMD_DRV_LOG(ERR,
5664                             "Invalid parameter passed to flow_xstat devarg.\n");
5665                 return -EINVAL;
5666         }
5667
5668         flow_xstat = strtoul(value, &end, 10);
5669         if (end == NULL || *end != '\0' ||
5670             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5671                 PMD_DRV_LOG(ERR,
5672                             "Invalid parameter passed to flow_xstat devarg.\n");
5673                 return -EINVAL;
5674         }
5675
5676         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5677                 PMD_DRV_LOG(ERR,
5678                             "Invalid value passed to flow_xstat devarg.\n");
5679                 return -EINVAL;
5680         }
5681
5682         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5683         if (BNXT_FLOW_XSTATS_EN(bp))
5684                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5685
5686         return 0;
5687 }
5688
5689 static int
5690 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5691                                         const char *value, void *opaque_arg)
5692 {
5693         struct bnxt *bp = opaque_arg;
5694         unsigned long max_num_kflows;
5695         char *end = NULL;
5696
5697         if (!value || !opaque_arg) {
5698                 PMD_DRV_LOG(ERR,
5699                         "Invalid parameter passed to max_num_kflows devarg.\n");
5700                 return -EINVAL;
5701         }
5702
5703         max_num_kflows = strtoul(value, &end, 10);
5704         if (end == NULL || *end != '\0' ||
5705                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5706                 PMD_DRV_LOG(ERR,
5707                         "Invalid parameter passed to max_num_kflows devarg.\n");
5708                 return -EINVAL;
5709         }
5710
5711         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5712                 PMD_DRV_LOG(ERR,
5713                         "Invalid value passed to max_num_kflows devarg.\n");
5714                 return -EINVAL;
5715         }
5716
5717         bp->max_num_kflows = max_num_kflows;
5718         if (bp->max_num_kflows)
5719                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5720                                 max_num_kflows);
5721
5722         return 0;
5723 }
5724
5725 static int
5726 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5727                             const char *value, void *opaque_arg)
5728 {
5729         struct bnxt_representor *vfr_bp = opaque_arg;
5730         unsigned long rep_is_pf;
5731         char *end = NULL;
5732
5733         if (!value || !opaque_arg) {
5734                 PMD_DRV_LOG(ERR,
5735                             "Invalid parameter passed to rep_is_pf devargs.\n");
5736                 return -EINVAL;
5737         }
5738
5739         rep_is_pf = strtoul(value, &end, 10);
5740         if (end == NULL || *end != '\0' ||
5741             (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5742                 PMD_DRV_LOG(ERR,
5743                             "Invalid parameter passed to rep_is_pf devargs.\n");
5744                 return -EINVAL;
5745         }
5746
5747         if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5748                 PMD_DRV_LOG(ERR,
5749                             "Invalid value passed to rep_is_pf devargs.\n");
5750                 return -EINVAL;
5751         }
5752
5753         vfr_bp->flags |= rep_is_pf;
5754         if (BNXT_REP_PF(vfr_bp))
5755                 PMD_DRV_LOG(INFO, "PF representor\n");
5756         else
5757                 PMD_DRV_LOG(INFO, "VF representor\n");
5758
5759         return 0;
5760 }
5761
5762 static int
5763 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5764                                const char *value, void *opaque_arg)
5765 {
5766         struct bnxt_representor *vfr_bp = opaque_arg;
5767         unsigned long rep_based_pf;
5768         char *end = NULL;
5769
5770         if (!value || !opaque_arg) {
5771                 PMD_DRV_LOG(ERR,
5772                             "Invalid parameter passed to rep_based_pf "
5773                             "devargs.\n");
5774                 return -EINVAL;
5775         }
5776
5777         rep_based_pf = strtoul(value, &end, 10);
5778         if (end == NULL || *end != '\0' ||
5779             (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5780                 PMD_DRV_LOG(ERR,
5781                             "Invalid parameter passed to rep_based_pf "
5782                             "devargs.\n");
5783                 return -EINVAL;
5784         }
5785
5786         if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5787                 PMD_DRV_LOG(ERR,
5788                             "Invalid value passed to rep_based_pf devargs.\n");
5789                 return -EINVAL;
5790         }
5791
5792         vfr_bp->rep_based_pf = rep_based_pf;
5793         PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5794
5795         return 0;
5796 }
5797
5798 static int
5799 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5800                             const char *value, void *opaque_arg)
5801 {
5802         struct bnxt_representor *vfr_bp = opaque_arg;
5803         unsigned long rep_q_r2f;
5804         char *end = NULL;
5805
5806         if (!value || !opaque_arg) {
5807                 PMD_DRV_LOG(ERR,
5808                             "Invalid parameter passed to rep_q_r2f "
5809                             "devargs.\n");
5810                 return -EINVAL;
5811         }
5812
5813         rep_q_r2f = strtoul(value, &end, 10);
5814         if (end == NULL || *end != '\0' ||
5815             (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5816                 PMD_DRV_LOG(ERR,
5817                             "Invalid parameter passed to rep_q_r2f "
5818                             "devargs.\n");
5819                 return -EINVAL;
5820         }
5821
5822         if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5823                 PMD_DRV_LOG(ERR,
5824                             "Invalid value passed to rep_q_r2f devargs.\n");
5825                 return -EINVAL;
5826         }
5827
5828         vfr_bp->rep_q_r2f = rep_q_r2f;
5829         vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5830         PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5831
5832         return 0;
5833 }
5834
5835 static int
5836 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5837                             const char *value, void *opaque_arg)
5838 {
5839         struct bnxt_representor *vfr_bp = opaque_arg;
5840         unsigned long rep_q_f2r;
5841         char *end = NULL;
5842
5843         if (!value || !opaque_arg) {
5844                 PMD_DRV_LOG(ERR,
5845                             "Invalid parameter passed to rep_q_f2r "
5846                             "devargs.\n");
5847                 return -EINVAL;
5848         }
5849
5850         rep_q_f2r = strtoul(value, &end, 10);
5851         if (end == NULL || *end != '\0' ||
5852             (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5853                 PMD_DRV_LOG(ERR,
5854                             "Invalid parameter passed to rep_q_f2r "
5855                             "devargs.\n");
5856                 return -EINVAL;
5857         }
5858
5859         if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5860                 PMD_DRV_LOG(ERR,
5861                             "Invalid value passed to rep_q_f2r devargs.\n");
5862                 return -EINVAL;
5863         }
5864
5865         vfr_bp->rep_q_f2r = rep_q_f2r;
5866         vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5867         PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5868
5869         return 0;
5870 }
5871
5872 static int
5873 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5874                              const char *value, void *opaque_arg)
5875 {
5876         struct bnxt_representor *vfr_bp = opaque_arg;
5877         unsigned long rep_fc_r2f;
5878         char *end = NULL;
5879
5880         if (!value || !opaque_arg) {
5881                 PMD_DRV_LOG(ERR,
5882                             "Invalid parameter passed to rep_fc_r2f "
5883                             "devargs.\n");
5884                 return -EINVAL;
5885         }
5886
5887         rep_fc_r2f = strtoul(value, &end, 10);
5888         if (end == NULL || *end != '\0' ||
5889             (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5890                 PMD_DRV_LOG(ERR,
5891                             "Invalid parameter passed to rep_fc_r2f "
5892                             "devargs.\n");
5893                 return -EINVAL;
5894         }
5895
5896         if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5897                 PMD_DRV_LOG(ERR,
5898                             "Invalid value passed to rep_fc_r2f devargs.\n");
5899                 return -EINVAL;
5900         }
5901
5902         vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5903         vfr_bp->rep_fc_r2f = rep_fc_r2f;
5904         PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5905
5906         return 0;
5907 }
5908
5909 static int
5910 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5911                              const char *value, void *opaque_arg)
5912 {
5913         struct bnxt_representor *vfr_bp = opaque_arg;
5914         unsigned long rep_fc_f2r;
5915         char *end = NULL;
5916
5917         if (!value || !opaque_arg) {
5918                 PMD_DRV_LOG(ERR,
5919                             "Invalid parameter passed to rep_fc_f2r "
5920                             "devargs.\n");
5921                 return -EINVAL;
5922         }
5923
5924         rep_fc_f2r = strtoul(value, &end, 10);
5925         if (end == NULL || *end != '\0' ||
5926             (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5927                 PMD_DRV_LOG(ERR,
5928                             "Invalid parameter passed to rep_fc_f2r "
5929                             "devargs.\n");
5930                 return -EINVAL;
5931         }
5932
5933         if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5934                 PMD_DRV_LOG(ERR,
5935                             "Invalid value passed to rep_fc_f2r devargs.\n");
5936                 return -EINVAL;
5937         }
5938
5939         vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5940         vfr_bp->rep_fc_f2r = rep_fc_f2r;
5941         PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5942
5943         return 0;
5944 }
5945
5946 static void
5947 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5948 {
5949         struct rte_kvargs *kvlist;
5950
5951         if (devargs == NULL)
5952                 return;
5953
5954         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5955         if (kvlist == NULL)
5956                 return;
5957
5958         /*
5959          * Handler for "truflow" devarg.
5960          * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1"
5961          */
5962         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5963                            bnxt_parse_devarg_truflow, bp);
5964
5965         /*
5966          * Handler for "flow_xstat" devarg.
5967          * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1"
5968          */
5969         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5970                            bnxt_parse_devarg_flow_xstat, bp);
5971
5972         /*
5973          * Handler for "max_num_kflows" devarg.
5974          * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32"
5975          */
5976         rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5977                            bnxt_parse_devarg_max_num_kflows, bp);
5978
5979         rte_kvargs_free(kvlist);
5980 }
5981
5982 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5983 {
5984         int rc = 0;
5985
5986         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5987                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5988                 if (rc)
5989                         PMD_DRV_LOG(ERR,
5990                                     "Failed to alloc switch domain: %d\n", rc);
5991                 else
5992                         PMD_DRV_LOG(INFO,
5993                                     "Switch domain allocated %d\n",
5994                                     bp->switch_domain_id);
5995         }
5996
5997         return rc;
5998 }
5999
6000 static int
6001 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
6002 {
6003         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
6004         static int version_printed;
6005         struct bnxt *bp;
6006         int rc;
6007
6008         if (version_printed++ == 0)
6009                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
6010
6011         eth_dev->dev_ops = &bnxt_dev_ops;
6012         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
6013         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
6014         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
6015         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
6016         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
6017
6018         /*
6019          * For secondary processes, we don't initialise any further
6020          * as primary has already done this work.
6021          */
6022         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6023                 return 0;
6024
6025         rte_eth_copy_pci_info(eth_dev, pci_dev);
6026
6027         bp = eth_dev->data->dev_private;
6028
6029         /* Parse dev arguments passed on when starting the DPDK application. */
6030         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
6031
6032         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
6033
6034         if (bnxt_vf_pciid(pci_dev->id.device_id))
6035                 bp->flags |= BNXT_FLAG_VF;
6036
6037         if (bnxt_thor_device(pci_dev->id.device_id))
6038                 bp->flags |= BNXT_FLAG_THOR_CHIP;
6039
6040         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
6041             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
6042             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
6043             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
6044                 bp->flags |= BNXT_FLAG_STINGRAY;
6045
6046         rc = bnxt_init_board(eth_dev);
6047         if (rc) {
6048                 PMD_DRV_LOG(ERR,
6049                             "Failed to initialize board rc: %x\n", rc);
6050                 return rc;
6051         }
6052
6053         rc = bnxt_alloc_pf_info(bp);
6054         if (rc)
6055                 goto error_free;
6056
6057         rc = bnxt_alloc_link_info(bp);
6058         if (rc)
6059                 goto error_free;
6060
6061         rc = bnxt_alloc_parent_info(bp);
6062         if (rc)
6063                 goto error_free;
6064
6065         rc = bnxt_alloc_hwrm_resources(bp);
6066         if (rc) {
6067                 PMD_DRV_LOG(ERR,
6068                             "Failed to allocate hwrm resource rc: %x\n", rc);
6069                 goto error_free;
6070         }
6071         rc = bnxt_alloc_leds_info(bp);
6072         if (rc)
6073                 goto error_free;
6074
6075         rc = bnxt_alloc_cos_queues(bp);
6076         if (rc)
6077                 goto error_free;
6078
6079         rc = bnxt_init_resources(bp, false);
6080         if (rc)
6081                 goto error_free;
6082
6083         rc = bnxt_alloc_stats_mem(bp);
6084         if (rc)
6085                 goto error_free;
6086
6087         bnxt_alloc_switch_domain(bp);
6088
6089         PMD_DRV_LOG(INFO,
6090                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
6091                     pci_dev->mem_resource[0].phys_addr,
6092                     pci_dev->mem_resource[0].addr);
6093
6094         return 0;
6095
6096 error_free:
6097         bnxt_dev_uninit(eth_dev);
6098         return rc;
6099 }
6100
6101
6102 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
6103 {
6104         if (!ctx)
6105                 return;
6106
6107         if (ctx->va)
6108                 rte_free(ctx->va);
6109
6110         ctx->va = NULL;
6111         ctx->dma = RTE_BAD_IOVA;
6112         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
6113 }
6114
6115 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
6116 {
6117         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
6118                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6119                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
6120                                   bp->flow_stat->max_fc,
6121                                   false);
6122
6123         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
6124                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6125                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
6126                                   bp->flow_stat->max_fc,
6127                                   false);
6128
6129         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6130                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
6131         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6132
6133         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6134                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
6135         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6136
6137         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6138                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
6139         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6140
6141         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6142                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
6143         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6144 }
6145
6146 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
6147 {
6148         bnxt_unregister_fc_ctx_mem(bp);
6149
6150         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
6151         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
6152         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
6153         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
6154 }
6155
6156 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
6157 {
6158         if (BNXT_FLOW_XSTATS_EN(bp))
6159                 bnxt_uninit_fc_ctx_mem(bp);
6160 }
6161
6162 static void
6163 bnxt_free_error_recovery_info(struct bnxt *bp)
6164 {
6165         rte_free(bp->recovery_info);
6166         bp->recovery_info = NULL;
6167         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
6168 }
6169
6170 static void
6171 bnxt_uninit_locks(struct bnxt *bp)
6172 {
6173         pthread_mutex_destroy(&bp->flow_lock);
6174         pthread_mutex_destroy(&bp->def_cp_lock);
6175         pthread_mutex_destroy(&bp->health_check_lock);
6176         if (bp->rep_info) {
6177                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
6178                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
6179         }
6180 }
6181
6182 static int
6183 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
6184 {
6185         int rc;
6186
6187         bnxt_free_int(bp);
6188         bnxt_free_mem(bp, reconfig_dev);
6189         bnxt_hwrm_func_buf_unrgtr(bp);
6190         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
6191         bp->flags &= ~BNXT_FLAG_REGISTERED;
6192         bnxt_free_ctx_mem(bp);
6193         if (!reconfig_dev) {
6194                 bnxt_free_hwrm_resources(bp);
6195                 bnxt_free_error_recovery_info(bp);
6196         }
6197
6198         bnxt_uninit_ctx_mem(bp);
6199
6200         bnxt_uninit_locks(bp);
6201         bnxt_free_flow_stats_info(bp);
6202         bnxt_free_rep_info(bp);
6203         rte_free(bp->ptp_cfg);
6204         bp->ptp_cfg = NULL;
6205         return rc;
6206 }
6207
6208 static int
6209 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
6210 {
6211         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6212                 return -EPERM;
6213
6214         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
6215
6216         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
6217                 bnxt_dev_close_op(eth_dev);
6218
6219         return 0;
6220 }
6221
6222 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
6223 {
6224         struct bnxt *bp = eth_dev->data->dev_private;
6225         struct rte_eth_dev *vf_rep_eth_dev;
6226         int ret = 0, i;
6227
6228         if (!bp)
6229                 return -EINVAL;
6230
6231         for (i = 0; i < bp->num_reps; i++) {
6232                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
6233                 if (!vf_rep_eth_dev)
6234                         continue;
6235                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
6236                             vf_rep_eth_dev->data->port_id);
6237                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
6238         }
6239         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
6240                     eth_dev->data->port_id);
6241         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
6242
6243         return ret;
6244 }
6245
6246 static void bnxt_free_rep_info(struct bnxt *bp)
6247 {
6248         rte_free(bp->rep_info);
6249         bp->rep_info = NULL;
6250         rte_free(bp->cfa_code_map);
6251         bp->cfa_code_map = NULL;
6252 }
6253
6254 static int bnxt_init_rep_info(struct bnxt *bp)
6255 {
6256         int i = 0, rc;
6257
6258         if (bp->rep_info)
6259                 return 0;
6260
6261         bp->rep_info = rte_zmalloc("bnxt_rep_info",
6262                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
6263                                    0);
6264         if (!bp->rep_info) {
6265                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
6266                 return -ENOMEM;
6267         }
6268         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
6269                                        sizeof(*bp->cfa_code_map) *
6270                                        BNXT_MAX_CFA_CODE, 0);
6271         if (!bp->cfa_code_map) {
6272                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
6273                 bnxt_free_rep_info(bp);
6274                 return -ENOMEM;
6275         }
6276
6277         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
6278                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
6279
6280         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
6281         if (rc) {
6282                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
6283                 bnxt_free_rep_info(bp);
6284                 return rc;
6285         }
6286
6287         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
6288         if (rc) {
6289                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
6290                 bnxt_free_rep_info(bp);
6291                 return rc;
6292         }
6293
6294         return rc;
6295 }
6296
6297 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
6298                                struct rte_eth_devargs eth_da,
6299                                struct rte_eth_dev *backing_eth_dev,
6300                                const char *dev_args)
6301 {
6302         struct rte_eth_dev *vf_rep_eth_dev;
6303         char name[RTE_ETH_NAME_MAX_LEN];
6304         struct bnxt *backing_bp;
6305         uint16_t num_rep;
6306         int i, ret = 0;
6307         struct rte_kvargs *kvlist;
6308
6309         num_rep = eth_da.nb_representor_ports;
6310         if (num_rep > BNXT_MAX_VF_REPS) {
6311                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
6312                             num_rep, BNXT_MAX_VF_REPS);
6313                 return -EINVAL;
6314         }
6315
6316         if (num_rep >= RTE_MAX_ETHPORTS) {
6317                 PMD_DRV_LOG(ERR,
6318                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6319                             num_rep, RTE_MAX_ETHPORTS);
6320                 return -EINVAL;
6321         }
6322
6323         backing_bp = backing_eth_dev->data->dev_private;
6324
6325         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6326                 PMD_DRV_LOG(ERR,
6327                             "Not a PF or trusted VF. No Representor support\n");
6328                 /* Returning an error is not an option.
6329                  * Applications are not handling this correctly
6330                  */
6331                 return 0;
6332         }
6333
6334         if (bnxt_init_rep_info(backing_bp))
6335                 return 0;
6336
6337         for (i = 0; i < num_rep; i++) {
6338                 struct bnxt_representor representor = {
6339                         .vf_id = eth_da.representor_ports[i],
6340                         .switch_domain_id = backing_bp->switch_domain_id,
6341                         .parent_dev = backing_eth_dev
6342                 };
6343
6344                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6345                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6346                                     representor.vf_id, BNXT_MAX_VF_REPS);
6347                         continue;
6348                 }
6349
6350                 /* representor port net_bdf_port */
6351                 snprintf(name, sizeof(name), "net_%s_representor_%d",
6352                          pci_dev->device.name, eth_da.representor_ports[i]);
6353
6354                 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
6355                 if (kvlist) {
6356                         /*
6357                          * Handler for "rep_is_pf" devarg.
6358                          * Invoked as for ex: "-w 000:00:0d.0,
6359                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6360                          */
6361                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
6362                                            bnxt_parse_devarg_rep_is_pf,
6363                                            (void *)&representor);
6364                         /*
6365                          * Handler for "rep_based_pf" devarg.
6366                          * Invoked as for ex: "-w 000:00:0d.0,
6367                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6368                          */
6369                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_BASED_PF,
6370                                            bnxt_parse_devarg_rep_based_pf,
6371                                            (void *)&representor);
6372                         /*
6373                          * Handler for "rep_based_pf" devarg.
6374                          * Invoked as for ex: "-w 000:00:0d.0,
6375                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6376                          */
6377                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
6378                                            bnxt_parse_devarg_rep_q_r2f,
6379                                            (void *)&representor);
6380                         /*
6381                          * Handler for "rep_based_pf" devarg.
6382                          * Invoked as for ex: "-w 000:00:0d.0,
6383                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6384                          */
6385                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
6386                                            bnxt_parse_devarg_rep_q_f2r,
6387                                            (void *)&representor);
6388                         /*
6389                          * Handler for "rep_based_pf" devarg.
6390                          * Invoked as for ex: "-w 000:00:0d.0,
6391                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6392                          */
6393                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
6394                                            bnxt_parse_devarg_rep_fc_r2f,
6395                                            (void *)&representor);
6396                         /*
6397                          * Handler for "rep_based_pf" devarg.
6398                          * Invoked as for ex: "-w 000:00:0d.0,
6399                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6400                          */
6401                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
6402                                            bnxt_parse_devarg_rep_fc_f2r,
6403                                            (void *)&representor);
6404                 }
6405
6406                 ret = rte_eth_dev_create(&pci_dev->device, name,
6407                                          sizeof(struct bnxt_representor),
6408                                          NULL, NULL,
6409                                          bnxt_representor_init,
6410                                          &representor);
6411                 if (ret) {
6412                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6413                                     "representor %s.", name);
6414                         goto err;
6415                 }
6416
6417                 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6418                 if (!vf_rep_eth_dev) {
6419                         PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6420                                     " for VF-Rep: %s.", name);
6421                         ret = -ENODEV;
6422                         goto err;
6423                 }
6424
6425                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6426                             backing_eth_dev->data->port_id);
6427                 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6428                                                          vf_rep_eth_dev;
6429                 backing_bp->num_reps++;
6430
6431         }
6432
6433         return 0;
6434
6435 err:
6436         /* If num_rep > 1, then rollback already created
6437          * ports, since we'll be failing the probe anyway
6438          */
6439         if (num_rep > 1)
6440                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6441
6442         return ret;
6443 }
6444
6445 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6446                           struct rte_pci_device *pci_dev)
6447 {
6448         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6449         struct rte_eth_dev *backing_eth_dev;
6450         uint16_t num_rep;
6451         int ret = 0;
6452
6453         if (pci_dev->device.devargs) {
6454                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6455                                             &eth_da);
6456                 if (ret)
6457                         return ret;
6458         }
6459
6460         num_rep = eth_da.nb_representor_ports;
6461         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6462                     num_rep);
6463
6464         /* We could come here after first level of probe is already invoked
6465          * as part of an application bringup(OVS-DPDK vswitchd), so first check
6466          * for already allocated eth_dev for the backing device (PF/Trusted VF)
6467          */
6468         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6469         if (backing_eth_dev == NULL) {
6470                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6471                                          sizeof(struct bnxt),
6472                                          eth_dev_pci_specific_init, pci_dev,
6473                                          bnxt_dev_init, NULL);
6474
6475                 if (ret || !num_rep)
6476                         return ret;
6477
6478                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6479         }
6480         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6481                     backing_eth_dev->data->port_id);
6482
6483         if (!num_rep)
6484                 return ret;
6485
6486         /* probe representor ports now */
6487         ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev,
6488                                   pci_dev->device.devargs->args);
6489
6490         return ret;
6491 }
6492
6493 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6494 {
6495         struct rte_eth_dev *eth_dev;
6496
6497         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6498         if (!eth_dev)
6499                 return 0; /* Invoked typically only by OVS-DPDK, by the
6500                            * time it comes here the eth_dev is already
6501                            * deleted by rte_eth_dev_close(), so returning
6502                            * +ve value will at least help in proper cleanup
6503                            */
6504
6505         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6506         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6507                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6508                         return rte_eth_dev_destroy(eth_dev,
6509                                                    bnxt_representor_uninit);
6510                 else
6511                         return rte_eth_dev_destroy(eth_dev,
6512                                                    bnxt_dev_uninit);
6513         } else {
6514                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6515         }
6516 }
6517
6518 static struct rte_pci_driver bnxt_rte_pmd = {
6519         .id_table = bnxt_pci_id_map,
6520         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6521                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6522                                                   * and OVS-DPDK
6523                                                   */
6524         .probe = bnxt_pci_probe,
6525         .remove = bnxt_pci_remove,
6526 };
6527
6528 static bool
6529 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6530 {
6531         if (strcmp(dev->device->driver->name, drv->driver.name))
6532                 return false;
6533
6534         return true;
6535 }
6536
6537 bool is_bnxt_supported(struct rte_eth_dev *dev)
6538 {
6539         return is_device_supported(dev, &bnxt_rte_pmd);
6540 }
6541
6542 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
6543 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6544 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6545 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");