drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16
  17 #include "bnxt.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_rxq.h"
  23 #include "bnxt_rxr.h"
  24 #include "bnxt_stats.h"
  25 #include "bnxt_txq.h"
  26 #include "bnxt_txr.h"
  27 #include "bnxt_vnic.h"
  28 #include "hsi_struct_def_dpdk.h"
  29 #include "bnxt_nvm_defs.h"
  30
  31 #define DRV_MODULE_NAME         "bnxt"
  32 static const char bnxt_version[] =
  33         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  34 int bnxt_logtype_driver;
  35
  36 /*
  37  * The set of PCI devices this driver supports
  38  */
  39 static const struct rte_pci_id bnxt_pci_id_map[] = {
  40         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  41                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  42         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  43                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  45         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  93         { .vendor_id = 0, /* sentinel */ },
  94 };
  95
  96 #define BNXT_ETH_RSS_SUPPORT (  \
  97         ETH_RSS_IPV4 |          \
  98         ETH_RSS_NONFRAG_IPV4_TCP |      \
  99         ETH_RSS_NONFRAG_IPV4_UDP |      \
 100         ETH_RSS_IPV6 |          \
 101         ETH_RSS_NONFRAG_IPV6_TCP |      \
 102         ETH_RSS_NONFRAG_IPV6_UDP)
 103
 104 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 105                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 106                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 107                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 108                                      DEV_TX_OFFLOAD_TCP_TSO | \
 109                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 110                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 111                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 112                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 113                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 114                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 115                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 116
 117 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 118                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 119                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 120                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 121                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 122                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 123                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 124                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 125                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 126                                      DEV_RX_OFFLOAD_TCP_LRO | \
 127                                      DEV_RX_OFFLOAD_SCATTER | \
 128                                      DEV_RX_OFFLOAD_RSS_HASH)
 129
 130 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
 131 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
 132 static const char *const bnxt_dev_args[] = {
 133         BNXT_DEVARG_TRUFLOW,
 134         BNXT_DEVARG_FLOW_XSTAT,
 135         NULL
 136 };
 137
 138 /*
 139  * truflow == false to disable the feature
 140  * truflow == true to enable the feature
 141  */
 142 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 143
 144 /*
 145  * flow_xstat == false to disable the feature
 146  * flow_xstat == true to enable the feature
 147  */
 148 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 149
 150 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 151 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 152 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 153 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 154 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 155 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 156 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 157 static void bnxt_dev_recover(void *arg);
 158
 159 int is_bnxt_in_error(struct bnxt *bp)
 160 {
 161         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 162                 return -EIO;
 163         if (bp->flags & BNXT_FLAG_FW_RESET)
 164                 return -EBUSY;
 165
 166         return 0;
 167 }
 168
 169 /***********************/
 170
 171 /*
 172  * High level utility functions
 173  */
 174
 175 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 176 {
 177         if (!BNXT_CHIP_THOR(bp))
 178                 return 1;
 179
 180         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 181                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 182                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 183 }
 184
 185 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 186 {
 187         if (!BNXT_CHIP_THOR(bp))
 188                 return HW_HASH_INDEX_SIZE;
 189
 190         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 191 }
 192
 193 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 194 {
 195         bnxt_free_filter_mem(bp);
 196         bnxt_free_vnic_attributes(bp);
 197         bnxt_free_vnic_mem(bp);
 198
 199         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 200          * If the number of rings change across fw update,
 201          * we don't have much choice except to warn the user.
 202          */
 203         if (!reconfig) {
 204                 bnxt_free_stats(bp);
 205                 bnxt_free_tx_rings(bp);
 206                 bnxt_free_rx_rings(bp);
 207         }
 208         bnxt_free_async_cp_ring(bp);
 209         bnxt_free_rxtx_nq_ring(bp);
 210
 211         rte_free(bp->grp_info);
 212         bp->grp_info = NULL;
 213 }
 214
 215 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 216 {
 217         int rc;
 218
 219         rc = bnxt_alloc_ring_grps(bp);
 220         if (rc)
 221                 goto alloc_mem_err;
 222
 223         rc = bnxt_alloc_async_ring_struct(bp);
 224         if (rc)
 225                 goto alloc_mem_err;
 226
 227         rc = bnxt_alloc_vnic_mem(bp);
 228         if (rc)
 229                 goto alloc_mem_err;
 230
 231         rc = bnxt_alloc_vnic_attributes(bp);
 232         if (rc)
 233                 goto alloc_mem_err;
 234
 235         rc = bnxt_alloc_filter_mem(bp);
 236         if (rc)
 237                 goto alloc_mem_err;
 238
 239         rc = bnxt_alloc_async_cp_ring(bp);
 240         if (rc)
 241                 goto alloc_mem_err;
 242
 243         rc = bnxt_alloc_rxtx_nq_ring(bp);
 244         if (rc)
 245                 goto alloc_mem_err;
 246
 247         return 0;
 248
 249 alloc_mem_err:
 250         bnxt_free_mem(bp, reconfig);
 251         return rc;
 252 }
 253
 254 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 255 {
 256         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 257         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 258         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 259         struct bnxt_rx_queue *rxq;
 260         unsigned int j;
 261         int rc;
 262
 263         rc = bnxt_vnic_grp_alloc(bp, vnic);
 264         if (rc)
 265                 goto err_out;
 266
 267         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 268                     vnic_id, vnic, vnic->fw_grp_ids);
 269
 270         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 271         if (rc)
 272                 goto err_out;
 273
 274         /* Alloc RSS context only if RSS mode is enabled */
 275         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 276                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 277
 278                 rc = 0;
 279                 for (j = 0; j < nr_ctxs; j++) {
 280                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 281                         if (rc)
 282                                 break;
 283                 }
 284                 if (rc) {
 285                         PMD_DRV_LOG(ERR,
 286                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 287                                     vnic_id, j, rc);
 288                         goto err_out;
 289                 }
 290                 vnic->num_lb_ctxts = nr_ctxs;
 291         }
 292
 293         /*
 294          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 295          * setting is not available at this time, it will not be
 296          * configured correctly in the CFA.
 297          */
 298         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 299                 vnic->vlan_strip = true;
 300         else
 301                 vnic->vlan_strip = false;
 302
 303         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 304         if (rc)
 305                 goto err_out;
 306
 307         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 308         if (rc)
 309                 goto err_out;
 310
 311         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 312                 rxq = bp->eth_dev->data->rx_queues[j];
 313
 314                 PMD_DRV_LOG(DEBUG,
 315                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 316                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 317
 318                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 319                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 320                 else
 321                         vnic->rx_queue_cnt++;
 322         }
 323
 324         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 325
 326         rc = bnxt_vnic_rss_configure(bp, vnic);
 327         if (rc)
 328                 goto err_out;
 329
 330         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 331
 332         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 333                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 334         else
 335                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 336
 337         return 0;
 338 err_out:
 339         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 340                     vnic_id, rc);
 341         return rc;
 342 }
 343
 344 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 345 {
 346         int rc = 0;
 347
 348         rc = bnxt_hwrm_ctx_rgtr(bp, bp->rx_fc_in_tbl.dma,
 349                                 &bp->rx_fc_in_tbl.ctx_id);
 350         if (rc)
 351                 return rc;
 352
 353         PMD_DRV_LOG(DEBUG,
 354                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 355                     " rx_fc_in_tbl.ctx_id = %d\n",
 356                     bp->rx_fc_in_tbl.va,
 357                     (void *)((uintptr_t)bp->rx_fc_in_tbl.dma),
 358                     bp->rx_fc_in_tbl.ctx_id);
 359
 360         rc = bnxt_hwrm_ctx_rgtr(bp, bp->rx_fc_out_tbl.dma,
 361                                 &bp->rx_fc_out_tbl.ctx_id);
 362         if (rc)
 363                 return rc;
 364
 365         PMD_DRV_LOG(DEBUG,
 366                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 367                     " rx_fc_out_tbl.ctx_id = %d\n",
 368                     bp->rx_fc_out_tbl.va,
 369                     (void *)((uintptr_t)bp->rx_fc_out_tbl.dma),
 370                     bp->rx_fc_out_tbl.ctx_id);
 371
 372         rc = bnxt_hwrm_ctx_rgtr(bp, bp->tx_fc_in_tbl.dma,
 373                                 &bp->tx_fc_in_tbl.ctx_id);
 374         if (rc)
 375                 return rc;
 376
 377         PMD_DRV_LOG(DEBUG,
 378                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 379                     " tx_fc_in_tbl.ctx_id = %d\n",
 380                     bp->tx_fc_in_tbl.va,
 381                     (void *)((uintptr_t)bp->tx_fc_in_tbl.dma),
 382                     bp->tx_fc_in_tbl.ctx_id);
 383
 384         rc = bnxt_hwrm_ctx_rgtr(bp, bp->tx_fc_out_tbl.dma,
 385                                 &bp->tx_fc_out_tbl.ctx_id);
 386         if (rc)
 387                 return rc;
 388
 389         PMD_DRV_LOG(DEBUG,
 390                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 391                     " tx_fc_out_tbl.ctx_id = %d\n",
 392                     bp->tx_fc_out_tbl.va,
 393                     (void *)((uintptr_t)bp->tx_fc_out_tbl.dma),
 394                     bp->tx_fc_out_tbl.ctx_id);
 395
 396         memset(bp->rx_fc_out_tbl.va, 0, bp->rx_fc_out_tbl.size);
 397         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 398                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 399                                        bp->rx_fc_out_tbl.ctx_id,
 400                                        bp->max_fc,
 401                                        true);
 402         if (rc)
 403                 return rc;
 404
 405         memset(bp->tx_fc_out_tbl.va, 0, bp->tx_fc_out_tbl.size);
 406         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 407                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 408                                        bp->tx_fc_out_tbl.ctx_id,
 409                                        bp->max_fc,
 410                                        true);
 411
 412         return rc;
 413 }
 414
 415 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 416                                   struct bnxt_ctx_mem_buf_info *ctx)
 417 {
 418         if (!ctx)
 419                 return -EINVAL;
 420
 421         ctx->va = rte_zmalloc(type, size, 0);
 422         if (ctx->va == NULL)
 423                 return -ENOMEM;
 424         rte_mem_lock_page(ctx->va);
 425         ctx->size = size;
 426         ctx->dma = rte_mem_virt2iova(ctx->va);
 427         if (ctx->dma == RTE_BAD_IOVA)
 428                 return -ENOMEM;
 429
 430         return 0;
 431 }
 432
 433 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 434 {
 435         struct rte_pci_device *pdev = bp->pdev;
 436         char type[RTE_MEMZONE_NAMESIZE];
 437         uint16_t max_fc;
 438         int rc = 0;
 439
 440         max_fc = bp->max_fc;
 441
 442         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 443                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 444         /* 4 bytes for each counter-id */
 445         rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 4, &bp->rx_fc_in_tbl);
 446         if (rc)
 447                 return rc;
 448
 449         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 450                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 451         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 452         rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 16, &bp->rx_fc_out_tbl);
 453         if (rc)
 454                 return rc;
 455
 456         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 457                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 458         /* 4 bytes for each counter-id */
 459         rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 4, &bp->tx_fc_in_tbl);
 460         if (rc)
 461                 return rc;
 462
 463         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 464                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 465         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 466         rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 16, &bp->tx_fc_out_tbl);
 467         if (rc)
 468                 return rc;
 469
 470         rc = bnxt_register_fc_ctx_mem(bp);
 471
 472         return rc;
 473 }
 474
 475 static int bnxt_init_ctx_mem(struct bnxt *bp)
 476 {
 477         int rc = 0;
 478
 479         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 480             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)))
 481                 return 0;
 482
 483         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->max_fc);
 484         if (rc)
 485                 return rc;
 486
 487         rc = bnxt_init_fc_ctx_mem(bp);
 488
 489         return rc;
 490 }
 491
 492 static int bnxt_init_chip(struct bnxt *bp)
 493 {
 494         struct rte_eth_link new;
 495         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 496         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 497         uint32_t intr_vector = 0;
 498         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 499         uint32_t vec = BNXT_MISC_VEC_ID;
 500         unsigned int i, j;
 501         int rc;
 502
 503         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 504                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 505                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 506                 bp->flags |= BNXT_FLAG_JUMBO;
 507         } else {
 508                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 509                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 510                 bp->flags &= ~BNXT_FLAG_JUMBO;
 511         }
 512
 513         /* THOR does not support ring groups.
 514          * But we will use the array to save RSS context IDs.
 515          */
 516         if (BNXT_CHIP_THOR(bp))
 517                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 518
 519         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 520         if (rc) {
 521                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 522                 goto err_out;
 523         }
 524
 525         rc = bnxt_alloc_hwrm_rings(bp);
 526         if (rc) {
 527                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 528                 goto err_out;
 529         }
 530
 531         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 532         if (rc) {
 533                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 534                 goto err_out;
 535         }
 536
 537         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 538                 goto skip_cosq_cfg;
 539
 540         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 541                 if (bp->rx_cos_queue[i].id != 0xff) {
 542                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 543
 544                         if (!vnic) {
 545                                 PMD_DRV_LOG(ERR,
 546                                             "Num pools more than FW profile\n");
 547                                 rc = -EINVAL;
 548                                 goto err_out;
 549                         }
 550                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 551                         bp->rx_cosq_cnt++;
 552                 }
 553         }
 554
 555 skip_cosq_cfg:
 556         rc = bnxt_mq_rx_configure(bp);
 557         if (rc) {
 558                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 559                 goto err_out;
 560         }
 561
 562         /* VNIC configuration */
 563         for (i = 0; i < bp->nr_vnics; i++) {
 564                 rc = bnxt_setup_one_vnic(bp, i);
 565                 if (rc)
 566                         goto err_out;
 567         }
 568
 569         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 570         if (rc) {
 571                 PMD_DRV_LOG(ERR,
 572                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 573                 goto err_out;
 574         }
 575
 576         /* check and configure queue intr-vector mapping */
 577         if ((rte_intr_cap_multiple(intr_handle) ||
 578              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 579             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 580                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 581                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 582                 if (intr_vector > bp->rx_cp_nr_rings) {
 583                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 584                                         bp->rx_cp_nr_rings);
 585                         return -ENOTSUP;
 586                 }
 587                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 588                 if (rc)
 589                         return rc;
 590         }
 591
 592         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 593                 intr_handle->intr_vec =
 594                         rte_zmalloc("intr_vec",
 595                                     bp->eth_dev->data->nb_rx_queues *
 596                                     sizeof(int), 0);
 597                 if (intr_handle->intr_vec == NULL) {
 598                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 599                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 600                         rc = -ENOMEM;
 601                         goto err_disable;
 602                 }
 603                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 604                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 605                          intr_handle->intr_vec, intr_handle->nb_efd,
 606                         intr_handle->max_intr);
 607                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 608                      queue_id++) {
 609                         intr_handle->intr_vec[queue_id] =
 610                                                         vec + BNXT_RX_VEC_START;
 611                         if (vec < base + intr_handle->nb_efd - 1)
 612                                 vec++;
 613                 }
 614         }
 615
 616         /* enable uio/vfio intr/eventfd mapping */
 617         rc = rte_intr_enable(intr_handle);
 618 #ifndef RTE_EXEC_ENV_FREEBSD
 619         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 620         if (rc)
 621                 goto err_free;
 622 #endif
 623
 624         rc = bnxt_get_hwrm_link_config(bp, &new);
 625         if (rc) {
 626                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 627                 goto err_free;
 628         }
 629
 630         if (!bp->link_info.link_up) {
 631                 rc = bnxt_set_hwrm_link_config(bp, true);
 632                 if (rc) {
 633                         PMD_DRV_LOG(ERR,
 634                                 "HWRM link config failure rc: %x\n", rc);
 635                         goto err_free;
 636                 }
 637         }
 638         bnxt_print_link_info(bp->eth_dev);
 639
 640         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 641         if (!bp->mark_table)
 642                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 643
 644         return 0;
 645
 646 err_free:
 647         rte_free(intr_handle->intr_vec);
 648 err_disable:
 649         rte_intr_efd_disable(intr_handle);
 650 err_out:
 651         /* Some of the error status returned by FW may not be from errno.h */
 652         if (rc > 0)
 653                 rc = -EIO;
 654
 655         return rc;
 656 }
 657
 658 static int bnxt_shutdown_nic(struct bnxt *bp)
 659 {
 660         bnxt_free_all_hwrm_resources(bp);
 661         bnxt_free_all_filters(bp);
 662         bnxt_free_all_vnics(bp);
 663         return 0;
 664 }
 665
 666 /*
 667  * Device configuration and status function
 668  */
 669
 670 static uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 671 {
 672         uint32_t link_speed = bp->link_info.support_speeds;
 673         uint32_t speed_capa = 0;
 674
 675         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 676                 speed_capa |= ETH_LINK_SPEED_100M;
 677         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 678                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 679         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 680                 speed_capa |= ETH_LINK_SPEED_1G;
 681         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 682                 speed_capa |= ETH_LINK_SPEED_2_5G;
 683         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 684                 speed_capa |= ETH_LINK_SPEED_10G;
 685         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 686                 speed_capa |= ETH_LINK_SPEED_20G;
 687         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 688                 speed_capa |= ETH_LINK_SPEED_25G;
 689         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 690                 speed_capa |= ETH_LINK_SPEED_40G;
 691         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 692                 speed_capa |= ETH_LINK_SPEED_50G;
 693         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 694                 speed_capa |= ETH_LINK_SPEED_100G;
 695
 696         if (bp->link_info.auto_mode == HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 697                 speed_capa |= ETH_LINK_SPEED_FIXED;
 698         else
 699                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 700
 701         return speed_capa;
 702 }
 703
 704 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 705                                 struct rte_eth_dev_info *dev_info)
 706 {
 707         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 708         struct bnxt *bp = eth_dev->data->dev_private;
 709         uint16_t max_vnics, i, j, vpool, vrxq;
 710         unsigned int max_rx_rings;
 711         int rc;
 712
 713         rc = is_bnxt_in_error(bp);
 714         if (rc)
 715                 return rc;
 716
 717         /* MAC Specifics */
 718         dev_info->max_mac_addrs = bp->max_l2_ctx;
 719         dev_info->max_hash_mac_addrs = 0;
 720
 721         /* PF/VF specifics */
 722         if (BNXT_PF(bp))
 723                 dev_info->max_vfs = pdev->max_vfs;
 724
 725         max_rx_rings = BNXT_MAX_RINGS(bp);
 726         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 727         dev_info->max_rx_queues = max_rx_rings;
 728         dev_info->max_tx_queues = max_rx_rings;
 729         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 730         dev_info->hash_key_size = 40;
 731         max_vnics = bp->max_vnics;
 732
 733         /* MTU specifics */
 734         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 735         dev_info->max_mtu = BNXT_MAX_MTU;
 736
 737         /* Fast path specifics */
 738         dev_info->min_rx_bufsize = 1;
 739         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 740
 741         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 742         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 743                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 744         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 745         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 746
 747         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 748
 749         /* *INDENT-OFF* */
 750         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 751                 .rx_thresh = {
 752                         .pthresh = 8,
 753                         .hthresh = 8,
 754                         .wthresh = 0,
 755                 },
 756                 .rx_free_thresh = 32,
 757                 /* If no descriptors available, pkts are dropped by default */
 758                 .rx_drop_en = 1,
 759         };
 760
 761         dev_info->default_txconf = (struct rte_eth_txconf) {
 762                 .tx_thresh = {
 763                         .pthresh = 32,
 764                         .hthresh = 0,
 765                         .wthresh = 0,
 766                 },
 767                 .tx_free_thresh = 32,
 768                 .tx_rs_thresh = 32,
 769         };
 770         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 771
 772         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 773         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 774         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 775         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 776         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 777
 778         /* *INDENT-ON* */
 779
 780         /*
 781          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 782          *       need further investigation.
 783          */
 784
 785         /* VMDq resources */
 786         vpool = 64; /* ETH_64_POOLS */
 787         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 788         for (i = 0; i < 4; vpool >>= 1, i++) {
 789                 if (max_vnics > vpool) {
 790                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 791                                 if (dev_info->max_rx_queues > vrxq) {
 792                                         if (vpool > vrxq)
 793                                                 vpool = vrxq;
 794                                         goto found;
 795                                 }
 796                         }
 797                         /* Not enough resources to support VMDq */
 798                         break;
 799                 }
 800         }
 801         /* Not enough resources to support VMDq */
 802         vpool = 0;
 803         vrxq = 0;
 804 found:
 805         dev_info->max_vmdq_pools = vpool;
 806         dev_info->vmdq_queue_num = vrxq;
 807
 808         dev_info->vmdq_pool_base = 0;
 809         dev_info->vmdq_queue_base = 0;
 810
 811         return 0;
 812 }
 813
 814 /* Configure the device based on the configuration provided */
 815 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 816 {
 817         struct bnxt *bp = eth_dev->data->dev_private;
 818         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 819         int rc;
 820
 821         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 822         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 823         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 824         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 825
 826         rc = is_bnxt_in_error(bp);
 827         if (rc)
 828                 return rc;
 829
 830         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 831                 rc = bnxt_hwrm_check_vf_rings(bp);
 832                 if (rc) {
 833                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 834                         return -ENOSPC;
 835                 }
 836
 837                 /* If a resource has already been allocated - in this case
 838                  * it is the async completion ring, free it. Reallocate it after
 839                  * resource reservation. This will ensure the resource counts
 840                  * are calculated correctly.
 841                  */
 842
 843                 pthread_mutex_lock(&bp->def_cp_lock);
 844
 845                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 846                         bnxt_disable_int(bp);
 847                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 848                 }
 849
 850                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 851                 if (rc) {
 852                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 853                         pthread_mutex_unlock(&bp->def_cp_lock);
 854                         return -ENOSPC;
 855                 }
 856
 857                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 858                         rc = bnxt_alloc_async_cp_ring(bp);
 859                         if (rc) {
 860                                 pthread_mutex_unlock(&bp->def_cp_lock);
 861                                 return rc;
 862                         }
 863                         bnxt_enable_int(bp);
 864                 }
 865
 866                 pthread_mutex_unlock(&bp->def_cp_lock);
 867         } else {
 868                 /* legacy driver needs to get updated values */
 869                 rc = bnxt_hwrm_func_qcaps(bp);
 870                 if (rc) {
 871                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 872                         return rc;
 873                 }
 874         }
 875
 876         /* Inherit new configurations */
 877         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 878             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 879             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 880                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 881             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 882             bp->max_stat_ctx)
 883                 goto resource_error;
 884
 885         if (BNXT_HAS_RING_GRPS(bp) &&
 886             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 887                 goto resource_error;
 888
 889         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 890             bp->max_vnics < eth_dev->data->nb_rx_queues)
 891                 goto resource_error;
 892
 893         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 894         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 895
 896         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
 897                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 898         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
 899
 900         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 901                 eth_dev->data->mtu =
 902                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 903                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 904                         BNXT_NUM_VLANS;
 905                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 906         }
 907         return 0;
 908
 909 resource_error:
 910         PMD_DRV_LOG(ERR,
 911                     "Insufficient resources to support requested config\n");
 912         PMD_DRV_LOG(ERR,
 913                     "Num Queues Requested: Tx %d, Rx %d\n",
 914                     eth_dev->data->nb_tx_queues,
 915                     eth_dev->data->nb_rx_queues);
 916         PMD_DRV_LOG(ERR,
 917                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 918                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 919                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 920         return -ENOSPC;
 921 }
 922
 923 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 924 {
 925         struct rte_eth_link *link = &eth_dev->data->dev_link;
 926
 927         if (link->link_status)
 928                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 929                         eth_dev->data->port_id,
 930                         (uint32_t)link->link_speed,
 931                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 932                         ("full-duplex") : ("half-duplex\n"));
 933         else
 934                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 935                         eth_dev->data->port_id);
 936 }
 937
 938 /*
 939  * Determine whether the current configuration requires support for scattered
 940  * receive; return 1 if scattered receive is required and 0 if not.
 941  */
 942 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 943 {
 944         uint16_t buf_size;
 945         int i;
 946
 947         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
 948                 return 1;
 949
 950         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 951                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 952
 953                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 954                                       RTE_PKTMBUF_HEADROOM);
 955                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 956                         return 1;
 957         }
 958         return 0;
 959 }
 960
 961 static eth_rx_burst_t
 962 bnxt_receive_function(struct rte_eth_dev *eth_dev)
 963 {
 964         struct bnxt *bp = eth_dev->data->dev_private;
 965
 966 #ifdef RTE_ARCH_X86
 967 #ifndef RTE_LIBRTE_IEEE1588
 968         /*
 969          * Vector mode receive can be enabled only if scatter rx is not
 970          * in use and rx offloads are limited to VLAN stripping and
 971          * CRC stripping.
 972          */
 973         if (!eth_dev->data->scattered_rx &&
 974             !(eth_dev->data->dev_conf.rxmode.offloads &
 975               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 976                 DEV_RX_OFFLOAD_KEEP_CRC |
 977                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 978                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 979                 DEV_RX_OFFLOAD_UDP_CKSUM |
 980                 DEV_RX_OFFLOAD_TCP_CKSUM |
 981                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 982                 DEV_RX_OFFLOAD_RSS_HASH |
 983                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
 984             !bp->truflow) {
 985                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 986                             eth_dev->data->port_id);
 987                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
 988                 return bnxt_recv_pkts_vec;
 989         }
 990         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 991                     eth_dev->data->port_id);
 992         PMD_DRV_LOG(INFO,
 993                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 994                     eth_dev->data->port_id,
 995                     eth_dev->data->scattered_rx,
 996                     eth_dev->data->dev_conf.rxmode.offloads);
 997 #endif
 998 #endif
 999         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1000         return bnxt_recv_pkts;
1001 }
1002
1003 static eth_tx_burst_t
1004 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1005 {
1006 #ifdef RTE_ARCH_X86
1007 #ifndef RTE_LIBRTE_IEEE1588
1008         /*
1009          * Vector mode transmit can be enabled only if not using scatter rx
1010          * or tx offloads.
1011          */
1012         if (!eth_dev->data->scattered_rx &&
1013             !eth_dev->data->dev_conf.txmode.offloads) {
1014                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1015                             eth_dev->data->port_id);
1016                 return bnxt_xmit_pkts_vec;
1017         }
1018         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1019                     eth_dev->data->port_id);
1020         PMD_DRV_LOG(INFO,
1021                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1022                     eth_dev->data->port_id,
1023                     eth_dev->data->scattered_rx,
1024                     eth_dev->data->dev_conf.txmode.offloads);
1025 #endif
1026 #endif
1027         return bnxt_xmit_pkts;
1028 }
1029
1030 static int bnxt_handle_if_change_status(struct bnxt *bp)
1031 {
1032         int rc;
1033
1034         /* Since fw has undergone a reset and lost all contexts,
1035          * set fatal flag to not issue hwrm during cleanup
1036          */
1037         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1038         bnxt_uninit_resources(bp, true);
1039
1040         /* clear fatal flag so that re-init happens */
1041         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1042         rc = bnxt_init_resources(bp, true);
1043
1044         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1045
1046         return rc;
1047 }
1048
1049 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1050 {
1051         struct bnxt *bp = eth_dev->data->dev_private;
1052         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1053         int vlan_mask = 0;
1054         int rc;
1055
1056         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1057                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1058                 return -EINVAL;
1059         }
1060
1061         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1062                 PMD_DRV_LOG(ERR,
1063                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1064                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1065         }
1066
1067         rc = bnxt_hwrm_if_change(bp, 1);
1068         if (!rc) {
1069                 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1070                         rc = bnxt_handle_if_change_status(bp);
1071                         if (rc)
1072                                 return rc;
1073                 }
1074         }
1075         bnxt_enable_int(bp);
1076
1077         rc = bnxt_init_chip(bp);
1078         if (rc)
1079                 goto error;
1080
1081         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1082         eth_dev->data->dev_started = 1;
1083
1084         bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1085
1086         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1087                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1088         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1089                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1090         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1091         if (rc)
1092                 goto error;
1093
1094         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1095         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1096
1097         pthread_mutex_lock(&bp->def_cp_lock);
1098         bnxt_schedule_fw_health_check(bp);
1099         pthread_mutex_unlock(&bp->def_cp_lock);
1100
1101         if (bp->truflow)
1102                 bnxt_ulp_init(bp);
1103
1104         return 0;
1105
1106 error:
1107         bnxt_hwrm_if_change(bp, 0);
1108         bnxt_shutdown_nic(bp);
1109         bnxt_free_tx_mbufs(bp);
1110         bnxt_free_rx_mbufs(bp);
1111         eth_dev->data->dev_started = 0;
1112         return rc;
1113 }
1114
1115 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1116 {
1117         struct bnxt *bp = eth_dev->data->dev_private;
1118         int rc = 0;
1119
1120         if (!bp->link_info.link_up)
1121                 rc = bnxt_set_hwrm_link_config(bp, true);
1122         if (!rc)
1123                 eth_dev->data->dev_link.link_status = 1;
1124
1125         bnxt_print_link_info(eth_dev);
1126         return rc;
1127 }
1128
1129 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1130 {
1131         struct bnxt *bp = eth_dev->data->dev_private;
1132
1133         eth_dev->data->dev_link.link_status = 0;
1134         bnxt_set_hwrm_link_config(bp, false);
1135         bp->link_info.link_up = 0;
1136
1137         return 0;
1138 }
1139
1140 /* Unload the driver, release resources */
1141 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1142 {
1143         struct bnxt *bp = eth_dev->data->dev_private;
1144         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1145         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1146
1147         if (bp->truflow)
1148                 bnxt_ulp_deinit(bp);
1149
1150         eth_dev->data->dev_started = 0;
1151         /* Prevent crashes when queues are still in use */
1152         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1153         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1154
1155         bnxt_disable_int(bp);
1156
1157         /* disable uio/vfio intr/eventfd mapping */
1158         rte_intr_disable(intr_handle);
1159
1160         bnxt_cancel_fw_health_check(bp);
1161
1162         bnxt_dev_set_link_down_op(eth_dev);
1163
1164         /* Wait for link to be reset and the async notification to process.
1165          * During reset recovery, there is no need to wait and
1166          * VF/NPAR functions do not have privilege to change PHY config.
1167          */
1168         if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1169                 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1170
1171         /* Clean queue intr-vector mapping */
1172         rte_intr_efd_disable(intr_handle);
1173         if (intr_handle->intr_vec != NULL) {
1174                 rte_free(intr_handle->intr_vec);
1175                 intr_handle->intr_vec = NULL;
1176         }
1177
1178         bnxt_hwrm_port_clr_stats(bp);
1179         bnxt_free_tx_mbufs(bp);
1180         bnxt_free_rx_mbufs(bp);
1181         /* Process any remaining notifications in default completion queue */
1182         bnxt_int_handler(eth_dev);
1183         bnxt_shutdown_nic(bp);
1184         bnxt_hwrm_if_change(bp, 0);
1185
1186         rte_free(bp->mark_table);
1187         bp->mark_table = NULL;
1188
1189         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1190         bp->rx_cosq_cnt = 0;
1191 }
1192
1193 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1194 {
1195         struct bnxt *bp = eth_dev->data->dev_private;
1196
1197         /* cancel the recovery handler before remove dev */
1198         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1199         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1200         bnxt_cancel_fc_thread(bp);
1201
1202         if (eth_dev->data->dev_started)
1203                 bnxt_dev_stop_op(eth_dev);
1204
1205         bnxt_uninit_resources(bp, false);
1206
1207         eth_dev->dev_ops = NULL;
1208         eth_dev->rx_pkt_burst = NULL;
1209         eth_dev->tx_pkt_burst = NULL;
1210
1211         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1212         bp->tx_mem_zone = NULL;
1213         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1214         bp->rx_mem_zone = NULL;
1215
1216         rte_free(bp->pf.vf_info);
1217         bp->pf.vf_info = NULL;
1218
1219         rte_free(bp->grp_info);
1220         bp->grp_info = NULL;
1221 }
1222
1223 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1224                                     uint32_t index)
1225 {
1226         struct bnxt *bp = eth_dev->data->dev_private;
1227         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1228         struct bnxt_vnic_info *vnic;
1229         struct bnxt_filter_info *filter, *temp_filter;
1230         uint32_t i;
1231
1232         if (is_bnxt_in_error(bp))
1233                 return;
1234
1235         /*
1236          * Loop through all VNICs from the specified filter flow pools to
1237          * remove the corresponding MAC addr filter
1238          */
1239         for (i = 0; i < bp->nr_vnics; i++) {
1240                 if (!(pool_mask & (1ULL << i)))
1241                         continue;
1242
1243                 vnic = &bp->vnic_info[i];
1244                 filter = STAILQ_FIRST(&vnic->filter);
1245                 while (filter) {
1246                         temp_filter = STAILQ_NEXT(filter, next);
1247                         if (filter->mac_index == index) {
1248                                 STAILQ_REMOVE(&vnic->filter, filter,
1249                                                 bnxt_filter_info, next);
1250                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1251                                 bnxt_free_filter(bp, filter);
1252                         }
1253                         filter = temp_filter;
1254                 }
1255         }
1256 }
1257
1258 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1259                                struct rte_ether_addr *mac_addr, uint32_t index,
1260                                uint32_t pool)
1261 {
1262         struct bnxt_filter_info *filter;
1263         int rc = 0;
1264
1265         /* Attach requested MAC address to the new l2_filter */
1266         STAILQ_FOREACH(filter, &vnic->filter, next) {
1267                 if (filter->mac_index == index) {
1268                         PMD_DRV_LOG(DEBUG,
1269                                     "MAC addr already existed for pool %d\n",
1270                                     pool);
1271                         return 0;
1272                 }
1273         }
1274
1275         filter = bnxt_alloc_filter(bp);
1276         if (!filter) {
1277                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1278                 return -ENODEV;
1279         }
1280
1281         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1282          * if the MAC that's been programmed now is a different one, then,
1283          * copy that addr to filter->l2_addr
1284          */
1285         if (mac_addr)
1286                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1287         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1288
1289         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1290         if (!rc) {
1291                 filter->mac_index = index;
1292                 if (filter->mac_index == 0)
1293                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1294                 else
1295                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1296         } else {
1297                 bnxt_free_filter(bp, filter);
1298         }
1299
1300         return rc;
1301 }
1302
1303 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1304                                 struct rte_ether_addr *mac_addr,
1305                                 uint32_t index, uint32_t pool)
1306 {
1307         struct bnxt *bp = eth_dev->data->dev_private;
1308         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1309         int rc = 0;
1310
1311         rc = is_bnxt_in_error(bp);
1312         if (rc)
1313                 return rc;
1314
1315         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1316                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1317                 return -ENOTSUP;
1318         }
1319
1320         if (!vnic) {
1321                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1322                 return -EINVAL;
1323         }
1324
1325         /* Filter settings will get applied when port is started */
1326         if (!eth_dev->data->dev_started)
1327                 return 0;
1328
1329         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1330
1331         return rc;
1332 }
1333
1334 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1335                      bool exp_link_status)
1336 {
1337         int rc = 0;
1338         struct bnxt *bp = eth_dev->data->dev_private;
1339         struct rte_eth_link new;
1340         int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1341                   BNXT_LINK_DOWN_WAIT_CNT;
1342
1343         rc = is_bnxt_in_error(bp);
1344         if (rc)
1345                 return rc;
1346
1347         memset(&new, 0, sizeof(new));
1348         do {
1349                 /* Retrieve link info from hardware */
1350                 rc = bnxt_get_hwrm_link_config(bp, &new);
1351                 if (rc) {
1352                         new.link_speed = ETH_LINK_SPEED_100M;
1353                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1354                         PMD_DRV_LOG(ERR,
1355                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1356                         goto out;
1357                 }
1358
1359                 if (!wait_to_complete || new.link_status == exp_link_status)
1360                         break;
1361
1362                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1363         } while (cnt--);
1364
1365 out:
1366         /* Timed out or success */
1367         if (new.link_status != eth_dev->data->dev_link.link_status ||
1368         new.link_speed != eth_dev->data->dev_link.link_speed) {
1369                 rte_eth_linkstatus_set(eth_dev, &new);
1370
1371                 _rte_eth_dev_callback_process(eth_dev,
1372                                               RTE_ETH_EVENT_INTR_LSC,
1373                                               NULL);
1374
1375                 bnxt_print_link_info(eth_dev);
1376         }
1377
1378         return rc;
1379 }
1380
1381 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1382                                int wait_to_complete)
1383 {
1384         return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1385 }
1386
1387 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1388 {
1389         struct bnxt *bp = eth_dev->data->dev_private;
1390         struct bnxt_vnic_info *vnic;
1391         uint32_t old_flags;
1392         int rc;
1393
1394         rc = is_bnxt_in_error(bp);
1395         if (rc)
1396                 return rc;
1397
1398         /* Filter settings will get applied when port is started */
1399         if (!eth_dev->data->dev_started)
1400                 return 0;
1401
1402         if (bp->vnic_info == NULL)
1403                 return 0;
1404
1405         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1406
1407         old_flags = vnic->flags;
1408         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1409         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1410         if (rc != 0)
1411                 vnic->flags = old_flags;
1412
1413         return rc;
1414 }
1415
1416 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1417 {
1418         struct bnxt *bp = eth_dev->data->dev_private;
1419         struct bnxt_vnic_info *vnic;
1420         uint32_t old_flags;
1421         int rc;
1422
1423         rc = is_bnxt_in_error(bp);
1424         if (rc)
1425                 return rc;
1426
1427         /* Filter settings will get applied when port is started */
1428         if (!eth_dev->data->dev_started)
1429                 return 0;
1430
1431         if (bp->vnic_info == NULL)
1432                 return 0;
1433
1434         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1435
1436         old_flags = vnic->flags;
1437         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1438         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1439         if (rc != 0)
1440                 vnic->flags = old_flags;
1441
1442         return rc;
1443 }
1444
1445 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1446 {
1447         struct bnxt *bp = eth_dev->data->dev_private;
1448         struct bnxt_vnic_info *vnic;
1449         uint32_t old_flags;
1450         int rc;
1451
1452         rc = is_bnxt_in_error(bp);
1453         if (rc)
1454                 return rc;
1455
1456         /* Filter settings will get applied when port is started */
1457         if (!eth_dev->data->dev_started)
1458                 return 0;
1459
1460         if (bp->vnic_info == NULL)
1461                 return 0;
1462
1463         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1464
1465         old_flags = vnic->flags;
1466         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1467         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1468         if (rc != 0)
1469                 vnic->flags = old_flags;
1470
1471         return rc;
1472 }
1473
1474 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1475 {
1476         struct bnxt *bp = eth_dev->data->dev_private;
1477         struct bnxt_vnic_info *vnic;
1478         uint32_t old_flags;
1479         int rc;
1480
1481         rc = is_bnxt_in_error(bp);
1482         if (rc)
1483                 return rc;
1484
1485         /* Filter settings will get applied when port is started */
1486         if (!eth_dev->data->dev_started)
1487                 return 0;
1488
1489         if (bp->vnic_info == NULL)
1490                 return 0;
1491
1492         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1493
1494         old_flags = vnic->flags;
1495         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1496         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1497         if (rc != 0)
1498                 vnic->flags = old_flags;
1499
1500         return rc;
1501 }
1502
1503 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1504 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1505 {
1506         if (qid >= bp->rx_nr_rings)
1507                 return NULL;
1508
1509         return bp->eth_dev->data->rx_queues[qid];
1510 }
1511
1512 /* Return rxq corresponding to a given rss table ring/group ID. */
1513 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1514 {
1515         struct bnxt_rx_queue *rxq;
1516         unsigned int i;
1517
1518         if (!BNXT_HAS_RING_GRPS(bp)) {
1519                 for (i = 0; i < bp->rx_nr_rings; i++) {
1520                         rxq = bp->eth_dev->data->rx_queues[i];
1521                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1522                                 return rxq->index;
1523                 }
1524         } else {
1525                 for (i = 0; i < bp->rx_nr_rings; i++) {
1526                         if (bp->grp_info[i].fw_grp_id == fwr)
1527                                 return i;
1528                 }
1529         }
1530
1531         return INVALID_HW_RING_ID;
1532 }
1533
1534 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1535                             struct rte_eth_rss_reta_entry64 *reta_conf,
1536                             uint16_t reta_size)
1537 {
1538         struct bnxt *bp = eth_dev->data->dev_private;
1539         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1540         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1541         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1542         uint16_t idx, sft;
1543         int i, rc;
1544
1545         rc = is_bnxt_in_error(bp);
1546         if (rc)
1547                 return rc;
1548
1549         if (!vnic->rss_table)
1550                 return -EINVAL;
1551
1552         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1553                 return -EINVAL;
1554
1555         if (reta_size != tbl_size) {
1556                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1557                         "(%d) must equal the size supported by the hardware "
1558                         "(%d)\n", reta_size, tbl_size);
1559                 return -EINVAL;
1560         }
1561
1562         for (i = 0; i < reta_size; i++) {
1563                 struct bnxt_rx_queue *rxq;
1564
1565                 idx = i / RTE_RETA_GROUP_SIZE;
1566                 sft = i % RTE_RETA_GROUP_SIZE;
1567
1568                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1569                         continue;
1570
1571                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1572                 if (!rxq) {
1573                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1574                         return -EINVAL;
1575                 }
1576
1577                 if (BNXT_CHIP_THOR(bp)) {
1578                         vnic->rss_table[i * 2] =
1579                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1580                         vnic->rss_table[i * 2 + 1] =
1581                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1582                 } else {
1583                         vnic->rss_table[i] =
1584                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1585                 }
1586         }
1587
1588         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1589         return 0;
1590 }
1591
1592 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1593                               struct rte_eth_rss_reta_entry64 *reta_conf,
1594                               uint16_t reta_size)
1595 {
1596         struct bnxt *bp = eth_dev->data->dev_private;
1597         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1598         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1599         uint16_t idx, sft, i;
1600         int rc;
1601
1602         rc = is_bnxt_in_error(bp);
1603         if (rc)
1604                 return rc;
1605
1606         /* Retrieve from the default VNIC */
1607         if (!vnic)
1608                 return -EINVAL;
1609         if (!vnic->rss_table)
1610                 return -EINVAL;
1611
1612         if (reta_size != tbl_size) {
1613                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1614                         "(%d) must equal the size supported by the hardware "
1615                         "(%d)\n", reta_size, tbl_size);
1616                 return -EINVAL;
1617         }
1618
1619         for (idx = 0, i = 0; i < reta_size; i++) {
1620                 idx = i / RTE_RETA_GROUP_SIZE;
1621                 sft = i % RTE_RETA_GROUP_SIZE;
1622
1623                 if (reta_conf[idx].mask & (1ULL << sft)) {
1624                         uint16_t qid;
1625
1626                         if (BNXT_CHIP_THOR(bp))
1627                                 qid = bnxt_rss_to_qid(bp,
1628                                                       vnic->rss_table[i * 2]);
1629                         else
1630                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1631
1632                         if (qid == INVALID_HW_RING_ID) {
1633                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1634                                 return -EINVAL;
1635                         }
1636                         reta_conf[idx].reta[sft] = qid;
1637                 }
1638         }
1639
1640         return 0;
1641 }
1642
1643 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1644                                    struct rte_eth_rss_conf *rss_conf)
1645 {
1646         struct bnxt *bp = eth_dev->data->dev_private;
1647         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1648         struct bnxt_vnic_info *vnic;
1649         int rc;
1650
1651         rc = is_bnxt_in_error(bp);
1652         if (rc)
1653                 return rc;
1654
1655         /*
1656          * If RSS enablement were different than dev_configure,
1657          * then return -EINVAL
1658          */
1659         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1660                 if (!rss_conf->rss_hf)
1661                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1662         } else {
1663                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1664                         return -EINVAL;
1665         }
1666
1667         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1668         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1669
1670         /* Update the default RSS VNIC(s) */
1671         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1672         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1673
1674         /*
1675          * If hashkey is not specified, use the previously configured
1676          * hashkey
1677          */
1678         if (!rss_conf->rss_key)
1679                 goto rss_config;
1680
1681         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1682                 PMD_DRV_LOG(ERR,
1683                             "Invalid hashkey length, should be 16 bytes\n");
1684                 return -EINVAL;
1685         }
1686         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1687
1688 rss_config:
1689         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1690         return 0;
1691 }
1692
1693 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1694                                      struct rte_eth_rss_conf *rss_conf)
1695 {
1696         struct bnxt *bp = eth_dev->data->dev_private;
1697         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1698         int len, rc;
1699         uint32_t hash_types;
1700
1701         rc = is_bnxt_in_error(bp);
1702         if (rc)
1703                 return rc;
1704
1705         /* RSS configuration is the same for all VNICs */
1706         if (vnic && vnic->rss_hash_key) {
1707                 if (rss_conf->rss_key) {
1708                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1709                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1710                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1711                 }
1712
1713                 hash_types = vnic->hash_type;
1714                 rss_conf->rss_hf = 0;
1715                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1716                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1717                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1718                 }
1719                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1720                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1721                         hash_types &=
1722                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1723                 }
1724                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1725                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1726                         hash_types &=
1727                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1728                 }
1729                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1730                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1731                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1732                 }
1733                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1734                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1735                         hash_types &=
1736                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1737                 }
1738                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1739                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1740                         hash_types &=
1741                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1742                 }
1743                 if (hash_types) {
1744                         PMD_DRV_LOG(ERR,
1745                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1746                                 vnic->hash_type);
1747                         return -ENOTSUP;
1748                 }
1749         } else {
1750                 rss_conf->rss_hf = 0;
1751         }
1752         return 0;
1753 }
1754
1755 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1756                                struct rte_eth_fc_conf *fc_conf)
1757 {
1758         struct bnxt *bp = dev->data->dev_private;
1759         struct rte_eth_link link_info;
1760         int rc;
1761
1762         rc = is_bnxt_in_error(bp);
1763         if (rc)
1764                 return rc;
1765
1766         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1767         if (rc)
1768                 return rc;
1769
1770         memset(fc_conf, 0, sizeof(*fc_conf));
1771         if (bp->link_info.auto_pause)
1772                 fc_conf->autoneg = 1;
1773         switch (bp->link_info.pause) {
1774         case 0:
1775                 fc_conf->mode = RTE_FC_NONE;
1776                 break;
1777         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1778                 fc_conf->mode = RTE_FC_TX_PAUSE;
1779                 break;
1780         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1781                 fc_conf->mode = RTE_FC_RX_PAUSE;
1782                 break;
1783         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1784                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1785                 fc_conf->mode = RTE_FC_FULL;
1786                 break;
1787         }
1788         return 0;
1789 }
1790
1791 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1792                                struct rte_eth_fc_conf *fc_conf)
1793 {
1794         struct bnxt *bp = dev->data->dev_private;
1795         int rc;
1796
1797         rc = is_bnxt_in_error(bp);
1798         if (rc)
1799                 return rc;
1800
1801         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1802                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1803                 return -ENOTSUP;
1804         }
1805
1806         switch (fc_conf->mode) {
1807         case RTE_FC_NONE:
1808                 bp->link_info.auto_pause = 0;
1809                 bp->link_info.force_pause = 0;
1810                 break;
1811         case RTE_FC_RX_PAUSE:
1812                 if (fc_conf->autoneg) {
1813                         bp->link_info.auto_pause =
1814                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1815                         bp->link_info.force_pause = 0;
1816                 } else {
1817                         bp->link_info.auto_pause = 0;
1818                         bp->link_info.force_pause =
1819                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1820                 }
1821                 break;
1822         case RTE_FC_TX_PAUSE:
1823                 if (fc_conf->autoneg) {
1824                         bp->link_info.auto_pause =
1825                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1826                         bp->link_info.force_pause = 0;
1827                 } else {
1828                         bp->link_info.auto_pause = 0;
1829                         bp->link_info.force_pause =
1830                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1831                 }
1832                 break;
1833         case RTE_FC_FULL:
1834                 if (fc_conf->autoneg) {
1835                         bp->link_info.auto_pause =
1836                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1837                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1838                         bp->link_info.force_pause = 0;
1839                 } else {
1840                         bp->link_info.auto_pause = 0;
1841                         bp->link_info.force_pause =
1842                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1843                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1844                 }
1845                 break;
1846         }
1847         return bnxt_set_hwrm_link_config(bp, true);
1848 }
1849
1850 /* Add UDP tunneling port */
1851 static int
1852 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1853                          struct rte_eth_udp_tunnel *udp_tunnel)
1854 {
1855         struct bnxt *bp = eth_dev->data->dev_private;
1856         uint16_t tunnel_type = 0;
1857         int rc = 0;
1858
1859         rc = is_bnxt_in_error(bp);
1860         if (rc)
1861                 return rc;
1862
1863         switch (udp_tunnel->prot_type) {
1864         case RTE_TUNNEL_TYPE_VXLAN:
1865                 if (bp->vxlan_port_cnt) {
1866                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1867                                 udp_tunnel->udp_port);
1868                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1869                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1870                                 return -ENOSPC;
1871                         }
1872                         bp->vxlan_port_cnt++;
1873                         return 0;
1874                 }
1875                 tunnel_type =
1876                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1877                 bp->vxlan_port_cnt++;
1878                 break;
1879         case RTE_TUNNEL_TYPE_GENEVE:
1880                 if (bp->geneve_port_cnt) {
1881                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1882                                 udp_tunnel->udp_port);
1883                         if (bp->geneve_port != udp_tunnel->udp_port) {
1884                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1885                                 return -ENOSPC;
1886                         }
1887                         bp->geneve_port_cnt++;
1888                         return 0;
1889                 }
1890                 tunnel_type =
1891                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1892                 bp->geneve_port_cnt++;
1893                 break;
1894         default:
1895                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1896                 return -ENOTSUP;
1897         }
1898         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1899                                              tunnel_type);
1900         return rc;
1901 }
1902
1903 static int
1904 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1905                          struct rte_eth_udp_tunnel *udp_tunnel)
1906 {
1907         struct bnxt *bp = eth_dev->data->dev_private;
1908         uint16_t tunnel_type = 0;
1909         uint16_t port = 0;
1910         int rc = 0;
1911
1912         rc = is_bnxt_in_error(bp);
1913         if (rc)
1914                 return rc;
1915
1916         switch (udp_tunnel->prot_type) {
1917         case RTE_TUNNEL_TYPE_VXLAN:
1918                 if (!bp->vxlan_port_cnt) {
1919                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1920                         return -EINVAL;
1921                 }
1922                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1923                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1924                                 udp_tunnel->udp_port, bp->vxlan_port);
1925                         return -EINVAL;
1926                 }
1927                 if (--bp->vxlan_port_cnt)
1928                         return 0;
1929
1930                 tunnel_type =
1931                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1932                 port = bp->vxlan_fw_dst_port_id;
1933                 break;
1934         case RTE_TUNNEL_TYPE_GENEVE:
1935                 if (!bp->geneve_port_cnt) {
1936                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1937                         return -EINVAL;
1938                 }
1939                 if (bp->geneve_port != udp_tunnel->udp_port) {
1940                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1941                                 udp_tunnel->udp_port, bp->geneve_port);
1942                         return -EINVAL;
1943                 }
1944                 if (--bp->geneve_port_cnt)
1945                         return 0;
1946
1947                 tunnel_type =
1948                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1949                 port = bp->geneve_fw_dst_port_id;
1950                 break;
1951         default:
1952                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1953                 return -ENOTSUP;
1954         }
1955
1956         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1957         if (!rc) {
1958                 if (tunnel_type ==
1959                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1960                         bp->vxlan_port = 0;
1961                 if (tunnel_type ==
1962                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1963                         bp->geneve_port = 0;
1964         }
1965         return rc;
1966 }
1967
1968 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1969 {
1970         struct bnxt_filter_info *filter;
1971         struct bnxt_vnic_info *vnic;
1972         int rc = 0;
1973         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1974
1975         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1976         filter = STAILQ_FIRST(&vnic->filter);
1977         while (filter) {
1978                 /* Search for this matching MAC+VLAN filter */
1979                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
1980                         /* Delete the filter */
1981                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1982                         if (rc)
1983                                 return rc;
1984                         STAILQ_REMOVE(&vnic->filter, filter,
1985                                       bnxt_filter_info, next);
1986                         bnxt_free_filter(bp, filter);
1987                         PMD_DRV_LOG(INFO,
1988                                     "Deleted vlan filter for %d\n",
1989                                     vlan_id);
1990                         return 0;
1991                 }
1992                 filter = STAILQ_NEXT(filter, next);
1993         }
1994         return -ENOENT;
1995 }
1996
1997 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1998 {
1999         struct bnxt_filter_info *filter;
2000         struct bnxt_vnic_info *vnic;
2001         int rc = 0;
2002         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2003                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2004         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2005
2006         /* Implementation notes on the use of VNIC in this command:
2007          *
2008          * By default, these filters belong to default vnic for the function.
2009          * Once these filters are set up, only destination VNIC can be modified.
2010          * If the destination VNIC is not specified in this command,
2011          * then the HWRM shall only create an l2 context id.
2012          */
2013
2014         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2015         filter = STAILQ_FIRST(&vnic->filter);
2016         /* Check if the VLAN has already been added */
2017         while (filter) {
2018                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2019                         return -EEXIST;
2020
2021                 filter = STAILQ_NEXT(filter, next);
2022         }
2023
2024         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2025          * command to create MAC+VLAN filter with the right flags, enables set.
2026          */
2027         filter = bnxt_alloc_filter(bp);
2028         if (!filter) {
2029                 PMD_DRV_LOG(ERR,
2030                             "MAC/VLAN filter alloc failed\n");
2031                 return -ENOMEM;
2032         }
2033         /* MAC + VLAN ID filter */
2034         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2035          * untagged packets are received
2036          *
2037          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2038          * packets and only the programmed vlan's packets are received
2039          */
2040         filter->l2_ivlan = vlan_id;
2041         filter->l2_ivlan_mask = 0x0FFF;
2042         filter->enables |= en;
2043         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2044
2045         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2046         if (rc) {
2047                 /* Free the newly allocated filter as we were
2048                  * not able to create the filter in hardware.
2049                  */
2050                 bnxt_free_filter(bp, filter);
2051                 return rc;
2052         }
2053
2054         filter->mac_index = 0;
2055         /* Add this new filter to the list */
2056         if (vlan_id == 0)
2057                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2058         else
2059                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2060
2061         PMD_DRV_LOG(INFO,
2062                     "Added Vlan filter for %d\n", vlan_id);
2063         return rc;
2064 }
2065
2066 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2067                 uint16_t vlan_id, int on)
2068 {
2069         struct bnxt *bp = eth_dev->data->dev_private;
2070         int rc;
2071
2072         rc = is_bnxt_in_error(bp);
2073         if (rc)
2074                 return rc;
2075
2076         /* These operations apply to ALL existing MAC/VLAN filters */
2077         if (on)
2078                 return bnxt_add_vlan_filter(bp, vlan_id);
2079         else
2080                 return bnxt_del_vlan_filter(bp, vlan_id);
2081 }
2082
2083 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2084                                     struct bnxt_vnic_info *vnic)
2085 {
2086         struct bnxt_filter_info *filter;
2087         int rc;
2088
2089         filter = STAILQ_FIRST(&vnic->filter);
2090         while (filter) {
2091                 if (filter->mac_index == 0 &&
2092                     !memcmp(filter->l2_addr, bp->mac_addr,
2093                             RTE_ETHER_ADDR_LEN)) {
2094                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2095                         if (!rc) {
2096                                 STAILQ_REMOVE(&vnic->filter, filter,
2097                                               bnxt_filter_info, next);
2098                                 bnxt_free_filter(bp, filter);
2099                         }
2100                         return rc;
2101                 }
2102                 filter = STAILQ_NEXT(filter, next);
2103         }
2104         return 0;
2105 }
2106
2107 static int
2108 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2109 {
2110         struct bnxt_vnic_info *vnic;
2111         unsigned int i;
2112         int rc;
2113
2114         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2115         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2116                 /* Remove any VLAN filters programmed */
2117                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2118                         bnxt_del_vlan_filter(bp, i);
2119
2120                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2121                 if (rc)
2122                         return rc;
2123         } else {
2124                 /* Default filter will allow packets that match the
2125                  * dest mac. So, it has to be deleted, otherwise, we
2126                  * will endup receiving vlan packets for which the
2127                  * filter is not programmed, when hw-vlan-filter
2128                  * configuration is ON
2129                  */
2130                 bnxt_del_dflt_mac_filter(bp, vnic);
2131                 /* This filter will allow only untagged packets */
2132                 bnxt_add_vlan_filter(bp, 0);
2133         }
2134         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2135                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2136
2137         return 0;
2138 }
2139
2140 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2141 {
2142         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2143         unsigned int i;
2144         int rc;
2145
2146         /* Destroy vnic filters and vnic */
2147         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2148             DEV_RX_OFFLOAD_VLAN_FILTER) {
2149                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2150                         bnxt_del_vlan_filter(bp, i);
2151         }
2152         bnxt_del_dflt_mac_filter(bp, vnic);
2153
2154         rc = bnxt_hwrm_vnic_free(bp, vnic);
2155         if (rc)
2156                 return rc;
2157
2158         rte_free(vnic->fw_grp_ids);
2159         vnic->fw_grp_ids = NULL;
2160
2161         return 0;
2162 }
2163
2164 static int
2165 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2166 {
2167         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2168         int rc;
2169
2170         /* Destroy, recreate and reconfigure the default vnic */
2171         rc = bnxt_free_one_vnic(bp, 0);
2172         if (rc)
2173                 return rc;
2174
2175         /* default vnic 0 */
2176         rc = bnxt_setup_one_vnic(bp, 0);
2177         if (rc)
2178                 return rc;
2179
2180         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2181             DEV_RX_OFFLOAD_VLAN_FILTER) {
2182                 rc = bnxt_add_vlan_filter(bp, 0);
2183                 if (rc)
2184                         return rc;
2185                 rc = bnxt_restore_vlan_filters(bp);
2186                 if (rc)
2187                         return rc;
2188         } else {
2189                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2190                 if (rc)
2191                         return rc;
2192         }
2193
2194         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2195         if (rc)
2196                 return rc;
2197
2198         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2199                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2200
2201         return rc;
2202 }
2203
2204 static int
2205 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2206 {
2207         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2208         struct bnxt *bp = dev->data->dev_private;
2209         int rc;
2210
2211         rc = is_bnxt_in_error(bp);
2212         if (rc)
2213                 return rc;
2214
2215         /* Filter settings will get applied when port is started */
2216         if (!dev->data->dev_started)
2217                 return 0;
2218
2219         if (mask & ETH_VLAN_FILTER_MASK) {
2220                 /* Enable or disable VLAN filtering */
2221                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2222                 if (rc)
2223                         return rc;
2224         }
2225
2226         if (mask & ETH_VLAN_STRIP_MASK) {
2227                 /* Enable or disable VLAN stripping */
2228                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2229                 if (rc)
2230                         return rc;
2231         }
2232
2233         if (mask & ETH_VLAN_EXTEND_MASK) {
2234                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2235                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2236                 else
2237                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2238         }
2239
2240         return 0;
2241 }
2242
2243 static int
2244 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2245                       uint16_t tpid)
2246 {
2247         struct bnxt *bp = dev->data->dev_private;
2248         int qinq = dev->data->dev_conf.rxmode.offloads &
2249                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2250
2251         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2252             vlan_type != ETH_VLAN_TYPE_OUTER) {
2253                 PMD_DRV_LOG(ERR,
2254                             "Unsupported vlan type.");
2255                 return -EINVAL;
2256         }
2257         if (!qinq) {
2258                 PMD_DRV_LOG(ERR,
2259                             "QinQ not enabled. Needs to be ON as we can "
2260                             "accelerate only outer vlan\n");
2261                 return -EINVAL;
2262         }
2263
2264         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2265                 switch (tpid) {
2266                 case RTE_ETHER_TYPE_QINQ:
2267                         bp->outer_tpid_bd =
2268                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2269                                 break;
2270                 case RTE_ETHER_TYPE_VLAN:
2271                         bp->outer_tpid_bd =
2272                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2273                                 break;
2274                 case 0x9100:
2275                         bp->outer_tpid_bd =
2276                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2277                                 break;
2278                 case 0x9200:
2279                         bp->outer_tpid_bd =
2280                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2281                                 break;
2282                 case 0x9300:
2283                         bp->outer_tpid_bd =
2284                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2285                                 break;
2286                 default:
2287                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2288                         return -EINVAL;
2289                 }
2290                 bp->outer_tpid_bd |= tpid;
2291                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2292         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2293                 PMD_DRV_LOG(ERR,
2294                             "Can accelerate only outer vlan in QinQ\n");
2295                 return -EINVAL;
2296         }
2297
2298         return 0;
2299 }
2300
2301 static int
2302 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2303                              struct rte_ether_addr *addr)
2304 {
2305         struct bnxt *bp = dev->data->dev_private;
2306         /* Default Filter is tied to VNIC 0 */
2307         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2308         int rc;
2309
2310         rc = is_bnxt_in_error(bp);
2311         if (rc)
2312                 return rc;
2313
2314         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2315                 return -EPERM;
2316
2317         if (rte_is_zero_ether_addr(addr))
2318                 return -EINVAL;
2319
2320         /* Filter settings will get applied when port is started */
2321         if (!dev->data->dev_started)
2322                 return 0;
2323
2324         /* Check if the requested MAC is already added */
2325         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2326                 return 0;
2327
2328         /* Destroy filter and re-create it */
2329         bnxt_del_dflt_mac_filter(bp, vnic);
2330
2331         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2332         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2333                 /* This filter will allow only untagged packets */
2334                 rc = bnxt_add_vlan_filter(bp, 0);
2335         } else {
2336                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2337         }
2338
2339         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2340         return rc;
2341 }
2342
2343 static int
2344 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2345                           struct rte_ether_addr *mc_addr_set,
2346                           uint32_t nb_mc_addr)
2347 {
2348         struct bnxt *bp = eth_dev->data->dev_private;
2349         char *mc_addr_list = (char *)mc_addr_set;
2350         struct bnxt_vnic_info *vnic;
2351         uint32_t off = 0, i = 0;
2352         int rc;
2353
2354         rc = is_bnxt_in_error(bp);
2355         if (rc)
2356                 return rc;
2357
2358         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2359
2360         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2361                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2362                 goto allmulti;
2363         }
2364
2365         /* TODO Check for Duplicate mcast addresses */
2366         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2367         for (i = 0; i < nb_mc_addr; i++) {
2368                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2369                         RTE_ETHER_ADDR_LEN);
2370                 off += RTE_ETHER_ADDR_LEN;
2371         }
2372
2373         vnic->mc_addr_cnt = i;
2374         if (vnic->mc_addr_cnt)
2375                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2376         else
2377                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2378
2379 allmulti:
2380         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2381 }
2382
2383 static int
2384 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2385 {
2386         struct bnxt *bp = dev->data->dev_private;
2387         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2388         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2389         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2390         int ret;
2391
2392         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2393                         fw_major, fw_minor, fw_updt);
2394
2395         ret += 1; /* add the size of '\0' */
2396         if (fw_size < (uint32_t)ret)
2397                 return ret;
2398         else
2399                 return 0;
2400 }
2401
2402 static void
2403 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2404         struct rte_eth_rxq_info *qinfo)
2405 {
2406         struct bnxt *bp = dev->data->dev_private;
2407         struct bnxt_rx_queue *rxq;
2408
2409         if (is_bnxt_in_error(bp))
2410                 return;
2411
2412         rxq = dev->data->rx_queues[queue_id];
2413
2414         qinfo->mp = rxq->mb_pool;
2415         qinfo->scattered_rx = dev->data->scattered_rx;
2416         qinfo->nb_desc = rxq->nb_rx_desc;
2417
2418         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2419         qinfo->conf.rx_drop_en = 0;
2420         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2421 }
2422
2423 static void
2424 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2425         struct rte_eth_txq_info *qinfo)
2426 {
2427         struct bnxt *bp = dev->data->dev_private;
2428         struct bnxt_tx_queue *txq;
2429
2430         if (is_bnxt_in_error(bp))
2431                 return;
2432
2433         txq = dev->data->tx_queues[queue_id];
2434
2435         qinfo->nb_desc = txq->nb_tx_desc;
2436
2437         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2438         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2439         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2440
2441         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2442         qinfo->conf.tx_rs_thresh = 0;
2443         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2444 }
2445
2446 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2447 {
2448         struct bnxt *bp = eth_dev->data->dev_private;
2449         uint32_t new_pkt_size;
2450         uint32_t rc = 0;
2451         uint32_t i;
2452
2453         rc = is_bnxt_in_error(bp);
2454         if (rc)
2455                 return rc;
2456
2457         /* Exit if receive queues are not configured yet */
2458         if (!eth_dev->data->nb_rx_queues)
2459                 return rc;
2460
2461         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2462                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2463
2464 #ifdef RTE_ARCH_X86
2465         /*
2466          * If vector-mode tx/rx is active, disallow any MTU change that would
2467          * require scattered receive support.
2468          */
2469         if (eth_dev->data->dev_started &&
2470             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2471              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2472             (new_pkt_size >
2473              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2474                 PMD_DRV_LOG(ERR,
2475                             "MTU change would require scattered rx support. ");
2476                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2477                 return -EINVAL;
2478         }
2479 #endif
2480
2481         if (new_mtu > RTE_ETHER_MTU) {
2482                 bp->flags |= BNXT_FLAG_JUMBO;
2483                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2484                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2485         } else {
2486                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2487                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2488                 bp->flags &= ~BNXT_FLAG_JUMBO;
2489         }
2490
2491         /* Is there a change in mtu setting? */
2492         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2493                 return rc;
2494
2495         for (i = 0; i < bp->nr_vnics; i++) {
2496                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2497                 uint16_t size = 0;
2498
2499                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2500                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2501                 if (rc)
2502                         break;
2503
2504                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2505                 size -= RTE_PKTMBUF_HEADROOM;
2506
2507                 if (size < new_mtu) {
2508                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2509                         if (rc)
2510                                 return rc;
2511                 }
2512         }
2513
2514         if (!rc)
2515                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2516
2517         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2518
2519         return rc;
2520 }
2521
2522 static int
2523 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2524 {
2525         struct bnxt *bp = dev->data->dev_private;
2526         uint16_t vlan = bp->vlan;
2527         int rc;
2528
2529         rc = is_bnxt_in_error(bp);
2530         if (rc)
2531                 return rc;
2532
2533         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2534                 PMD_DRV_LOG(ERR,
2535                         "PVID cannot be modified for this function\n");
2536                 return -ENOTSUP;
2537         }
2538         bp->vlan = on ? pvid : 0;
2539
2540         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2541         if (rc)
2542                 bp->vlan = vlan;
2543         return rc;
2544 }
2545
2546 static int
2547 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2548 {
2549         struct bnxt *bp = dev->data->dev_private;
2550         int rc;
2551
2552         rc = is_bnxt_in_error(bp);
2553         if (rc)
2554                 return rc;
2555
2556         return bnxt_hwrm_port_led_cfg(bp, true);
2557 }
2558
2559 static int
2560 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2561 {
2562         struct bnxt *bp = dev->data->dev_private;
2563         int rc;
2564
2565         rc = is_bnxt_in_error(bp);
2566         if (rc)
2567                 return rc;
2568
2569         return bnxt_hwrm_port_led_cfg(bp, false);
2570 }
2571
2572 static uint32_t
2573 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2574 {
2575         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2576         uint32_t desc = 0, raw_cons = 0, cons;
2577         struct bnxt_cp_ring_info *cpr;
2578         struct bnxt_rx_queue *rxq;
2579         struct rx_pkt_cmpl *rxcmp;
2580         int rc;
2581
2582         rc = is_bnxt_in_error(bp);
2583         if (rc)
2584                 return rc;
2585
2586         rxq = dev->data->rx_queues[rx_queue_id];
2587         cpr = rxq->cp_ring;
2588         raw_cons = cpr->cp_raw_cons;
2589
2590         while (1) {
2591                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2592                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2593                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2594
2595                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2596                         break;
2597                 } else {
2598                         raw_cons++;
2599                         desc++;
2600                 }
2601         }
2602
2603         return desc;
2604 }
2605
2606 static int
2607 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2608 {
2609         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2610         struct bnxt_rx_ring_info *rxr;
2611         struct bnxt_cp_ring_info *cpr;
2612         struct bnxt_sw_rx_bd *rx_buf;
2613         struct rx_pkt_cmpl *rxcmp;
2614         uint32_t cons, cp_cons;
2615         int rc;
2616
2617         if (!rxq)
2618                 return -EINVAL;
2619
2620         rc = is_bnxt_in_error(rxq->bp);
2621         if (rc)
2622                 return rc;
2623
2624         cpr = rxq->cp_ring;
2625         rxr = rxq->rx_ring;
2626
2627         if (offset >= rxq->nb_rx_desc)
2628                 return -EINVAL;
2629
2630         cons = RING_CMP(cpr->cp_ring_struct, offset);
2631         cp_cons = cpr->cp_raw_cons;
2632         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2633
2634         if (cons > cp_cons) {
2635                 if (CMPL_VALID(rxcmp, cpr->valid))
2636                         return RTE_ETH_RX_DESC_DONE;
2637         } else {
2638                 if (CMPL_VALID(rxcmp, !cpr->valid))
2639                         return RTE_ETH_RX_DESC_DONE;
2640         }
2641         rx_buf = &rxr->rx_buf_ring[cons];
2642         if (rx_buf->mbuf == NULL)
2643                 return RTE_ETH_RX_DESC_UNAVAIL;
2644
2645
2646         return RTE_ETH_RX_DESC_AVAIL;
2647 }
2648
2649 static int
2650 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2651 {
2652         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2653         struct bnxt_tx_ring_info *txr;
2654         struct bnxt_cp_ring_info *cpr;
2655         struct bnxt_sw_tx_bd *tx_buf;
2656         struct tx_pkt_cmpl *txcmp;
2657         uint32_t cons, cp_cons;
2658         int rc;
2659
2660         if (!txq)
2661                 return -EINVAL;
2662
2663         rc = is_bnxt_in_error(txq->bp);
2664         if (rc)
2665                 return rc;
2666
2667         cpr = txq->cp_ring;
2668         txr = txq->tx_ring;
2669
2670         if (offset >= txq->nb_tx_desc)
2671                 return -EINVAL;
2672
2673         cons = RING_CMP(cpr->cp_ring_struct, offset);
2674         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2675         cp_cons = cpr->cp_raw_cons;
2676
2677         if (cons > cp_cons) {
2678                 if (CMPL_VALID(txcmp, cpr->valid))
2679                         return RTE_ETH_TX_DESC_UNAVAIL;
2680         } else {
2681                 if (CMPL_VALID(txcmp, !cpr->valid))
2682                         return RTE_ETH_TX_DESC_UNAVAIL;
2683         }
2684         tx_buf = &txr->tx_buf_ring[cons];
2685         if (tx_buf->mbuf == NULL)
2686                 return RTE_ETH_TX_DESC_DONE;
2687
2688         return RTE_ETH_TX_DESC_FULL;
2689 }
2690
2691 static struct bnxt_filter_info *
2692 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2693                                 struct rte_eth_ethertype_filter *efilter,
2694                                 struct bnxt_vnic_info *vnic0,
2695                                 struct bnxt_vnic_info *vnic,
2696                                 int *ret)
2697 {
2698         struct bnxt_filter_info *mfilter = NULL;
2699         int match = 0;
2700         *ret = 0;
2701
2702         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2703                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2704                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2705                         " ethertype filter.", efilter->ether_type);
2706                 *ret = -EINVAL;
2707                 goto exit;
2708         }
2709         if (efilter->queue >= bp->rx_nr_rings) {
2710                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2711                 *ret = -EINVAL;
2712                 goto exit;
2713         }
2714
2715         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2716         vnic = &bp->vnic_info[efilter->queue];
2717         if (vnic == NULL) {
2718                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2719                 *ret = -EINVAL;
2720                 goto exit;
2721         }
2722
2723         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2724                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2725                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2726                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2727                              mfilter->flags ==
2728                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2729                              mfilter->ethertype == efilter->ether_type)) {
2730                                 match = 1;
2731                                 break;
2732                         }
2733                 }
2734         } else {
2735                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2736                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2737                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2738                              mfilter->ethertype == efilter->ether_type &&
2739                              mfilter->flags ==
2740                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2741                                 match = 1;
2742                                 break;
2743                         }
2744         }
2745
2746         if (match)
2747                 *ret = -EEXIST;
2748
2749 exit:
2750         return mfilter;
2751 }
2752
2753 static int
2754 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2755                         enum rte_filter_op filter_op,
2756                         void *arg)
2757 {
2758         struct bnxt *bp = dev->data->dev_private;
2759         struct rte_eth_ethertype_filter *efilter =
2760                         (struct rte_eth_ethertype_filter *)arg;
2761         struct bnxt_filter_info *bfilter, *filter1;
2762         struct bnxt_vnic_info *vnic, *vnic0;
2763         int ret;
2764
2765         if (filter_op == RTE_ETH_FILTER_NOP)
2766                 return 0;
2767
2768         if (arg == NULL) {
2769                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2770                             filter_op);
2771                 return -EINVAL;
2772         }
2773
2774         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2775         vnic = &bp->vnic_info[efilter->queue];
2776
2777         switch (filter_op) {
2778         case RTE_ETH_FILTER_ADD:
2779                 bnxt_match_and_validate_ether_filter(bp, efilter,
2780                                                         vnic0, vnic, &ret);
2781                 if (ret < 0)
2782                         return ret;
2783
2784                 bfilter = bnxt_get_unused_filter(bp);
2785                 if (bfilter == NULL) {
2786                         PMD_DRV_LOG(ERR,
2787                                 "Not enough resources for a new filter.\n");
2788                         return -ENOMEM;
2789                 }
2790                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2791                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2792                        RTE_ETHER_ADDR_LEN);
2793                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2794                        RTE_ETHER_ADDR_LEN);
2795                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2796                 bfilter->ethertype = efilter->ether_type;
2797                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2798
2799                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2800                 if (filter1 == NULL) {
2801                         ret = -EINVAL;
2802                         goto cleanup;
2803                 }
2804                 bfilter->enables |=
2805                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2806                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2807
2808                 bfilter->dst_id = vnic->fw_vnic_id;
2809
2810                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2811                         bfilter->flags =
2812                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2813                 }
2814
2815                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2816                 if (ret)
2817                         goto cleanup;
2818                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2819                 break;
2820         case RTE_ETH_FILTER_DELETE:
2821                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2822                                                         vnic0, vnic, &ret);
2823                 if (ret == -EEXIST) {
2824                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2825
2826                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2827                                       next);
2828                         bnxt_free_filter(bp, filter1);
2829                 } else if (ret == 0) {
2830                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2831                 }
2832                 break;
2833         default:
2834                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2835                 ret = -EINVAL;
2836                 goto error;
2837         }
2838         return ret;
2839 cleanup:
2840         bnxt_free_filter(bp, bfilter);
2841 error:
2842         return ret;
2843 }
2844
2845 static inline int
2846 parse_ntuple_filter(struct bnxt *bp,
2847                     struct rte_eth_ntuple_filter *nfilter,
2848                     struct bnxt_filter_info *bfilter)
2849 {
2850         uint32_t en = 0;
2851
2852         if (nfilter->queue >= bp->rx_nr_rings) {
2853                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2854                 return -EINVAL;
2855         }
2856
2857         switch (nfilter->dst_port_mask) {
2858         case UINT16_MAX:
2859                 bfilter->dst_port_mask = -1;
2860                 bfilter->dst_port = nfilter->dst_port;
2861                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2862                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2863                 break;
2864         default:
2865                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2866                 return -EINVAL;
2867         }
2868
2869         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2870         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2871
2872         switch (nfilter->proto_mask) {
2873         case UINT8_MAX:
2874                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2875                         bfilter->ip_protocol = 17;
2876                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2877                         bfilter->ip_protocol = 6;
2878                 else
2879                         return -EINVAL;
2880                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2881                 break;
2882         default:
2883                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2884                 return -EINVAL;
2885         }
2886
2887         switch (nfilter->dst_ip_mask) {
2888         case UINT32_MAX:
2889                 bfilter->dst_ipaddr_mask[0] = -1;
2890                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2891                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2892                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2893                 break;
2894         default:
2895                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2896                 return -EINVAL;
2897         }
2898
2899         switch (nfilter->src_ip_mask) {
2900         case UINT32_MAX:
2901                 bfilter->src_ipaddr_mask[0] = -1;
2902                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2903                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2904                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2905                 break;
2906         default:
2907                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2908                 return -EINVAL;
2909         }
2910
2911         switch (nfilter->src_port_mask) {
2912         case UINT16_MAX:
2913                 bfilter->src_port_mask = -1;
2914                 bfilter->src_port = nfilter->src_port;
2915                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2916                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2917                 break;
2918         default:
2919                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2920                 return -EINVAL;
2921         }
2922
2923         bfilter->enables = en;
2924         return 0;
2925 }
2926
2927 static struct bnxt_filter_info*
2928 bnxt_match_ntuple_filter(struct bnxt *bp,
2929                          struct bnxt_filter_info *bfilter,
2930                          struct bnxt_vnic_info **mvnic)
2931 {
2932         struct bnxt_filter_info *mfilter = NULL;
2933         int i;
2934
2935         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2936                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2937                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2938                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2939                             bfilter->src_ipaddr_mask[0] ==
2940                             mfilter->src_ipaddr_mask[0] &&
2941                             bfilter->src_port == mfilter->src_port &&
2942                             bfilter->src_port_mask == mfilter->src_port_mask &&
2943                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2944                             bfilter->dst_ipaddr_mask[0] ==
2945                             mfilter->dst_ipaddr_mask[0] &&
2946                             bfilter->dst_port == mfilter->dst_port &&
2947                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2948                             bfilter->flags == mfilter->flags &&
2949                             bfilter->enables == mfilter->enables) {
2950                                 if (mvnic)
2951                                         *mvnic = vnic;
2952                                 return mfilter;
2953                         }
2954                 }
2955         }
2956         return NULL;
2957 }
2958
2959 static int
2960 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2961                        struct rte_eth_ntuple_filter *nfilter,
2962                        enum rte_filter_op filter_op)
2963 {
2964         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2965         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2966         int ret;
2967
2968         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2969                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2970                 return -EINVAL;
2971         }
2972
2973         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2974                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2975                 return -EINVAL;
2976         }
2977
2978         bfilter = bnxt_get_unused_filter(bp);
2979         if (bfilter == NULL) {
2980                 PMD_DRV_LOG(ERR,
2981                         "Not enough resources for a new filter.\n");
2982                 return -ENOMEM;
2983         }
2984         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2985         if (ret < 0)
2986                 goto free_filter;
2987
2988         vnic = &bp->vnic_info[nfilter->queue];
2989         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2990         filter1 = STAILQ_FIRST(&vnic0->filter);
2991         if (filter1 == NULL) {
2992                 ret = -EINVAL;
2993                 goto free_filter;
2994         }
2995
2996         bfilter->dst_id = vnic->fw_vnic_id;
2997         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2998         bfilter->enables |=
2999                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3000         bfilter->ethertype = 0x800;
3001         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3002
3003         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3004
3005         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3006             bfilter->dst_id == mfilter->dst_id) {
3007                 PMD_DRV_LOG(ERR, "filter exists.\n");
3008                 ret = -EEXIST;
3009                 goto free_filter;
3010         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3011                    bfilter->dst_id != mfilter->dst_id) {
3012                 mfilter->dst_id = vnic->fw_vnic_id;
3013                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3014                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3015                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3016                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3017                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3018                 goto free_filter;
3019         }
3020         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3021                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3022                 ret = -ENOENT;
3023                 goto free_filter;
3024         }
3025
3026         if (filter_op == RTE_ETH_FILTER_ADD) {
3027                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3028                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3029                 if (ret)
3030                         goto free_filter;
3031                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3032         } else {
3033                 if (mfilter == NULL) {
3034                         /* This should not happen. But for Coverity! */
3035                         ret = -ENOENT;
3036                         goto free_filter;
3037                 }
3038                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3039
3040                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3041                 bnxt_free_filter(bp, mfilter);
3042                 bnxt_free_filter(bp, bfilter);
3043         }
3044
3045         return 0;
3046 free_filter:
3047         bnxt_free_filter(bp, bfilter);
3048         return ret;
3049 }
3050
3051 static int
3052 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3053                         enum rte_filter_op filter_op,
3054                         void *arg)
3055 {
3056         struct bnxt *bp = dev->data->dev_private;
3057         int ret;
3058
3059         if (filter_op == RTE_ETH_FILTER_NOP)
3060                 return 0;
3061
3062         if (arg == NULL) {
3063                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3064                             filter_op);
3065                 return -EINVAL;
3066         }
3067
3068         switch (filter_op) {
3069         case RTE_ETH_FILTER_ADD:
3070                 ret = bnxt_cfg_ntuple_filter(bp,
3071                         (struct rte_eth_ntuple_filter *)arg,
3072                         filter_op);
3073                 break;
3074         case RTE_ETH_FILTER_DELETE:
3075                 ret = bnxt_cfg_ntuple_filter(bp,
3076                         (struct rte_eth_ntuple_filter *)arg,
3077                         filter_op);
3078                 break;
3079         default:
3080                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3081                 ret = -EINVAL;
3082                 break;
3083         }
3084         return ret;
3085 }
3086
3087 static int
3088 bnxt_parse_fdir_filter(struct bnxt *bp,
3089                        struct rte_eth_fdir_filter *fdir,
3090                        struct bnxt_filter_info *filter)
3091 {
3092         enum rte_fdir_mode fdir_mode =
3093                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3094         struct bnxt_vnic_info *vnic0, *vnic;
3095         struct bnxt_filter_info *filter1;
3096         uint32_t en = 0;
3097         int i;
3098
3099         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3100                 return -EINVAL;
3101
3102         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3103         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3104
3105         switch (fdir->input.flow_type) {
3106         case RTE_ETH_FLOW_IPV4:
3107         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3108                 /* FALLTHROUGH */
3109                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3110                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3111                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3112                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3113                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3114                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3115                 filter->ip_addr_type =
3116                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3117                 filter->src_ipaddr_mask[0] = 0xffffffff;
3118                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3119                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3120                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3121                 filter->ethertype = 0x800;
3122                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3123                 break;
3124         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3125                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3126                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3127                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3128                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3129                 filter->dst_port_mask = 0xffff;
3130                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3131                 filter->src_port_mask = 0xffff;
3132                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3133                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3134                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3135                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3136                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3137                 filter->ip_protocol = 6;
3138                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3139                 filter->ip_addr_type =
3140                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3141                 filter->src_ipaddr_mask[0] = 0xffffffff;
3142                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3143                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3144                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3145                 filter->ethertype = 0x800;
3146                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3147                 break;
3148         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3149                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3150                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3151                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3152                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3153                 filter->dst_port_mask = 0xffff;
3154                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3155                 filter->src_port_mask = 0xffff;
3156                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3157                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3158                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3159                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3160                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3161                 filter->ip_protocol = 17;
3162                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3163                 filter->ip_addr_type =
3164                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3165                 filter->src_ipaddr_mask[0] = 0xffffffff;
3166                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3167                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3168                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3169                 filter->ethertype = 0x800;
3170                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3171                 break;
3172         case RTE_ETH_FLOW_IPV6:
3173         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3174                 /* FALLTHROUGH */
3175                 filter->ip_addr_type =
3176                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3177                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3178                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3179                 rte_memcpy(filter->src_ipaddr,
3180                            fdir->input.flow.ipv6_flow.src_ip, 16);
3181                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3182                 rte_memcpy(filter->dst_ipaddr,
3183                            fdir->input.flow.ipv6_flow.dst_ip, 16);
3184                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3185                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3186                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3187                 memset(filter->src_ipaddr_mask, 0xff, 16);
3188                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3189                 filter->ethertype = 0x86dd;
3190                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3191                 break;
3192         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3193                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3194                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3195                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3196                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3197                 filter->dst_port_mask = 0xffff;
3198                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3199                 filter->src_port_mask = 0xffff;
3200                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3201                 filter->ip_addr_type =
3202                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3203                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3204                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3205                 rte_memcpy(filter->src_ipaddr,
3206                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3207                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3208                 rte_memcpy(filter->dst_ipaddr,
3209                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3210                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3211                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3212                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3213                 memset(filter->src_ipaddr_mask, 0xff, 16);
3214                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3215                 filter->ethertype = 0x86dd;
3216                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3217                 break;
3218         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3219                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3220                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3221                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3222                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3223                 filter->dst_port_mask = 0xffff;
3224                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3225                 filter->src_port_mask = 0xffff;
3226                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3227                 filter->ip_addr_type =
3228                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3229                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3230                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3231                 rte_memcpy(filter->src_ipaddr,
3232                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3233                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3234                 rte_memcpy(filter->dst_ipaddr,
3235                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3236                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3237                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3238                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3239                 memset(filter->src_ipaddr_mask, 0xff, 16);
3240                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3241                 filter->ethertype = 0x86dd;
3242                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3243                 break;
3244         case RTE_ETH_FLOW_L2_PAYLOAD:
3245                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3246                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3247                 break;
3248         case RTE_ETH_FLOW_VXLAN:
3249                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3250                         return -EINVAL;
3251                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3252                 filter->tunnel_type =
3253                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3254                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3255                 break;
3256         case RTE_ETH_FLOW_NVGRE:
3257                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3258                         return -EINVAL;
3259                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3260                 filter->tunnel_type =
3261                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3262                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3263                 break;
3264         case RTE_ETH_FLOW_UNKNOWN:
3265         case RTE_ETH_FLOW_RAW:
3266         case RTE_ETH_FLOW_FRAG_IPV4:
3267         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3268         case RTE_ETH_FLOW_FRAG_IPV6:
3269         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3270         case RTE_ETH_FLOW_IPV6_EX:
3271         case RTE_ETH_FLOW_IPV6_TCP_EX:
3272         case RTE_ETH_FLOW_IPV6_UDP_EX:
3273         case RTE_ETH_FLOW_GENEVE:
3274                 /* FALLTHROUGH */
3275         default:
3276                 return -EINVAL;
3277         }
3278
3279         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3280         vnic = &bp->vnic_info[fdir->action.rx_queue];
3281         if (vnic == NULL) {
3282                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3283                 return -EINVAL;
3284         }
3285
3286         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3287                 rte_memcpy(filter->dst_macaddr,
3288                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3289                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3290         }
3291
3292         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3293                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3294                 filter1 = STAILQ_FIRST(&vnic0->filter);
3295                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3296         } else {
3297                 filter->dst_id = vnic->fw_vnic_id;
3298                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3299                         if (filter->dst_macaddr[i] == 0x00)
3300                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3301                         else
3302                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3303         }
3304
3305         if (filter1 == NULL)
3306                 return -EINVAL;
3307
3308         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3309         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3310
3311         filter->enables = en;
3312
3313         return 0;
3314 }
3315
3316 static struct bnxt_filter_info *
3317 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3318                 struct bnxt_vnic_info **mvnic)
3319 {
3320         struct bnxt_filter_info *mf = NULL;
3321         int i;
3322
3323         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3324                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3325
3326                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3327                         if (mf->filter_type == nf->filter_type &&
3328                             mf->flags == nf->flags &&
3329                             mf->src_port == nf->src_port &&
3330                             mf->src_port_mask == nf->src_port_mask &&
3331                             mf->dst_port == nf->dst_port &&
3332                             mf->dst_port_mask == nf->dst_port_mask &&
3333                             mf->ip_protocol == nf->ip_protocol &&
3334                             mf->ip_addr_type == nf->ip_addr_type &&
3335                             mf->ethertype == nf->ethertype &&
3336                             mf->vni == nf->vni &&
3337                             mf->tunnel_type == nf->tunnel_type &&
3338                             mf->l2_ovlan == nf->l2_ovlan &&
3339                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3340                             mf->l2_ivlan == nf->l2_ivlan &&
3341                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3342                             !memcmp(mf->l2_addr, nf->l2_addr,
3343                                     RTE_ETHER_ADDR_LEN) &&
3344                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3345                                     RTE_ETHER_ADDR_LEN) &&
3346                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3347                                     RTE_ETHER_ADDR_LEN) &&
3348                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3349                                     RTE_ETHER_ADDR_LEN) &&
3350                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3351                                     sizeof(nf->src_ipaddr)) &&
3352                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3353                                     sizeof(nf->src_ipaddr_mask)) &&
3354                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3355                                     sizeof(nf->dst_ipaddr)) &&
3356                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3357                                     sizeof(nf->dst_ipaddr_mask))) {
3358                                 if (mvnic)
3359                                         *mvnic = vnic;
3360                                 return mf;
3361                         }
3362                 }
3363         }
3364         return NULL;
3365 }
3366
3367 static int
3368 bnxt_fdir_filter(struct rte_eth_dev *dev,
3369                  enum rte_filter_op filter_op,
3370                  void *arg)
3371 {
3372         struct bnxt *bp = dev->data->dev_private;
3373         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3374         struct bnxt_filter_info *filter, *match;
3375         struct bnxt_vnic_info *vnic, *mvnic;
3376         int ret = 0, i;
3377
3378         if (filter_op == RTE_ETH_FILTER_NOP)
3379                 return 0;
3380
3381         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3382                 return -EINVAL;
3383
3384         switch (filter_op) {
3385         case RTE_ETH_FILTER_ADD:
3386         case RTE_ETH_FILTER_DELETE:
3387                 /* FALLTHROUGH */
3388                 filter = bnxt_get_unused_filter(bp);
3389                 if (filter == NULL) {
3390                         PMD_DRV_LOG(ERR,
3391                                 "Not enough resources for a new flow.\n");
3392                         return -ENOMEM;
3393                 }
3394
3395                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3396                 if (ret != 0)
3397                         goto free_filter;
3398                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3399
3400                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3401                         vnic = &bp->vnic_info[0];
3402                 else
3403                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3404
3405                 match = bnxt_match_fdir(bp, filter, &mvnic);
3406                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3407                         if (match->dst_id == vnic->fw_vnic_id) {
3408                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3409                                 ret = -EEXIST;
3410                                 goto free_filter;
3411                         } else {
3412                                 match->dst_id = vnic->fw_vnic_id;
3413                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3414                                                                   match->dst_id,
3415                                                                   match);
3416                                 STAILQ_REMOVE(&mvnic->filter, match,
3417                                               bnxt_filter_info, next);
3418                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3419                                 PMD_DRV_LOG(ERR,
3420                                         "Filter with matching pattern exist\n");
3421                                 PMD_DRV_LOG(ERR,
3422                                         "Updated it to new destination q\n");
3423                                 goto free_filter;
3424                         }
3425                 }
3426                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3427                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3428                         ret = -ENOENT;
3429                         goto free_filter;
3430                 }
3431
3432                 if (filter_op == RTE_ETH_FILTER_ADD) {
3433                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3434                                                           filter->dst_id,
3435                                                           filter);
3436                         if (ret)
3437                                 goto free_filter;
3438                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3439                 } else {
3440                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3441                         STAILQ_REMOVE(&vnic->filter, match,
3442                                       bnxt_filter_info, next);
3443                         bnxt_free_filter(bp, match);
3444                         bnxt_free_filter(bp, filter);
3445                 }
3446                 break;
3447         case RTE_ETH_FILTER_FLUSH:
3448                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3449                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3450
3451                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3452                                 if (filter->filter_type ==
3453                                     HWRM_CFA_NTUPLE_FILTER) {
3454                                         ret =
3455                                         bnxt_hwrm_clear_ntuple_filter(bp,
3456                                                                       filter);
3457                                         STAILQ_REMOVE(&vnic->filter, filter,
3458                                                       bnxt_filter_info, next);
3459                                 }
3460                         }
3461                 }
3462                 return ret;
3463         case RTE_ETH_FILTER_UPDATE:
3464         case RTE_ETH_FILTER_STATS:
3465         case RTE_ETH_FILTER_INFO:
3466                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3467                 break;
3468         default:
3469                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3470                 ret = -EINVAL;
3471                 break;
3472         }
3473         return ret;
3474
3475 free_filter:
3476         bnxt_free_filter(bp, filter);
3477         return ret;
3478 }
3479
3480 static int
3481 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3482                     enum rte_filter_type filter_type,
3483                     enum rte_filter_op filter_op, void *arg)
3484 {
3485         struct bnxt *bp = dev->data->dev_private;
3486         int ret = 0;
3487
3488         ret = is_bnxt_in_error(dev->data->dev_private);
3489         if (ret)
3490                 return ret;
3491
3492         switch (filter_type) {
3493         case RTE_ETH_FILTER_TUNNEL:
3494                 PMD_DRV_LOG(ERR,
3495                         "filter type: %d: To be implemented\n", filter_type);
3496                 break;
3497         case RTE_ETH_FILTER_FDIR:
3498                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3499                 break;
3500         case RTE_ETH_FILTER_NTUPLE:
3501                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3502                 break;
3503         case RTE_ETH_FILTER_ETHERTYPE:
3504                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3505                 break;
3506         case RTE_ETH_FILTER_GENERIC:
3507                 if (filter_op != RTE_ETH_FILTER_GET)
3508                         return -EINVAL;
3509                 if (bp->truflow)
3510                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3511                 else
3512                         *(const void **)arg = &bnxt_flow_ops;
3513                 break;
3514         default:
3515                 PMD_DRV_LOG(ERR,
3516                         "Filter type (%d) not supported", filter_type);
3517                 ret = -EINVAL;
3518                 break;
3519         }
3520         return ret;
3521 }
3522
3523 static const uint32_t *
3524 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3525 {
3526         static const uint32_t ptypes[] = {
3527                 RTE_PTYPE_L2_ETHER_VLAN,
3528                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3529                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3530                 RTE_PTYPE_L4_ICMP,
3531                 RTE_PTYPE_L4_TCP,
3532                 RTE_PTYPE_L4_UDP,
3533                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3534                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3535                 RTE_PTYPE_INNER_L4_ICMP,
3536                 RTE_PTYPE_INNER_L4_TCP,
3537                 RTE_PTYPE_INNER_L4_UDP,
3538                 RTE_PTYPE_UNKNOWN
3539         };
3540
3541         if (!dev->rx_pkt_burst)
3542                 return NULL;
3543
3544         return ptypes;
3545 }
3546
3547 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3548                          int reg_win)
3549 {
3550         uint32_t reg_base = *reg_arr & 0xfffff000;
3551         uint32_t win_off;
3552         int i;
3553
3554         for (i = 0; i < count; i++) {
3555                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3556                         return -ERANGE;
3557         }
3558         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3559         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3560         return 0;
3561 }
3562
3563 static int bnxt_map_ptp_regs(struct bnxt *bp)
3564 {
3565         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3566         uint32_t *reg_arr;
3567         int rc, i;
3568
3569         reg_arr = ptp->rx_regs;
3570         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3571         if (rc)
3572                 return rc;
3573
3574         reg_arr = ptp->tx_regs;
3575         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3576         if (rc)
3577                 return rc;
3578
3579         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3580                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3581
3582         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3583                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3584
3585         return 0;
3586 }
3587
3588 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3589 {
3590         rte_write32(0, (uint8_t *)bp->bar0 +
3591                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3592         rte_write32(0, (uint8_t *)bp->bar0 +
3593                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3594 }
3595
3596 static uint64_t bnxt_cc_read(struct bnxt *bp)
3597 {
3598         uint64_t ns;
3599
3600         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3601                               BNXT_GRCPF_REG_SYNC_TIME));
3602         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3603                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3604         return ns;
3605 }
3606
3607 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3608 {
3609         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3610         uint32_t fifo;
3611
3612         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3613                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3614         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3615                 return -EAGAIN;
3616
3617         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3618                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3619         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3620                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3621         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3622                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3623
3624         return 0;
3625 }
3626
3627 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3628 {
3629         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3630         struct bnxt_pf_info *pf = &bp->pf;
3631         uint16_t port_id;
3632         uint32_t fifo;
3633
3634         if (!ptp)
3635                 return -ENODEV;
3636
3637         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3638                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3639         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3640                 return -EAGAIN;
3641
3642         port_id = pf->port_id;
3643         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3644                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3645
3646         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3647                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3648         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3649 /*              bnxt_clr_rx_ts(bp);       TBD  */
3650                 return -EBUSY;
3651         }
3652
3653         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3654                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3655         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3656                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3657
3658         return 0;
3659 }
3660
3661 static int
3662 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3663 {
3664         uint64_t ns;
3665         struct bnxt *bp = dev->data->dev_private;
3666         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3667
3668         if (!ptp)
3669                 return 0;
3670
3671         ns = rte_timespec_to_ns(ts);
3672         /* Set the timecounters to a new value. */
3673         ptp->tc.nsec = ns;
3674
3675         return 0;
3676 }
3677
3678 static int
3679 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3680 {
3681         struct bnxt *bp = dev->data->dev_private;
3682         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3683         uint64_t ns, systime_cycles = 0;
3684         int rc = 0;
3685
3686         if (!ptp)
3687                 return 0;
3688
3689         if (BNXT_CHIP_THOR(bp))
3690                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3691                                              &systime_cycles);
3692         else
3693                 systime_cycles = bnxt_cc_read(bp);
3694
3695         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3696         *ts = rte_ns_to_timespec(ns);
3697
3698         return rc;
3699 }
3700 static int
3701 bnxt_timesync_enable(struct rte_eth_dev *dev)
3702 {
3703         struct bnxt *bp = dev->data->dev_private;
3704         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3705         uint32_t shift = 0;
3706         int rc;
3707
3708         if (!ptp)
3709                 return 0;
3710
3711         ptp->rx_filter = 1;
3712         ptp->tx_tstamp_en = 1;
3713         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3714
3715         rc = bnxt_hwrm_ptp_cfg(bp);
3716         if (rc)
3717                 return rc;
3718
3719         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3720         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3721         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3722
3723         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3724         ptp->tc.cc_shift = shift;
3725         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3726
3727         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3728         ptp->rx_tstamp_tc.cc_shift = shift;
3729         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3730
3731         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3732         ptp->tx_tstamp_tc.cc_shift = shift;
3733         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3734
3735         if (!BNXT_CHIP_THOR(bp))
3736                 bnxt_map_ptp_regs(bp);
3737
3738         return 0;
3739 }
3740
3741 static int
3742 bnxt_timesync_disable(struct rte_eth_dev *dev)
3743 {
3744         struct bnxt *bp = dev->data->dev_private;
3745         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3746
3747         if (!ptp)
3748                 return 0;
3749
3750         ptp->rx_filter = 0;
3751         ptp->tx_tstamp_en = 0;
3752         ptp->rxctl = 0;
3753
3754         bnxt_hwrm_ptp_cfg(bp);
3755
3756         if (!BNXT_CHIP_THOR(bp))
3757                 bnxt_unmap_ptp_regs(bp);
3758
3759         return 0;
3760 }
3761
3762 static int
3763 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3764                                  struct timespec *timestamp,
3765                                  uint32_t flags __rte_unused)
3766 {
3767         struct bnxt *bp = dev->data->dev_private;
3768         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3769         uint64_t rx_tstamp_cycles = 0;
3770         uint64_t ns;
3771
3772         if (!ptp)
3773                 return 0;
3774
3775         if (BNXT_CHIP_THOR(bp))
3776                 rx_tstamp_cycles = ptp->rx_timestamp;
3777         else
3778                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3779
3780         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3781         *timestamp = rte_ns_to_timespec(ns);
3782         return  0;
3783 }
3784
3785 static int
3786 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3787                                  struct timespec *timestamp)
3788 {
3789         struct bnxt *bp = dev->data->dev_private;
3790         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3791         uint64_t tx_tstamp_cycles = 0;
3792         uint64_t ns;
3793         int rc = 0;
3794
3795         if (!ptp)
3796                 return 0;
3797
3798         if (BNXT_CHIP_THOR(bp))
3799                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3800                                              &tx_tstamp_cycles);
3801         else
3802                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3803
3804         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3805         *timestamp = rte_ns_to_timespec(ns);
3806
3807         return rc;
3808 }
3809
3810 static int
3811 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3812 {
3813         struct bnxt *bp = dev->data->dev_private;
3814         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3815
3816         if (!ptp)
3817                 return 0;
3818
3819         ptp->tc.nsec += delta;
3820
3821         return 0;
3822 }
3823
3824 static int
3825 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3826 {
3827         struct bnxt *bp = dev->data->dev_private;
3828         int rc;
3829         uint32_t dir_entries;
3830         uint32_t entry_length;
3831
3832         rc = is_bnxt_in_error(bp);
3833         if (rc)
3834                 return rc;
3835
3836         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3837                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3838                     bp->pdev->addr.devid, bp->pdev->addr.function);
3839
3840         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3841         if (rc != 0)
3842                 return rc;
3843
3844         return dir_entries * entry_length;
3845 }
3846
3847 static int
3848 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3849                 struct rte_dev_eeprom_info *in_eeprom)
3850 {
3851         struct bnxt *bp = dev->data->dev_private;
3852         uint32_t index;
3853         uint32_t offset;
3854         int rc;
3855
3856         rc = is_bnxt_in_error(bp);
3857         if (rc)
3858                 return rc;
3859
3860         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3861                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3862                     bp->pdev->addr.devid, bp->pdev->addr.function,
3863                     in_eeprom->offset, in_eeprom->length);
3864
3865         if (in_eeprom->offset == 0) /* special offset value to get directory */
3866                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3867                                                 in_eeprom->data);
3868
3869         index = in_eeprom->offset >> 24;
3870         offset = in_eeprom->offset & 0xffffff;
3871
3872         if (index != 0)
3873                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3874                                            in_eeprom->length, in_eeprom->data);
3875
3876         return 0;
3877 }
3878
3879 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3880 {
3881         switch (dir_type) {
3882         case BNX_DIR_TYPE_CHIMP_PATCH:
3883         case BNX_DIR_TYPE_BOOTCODE:
3884         case BNX_DIR_TYPE_BOOTCODE_2:
3885         case BNX_DIR_TYPE_APE_FW:
3886         case BNX_DIR_TYPE_APE_PATCH:
3887         case BNX_DIR_TYPE_KONG_FW:
3888         case BNX_DIR_TYPE_KONG_PATCH:
3889         case BNX_DIR_TYPE_BONO_FW:
3890         case BNX_DIR_TYPE_BONO_PATCH:
3891                 /* FALLTHROUGH */
3892                 return true;
3893         }
3894
3895         return false;
3896 }
3897
3898 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3899 {
3900         switch (dir_type) {
3901         case BNX_DIR_TYPE_AVS:
3902         case BNX_DIR_TYPE_EXP_ROM_MBA:
3903         case BNX_DIR_TYPE_PCIE:
3904         case BNX_DIR_TYPE_TSCF_UCODE:
3905         case BNX_DIR_TYPE_EXT_PHY:
3906         case BNX_DIR_TYPE_CCM:
3907         case BNX_DIR_TYPE_ISCSI_BOOT:
3908         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3909         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3910                 /* FALLTHROUGH */
3911                 return true;
3912         }
3913
3914         return false;
3915 }
3916
3917 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3918 {
3919         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3920                 bnxt_dir_type_is_other_exec_format(dir_type);
3921 }
3922
3923 static int
3924 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3925                 struct rte_dev_eeprom_info *in_eeprom)
3926 {
3927         struct bnxt *bp = dev->data->dev_private;
3928         uint8_t index, dir_op;
3929         uint16_t type, ext, ordinal, attr;
3930         int rc;
3931
3932         rc = is_bnxt_in_error(bp);
3933         if (rc)
3934                 return rc;
3935
3936         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3937                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3938                     bp->pdev->addr.devid, bp->pdev->addr.function,
3939                     in_eeprom->offset, in_eeprom->length);
3940
3941         if (!BNXT_PF(bp)) {
3942                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3943                 return -EINVAL;
3944         }
3945
3946         type = in_eeprom->magic >> 16;
3947
3948         if (type == 0xffff) { /* special value for directory operations */
3949                 index = in_eeprom->magic & 0xff;
3950                 dir_op = in_eeprom->magic >> 8;
3951                 if (index == 0)
3952                         return -EINVAL;
3953                 switch (dir_op) {
3954                 case 0x0e: /* erase */
3955                         if (in_eeprom->offset != ~in_eeprom->magic)
3956                                 return -EINVAL;
3957                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3958                 default:
3959                         return -EINVAL;
3960                 }
3961         }
3962
3963         /* Create or re-write an NVM item: */
3964         if (bnxt_dir_type_is_executable(type) == true)
3965                 return -EOPNOTSUPP;
3966         ext = in_eeprom->magic & 0xffff;
3967         ordinal = in_eeprom->offset >> 16;
3968         attr = in_eeprom->offset & 0xffff;
3969
3970         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3971                                      in_eeprom->data, in_eeprom->length);
3972 }
3973
3974 /*
3975  * Initialization
3976  */
3977
3978 static const struct eth_dev_ops bnxt_dev_ops = {
3979         .dev_infos_get = bnxt_dev_info_get_op,
3980         .dev_close = bnxt_dev_close_op,
3981         .dev_configure = bnxt_dev_configure_op,
3982         .dev_start = bnxt_dev_start_op,
3983         .dev_stop = bnxt_dev_stop_op,
3984         .dev_set_link_up = bnxt_dev_set_link_up_op,
3985         .dev_set_link_down = bnxt_dev_set_link_down_op,
3986         .stats_get = bnxt_stats_get_op,
3987         .stats_reset = bnxt_stats_reset_op,
3988         .rx_queue_setup = bnxt_rx_queue_setup_op,
3989         .rx_queue_release = bnxt_rx_queue_release_op,
3990         .tx_queue_setup = bnxt_tx_queue_setup_op,
3991         .tx_queue_release = bnxt_tx_queue_release_op,
3992         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3993         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3994         .reta_update = bnxt_reta_update_op,
3995         .reta_query = bnxt_reta_query_op,
3996         .rss_hash_update = bnxt_rss_hash_update_op,
3997         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3998         .link_update = bnxt_link_update_op,
3999         .promiscuous_enable = bnxt_promiscuous_enable_op,
4000         .promiscuous_disable = bnxt_promiscuous_disable_op,
4001         .allmulticast_enable = bnxt_allmulticast_enable_op,
4002         .allmulticast_disable = bnxt_allmulticast_disable_op,
4003         .mac_addr_add = bnxt_mac_addr_add_op,
4004         .mac_addr_remove = bnxt_mac_addr_remove_op,
4005         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4006         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4007         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4008         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4009         .vlan_filter_set = bnxt_vlan_filter_set_op,
4010         .vlan_offload_set = bnxt_vlan_offload_set_op,
4011         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4012         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4013         .mtu_set = bnxt_mtu_set_op,
4014         .mac_addr_set = bnxt_set_default_mac_addr_op,
4015         .xstats_get = bnxt_dev_xstats_get_op,
4016         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4017         .xstats_reset = bnxt_dev_xstats_reset_op,
4018         .fw_version_get = bnxt_fw_version_get,
4019         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4020         .rxq_info_get = bnxt_rxq_info_get_op,
4021         .txq_info_get = bnxt_txq_info_get_op,
4022         .dev_led_on = bnxt_dev_led_on_op,
4023         .dev_led_off = bnxt_dev_led_off_op,
4024         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4025         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4026         .rx_queue_count = bnxt_rx_queue_count_op,
4027         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
4028         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
4029         .rx_queue_start = bnxt_rx_queue_start,
4030         .rx_queue_stop = bnxt_rx_queue_stop,
4031         .tx_queue_start = bnxt_tx_queue_start,
4032         .tx_queue_stop = bnxt_tx_queue_stop,
4033         .filter_ctrl = bnxt_filter_ctrl_op,
4034         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4035         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4036         .get_eeprom           = bnxt_get_eeprom_op,
4037         .set_eeprom           = bnxt_set_eeprom_op,
4038         .timesync_enable      = bnxt_timesync_enable,
4039         .timesync_disable     = bnxt_timesync_disable,
4040         .timesync_read_time   = bnxt_timesync_read_time,
4041         .timesync_write_time   = bnxt_timesync_write_time,
4042         .timesync_adjust_time = bnxt_timesync_adjust_time,
4043         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4044         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4045 };
4046
4047 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4048 {
4049         uint32_t offset;
4050
4051         /* Only pre-map the reset GRC registers using window 3 */
4052         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4053                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4054
4055         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4056
4057         return offset;
4058 }
4059
4060 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4061 {
4062         struct bnxt_error_recovery_info *info = bp->recovery_info;
4063         uint32_t reg_base = 0xffffffff;
4064         int i;
4065
4066         /* Only pre-map the monitoring GRC registers using window 2 */
4067         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4068                 uint32_t reg = info->status_regs[i];
4069
4070                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4071                         continue;
4072
4073                 if (reg_base == 0xffffffff)
4074                         reg_base = reg & 0xfffff000;
4075                 if ((reg & 0xfffff000) != reg_base)
4076                         return -ERANGE;
4077
4078                 /* Use mask 0xffc as the Lower 2 bits indicates
4079                  * address space location
4080                  */
4081                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4082                                                 (reg & 0xffc);
4083         }
4084
4085         if (reg_base == 0xffffffff)
4086                 return 0;
4087
4088         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4089                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4090
4091         return 0;
4092 }
4093
4094 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4095 {
4096         struct bnxt_error_recovery_info *info = bp->recovery_info;
4097         uint32_t delay = info->delay_after_reset[index];
4098         uint32_t val = info->reset_reg_val[index];
4099         uint32_t reg = info->reset_reg[index];
4100         uint32_t type, offset;
4101
4102         type = BNXT_FW_STATUS_REG_TYPE(reg);
4103         offset = BNXT_FW_STATUS_REG_OFF(reg);
4104
4105         switch (type) {
4106         case BNXT_FW_STATUS_REG_TYPE_CFG:
4107                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4108                 break;
4109         case BNXT_FW_STATUS_REG_TYPE_GRC:
4110                 offset = bnxt_map_reset_regs(bp, offset);
4111                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4112                 break;
4113         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4114                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4115                 break;
4116         }
4117         /* wait on a specific interval of time until core reset is complete */
4118         if (delay)
4119                 rte_delay_ms(delay);
4120 }
4121
4122 static void bnxt_dev_cleanup(struct bnxt *bp)
4123 {
4124         bnxt_set_hwrm_link_config(bp, false);
4125         bp->link_info.link_up = 0;
4126         if (bp->eth_dev->data->dev_started)
4127                 bnxt_dev_stop_op(bp->eth_dev);
4128
4129         bnxt_uninit_resources(bp, true);
4130 }
4131
4132 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4133 {
4134         struct rte_eth_dev *dev = bp->eth_dev;
4135         struct rte_vlan_filter_conf *vfc;
4136         int vidx, vbit, rc;
4137         uint16_t vlan_id;
4138
4139         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4140                 vfc = &dev->data->vlan_filter_conf;
4141                 vidx = vlan_id / 64;
4142                 vbit = vlan_id % 64;
4143
4144                 /* Each bit corresponds to a VLAN id */
4145                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4146                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4147                         if (rc)
4148                                 return rc;
4149                 }
4150         }
4151
4152         return 0;
4153 }
4154
4155 static int bnxt_restore_mac_filters(struct bnxt *bp)
4156 {
4157         struct rte_eth_dev *dev = bp->eth_dev;
4158         struct rte_eth_dev_info dev_info;
4159         struct rte_ether_addr *addr;
4160         uint64_t pool_mask;
4161         uint32_t pool = 0;
4162         uint16_t i;
4163         int rc;
4164
4165         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
4166                 return 0;
4167
4168         rc = bnxt_dev_info_get_op(dev, &dev_info);
4169         if (rc)
4170                 return rc;
4171
4172         /* replay MAC address configuration */
4173         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4174                 addr = &dev->data->mac_addrs[i];
4175
4176                 /* skip zero address */
4177                 if (rte_is_zero_ether_addr(addr))
4178                         continue;
4179
4180                 pool = 0;
4181                 pool_mask = dev->data->mac_pool_sel[i];
4182
4183                 do {
4184                         if (pool_mask & 1ULL) {
4185                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4186                                 if (rc)
4187                                         return rc;
4188                         }
4189                         pool_mask >>= 1;
4190                         pool++;
4191                 } while (pool_mask);
4192         }
4193
4194         return 0;
4195 }
4196
4197 static int bnxt_restore_filters(struct bnxt *bp)
4198 {
4199         struct rte_eth_dev *dev = bp->eth_dev;
4200         int ret = 0;
4201
4202         if (dev->data->all_multicast) {
4203                 ret = bnxt_allmulticast_enable_op(dev);
4204                 if (ret)
4205                         return ret;
4206         }
4207         if (dev->data->promiscuous) {
4208                 ret = bnxt_promiscuous_enable_op(dev);
4209                 if (ret)
4210                         return ret;
4211         }
4212
4213         ret = bnxt_restore_mac_filters(bp);
4214         if (ret)
4215                 return ret;
4216
4217         ret = bnxt_restore_vlan_filters(bp);
4218         /* TODO restore other filters as well */
4219         return ret;
4220 }
4221
4222 static void bnxt_dev_recover(void *arg)
4223 {
4224         struct bnxt *bp = arg;
4225         int timeout = bp->fw_reset_max_msecs;
4226         int rc = 0;
4227
4228         /* Clear Error flag so that device re-init should happen */
4229         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4230
4231         do {
4232                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4233                 if (rc == 0)
4234                         break;
4235                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4236                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4237         } while (rc && timeout);
4238
4239         if (rc) {
4240                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4241                 goto err;
4242         }
4243
4244         rc = bnxt_init_resources(bp, true);
4245         if (rc) {
4246                 PMD_DRV_LOG(ERR,
4247                             "Failed to initialize resources after reset\n");
4248                 goto err;
4249         }
4250         /* clear reset flag as the device is initialized now */
4251         bp->flags &= ~BNXT_FLAG_FW_RESET;
4252
4253         rc = bnxt_dev_start_op(bp->eth_dev);
4254         if (rc) {
4255                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4256                 goto err_start;
4257         }
4258
4259         rc = bnxt_restore_filters(bp);
4260         if (rc)
4261                 goto err_start;
4262
4263         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4264         return;
4265 err_start:
4266         bnxt_dev_stop_op(bp->eth_dev);
4267 err:
4268         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4269         bnxt_uninit_resources(bp, false);
4270         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4271 }
4272
4273 void bnxt_dev_reset_and_resume(void *arg)
4274 {
4275         struct bnxt *bp = arg;
4276         int rc;
4277
4278         bnxt_dev_cleanup(bp);
4279
4280         bnxt_wait_for_device_shutdown(bp);
4281
4282         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4283                                bnxt_dev_recover, (void *)bp);
4284         if (rc)
4285                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4286 }
4287
4288 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4289 {
4290         struct bnxt_error_recovery_info *info = bp->recovery_info;
4291         uint32_t reg = info->status_regs[index];
4292         uint32_t type, offset, val = 0;
4293
4294         type = BNXT_FW_STATUS_REG_TYPE(reg);
4295         offset = BNXT_FW_STATUS_REG_OFF(reg);
4296
4297         switch (type) {
4298         case BNXT_FW_STATUS_REG_TYPE_CFG:
4299                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4300                 break;
4301         case BNXT_FW_STATUS_REG_TYPE_GRC:
4302                 offset = info->mapped_status_regs[index];
4303                 /* FALLTHROUGH */
4304         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4305                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4306                                        offset));
4307                 break;
4308         }
4309
4310         return val;
4311 }
4312
4313 static int bnxt_fw_reset_all(struct bnxt *bp)
4314 {
4315         struct bnxt_error_recovery_info *info = bp->recovery_info;
4316         uint32_t i;
4317         int rc = 0;
4318
4319         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4320                 /* Reset through master function driver */
4321                 for (i = 0; i < info->reg_array_cnt; i++)
4322                         bnxt_write_fw_reset_reg(bp, i);
4323                 /* Wait for time specified by FW after triggering reset */
4324                 rte_delay_ms(info->master_func_wait_period_after_reset);
4325         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4326                 /* Reset with the help of Kong processor */
4327                 rc = bnxt_hwrm_fw_reset(bp);
4328                 if (rc)
4329                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4330         }
4331
4332         return rc;
4333 }
4334
4335 static void bnxt_fw_reset_cb(void *arg)
4336 {
4337         struct bnxt *bp = arg;
4338         struct bnxt_error_recovery_info *info = bp->recovery_info;
4339         int rc = 0;
4340
4341         /* Only Master function can do FW reset */
4342         if (bnxt_is_master_func(bp) &&
4343             bnxt_is_recovery_enabled(bp)) {
4344                 rc = bnxt_fw_reset_all(bp);
4345                 if (rc) {
4346                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4347                         return;
4348                 }
4349         }
4350
4351         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4352          * EXCEPTION_FATAL_ASYNC event to all the functions
4353          * (including MASTER FUNC). After receiving this Async, all the active
4354          * drivers should treat this case as FW initiated recovery
4355          */
4356         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4357                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4358                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4359
4360                 /* To recover from error */
4361                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4362                                   (void *)bp);
4363         }
4364 }
4365
4366 /* Driver should poll FW heartbeat, reset_counter with the frequency
4367  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4368  * When the driver detects heartbeat stop or change in reset_counter,
4369  * it has to trigger a reset to recover from the error condition.
4370  * A “master PF” is the function who will have the privilege to
4371  * initiate the chimp reset. The master PF will be elected by the
4372  * firmware and will be notified through async message.
4373  */
4374 static void bnxt_check_fw_health(void *arg)
4375 {
4376         struct bnxt *bp = arg;
4377         struct bnxt_error_recovery_info *info = bp->recovery_info;
4378         uint32_t val = 0, wait_msec;
4379
4380         if (!info || !bnxt_is_recovery_enabled(bp) ||
4381             is_bnxt_in_error(bp))
4382                 return;
4383
4384         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4385         if (val == info->last_heart_beat)
4386                 goto reset;
4387
4388         info->last_heart_beat = val;
4389
4390         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4391         if (val != info->last_reset_counter)
4392                 goto reset;
4393
4394         info->last_reset_counter = val;
4395
4396         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4397                           bnxt_check_fw_health, (void *)bp);
4398
4399         return;
4400 reset:
4401         /* Stop DMA to/from device */
4402         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4403         bp->flags |= BNXT_FLAG_FW_RESET;
4404
4405         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4406
4407         if (bnxt_is_master_func(bp))
4408                 wait_msec = info->master_func_wait_period;
4409         else
4410                 wait_msec = info->normal_func_wait_period;
4411
4412         rte_eal_alarm_set(US_PER_MS * wait_msec,
4413                           bnxt_fw_reset_cb, (void *)bp);
4414 }
4415
4416 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4417 {
4418         uint32_t polling_freq;
4419
4420         if (!bnxt_is_recovery_enabled(bp))
4421                 return;
4422
4423         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4424                 return;
4425
4426         polling_freq = bp->recovery_info->driver_polling_freq;
4427
4428         rte_eal_alarm_set(US_PER_MS * polling_freq,
4429                           bnxt_check_fw_health, (void *)bp);
4430         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4431 }
4432
4433 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4434 {
4435         if (!bnxt_is_recovery_enabled(bp))
4436                 return;
4437
4438         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4439         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4440 }
4441
4442 static bool bnxt_vf_pciid(uint16_t device_id)
4443 {
4444         switch (device_id) {
4445         case BROADCOM_DEV_ID_57304_VF:
4446         case BROADCOM_DEV_ID_57406_VF:
4447         case BROADCOM_DEV_ID_5731X_VF:
4448         case BROADCOM_DEV_ID_5741X_VF:
4449         case BROADCOM_DEV_ID_57414_VF:
4450         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4451         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4452         case BROADCOM_DEV_ID_58802_VF:
4453         case BROADCOM_DEV_ID_57500_VF1:
4454         case BROADCOM_DEV_ID_57500_VF2:
4455                 /* FALLTHROUGH */
4456                 return true;
4457         default:
4458                 return false;
4459         }
4460 }
4461
4462 static bool bnxt_thor_device(uint16_t device_id)
4463 {
4464         switch (device_id) {
4465         case BROADCOM_DEV_ID_57508:
4466         case BROADCOM_DEV_ID_57504:
4467         case BROADCOM_DEV_ID_57502:
4468         case BROADCOM_DEV_ID_57508_MF1:
4469         case BROADCOM_DEV_ID_57504_MF1:
4470         case BROADCOM_DEV_ID_57502_MF1:
4471         case BROADCOM_DEV_ID_57508_MF2:
4472         case BROADCOM_DEV_ID_57504_MF2:
4473         case BROADCOM_DEV_ID_57502_MF2:
4474         case BROADCOM_DEV_ID_57500_VF1:
4475         case BROADCOM_DEV_ID_57500_VF2:
4476                 /* FALLTHROUGH */
4477                 return true;
4478         default:
4479                 return false;
4480         }
4481 }
4482
4483 bool bnxt_stratus_device(struct bnxt *bp)
4484 {
4485         uint16_t device_id = bp->pdev->id.device_id;
4486
4487         switch (device_id) {
4488         case BROADCOM_DEV_ID_STRATUS_NIC:
4489         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4490         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4491                 /* FALLTHROUGH */
4492                 return true;
4493         default:
4494                 return false;
4495         }
4496 }
4497
4498 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4499 {
4500         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4501         struct bnxt *bp = eth_dev->data->dev_private;
4502
4503         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4504         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4505         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4506         if (!bp->bar0 || !bp->doorbell_base) {
4507                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4508                 return -ENODEV;
4509         }
4510
4511         bp->eth_dev = eth_dev;
4512         bp->pdev = pci_dev;
4513
4514         return 0;
4515 }
4516
4517 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4518                                   struct bnxt_ctx_pg_info *ctx_pg,
4519                                   uint32_t mem_size,
4520                                   const char *suffix,
4521                                   uint16_t idx)
4522 {
4523         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4524         const struct rte_memzone *mz = NULL;
4525         char mz_name[RTE_MEMZONE_NAMESIZE];
4526         rte_iova_t mz_phys_addr;
4527         uint64_t valid_bits = 0;
4528         uint32_t sz;
4529         int i;
4530
4531         if (!mem_size)
4532                 return 0;
4533
4534         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4535                          BNXT_PAGE_SIZE;
4536         rmem->page_size = BNXT_PAGE_SIZE;
4537         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4538         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4539         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4540
4541         valid_bits = PTU_PTE_VALID;
4542
4543         if (rmem->nr_pages > 1) {
4544                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4545                          "bnxt_ctx_pg_tbl%s_%x_%d",
4546                          suffix, idx, bp->eth_dev->data->port_id);
4547                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4548                 mz = rte_memzone_lookup(mz_name);
4549                 if (!mz) {
4550                         mz = rte_memzone_reserve_aligned(mz_name,
4551                                                 rmem->nr_pages * 8,
4552                                                 SOCKET_ID_ANY,
4553                                                 RTE_MEMZONE_2MB |
4554                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4555                                                 RTE_MEMZONE_IOVA_CONTIG,
4556                                                 BNXT_PAGE_SIZE);
4557                         if (mz == NULL)
4558                                 return -ENOMEM;
4559                 }
4560
4561                 memset(mz->addr, 0, mz->len);
4562                 mz_phys_addr = mz->iova;
4563
4564                 rmem->pg_tbl = mz->addr;
4565                 rmem->pg_tbl_map = mz_phys_addr;
4566                 rmem->pg_tbl_mz = mz;
4567         }
4568
4569         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4570                  suffix, idx, bp->eth_dev->data->port_id);
4571         mz = rte_memzone_lookup(mz_name);
4572         if (!mz) {
4573                 mz = rte_memzone_reserve_aligned(mz_name,
4574                                                  mem_size,
4575                                                  SOCKET_ID_ANY,
4576                                                  RTE_MEMZONE_1GB |
4577                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4578                                                  RTE_MEMZONE_IOVA_CONTIG,
4579                                                  BNXT_PAGE_SIZE);
4580                 if (mz == NULL)
4581                         return -ENOMEM;
4582         }
4583
4584         memset(mz->addr, 0, mz->len);
4585         mz_phys_addr = mz->iova;
4586
4587         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4588                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4589                 rmem->dma_arr[i] = mz_phys_addr + sz;
4590
4591                 if (rmem->nr_pages > 1) {
4592                         if (i == rmem->nr_pages - 2 &&
4593                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4594                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4595                         else if (i == rmem->nr_pages - 1 &&
4596                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4597                                 valid_bits |= PTU_PTE_LAST;
4598
4599                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4600                                                            valid_bits);
4601                 }
4602         }
4603
4604         rmem->mz = mz;
4605         if (rmem->vmem_size)
4606                 rmem->vmem = (void **)mz->addr;
4607         rmem->dma_arr[0] = mz_phys_addr;
4608         return 0;
4609 }
4610
4611 static void bnxt_free_ctx_mem(struct bnxt *bp)
4612 {
4613         int i;
4614
4615         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4616                 return;
4617
4618         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4619         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4620         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4621         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4622         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4623         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4624         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4625         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4626         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4627         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4628         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4629
4630         for (i = 0; i < BNXT_MAX_Q; i++) {
4631                 if (bp->ctx->tqm_mem[i])
4632                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4633         }
4634
4635         rte_free(bp->ctx);
4636         bp->ctx = NULL;
4637 }
4638
4639 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4640
4641 #define min_t(type, x, y) ({                    \
4642         type __min1 = (x);                      \
4643         type __min2 = (y);                      \
4644         __min1 < __min2 ? __min1 : __min2; })
4645
4646 #define max_t(type, x, y) ({                    \
4647         type __max1 = (x);                      \
4648         type __max2 = (y);                      \
4649         __max1 > __max2 ? __max1 : __max2; })
4650
4651 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4652
4653 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4654 {
4655         struct bnxt_ctx_pg_info *ctx_pg;
4656         struct bnxt_ctx_mem_info *ctx;
4657         uint32_t mem_size, ena, entries;
4658         int i, rc;
4659
4660         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4661         if (rc) {
4662                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4663                 return rc;
4664         }
4665         ctx = bp->ctx;
4666         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4667                 return 0;
4668
4669         ctx_pg = &ctx->qp_mem;
4670         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4671         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4672         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4673         if (rc)
4674                 return rc;
4675
4676         ctx_pg = &ctx->srq_mem;
4677         ctx_pg->entries = ctx->srq_max_l2_entries;
4678         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4679         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4680         if (rc)
4681                 return rc;
4682
4683         ctx_pg = &ctx->cq_mem;
4684         ctx_pg->entries = ctx->cq_max_l2_entries;
4685         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4686         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4687         if (rc)
4688                 return rc;
4689
4690         ctx_pg = &ctx->vnic_mem;
4691         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4692                 ctx->vnic_max_ring_table_entries;
4693         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4694         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4695         if (rc)
4696                 return rc;
4697
4698         ctx_pg = &ctx->stat_mem;
4699         ctx_pg->entries = ctx->stat_max_entries;
4700         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4701         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4702         if (rc)
4703                 return rc;
4704
4705         entries = ctx->qp_max_l2_entries +
4706                   ctx->vnic_max_vnic_entries +
4707                   ctx->tqm_min_entries_per_ring;
4708         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4709         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4710                           ctx->tqm_max_entries_per_ring);
4711         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4712                 ctx_pg = ctx->tqm_mem[i];
4713                 /* use min tqm entries for now. */
4714                 ctx_pg->entries = entries;
4715                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4716                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4717                 if (rc)
4718                         return rc;
4719                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4720         }
4721
4722         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4723         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4724         if (rc)
4725                 PMD_DRV_LOG(ERR,
4726                             "Failed to configure context mem: rc = %d\n", rc);
4727         else
4728                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4729
4730         return rc;
4731 }
4732
4733 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4734 {
4735         struct rte_pci_device *pci_dev = bp->pdev;
4736         char mz_name[RTE_MEMZONE_NAMESIZE];
4737         const struct rte_memzone *mz = NULL;
4738         uint32_t total_alloc_len;
4739         rte_iova_t mz_phys_addr;
4740
4741         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4742                 return 0;
4743
4744         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4745                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4746                  pci_dev->addr.bus, pci_dev->addr.devid,
4747                  pci_dev->addr.function, "rx_port_stats");
4748         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4749         mz = rte_memzone_lookup(mz_name);
4750         total_alloc_len =
4751                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4752                                        sizeof(struct rx_port_stats_ext) + 512);
4753         if (!mz) {
4754                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4755                                          SOCKET_ID_ANY,
4756                                          RTE_MEMZONE_2MB |
4757                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4758                                          RTE_MEMZONE_IOVA_CONTIG);
4759                 if (mz == NULL)
4760                         return -ENOMEM;
4761         }
4762         memset(mz->addr, 0, mz->len);
4763         mz_phys_addr = mz->iova;
4764
4765         bp->rx_mem_zone = (const void *)mz;
4766         bp->hw_rx_port_stats = mz->addr;
4767         bp->hw_rx_port_stats_map = mz_phys_addr;
4768
4769         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4770                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4771                  pci_dev->addr.bus, pci_dev->addr.devid,
4772                  pci_dev->addr.function, "tx_port_stats");
4773         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4774         mz = rte_memzone_lookup(mz_name);
4775         total_alloc_len =
4776                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4777                                        sizeof(struct tx_port_stats_ext) + 512);
4778         if (!mz) {
4779                 mz = rte_memzone_reserve(mz_name,
4780                                          total_alloc_len,
4781                                          SOCKET_ID_ANY,
4782                                          RTE_MEMZONE_2MB |
4783                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4784                                          RTE_MEMZONE_IOVA_CONTIG);
4785                 if (mz == NULL)
4786                         return -ENOMEM;
4787         }
4788         memset(mz->addr, 0, mz->len);
4789         mz_phys_addr = mz->iova;
4790
4791         bp->tx_mem_zone = (const void *)mz;
4792         bp->hw_tx_port_stats = mz->addr;
4793         bp->hw_tx_port_stats_map = mz_phys_addr;
4794         bp->flags |= BNXT_FLAG_PORT_STATS;
4795
4796         /* Display extended statistics if FW supports it */
4797         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4798             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4799             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4800                 return 0;
4801
4802         bp->hw_rx_port_stats_ext = (void *)
4803                 ((uint8_t *)bp->hw_rx_port_stats +
4804                  sizeof(struct rx_port_stats));
4805         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4806                 sizeof(struct rx_port_stats);
4807         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4808
4809         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4810             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4811                 bp->hw_tx_port_stats_ext = (void *)
4812                         ((uint8_t *)bp->hw_tx_port_stats +
4813                          sizeof(struct tx_port_stats));
4814                 bp->hw_tx_port_stats_ext_map =
4815                         bp->hw_tx_port_stats_map +
4816                         sizeof(struct tx_port_stats);
4817                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4818         }
4819
4820         return 0;
4821 }
4822
4823 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4824 {
4825         struct bnxt *bp = eth_dev->data->dev_private;
4826         int rc = 0;
4827
4828         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4829                                                RTE_ETHER_ADDR_LEN *
4830                                                bp->max_l2_ctx,
4831                                                0);
4832         if (eth_dev->data->mac_addrs == NULL) {
4833                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4834                 return -ENOMEM;
4835         }
4836
4837         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4838                 if (BNXT_PF(bp))
4839                         return -EINVAL;
4840
4841                 /* Generate a random MAC address, if none was assigned by PF */
4842                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4843                 bnxt_eth_hw_addr_random(bp->mac_addr);
4844                 PMD_DRV_LOG(INFO,
4845                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4846                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4847                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4848
4849                 rc = bnxt_hwrm_set_mac(bp);
4850                 if (!rc)
4851                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4852                                RTE_ETHER_ADDR_LEN);
4853                 return rc;
4854         }
4855
4856         /* Copy the permanent MAC from the FUNC_QCAPS response */
4857         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4858         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4859
4860         return rc;
4861 }
4862
4863 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4864 {
4865         int rc = 0;
4866
4867         /* MAC is already configured in FW */
4868         if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4869                 return 0;
4870
4871         /* Restore the old MAC configured */
4872         rc = bnxt_hwrm_set_mac(bp);
4873         if (rc)
4874                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4875
4876         return rc;
4877 }
4878
4879 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4880 {
4881         if (!BNXT_PF(bp))
4882                 return;
4883
4884 #define ALLOW_FUNC(x)   \
4885         { \
4886                 uint32_t arg = (x); \
4887                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4888                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4889         }
4890
4891         /* Forward all requests if firmware is new enough */
4892         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4893              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4894             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4895                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4896         } else {
4897                 PMD_DRV_LOG(WARNING,
4898                             "Firmware too old for VF mailbox functionality\n");
4899                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4900         }
4901
4902         /*
4903          * The following are used for driver cleanup. If we disallow these,
4904          * VF drivers can't clean up cleanly.
4905          */
4906         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4907         ALLOW_FUNC(HWRM_VNIC_FREE);
4908         ALLOW_FUNC(HWRM_RING_FREE);
4909         ALLOW_FUNC(HWRM_RING_GRP_FREE);
4910         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4911         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4912         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4913         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4914         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4915 }
4916
4917 uint16_t
4918 bnxt_get_svif(uint16_t port_id, bool func_svif)
4919 {
4920         struct rte_eth_dev *eth_dev;
4921         struct bnxt *bp;
4922
4923         eth_dev = &rte_eth_devices[port_id];
4924         bp = eth_dev->data->dev_private;
4925
4926         return func_svif ? bp->func_svif : bp->port_svif;
4927 }
4928
4929 uint16_t
4930 bnxt_get_vnic_id(uint16_t port)
4931 {
4932         struct rte_eth_dev *eth_dev;
4933         struct bnxt_vnic_info *vnic;
4934         struct bnxt *bp;
4935
4936         eth_dev = &rte_eth_devices[port];
4937         bp = eth_dev->data->dev_private;
4938
4939         vnic = BNXT_GET_DEFAULT_VNIC(bp);
4940
4941         return vnic->fw_vnic_id;
4942 }
4943
4944 uint16_t
4945 bnxt_get_fw_func_id(uint16_t port)
4946 {
4947         struct rte_eth_dev *eth_dev;
4948         struct bnxt *bp;
4949
4950         eth_dev = &rte_eth_devices[port];
4951         bp = eth_dev->data->dev_private;
4952
4953         return bp->fw_fid;
4954 }
4955
4956 static int bnxt_init_fw(struct bnxt *bp)
4957 {
4958         uint16_t mtu;
4959         int rc = 0;
4960
4961         bp->fw_cap = 0;
4962
4963         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
4964         if (rc)
4965                 return rc;
4966
4967         rc = bnxt_hwrm_func_reset(bp);
4968         if (rc)
4969                 return -EIO;
4970
4971         rc = bnxt_hwrm_vnic_qcaps(bp);
4972         if (rc)
4973                 return rc;
4974
4975         rc = bnxt_hwrm_queue_qportcfg(bp);
4976         if (rc)
4977                 return rc;
4978
4979         /* Get the MAX capabilities for this function.
4980          * This function also allocates context memory for TQM rings and
4981          * informs the firmware about this allocated backing store memory.
4982          */
4983         rc = bnxt_hwrm_func_qcaps(bp);
4984         if (rc)
4985                 return rc;
4986
4987         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4988         if (rc)
4989                 return rc;
4990
4991         bnxt_hwrm_port_mac_qcfg(bp);
4992
4993         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4994         if (rc)
4995                 return rc;
4996
4997         /* Get the adapter error recovery support info */
4998         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4999         if (rc)
5000                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5001
5002         bnxt_hwrm_port_led_qcaps(bp);
5003
5004         return 0;
5005 }
5006
5007 static int
5008 bnxt_init_locks(struct bnxt *bp)
5009 {
5010         int err;
5011
5012         err = pthread_mutex_init(&bp->flow_lock, NULL);
5013         if (err) {
5014                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5015                 return err;
5016         }
5017
5018         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5019         if (err)
5020                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5021         return err;
5022 }
5023
5024 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5025 {
5026         int rc;
5027
5028         rc = bnxt_init_fw(bp);
5029         if (rc)
5030                 return rc;
5031
5032         if (!reconfig_dev) {
5033                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5034                 if (rc)
5035                         return rc;
5036         } else {
5037                 rc = bnxt_restore_dflt_mac(bp);
5038                 if (rc)
5039                         return rc;
5040         }
5041
5042         bnxt_config_vf_req_fwd(bp);
5043
5044         rc = bnxt_hwrm_func_driver_register(bp);
5045         if (rc) {
5046                 PMD_DRV_LOG(ERR, "Failed to register driver");
5047                 return -EBUSY;
5048         }
5049
5050         if (BNXT_PF(bp)) {
5051                 if (bp->pdev->max_vfs) {
5052                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5053                         if (rc) {
5054                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5055                                 return rc;
5056                         }
5057                 } else {
5058                         rc = bnxt_hwrm_allocate_pf_only(bp);
5059                         if (rc) {
5060                                 PMD_DRV_LOG(ERR,
5061                                             "Failed to allocate PF resources");
5062                                 return rc;
5063                         }
5064                 }
5065         }
5066
5067         rc = bnxt_alloc_mem(bp, reconfig_dev);
5068         if (rc)
5069                 return rc;
5070
5071         rc = bnxt_setup_int(bp);
5072         if (rc)
5073                 return rc;
5074
5075         rc = bnxt_request_int(bp);
5076         if (rc)
5077                 return rc;
5078
5079         rc = bnxt_init_ctx_mem(bp);
5080         if (rc) {
5081                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5082                 return rc;
5083         }
5084
5085         rc = bnxt_init_locks(bp);
5086         if (rc)
5087                 return rc;
5088
5089         return 0;
5090 }
5091
5092 static int
5093 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5094                           const char *value, void *opaque_arg)
5095 {
5096         struct bnxt *bp = opaque_arg;
5097         unsigned long truflow;
5098         char *end = NULL;
5099
5100         if (!value || !opaque_arg) {
5101                 PMD_DRV_LOG(ERR,
5102                             "Invalid parameter passed to truflow devargs.\n");
5103                 return -EINVAL;
5104         }
5105
5106         truflow = strtoul(value, &end, 10);
5107         if (end == NULL || *end != '\0' ||
5108             (truflow == ULONG_MAX && errno == ERANGE)) {
5109                 PMD_DRV_LOG(ERR,
5110                             "Invalid parameter passed to truflow devargs.\n");
5111                 return -EINVAL;
5112         }
5113
5114         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5115                 PMD_DRV_LOG(ERR,
5116                             "Invalid value passed to truflow devargs.\n");
5117                 return -EINVAL;
5118         }
5119
5120         bp->truflow = truflow;
5121         if (bp->truflow)
5122                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5123
5124         return 0;
5125 }
5126
5127 static int
5128 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5129                              const char *value, void *opaque_arg)
5130 {
5131         struct bnxt *bp = opaque_arg;
5132         unsigned long flow_xstat;
5133         char *end = NULL;
5134
5135         if (!value || !opaque_arg) {
5136                 PMD_DRV_LOG(ERR,
5137                             "Invalid parameter passed to flow_xstat devarg.\n");
5138                 return -EINVAL;
5139         }
5140
5141         flow_xstat = strtoul(value, &end, 10);
5142         if (end == NULL || *end != '\0' ||
5143             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5144                 PMD_DRV_LOG(ERR,
5145                             "Invalid parameter passed to flow_xstat devarg.\n");
5146                 return -EINVAL;
5147         }
5148
5149         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5150                 PMD_DRV_LOG(ERR,
5151                             "Invalid value passed to flow_xstat devarg.\n");
5152                 return -EINVAL;
5153         }
5154
5155         bp->flow_xstat = flow_xstat;
5156         if (bp->flow_xstat)
5157                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5158
5159         return 0;
5160 }
5161
5162 static void
5163 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5164 {
5165         struct rte_kvargs *kvlist;
5166
5167         if (devargs == NULL)
5168                 return;
5169
5170         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5171         if (kvlist == NULL)
5172                 return;
5173
5174         /*
5175          * Handler for "truflow" devarg.
5176          * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1”
5177          */
5178         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5179                            bnxt_parse_devarg_truflow, bp);
5180
5181         /*
5182          * Handler for "flow_xstat" devarg.
5183          * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1”
5184          */
5185         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5186                            bnxt_parse_devarg_flow_xstat, bp);
5187
5188         rte_kvargs_free(kvlist);
5189 }
5190
5191 static int
5192 bnxt_dev_init(struct rte_eth_dev *eth_dev)
5193 {
5194         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5195         static int version_printed;
5196         struct bnxt *bp;
5197         int rc;
5198
5199         if (version_printed++ == 0)
5200                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5201
5202         eth_dev->dev_ops = &bnxt_dev_ops;
5203         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5204         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5205
5206         /*
5207          * For secondary processes, we don't initialise any further
5208          * as primary has already done this work.
5209          */
5210         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5211                 return 0;
5212
5213         rte_eth_copy_pci_info(eth_dev, pci_dev);
5214
5215         bp = eth_dev->data->dev_private;
5216
5217         /* Parse dev arguments passed on when starting the DPDK application. */
5218         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5219
5220         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5221
5222         if (bnxt_vf_pciid(pci_dev->id.device_id))
5223                 bp->flags |= BNXT_FLAG_VF;
5224
5225         if (bnxt_thor_device(pci_dev->id.device_id))
5226                 bp->flags |= BNXT_FLAG_THOR_CHIP;
5227
5228         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5229             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5230             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5231             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5232                 bp->flags |= BNXT_FLAG_STINGRAY;
5233
5234         rc = bnxt_init_board(eth_dev);
5235         if (rc) {
5236                 PMD_DRV_LOG(ERR,
5237                             "Failed to initialize board rc: %x\n", rc);
5238                 return rc;
5239         }
5240
5241         rc = bnxt_alloc_hwrm_resources(bp);
5242         if (rc) {
5243                 PMD_DRV_LOG(ERR,
5244                             "Failed to allocate hwrm resource rc: %x\n", rc);
5245                 goto error_free;
5246         }
5247         rc = bnxt_init_resources(bp, false);
5248         if (rc)
5249                 goto error_free;
5250
5251         rc = bnxt_alloc_stats_mem(bp);
5252         if (rc)
5253                 goto error_free;
5254
5255         /* Pass the information to the rte_eth_dev_close() that it should also
5256          * release the private port resources.
5257          */
5258         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5259
5260         PMD_DRV_LOG(INFO,
5261                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5262                     pci_dev->mem_resource[0].phys_addr,
5263                     pci_dev->mem_resource[0].addr);
5264
5265         return 0;
5266
5267 error_free:
5268         bnxt_dev_uninit(eth_dev);
5269         return rc;
5270 }
5271
5272
5273 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5274 {
5275         if (!ctx)
5276                 return;
5277
5278         if (ctx->va)
5279                 rte_free(ctx->va);
5280
5281         ctx->va = NULL;
5282         ctx->dma = RTE_BAD_IOVA;
5283         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5284 }
5285
5286 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5287 {
5288         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5289                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5290                                   bp->rx_fc_out_tbl.ctx_id,
5291                                   bp->max_fc,
5292                                   false);
5293
5294         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5295                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5296                                   bp->tx_fc_out_tbl.ctx_id,
5297                                   bp->max_fc,
5298                                   false);
5299
5300         if (bp->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5301                 bnxt_hwrm_ctx_unrgtr(bp, bp->rx_fc_in_tbl.ctx_id);
5302         bp->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5303
5304         if (bp->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5305                 bnxt_hwrm_ctx_unrgtr(bp, bp->rx_fc_out_tbl.ctx_id);
5306         bp->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5307
5308         if (bp->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5309                 bnxt_hwrm_ctx_unrgtr(bp, bp->tx_fc_in_tbl.ctx_id);
5310         bp->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5311
5312         if (bp->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5313                 bnxt_hwrm_ctx_unrgtr(bp, bp->tx_fc_out_tbl.ctx_id);
5314         bp->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5315 }
5316
5317 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5318 {
5319         bnxt_unregister_fc_ctx_mem(bp);
5320
5321         bnxt_free_ctx_mem_buf(&bp->rx_fc_in_tbl);
5322         bnxt_free_ctx_mem_buf(&bp->rx_fc_out_tbl);
5323         bnxt_free_ctx_mem_buf(&bp->tx_fc_in_tbl);
5324         bnxt_free_ctx_mem_buf(&bp->tx_fc_out_tbl);
5325 }
5326
5327 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5328 {
5329         bnxt_uninit_fc_ctx_mem(bp);
5330 }
5331
5332 static void
5333 bnxt_uninit_locks(struct bnxt *bp)
5334 {
5335         pthread_mutex_destroy(&bp->flow_lock);
5336         pthread_mutex_destroy(&bp->def_cp_lock);
5337 }
5338
5339 static int
5340 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5341 {
5342         int rc;
5343
5344         bnxt_free_int(bp);
5345         bnxt_free_mem(bp, reconfig_dev);
5346         bnxt_hwrm_func_buf_unrgtr(bp);
5347         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5348         bp->flags &= ~BNXT_FLAG_REGISTERED;
5349         bnxt_free_ctx_mem(bp);
5350         if (!reconfig_dev) {
5351                 bnxt_free_hwrm_resources(bp);
5352
5353                 if (bp->recovery_info != NULL) {
5354                         rte_free(bp->recovery_info);
5355                         bp->recovery_info = NULL;
5356                 }
5357         }
5358
5359         bnxt_uninit_ctx_mem(bp);
5360
5361         bnxt_uninit_locks(bp);
5362         rte_free(bp->ptp_cfg);
5363         bp->ptp_cfg = NULL;
5364         return rc;
5365 }
5366
5367 static int
5368 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5369 {
5370         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5371                 return -EPERM;
5372
5373         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5374
5375         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5376                 bnxt_dev_close_op(eth_dev);
5377
5378         return 0;
5379 }
5380
5381 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5382         struct rte_pci_device *pci_dev)
5383 {
5384         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
5385                 bnxt_dev_init);
5386 }
5387
5388 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5389 {
5390         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
5391                 return rte_eth_dev_pci_generic_remove(pci_dev,
5392                                 bnxt_dev_uninit);
5393         else
5394                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5395 }
5396
5397 static struct rte_pci_driver bnxt_rte_pmd = {
5398         .id_table = bnxt_pci_id_map,
5399         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5400         .probe = bnxt_pci_probe,
5401         .remove = bnxt_pci_remove,
5402 };
5403
5404 static bool
5405 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5406 {
5407         if (strcmp(dev->device->driver->name, drv->driver.name))
5408                 return false;
5409
5410         return true;
5411 }
5412
5413 bool is_bnxt_supported(struct rte_eth_dev *dev)
5414 {
5415         return is_device_supported(dev, &bnxt_rte_pmd);
5416 }
5417
5418 RTE_INIT(bnxt_init_log)
5419 {
5420         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
5421         if (bnxt_logtype_driver >= 0)
5422                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
5423 }
5424
5425 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5426 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5427 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");