drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <ethdev_driver.h>
  11 #include <ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16 #include <rte_vect.h>
  17
  18 #include "bnxt.h"
  19 #include "bnxt_filter.h"
  20 #include "bnxt_hwrm.h"
  21 #include "bnxt_irq.h"
  22 #include "bnxt_reps.h"
  23 #include "bnxt_ring.h"
  24 #include "bnxt_rxq.h"
  25 #include "bnxt_rxr.h"
  26 #include "bnxt_stats.h"
  27 #include "bnxt_txq.h"
  28 #include "bnxt_txr.h"
  29 #include "bnxt_vnic.h"
  30 #include "hsi_struct_def_dpdk.h"
  31 #include "bnxt_nvm_defs.h"
  32 #include "bnxt_tf_common.h"
  33 #include "ulp_flow_db.h"
  34 #include "rte_pmd_bnxt.h"
  35
  36 #define DRV_MODULE_NAME         "bnxt"
  37 static const char bnxt_version[] =
  38         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  39
  40 /*
  41  * The set of PCI devices this driver supports
  42  */
  43 static const struct rte_pci_id bnxt_pci_id_map[] = {
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  47                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
  87         { .vendor_id = 0, /* sentinel */ },
  88 };
  89
  90 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
  91 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
  92 #define BNXT_DEVARG_REPRESENTOR "representor"
  93 #define BNXT_DEVARG_REP_BASED_PF  "rep-based-pf"
  94 #define BNXT_DEVARG_REP_IS_PF  "rep-is-pf"
  95 #define BNXT_DEVARG_REP_Q_R2F  "rep-q-r2f"
  96 #define BNXT_DEVARG_REP_Q_F2R  "rep-q-f2r"
  97 #define BNXT_DEVARG_REP_FC_R2F  "rep-fc-r2f"
  98 #define BNXT_DEVARG_REP_FC_F2R  "rep-fc-f2r"
  99 #define BNXT_DEVARG_APP_ID      "app-id"
 100
 101 static const char *const bnxt_dev_args[] = {
 102         BNXT_DEVARG_REPRESENTOR,
 103         BNXT_DEVARG_FLOW_XSTAT,
 104         BNXT_DEVARG_MAX_NUM_KFLOWS,
 105         BNXT_DEVARG_REP_BASED_PF,
 106         BNXT_DEVARG_REP_IS_PF,
 107         BNXT_DEVARG_REP_Q_R2F,
 108         BNXT_DEVARG_REP_Q_F2R,
 109         BNXT_DEVARG_REP_FC_R2F,
 110         BNXT_DEVARG_REP_FC_F2R,
 111         BNXT_DEVARG_APP_ID,
 112         NULL
 113 };
 114
 115 /*
 116  * app-id = an non-negative 8-bit number
 117  */
 118 #define BNXT_DEVARG_APP_ID_INVALID(val)                 ((val) > 255)
 119
 120 /*
 121  * flow_xstat == false to disable the feature
 122  * flow_xstat == true to enable the feature
 123  */
 124 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 125
 126 /*
 127  * rep_is_pf == false to indicate VF representor
 128  * rep_is_pf == true to indicate PF representor
 129  */
 130 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)        ((rep_is_pf) > 1)
 131
 132 /*
 133  * rep_based_pf == Physical index of the PF
 134  */
 135 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)  ((rep_based_pf) > 15)
 136 /*
 137  * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
 138  */
 139 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)        ((rep_q_r2f) > 3)
 140
 141 /*
 142  * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
 143  */
 144 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)        ((rep_q_f2r) > 3)
 145
 146 /*
 147  * rep_fc_r2f == Flow control for the representor to endpoint direction
 148  */
 149 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)      ((rep_fc_r2f) > 1)
 150
 151 /*
 152  * rep_fc_f2r == Flow control for the endpoint to representor direction
 153  */
 154 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)      ((rep_fc_f2r) > 1)
 155
 156 int bnxt_cfa_code_dynfield_offset = -1;
 157
 158 /*
 159  * max_num_kflows must be >= 32
 160  * and must be a power-of-2 supported value
 161  * return: 1 -> invalid
 162  *         0 -> valid
 163  */
 164 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 165 {
 166         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 167                 return 1;
 168         return 0;
 169 }
 170
 171 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 172 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 173 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 174 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 175 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 176 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 177 static void bnxt_dev_recover(void *arg);
 178 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 179 static void bnxt_free_rep_info(struct bnxt *bp);
 180
 181 int is_bnxt_in_error(struct bnxt *bp)
 182 {
 183         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 184                 return -EIO;
 185         if (bp->flags & BNXT_FLAG_FW_RESET)
 186                 return -EBUSY;
 187
 188         return 0;
 189 }
 190
 191 /***********************/
 192
 193 /*
 194  * High level utility functions
 195  */
 196
 197 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 198 {
 199         unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
 200                                              BNXT_RSS_TBL_SIZE_P5);
 201
 202         if (!BNXT_CHIP_P5(bp))
 203                 return 1;
 204
 205         return RTE_ALIGN_MUL_CEIL(num_rss_rings,
 206                                   BNXT_RSS_ENTRIES_PER_CTX_P5) /
 207                                   BNXT_RSS_ENTRIES_PER_CTX_P5;
 208 }
 209
 210 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 211 {
 212         if (!BNXT_CHIP_P5(bp))
 213                 return HW_HASH_INDEX_SIZE;
 214
 215         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
 216 }
 217
 218 static void bnxt_free_parent_info(struct bnxt *bp)
 219 {
 220         rte_free(bp->parent);
 221         bp->parent = NULL;
 222 }
 223
 224 static void bnxt_free_pf_info(struct bnxt *bp)
 225 {
 226         rte_free(bp->pf);
 227         bp->pf = NULL;
 228 }
 229
 230 static void bnxt_free_link_info(struct bnxt *bp)
 231 {
 232         rte_free(bp->link_info);
 233         bp->link_info = NULL;
 234 }
 235
 236 static void bnxt_free_leds_info(struct bnxt *bp)
 237 {
 238         if (BNXT_VF(bp))
 239                 return;
 240
 241         rte_free(bp->leds);
 242         bp->leds = NULL;
 243 }
 244
 245 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 246 {
 247         rte_free(bp->flow_stat);
 248         bp->flow_stat = NULL;
 249 }
 250
 251 static void bnxt_free_cos_queues(struct bnxt *bp)
 252 {
 253         rte_free(bp->rx_cos_queue);
 254         bp->rx_cos_queue = NULL;
 255         rte_free(bp->tx_cos_queue);
 256         bp->tx_cos_queue = NULL;
 257 }
 258
 259 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 260 {
 261         bnxt_free_filter_mem(bp);
 262         bnxt_free_vnic_attributes(bp);
 263         bnxt_free_vnic_mem(bp);
 264
 265         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 266          * If the number of rings change across fw update,
 267          * we don't have much choice except to warn the user.
 268          */
 269         if (!reconfig) {
 270                 bnxt_free_stats(bp);
 271                 bnxt_free_tx_rings(bp);
 272                 bnxt_free_rx_rings(bp);
 273         }
 274         bnxt_free_async_cp_ring(bp);
 275         bnxt_free_rxtx_nq_ring(bp);
 276
 277         rte_free(bp->grp_info);
 278         bp->grp_info = NULL;
 279 }
 280
 281 static int bnxt_alloc_parent_info(struct bnxt *bp)
 282 {
 283         bp->parent = rte_zmalloc("bnxt_parent_info",
 284                                  sizeof(struct bnxt_parent_info), 0);
 285         if (bp->parent == NULL)
 286                 return -ENOMEM;
 287
 288         return 0;
 289 }
 290
 291 static int bnxt_alloc_pf_info(struct bnxt *bp)
 292 {
 293         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 294         if (bp->pf == NULL)
 295                 return -ENOMEM;
 296
 297         return 0;
 298 }
 299
 300 static int bnxt_alloc_link_info(struct bnxt *bp)
 301 {
 302         bp->link_info =
 303                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 304         if (bp->link_info == NULL)
 305                 return -ENOMEM;
 306
 307         return 0;
 308 }
 309
 310 static int bnxt_alloc_leds_info(struct bnxt *bp)
 311 {
 312         if (BNXT_VF(bp))
 313                 return 0;
 314
 315         bp->leds = rte_zmalloc("bnxt_leds",
 316                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 317                                0);
 318         if (bp->leds == NULL)
 319                 return -ENOMEM;
 320
 321         return 0;
 322 }
 323
 324 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 325 {
 326         bp->rx_cos_queue =
 327                 rte_zmalloc("bnxt_rx_cosq",
 328                             BNXT_COS_QUEUE_COUNT *
 329                             sizeof(struct bnxt_cos_queue_info),
 330                             0);
 331         if (bp->rx_cos_queue == NULL)
 332                 return -ENOMEM;
 333
 334         bp->tx_cos_queue =
 335                 rte_zmalloc("bnxt_tx_cosq",
 336                             BNXT_COS_QUEUE_COUNT *
 337                             sizeof(struct bnxt_cos_queue_info),
 338                             0);
 339         if (bp->tx_cos_queue == NULL)
 340                 return -ENOMEM;
 341
 342         return 0;
 343 }
 344
 345 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 346 {
 347         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 348                                     sizeof(struct bnxt_flow_stat_info), 0);
 349         if (bp->flow_stat == NULL)
 350                 return -ENOMEM;
 351
 352         return 0;
 353 }
 354
 355 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 356 {
 357         int rc;
 358
 359         rc = bnxt_alloc_ring_grps(bp);
 360         if (rc)
 361                 goto alloc_mem_err;
 362
 363         rc = bnxt_alloc_async_ring_struct(bp);
 364         if (rc)
 365                 goto alloc_mem_err;
 366
 367         rc = bnxt_alloc_vnic_mem(bp);
 368         if (rc)
 369                 goto alloc_mem_err;
 370
 371         rc = bnxt_alloc_vnic_attributes(bp, reconfig);
 372         if (rc)
 373                 goto alloc_mem_err;
 374
 375         rc = bnxt_alloc_filter_mem(bp);
 376         if (rc)
 377                 goto alloc_mem_err;
 378
 379         rc = bnxt_alloc_async_cp_ring(bp);
 380         if (rc)
 381                 goto alloc_mem_err;
 382
 383         rc = bnxt_alloc_rxtx_nq_ring(bp);
 384         if (rc)
 385                 goto alloc_mem_err;
 386
 387         if (BNXT_FLOW_XSTATS_EN(bp)) {
 388                 rc = bnxt_alloc_flow_stats_info(bp);
 389                 if (rc)
 390                         goto alloc_mem_err;
 391         }
 392
 393         return 0;
 394
 395 alloc_mem_err:
 396         bnxt_free_mem(bp, reconfig);
 397         return rc;
 398 }
 399
 400 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 401 {
 402         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 403         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 404         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 405         struct bnxt_rx_queue *rxq;
 406         unsigned int j;
 407         int rc;
 408
 409         rc = bnxt_vnic_grp_alloc(bp, vnic);
 410         if (rc)
 411                 goto err_out;
 412
 413         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 414                     vnic_id, vnic, vnic->fw_grp_ids);
 415
 416         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 417         if (rc)
 418                 goto err_out;
 419
 420         /* Alloc RSS context only if RSS mode is enabled */
 421         if (dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS) {
 422                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 423
 424                 /* RSS table size in Thor is 512.
 425                  * Cap max Rx rings to same value
 426                  */
 427                 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
 428                         PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
 429                                     bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
 430                         goto err_out;
 431                 }
 432
 433                 rc = 0;
 434                 for (j = 0; j < nr_ctxs; j++) {
 435                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 436                         if (rc)
 437                                 break;
 438                 }
 439                 if (rc) {
 440                         PMD_DRV_LOG(ERR,
 441                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 442                                     vnic_id, j, rc);
 443                         goto err_out;
 444                 }
 445                 vnic->num_lb_ctxts = nr_ctxs;
 446         }
 447
 448         /*
 449          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 450          * setting is not available at this time, it will not be
 451          * configured correctly in the CFA.
 452          */
 453         if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
 454                 vnic->vlan_strip = true;
 455         else
 456                 vnic->vlan_strip = false;
 457
 458         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 459         if (rc)
 460                 goto err_out;
 461
 462         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 463         if (rc)
 464                 goto err_out;
 465
 466         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 467                 rxq = bp->eth_dev->data->rx_queues[j];
 468
 469                 PMD_DRV_LOG(DEBUG,
 470                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 471                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 472
 473                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 474                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 475                 else
 476                         vnic->rx_queue_cnt++;
 477         }
 478
 479         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 480
 481         rc = bnxt_vnic_rss_configure(bp, vnic);
 482         if (rc)
 483                 goto err_out;
 484
 485         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 486
 487         rc = bnxt_hwrm_vnic_tpa_cfg(bp, vnic,
 488                                     (rx_offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO) ?
 489                                     true : false);
 490         if (rc)
 491                 goto err_out;
 492
 493         return 0;
 494 err_out:
 495         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 496                     vnic_id, rc);
 497         return rc;
 498 }
 499
 500 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 501 {
 502         int rc = 0;
 503
 504         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 505                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 506         if (rc)
 507                 return rc;
 508
 509         PMD_DRV_LOG(DEBUG,
 510                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 511                     " rx_fc_in_tbl.ctx_id = %d\n",
 512                     bp->flow_stat->rx_fc_in_tbl.va,
 513                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 514                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 515
 516         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 517                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 518         if (rc)
 519                 return rc;
 520
 521         PMD_DRV_LOG(DEBUG,
 522                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 523                     " rx_fc_out_tbl.ctx_id = %d\n",
 524                     bp->flow_stat->rx_fc_out_tbl.va,
 525                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 526                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 527
 528         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 529                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 530         if (rc)
 531                 return rc;
 532
 533         PMD_DRV_LOG(DEBUG,
 534                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 535                     " tx_fc_in_tbl.ctx_id = %d\n",
 536                     bp->flow_stat->tx_fc_in_tbl.va,
 537                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 538                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 539
 540         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 541                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 542         if (rc)
 543                 return rc;
 544
 545         PMD_DRV_LOG(DEBUG,
 546                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 547                     " tx_fc_out_tbl.ctx_id = %d\n",
 548                     bp->flow_stat->tx_fc_out_tbl.va,
 549                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 550                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 551
 552         memset(bp->flow_stat->rx_fc_out_tbl.va,
 553                0,
 554                bp->flow_stat->rx_fc_out_tbl.size);
 555         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 556                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 557                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 558                                        bp->flow_stat->max_fc,
 559                                        true);
 560         if (rc)
 561                 return rc;
 562
 563         memset(bp->flow_stat->tx_fc_out_tbl.va,
 564                0,
 565                bp->flow_stat->tx_fc_out_tbl.size);
 566         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 567                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 568                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 569                                        bp->flow_stat->max_fc,
 570                                        true);
 571
 572         return rc;
 573 }
 574
 575 static int bnxt_alloc_ctx_mem_buf(struct bnxt *bp, char *type, size_t size,
 576                                   struct bnxt_ctx_mem_buf_info *ctx)
 577 {
 578         if (!ctx)
 579                 return -EINVAL;
 580
 581         ctx->va = rte_zmalloc_socket(type, size, 0,
 582                                      bp->eth_dev->device->numa_node);
 583         if (ctx->va == NULL)
 584                 return -ENOMEM;
 585         rte_mem_lock_page(ctx->va);
 586         ctx->size = size;
 587         ctx->dma = rte_mem_virt2iova(ctx->va);
 588         if (ctx->dma == RTE_BAD_IOVA)
 589                 return -ENOMEM;
 590
 591         return 0;
 592 }
 593
 594 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 595 {
 596         struct rte_pci_device *pdev = bp->pdev;
 597         char type[RTE_MEMZONE_NAMESIZE];
 598         uint16_t max_fc;
 599         int rc = 0;
 600
 601         max_fc = bp->flow_stat->max_fc;
 602
 603         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 604                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 605         /* 4 bytes for each counter-id */
 606         rc = bnxt_alloc_ctx_mem_buf(bp, type,
 607                                     max_fc * 4,
 608                                     &bp->flow_stat->rx_fc_in_tbl);
 609         if (rc)
 610                 return rc;
 611
 612         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 613                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 614         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 615         rc = bnxt_alloc_ctx_mem_buf(bp, type,
 616                                     max_fc * 16,
 617                                     &bp->flow_stat->rx_fc_out_tbl);
 618         if (rc)
 619                 return rc;
 620
 621         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 622                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 623         /* 4 bytes for each counter-id */
 624         rc = bnxt_alloc_ctx_mem_buf(bp, type,
 625                                     max_fc * 4,
 626                                     &bp->flow_stat->tx_fc_in_tbl);
 627         if (rc)
 628                 return rc;
 629
 630         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 631                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 632         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 633         rc = bnxt_alloc_ctx_mem_buf(bp, type,
 634                                     max_fc * 16,
 635                                     &bp->flow_stat->tx_fc_out_tbl);
 636         if (rc)
 637                 return rc;
 638
 639         rc = bnxt_register_fc_ctx_mem(bp);
 640
 641         return rc;
 642 }
 643
 644 static int bnxt_init_ctx_mem(struct bnxt *bp)
 645 {
 646         int rc = 0;
 647
 648         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 649             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 650             !BNXT_FLOW_XSTATS_EN(bp))
 651                 return 0;
 652
 653         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 654         if (rc)
 655                 return rc;
 656
 657         rc = bnxt_init_fc_ctx_mem(bp);
 658
 659         return rc;
 660 }
 661
 662 static int bnxt_update_phy_setting(struct bnxt *bp)
 663 {
 664         struct rte_eth_link new;
 665         int rc;
 666
 667         rc = bnxt_get_hwrm_link_config(bp, &new);
 668         if (rc) {
 669                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 670                 return rc;
 671         }
 672
 673         /*
 674          * On BCM957508-N2100 adapters, FW will not allow any user other
 675          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 676          * always returns link up. Force phy update always in that case.
 677          */
 678         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 679                 rc = bnxt_set_hwrm_link_config(bp, true);
 680                 if (rc) {
 681                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 682                         return rc;
 683                 }
 684         }
 685
 686         return rc;
 687 }
 688
 689 static void bnxt_free_prev_ring_stats(struct bnxt *bp)
 690 {
 691         rte_free(bp->prev_rx_ring_stats);
 692         rte_free(bp->prev_tx_ring_stats);
 693
 694         bp->prev_rx_ring_stats = NULL;
 695         bp->prev_tx_ring_stats = NULL;
 696 }
 697
 698 static int bnxt_alloc_prev_ring_stats(struct bnxt *bp)
 699 {
 700         bp->prev_rx_ring_stats =  rte_zmalloc("bnxt_prev_rx_ring_stats",
 701                                               sizeof(struct bnxt_ring_stats) *
 702                                               bp->rx_cp_nr_rings,
 703                                               0);
 704         if (bp->prev_rx_ring_stats == NULL)
 705                 return -ENOMEM;
 706
 707         bp->prev_tx_ring_stats = rte_zmalloc("bnxt_prev_tx_ring_stats",
 708                                              sizeof(struct bnxt_ring_stats) *
 709                                              bp->tx_cp_nr_rings,
 710                                              0);
 711         if (bp->prev_tx_ring_stats == NULL)
 712                 goto error;
 713
 714         return 0;
 715
 716 error:
 717         bnxt_free_prev_ring_stats(bp);
 718         return -ENOMEM;
 719 }
 720
 721 static int bnxt_start_nic(struct bnxt *bp)
 722 {
 723         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 724         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
 725         uint32_t intr_vector = 0;
 726         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 727         uint32_t vec = BNXT_MISC_VEC_ID;
 728         unsigned int i, j;
 729         int rc;
 730
 731         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU)
 732                 bp->flags |= BNXT_FLAG_JUMBO;
 733         else
 734                 bp->flags &= ~BNXT_FLAG_JUMBO;
 735
 736         /* THOR does not support ring groups.
 737          * But we will use the array to save RSS context IDs.
 738          */
 739         if (BNXT_CHIP_P5(bp))
 740                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
 741
 742         rc = bnxt_alloc_hwrm_rings(bp);
 743         if (rc) {
 744                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 745                 goto err_out;
 746         }
 747
 748         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 749         if (rc) {
 750                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 751                 goto err_out;
 752         }
 753
 754         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 755                 goto skip_cosq_cfg;
 756
 757         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 758                 if (bp->rx_cos_queue[i].id != 0xff) {
 759                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 760
 761                         if (!vnic) {
 762                                 PMD_DRV_LOG(ERR,
 763                                             "Num pools more than FW profile\n");
 764                                 rc = -EINVAL;
 765                                 goto err_out;
 766                         }
 767                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 768                         bp->rx_cosq_cnt++;
 769                 }
 770         }
 771
 772 skip_cosq_cfg:
 773         rc = bnxt_mq_rx_configure(bp);
 774         if (rc) {
 775                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 776                 goto err_out;
 777         }
 778
 779         for (j = 0; j < bp->rx_nr_rings; j++) {
 780                 struct bnxt_rx_queue *rxq = bp->rx_queues[j];
 781
 782                 if (!rxq->rx_deferred_start) {
 783                         bp->eth_dev->data->rx_queue_state[j] =
 784                                 RTE_ETH_QUEUE_STATE_STARTED;
 785                         rxq->rx_started = true;
 786                 }
 787         }
 788
 789         /* default vnic 0 */
 790         rc = bnxt_setup_one_vnic(bp, 0);
 791         if (rc)
 792                 goto err_out;
 793         /* VNIC configuration */
 794         if (BNXT_RFS_NEEDS_VNIC(bp)) {
 795                 for (i = 1; i < bp->nr_vnics; i++) {
 796                         rc = bnxt_setup_one_vnic(bp, i);
 797                         if (rc)
 798                                 goto err_out;
 799                 }
 800         }
 801
 802         for (j = 0; j < bp->tx_nr_rings; j++) {
 803                 struct bnxt_tx_queue *txq = bp->tx_queues[j];
 804
 805                 if (!txq->tx_deferred_start) {
 806                         bp->eth_dev->data->tx_queue_state[j] =
 807                                 RTE_ETH_QUEUE_STATE_STARTED;
 808                         txq->tx_started = true;
 809                 }
 810         }
 811
 812         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 813         if (rc) {
 814                 PMD_DRV_LOG(ERR,
 815                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 816                 goto err_out;
 817         }
 818
 819         /* check and configure queue intr-vector mapping */
 820         if ((rte_intr_cap_multiple(intr_handle) ||
 821              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 822             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 823                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 824                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 825                 if (intr_vector > bp->rx_cp_nr_rings) {
 826                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 827                                         bp->rx_cp_nr_rings);
 828                         return -ENOTSUP;
 829                 }
 830                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 831                 if (rc)
 832                         return rc;
 833         }
 834
 835         if (rte_intr_dp_is_en(intr_handle)) {
 836                 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
 837                                         bp->eth_dev->data->nb_rx_queues)) {
 838                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 839                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 840                         rc = -ENOMEM;
 841                         goto err_out;
 842                 }
 843                 PMD_DRV_LOG(DEBUG, "intr_handle->nb_efd = %d "
 844                             "intr_handle->max_intr = %d\n",
 845                             rte_intr_nb_efd_get(intr_handle),
 846                             rte_intr_max_intr_get(intr_handle));
 847                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 848                      queue_id++) {
 849                         rte_intr_vec_list_index_set(intr_handle,
 850                                         queue_id, vec + BNXT_RX_VEC_START);
 851                         if (vec < base + rte_intr_nb_efd_get(intr_handle)
 852                             - 1)
 853                                 vec++;
 854                 }
 855         }
 856
 857         /* enable uio/vfio intr/eventfd mapping */
 858         rc = rte_intr_enable(intr_handle);
 859 #ifndef RTE_EXEC_ENV_FREEBSD
 860         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 861         if (rc)
 862                 goto err_out;
 863 #endif
 864
 865         rc = bnxt_update_phy_setting(bp);
 866         if (rc)
 867                 goto err_out;
 868
 869         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 870         if (!bp->mark_table)
 871                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 872
 873         return 0;
 874
 875 err_out:
 876         /* Some of the error status returned by FW may not be from errno.h */
 877         if (rc > 0)
 878                 rc = -EIO;
 879
 880         return rc;
 881 }
 882
 883 static int bnxt_shutdown_nic(struct bnxt *bp)
 884 {
 885         bnxt_free_all_hwrm_resources(bp);
 886         bnxt_free_all_filters(bp);
 887         bnxt_free_all_vnics(bp);
 888         return 0;
 889 }
 890
 891 /*
 892  * Device configuration and status function
 893  */
 894
 895 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 896 {
 897         uint32_t link_speed = 0;
 898         uint32_t speed_capa = 0;
 899
 900         if (bp->link_info == NULL)
 901                 return 0;
 902
 903         link_speed = bp->link_info->support_speeds;
 904
 905         /* If PAM4 is configured, use PAM4 supported speed */
 906         if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
 907                 link_speed = bp->link_info->support_pam4_speeds;
 908
 909         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 910                 speed_capa |= RTE_ETH_LINK_SPEED_100M;
 911         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 912                 speed_capa |= RTE_ETH_LINK_SPEED_100M_HD;
 913         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 914                 speed_capa |= RTE_ETH_LINK_SPEED_1G;
 915         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 916                 speed_capa |= RTE_ETH_LINK_SPEED_2_5G;
 917         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 918                 speed_capa |= RTE_ETH_LINK_SPEED_10G;
 919         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 920                 speed_capa |= RTE_ETH_LINK_SPEED_20G;
 921         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 922                 speed_capa |= RTE_ETH_LINK_SPEED_25G;
 923         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 924                 speed_capa |= RTE_ETH_LINK_SPEED_40G;
 925         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 926                 speed_capa |= RTE_ETH_LINK_SPEED_50G;
 927         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 928                 speed_capa |= RTE_ETH_LINK_SPEED_100G;
 929         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
 930                 speed_capa |= RTE_ETH_LINK_SPEED_50G;
 931         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
 932                 speed_capa |= RTE_ETH_LINK_SPEED_100G;
 933         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
 934                 speed_capa |= RTE_ETH_LINK_SPEED_200G;
 935
 936         if (bp->link_info->auto_mode ==
 937             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 938                 speed_capa |= RTE_ETH_LINK_SPEED_FIXED;
 939
 940         return speed_capa;
 941 }
 942
 943 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 944                                 struct rte_eth_dev_info *dev_info)
 945 {
 946         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 947         struct bnxt *bp = eth_dev->data->dev_private;
 948         uint16_t max_vnics, i, j, vpool, vrxq;
 949         unsigned int max_rx_rings;
 950         int rc;
 951
 952         rc = is_bnxt_in_error(bp);
 953         if (rc)
 954                 return rc;
 955
 956         /* MAC Specifics */
 957         dev_info->max_mac_addrs = bp->max_l2_ctx;
 958         dev_info->max_hash_mac_addrs = 0;
 959
 960         /* PF/VF specifics */
 961         if (BNXT_PF(bp))
 962                 dev_info->max_vfs = pdev->max_vfs;
 963
 964         max_rx_rings = bnxt_max_rings(bp);
 965         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 966         dev_info->max_rx_queues = max_rx_rings;
 967         dev_info->max_tx_queues = max_rx_rings;
 968         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 969         dev_info->hash_key_size = HW_HASH_KEY_SIZE;
 970         max_vnics = bp->max_vnics;
 971
 972         /* MTU specifics */
 973         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 974         dev_info->max_mtu = BNXT_MAX_MTU;
 975
 976         /* Fast path specifics */
 977         dev_info->min_rx_bufsize = 1;
 978         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 979
 980         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 981         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 982                 dev_info->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_TIMESTAMP;
 983         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_VLAN_RX_STRIP)
 984                 dev_info->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_VLAN_STRIP;
 985         dev_info->tx_queue_offload_capa = RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE;
 986         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
 987                                     dev_info->tx_queue_offload_capa;
 988         if (bp->fw_cap & BNXT_FW_CAP_VLAN_TX_INSERT)
 989                 dev_info->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_VLAN_INSERT;
 990         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 991
 992         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 993         dev_info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
 994                              RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
 995         dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
 996
 997         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 998                 .rx_thresh = {
 999                         .pthresh = 8,
1000                         .hthresh = 8,
1001                         .wthresh = 0,
1002                 },
1003                 .rx_free_thresh = 32,
1004                 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
1005         };
1006
1007         dev_info->default_txconf = (struct rte_eth_txconf) {
1008                 .tx_thresh = {
1009                         .pthresh = 32,
1010                         .hthresh = 0,
1011                         .wthresh = 0,
1012                 },
1013                 .tx_free_thresh = 32,
1014                 .tx_rs_thresh = 32,
1015         };
1016         eth_dev->data->dev_conf.intr_conf.lsc = 1;
1017
1018         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
1019         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
1020         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
1021         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
1022
1023         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
1024                 dev_info->switch_info.name = eth_dev->device->name;
1025                 dev_info->switch_info.domain_id = bp->switch_domain_id;
1026                 dev_info->switch_info.port_id =
1027                                 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
1028                                     BNXT_SWITCH_PORT_ID_TRUSTED_VF;
1029         }
1030
1031         /*
1032          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
1033          *       need further investigation.
1034          */
1035
1036         /* VMDq resources */
1037         vpool = 64; /* RTE_ETH_64_POOLS */
1038         vrxq = 128; /* RTE_ETH_VMDQ_DCB_NUM_QUEUES */
1039         for (i = 0; i < 4; vpool >>= 1, i++) {
1040                 if (max_vnics > vpool) {
1041                         for (j = 0; j < 5; vrxq >>= 1, j++) {
1042                                 if (dev_info->max_rx_queues > vrxq) {
1043                                         if (vpool > vrxq)
1044                                                 vpool = vrxq;
1045                                         goto found;
1046                                 }
1047                         }
1048                         /* Not enough resources to support VMDq */
1049                         break;
1050                 }
1051         }
1052         /* Not enough resources to support VMDq */
1053         vpool = 0;
1054         vrxq = 0;
1055 found:
1056         dev_info->max_vmdq_pools = vpool;
1057         dev_info->vmdq_queue_num = vrxq;
1058
1059         dev_info->vmdq_pool_base = 0;
1060         dev_info->vmdq_queue_base = 0;
1061
1062         return 0;
1063 }
1064
1065 /* Configure the device based on the configuration provided */
1066 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1067 {
1068         struct bnxt *bp = eth_dev->data->dev_private;
1069         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1070         struct rte_eth_rss_conf *rss_conf = &eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
1071         int rc;
1072
1073         bp->rx_queues = (void *)eth_dev->data->rx_queues;
1074         bp->tx_queues = (void *)eth_dev->data->tx_queues;
1075         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1076         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1077
1078         rc = is_bnxt_in_error(bp);
1079         if (rc)
1080                 return rc;
1081
1082         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1083                 rc = bnxt_hwrm_check_vf_rings(bp);
1084                 if (rc) {
1085                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1086                         return -ENOSPC;
1087                 }
1088
1089                 /* If a resource has already been allocated - in this case
1090                  * it is the async completion ring, free it. Reallocate it after
1091                  * resource reservation. This will ensure the resource counts
1092                  * are calculated correctly.
1093                  */
1094
1095                 pthread_mutex_lock(&bp->def_cp_lock);
1096
1097                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1098                         bnxt_disable_int(bp);
1099                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
1100                 }
1101
1102                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1103                 if (rc) {
1104                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1105                         pthread_mutex_unlock(&bp->def_cp_lock);
1106                         return -ENOSPC;
1107                 }
1108
1109                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1110                         rc = bnxt_alloc_async_cp_ring(bp);
1111                         if (rc) {
1112                                 pthread_mutex_unlock(&bp->def_cp_lock);
1113                                 return rc;
1114                         }
1115                         bnxt_enable_int(bp);
1116                 }
1117
1118                 pthread_mutex_unlock(&bp->def_cp_lock);
1119         }
1120
1121         /* Inherit new configurations */
1122         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1123             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1124             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1125                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1126             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1127             bp->max_stat_ctx)
1128                 goto resource_error;
1129
1130         if (BNXT_HAS_RING_GRPS(bp) &&
1131             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1132                 goto resource_error;
1133
1134         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS) &&
1135             bp->max_vnics < eth_dev->data->nb_rx_queues)
1136                 goto resource_error;
1137
1138         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1139         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1140
1141         if (eth_dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)
1142                 rx_offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
1143         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1144
1145         /* application provides the hash key to program */
1146         if (rss_conf->rss_key != NULL) {
1147                 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE)
1148                         PMD_DRV_LOG(WARNING, "port %u RSS key len must be %d bytes long",
1149                                     eth_dev->data->port_id, HW_HASH_KEY_SIZE);
1150                 else
1151                         memcpy(bp->rss_conf.rss_key, rss_conf->rss_key, HW_HASH_KEY_SIZE);
1152         }
1153         bp->rss_conf.rss_key_len = HW_HASH_KEY_SIZE;
1154         bp->rss_conf.rss_hf = rss_conf->rss_hf;
1155
1156         bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1157
1158         return 0;
1159
1160 resource_error:
1161         PMD_DRV_LOG(ERR,
1162                     "Insufficient resources to support requested config\n");
1163         PMD_DRV_LOG(ERR,
1164                     "Num Queues Requested: Tx %d, Rx %d\n",
1165                     eth_dev->data->nb_tx_queues,
1166                     eth_dev->data->nb_rx_queues);
1167         PMD_DRV_LOG(ERR,
1168                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1169                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1170                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1171         return -ENOSPC;
1172 }
1173
1174 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1175 {
1176         struct rte_eth_link *link = &eth_dev->data->dev_link;
1177
1178         if (link->link_status)
1179                 PMD_DRV_LOG(DEBUG, "Port %d Link Up - speed %u Mbps - %s\n",
1180                         eth_dev->data->port_id,
1181                         (uint32_t)link->link_speed,
1182                         (link->link_duplex == RTE_ETH_LINK_FULL_DUPLEX) ?
1183                         ("full-duplex") : ("half-duplex\n"));
1184         else
1185                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1186                         eth_dev->data->port_id);
1187 }
1188
1189 /*
1190  * Determine whether the current configuration requires support for scattered
1191  * receive; return 1 if scattered receive is required and 0 if not.
1192  */
1193 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1194 {
1195         uint32_t overhead = BNXT_MAX_PKT_LEN - BNXT_MAX_MTU;
1196         uint16_t buf_size;
1197         int i;
1198
1199         if (eth_dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_SCATTER)
1200                 return 1;
1201
1202         if (eth_dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO)
1203                 return 1;
1204
1205         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1206                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1207
1208                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1209                                       RTE_PKTMBUF_HEADROOM);
1210                 if (eth_dev->data->mtu + overhead > buf_size)
1211                         return 1;
1212         }
1213         return 0;
1214 }
1215
1216 static eth_rx_burst_t
1217 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1218 {
1219         struct bnxt *bp = eth_dev->data->dev_private;
1220
1221         /* Disable vector mode RX for Stingray2 for now */
1222         if (BNXT_CHIP_SR2(bp)) {
1223                 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1224                 return bnxt_recv_pkts;
1225         }
1226
1227 #if (defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)) && \
1228         !defined(RTE_LIBRTE_IEEE1588)
1229
1230         /* Vector mode receive cannot be enabled if scattered rx is in use. */
1231         if (eth_dev->data->scattered_rx)
1232                 goto use_scalar_rx;
1233
1234         /*
1235          * Vector mode receive cannot be enabled if Truflow is enabled or if
1236          * asynchronous completions and receive completions can be placed in
1237          * the same completion ring.
1238          */
1239         if (BNXT_TRUFLOW_EN(bp) || !BNXT_NUM_ASYNC_CPR(bp))
1240                 goto use_scalar_rx;
1241
1242         /*
1243          * Vector mode receive cannot be enabled if any receive offloads outside
1244          * a limited subset have been enabled.
1245          */
1246         if (eth_dev->data->dev_conf.rxmode.offloads &
1247                 ~(RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
1248                   RTE_ETH_RX_OFFLOAD_KEEP_CRC |
1249                   RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
1250                   RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
1251                   RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
1252                   RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1253                   RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM |
1254                   RTE_ETH_RX_OFFLOAD_RSS_HASH |
1255                   RTE_ETH_RX_OFFLOAD_VLAN_FILTER))
1256                 goto use_scalar_rx;
1257
1258 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1259         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1260             rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1261                 PMD_DRV_LOG(INFO,
1262                             "Using AVX2 vector mode receive for port %d\n",
1263                             eth_dev->data->port_id);
1264                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1265                 return bnxt_recv_pkts_vec_avx2;
1266         }
1267  #endif
1268         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1269                 PMD_DRV_LOG(INFO,
1270                             "Using SSE vector mode receive for port %d\n",
1271                             eth_dev->data->port_id);
1272                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1273                 return bnxt_recv_pkts_vec;
1274         }
1275
1276 use_scalar_rx:
1277         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1278                     eth_dev->data->port_id);
1279         PMD_DRV_LOG(INFO,
1280                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1281                     eth_dev->data->port_id,
1282                     eth_dev->data->scattered_rx,
1283                     eth_dev->data->dev_conf.rxmode.offloads);
1284 #endif
1285         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1286         return bnxt_recv_pkts;
1287 }
1288
1289 static eth_tx_burst_t
1290 bnxt_transmit_function(struct rte_eth_dev *eth_dev)
1291 {
1292         struct bnxt *bp = eth_dev->data->dev_private;
1293
1294         /* Disable vector mode TX for Stingray2 for now */
1295         if (BNXT_CHIP_SR2(bp))
1296                 return bnxt_xmit_pkts;
1297
1298 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) && \
1299         !defined(RTE_LIBRTE_IEEE1588)
1300         uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1301
1302         /*
1303          * Vector mode transmit can be enabled only if not using scatter rx
1304          * or tx offloads.
1305          */
1306         if (eth_dev->data->scattered_rx ||
1307             (offloads & ~RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) ||
1308             BNXT_TRUFLOW_EN(bp))
1309                 goto use_scalar_tx;
1310
1311 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1312         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1313             rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1314                 PMD_DRV_LOG(INFO,
1315                             "Using AVX2 vector mode transmit for port %d\n",
1316                             eth_dev->data->port_id);
1317                 return bnxt_xmit_pkts_vec_avx2;
1318         }
1319 #endif
1320         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1321                 PMD_DRV_LOG(INFO,
1322                             "Using SSE vector mode transmit for port %d\n",
1323                             eth_dev->data->port_id);
1324                 return bnxt_xmit_pkts_vec;
1325         }
1326
1327 use_scalar_tx:
1328         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1329                     eth_dev->data->port_id);
1330         PMD_DRV_LOG(INFO,
1331                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1332                     eth_dev->data->port_id,
1333                     eth_dev->data->scattered_rx,
1334                     offloads);
1335 #endif
1336         return bnxt_xmit_pkts;
1337 }
1338
1339 static int bnxt_handle_if_change_status(struct bnxt *bp)
1340 {
1341         int rc;
1342
1343         /* Since fw has undergone a reset and lost all contexts,
1344          * set fatal flag to not issue hwrm during cleanup
1345          */
1346         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1347         bnxt_uninit_resources(bp, true);
1348
1349         /* clear fatal flag so that re-init happens */
1350         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1351         rc = bnxt_init_resources(bp, true);
1352
1353         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1354
1355         return rc;
1356 }
1357
1358 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1359 {
1360         struct bnxt *bp = eth_dev->data->dev_private;
1361         int rc = 0;
1362
1363         if (!BNXT_SINGLE_PF(bp))
1364                 return -ENOTSUP;
1365
1366         if (!bp->link_info->link_up)
1367                 rc = bnxt_set_hwrm_link_config(bp, true);
1368         if (!rc)
1369                 eth_dev->data->dev_link.link_status = 1;
1370
1371         bnxt_print_link_info(eth_dev);
1372         return rc;
1373 }
1374
1375 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1376 {
1377         struct bnxt *bp = eth_dev->data->dev_private;
1378
1379         if (!BNXT_SINGLE_PF(bp))
1380                 return -ENOTSUP;
1381
1382         eth_dev->data->dev_link.link_status = 0;
1383         bnxt_set_hwrm_link_config(bp, false);
1384         bp->link_info->link_up = 0;
1385
1386         return 0;
1387 }
1388
1389 static void bnxt_free_switch_domain(struct bnxt *bp)
1390 {
1391         int rc = 0;
1392
1393         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)))
1394                 return;
1395
1396         rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1397         if (rc)
1398                 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1399                             bp->switch_domain_id, rc);
1400 }
1401
1402 static void bnxt_ptp_get_current_time(void *arg)
1403 {
1404         struct bnxt *bp = arg;
1405         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1406         int rc;
1407
1408         rc = is_bnxt_in_error(bp);
1409         if (rc)
1410                 return;
1411
1412         if (!ptp)
1413                 return;
1414
1415         bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1416                                 &ptp->current_time);
1417
1418         rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1419         if (rc != 0) {
1420                 PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n");
1421                 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1422         }
1423 }
1424
1425 static int bnxt_schedule_ptp_alarm(struct bnxt *bp)
1426 {
1427         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1428         int rc;
1429
1430         if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED)
1431                 return 0;
1432
1433         bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1434                                 &ptp->current_time);
1435
1436         rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1437         return rc;
1438 }
1439
1440 static void bnxt_cancel_ptp_alarm(struct bnxt *bp)
1441 {
1442         if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) {
1443                 rte_eal_alarm_cancel(bnxt_ptp_get_current_time, (void *)bp);
1444                 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1445         }
1446 }
1447
1448 static void bnxt_ptp_stop(struct bnxt *bp)
1449 {
1450         bnxt_cancel_ptp_alarm(bp);
1451         bp->flags2 &= ~BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1452 }
1453
1454 static int bnxt_ptp_start(struct bnxt *bp)
1455 {
1456         int rc;
1457
1458         rc = bnxt_schedule_ptp_alarm(bp);
1459         if (rc != 0) {
1460                 PMD_DRV_LOG(ERR, "Failed to schedule PTP alarm\n");
1461         } else {
1462                 bp->flags2 |= BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1463                 bp->flags2 |= BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1464         }
1465
1466         return rc;
1467 }
1468
1469 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev)
1470 {
1471         struct bnxt *bp = eth_dev->data->dev_private;
1472         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1473         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1474         struct rte_eth_link link;
1475         int ret;
1476
1477         eth_dev->data->dev_started = 0;
1478
1479         /* Prevent crashes when queues are still in use */
1480         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1481         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1482
1483         bnxt_disable_int(bp);
1484
1485         /* disable uio/vfio intr/eventfd mapping */
1486         rte_intr_disable(intr_handle);
1487
1488         /* Stop the child representors for this device */
1489         ret = bnxt_rep_stop_all(bp);
1490         if (ret != 0)
1491                 return ret;
1492
1493         /* delete the bnxt ULP port details */
1494         bnxt_ulp_port_deinit(bp);
1495
1496         bnxt_cancel_fw_health_check(bp);
1497
1498         if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1499                 bnxt_cancel_ptp_alarm(bp);
1500
1501         /* Do not bring link down during reset recovery */
1502         if (!is_bnxt_in_error(bp)) {
1503                 bnxt_dev_set_link_down_op(eth_dev);
1504                 /* Wait for link to be reset */
1505                 if (BNXT_SINGLE_PF(bp))
1506                         rte_delay_ms(500);
1507                 /* clear the recorded link status */
1508                 memset(&link, 0, sizeof(link));
1509                 rte_eth_linkstatus_set(eth_dev, &link);
1510         }
1511
1512         /* Clean queue intr-vector mapping */
1513         rte_intr_efd_disable(intr_handle);
1514         rte_intr_vec_list_free(intr_handle);
1515
1516         bnxt_hwrm_port_clr_stats(bp);
1517         bnxt_free_tx_mbufs(bp);
1518         bnxt_free_rx_mbufs(bp);
1519         /* Process any remaining notifications in default completion queue */
1520         bnxt_int_handler(eth_dev);
1521         bnxt_shutdown_nic(bp);
1522         bnxt_hwrm_if_change(bp, false);
1523
1524         bnxt_free_prev_ring_stats(bp);
1525         rte_free(bp->mark_table);
1526         bp->mark_table = NULL;
1527
1528         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1529         bp->rx_cosq_cnt = 0;
1530         /* All filters are deleted on a port stop. */
1531         if (BNXT_FLOW_XSTATS_EN(bp))
1532                 bp->flow_stat->flow_count = 0;
1533
1534         eth_dev->data->scattered_rx = 0;
1535
1536         return 0;
1537 }
1538
1539 /* Unload the driver, release resources */
1540 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1541 {
1542         struct bnxt *bp = eth_dev->data->dev_private;
1543
1544         pthread_mutex_lock(&bp->err_recovery_lock);
1545         if (bp->flags & BNXT_FLAG_FW_RESET) {
1546                 PMD_DRV_LOG(ERR,
1547                             "Adapter recovering from error..Please retry\n");
1548                 pthread_mutex_unlock(&bp->err_recovery_lock);
1549                 return -EAGAIN;
1550         }
1551         pthread_mutex_unlock(&bp->err_recovery_lock);
1552
1553         return bnxt_dev_stop(eth_dev);
1554 }
1555
1556 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1557 {
1558         struct bnxt *bp = eth_dev->data->dev_private;
1559         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1560         int vlan_mask = 0;
1561         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1562
1563         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1564                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1565                 return -EINVAL;
1566         }
1567
1568         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1569                 PMD_DRV_LOG(ERR,
1570                             "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1571                             bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1572
1573         do {
1574                 rc = bnxt_hwrm_if_change(bp, true);
1575                 if (rc == 0 || rc != -EAGAIN)
1576                         break;
1577
1578                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1579         } while (retry_cnt--);
1580
1581         if (rc)
1582                 return rc;
1583
1584         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1585                 rc = bnxt_handle_if_change_status(bp);
1586                 if (rc)
1587                         return rc;
1588         }
1589
1590         bnxt_enable_int(bp);
1591
1592         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1593
1594         rc = bnxt_start_nic(bp);
1595         if (rc)
1596                 goto error;
1597
1598         rc = bnxt_alloc_prev_ring_stats(bp);
1599         if (rc)
1600                 goto error;
1601
1602         eth_dev->data->dev_started = 1;
1603
1604         bnxt_link_update_op(eth_dev, 1);
1605
1606         if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
1607                 vlan_mask |= RTE_ETH_VLAN_FILTER_MASK;
1608         if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
1609                 vlan_mask |= RTE_ETH_VLAN_STRIP_MASK;
1610         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1611         if (rc)
1612                 goto error;
1613
1614         /* Initialize bnxt ULP port details */
1615         rc = bnxt_ulp_port_init(bp);
1616         if (rc)
1617                 goto error;
1618
1619         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1620         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1621
1622         bnxt_schedule_fw_health_check(bp);
1623
1624         if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1625                 bnxt_schedule_ptp_alarm(bp);
1626
1627         return 0;
1628
1629 error:
1630         bnxt_dev_stop(eth_dev);
1631         return rc;
1632 }
1633
1634 static void
1635 bnxt_uninit_locks(struct bnxt *bp)
1636 {
1637         pthread_mutex_destroy(&bp->flow_lock);
1638         pthread_mutex_destroy(&bp->def_cp_lock);
1639         pthread_mutex_destroy(&bp->health_check_lock);
1640         pthread_mutex_destroy(&bp->err_recovery_lock);
1641         if (bp->rep_info) {
1642                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
1643                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
1644         }
1645 }
1646
1647 static void bnxt_drv_uninit(struct bnxt *bp)
1648 {
1649         bnxt_free_leds_info(bp);
1650         bnxt_free_cos_queues(bp);
1651         bnxt_free_link_info(bp);
1652         bnxt_free_parent_info(bp);
1653         bnxt_uninit_locks(bp);
1654
1655         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1656         bp->tx_mem_zone = NULL;
1657         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1658         bp->rx_mem_zone = NULL;
1659
1660         bnxt_free_vf_info(bp);
1661         bnxt_free_pf_info(bp);
1662
1663         rte_free(bp->grp_info);
1664         bp->grp_info = NULL;
1665 }
1666
1667 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1668 {
1669         struct bnxt *bp = eth_dev->data->dev_private;
1670         int ret = 0;
1671
1672         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1673                 return 0;
1674
1675         pthread_mutex_lock(&bp->err_recovery_lock);
1676         if (bp->flags & BNXT_FLAG_FW_RESET) {
1677                 PMD_DRV_LOG(ERR,
1678                             "Adapter recovering from error...Please retry\n");
1679                 pthread_mutex_unlock(&bp->err_recovery_lock);
1680                 return -EAGAIN;
1681         }
1682         pthread_mutex_unlock(&bp->err_recovery_lock);
1683
1684         /* cancel the recovery handler before remove dev */
1685         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1686         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1687         bnxt_cancel_fc_thread(bp);
1688
1689         if (eth_dev->data->dev_started)
1690                 ret = bnxt_dev_stop(eth_dev);
1691
1692         bnxt_uninit_resources(bp, false);
1693
1694         bnxt_drv_uninit(bp);
1695
1696         return ret;
1697 }
1698
1699 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1700                                     uint32_t index)
1701 {
1702         struct bnxt *bp = eth_dev->data->dev_private;
1703         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1704         struct bnxt_vnic_info *vnic;
1705         struct bnxt_filter_info *filter, *temp_filter;
1706         uint32_t i;
1707
1708         if (is_bnxt_in_error(bp))
1709                 return;
1710
1711         /*
1712          * Loop through all VNICs from the specified filter flow pools to
1713          * remove the corresponding MAC addr filter
1714          */
1715         for (i = 0; i < bp->nr_vnics; i++) {
1716                 if (!(pool_mask & (1ULL << i)))
1717                         continue;
1718
1719                 vnic = &bp->vnic_info[i];
1720                 filter = STAILQ_FIRST(&vnic->filter);
1721                 while (filter) {
1722                         temp_filter = STAILQ_NEXT(filter, next);
1723                         if (filter->mac_index == index) {
1724                                 STAILQ_REMOVE(&vnic->filter, filter,
1725                                                 bnxt_filter_info, next);
1726                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1727                                 bnxt_free_filter(bp, filter);
1728                         }
1729                         filter = temp_filter;
1730                 }
1731         }
1732 }
1733
1734 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1735                                struct rte_ether_addr *mac_addr, uint32_t index,
1736                                uint32_t pool)
1737 {
1738         struct bnxt_filter_info *filter;
1739         int rc = 0;
1740
1741         /* Attach requested MAC address to the new l2_filter */
1742         STAILQ_FOREACH(filter, &vnic->filter, next) {
1743                 if (filter->mac_index == index) {
1744                         PMD_DRV_LOG(DEBUG,
1745                                     "MAC addr already existed for pool %d\n",
1746                                     pool);
1747                         return 0;
1748                 }
1749         }
1750
1751         filter = bnxt_alloc_filter(bp);
1752         if (!filter) {
1753                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1754                 return -ENODEV;
1755         }
1756
1757         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1758          * if the MAC that's been programmed now is a different one, then,
1759          * copy that addr to filter->l2_addr
1760          */
1761         if (mac_addr)
1762                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1763         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1764
1765         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1766         if (!rc) {
1767                 filter->mac_index = index;
1768                 if (filter->mac_index == 0)
1769                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1770                 else
1771                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1772         } else {
1773                 bnxt_free_filter(bp, filter);
1774         }
1775
1776         return rc;
1777 }
1778
1779 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1780                                 struct rte_ether_addr *mac_addr,
1781                                 uint32_t index, uint32_t pool)
1782 {
1783         struct bnxt *bp = eth_dev->data->dev_private;
1784         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1785         int rc = 0;
1786
1787         rc = is_bnxt_in_error(bp);
1788         if (rc)
1789                 return rc;
1790
1791         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1792                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1793                 return -ENOTSUP;
1794         }
1795
1796         if (!vnic) {
1797                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1798                 return -EINVAL;
1799         }
1800
1801         /* Filter settings will get applied when port is started */
1802         if (!eth_dev->data->dev_started)
1803                 return 0;
1804
1805         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1806
1807         return rc;
1808 }
1809
1810 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1811 {
1812         int rc = 0;
1813         struct bnxt *bp = eth_dev->data->dev_private;
1814         struct rte_eth_link new;
1815         int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1816                         BNXT_MIN_LINK_WAIT_CNT;
1817
1818         rc = is_bnxt_in_error(bp);
1819         if (rc)
1820                 return rc;
1821
1822         memset(&new, 0, sizeof(new));
1823
1824         if (bp->link_info == NULL)
1825                 goto out;
1826
1827         do {
1828                 /* Retrieve link info from hardware */
1829                 rc = bnxt_get_hwrm_link_config(bp, &new);
1830                 if (rc) {
1831                         new.link_speed = RTE_ETH_LINK_SPEED_100M;
1832                         new.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
1833                         PMD_DRV_LOG(ERR,
1834                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1835                         goto out;
1836                 }
1837
1838                 if (!wait_to_complete || new.link_status)
1839                         break;
1840
1841                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1842         } while (cnt--);
1843
1844         /* Only single function PF can bring phy down.
1845          * When port is stopped, report link down for VF/MH/NPAR functions.
1846          */
1847         if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1848                 memset(&new, 0, sizeof(new));
1849
1850 out:
1851         /* Timed out or success */
1852         if (new.link_status != eth_dev->data->dev_link.link_status ||
1853             new.link_speed != eth_dev->data->dev_link.link_speed) {
1854                 rte_eth_linkstatus_set(eth_dev, &new);
1855                 bnxt_print_link_info(eth_dev);
1856         }
1857
1858         return rc;
1859 }
1860
1861 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1862 {
1863         struct bnxt *bp = eth_dev->data->dev_private;
1864         struct bnxt_vnic_info *vnic;
1865         uint32_t old_flags;
1866         int rc;
1867
1868         rc = is_bnxt_in_error(bp);
1869         if (rc)
1870                 return rc;
1871
1872         /* Filter settings will get applied when port is started */
1873         if (!eth_dev->data->dev_started)
1874                 return 0;
1875
1876         if (bp->vnic_info == NULL)
1877                 return 0;
1878
1879         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1880
1881         old_flags = vnic->flags;
1882         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1883         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1884         if (rc != 0)
1885                 vnic->flags = old_flags;
1886
1887         return rc;
1888 }
1889
1890 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1891 {
1892         struct bnxt *bp = eth_dev->data->dev_private;
1893         struct bnxt_vnic_info *vnic;
1894         uint32_t old_flags;
1895         int rc;
1896
1897         rc = is_bnxt_in_error(bp);
1898         if (rc)
1899                 return rc;
1900
1901         /* Filter settings will get applied when port is started */
1902         if (!eth_dev->data->dev_started)
1903                 return 0;
1904
1905         if (bp->vnic_info == NULL)
1906                 return 0;
1907
1908         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1909
1910         old_flags = vnic->flags;
1911         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1912         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1913         if (rc != 0)
1914                 vnic->flags = old_flags;
1915
1916         return rc;
1917 }
1918
1919 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1920 {
1921         struct bnxt *bp = eth_dev->data->dev_private;
1922         struct bnxt_vnic_info *vnic;
1923         uint32_t old_flags;
1924         int rc;
1925
1926         rc = is_bnxt_in_error(bp);
1927         if (rc)
1928                 return rc;
1929
1930         /* Filter settings will get applied when port is started */
1931         if (!eth_dev->data->dev_started)
1932                 return 0;
1933
1934         if (bp->vnic_info == NULL)
1935                 return 0;
1936
1937         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1938
1939         old_flags = vnic->flags;
1940         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1941         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1942         if (rc != 0)
1943                 vnic->flags = old_flags;
1944
1945         return rc;
1946 }
1947
1948 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1949 {
1950         struct bnxt *bp = eth_dev->data->dev_private;
1951         struct bnxt_vnic_info *vnic;
1952         uint32_t old_flags;
1953         int rc;
1954
1955         rc = is_bnxt_in_error(bp);
1956         if (rc)
1957                 return rc;
1958
1959         /* Filter settings will get applied when port is started */
1960         if (!eth_dev->data->dev_started)
1961                 return 0;
1962
1963         if (bp->vnic_info == NULL)
1964                 return 0;
1965
1966         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1967
1968         old_flags = vnic->flags;
1969         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1970         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1971         if (rc != 0)
1972                 vnic->flags = old_flags;
1973
1974         return rc;
1975 }
1976
1977 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1978 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1979 {
1980         if (qid >= bp->rx_nr_rings)
1981                 return NULL;
1982
1983         return bp->eth_dev->data->rx_queues[qid];
1984 }
1985
1986 /* Return rxq corresponding to a given rss table ring/group ID. */
1987 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1988 {
1989         struct bnxt_rx_queue *rxq;
1990         unsigned int i;
1991
1992         if (!BNXT_HAS_RING_GRPS(bp)) {
1993                 for (i = 0; i < bp->rx_nr_rings; i++) {
1994                         rxq = bp->eth_dev->data->rx_queues[i];
1995                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1996                                 return rxq->index;
1997                 }
1998         } else {
1999                 for (i = 0; i < bp->rx_nr_rings; i++) {
2000                         if (bp->grp_info[i].fw_grp_id == fwr)
2001                                 return i;
2002                 }
2003         }
2004
2005         return INVALID_HW_RING_ID;
2006 }
2007
2008 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
2009                             struct rte_eth_rss_reta_entry64 *reta_conf,
2010                             uint16_t reta_size)
2011 {
2012         struct bnxt *bp = eth_dev->data->dev_private;
2013         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2014         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2015         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
2016         uint16_t idx, sft;
2017         int i, rc;
2018
2019         rc = is_bnxt_in_error(bp);
2020         if (rc)
2021                 return rc;
2022
2023         if (!vnic->rss_table)
2024                 return -EINVAL;
2025
2026         if (!(dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG))
2027                 return -EINVAL;
2028
2029         if (reta_size != tbl_size) {
2030                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2031                         "(%d) must equal the size supported by the hardware "
2032                         "(%d)\n", reta_size, tbl_size);
2033                 return -EINVAL;
2034         }
2035
2036         for (i = 0; i < reta_size; i++) {
2037                 struct bnxt_rx_queue *rxq;
2038
2039                 idx = i / RTE_ETH_RETA_GROUP_SIZE;
2040                 sft = i % RTE_ETH_RETA_GROUP_SIZE;
2041
2042                 if (!(reta_conf[idx].mask & (1ULL << sft)))
2043                         continue;
2044
2045                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
2046                 if (!rxq) {
2047                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
2048                         return -EINVAL;
2049                 }
2050
2051                 if (BNXT_CHIP_P5(bp)) {
2052                         vnic->rss_table[i * 2] =
2053                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
2054                         vnic->rss_table[i * 2 + 1] =
2055                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
2056                 } else {
2057                         vnic->rss_table[i] =
2058                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
2059                 }
2060         }
2061
2062         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2063         return rc;
2064 }
2065
2066 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
2067                               struct rte_eth_rss_reta_entry64 *reta_conf,
2068                               uint16_t reta_size)
2069 {
2070         struct bnxt *bp = eth_dev->data->dev_private;
2071         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2072         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
2073         uint16_t idx, sft, i;
2074         int rc;
2075
2076         rc = is_bnxt_in_error(bp);
2077         if (rc)
2078                 return rc;
2079
2080         if (!vnic)
2081                 return -EINVAL;
2082         if (!vnic->rss_table)
2083                 return -EINVAL;
2084
2085         if (reta_size != tbl_size) {
2086                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2087                         "(%d) must equal the size supported by the hardware "
2088                         "(%d)\n", reta_size, tbl_size);
2089                 return -EINVAL;
2090         }
2091
2092         for (idx = 0, i = 0; i < reta_size; i++) {
2093                 idx = i / RTE_ETH_RETA_GROUP_SIZE;
2094                 sft = i % RTE_ETH_RETA_GROUP_SIZE;
2095
2096                 if (reta_conf[idx].mask & (1ULL << sft)) {
2097                         uint16_t qid;
2098
2099                         if (BNXT_CHIP_P5(bp))
2100                                 qid = bnxt_rss_to_qid(bp,
2101                                                       vnic->rss_table[i * 2]);
2102                         else
2103                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
2104
2105                         if (qid == INVALID_HW_RING_ID) {
2106                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
2107                                 return -EINVAL;
2108                         }
2109                         reta_conf[idx].reta[sft] = qid;
2110                 }
2111         }
2112
2113         return 0;
2114 }
2115
2116 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
2117                                    struct rte_eth_rss_conf *rss_conf)
2118 {
2119         struct bnxt *bp = eth_dev->data->dev_private;
2120         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2121         struct bnxt_vnic_info *vnic;
2122         int rc;
2123
2124         rc = is_bnxt_in_error(bp);
2125         if (rc)
2126                 return rc;
2127
2128         /*
2129          * If RSS enablement were different than dev_configure,
2130          * then return -EINVAL
2131          */
2132         if (dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
2133                 if (!rss_conf->rss_hf)
2134                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
2135         } else {
2136                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
2137                         return -EINVAL;
2138         }
2139
2140         bp->flags |= BNXT_FLAG_UPDATE_HASH;
2141
2142         /* Update the default RSS VNIC(s) */
2143         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2144         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
2145         vnic->hash_mode =
2146                 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
2147                                             RTE_ETH_RSS_LEVEL(rss_conf->rss_hf));
2148
2149         /* Cache the hash function */
2150         bp->rss_conf.rss_hf = rss_conf->rss_hf;
2151
2152         /*
2153          * If hashkey is not specified, use the previously configured
2154          * hashkey
2155          */
2156         if (!rss_conf->rss_key)
2157                 goto rss_config;
2158
2159         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
2160                 PMD_DRV_LOG(ERR,
2161                             "Invalid hashkey length, should be %d bytes\n",
2162                             HW_HASH_KEY_SIZE);
2163                 return -EINVAL;
2164         }
2165         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
2166
2167         /* Cache the hash key */
2168         memcpy(bp->rss_conf.rss_key, rss_conf->rss_key, HW_HASH_KEY_SIZE);
2169
2170 rss_config:
2171         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2172         return rc;
2173 }
2174
2175 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
2176                                      struct rte_eth_rss_conf *rss_conf)
2177 {
2178         struct bnxt *bp = eth_dev->data->dev_private;
2179         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2180         int len, rc;
2181         uint32_t hash_types;
2182
2183         rc = is_bnxt_in_error(bp);
2184         if (rc)
2185                 return rc;
2186
2187         /* RSS configuration is the same for all VNICs */
2188         if (vnic && vnic->rss_hash_key) {
2189                 if (rss_conf->rss_key) {
2190                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
2191                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
2192                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
2193                 }
2194
2195                 hash_types = vnic->hash_type;
2196                 rss_conf->rss_hf = 0;
2197                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
2198                         rss_conf->rss_hf |= RTE_ETH_RSS_IPV4;
2199                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
2200                 }
2201                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
2202                         rss_conf->rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_TCP;
2203                         hash_types &=
2204                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
2205                 }
2206                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
2207                         rss_conf->rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_UDP;
2208                         hash_types &=
2209                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
2210                 }
2211                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
2212                         rss_conf->rss_hf |= RTE_ETH_RSS_IPV6;
2213                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
2214                 }
2215                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
2216                         rss_conf->rss_hf |= RTE_ETH_RSS_NONFRAG_IPV6_TCP;
2217                         hash_types &=
2218                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
2219                 }
2220                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
2221                         rss_conf->rss_hf |= RTE_ETH_RSS_NONFRAG_IPV6_UDP;
2222                         hash_types &=
2223                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2224                 }
2225
2226                 rss_conf->rss_hf |=
2227                         bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2228
2229                 if (hash_types) {
2230                         PMD_DRV_LOG(ERR,
2231                                 "Unknown RSS config from firmware (%08x), RSS disabled",
2232                                 vnic->hash_type);
2233                         return -ENOTSUP;
2234                 }
2235         } else {
2236                 rss_conf->rss_hf = 0;
2237         }
2238         return 0;
2239 }
2240
2241 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2242                                struct rte_eth_fc_conf *fc_conf)
2243 {
2244         struct bnxt *bp = dev->data->dev_private;
2245         struct rte_eth_link link_info;
2246         int rc;
2247
2248         rc = is_bnxt_in_error(bp);
2249         if (rc)
2250                 return rc;
2251
2252         rc = bnxt_get_hwrm_link_config(bp, &link_info);
2253         if (rc)
2254                 return rc;
2255
2256         memset(fc_conf, 0, sizeof(*fc_conf));
2257         if (bp->link_info->auto_pause)
2258                 fc_conf->autoneg = 1;
2259         switch (bp->link_info->pause) {
2260         case 0:
2261                 fc_conf->mode = RTE_ETH_FC_NONE;
2262                 break;
2263         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2264                 fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
2265                 break;
2266         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2267                 fc_conf->mode = RTE_ETH_FC_RX_PAUSE;
2268                 break;
2269         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2270                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2271                 fc_conf->mode = RTE_ETH_FC_FULL;
2272                 break;
2273         }
2274         return 0;
2275 }
2276
2277 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2278                                struct rte_eth_fc_conf *fc_conf)
2279 {
2280         struct bnxt *bp = dev->data->dev_private;
2281         int rc;
2282
2283         rc = is_bnxt_in_error(bp);
2284         if (rc)
2285                 return rc;
2286
2287         if (!BNXT_SINGLE_PF(bp)) {
2288                 PMD_DRV_LOG(ERR,
2289                             "Flow Control Settings cannot be modified on VF or on shared PF\n");
2290                 return -ENOTSUP;
2291         }
2292
2293         switch (fc_conf->mode) {
2294         case RTE_ETH_FC_NONE:
2295                 bp->link_info->auto_pause = 0;
2296                 bp->link_info->force_pause = 0;
2297                 break;
2298         case RTE_ETH_FC_RX_PAUSE:
2299                 if (fc_conf->autoneg) {
2300                         bp->link_info->auto_pause =
2301                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2302                         bp->link_info->force_pause = 0;
2303                 } else {
2304                         bp->link_info->auto_pause = 0;
2305                         bp->link_info->force_pause =
2306                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2307                 }
2308                 break;
2309         case RTE_ETH_FC_TX_PAUSE:
2310                 if (fc_conf->autoneg) {
2311                         bp->link_info->auto_pause =
2312                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2313                         bp->link_info->force_pause = 0;
2314                 } else {
2315                         bp->link_info->auto_pause = 0;
2316                         bp->link_info->force_pause =
2317                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2318                 }
2319                 break;
2320         case RTE_ETH_FC_FULL:
2321                 if (fc_conf->autoneg) {
2322                         bp->link_info->auto_pause =
2323                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2324                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2325                         bp->link_info->force_pause = 0;
2326                 } else {
2327                         bp->link_info->auto_pause = 0;
2328                         bp->link_info->force_pause =
2329                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2330                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2331                 }
2332                 break;
2333         }
2334         return bnxt_set_hwrm_link_config(bp, true);
2335 }
2336
2337 /* Add UDP tunneling port */
2338 static int
2339 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2340                          struct rte_eth_udp_tunnel *udp_tunnel)
2341 {
2342         struct bnxt *bp = eth_dev->data->dev_private;
2343         uint16_t tunnel_type = 0;
2344         int rc = 0;
2345
2346         rc = is_bnxt_in_error(bp);
2347         if (rc)
2348                 return rc;
2349
2350         switch (udp_tunnel->prot_type) {
2351         case RTE_ETH_TUNNEL_TYPE_VXLAN:
2352                 if (bp->vxlan_port_cnt) {
2353                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2354                                 udp_tunnel->udp_port);
2355                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2356                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2357                                 return -ENOSPC;
2358                         }
2359                         bp->vxlan_port_cnt++;
2360                         return 0;
2361                 }
2362                 tunnel_type =
2363                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2364                 break;
2365         case RTE_ETH_TUNNEL_TYPE_GENEVE:
2366                 if (bp->geneve_port_cnt) {
2367                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2368                                 udp_tunnel->udp_port);
2369                         if (bp->geneve_port != udp_tunnel->udp_port) {
2370                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2371                                 return -ENOSPC;
2372                         }
2373                         bp->geneve_port_cnt++;
2374                         return 0;
2375                 }
2376                 tunnel_type =
2377                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2378                 break;
2379         default:
2380                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2381                 return -ENOTSUP;
2382         }
2383         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2384                                              tunnel_type);
2385
2386         if (rc != 0)
2387                 return rc;
2388
2389         if (tunnel_type ==
2390             HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN)
2391                 bp->vxlan_port_cnt++;
2392
2393         if (tunnel_type ==
2394             HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE)
2395                 bp->geneve_port_cnt++;
2396
2397         return rc;
2398 }
2399
2400 static int
2401 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2402                          struct rte_eth_udp_tunnel *udp_tunnel)
2403 {
2404         struct bnxt *bp = eth_dev->data->dev_private;
2405         uint16_t tunnel_type = 0;
2406         uint16_t port = 0;
2407         int rc = 0;
2408
2409         rc = is_bnxt_in_error(bp);
2410         if (rc)
2411                 return rc;
2412
2413         switch (udp_tunnel->prot_type) {
2414         case RTE_ETH_TUNNEL_TYPE_VXLAN:
2415                 if (!bp->vxlan_port_cnt) {
2416                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2417                         return -EINVAL;
2418                 }
2419                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2420                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2421                                 udp_tunnel->udp_port, bp->vxlan_port);
2422                         return -EINVAL;
2423                 }
2424                 if (--bp->vxlan_port_cnt)
2425                         return 0;
2426
2427                 tunnel_type =
2428                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2429                 port = bp->vxlan_fw_dst_port_id;
2430                 break;
2431         case RTE_ETH_TUNNEL_TYPE_GENEVE:
2432                 if (!bp->geneve_port_cnt) {
2433                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2434                         return -EINVAL;
2435                 }
2436                 if (bp->geneve_port != udp_tunnel->udp_port) {
2437                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2438                                 udp_tunnel->udp_port, bp->geneve_port);
2439                         return -EINVAL;
2440                 }
2441                 if (--bp->geneve_port_cnt)
2442                         return 0;
2443
2444                 tunnel_type =
2445                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2446                 port = bp->geneve_fw_dst_port_id;
2447                 break;
2448         default:
2449                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2450                 return -ENOTSUP;
2451         }
2452
2453         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2454         return rc;
2455 }
2456
2457 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2458 {
2459         struct bnxt_filter_info *filter;
2460         struct bnxt_vnic_info *vnic;
2461         int rc = 0;
2462         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2463
2464         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2465         filter = STAILQ_FIRST(&vnic->filter);
2466         while (filter) {
2467                 /* Search for this matching MAC+VLAN filter */
2468                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2469                         /* Delete the filter */
2470                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2471                         if (rc)
2472                                 return rc;
2473                         STAILQ_REMOVE(&vnic->filter, filter,
2474                                       bnxt_filter_info, next);
2475                         bnxt_free_filter(bp, filter);
2476                         PMD_DRV_LOG(INFO,
2477                                     "Deleted vlan filter for %d\n",
2478                                     vlan_id);
2479                         return 0;
2480                 }
2481                 filter = STAILQ_NEXT(filter, next);
2482         }
2483         return -ENOENT;
2484 }
2485
2486 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2487 {
2488         struct bnxt_filter_info *filter;
2489         struct bnxt_vnic_info *vnic;
2490         int rc = 0;
2491         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2492                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2493         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2494
2495         /* Implementation notes on the use of VNIC in this command:
2496          *
2497          * By default, these filters belong to default vnic for the function.
2498          * Once these filters are set up, only destination VNIC can be modified.
2499          * If the destination VNIC is not specified in this command,
2500          * then the HWRM shall only create an l2 context id.
2501          */
2502
2503         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2504         filter = STAILQ_FIRST(&vnic->filter);
2505         /* Check if the VLAN has already been added */
2506         while (filter) {
2507                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2508                         return -EEXIST;
2509
2510                 filter = STAILQ_NEXT(filter, next);
2511         }
2512
2513         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2514          * command to create MAC+VLAN filter with the right flags, enables set.
2515          */
2516         filter = bnxt_alloc_filter(bp);
2517         if (!filter) {
2518                 PMD_DRV_LOG(ERR,
2519                             "MAC/VLAN filter alloc failed\n");
2520                 return -ENOMEM;
2521         }
2522         /* MAC + VLAN ID filter */
2523         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2524          * untagged packets are received
2525          *
2526          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2527          * packets and only the programmed vlan's packets are received
2528          */
2529         filter->l2_ivlan = vlan_id;
2530         filter->l2_ivlan_mask = 0x0FFF;
2531         filter->enables |= en;
2532         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2533
2534         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2535         if (rc) {
2536                 /* Free the newly allocated filter as we were
2537                  * not able to create the filter in hardware.
2538                  */
2539                 bnxt_free_filter(bp, filter);
2540                 return rc;
2541         }
2542
2543         filter->mac_index = 0;
2544         /* Add this new filter to the list */
2545         if (vlan_id == 0)
2546                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2547         else
2548                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2549
2550         PMD_DRV_LOG(INFO,
2551                     "Added Vlan filter for %d\n", vlan_id);
2552         return rc;
2553 }
2554
2555 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2556                 uint16_t vlan_id, int on)
2557 {
2558         struct bnxt *bp = eth_dev->data->dev_private;
2559         int rc;
2560
2561         rc = is_bnxt_in_error(bp);
2562         if (rc)
2563                 return rc;
2564
2565         if (!eth_dev->data->dev_started) {
2566                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2567                 return -EINVAL;
2568         }
2569
2570         /* These operations apply to ALL existing MAC/VLAN filters */
2571         if (on)
2572                 return bnxt_add_vlan_filter(bp, vlan_id);
2573         else
2574                 return bnxt_del_vlan_filter(bp, vlan_id);
2575 }
2576
2577 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2578                                     struct bnxt_vnic_info *vnic)
2579 {
2580         struct bnxt_filter_info *filter;
2581         int rc;
2582
2583         filter = STAILQ_FIRST(&vnic->filter);
2584         while (filter) {
2585                 if (filter->mac_index == 0 &&
2586                     !memcmp(filter->l2_addr, bp->mac_addr,
2587                             RTE_ETHER_ADDR_LEN)) {
2588                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2589                         if (!rc) {
2590                                 STAILQ_REMOVE(&vnic->filter, filter,
2591                                               bnxt_filter_info, next);
2592                                 bnxt_free_filter(bp, filter);
2593                         }
2594                         return rc;
2595                 }
2596                 filter = STAILQ_NEXT(filter, next);
2597         }
2598         return 0;
2599 }
2600
2601 static int
2602 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2603 {
2604         struct bnxt_vnic_info *vnic;
2605         unsigned int i;
2606         int rc;
2607
2608         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2609         if (!(rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)) {
2610                 /* Remove any VLAN filters programmed */
2611                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2612                         bnxt_del_vlan_filter(bp, i);
2613
2614                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2615                 if (rc)
2616                         return rc;
2617         } else {
2618                 /* Default filter will allow packets that match the
2619                  * dest mac. So, it has to be deleted, otherwise, we
2620                  * will endup receiving vlan packets for which the
2621                  * filter is not programmed, when hw-vlan-filter
2622                  * configuration is ON
2623                  */
2624                 bnxt_del_dflt_mac_filter(bp, vnic);
2625                 /* This filter will allow only untagged packets */
2626                 bnxt_add_vlan_filter(bp, 0);
2627         }
2628         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2629                     !!(rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER));
2630
2631         return 0;
2632 }
2633
2634 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2635 {
2636         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2637         unsigned int i;
2638         int rc;
2639
2640         /* Destroy vnic filters and vnic */
2641         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2642             RTE_ETH_RX_OFFLOAD_VLAN_FILTER) {
2643                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2644                         bnxt_del_vlan_filter(bp, i);
2645         }
2646         bnxt_del_dflt_mac_filter(bp, vnic);
2647
2648         rc = bnxt_hwrm_vnic_ctx_free(bp, vnic);
2649         if (rc)
2650                 return rc;
2651
2652         rc = bnxt_hwrm_vnic_free(bp, vnic);
2653         if (rc)
2654                 return rc;
2655
2656         rte_free(vnic->fw_grp_ids);
2657         vnic->fw_grp_ids = NULL;
2658
2659         vnic->rx_queue_cnt = 0;
2660
2661         return 0;
2662 }
2663
2664 static int
2665 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2666 {
2667         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2668         int rc;
2669
2670         /* Destroy, recreate and reconfigure the default vnic */
2671         rc = bnxt_free_one_vnic(bp, 0);
2672         if (rc)
2673                 return rc;
2674
2675         /* default vnic 0 */
2676         rc = bnxt_setup_one_vnic(bp, 0);
2677         if (rc)
2678                 return rc;
2679
2680         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2681             RTE_ETH_RX_OFFLOAD_VLAN_FILTER) {
2682                 rc = bnxt_add_vlan_filter(bp, 0);
2683                 if (rc)
2684                         return rc;
2685                 rc = bnxt_restore_vlan_filters(bp);
2686                 if (rc)
2687                         return rc;
2688         } else {
2689                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2690                 if (rc)
2691                         return rc;
2692         }
2693
2694         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2695         if (rc)
2696                 return rc;
2697
2698         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2699                     !!(rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP));
2700
2701         return rc;
2702 }
2703
2704 static int
2705 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2706 {
2707         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2708         struct bnxt *bp = dev->data->dev_private;
2709         int rc;
2710
2711         rc = is_bnxt_in_error(bp);
2712         if (rc)
2713                 return rc;
2714
2715         /* Filter settings will get applied when port is started */
2716         if (!dev->data->dev_started)
2717                 return 0;
2718
2719         if (mask & RTE_ETH_VLAN_FILTER_MASK) {
2720                 /* Enable or disable VLAN filtering */
2721                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2722                 if (rc)
2723                         return rc;
2724         }
2725
2726         if (mask & RTE_ETH_VLAN_STRIP_MASK) {
2727                 /* Enable or disable VLAN stripping */
2728                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2729                 if (rc)
2730                         return rc;
2731         }
2732
2733         if (mask & RTE_ETH_VLAN_EXTEND_MASK) {
2734                 if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND)
2735                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2736                 else
2737                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2738         }
2739
2740         return 0;
2741 }
2742
2743 static int
2744 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2745                       uint16_t tpid)
2746 {
2747         struct bnxt *bp = dev->data->dev_private;
2748         int qinq = dev->data->dev_conf.rxmode.offloads &
2749                    RTE_ETH_RX_OFFLOAD_VLAN_EXTEND;
2750
2751         if (vlan_type != RTE_ETH_VLAN_TYPE_INNER &&
2752             vlan_type != RTE_ETH_VLAN_TYPE_OUTER) {
2753                 PMD_DRV_LOG(ERR,
2754                             "Unsupported vlan type.");
2755                 return -EINVAL;
2756         }
2757         if (!qinq) {
2758                 PMD_DRV_LOG(ERR,
2759                             "QinQ not enabled. Needs to be ON as we can "
2760                             "accelerate only outer vlan\n");
2761                 return -EINVAL;
2762         }
2763
2764         if (vlan_type == RTE_ETH_VLAN_TYPE_OUTER) {
2765                 switch (tpid) {
2766                 case RTE_ETHER_TYPE_QINQ:
2767                         bp->outer_tpid_bd =
2768                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2769                                 break;
2770                 case RTE_ETHER_TYPE_VLAN:
2771                         bp->outer_tpid_bd =
2772                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2773                                 break;
2774                 case RTE_ETHER_TYPE_QINQ1:
2775                         bp->outer_tpid_bd =
2776                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2777                                 break;
2778                 case RTE_ETHER_TYPE_QINQ2:
2779                         bp->outer_tpid_bd =
2780                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2781                                 break;
2782                 case RTE_ETHER_TYPE_QINQ3:
2783                         bp->outer_tpid_bd =
2784                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2785                                 break;
2786                 default:
2787                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2788                         return -EINVAL;
2789                 }
2790                 bp->outer_tpid_bd |= tpid;
2791                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2792         } else if (vlan_type == RTE_ETH_VLAN_TYPE_INNER) {
2793                 PMD_DRV_LOG(ERR,
2794                             "Can accelerate only outer vlan in QinQ\n");
2795                 return -EINVAL;
2796         }
2797
2798         return 0;
2799 }
2800
2801 static int
2802 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2803                              struct rte_ether_addr *addr)
2804 {
2805         struct bnxt *bp = dev->data->dev_private;
2806         /* Default Filter is tied to VNIC 0 */
2807         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2808         int rc;
2809
2810         rc = is_bnxt_in_error(bp);
2811         if (rc)
2812                 return rc;
2813
2814         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2815                 return -EPERM;
2816
2817         if (rte_is_zero_ether_addr(addr))
2818                 return -EINVAL;
2819
2820         /* Filter settings will get applied when port is started */
2821         if (!dev->data->dev_started)
2822                 return 0;
2823
2824         /* Check if the requested MAC is already added */
2825         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2826                 return 0;
2827
2828         /* Destroy filter and re-create it */
2829         bnxt_del_dflt_mac_filter(bp, vnic);
2830
2831         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2832         if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) {
2833                 /* This filter will allow only untagged packets */
2834                 rc = bnxt_add_vlan_filter(bp, 0);
2835         } else {
2836                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2837         }
2838
2839         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2840         return rc;
2841 }
2842
2843 static int
2844 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2845                           struct rte_ether_addr *mc_addr_set,
2846                           uint32_t nb_mc_addr)
2847 {
2848         struct bnxt *bp = eth_dev->data->dev_private;
2849         struct bnxt_vnic_info *vnic;
2850         uint32_t i = 0;
2851         int rc;
2852
2853         rc = is_bnxt_in_error(bp);
2854         if (rc)
2855                 return rc;
2856
2857         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2858
2859         bp->nb_mc_addr = nb_mc_addr;
2860
2861         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2862                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2863                 goto allmulti;
2864         }
2865
2866         /* TODO Check for Duplicate mcast addresses */
2867         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2868         for (i = 0; i < nb_mc_addr; i++)
2869                 rte_ether_addr_copy(&mc_addr_set[i], &bp->mcast_addr_list[i]);
2870
2871         if (bp->nb_mc_addr)
2872                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2873         else
2874                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2875
2876 allmulti:
2877         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2878 }
2879
2880 static int
2881 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2882 {
2883         struct bnxt *bp = dev->data->dev_private;
2884         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2885         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2886         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2887         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2888         int ret;
2889
2890         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2891                         fw_major, fw_minor, fw_updt, fw_rsvd);
2892         if (ret < 0)
2893                 return -EINVAL;
2894
2895         ret += 1; /* add the size of '\0' */
2896         if (fw_size < (size_t)ret)
2897                 return ret;
2898         else
2899                 return 0;
2900 }
2901
2902 static void
2903 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2904         struct rte_eth_rxq_info *qinfo)
2905 {
2906         struct bnxt *bp = dev->data->dev_private;
2907         struct bnxt_rx_queue *rxq;
2908
2909         if (is_bnxt_in_error(bp))
2910                 return;
2911
2912         rxq = dev->data->rx_queues[queue_id];
2913
2914         qinfo->mp = rxq->mb_pool;
2915         qinfo->scattered_rx = dev->data->scattered_rx;
2916         qinfo->nb_desc = rxq->nb_rx_desc;
2917
2918         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2919         qinfo->conf.rx_drop_en = rxq->drop_en;
2920         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2921         qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2922 }
2923
2924 static void
2925 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2926         struct rte_eth_txq_info *qinfo)
2927 {
2928         struct bnxt *bp = dev->data->dev_private;
2929         struct bnxt_tx_queue *txq;
2930
2931         if (is_bnxt_in_error(bp))
2932                 return;
2933
2934         txq = dev->data->tx_queues[queue_id];
2935
2936         qinfo->nb_desc = txq->nb_tx_desc;
2937
2938         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2939         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2940         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2941
2942         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2943         qinfo->conf.tx_rs_thresh = 0;
2944         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2945         qinfo->conf.offloads = txq->offloads;
2946 }
2947
2948 static const struct {
2949         eth_rx_burst_t pkt_burst;
2950         const char *info;
2951 } bnxt_rx_burst_info[] = {
2952         {bnxt_recv_pkts,                "Scalar"},
2953 #if defined(RTE_ARCH_X86)
2954         {bnxt_recv_pkts_vec,            "Vector SSE"},
2955 #endif
2956 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2957         {bnxt_recv_pkts_vec_avx2,       "Vector AVX2"},
2958 #endif
2959 #if defined(RTE_ARCH_ARM64)
2960         {bnxt_recv_pkts_vec,            "Vector Neon"},
2961 #endif
2962 };
2963
2964 static int
2965 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2966                        struct rte_eth_burst_mode *mode)
2967 {
2968         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2969         size_t i;
2970
2971         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2972                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2973                         snprintf(mode->info, sizeof(mode->info), "%s",
2974                                  bnxt_rx_burst_info[i].info);
2975                         return 0;
2976                 }
2977         }
2978
2979         return -EINVAL;
2980 }
2981
2982 static const struct {
2983         eth_tx_burst_t pkt_burst;
2984         const char *info;
2985 } bnxt_tx_burst_info[] = {
2986         {bnxt_xmit_pkts,                "Scalar"},
2987 #if defined(RTE_ARCH_X86)
2988         {bnxt_xmit_pkts_vec,            "Vector SSE"},
2989 #endif
2990 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2991         {bnxt_xmit_pkts_vec_avx2,       "Vector AVX2"},
2992 #endif
2993 #if defined(RTE_ARCH_ARM64)
2994         {bnxt_xmit_pkts_vec,            "Vector Neon"},
2995 #endif
2996 };
2997
2998 static int
2999 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3000                        struct rte_eth_burst_mode *mode)
3001 {
3002         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3003         size_t i;
3004
3005         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
3006                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
3007                         snprintf(mode->info, sizeof(mode->info), "%s",
3008                                  bnxt_tx_burst_info[i].info);
3009                         return 0;
3010                 }
3011         }
3012
3013         return -EINVAL;
3014 }
3015
3016 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
3017 {
3018         uint32_t overhead = BNXT_MAX_PKT_LEN - BNXT_MAX_MTU;
3019         struct bnxt *bp = eth_dev->data->dev_private;
3020         uint32_t new_pkt_size;
3021         uint32_t rc;
3022         uint32_t i;
3023
3024         rc = is_bnxt_in_error(bp);
3025         if (rc)
3026                 return rc;
3027
3028         /* Exit if receive queues are not configured yet */
3029         if (!eth_dev->data->nb_rx_queues)
3030                 return rc;
3031
3032         new_pkt_size = new_mtu + overhead;
3033
3034         /*
3035          * Disallow any MTU change that would require scattered receive support
3036          * if it is not already enabled.
3037          */
3038         if (eth_dev->data->dev_started &&
3039             !eth_dev->data->scattered_rx &&
3040             (new_pkt_size >
3041              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
3042                 PMD_DRV_LOG(ERR,
3043                             "MTU change would require scattered rx support. ");
3044                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
3045                 return -EINVAL;
3046         }
3047
3048         if (new_mtu > RTE_ETHER_MTU)
3049                 bp->flags |= BNXT_FLAG_JUMBO;
3050         else
3051                 bp->flags &= ~BNXT_FLAG_JUMBO;
3052
3053         /* Is there a change in mtu setting? */
3054         if (eth_dev->data->mtu == new_mtu)
3055                 return rc;
3056
3057         for (i = 0; i < bp->nr_vnics; i++) {
3058                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3059                 uint16_t size = 0;
3060
3061                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
3062                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
3063                 if (rc)
3064                         break;
3065
3066                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
3067                 size -= RTE_PKTMBUF_HEADROOM;
3068
3069                 if (size < new_mtu) {
3070                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
3071                         if (rc)
3072                                 return rc;
3073                 }
3074         }
3075
3076         if (bnxt_hwrm_config_host_mtu(bp))
3077                 PMD_DRV_LOG(WARNING, "Failed to configure host MTU\n");
3078
3079         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
3080
3081         return rc;
3082 }
3083
3084 static int
3085 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
3086 {
3087         struct bnxt *bp = dev->data->dev_private;
3088         uint16_t vlan = bp->vlan;
3089         int rc;
3090
3091         rc = is_bnxt_in_error(bp);
3092         if (rc)
3093                 return rc;
3094
3095         if (!BNXT_SINGLE_PF(bp)) {
3096                 PMD_DRV_LOG(ERR, "PVID cannot be modified on VF or on shared PF\n");
3097                 return -ENOTSUP;
3098         }
3099         bp->vlan = on ? pvid : 0;
3100
3101         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
3102         if (rc)
3103                 bp->vlan = vlan;
3104         return rc;
3105 }
3106
3107 static int
3108 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
3109 {
3110         struct bnxt *bp = dev->data->dev_private;
3111         int rc;
3112
3113         rc = is_bnxt_in_error(bp);
3114         if (rc)
3115                 return rc;
3116
3117         return bnxt_hwrm_port_led_cfg(bp, true);
3118 }
3119
3120 static int
3121 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
3122 {
3123         struct bnxt *bp = dev->data->dev_private;
3124         int rc;
3125
3126         rc = is_bnxt_in_error(bp);
3127         if (rc)
3128                 return rc;
3129
3130         return bnxt_hwrm_port_led_cfg(bp, false);
3131 }
3132
3133 static uint32_t
3134 bnxt_rx_queue_count_op(void *rx_queue)
3135 {
3136         struct bnxt *bp;
3137         struct bnxt_cp_ring_info *cpr;
3138         uint32_t desc = 0, raw_cons, cp_ring_size;
3139         struct bnxt_rx_queue *rxq;
3140         struct rx_pkt_cmpl *rxcmp;
3141         int rc;
3142
3143         rxq = rx_queue;
3144         bp = rxq->bp;
3145
3146         rc = is_bnxt_in_error(bp);
3147         if (rc)
3148                 return rc;
3149
3150         cpr = rxq->cp_ring;
3151         raw_cons = cpr->cp_raw_cons;
3152         cp_ring_size = cpr->cp_ring_struct->ring_size;
3153
3154         while (1) {
3155                 uint32_t agg_cnt, cons, cmpl_type;
3156
3157                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3158                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3159
3160                 if (!bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size))
3161                         break;
3162
3163                 cmpl_type = CMP_TYPE(rxcmp);
3164
3165                 switch (cmpl_type) {
3166                 case CMPL_BASE_TYPE_RX_L2:
3167                 case CMPL_BASE_TYPE_RX_L2_V2:
3168                         agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3169                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3170                         desc++;
3171                         break;
3172
3173                 case CMPL_BASE_TYPE_RX_TPA_END:
3174                         if (BNXT_CHIP_P5(rxq->bp)) {
3175                                 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3176
3177                                 p5_tpa_end = (void *)rxcmp;
3178                                 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3179                         } else {
3180                                 struct rx_tpa_end_cmpl *tpa_end;
3181
3182                                 tpa_end = (void *)rxcmp;
3183                                 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3184                         }
3185
3186                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3187                         desc++;
3188                         break;
3189
3190                 default:
3191                         raw_cons += CMP_LEN(cmpl_type);
3192                 }
3193         }
3194
3195         return desc;
3196 }
3197
3198 static int
3199 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
3200 {
3201         struct bnxt_rx_queue *rxq = rx_queue;
3202         struct bnxt_cp_ring_info *cpr;
3203         struct bnxt_rx_ring_info *rxr;
3204         uint32_t desc, raw_cons, cp_ring_size;
3205         struct bnxt *bp = rxq->bp;
3206         struct rx_pkt_cmpl *rxcmp;
3207         int rc;
3208
3209         rc = is_bnxt_in_error(bp);
3210         if (rc)
3211                 return rc;
3212
3213         if (offset >= rxq->nb_rx_desc)
3214                 return -EINVAL;
3215
3216         rxr = rxq->rx_ring;
3217         cpr = rxq->cp_ring;
3218         cp_ring_size = cpr->cp_ring_struct->ring_size;
3219
3220         /*
3221          * For the vector receive case, the completion at the requested
3222          * offset can be indexed directly.
3223          */
3224 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
3225         if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) {
3226                 struct rx_pkt_cmpl *rxcmp;
3227                 uint32_t cons;
3228
3229                 /* Check status of completion descriptor. */
3230                 raw_cons = cpr->cp_raw_cons +
3231                            offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2);
3232                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3233                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3234
3235                 if (bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size))
3236                         return RTE_ETH_RX_DESC_DONE;
3237
3238                 /* Check whether rx desc has an mbuf attached. */
3239                 cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2);
3240                 if (cons >= rxq->rxrearm_start &&
3241                     cons < rxq->rxrearm_start + rxq->rxrearm_nb) {
3242                         return RTE_ETH_RX_DESC_UNAVAIL;
3243                 }
3244
3245                 return RTE_ETH_RX_DESC_AVAIL;
3246         }
3247 #endif
3248
3249         /*
3250          * For the non-vector receive case, scan the completion ring to
3251          * locate the completion descriptor for the requested offset.
3252          */
3253         raw_cons = cpr->cp_raw_cons;
3254         desc = 0;
3255         while (1) {
3256                 uint32_t agg_cnt, cons, cmpl_type;
3257
3258                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3259                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3260
3261                 if (!bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size))
3262                         break;
3263
3264                 cmpl_type = CMP_TYPE(rxcmp);
3265
3266                 switch (cmpl_type) {
3267                 case CMPL_BASE_TYPE_RX_L2:
3268                 case CMPL_BASE_TYPE_RX_L2_V2:
3269                         if (desc == offset) {
3270                                 cons = rxcmp->opaque;
3271                                 if (rxr->rx_buf_ring[cons])
3272                                         return RTE_ETH_RX_DESC_DONE;
3273                                 else
3274                                         return RTE_ETH_RX_DESC_UNAVAIL;
3275                         }
3276                         agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3277                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3278                         desc++;
3279                         break;
3280
3281                 case CMPL_BASE_TYPE_RX_TPA_END:
3282                         if (desc == offset)
3283                                 return RTE_ETH_RX_DESC_DONE;
3284
3285                         if (BNXT_CHIP_P5(rxq->bp)) {
3286                                 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3287
3288                                 p5_tpa_end = (void *)rxcmp;
3289                                 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3290                         } else {
3291                                 struct rx_tpa_end_cmpl *tpa_end;
3292
3293                                 tpa_end = (void *)rxcmp;
3294                                 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3295                         }
3296
3297                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3298                         desc++;
3299                         break;
3300
3301                 default:
3302                         raw_cons += CMP_LEN(cmpl_type);
3303                 }
3304         }
3305
3306         return RTE_ETH_RX_DESC_AVAIL;
3307 }
3308
3309 static int
3310 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
3311 {
3312         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
3313         struct bnxt_cp_ring_info *cpr = txq->cp_ring;
3314         uint32_t ring_mask, raw_cons, nb_tx_pkts = 0;
3315         struct cmpl_base *cp_desc_ring;
3316         int rc;
3317
3318         rc = is_bnxt_in_error(txq->bp);
3319         if (rc)
3320                 return rc;
3321
3322         if (offset >= txq->nb_tx_desc)
3323                 return -EINVAL;
3324
3325         /* Return "desc done" if descriptor is available for use. */
3326         if (bnxt_tx_bds_in_hw(txq) <= offset)
3327                 return RTE_ETH_TX_DESC_DONE;
3328
3329         raw_cons = cpr->cp_raw_cons;
3330         cp_desc_ring = cpr->cp_desc_ring;
3331         ring_mask = cpr->cp_ring_struct->ring_mask;
3332
3333         /* Check to see if hw has posted a completion for the descriptor. */
3334         while (1) {
3335                 struct tx_cmpl *txcmp;
3336                 uint32_t cons;
3337
3338                 cons = RING_CMPL(ring_mask, raw_cons);
3339                 txcmp = (struct tx_cmpl *)&cp_desc_ring[cons];
3340
3341                 if (!bnxt_cpr_cmp_valid(txcmp, raw_cons, ring_mask + 1))
3342                         break;
3343
3344                 if (CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2)
3345                         nb_tx_pkts += rte_le_to_cpu_32(txcmp->opaque);
3346
3347                 if (nb_tx_pkts > offset)
3348                         return RTE_ETH_TX_DESC_DONE;
3349
3350                 raw_cons = NEXT_RAW_CMP(raw_cons);
3351         }
3352
3353         /* Descriptor is pending transmit, not yet completed by hardware. */
3354         return RTE_ETH_TX_DESC_FULL;
3355 }
3356
3357 int
3358 bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
3359                      const struct rte_flow_ops **ops)
3360 {
3361         struct bnxt *bp = dev->data->dev_private;
3362         int ret = 0;
3363
3364         if (!bp)
3365                 return -EIO;
3366
3367         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3368                 struct bnxt_representor *vfr = dev->data->dev_private;
3369                 bp = vfr->parent_dev->data->dev_private;
3370                 /* parent is deleted while children are still valid */
3371                 if (!bp) {
3372                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error\n",
3373                                     dev->data->port_id);
3374                         return -EIO;
3375                 }
3376         }
3377
3378         ret = is_bnxt_in_error(bp);
3379         if (ret)
3380                 return ret;
3381
3382         /* PMD supports thread-safe flow operations.  rte_flow API
3383          * functions can avoid mutex for multi-thread safety.
3384          */
3385         dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3386
3387         if (BNXT_TRUFLOW_EN(bp))
3388                 *ops = &bnxt_ulp_rte_flow_ops;
3389         else
3390                 *ops = &bnxt_flow_ops;
3391
3392         return ret;
3393 }
3394
3395 static const uint32_t *
3396 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3397 {
3398         static const uint32_t ptypes[] = {
3399                 RTE_PTYPE_L2_ETHER_VLAN,
3400                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3401                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3402                 RTE_PTYPE_L4_ICMP,
3403                 RTE_PTYPE_L4_TCP,
3404                 RTE_PTYPE_L4_UDP,
3405                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3406                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3407                 RTE_PTYPE_INNER_L4_ICMP,
3408                 RTE_PTYPE_INNER_L4_TCP,
3409                 RTE_PTYPE_INNER_L4_UDP,
3410                 RTE_PTYPE_UNKNOWN
3411         };
3412
3413         if (!dev->rx_pkt_burst)
3414                 return NULL;
3415
3416         return ptypes;
3417 }
3418
3419 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3420                          int reg_win)
3421 {
3422         uint32_t reg_base = *reg_arr & 0xfffff000;
3423         uint32_t win_off;
3424         int i;
3425
3426         for (i = 0; i < count; i++) {
3427                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3428                         return -ERANGE;
3429         }
3430         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3431         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3432         return 0;
3433 }
3434
3435 static int bnxt_map_ptp_regs(struct bnxt *bp)
3436 {
3437         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3438         uint32_t *reg_arr;
3439         int rc, i;
3440
3441         reg_arr = ptp->rx_regs;
3442         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3443         if (rc)
3444                 return rc;
3445
3446         reg_arr = ptp->tx_regs;
3447         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3448         if (rc)
3449                 return rc;
3450
3451         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3452                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3453
3454         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3455                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3456
3457         return 0;
3458 }
3459
3460 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3461 {
3462         rte_write32(0, (uint8_t *)bp->bar0 +
3463                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3464         rte_write32(0, (uint8_t *)bp->bar0 +
3465                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3466 }
3467
3468 static uint64_t bnxt_cc_read(struct bnxt *bp)
3469 {
3470         uint64_t ns;
3471
3472         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3473                               BNXT_GRCPF_REG_SYNC_TIME));
3474         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3475                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3476         return ns;
3477 }
3478
3479 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3480 {
3481         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3482         uint32_t fifo;
3483
3484         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3485                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3486         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3487                 return -EAGAIN;
3488
3489         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3490                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3491         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3492                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3493         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3494                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3495         rte_read32((uint8_t *)bp->bar0 + ptp->tx_mapped_regs[BNXT_PTP_TX_SEQ]);
3496
3497         return 0;
3498 }
3499
3500 static int bnxt_clr_rx_ts(struct bnxt *bp, uint64_t *last_ts)
3501 {
3502         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3503         struct bnxt_pf_info *pf = bp->pf;
3504         uint16_t port_id;
3505         int i = 0;
3506         uint32_t fifo;
3507
3508         if (!ptp || (bp->flags & BNXT_FLAG_CHIP_P5))
3509                 return -EINVAL;
3510
3511         port_id = pf->port_id;
3512         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3513                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3514         while ((fifo & BNXT_PTP_RX_FIFO_PENDING) && (i < BNXT_PTP_RX_PND_CNT)) {
3515                 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3516                             ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3517                 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3518                                         ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3519                 *last_ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3520                                         ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3521                 *last_ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3522                                         ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3523                 i++;
3524         }
3525
3526         if (i >= BNXT_PTP_RX_PND_CNT)
3527                 return -EBUSY;
3528
3529         return 0;
3530 }
3531
3532 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3533 {
3534         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3535         struct bnxt_pf_info *pf = bp->pf;
3536         uint16_t port_id;
3537         uint32_t fifo;
3538
3539         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3540                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3541         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3542                 return -EAGAIN;
3543
3544         port_id = pf->port_id;
3545         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3546                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3547
3548         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3549                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3550         if (fifo & BNXT_PTP_RX_FIFO_PENDING)
3551                 return bnxt_clr_rx_ts(bp, ts);
3552
3553         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3554                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3555         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3556                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3557
3558         return 0;
3559 }
3560
3561 static int
3562 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3563 {
3564         uint64_t ns;
3565         struct bnxt *bp = dev->data->dev_private;
3566         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3567
3568         if (!ptp)
3569                 return -ENOTSUP;
3570
3571         ns = rte_timespec_to_ns(ts);
3572         /* Set the timecounters to a new value. */
3573         ptp->tc.nsec = ns;
3574         ptp->tx_tstamp_tc.nsec = ns;
3575         ptp->rx_tstamp_tc.nsec = ns;
3576
3577         return 0;
3578 }
3579
3580 static int
3581 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3582 {
3583         struct bnxt *bp = dev->data->dev_private;
3584         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3585         uint64_t ns, systime_cycles = 0;
3586         int rc = 0;
3587
3588         if (!ptp)
3589                 return -ENOTSUP;
3590
3591         if (BNXT_CHIP_P5(bp))
3592                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3593                                              &systime_cycles);
3594         else
3595                 systime_cycles = bnxt_cc_read(bp);
3596
3597         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3598         *ts = rte_ns_to_timespec(ns);
3599
3600         return rc;
3601 }
3602 static int
3603 bnxt_timesync_enable(struct rte_eth_dev *dev)
3604 {
3605         struct bnxt *bp = dev->data->dev_private;
3606         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3607         uint32_t shift = 0;
3608         int rc;
3609
3610         if (!ptp)
3611                 return -ENOTSUP;
3612
3613         ptp->rx_filter = 1;
3614         ptp->tx_tstamp_en = 1;
3615         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3616
3617         rc = bnxt_hwrm_ptp_cfg(bp);
3618         if (rc)
3619                 return rc;
3620
3621         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3622         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3623         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3624
3625         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3626         ptp->tc.cc_shift = shift;
3627         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3628
3629         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3630         ptp->rx_tstamp_tc.cc_shift = shift;
3631         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3632
3633         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3634         ptp->tx_tstamp_tc.cc_shift = shift;
3635         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3636
3637         if (!BNXT_CHIP_P5(bp))
3638                 bnxt_map_ptp_regs(bp);
3639         else
3640                 rc = bnxt_ptp_start(bp);
3641
3642         return rc;
3643 }
3644
3645 static int
3646 bnxt_timesync_disable(struct rte_eth_dev *dev)
3647 {
3648         struct bnxt *bp = dev->data->dev_private;
3649         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3650
3651         if (!ptp)
3652                 return -ENOTSUP;
3653
3654         ptp->rx_filter = 0;
3655         ptp->tx_tstamp_en = 0;
3656         ptp->rxctl = 0;
3657
3658         bnxt_hwrm_ptp_cfg(bp);
3659
3660         if (!BNXT_CHIP_P5(bp))
3661                 bnxt_unmap_ptp_regs(bp);
3662         else
3663                 bnxt_ptp_stop(bp);
3664
3665         return 0;
3666 }
3667
3668 static int
3669 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3670                                  struct timespec *timestamp,
3671                                  uint32_t flags __rte_unused)
3672 {
3673         struct bnxt *bp = dev->data->dev_private;
3674         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3675         uint64_t rx_tstamp_cycles = 0;
3676         uint64_t ns;
3677
3678         if (!ptp)
3679                 return -ENOTSUP;
3680
3681         if (BNXT_CHIP_P5(bp))
3682                 rx_tstamp_cycles = ptp->rx_timestamp;
3683         else
3684                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3685
3686         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3687         *timestamp = rte_ns_to_timespec(ns);
3688         return  0;
3689 }
3690
3691 static int
3692 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3693                                  struct timespec *timestamp)
3694 {
3695         struct bnxt *bp = dev->data->dev_private;
3696         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3697         uint64_t tx_tstamp_cycles = 0;
3698         uint64_t ns;
3699         int rc = 0;
3700
3701         if (!ptp)
3702                 return -ENOTSUP;
3703
3704         if (BNXT_CHIP_P5(bp))
3705                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3706                                              &tx_tstamp_cycles);
3707         else
3708                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3709
3710         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3711         *timestamp = rte_ns_to_timespec(ns);
3712
3713         return rc;
3714 }
3715
3716 static int
3717 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3718 {
3719         struct bnxt *bp = dev->data->dev_private;
3720         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3721
3722         if (!ptp)
3723                 return -ENOTSUP;
3724
3725         ptp->tc.nsec += delta;
3726         ptp->tx_tstamp_tc.nsec += delta;
3727         ptp->rx_tstamp_tc.nsec += delta;
3728
3729         return 0;
3730 }
3731
3732 static int
3733 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3734 {
3735         struct bnxt *bp = dev->data->dev_private;
3736         int rc;
3737         uint32_t dir_entries;
3738         uint32_t entry_length;
3739
3740         rc = is_bnxt_in_error(bp);
3741         if (rc)
3742                 return rc;
3743
3744         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3745                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3746                     bp->pdev->addr.devid, bp->pdev->addr.function);
3747
3748         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3749         if (rc != 0)
3750                 return rc;
3751
3752         return dir_entries * entry_length;
3753 }
3754
3755 static int
3756 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3757                 struct rte_dev_eeprom_info *in_eeprom)
3758 {
3759         struct bnxt *bp = dev->data->dev_private;
3760         uint32_t index;
3761         uint32_t offset;
3762         int rc;
3763
3764         rc = is_bnxt_in_error(bp);
3765         if (rc)
3766                 return rc;
3767
3768         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3769                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3770                     bp->pdev->addr.devid, bp->pdev->addr.function,
3771                     in_eeprom->offset, in_eeprom->length);
3772
3773         if (in_eeprom->offset == 0) /* special offset value to get directory */
3774                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3775                                                 in_eeprom->data);
3776
3777         index = in_eeprom->offset >> 24;
3778         offset = in_eeprom->offset & 0xffffff;
3779
3780         if (index != 0)
3781                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3782                                            in_eeprom->length, in_eeprom->data);
3783
3784         return 0;
3785 }
3786
3787 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3788 {
3789         switch (dir_type) {
3790         case BNX_DIR_TYPE_CHIMP_PATCH:
3791         case BNX_DIR_TYPE_BOOTCODE:
3792         case BNX_DIR_TYPE_BOOTCODE_2:
3793         case BNX_DIR_TYPE_APE_FW:
3794         case BNX_DIR_TYPE_APE_PATCH:
3795         case BNX_DIR_TYPE_KONG_FW:
3796         case BNX_DIR_TYPE_KONG_PATCH:
3797         case BNX_DIR_TYPE_BONO_FW:
3798         case BNX_DIR_TYPE_BONO_PATCH:
3799                 /* FALLTHROUGH */
3800                 return true;
3801         }
3802
3803         return false;
3804 }
3805
3806 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3807 {
3808         switch (dir_type) {
3809         case BNX_DIR_TYPE_AVS:
3810         case BNX_DIR_TYPE_EXP_ROM_MBA:
3811         case BNX_DIR_TYPE_PCIE:
3812         case BNX_DIR_TYPE_TSCF_UCODE:
3813         case BNX_DIR_TYPE_EXT_PHY:
3814         case BNX_DIR_TYPE_CCM:
3815         case BNX_DIR_TYPE_ISCSI_BOOT:
3816         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3817         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3818                 /* FALLTHROUGH */
3819                 return true;
3820         }
3821
3822         return false;
3823 }
3824
3825 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3826 {
3827         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3828                 bnxt_dir_type_is_other_exec_format(dir_type);
3829 }
3830
3831 static int
3832 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3833                 struct rte_dev_eeprom_info *in_eeprom)
3834 {
3835         struct bnxt *bp = dev->data->dev_private;
3836         uint8_t index, dir_op;
3837         uint16_t type, ext, ordinal, attr;
3838         int rc;
3839
3840         rc = is_bnxt_in_error(bp);
3841         if (rc)
3842                 return rc;
3843
3844         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3845                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3846                     bp->pdev->addr.devid, bp->pdev->addr.function,
3847                     in_eeprom->offset, in_eeprom->length);
3848
3849         if (!BNXT_PF(bp)) {
3850                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3851                 return -EINVAL;
3852         }
3853
3854         type = in_eeprom->magic >> 16;
3855
3856         if (type == 0xffff) { /* special value for directory operations */
3857                 index = in_eeprom->magic & 0xff;
3858                 dir_op = in_eeprom->magic >> 8;
3859                 if (index == 0)
3860                         return -EINVAL;
3861                 switch (dir_op) {
3862                 case 0x0e: /* erase */
3863                         if (in_eeprom->offset != ~in_eeprom->magic)
3864                                 return -EINVAL;
3865                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3866                 default:
3867                         return -EINVAL;
3868                 }
3869         }
3870
3871         /* Create or re-write an NVM item: */
3872         if (bnxt_dir_type_is_executable(type) == true)
3873                 return -EOPNOTSUPP;
3874         ext = in_eeprom->magic & 0xffff;
3875         ordinal = in_eeprom->offset >> 16;
3876         attr = in_eeprom->offset & 0xffff;
3877
3878         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3879                                      in_eeprom->data, in_eeprom->length);
3880 }
3881
3882 static int bnxt_get_module_info(struct rte_eth_dev *dev,
3883                                 struct rte_eth_dev_module_info *modinfo)
3884 {
3885         uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1];
3886         struct bnxt *bp = dev->data->dev_private;
3887         int rc;
3888
3889         /* No point in going further if phy status indicates
3890          * module is not inserted or if it is powered down or
3891          * if it is of type 10GBase-T
3892          */
3893         if (bp->link_info->module_status >
3894             HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG) {
3895                 PMD_DRV_LOG(NOTICE, "Port %u : Module is not inserted or is powered down\n",
3896                             dev->data->port_id);
3897                 return -ENOTSUP;
3898         }
3899
3900         /* This feature is not supported in older firmware versions */
3901         if (bp->hwrm_spec_code < 0x10202) {
3902                 PMD_DRV_LOG(NOTICE, "Port %u : Feature is not supported in older firmware\n",
3903                             dev->data->port_id);
3904                 return -ENOTSUP;
3905         }
3906
3907         rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
3908                                                    SFF_DIAG_SUPPORT_OFFSET + 1,
3909                                                    module_info);
3910
3911         if (rc)
3912                 return rc;
3913
3914         switch (module_info[0]) {
3915         case SFF_MODULE_ID_SFP:
3916                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
3917                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
3918                 if (module_info[SFF_DIAG_SUPPORT_OFFSET] == 0)
3919                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN;
3920                 break;
3921         case SFF_MODULE_ID_QSFP:
3922         case SFF_MODULE_ID_QSFP_PLUS:
3923                 modinfo->type = RTE_ETH_MODULE_SFF_8436;
3924                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN;
3925                 break;
3926         case SFF_MODULE_ID_QSFP28:
3927                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
3928                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
3929                 if (module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK)
3930                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_LEN;
3931                 break;
3932         default:
3933                 PMD_DRV_LOG(NOTICE, "Port %u : Unsupported module\n", dev->data->port_id);
3934                 return -ENOTSUP;
3935         }
3936
3937         PMD_DRV_LOG(INFO, "Port %u : modinfo->type = %d modinfo->eeprom_len = %d\n",
3938                     dev->data->port_id, modinfo->type, modinfo->eeprom_len);
3939
3940         return 0;
3941 }
3942
3943 static int bnxt_get_module_eeprom(struct rte_eth_dev *dev,
3944                                   struct rte_dev_eeprom_info *info)
3945 {
3946         uint8_t pg_addr[5] = { I2C_DEV_ADDR_A0, I2C_DEV_ADDR_A0 };
3947         uint32_t offset = info->offset, length = info->length;
3948         uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1];
3949         struct bnxt *bp = dev->data->dev_private;
3950         uint8_t *data = info->data;
3951         uint8_t page = offset >> 7;
3952         uint8_t max_pages = 2;
3953         uint8_t opt_pages;
3954         int rc;
3955
3956         rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
3957                                                    SFF_DIAG_SUPPORT_OFFSET + 1,
3958                                                    module_info);
3959         if (rc)
3960                 return rc;
3961
3962         switch (module_info[0]) {
3963         case SFF_MODULE_ID_SFP:
3964                 module_info[SFF_DIAG_SUPPORT_OFFSET] = 0;
3965                 if (module_info[SFF_DIAG_SUPPORT_OFFSET]) {
3966                         pg_addr[2] = I2C_DEV_ADDR_A2;
3967                         pg_addr[3] = I2C_DEV_ADDR_A2;
3968                         max_pages = 4;
3969                 }
3970                 break;
3971         case SFF_MODULE_ID_QSFP28:
3972                 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0,
3973                                                            SFF8636_OPT_PAGES_OFFSET,
3974                                                            1, &opt_pages);
3975                 if (rc)
3976                         return rc;
3977
3978                 if (opt_pages & SFF8636_PAGE1_MASK) {
3979                         pg_addr[2] = I2C_DEV_ADDR_A0;
3980                         max_pages = 3;
3981                 }
3982                 if (opt_pages & SFF8636_PAGE2_MASK) {
3983                         pg_addr[3] = I2C_DEV_ADDR_A0;
3984                         max_pages = 4;
3985                 }
3986                 if (~module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK) {
3987                         pg_addr[4] = I2C_DEV_ADDR_A0;
3988                         max_pages = 5;
3989                 }
3990                 break;
3991         default:
3992                 break;
3993         }
3994
3995         memset(data, 0, length);
3996
3997         offset &= 0xff;
3998         while (length && page < max_pages) {
3999                 uint8_t raw_page = page ? page - 1 : 0;
4000                 uint16_t chunk;
4001
4002                 if (pg_addr[page] == I2C_DEV_ADDR_A2)
4003                         raw_page = 0;
4004                 else if (page)
4005                         offset |= 0x80;
4006                 chunk = RTE_MIN(length, 256 - offset);
4007
4008                 if (pg_addr[page]) {
4009                         rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, pg_addr[page],
4010                                                                    raw_page, offset,
4011                                                                    chunk, data);
4012                         if (rc)
4013                                 return rc;
4014                 }
4015
4016                 data += chunk;
4017                 length -= chunk;
4018                 offset = 0;
4019                 page += 1 + (chunk > 128);
4020         }
4021
4022         return length ? -EINVAL : 0;
4023 }
4024
4025 /*
4026  * Initialization
4027  */
4028
4029 static const struct eth_dev_ops bnxt_dev_ops = {
4030         .dev_infos_get = bnxt_dev_info_get_op,
4031         .dev_close = bnxt_dev_close_op,
4032         .dev_configure = bnxt_dev_configure_op,
4033         .dev_start = bnxt_dev_start_op,
4034         .dev_stop = bnxt_dev_stop_op,
4035         .dev_set_link_up = bnxt_dev_set_link_up_op,
4036         .dev_set_link_down = bnxt_dev_set_link_down_op,
4037         .stats_get = bnxt_stats_get_op,
4038         .stats_reset = bnxt_stats_reset_op,
4039         .rx_queue_setup = bnxt_rx_queue_setup_op,
4040         .rx_queue_release = bnxt_rx_queue_release_op,
4041         .tx_queue_setup = bnxt_tx_queue_setup_op,
4042         .tx_queue_release = bnxt_tx_queue_release_op,
4043         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4044         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4045         .reta_update = bnxt_reta_update_op,
4046         .reta_query = bnxt_reta_query_op,
4047         .rss_hash_update = bnxt_rss_hash_update_op,
4048         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4049         .link_update = bnxt_link_update_op,
4050         .promiscuous_enable = bnxt_promiscuous_enable_op,
4051         .promiscuous_disable = bnxt_promiscuous_disable_op,
4052         .allmulticast_enable = bnxt_allmulticast_enable_op,
4053         .allmulticast_disable = bnxt_allmulticast_disable_op,
4054         .mac_addr_add = bnxt_mac_addr_add_op,
4055         .mac_addr_remove = bnxt_mac_addr_remove_op,
4056         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4057         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4058         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4059         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4060         .vlan_filter_set = bnxt_vlan_filter_set_op,
4061         .vlan_offload_set = bnxt_vlan_offload_set_op,
4062         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4063         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4064         .mtu_set = bnxt_mtu_set_op,
4065         .mac_addr_set = bnxt_set_default_mac_addr_op,
4066         .xstats_get = bnxt_dev_xstats_get_op,
4067         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4068         .xstats_reset = bnxt_dev_xstats_reset_op,
4069         .fw_version_get = bnxt_fw_version_get,
4070         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4071         .rxq_info_get = bnxt_rxq_info_get_op,
4072         .txq_info_get = bnxt_txq_info_get_op,
4073         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4074         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4075         .dev_led_on = bnxt_dev_led_on_op,
4076         .dev_led_off = bnxt_dev_led_off_op,
4077         .rx_queue_start = bnxt_rx_queue_start,
4078         .rx_queue_stop = bnxt_rx_queue_stop,
4079         .tx_queue_start = bnxt_tx_queue_start,
4080         .tx_queue_stop = bnxt_tx_queue_stop,
4081         .flow_ops_get = bnxt_flow_ops_get_op,
4082         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4083         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4084         .get_eeprom           = bnxt_get_eeprom_op,
4085         .set_eeprom           = bnxt_set_eeprom_op,
4086         .get_module_info = bnxt_get_module_info,
4087         .get_module_eeprom = bnxt_get_module_eeprom,
4088         .timesync_enable      = bnxt_timesync_enable,
4089         .timesync_disable     = bnxt_timesync_disable,
4090         .timesync_read_time   = bnxt_timesync_read_time,
4091         .timesync_write_time   = bnxt_timesync_write_time,
4092         .timesync_adjust_time = bnxt_timesync_adjust_time,
4093         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4094         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4095 };
4096
4097 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4098 {
4099         uint32_t offset;
4100
4101         /* Only pre-map the reset GRC registers using window 3 */
4102         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4103                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4104
4105         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4106
4107         return offset;
4108 }
4109
4110 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4111 {
4112         struct bnxt_error_recovery_info *info = bp->recovery_info;
4113         uint32_t reg_base = 0xffffffff;
4114         int i;
4115
4116         /* Only pre-map the monitoring GRC registers using window 2 */
4117         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4118                 uint32_t reg = info->status_regs[i];
4119
4120                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4121                         continue;
4122
4123                 if (reg_base == 0xffffffff)
4124                         reg_base = reg & 0xfffff000;
4125                 if ((reg & 0xfffff000) != reg_base)
4126                         return -ERANGE;
4127
4128                 /* Use mask 0xffc as the Lower 2 bits indicates
4129                  * address space location
4130                  */
4131                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4132                                                 (reg & 0xffc);
4133         }
4134
4135         if (reg_base == 0xffffffff)
4136                 return 0;
4137
4138         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4139                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4140
4141         return 0;
4142 }
4143
4144 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4145 {
4146         struct bnxt_error_recovery_info *info = bp->recovery_info;
4147         uint32_t delay = info->delay_after_reset[index];
4148         uint32_t val = info->reset_reg_val[index];
4149         uint32_t reg = info->reset_reg[index];
4150         uint32_t type, offset;
4151         int ret;
4152
4153         type = BNXT_FW_STATUS_REG_TYPE(reg);
4154         offset = BNXT_FW_STATUS_REG_OFF(reg);
4155
4156         switch (type) {
4157         case BNXT_FW_STATUS_REG_TYPE_CFG:
4158                 ret = rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4159                 if (ret < 0) {
4160                         PMD_DRV_LOG(ERR, "Failed to write %#x at PCI offset %#x",
4161                                     val, offset);
4162                         return;
4163                 }
4164                 break;
4165         case BNXT_FW_STATUS_REG_TYPE_GRC:
4166                 offset = bnxt_map_reset_regs(bp, offset);
4167                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4168                 break;
4169         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4170                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4171                 break;
4172         }
4173         /* wait on a specific interval of time until core reset is complete */
4174         if (delay)
4175                 rte_delay_ms(delay);
4176 }
4177
4178 static void bnxt_dev_cleanup(struct bnxt *bp)
4179 {
4180         bp->eth_dev->data->dev_link.link_status = 0;
4181         bp->link_info->link_up = 0;
4182         if (bp->eth_dev->data->dev_started)
4183                 bnxt_dev_stop(bp->eth_dev);
4184
4185         bnxt_uninit_resources(bp, true);
4186 }
4187
4188 static int
4189 bnxt_check_fw_reset_done(struct bnxt *bp)
4190 {
4191         int timeout = bp->fw_reset_max_msecs;
4192         uint16_t val = 0;
4193         int rc;
4194
4195         do {
4196                 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4197                 if (rc < 0) {
4198                         PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4199                         return rc;
4200                 }
4201                 if (val != 0xffff)
4202                         break;
4203                 rte_delay_ms(1);
4204         } while (timeout--);
4205
4206         if (val == 0xffff) {
4207                 PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n");
4208                 return -1;
4209         }
4210
4211         return 0;
4212 }
4213
4214 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4215 {
4216         struct rte_eth_dev *dev = bp->eth_dev;
4217         struct rte_vlan_filter_conf *vfc;
4218         int vidx, vbit, rc;
4219         uint16_t vlan_id;
4220
4221         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4222                 vfc = &dev->data->vlan_filter_conf;
4223                 vidx = vlan_id / 64;
4224                 vbit = vlan_id % 64;
4225
4226                 /* Each bit corresponds to a VLAN id */
4227                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4228                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4229                         if (rc)
4230                                 return rc;
4231                 }
4232         }
4233
4234         return 0;
4235 }
4236
4237 static int bnxt_restore_mac_filters(struct bnxt *bp)
4238 {
4239         struct rte_eth_dev *dev = bp->eth_dev;
4240         struct rte_eth_dev_info dev_info;
4241         struct rte_ether_addr *addr;
4242         uint64_t pool_mask;
4243         uint32_t pool = 0;
4244         uint32_t i;
4245         int rc;
4246
4247         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4248                 return 0;
4249
4250         rc = bnxt_dev_info_get_op(dev, &dev_info);
4251         if (rc)
4252                 return rc;
4253
4254         /* replay MAC address configuration */
4255         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4256                 addr = &dev->data->mac_addrs[i];
4257
4258                 /* skip zero address */
4259                 if (rte_is_zero_ether_addr(addr))
4260                         continue;
4261
4262                 pool = 0;
4263                 pool_mask = dev->data->mac_pool_sel[i];
4264
4265                 do {
4266                         if (pool_mask & 1ULL) {
4267                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4268                                 if (rc)
4269                                         return rc;
4270                         }
4271                         pool_mask >>= 1;
4272                         pool++;
4273                 } while (pool_mask);
4274         }
4275
4276         return 0;
4277 }
4278
4279 static int bnxt_restore_mcast_mac_filters(struct bnxt *bp)
4280 {
4281         int ret = 0;
4282
4283         ret = bnxt_dev_set_mc_addr_list_op(bp->eth_dev, bp->mcast_addr_list,
4284                                            bp->nb_mc_addr);
4285         if (ret)
4286                 PMD_DRV_LOG(ERR, "Failed to restore multicast MAC addreeses\n");
4287
4288         return ret;
4289 }
4290
4291 static int bnxt_restore_filters(struct bnxt *bp)
4292 {
4293         struct rte_eth_dev *dev = bp->eth_dev;
4294         int ret = 0;
4295
4296         if (dev->data->all_multicast) {
4297                 ret = bnxt_allmulticast_enable_op(dev);
4298                 if (ret)
4299                         return ret;
4300         }
4301         if (dev->data->promiscuous) {
4302                 ret = bnxt_promiscuous_enable_op(dev);
4303                 if (ret)
4304                         return ret;
4305         }
4306
4307         ret = bnxt_restore_mac_filters(bp);
4308         if (ret)
4309                 return ret;
4310
4311         /* if vlans are already programmed, this can fail with -EEXIST */
4312         ret = bnxt_restore_vlan_filters(bp);
4313         if (ret && ret != -EEXIST)
4314                 return ret;
4315
4316         ret = bnxt_restore_mcast_mac_filters(bp);
4317         if (ret)
4318                 return ret;
4319
4320         return ret;
4321 }
4322
4323 static int bnxt_check_fw_ready(struct bnxt *bp)
4324 {
4325         int timeout = bp->fw_reset_max_msecs;
4326         int rc = 0;
4327
4328         do {
4329                 rc = bnxt_hwrm_poll_ver_get(bp);
4330                 if (rc == 0)
4331                         break;
4332                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4333                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4334         } while (rc && timeout > 0);
4335
4336         if (rc)
4337                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4338
4339         return rc;
4340 }
4341
4342 static void bnxt_dev_recover(void *arg)
4343 {
4344         struct bnxt *bp = arg;
4345         int rc = 0;
4346
4347         pthread_mutex_lock(&bp->err_recovery_lock);
4348
4349         if (!bp->fw_reset_min_msecs) {
4350                 rc = bnxt_check_fw_reset_done(bp);
4351                 if (rc)
4352                         goto err;
4353         }
4354
4355         /* Clear Error flag so that device re-init should happen */
4356         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4357         PMD_DRV_LOG(INFO, "Port: %u Starting recovery...\n",
4358                     bp->eth_dev->data->port_id);
4359
4360         rc = bnxt_check_fw_ready(bp);
4361         if (rc)
4362                 goto err;
4363
4364         rc = bnxt_init_resources(bp, true);
4365         if (rc) {
4366                 PMD_DRV_LOG(ERR,
4367                             "Failed to initialize resources after reset\n");
4368                 goto err;
4369         }
4370         /* clear reset flag as the device is initialized now */
4371         bp->flags &= ~BNXT_FLAG_FW_RESET;
4372
4373         rc = bnxt_dev_start_op(bp->eth_dev);
4374         if (rc) {
4375                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4376                 goto err_start;
4377         }
4378
4379         rte_eth_fp_ops[bp->eth_dev->data->port_id].rx_pkt_burst =
4380                 bp->eth_dev->rx_pkt_burst;
4381         rte_eth_fp_ops[bp->eth_dev->data->port_id].tx_pkt_burst =
4382                 bp->eth_dev->tx_pkt_burst;
4383         rte_mb();
4384
4385         rc = bnxt_restore_filters(bp);
4386         if (rc)
4387                 goto err_start;
4388
4389         PMD_DRV_LOG(INFO, "Port: %u Recovered from FW reset\n",
4390                     bp->eth_dev->data->port_id);
4391         pthread_mutex_unlock(&bp->err_recovery_lock);
4392
4393         return;
4394 err_start:
4395         bnxt_dev_stop(bp->eth_dev);
4396 err:
4397         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4398         bnxt_uninit_resources(bp, false);
4399         if (bp->eth_dev->data->dev_conf.intr_conf.rmv)
4400                 rte_eth_dev_callback_process(bp->eth_dev,
4401                                              RTE_ETH_EVENT_INTR_RMV,
4402                                              NULL);
4403         pthread_mutex_unlock(&bp->err_recovery_lock);
4404         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4405 }
4406
4407 void bnxt_dev_reset_and_resume(void *arg)
4408 {
4409         struct bnxt *bp = arg;
4410         uint32_t us = US_PER_MS * bp->fw_reset_min_msecs;
4411         uint16_t val = 0;
4412         int rc;
4413
4414         bnxt_dev_cleanup(bp);
4415         PMD_DRV_LOG(INFO, "Port: %u Finished bnxt_dev_cleanup\n",
4416                     bp->eth_dev->data->port_id);
4417
4418         bnxt_wait_for_device_shutdown(bp);
4419
4420         /* During some fatal firmware error conditions, the PCI config space
4421          * register 0x2e which normally contains the subsystem ID will become
4422          * 0xffff. This register will revert back to the normal value after
4423          * the chip has completed core reset. If we detect this condition,
4424          * we can poll this config register immediately for the value to revert.
4425          */
4426         if (bp->flags & BNXT_FLAG_FATAL_ERROR) {
4427                 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4428                 if (rc < 0) {
4429                         PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4430                         return;
4431                 }
4432                 if (val == 0xffff) {
4433                         bp->fw_reset_min_msecs = 0;
4434                         us = 1;
4435                 }
4436         }
4437
4438         rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp);
4439         if (rc)
4440                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4441 }
4442
4443 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4444 {
4445         struct bnxt_error_recovery_info *info = bp->recovery_info;
4446         uint32_t reg = info->status_regs[index];
4447         uint32_t type, offset, val = 0;
4448         int ret = 0;
4449
4450         type = BNXT_FW_STATUS_REG_TYPE(reg);
4451         offset = BNXT_FW_STATUS_REG_OFF(reg);
4452
4453         switch (type) {
4454         case BNXT_FW_STATUS_REG_TYPE_CFG:
4455                 ret = rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4456                 if (ret < 0)
4457                         PMD_DRV_LOG(ERR, "Failed to read PCI offset %#x",
4458                                     offset);
4459                 break;
4460         case BNXT_FW_STATUS_REG_TYPE_GRC:
4461                 offset = info->mapped_status_regs[index];
4462                 /* FALLTHROUGH */
4463         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4464                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4465                                        offset));
4466                 break;
4467         }
4468
4469         return val;
4470 }
4471
4472 static int bnxt_fw_reset_all(struct bnxt *bp)
4473 {
4474         struct bnxt_error_recovery_info *info = bp->recovery_info;
4475         uint32_t i;
4476         int rc = 0;
4477
4478         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4479                 /* Reset through primary function driver */
4480                 for (i = 0; i < info->reg_array_cnt; i++)
4481                         bnxt_write_fw_reset_reg(bp, i);
4482                 /* Wait for time specified by FW after triggering reset */
4483                 rte_delay_ms(info->primary_func_wait_period_after_reset);
4484         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4485                 /* Reset with the help of Kong processor */
4486                 rc = bnxt_hwrm_fw_reset(bp);
4487                 if (rc)
4488                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4489         }
4490
4491         return rc;
4492 }
4493
4494 static void bnxt_fw_reset_cb(void *arg)
4495 {
4496         struct bnxt *bp = arg;
4497         struct bnxt_error_recovery_info *info = bp->recovery_info;
4498         int rc = 0;
4499
4500         /* Only Primary function can do FW reset */
4501         if (bnxt_is_primary_func(bp) &&
4502             bnxt_is_recovery_enabled(bp)) {
4503                 rc = bnxt_fw_reset_all(bp);
4504                 if (rc) {
4505                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4506                         return;
4507                 }
4508         }
4509
4510         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4511          * EXCEPTION_FATAL_ASYNC event to all the functions
4512          * (including MASTER FUNC). After receiving this Async, all the active
4513          * drivers should treat this case as FW initiated recovery
4514          */
4515         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4516                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4517                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4518
4519                 /* To recover from error */
4520                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4521                                   (void *)bp);
4522         }
4523 }
4524
4525 /* Driver should poll FW heartbeat, reset_counter with the frequency
4526  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4527  * When the driver detects heartbeat stop or change in reset_counter,
4528  * it has to trigger a reset to recover from the error condition.
4529  * A “primary function” is the function who will have the privilege to
4530  * initiate the chimp reset. The primary function will be elected by the
4531  * firmware and will be notified through async message.
4532  */
4533 static void bnxt_check_fw_health(void *arg)
4534 {
4535         struct bnxt *bp = arg;
4536         struct bnxt_error_recovery_info *info = bp->recovery_info;
4537         uint32_t val = 0, wait_msec;
4538
4539         if (!info || !bnxt_is_recovery_enabled(bp) ||
4540             is_bnxt_in_error(bp))
4541                 return;
4542
4543         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4544         if (val == info->last_heart_beat)
4545                 goto reset;
4546
4547         info->last_heart_beat = val;
4548
4549         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4550         if (val != info->last_reset_counter)
4551                 goto reset;
4552
4553         info->last_reset_counter = val;
4554
4555         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4556                           bnxt_check_fw_health, (void *)bp);
4557
4558         return;
4559 reset:
4560         /* Stop DMA to/from device */
4561         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4562         bp->flags |= BNXT_FLAG_FW_RESET;
4563
4564         bnxt_stop_rxtx(bp);
4565
4566         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4567
4568         if (bnxt_is_primary_func(bp))
4569                 wait_msec = info->primary_func_wait_period;
4570         else
4571                 wait_msec = info->normal_func_wait_period;
4572
4573         rte_eal_alarm_set(US_PER_MS * wait_msec,
4574                           bnxt_fw_reset_cb, (void *)bp);
4575 }
4576
4577 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4578 {
4579         uint32_t polling_freq;
4580
4581         pthread_mutex_lock(&bp->health_check_lock);
4582
4583         if (!bnxt_is_recovery_enabled(bp))
4584                 goto done;
4585
4586         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4587                 goto done;
4588
4589         polling_freq = bp->recovery_info->driver_polling_freq;
4590
4591         rte_eal_alarm_set(US_PER_MS * polling_freq,
4592                           bnxt_check_fw_health, (void *)bp);
4593         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4594
4595 done:
4596         pthread_mutex_unlock(&bp->health_check_lock);
4597 }
4598
4599 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4600 {
4601         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4602         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4603 }
4604
4605 static bool bnxt_vf_pciid(uint16_t device_id)
4606 {
4607         switch (device_id) {
4608         case BROADCOM_DEV_ID_57304_VF:
4609         case BROADCOM_DEV_ID_57406_VF:
4610         case BROADCOM_DEV_ID_5731X_VF:
4611         case BROADCOM_DEV_ID_5741X_VF:
4612         case BROADCOM_DEV_ID_57414_VF:
4613         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4614         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4615         case BROADCOM_DEV_ID_58802_VF:
4616         case BROADCOM_DEV_ID_57500_VF1:
4617         case BROADCOM_DEV_ID_57500_VF2:
4618         case BROADCOM_DEV_ID_58818_VF:
4619                 /* FALLTHROUGH */
4620                 return true;
4621         default:
4622                 return false;
4623         }
4624 }
4625
4626 /* Phase 5 device */
4627 static bool bnxt_p5_device(uint16_t device_id)
4628 {
4629         switch (device_id) {
4630         case BROADCOM_DEV_ID_57508:
4631         case BROADCOM_DEV_ID_57504:
4632         case BROADCOM_DEV_ID_57502:
4633         case BROADCOM_DEV_ID_57508_MF1:
4634         case BROADCOM_DEV_ID_57504_MF1:
4635         case BROADCOM_DEV_ID_57502_MF1:
4636         case BROADCOM_DEV_ID_57508_MF2:
4637         case BROADCOM_DEV_ID_57504_MF2:
4638         case BROADCOM_DEV_ID_57502_MF2:
4639         case BROADCOM_DEV_ID_57500_VF1:
4640         case BROADCOM_DEV_ID_57500_VF2:
4641         case BROADCOM_DEV_ID_58812:
4642         case BROADCOM_DEV_ID_58814:
4643         case BROADCOM_DEV_ID_58818:
4644         case BROADCOM_DEV_ID_58818_VF:
4645                 /* FALLTHROUGH */
4646                 return true;
4647         default:
4648                 return false;
4649         }
4650 }
4651
4652 bool bnxt_stratus_device(struct bnxt *bp)
4653 {
4654         uint16_t device_id = bp->pdev->id.device_id;
4655
4656         switch (device_id) {
4657         case BROADCOM_DEV_ID_STRATUS_NIC:
4658         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4659         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4660                 /* FALLTHROUGH */
4661                 return true;
4662         default:
4663                 return false;
4664         }
4665 }
4666
4667 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev)
4668 {
4669         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4670         struct bnxt *bp = eth_dev->data->dev_private;
4671
4672         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4673         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4674         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4675         if (!bp->bar0 || !bp->doorbell_base) {
4676                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4677                 return -ENODEV;
4678         }
4679
4680         bp->eth_dev = eth_dev;
4681         bp->pdev = pci_dev;
4682
4683         return 0;
4684 }
4685
4686 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4687                                   struct bnxt_ctx_pg_info *ctx_pg,
4688                                   uint32_t mem_size,
4689                                   const char *suffix,
4690                                   uint16_t idx)
4691 {
4692         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4693         const struct rte_memzone *mz = NULL;
4694         char mz_name[RTE_MEMZONE_NAMESIZE];
4695         rte_iova_t mz_phys_addr;
4696         uint64_t valid_bits = 0;
4697         uint32_t sz;
4698         int i;
4699
4700         if (!mem_size)
4701                 return 0;
4702
4703         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4704                          BNXT_PAGE_SIZE;
4705         rmem->page_size = BNXT_PAGE_SIZE;
4706         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4707         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4708         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4709
4710         valid_bits = PTU_PTE_VALID;
4711
4712         if (rmem->nr_pages > 1) {
4713                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4714                          "bnxt_ctx_pg_tbl%s_%x_%d",
4715                          suffix, idx, bp->eth_dev->data->port_id);
4716                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4717                 mz = rte_memzone_lookup(mz_name);
4718                 if (!mz) {
4719                         mz = rte_memzone_reserve_aligned(mz_name,
4720                                                 rmem->nr_pages * 8,
4721                                                 bp->eth_dev->device->numa_node,
4722                                                 RTE_MEMZONE_2MB |
4723                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4724                                                 RTE_MEMZONE_IOVA_CONTIG,
4725                                                 BNXT_PAGE_SIZE);
4726                         if (mz == NULL)
4727                                 return -ENOMEM;
4728                 }
4729
4730                 memset(mz->addr, 0, mz->len);
4731                 mz_phys_addr = mz->iova;
4732
4733                 rmem->pg_tbl = mz->addr;
4734                 rmem->pg_tbl_map = mz_phys_addr;
4735                 rmem->pg_tbl_mz = mz;
4736         }
4737
4738         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4739                  suffix, idx, bp->eth_dev->data->port_id);
4740         mz = rte_memzone_lookup(mz_name);
4741         if (!mz) {
4742                 mz = rte_memzone_reserve_aligned(mz_name,
4743                                                  mem_size,
4744                                                  bp->eth_dev->device->numa_node,
4745                                                  RTE_MEMZONE_1GB |
4746                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4747                                                  RTE_MEMZONE_IOVA_CONTIG,
4748                                                  BNXT_PAGE_SIZE);
4749                 if (mz == NULL)
4750                         return -ENOMEM;
4751         }
4752
4753         memset(mz->addr, 0, mz->len);
4754         mz_phys_addr = mz->iova;
4755
4756         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4757                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4758                 rmem->dma_arr[i] = mz_phys_addr + sz;
4759
4760                 if (rmem->nr_pages > 1) {
4761                         if (i == rmem->nr_pages - 2 &&
4762                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4763                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4764                         else if (i == rmem->nr_pages - 1 &&
4765                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4766                                 valid_bits |= PTU_PTE_LAST;
4767
4768                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4769                                                            valid_bits);
4770                 }
4771         }
4772
4773         rmem->mz = mz;
4774         if (rmem->vmem_size)
4775                 rmem->vmem = (void **)mz->addr;
4776         rmem->dma_arr[0] = mz_phys_addr;
4777         return 0;
4778 }
4779
4780 static void bnxt_free_ctx_mem(struct bnxt *bp)
4781 {
4782         int i;
4783
4784         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4785                 return;
4786
4787         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4788         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4789         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4790         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4791         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4792         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4793         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4794         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4795         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4796         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4797         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4798
4799         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4800                 if (bp->ctx->tqm_mem[i])
4801                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4802         }
4803
4804         rte_free(bp->ctx);
4805         bp->ctx = NULL;
4806 }
4807
4808 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4809
4810 #define min_t(type, x, y) ({                    \
4811         type __min1 = (x);                      \
4812         type __min2 = (y);                      \
4813         __min1 < __min2 ? __min1 : __min2; })
4814
4815 #define max_t(type, x, y) ({                    \
4816         type __max1 = (x);                      \
4817         type __max2 = (y);                      \
4818         __max1 > __max2 ? __max1 : __max2; })
4819
4820 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4821
4822 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4823 {
4824         struct bnxt_ctx_pg_info *ctx_pg;
4825         struct bnxt_ctx_mem_info *ctx;
4826         uint32_t mem_size, ena, entries;
4827         uint32_t entries_sp, min;
4828         int i, rc;
4829
4830         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4831         if (rc) {
4832                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4833                 return rc;
4834         }
4835         ctx = bp->ctx;
4836         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4837                 return 0;
4838
4839         ctx_pg = &ctx->qp_mem;
4840         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4841         if (ctx->qp_entry_size) {
4842                 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4843                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4844                 if (rc)
4845                         return rc;
4846         }
4847
4848         ctx_pg = &ctx->srq_mem;
4849         ctx_pg->entries = ctx->srq_max_l2_entries;
4850         if (ctx->srq_entry_size) {
4851                 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4852                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4853                 if (rc)
4854                         return rc;
4855         }
4856
4857         ctx_pg = &ctx->cq_mem;
4858         ctx_pg->entries = ctx->cq_max_l2_entries;
4859         if (ctx->cq_entry_size) {
4860                 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4861                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4862                 if (rc)
4863                         return rc;
4864         }
4865
4866         ctx_pg = &ctx->vnic_mem;
4867         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4868                 ctx->vnic_max_ring_table_entries;
4869         if (ctx->vnic_entry_size) {
4870                 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4871                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4872                 if (rc)
4873                         return rc;
4874         }
4875
4876         ctx_pg = &ctx->stat_mem;
4877         ctx_pg->entries = ctx->stat_max_entries;
4878         if (ctx->stat_entry_size) {
4879                 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4880                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4881                 if (rc)
4882                         return rc;
4883         }
4884
4885         min = ctx->tqm_min_entries_per_ring;
4886
4887         entries_sp = ctx->qp_max_l2_entries +
4888                      ctx->vnic_max_vnic_entries +
4889                      2 * ctx->qp_min_qp1_entries + min;
4890         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4891
4892         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4893         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4894         entries = clamp_t(uint32_t, entries, min,
4895                           ctx->tqm_max_entries_per_ring);
4896         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4897                 /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7.
4898                  * i > 8 is other ext rings.
4899                  */
4900                 ctx_pg = ctx->tqm_mem[i];
4901                 ctx_pg->entries = i ? entries : entries_sp;
4902                 if (ctx->tqm_entry_size) {
4903                         mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4904                         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size,
4905                                                     "tqm_mem", i);
4906                         if (rc)
4907                                 return rc;
4908                 }
4909                 if (i < BNXT_MAX_TQM_LEGACY_RINGS)
4910                         ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4911                 else
4912                         ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8;
4913         }
4914
4915         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4916         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4917         if (rc)
4918                 PMD_DRV_LOG(ERR,
4919                             "Failed to configure context mem: rc = %d\n", rc);
4920         else
4921                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4922
4923         return rc;
4924 }
4925
4926 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4927 {
4928         struct rte_pci_device *pci_dev = bp->pdev;
4929         char mz_name[RTE_MEMZONE_NAMESIZE];
4930         const struct rte_memzone *mz = NULL;
4931         uint32_t total_alloc_len;
4932         rte_iova_t mz_phys_addr;
4933
4934         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4935                 return 0;
4936
4937         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4938                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4939                  pci_dev->addr.bus, pci_dev->addr.devid,
4940                  pci_dev->addr.function, "rx_port_stats");
4941         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4942         mz = rte_memzone_lookup(mz_name);
4943         total_alloc_len =
4944                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4945                                        sizeof(struct rx_port_stats_ext) + 512);
4946         if (!mz) {
4947                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4948                                          SOCKET_ID_ANY,
4949                                          RTE_MEMZONE_2MB |
4950                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4951                                          RTE_MEMZONE_IOVA_CONTIG);
4952                 if (mz == NULL)
4953                         return -ENOMEM;
4954         }
4955         memset(mz->addr, 0, mz->len);
4956         mz_phys_addr = mz->iova;
4957
4958         bp->rx_mem_zone = (const void *)mz;
4959         bp->hw_rx_port_stats = mz->addr;
4960         bp->hw_rx_port_stats_map = mz_phys_addr;
4961
4962         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4963                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4964                  pci_dev->addr.bus, pci_dev->addr.devid,
4965                  pci_dev->addr.function, "tx_port_stats");
4966         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4967         mz = rte_memzone_lookup(mz_name);
4968         total_alloc_len =
4969                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4970                                        sizeof(struct tx_port_stats_ext) + 512);
4971         if (!mz) {
4972                 mz = rte_memzone_reserve(mz_name,
4973                                          total_alloc_len,
4974                                          SOCKET_ID_ANY,
4975                                          RTE_MEMZONE_2MB |
4976                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4977                                          RTE_MEMZONE_IOVA_CONTIG);
4978                 if (mz == NULL)
4979                         return -ENOMEM;
4980         }
4981         memset(mz->addr, 0, mz->len);
4982         mz_phys_addr = mz->iova;
4983
4984         bp->tx_mem_zone = (const void *)mz;
4985         bp->hw_tx_port_stats = mz->addr;
4986         bp->hw_tx_port_stats_map = mz_phys_addr;
4987         bp->flags |= BNXT_FLAG_PORT_STATS;
4988
4989         /* Display extended statistics if FW supports it */
4990         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4991             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4992             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4993                 return 0;
4994
4995         bp->hw_rx_port_stats_ext = (void *)
4996                 ((uint8_t *)bp->hw_rx_port_stats +
4997                  sizeof(struct rx_port_stats));
4998         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4999                 sizeof(struct rx_port_stats);
5000         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
5001
5002         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
5003             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
5004                 bp->hw_tx_port_stats_ext = (void *)
5005                         ((uint8_t *)bp->hw_tx_port_stats +
5006                          sizeof(struct tx_port_stats));
5007                 bp->hw_tx_port_stats_ext_map =
5008                         bp->hw_tx_port_stats_map +
5009                         sizeof(struct tx_port_stats);
5010                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
5011         }
5012
5013         return 0;
5014 }
5015
5016 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
5017 {
5018         struct bnxt *bp = eth_dev->data->dev_private;
5019         int rc = 0;
5020
5021         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
5022                                                RTE_ETHER_ADDR_LEN *
5023                                                bp->max_l2_ctx,
5024                                                0);
5025         if (eth_dev->data->mac_addrs == NULL) {
5026                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
5027                 return -ENOMEM;
5028         }
5029
5030         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
5031                 if (BNXT_PF(bp))
5032                         return -EINVAL;
5033
5034                 /* Generate a random MAC address, if none was assigned by PF */
5035                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5036                 bnxt_eth_hw_addr_random(bp->mac_addr);
5037                 PMD_DRV_LOG(INFO,
5038                             "Assign random MAC:" RTE_ETHER_ADDR_PRT_FMT "\n",
5039                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5040                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5041
5042                 rc = bnxt_hwrm_set_mac(bp);
5043                 if (rc)
5044                         return rc;
5045         }
5046
5047         /* Copy the permanent MAC from the FUNC_QCAPS response */
5048         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5049
5050         /*
5051          *  Allocate memory to hold multicast mac addresses added.
5052          *  Used to restore them during reset recovery
5053          */
5054         bp->mcast_addr_list = rte_zmalloc("bnxt_mcast_addr_tbl",
5055                                           sizeof(struct rte_ether_addr) *
5056                                           BNXT_MAX_MC_ADDRS, 0);
5057         if (bp->mcast_addr_list == NULL) {
5058                 PMD_DRV_LOG(ERR, "Failed to allocate multicast addr table\n");
5059                 return -ENOMEM;
5060         }
5061         bp->mc_list_dma_addr = rte_malloc_virt2iova(bp->mcast_addr_list);
5062         if (bp->mc_list_dma_addr == RTE_BAD_IOVA) {
5063                 PMD_DRV_LOG(ERR, "Fail to map mcast_addr_list to physical memory\n");
5064                 return -ENOMEM;
5065         }
5066
5067         return rc;
5068 }
5069
5070 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5071 {
5072         int rc = 0;
5073
5074         /* MAC is already configured in FW */
5075         if (BNXT_HAS_DFLT_MAC_SET(bp))
5076                 return 0;
5077
5078         /* Restore the old MAC configured */
5079         rc = bnxt_hwrm_set_mac(bp);
5080         if (rc)
5081                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5082
5083         return rc;
5084 }
5085
5086 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5087 {
5088         if (!BNXT_PF(bp))
5089                 return;
5090
5091         memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5092
5093         if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
5094                 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
5095         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
5096         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
5097         BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
5098         BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
5099 }
5100
5101 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5102 {
5103         struct bnxt_error_recovery_info *info = bp->recovery_info;
5104
5105         if (info) {
5106                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5107                         memset(info, 0, sizeof(*info));
5108                 return;
5109         }
5110
5111         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5112                 return;
5113
5114         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5115                            sizeof(*info), 0);
5116         if (!info)
5117                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5118
5119         bp->recovery_info = info;
5120 }
5121
5122 static void bnxt_check_fw_status(struct bnxt *bp)
5123 {
5124         uint32_t fw_status;
5125
5126         if (!(bp->recovery_info &&
5127               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5128                 return;
5129
5130         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5131         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5132                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5133                             fw_status);
5134 }
5135
5136 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5137 {
5138         struct bnxt_error_recovery_info *info = bp->recovery_info;
5139         uint32_t status_loc;
5140         uint32_t sig_ver;
5141
5142         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5143                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5144         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5145                                    BNXT_GRCP_WINDOW_2_BASE +
5146                                    offsetof(struct hcomm_status,
5147                                             sig_ver)));
5148         /* If the signature is absent, then FW does not support this feature */
5149         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5150             HCOMM_STATUS_SIGNATURE_VAL)
5151                 return 0;
5152
5153         if (!info) {
5154                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5155                                    sizeof(*info), 0);
5156                 if (!info)
5157                         return -ENOMEM;
5158                 bp->recovery_info = info;
5159         } else {
5160                 memset(info, 0, sizeof(*info));
5161         }
5162
5163         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5164                                       BNXT_GRCP_WINDOW_2_BASE +
5165                                       offsetof(struct hcomm_status,
5166                                                fw_status_loc)));
5167
5168         /* Only pre-map the FW health status GRC register */
5169         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5170                 return 0;
5171
5172         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5173         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5174                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5175
5176         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5177                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5178
5179         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5180
5181         return 0;
5182 }
5183
5184 /* This function gets the FW version along with the
5185  * capabilities(MAX and current) of the function, vnic,
5186  * error recovery, phy and other chip related info
5187  */
5188 static int bnxt_get_config(struct bnxt *bp)
5189 {
5190         uint16_t mtu;
5191         int rc = 0;
5192
5193         bp->fw_cap = 0;
5194
5195         rc = bnxt_map_hcomm_fw_status_reg(bp);
5196         if (rc)
5197                 return rc;
5198
5199         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5200         if (rc) {
5201                 bnxt_check_fw_status(bp);
5202                 return rc;
5203         }
5204
5205         rc = bnxt_hwrm_func_reset(bp);
5206         if (rc)
5207                 return -EIO;
5208
5209         rc = bnxt_hwrm_vnic_qcaps(bp);
5210         if (rc)
5211                 return rc;
5212
5213         rc = bnxt_hwrm_queue_qportcfg(bp);
5214         if (rc)
5215                 return rc;
5216
5217         /* Get the MAX capabilities for this function.
5218          * This function also allocates context memory for TQM rings and
5219          * informs the firmware about this allocated backing store memory.
5220          */
5221         rc = bnxt_hwrm_func_qcaps(bp);
5222         if (rc)
5223                 return rc;
5224
5225         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5226         if (rc)
5227                 return rc;
5228
5229         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5230         if (rc)
5231                 return rc;
5232
5233         bnxt_hwrm_port_mac_qcfg(bp);
5234
5235         bnxt_hwrm_parent_pf_qcfg(bp);
5236
5237         bnxt_hwrm_port_phy_qcaps(bp);
5238
5239         bnxt_alloc_error_recovery_info(bp);
5240         /* Get the adapter error recovery support info */
5241         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5242         if (rc)
5243                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5244
5245         bnxt_hwrm_port_led_qcaps(bp);
5246
5247         return 0;
5248 }
5249
5250 static int
5251 bnxt_init_locks(struct bnxt *bp)
5252 {
5253         int err;
5254
5255         err = pthread_mutex_init(&bp->flow_lock, NULL);
5256         if (err) {
5257                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5258                 return err;
5259         }
5260
5261         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5262         if (err) {
5263                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5264                 return err;
5265         }
5266
5267         err = pthread_mutex_init(&bp->health_check_lock, NULL);
5268         if (err) {
5269                 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5270                 return err;
5271         }
5272
5273         err = pthread_mutex_init(&bp->err_recovery_lock, NULL);
5274         if (err)
5275                 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n");
5276
5277         return err;
5278 }
5279
5280 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5281 {
5282         int rc = 0;
5283
5284         rc = bnxt_get_config(bp);
5285         if (rc)
5286                 return rc;
5287
5288         if (!reconfig_dev) {
5289                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5290                 if (rc)
5291                         return rc;
5292         } else {
5293                 rc = bnxt_restore_dflt_mac(bp);
5294                 if (rc)
5295                         return rc;
5296         }
5297
5298         bnxt_config_vf_req_fwd(bp);
5299
5300         rc = bnxt_hwrm_func_driver_register(bp);
5301         if (rc) {
5302                 PMD_DRV_LOG(ERR, "Failed to register driver");
5303                 return -EBUSY;
5304         }
5305
5306         if (BNXT_PF(bp)) {
5307                 if (bp->pdev->max_vfs) {
5308                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5309                         if (rc) {
5310                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5311                                 return rc;
5312                         }
5313                 } else {
5314                         rc = bnxt_hwrm_allocate_pf_only(bp);
5315                         if (rc) {
5316                                 PMD_DRV_LOG(ERR,
5317                                             "Failed to allocate PF resources");
5318                                 return rc;
5319                         }
5320                 }
5321         }
5322
5323         if (!reconfig_dev) {
5324                 bp->rss_conf.rss_key = rte_zmalloc("bnxt_rss_key",
5325                                                    HW_HASH_KEY_SIZE, 0);
5326                 if (bp->rss_conf.rss_key == NULL) {
5327                         PMD_DRV_LOG(ERR, "port %u cannot allocate RSS hash key memory",
5328                                     bp->eth_dev->data->port_id);
5329                         return -ENOMEM;
5330                 }
5331         }
5332
5333         rc = bnxt_alloc_mem(bp, reconfig_dev);
5334         if (rc)
5335                 return rc;
5336
5337         rc = bnxt_setup_int(bp);
5338         if (rc)
5339                 return rc;
5340
5341         rc = bnxt_request_int(bp);
5342         if (rc)
5343                 return rc;
5344
5345         rc = bnxt_init_ctx_mem(bp);
5346         if (rc) {
5347                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5348                 return rc;
5349         }
5350
5351         return 0;
5352 }
5353
5354 static int
5355 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5356                              const char *value, void *opaque_arg)
5357 {
5358         struct bnxt *bp = opaque_arg;
5359         unsigned long flow_xstat;
5360         char *end = NULL;
5361
5362         if (!value || !opaque_arg) {
5363                 PMD_DRV_LOG(ERR,
5364                             "Invalid parameter passed to flow_xstat devarg.\n");
5365                 return -EINVAL;
5366         }
5367
5368         flow_xstat = strtoul(value, &end, 10);
5369         if (end == NULL || *end != '\0' ||
5370             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5371                 PMD_DRV_LOG(ERR,
5372                             "Invalid parameter passed to flow_xstat devarg.\n");
5373                 return -EINVAL;
5374         }
5375
5376         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5377                 PMD_DRV_LOG(ERR,
5378                             "Invalid value passed to flow_xstat devarg.\n");
5379                 return -EINVAL;
5380         }
5381
5382         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5383         if (BNXT_FLOW_XSTATS_EN(bp))
5384                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5385
5386         return 0;
5387 }
5388
5389 static int
5390 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5391                                         const char *value, void *opaque_arg)
5392 {
5393         struct bnxt *bp = opaque_arg;
5394         unsigned long max_num_kflows;
5395         char *end = NULL;
5396
5397         if (!value || !opaque_arg) {
5398                 PMD_DRV_LOG(ERR,
5399                         "Invalid parameter passed to max_num_kflows devarg.\n");
5400                 return -EINVAL;
5401         }
5402
5403         max_num_kflows = strtoul(value, &end, 10);
5404         if (end == NULL || *end != '\0' ||
5405                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5406                 PMD_DRV_LOG(ERR,
5407                         "Invalid parameter passed to max_num_kflows devarg.\n");
5408                 return -EINVAL;
5409         }
5410
5411         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5412                 PMD_DRV_LOG(ERR,
5413                         "Invalid value passed to max_num_kflows devarg.\n");
5414                 return -EINVAL;
5415         }
5416
5417         bp->max_num_kflows = max_num_kflows;
5418         if (bp->max_num_kflows)
5419                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5420                                 max_num_kflows);
5421
5422         return 0;
5423 }
5424
5425 static int
5426 bnxt_parse_devarg_app_id(__rte_unused const char *key,
5427                                  const char *value, void *opaque_arg)
5428 {
5429         struct bnxt *bp = opaque_arg;
5430         unsigned long app_id;
5431         char *end = NULL;
5432
5433         if (!value || !opaque_arg) {
5434                 PMD_DRV_LOG(ERR,
5435                             "Invalid parameter passed to app-id "
5436                             "devargs.\n");
5437                 return -EINVAL;
5438         }
5439
5440         app_id = strtoul(value, &end, 10);
5441         if (end == NULL || *end != '\0' ||
5442             (app_id == ULONG_MAX && errno == ERANGE)) {
5443                 PMD_DRV_LOG(ERR,
5444                             "Invalid parameter passed to app_id "
5445                             "devargs.\n");
5446                 return -EINVAL;
5447         }
5448
5449         if (BNXT_DEVARG_APP_ID_INVALID(app_id)) {
5450                 PMD_DRV_LOG(ERR, "Invalid app-id(%d) devargs.\n",
5451                             (uint16_t)app_id);
5452                 return -EINVAL;
5453         }
5454
5455         bp->app_id = app_id;
5456         PMD_DRV_LOG(INFO, "app-id=%d feature enabled.\n", (uint16_t)app_id);
5457
5458         return 0;
5459 }
5460
5461 static int
5462 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5463                             const char *value, void *opaque_arg)
5464 {
5465         struct bnxt_representor *vfr_bp = opaque_arg;
5466         unsigned long rep_is_pf;
5467         char *end = NULL;
5468
5469         if (!value || !opaque_arg) {
5470                 PMD_DRV_LOG(ERR,
5471                             "Invalid parameter passed to rep_is_pf devargs.\n");
5472                 return -EINVAL;
5473         }
5474
5475         rep_is_pf = strtoul(value, &end, 10);
5476         if (end == NULL || *end != '\0' ||
5477             (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5478                 PMD_DRV_LOG(ERR,
5479                             "Invalid parameter passed to rep_is_pf devargs.\n");
5480                 return -EINVAL;
5481         }
5482
5483         if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5484                 PMD_DRV_LOG(ERR,
5485                             "Invalid value passed to rep_is_pf devargs.\n");
5486                 return -EINVAL;
5487         }
5488
5489         vfr_bp->flags |= rep_is_pf;
5490         if (BNXT_REP_PF(vfr_bp))
5491                 PMD_DRV_LOG(INFO, "PF representor\n");
5492         else
5493                 PMD_DRV_LOG(INFO, "VF representor\n");
5494
5495         return 0;
5496 }
5497
5498 static int
5499 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5500                                const char *value, void *opaque_arg)
5501 {
5502         struct bnxt_representor *vfr_bp = opaque_arg;
5503         unsigned long rep_based_pf;
5504         char *end = NULL;
5505
5506         if (!value || !opaque_arg) {
5507                 PMD_DRV_LOG(ERR,
5508                             "Invalid parameter passed to rep_based_pf "
5509                             "devargs.\n");
5510                 return -EINVAL;
5511         }
5512
5513         rep_based_pf = strtoul(value, &end, 10);
5514         if (end == NULL || *end != '\0' ||
5515             (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5516                 PMD_DRV_LOG(ERR,
5517                             "Invalid parameter passed to rep_based_pf "
5518                             "devargs.\n");
5519                 return -EINVAL;
5520         }
5521
5522         if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5523                 PMD_DRV_LOG(ERR,
5524                             "Invalid value passed to rep_based_pf devargs.\n");
5525                 return -EINVAL;
5526         }
5527
5528         vfr_bp->rep_based_pf = rep_based_pf;
5529         vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
5530
5531         PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5532
5533         return 0;
5534 }
5535
5536 static int
5537 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5538                             const char *value, void *opaque_arg)
5539 {
5540         struct bnxt_representor *vfr_bp = opaque_arg;
5541         unsigned long rep_q_r2f;
5542         char *end = NULL;
5543
5544         if (!value || !opaque_arg) {
5545                 PMD_DRV_LOG(ERR,
5546                             "Invalid parameter passed to rep_q_r2f "
5547                             "devargs.\n");
5548                 return -EINVAL;
5549         }
5550
5551         rep_q_r2f = strtoul(value, &end, 10);
5552         if (end == NULL || *end != '\0' ||
5553             (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5554                 PMD_DRV_LOG(ERR,
5555                             "Invalid parameter passed to rep_q_r2f "
5556                             "devargs.\n");
5557                 return -EINVAL;
5558         }
5559
5560         if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5561                 PMD_DRV_LOG(ERR,
5562                             "Invalid value passed to rep_q_r2f devargs.\n");
5563                 return -EINVAL;
5564         }
5565
5566         vfr_bp->rep_q_r2f = rep_q_r2f;
5567         vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5568         PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5569
5570         return 0;
5571 }
5572
5573 static int
5574 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5575                             const char *value, void *opaque_arg)
5576 {
5577         struct bnxt_representor *vfr_bp = opaque_arg;
5578         unsigned long rep_q_f2r;
5579         char *end = NULL;
5580
5581         if (!value || !opaque_arg) {
5582                 PMD_DRV_LOG(ERR,
5583                             "Invalid parameter passed to rep_q_f2r "
5584                             "devargs.\n");
5585                 return -EINVAL;
5586         }
5587
5588         rep_q_f2r = strtoul(value, &end, 10);
5589         if (end == NULL || *end != '\0' ||
5590             (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5591                 PMD_DRV_LOG(ERR,
5592                             "Invalid parameter passed to rep_q_f2r "
5593                             "devargs.\n");
5594                 return -EINVAL;
5595         }
5596
5597         if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5598                 PMD_DRV_LOG(ERR,
5599                             "Invalid value passed to rep_q_f2r devargs.\n");
5600                 return -EINVAL;
5601         }
5602
5603         vfr_bp->rep_q_f2r = rep_q_f2r;
5604         vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5605         PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5606
5607         return 0;
5608 }
5609
5610 static int
5611 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5612                              const char *value, void *opaque_arg)
5613 {
5614         struct bnxt_representor *vfr_bp = opaque_arg;
5615         unsigned long rep_fc_r2f;
5616         char *end = NULL;
5617
5618         if (!value || !opaque_arg) {
5619                 PMD_DRV_LOG(ERR,
5620                             "Invalid parameter passed to rep_fc_r2f "
5621                             "devargs.\n");
5622                 return -EINVAL;
5623         }
5624
5625         rep_fc_r2f = strtoul(value, &end, 10);
5626         if (end == NULL || *end != '\0' ||
5627             (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5628                 PMD_DRV_LOG(ERR,
5629                             "Invalid parameter passed to rep_fc_r2f "
5630                             "devargs.\n");
5631                 return -EINVAL;
5632         }
5633
5634         if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5635                 PMD_DRV_LOG(ERR,
5636                             "Invalid value passed to rep_fc_r2f devargs.\n");
5637                 return -EINVAL;
5638         }
5639
5640         vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5641         vfr_bp->rep_fc_r2f = rep_fc_r2f;
5642         PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5643
5644         return 0;
5645 }
5646
5647 static int
5648 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5649                              const char *value, void *opaque_arg)
5650 {
5651         struct bnxt_representor *vfr_bp = opaque_arg;
5652         unsigned long rep_fc_f2r;
5653         char *end = NULL;
5654
5655         if (!value || !opaque_arg) {
5656                 PMD_DRV_LOG(ERR,
5657                             "Invalid parameter passed to rep_fc_f2r "
5658                             "devargs.\n");
5659                 return -EINVAL;
5660         }
5661
5662         rep_fc_f2r = strtoul(value, &end, 10);
5663         if (end == NULL || *end != '\0' ||
5664             (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5665                 PMD_DRV_LOG(ERR,
5666                             "Invalid parameter passed to rep_fc_f2r "
5667                             "devargs.\n");
5668                 return -EINVAL;
5669         }
5670
5671         if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5672                 PMD_DRV_LOG(ERR,
5673                             "Invalid value passed to rep_fc_f2r devargs.\n");
5674                 return -EINVAL;
5675         }
5676
5677         vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5678         vfr_bp->rep_fc_f2r = rep_fc_f2r;
5679         PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5680
5681         return 0;
5682 }
5683
5684 static int
5685 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5686 {
5687         struct rte_kvargs *kvlist;
5688         int ret;
5689
5690         if (devargs == NULL)
5691                 return 0;
5692
5693         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5694         if (kvlist == NULL)
5695                 return -EINVAL;
5696
5697         /*
5698          * Handler for "flow_xstat" devarg.
5699          * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5700          */
5701         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5702                                  bnxt_parse_devarg_flow_xstat, bp);
5703         if (ret)
5704                 goto err;
5705
5706         /*
5707          * Handler for "max_num_kflows" devarg.
5708          * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5709          */
5710         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5711                                  bnxt_parse_devarg_max_num_kflows, bp);
5712         if (ret)
5713                 goto err;
5714
5715 err:
5716         /*
5717          * Handler for "app-id" devarg.
5718          * Invoked as for ex: "-a 000:00:0d.0,app-id=1"
5719          */
5720         rte_kvargs_process(kvlist, BNXT_DEVARG_APP_ID,
5721                            bnxt_parse_devarg_app_id, bp);
5722
5723         rte_kvargs_free(kvlist);
5724         return ret;
5725 }
5726
5727 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5728 {
5729         int rc = 0;
5730
5731         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5732                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5733                 if (rc)
5734                         PMD_DRV_LOG(ERR,
5735                                     "Failed to alloc switch domain: %d\n", rc);
5736                 else
5737                         PMD_DRV_LOG(INFO,
5738                                     "Switch domain allocated %d\n",
5739                                     bp->switch_domain_id);
5740         }
5741
5742         return rc;
5743 }
5744
5745 /* Allocate and initialize various fields in bnxt struct that
5746  * need to be allocated/destroyed only once in the lifetime of the driver
5747  */
5748 static int bnxt_drv_init(struct rte_eth_dev *eth_dev)
5749 {
5750         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5751         struct bnxt *bp = eth_dev->data->dev_private;
5752         int rc = 0;
5753
5754         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5755
5756         if (bnxt_vf_pciid(pci_dev->id.device_id))
5757                 bp->flags |= BNXT_FLAG_VF;
5758
5759         if (bnxt_p5_device(pci_dev->id.device_id))
5760                 bp->flags |= BNXT_FLAG_CHIP_P5;
5761
5762         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5763             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5764             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5765             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5766                 bp->flags |= BNXT_FLAG_STINGRAY;
5767
5768         if (BNXT_TRUFLOW_EN(bp)) {
5769                 /* extra mbuf field is required to store CFA code from mark */
5770                 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5771                         .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5772                         .size = sizeof(bnxt_cfa_code_dynfield_t),
5773                         .align = __alignof__(bnxt_cfa_code_dynfield_t),
5774                 };
5775                 bnxt_cfa_code_dynfield_offset =
5776                         rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5777                 if (bnxt_cfa_code_dynfield_offset < 0) {
5778                         PMD_DRV_LOG(ERR,
5779                             "Failed to register mbuf field for TruFlow mark\n");
5780                         return -rte_errno;
5781                 }
5782         }
5783
5784         rc = bnxt_map_pci_bars(eth_dev);
5785         if (rc) {
5786                 PMD_DRV_LOG(ERR,
5787                             "Failed to initialize board rc: %x\n", rc);
5788                 return rc;
5789         }
5790
5791         rc = bnxt_alloc_pf_info(bp);
5792         if (rc)
5793                 return rc;
5794
5795         rc = bnxt_alloc_link_info(bp);
5796         if (rc)
5797                 return rc;
5798
5799         rc = bnxt_alloc_parent_info(bp);
5800         if (rc)
5801                 return rc;
5802
5803         rc = bnxt_alloc_hwrm_resources(bp);
5804         if (rc) {
5805                 PMD_DRV_LOG(ERR,
5806                             "Failed to allocate response buffer rc: %x\n", rc);
5807                 return rc;
5808         }
5809         rc = bnxt_alloc_leds_info(bp);
5810         if (rc)
5811                 return rc;
5812
5813         rc = bnxt_alloc_cos_queues(bp);
5814         if (rc)
5815                 return rc;
5816
5817         rc = bnxt_init_locks(bp);
5818         if (rc)
5819                 return rc;
5820
5821         rc = bnxt_alloc_switch_domain(bp);
5822         if (rc)
5823                 return rc;
5824
5825         return rc;
5826 }
5827
5828 static int
5829 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5830 {
5831         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5832         static int version_printed;
5833         struct bnxt *bp;
5834         int rc;
5835
5836         if (version_printed++ == 0)
5837                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5838
5839         eth_dev->dev_ops = &bnxt_dev_ops;
5840         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5841         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5842         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5843         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5844         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5845
5846         /*
5847          * For secondary processes, we don't initialise any further
5848          * as primary has already done this work.
5849          */
5850         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5851                 return 0;
5852
5853         rte_eth_copy_pci_info(eth_dev, pci_dev);
5854         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
5855
5856         bp = eth_dev->data->dev_private;
5857
5858         /* Parse dev arguments passed on when starting the DPDK application. */
5859         rc = bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5860         if (rc)
5861                 goto error_free;
5862
5863         rc = bnxt_drv_init(eth_dev);
5864         if (rc)
5865                 goto error_free;
5866
5867         rc = bnxt_init_resources(bp, false);
5868         if (rc)
5869                 goto error_free;
5870
5871         rc = bnxt_alloc_stats_mem(bp);
5872         if (rc)
5873                 goto error_free;
5874
5875         PMD_DRV_LOG(INFO,
5876                     "Found %s device at mem %" PRIX64 ", node addr %pM\n",
5877                     DRV_MODULE_NAME,
5878                     pci_dev->mem_resource[0].phys_addr,
5879                     pci_dev->mem_resource[0].addr);
5880
5881         return 0;
5882
5883 error_free:
5884         bnxt_dev_uninit(eth_dev);
5885         return rc;
5886 }
5887
5888
5889 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5890 {
5891         if (!ctx)
5892                 return;
5893
5894         if (ctx->va)
5895                 rte_free(ctx->va);
5896
5897         ctx->va = NULL;
5898         ctx->dma = RTE_BAD_IOVA;
5899         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5900 }
5901
5902 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5903 {
5904         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5905                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5906                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
5907                                   bp->flow_stat->max_fc,
5908                                   false);
5909
5910         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5911                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5912                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
5913                                   bp->flow_stat->max_fc,
5914                                   false);
5915
5916         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5917                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5918         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5919
5920         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5921                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5922         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5923
5924         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5925                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5926         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5927
5928         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5929                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5930         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5931 }
5932
5933 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5934 {
5935         bnxt_unregister_fc_ctx_mem(bp);
5936
5937         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5938         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5939         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5940         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5941 }
5942
5943 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5944 {
5945         if (BNXT_FLOW_XSTATS_EN(bp))
5946                 bnxt_uninit_fc_ctx_mem(bp);
5947 }
5948
5949 static void
5950 bnxt_free_error_recovery_info(struct bnxt *bp)
5951 {
5952         rte_free(bp->recovery_info);
5953         bp->recovery_info = NULL;
5954         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5955 }
5956
5957 static int
5958 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5959 {
5960         int rc;
5961
5962         bnxt_free_int(bp);
5963         bnxt_free_mem(bp, reconfig_dev);
5964
5965         bnxt_hwrm_func_buf_unrgtr(bp);
5966         if (bp->pf != NULL) {
5967                 rte_free(bp->pf->vf_req_buf);
5968                 bp->pf->vf_req_buf = NULL;
5969         }
5970
5971         rc = bnxt_hwrm_func_driver_unregister(bp);
5972         bp->flags &= ~BNXT_FLAG_REGISTERED;
5973         bnxt_free_ctx_mem(bp);
5974         if (!reconfig_dev) {
5975                 bnxt_free_hwrm_resources(bp);
5976                 bnxt_free_error_recovery_info(bp);
5977                 rte_free(bp->mcast_addr_list);
5978                 bp->mcast_addr_list = NULL;
5979                 rte_free(bp->rss_conf.rss_key);
5980                 bp->rss_conf.rss_key = NULL;
5981         }
5982
5983         bnxt_uninit_ctx_mem(bp);
5984
5985         bnxt_free_flow_stats_info(bp);
5986         if (bp->rep_info != NULL)
5987                 bnxt_free_switch_domain(bp);
5988         bnxt_free_rep_info(bp);
5989         rte_free(bp->ptp_cfg);
5990         bp->ptp_cfg = NULL;
5991         return rc;
5992 }
5993
5994 static int
5995 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5996 {
5997         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5998                 return -EPERM;
5999
6000         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
6001
6002         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
6003                 bnxt_dev_close_op(eth_dev);
6004
6005         return 0;
6006 }
6007
6008 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
6009 {
6010         struct bnxt *bp = eth_dev->data->dev_private;
6011         struct rte_eth_dev *vf_rep_eth_dev;
6012         int ret = 0, i;
6013
6014         if (!bp)
6015                 return -EINVAL;
6016
6017         for (i = 0; i < bp->num_reps; i++) {
6018                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
6019                 if (!vf_rep_eth_dev)
6020                         continue;
6021                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
6022                             vf_rep_eth_dev->data->port_id);
6023                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
6024         }
6025         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
6026                     eth_dev->data->port_id);
6027         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
6028
6029         return ret;
6030 }
6031
6032 static void bnxt_free_rep_info(struct bnxt *bp)
6033 {
6034         rte_free(bp->rep_info);
6035         bp->rep_info = NULL;
6036         rte_free(bp->cfa_code_map);
6037         bp->cfa_code_map = NULL;
6038 }
6039
6040 static int bnxt_init_rep_info(struct bnxt *bp)
6041 {
6042         int i = 0, rc;
6043
6044         if (bp->rep_info)
6045                 return 0;
6046
6047         bp->rep_info = rte_zmalloc("bnxt_rep_info",
6048                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS(bp),
6049                                    0);
6050         if (!bp->rep_info) {
6051                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
6052                 return -ENOMEM;
6053         }
6054         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
6055                                        sizeof(*bp->cfa_code_map) *
6056                                        BNXT_MAX_CFA_CODE, 0);
6057         if (!bp->cfa_code_map) {
6058                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
6059                 bnxt_free_rep_info(bp);
6060                 return -ENOMEM;
6061         }
6062
6063         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
6064                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
6065
6066         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
6067         if (rc) {
6068                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
6069                 bnxt_free_rep_info(bp);
6070                 return rc;
6071         }
6072
6073         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
6074         if (rc) {
6075                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
6076                 bnxt_free_rep_info(bp);
6077                 return rc;
6078         }
6079
6080         return rc;
6081 }
6082
6083 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
6084                                struct rte_eth_devargs *eth_da,
6085                                struct rte_eth_dev *backing_eth_dev,
6086                                const char *dev_args)
6087 {
6088         struct rte_eth_dev *vf_rep_eth_dev;
6089         char name[RTE_ETH_NAME_MAX_LEN];
6090         struct bnxt *backing_bp = backing_eth_dev->data->dev_private;
6091         uint16_t max_vf_reps = BNXT_MAX_VF_REPS(backing_bp);
6092
6093         uint16_t num_rep;
6094         int i, ret = 0;
6095         struct rte_kvargs *kvlist = NULL;
6096
6097         if (eth_da->type == RTE_ETH_REPRESENTOR_NONE)
6098                 return 0;
6099         if (eth_da->type != RTE_ETH_REPRESENTOR_VF) {
6100                 PMD_DRV_LOG(ERR, "unsupported representor type %d\n",
6101                             eth_da->type);
6102                 return -ENOTSUP;
6103         }
6104         num_rep = eth_da->nb_representor_ports;
6105         if (num_rep > max_vf_reps) {
6106                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
6107                             num_rep, max_vf_reps);
6108                 return -EINVAL;
6109         }
6110
6111         if (num_rep >= RTE_MAX_ETHPORTS) {
6112                 PMD_DRV_LOG(ERR,
6113                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6114                             num_rep, RTE_MAX_ETHPORTS);
6115                 return -EINVAL;
6116         }
6117
6118         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6119                 PMD_DRV_LOG(ERR,
6120                             "Not a PF or trusted VF. No Representor support\n");
6121                 /* Returning an error is not an option.
6122                  * Applications are not handling this correctly
6123                  */
6124                 return 0;
6125         }
6126
6127         if (bnxt_init_rep_info(backing_bp))
6128                 return 0;
6129
6130         for (i = 0; i < num_rep; i++) {
6131                 struct bnxt_representor representor = {
6132                         .vf_id = eth_da->representor_ports[i],
6133                         .switch_domain_id = backing_bp->switch_domain_id,
6134                         .parent_dev = backing_eth_dev
6135                 };
6136
6137                 if (representor.vf_id >= max_vf_reps) {
6138                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6139                                     representor.vf_id, max_vf_reps);
6140                         continue;
6141                 }
6142
6143                 /* representor port net_bdf_port */
6144                 snprintf(name, sizeof(name), "net_%s_representor_%d",
6145                          pci_dev->device.name, eth_da->representor_ports[i]);
6146
6147                 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
6148                 if (kvlist) {
6149                         /*
6150                          * Handler for "rep_is_pf" devarg.
6151                          * Invoked as for ex: "-a 000:00:0d.0,
6152                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6153                          */
6154                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
6155                                                  bnxt_parse_devarg_rep_is_pf,
6156                                                  (void *)&representor);
6157                         if (ret) {
6158                                 ret = -EINVAL;
6159                                 goto err;
6160                         }
6161                         /*
6162                          * Handler for "rep_based_pf" devarg.
6163                          * Invoked as for ex: "-a 000:00:0d.0,
6164                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6165                          */
6166                         ret = rte_kvargs_process(kvlist,
6167                                                  BNXT_DEVARG_REP_BASED_PF,
6168                                                  bnxt_parse_devarg_rep_based_pf,
6169                                                  (void *)&representor);
6170                         if (ret) {
6171                                 ret = -EINVAL;
6172                                 goto err;
6173                         }
6174                         /*
6175                          * Handler for "rep_based_pf" devarg.
6176                          * Invoked as for ex: "-a 000:00:0d.0,
6177                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6178                          */
6179                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
6180                                                  bnxt_parse_devarg_rep_q_r2f,
6181                                                  (void *)&representor);
6182                         if (ret) {
6183                                 ret = -EINVAL;
6184                                 goto err;
6185                         }
6186                         /*
6187                          * Handler for "rep_based_pf" devarg.
6188                          * Invoked as for ex: "-a 000:00:0d.0,
6189                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6190                          */
6191                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
6192                                                  bnxt_parse_devarg_rep_q_f2r,
6193                                                  (void *)&representor);
6194                         if (ret) {
6195                                 ret = -EINVAL;
6196                                 goto err;
6197                         }
6198                         /*
6199                          * Handler for "rep_based_pf" devarg.
6200                          * Invoked as for ex: "-a 000:00:0d.0,
6201                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6202                          */
6203                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
6204                                                  bnxt_parse_devarg_rep_fc_r2f,
6205                                                  (void *)&representor);
6206                         if (ret) {
6207                                 ret = -EINVAL;
6208                                 goto err;
6209                         }
6210                         /*
6211                          * Handler for "rep_based_pf" devarg.
6212                          * Invoked as for ex: "-a 000:00:0d.0,
6213                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6214                          */
6215                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
6216                                                  bnxt_parse_devarg_rep_fc_f2r,
6217                                                  (void *)&representor);
6218                         if (ret) {
6219                                 ret = -EINVAL;
6220                                 goto err;
6221                         }
6222                 }
6223
6224                 ret = rte_eth_dev_create(&pci_dev->device, name,
6225                                          sizeof(struct bnxt_representor),
6226                                          NULL, NULL,
6227                                          bnxt_representor_init,
6228                                          &representor);
6229                 if (ret) {
6230                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6231                                     "representor %s.", name);
6232                         goto err;
6233                 }
6234
6235                 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6236                 if (!vf_rep_eth_dev) {
6237                         PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6238                                     " for VF-Rep: %s.", name);
6239                         ret = -ENODEV;
6240                         goto err;
6241                 }
6242
6243                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6244                             backing_eth_dev->data->port_id);
6245                 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6246                                                          vf_rep_eth_dev;
6247                 backing_bp->num_reps++;
6248
6249         }
6250
6251         rte_kvargs_free(kvlist);
6252         return 0;
6253
6254 err:
6255         /* If num_rep > 1, then rollback already created
6256          * ports, since we'll be failing the probe anyway
6257          */
6258         if (num_rep > 1)
6259                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6260         rte_errno = -ret;
6261         rte_kvargs_free(kvlist);
6262
6263         return ret;
6264 }
6265
6266 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6267                           struct rte_pci_device *pci_dev)
6268 {
6269         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6270         struct rte_eth_dev *backing_eth_dev;
6271         uint16_t num_rep;
6272         int ret = 0;
6273
6274         if (pci_dev->device.devargs) {
6275                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6276                                             &eth_da);
6277                 if (ret)
6278                         return ret;
6279         }
6280
6281         num_rep = eth_da.nb_representor_ports;
6282         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6283                     num_rep);
6284
6285         /* We could come here after first level of probe is already invoked
6286          * as part of an application bringup(OVS-DPDK vswitchd), so first check
6287          * for already allocated eth_dev for the backing device (PF/Trusted VF)
6288          */
6289         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6290         if (backing_eth_dev == NULL) {
6291                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6292                                          sizeof(struct bnxt),
6293                                          eth_dev_pci_specific_init, pci_dev,
6294                                          bnxt_dev_init, NULL);
6295
6296                 if (ret || !num_rep)
6297                         return ret;
6298
6299                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6300         }
6301         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6302                     backing_eth_dev->data->port_id);
6303
6304         if (!num_rep)
6305                 return ret;
6306
6307         /* probe representor ports now */
6308         ret = bnxt_rep_port_probe(pci_dev, &eth_da, backing_eth_dev,
6309                                   pci_dev->device.devargs->args);
6310
6311         return ret;
6312 }
6313
6314 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6315 {
6316         struct rte_eth_dev *eth_dev;
6317
6318         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6319         if (!eth_dev)
6320                 return 0; /* Invoked typically only by OVS-DPDK, by the
6321                            * time it comes here the eth_dev is already
6322                            * deleted by rte_eth_dev_close(), so returning
6323                            * +ve value will at least help in proper cleanup
6324                            */
6325
6326         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6327         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6328                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6329                         return rte_eth_dev_destroy(eth_dev,
6330                                                    bnxt_representor_uninit);
6331                 else
6332                         return rte_eth_dev_destroy(eth_dev,
6333                                                    bnxt_dev_uninit);
6334         } else {
6335                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6336         }
6337 }
6338
6339 static struct rte_pci_driver bnxt_rte_pmd = {
6340         .id_table = bnxt_pci_id_map,
6341         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6342                         RTE_PCI_DRV_INTR_RMV |
6343                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6344                                                   * and OVS-DPDK
6345                                                   */
6346         .probe = bnxt_pci_probe,
6347         .remove = bnxt_pci_remove,
6348 };
6349
6350 static bool
6351 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6352 {
6353         if (strcmp(dev->device->driver->name, drv->driver.name))
6354                 return false;
6355
6356         return true;
6357 }
6358
6359 bool is_bnxt_supported(struct rte_eth_dev *dev)
6360 {
6361         return is_device_supported(dev, &bnxt_rte_pmd);
6362 }
6363
6364 RTE_LOG_REGISTER_SUFFIX(bnxt_logtype_driver, driver, NOTICE);
6365 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6366 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6367