drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <ethdev_driver.h>
  11 #include <ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16 #include <rte_vect.h>
  17
  18 #include "bnxt.h"
  19 #include "bnxt_filter.h"
  20 #include "bnxt_hwrm.h"
  21 #include "bnxt_irq.h"
  22 #include "bnxt_reps.h"
  23 #include "bnxt_ring.h"
  24 #include "bnxt_rxq.h"
  25 #include "bnxt_rxr.h"
  26 #include "bnxt_stats.h"
  27 #include "bnxt_txq.h"
  28 #include "bnxt_txr.h"
  29 #include "bnxt_vnic.h"
  30 #include "hsi_struct_def_dpdk.h"
  31 #include "bnxt_nvm_defs.h"
  32 #include "bnxt_tf_common.h"
  33 #include "ulp_flow_db.h"
  34 #include "rte_pmd_bnxt.h"
  35
  36 #define DRV_MODULE_NAME         "bnxt"
  37 static const char bnxt_version[] =
  38         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  39
  40 /*
  41  * The set of PCI devices this driver supports
  42  */
  43 static const struct rte_pci_id bnxt_pci_id_map[] = {
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  47                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
  87         { .vendor_id = 0, /* sentinel */ },
  88 };
  89
  90 #define BNXT_DEVARG_ACCUM_STATS "accum-stats"
  91 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
  92 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
  93 #define BNXT_DEVARG_REPRESENTOR "representor"
  94 #define BNXT_DEVARG_REP_BASED_PF  "rep-based-pf"
  95 #define BNXT_DEVARG_REP_IS_PF  "rep-is-pf"
  96 #define BNXT_DEVARG_REP_Q_R2F  "rep-q-r2f"
  97 #define BNXT_DEVARG_REP_Q_F2R  "rep-q-f2r"
  98 #define BNXT_DEVARG_REP_FC_R2F  "rep-fc-r2f"
  99 #define BNXT_DEVARG_REP_FC_F2R  "rep-fc-f2r"
 100 #define BNXT_DEVARG_APP_ID      "app-id"
 101
 102 static const char *const bnxt_dev_args[] = {
 103         BNXT_DEVARG_REPRESENTOR,
 104         BNXT_DEVARG_ACCUM_STATS,
 105         BNXT_DEVARG_FLOW_XSTAT,
 106         BNXT_DEVARG_MAX_NUM_KFLOWS,
 107         BNXT_DEVARG_REP_BASED_PF,
 108         BNXT_DEVARG_REP_IS_PF,
 109         BNXT_DEVARG_REP_Q_R2F,
 110         BNXT_DEVARG_REP_Q_F2R,
 111         BNXT_DEVARG_REP_FC_R2F,
 112         BNXT_DEVARG_REP_FC_F2R,
 113         BNXT_DEVARG_APP_ID,
 114         NULL
 115 };
 116
 117 /*
 118  * accum-stats == false to disable flow counter accumulation
 119  * accum-stats == true to enable flow counter accumulation
 120  */
 121 #define BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats)    ((accum_stats) > 1)
 122
 123 /*
 124  * app-id = an non-negative 8-bit number
 125  */
 126 #define BNXT_DEVARG_APP_ID_INVALID(val)                 ((val) > 255)
 127
 128 /*
 129  * flow_xstat == false to disable the feature
 130  * flow_xstat == true to enable the feature
 131  */
 132 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 133
 134 /*
 135  * rep_is_pf == false to indicate VF representor
 136  * rep_is_pf == true to indicate PF representor
 137  */
 138 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)        ((rep_is_pf) > 1)
 139
 140 /*
 141  * rep_based_pf == Physical index of the PF
 142  */
 143 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)  ((rep_based_pf) > 15)
 144 /*
 145  * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
 146  */
 147 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)        ((rep_q_r2f) > 3)
 148
 149 /*
 150  * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
 151  */
 152 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)        ((rep_q_f2r) > 3)
 153
 154 /*
 155  * rep_fc_r2f == Flow control for the representor to endpoint direction
 156  */
 157 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)      ((rep_fc_r2f) > 1)
 158
 159 /*
 160  * rep_fc_f2r == Flow control for the endpoint to representor direction
 161  */
 162 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)      ((rep_fc_f2r) > 1)
 163
 164 int bnxt_cfa_code_dynfield_offset = -1;
 165
 166 /*
 167  * max_num_kflows must be >= 32
 168  * and must be a power-of-2 supported value
 169  * return: 1 -> invalid
 170  *         0 -> valid
 171  */
 172 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 173 {
 174         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 175                 return 1;
 176         return 0;
 177 }
 178
 179 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 180 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 181 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 182 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 183 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 184 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 185 static void bnxt_dev_recover(void *arg);
 186 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 187 static void bnxt_free_rep_info(struct bnxt *bp);
 188
 189 int is_bnxt_in_error(struct bnxt *bp)
 190 {
 191         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 192                 return -EIO;
 193         if (bp->flags & BNXT_FLAG_FW_RESET)
 194                 return -EBUSY;
 195
 196         return 0;
 197 }
 198
 199 /***********************/
 200
 201 /*
 202  * High level utility functions
 203  */
 204
 205 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 206 {
 207         unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
 208                                              BNXT_RSS_TBL_SIZE_P5);
 209
 210         if (!BNXT_CHIP_P5(bp))
 211                 return 1;
 212
 213         return RTE_ALIGN_MUL_CEIL(num_rss_rings,
 214                                   BNXT_RSS_ENTRIES_PER_CTX_P5) /
 215                                   BNXT_RSS_ENTRIES_PER_CTX_P5;
 216 }
 217
 218 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 219 {
 220         if (!BNXT_CHIP_P5(bp))
 221                 return HW_HASH_INDEX_SIZE;
 222
 223         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
 224 }
 225
 226 static void bnxt_free_parent_info(struct bnxt *bp)
 227 {
 228         rte_free(bp->parent);
 229         bp->parent = NULL;
 230 }
 231
 232 static void bnxt_free_pf_info(struct bnxt *bp)
 233 {
 234         rte_free(bp->pf);
 235         bp->pf = NULL;
 236 }
 237
 238 static void bnxt_free_link_info(struct bnxt *bp)
 239 {
 240         rte_free(bp->link_info);
 241         bp->link_info = NULL;
 242 }
 243
 244 static void bnxt_free_leds_info(struct bnxt *bp)
 245 {
 246         if (BNXT_VF(bp))
 247                 return;
 248
 249         rte_free(bp->leds);
 250         bp->leds = NULL;
 251 }
 252
 253 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 254 {
 255         rte_free(bp->flow_stat);
 256         bp->flow_stat = NULL;
 257 }
 258
 259 static void bnxt_free_cos_queues(struct bnxt *bp)
 260 {
 261         rte_free(bp->rx_cos_queue);
 262         bp->rx_cos_queue = NULL;
 263         rte_free(bp->tx_cos_queue);
 264         bp->tx_cos_queue = NULL;
 265 }
 266
 267 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 268 {
 269         bnxt_free_filter_mem(bp);
 270         bnxt_free_vnic_attributes(bp);
 271         bnxt_free_vnic_mem(bp);
 272
 273         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 274          * If the number of rings change across fw update,
 275          * we don't have much choice except to warn the user.
 276          */
 277         if (!reconfig) {
 278                 bnxt_free_stats(bp);
 279                 bnxt_free_tx_rings(bp);
 280                 bnxt_free_rx_rings(bp);
 281         }
 282         bnxt_free_async_cp_ring(bp);
 283         bnxt_free_rxtx_nq_ring(bp);
 284
 285         rte_free(bp->grp_info);
 286         bp->grp_info = NULL;
 287 }
 288
 289 static int bnxt_alloc_parent_info(struct bnxt *bp)
 290 {
 291         bp->parent = rte_zmalloc("bnxt_parent_info",
 292                                  sizeof(struct bnxt_parent_info), 0);
 293         if (bp->parent == NULL)
 294                 return -ENOMEM;
 295
 296         return 0;
 297 }
 298
 299 static int bnxt_alloc_pf_info(struct bnxt *bp)
 300 {
 301         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 302         if (bp->pf == NULL)
 303                 return -ENOMEM;
 304
 305         return 0;
 306 }
 307
 308 static int bnxt_alloc_link_info(struct bnxt *bp)
 309 {
 310         bp->link_info =
 311                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 312         if (bp->link_info == NULL)
 313                 return -ENOMEM;
 314
 315         return 0;
 316 }
 317
 318 static int bnxt_alloc_leds_info(struct bnxt *bp)
 319 {
 320         if (BNXT_VF(bp))
 321                 return 0;
 322
 323         bp->leds = rte_zmalloc("bnxt_leds",
 324                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 325                                0);
 326         if (bp->leds == NULL)
 327                 return -ENOMEM;
 328
 329         return 0;
 330 }
 331
 332 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 333 {
 334         bp->rx_cos_queue =
 335                 rte_zmalloc("bnxt_rx_cosq",
 336                             BNXT_COS_QUEUE_COUNT *
 337                             sizeof(struct bnxt_cos_queue_info),
 338                             0);
 339         if (bp->rx_cos_queue == NULL)
 340                 return -ENOMEM;
 341
 342         bp->tx_cos_queue =
 343                 rte_zmalloc("bnxt_tx_cosq",
 344                             BNXT_COS_QUEUE_COUNT *
 345                             sizeof(struct bnxt_cos_queue_info),
 346                             0);
 347         if (bp->tx_cos_queue == NULL)
 348                 return -ENOMEM;
 349
 350         return 0;
 351 }
 352
 353 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 354 {
 355         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 356                                     sizeof(struct bnxt_flow_stat_info), 0);
 357         if (bp->flow_stat == NULL)
 358                 return -ENOMEM;
 359
 360         return 0;
 361 }
 362
 363 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 364 {
 365         int rc;
 366
 367         rc = bnxt_alloc_ring_grps(bp);
 368         if (rc)
 369                 goto alloc_mem_err;
 370
 371         rc = bnxt_alloc_async_ring_struct(bp);
 372         if (rc)
 373                 goto alloc_mem_err;
 374
 375         rc = bnxt_alloc_vnic_mem(bp);
 376         if (rc)
 377                 goto alloc_mem_err;
 378
 379         rc = bnxt_alloc_vnic_attributes(bp);
 380         if (rc)
 381                 goto alloc_mem_err;
 382
 383         rc = bnxt_alloc_filter_mem(bp);
 384         if (rc)
 385                 goto alloc_mem_err;
 386
 387         rc = bnxt_alloc_async_cp_ring(bp);
 388         if (rc)
 389                 goto alloc_mem_err;
 390
 391         rc = bnxt_alloc_rxtx_nq_ring(bp);
 392         if (rc)
 393                 goto alloc_mem_err;
 394
 395         if (BNXT_FLOW_XSTATS_EN(bp)) {
 396                 rc = bnxt_alloc_flow_stats_info(bp);
 397                 if (rc)
 398                         goto alloc_mem_err;
 399         }
 400
 401         return 0;
 402
 403 alloc_mem_err:
 404         bnxt_free_mem(bp, reconfig);
 405         return rc;
 406 }
 407
 408 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 409 {
 410         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 411         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 412         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 413         struct bnxt_rx_queue *rxq;
 414         unsigned int j;
 415         int rc;
 416
 417         rc = bnxt_vnic_grp_alloc(bp, vnic);
 418         if (rc)
 419                 goto err_out;
 420
 421         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 422                     vnic_id, vnic, vnic->fw_grp_ids);
 423
 424         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 425         if (rc)
 426                 goto err_out;
 427
 428         /* Alloc RSS context only if RSS mode is enabled */
 429         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 430                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 431
 432                 /* RSS table size in Thor is 512.
 433                  * Cap max Rx rings to same value
 434                  */
 435                 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
 436                         PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
 437                                     bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
 438                         goto err_out;
 439                 }
 440
 441                 rc = 0;
 442                 for (j = 0; j < nr_ctxs; j++) {
 443                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 444                         if (rc)
 445                                 break;
 446                 }
 447                 if (rc) {
 448                         PMD_DRV_LOG(ERR,
 449                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 450                                     vnic_id, j, rc);
 451                         goto err_out;
 452                 }
 453                 vnic->num_lb_ctxts = nr_ctxs;
 454         }
 455
 456         /*
 457          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 458          * setting is not available at this time, it will not be
 459          * configured correctly in the CFA.
 460          */
 461         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 462                 vnic->vlan_strip = true;
 463         else
 464                 vnic->vlan_strip = false;
 465
 466         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 467         if (rc)
 468                 goto err_out;
 469
 470         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 471         if (rc)
 472                 goto err_out;
 473
 474         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 475                 rxq = bp->eth_dev->data->rx_queues[j];
 476
 477                 PMD_DRV_LOG(DEBUG,
 478                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 479                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 480
 481                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 482                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 483                 else
 484                         vnic->rx_queue_cnt++;
 485         }
 486
 487         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 488
 489         rc = bnxt_vnic_rss_configure(bp, vnic);
 490         if (rc)
 491                 goto err_out;
 492
 493         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 494
 495         rc = bnxt_hwrm_vnic_tpa_cfg(bp, vnic,
 496                                     (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) ?
 497                                     true : false);
 498         if (rc)
 499                 goto err_out;
 500
 501         return 0;
 502 err_out:
 503         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 504                     vnic_id, rc);
 505         return rc;
 506 }
 507
 508 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 509 {
 510         int rc = 0;
 511
 512         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 513                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 514         if (rc)
 515                 return rc;
 516
 517         PMD_DRV_LOG(DEBUG,
 518                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 519                     " rx_fc_in_tbl.ctx_id = %d\n",
 520                     bp->flow_stat->rx_fc_in_tbl.va,
 521                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 522                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 523
 524         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 525                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 526         if (rc)
 527                 return rc;
 528
 529         PMD_DRV_LOG(DEBUG,
 530                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 531                     " rx_fc_out_tbl.ctx_id = %d\n",
 532                     bp->flow_stat->rx_fc_out_tbl.va,
 533                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 534                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 535
 536         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 537                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 538         if (rc)
 539                 return rc;
 540
 541         PMD_DRV_LOG(DEBUG,
 542                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 543                     " tx_fc_in_tbl.ctx_id = %d\n",
 544                     bp->flow_stat->tx_fc_in_tbl.va,
 545                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 546                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 547
 548         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 549                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 550         if (rc)
 551                 return rc;
 552
 553         PMD_DRV_LOG(DEBUG,
 554                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 555                     " tx_fc_out_tbl.ctx_id = %d\n",
 556                     bp->flow_stat->tx_fc_out_tbl.va,
 557                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 558                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 559
 560         memset(bp->flow_stat->rx_fc_out_tbl.va,
 561                0,
 562                bp->flow_stat->rx_fc_out_tbl.size);
 563         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 564                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 565                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 566                                        bp->flow_stat->max_fc,
 567                                        true);
 568         if (rc)
 569                 return rc;
 570
 571         memset(bp->flow_stat->tx_fc_out_tbl.va,
 572                0,
 573                bp->flow_stat->tx_fc_out_tbl.size);
 574         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 575                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 576                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 577                                        bp->flow_stat->max_fc,
 578                                        true);
 579
 580         return rc;
 581 }
 582
 583 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 584                                   struct bnxt_ctx_mem_buf_info *ctx)
 585 {
 586         if (!ctx)
 587                 return -EINVAL;
 588
 589         ctx->va = rte_zmalloc(type, size, 0);
 590         if (ctx->va == NULL)
 591                 return -ENOMEM;
 592         rte_mem_lock_page(ctx->va);
 593         ctx->size = size;
 594         ctx->dma = rte_mem_virt2iova(ctx->va);
 595         if (ctx->dma == RTE_BAD_IOVA)
 596                 return -ENOMEM;
 597
 598         return 0;
 599 }
 600
 601 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 602 {
 603         struct rte_pci_device *pdev = bp->pdev;
 604         char type[RTE_MEMZONE_NAMESIZE];
 605         uint16_t max_fc;
 606         int rc = 0;
 607
 608         max_fc = bp->flow_stat->max_fc;
 609
 610         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 611                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 612         /* 4 bytes for each counter-id */
 613         rc = bnxt_alloc_ctx_mem_buf(type,
 614                                     max_fc * 4,
 615                                     &bp->flow_stat->rx_fc_in_tbl);
 616         if (rc)
 617                 return rc;
 618
 619         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 620                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 621         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 622         rc = bnxt_alloc_ctx_mem_buf(type,
 623                                     max_fc * 16,
 624                                     &bp->flow_stat->rx_fc_out_tbl);
 625         if (rc)
 626                 return rc;
 627
 628         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 629                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 630         /* 4 bytes for each counter-id */
 631         rc = bnxt_alloc_ctx_mem_buf(type,
 632                                     max_fc * 4,
 633                                     &bp->flow_stat->tx_fc_in_tbl);
 634         if (rc)
 635                 return rc;
 636
 637         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 638                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 639         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 640         rc = bnxt_alloc_ctx_mem_buf(type,
 641                                     max_fc * 16,
 642                                     &bp->flow_stat->tx_fc_out_tbl);
 643         if (rc)
 644                 return rc;
 645
 646         rc = bnxt_register_fc_ctx_mem(bp);
 647
 648         return rc;
 649 }
 650
 651 static int bnxt_init_ctx_mem(struct bnxt *bp)
 652 {
 653         int rc = 0;
 654
 655         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 656             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 657             !BNXT_FLOW_XSTATS_EN(bp))
 658                 return 0;
 659
 660         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 661         if (rc)
 662                 return rc;
 663
 664         rc = bnxt_init_fc_ctx_mem(bp);
 665
 666         return rc;
 667 }
 668
 669 static int bnxt_update_phy_setting(struct bnxt *bp)
 670 {
 671         struct rte_eth_link new;
 672         int rc;
 673
 674         rc = bnxt_get_hwrm_link_config(bp, &new);
 675         if (rc) {
 676                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 677                 return rc;
 678         }
 679
 680         /*
 681          * On BCM957508-N2100 adapters, FW will not allow any user other
 682          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 683          * always returns link up. Force phy update always in that case.
 684          */
 685         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 686                 rc = bnxt_set_hwrm_link_config(bp, true);
 687                 if (rc) {
 688                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 689                         return rc;
 690                 }
 691         }
 692
 693         return rc;
 694 }
 695
 696 static void bnxt_free_prev_ring_stats(struct bnxt *bp)
 697 {
 698         rte_free(bp->prev_rx_ring_stats);
 699         rte_free(bp->prev_tx_ring_stats);
 700
 701         bp->prev_rx_ring_stats = NULL;
 702         bp->prev_tx_ring_stats = NULL;
 703 }
 704
 705 static int bnxt_alloc_prev_ring_stats(struct bnxt *bp)
 706 {
 707         bp->prev_rx_ring_stats =  rte_zmalloc("bnxt_prev_rx_ring_stats",
 708                                               sizeof(struct bnxt_ring_stats) *
 709                                               bp->rx_cp_nr_rings,
 710                                               0);
 711         if (bp->prev_rx_ring_stats == NULL)
 712                 return -ENOMEM;
 713
 714         bp->prev_tx_ring_stats = rte_zmalloc("bnxt_prev_tx_ring_stats",
 715                                              sizeof(struct bnxt_ring_stats) *
 716                                              bp->tx_cp_nr_rings,
 717                                              0);
 718         if (bp->prev_tx_ring_stats == NULL)
 719                 goto error;
 720
 721         return 0;
 722
 723 error:
 724         bnxt_free_prev_ring_stats(bp);
 725         return -ENOMEM;
 726 }
 727
 728 static int bnxt_start_nic(struct bnxt *bp)
 729 {
 730         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 731         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 732         uint32_t intr_vector = 0;
 733         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 734         uint32_t vec = BNXT_MISC_VEC_ID;
 735         unsigned int i, j;
 736         int rc;
 737
 738         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 739                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 740                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 741                 bp->flags |= BNXT_FLAG_JUMBO;
 742         } else {
 743                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 744                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 745                 bp->flags &= ~BNXT_FLAG_JUMBO;
 746         }
 747
 748         /* THOR does not support ring groups.
 749          * But we will use the array to save RSS context IDs.
 750          */
 751         if (BNXT_CHIP_P5(bp))
 752                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
 753
 754         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 755         if (rc) {
 756                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 757                 goto err_out;
 758         }
 759
 760         rc = bnxt_alloc_hwrm_rings(bp);
 761         if (rc) {
 762                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 763                 goto err_out;
 764         }
 765
 766         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 767         if (rc) {
 768                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 769                 goto err_out;
 770         }
 771
 772         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 773                 goto skip_cosq_cfg;
 774
 775         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 776                 if (bp->rx_cos_queue[i].id != 0xff) {
 777                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 778
 779                         if (!vnic) {
 780                                 PMD_DRV_LOG(ERR,
 781                                             "Num pools more than FW profile\n");
 782                                 rc = -EINVAL;
 783                                 goto err_out;
 784                         }
 785                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 786                         bp->rx_cosq_cnt++;
 787                 }
 788         }
 789
 790 skip_cosq_cfg:
 791         rc = bnxt_mq_rx_configure(bp);
 792         if (rc) {
 793                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 794                 goto err_out;
 795         }
 796
 797         /* default vnic 0 */
 798         rc = bnxt_setup_one_vnic(bp, 0);
 799         if (rc)
 800                 goto err_out;
 801         /* VNIC configuration */
 802         if (BNXT_RFS_NEEDS_VNIC(bp)) {
 803                 for (i = 1; i < bp->nr_vnics; i++) {
 804                         rc = bnxt_setup_one_vnic(bp, i);
 805                         if (rc)
 806                                 goto err_out;
 807                 }
 808         }
 809
 810         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 811         if (rc) {
 812                 PMD_DRV_LOG(ERR,
 813                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 814                 goto err_out;
 815         }
 816
 817         /* check and configure queue intr-vector mapping */
 818         if ((rte_intr_cap_multiple(intr_handle) ||
 819              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 820             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 821                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 822                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 823                 if (intr_vector > bp->rx_cp_nr_rings) {
 824                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 825                                         bp->rx_cp_nr_rings);
 826                         return -ENOTSUP;
 827                 }
 828                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 829                 if (rc)
 830                         return rc;
 831         }
 832
 833         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 834                 intr_handle->intr_vec =
 835                         rte_zmalloc("intr_vec",
 836                                     bp->eth_dev->data->nb_rx_queues *
 837                                     sizeof(int), 0);
 838                 if (intr_handle->intr_vec == NULL) {
 839                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 840                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 841                         rc = -ENOMEM;
 842                         goto err_out;
 843                 }
 844                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 845                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 846                          intr_handle->intr_vec, intr_handle->nb_efd,
 847                         intr_handle->max_intr);
 848                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 849                      queue_id++) {
 850                         intr_handle->intr_vec[queue_id] =
 851                                                         vec + BNXT_RX_VEC_START;
 852                         if (vec < base + intr_handle->nb_efd - 1)
 853                                 vec++;
 854                 }
 855         }
 856
 857         /* enable uio/vfio intr/eventfd mapping */
 858         rc = rte_intr_enable(intr_handle);
 859 #ifndef RTE_EXEC_ENV_FREEBSD
 860         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 861         if (rc)
 862                 goto err_out;
 863 #endif
 864
 865         rc = bnxt_update_phy_setting(bp);
 866         if (rc)
 867                 goto err_out;
 868
 869         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 870         if (!bp->mark_table)
 871                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 872
 873         return 0;
 874
 875 err_out:
 876         /* Some of the error status returned by FW may not be from errno.h */
 877         if (rc > 0)
 878                 rc = -EIO;
 879
 880         return rc;
 881 }
 882
 883 static int bnxt_shutdown_nic(struct bnxt *bp)
 884 {
 885         bnxt_free_all_hwrm_resources(bp);
 886         bnxt_free_all_filters(bp);
 887         bnxt_free_all_vnics(bp);
 888         return 0;
 889 }
 890
 891 /*
 892  * Device configuration and status function
 893  */
 894
 895 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 896 {
 897         uint32_t link_speed = 0;
 898         uint32_t speed_capa = 0;
 899
 900         if (bp->link_info == NULL)
 901                 return 0;
 902
 903         link_speed = bp->link_info->support_speeds;
 904
 905         /* If PAM4 is configured, use PAM4 supported speed */
 906         if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
 907                 link_speed = bp->link_info->support_pam4_speeds;
 908
 909         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 910                 speed_capa |= ETH_LINK_SPEED_100M;
 911         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 912                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 913         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 914                 speed_capa |= ETH_LINK_SPEED_1G;
 915         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 916                 speed_capa |= ETH_LINK_SPEED_2_5G;
 917         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 918                 speed_capa |= ETH_LINK_SPEED_10G;
 919         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 920                 speed_capa |= ETH_LINK_SPEED_20G;
 921         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 922                 speed_capa |= ETH_LINK_SPEED_25G;
 923         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 924                 speed_capa |= ETH_LINK_SPEED_40G;
 925         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 926                 speed_capa |= ETH_LINK_SPEED_50G;
 927         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 928                 speed_capa |= ETH_LINK_SPEED_100G;
 929         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
 930                 speed_capa |= ETH_LINK_SPEED_50G;
 931         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
 932                 speed_capa |= ETH_LINK_SPEED_100G;
 933         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
 934                 speed_capa |= ETH_LINK_SPEED_200G;
 935
 936         if (bp->link_info->auto_mode ==
 937             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 938                 speed_capa |= ETH_LINK_SPEED_FIXED;
 939
 940         return speed_capa;
 941 }
 942
 943 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 944                                 struct rte_eth_dev_info *dev_info)
 945 {
 946         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 947         struct bnxt *bp = eth_dev->data->dev_private;
 948         uint16_t max_vnics, i, j, vpool, vrxq;
 949         unsigned int max_rx_rings;
 950         int rc;
 951
 952         rc = is_bnxt_in_error(bp);
 953         if (rc)
 954                 return rc;
 955
 956         /* MAC Specifics */
 957         dev_info->max_mac_addrs = bp->max_l2_ctx;
 958         dev_info->max_hash_mac_addrs = 0;
 959
 960         /* PF/VF specifics */
 961         if (BNXT_PF(bp))
 962                 dev_info->max_vfs = pdev->max_vfs;
 963
 964         max_rx_rings = bnxt_max_rings(bp);
 965         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 966         dev_info->max_rx_queues = max_rx_rings;
 967         dev_info->max_tx_queues = max_rx_rings;
 968         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 969         dev_info->hash_key_size = HW_HASH_KEY_SIZE;
 970         max_vnics = bp->max_vnics;
 971
 972         /* MTU specifics */
 973         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 974         dev_info->max_mtu = BNXT_MAX_MTU;
 975
 976         /* Fast path specifics */
 977         dev_info->min_rx_bufsize = 1;
 978         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 979
 980         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 981         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 982                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 983         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 984         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
 985                                     dev_info->tx_queue_offload_capa;
 986         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 987
 988         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 989
 990         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 991                 .rx_thresh = {
 992                         .pthresh = 8,
 993                         .hthresh = 8,
 994                         .wthresh = 0,
 995                 },
 996                 .rx_free_thresh = 32,
 997                 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
 998         };
 999
1000         dev_info->default_txconf = (struct rte_eth_txconf) {
1001                 .tx_thresh = {
1002                         .pthresh = 32,
1003                         .hthresh = 0,
1004                         .wthresh = 0,
1005                 },
1006                 .tx_free_thresh = 32,
1007                 .tx_rs_thresh = 32,
1008         };
1009         eth_dev->data->dev_conf.intr_conf.lsc = 1;
1010
1011         eth_dev->data->dev_conf.intr_conf.rxq = 1;
1012         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
1013         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
1014         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
1015         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
1016
1017         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
1018                 dev_info->switch_info.name = eth_dev->device->name;
1019                 dev_info->switch_info.domain_id = bp->switch_domain_id;
1020                 dev_info->switch_info.port_id =
1021                                 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
1022                                     BNXT_SWITCH_PORT_ID_TRUSTED_VF;
1023         }
1024
1025         /*
1026          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
1027          *       need further investigation.
1028          */
1029
1030         /* VMDq resources */
1031         vpool = 64; /* ETH_64_POOLS */
1032         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
1033         for (i = 0; i < 4; vpool >>= 1, i++) {
1034                 if (max_vnics > vpool) {
1035                         for (j = 0; j < 5; vrxq >>= 1, j++) {
1036                                 if (dev_info->max_rx_queues > vrxq) {
1037                                         if (vpool > vrxq)
1038                                                 vpool = vrxq;
1039                                         goto found;
1040                                 }
1041                         }
1042                         /* Not enough resources to support VMDq */
1043                         break;
1044                 }
1045         }
1046         /* Not enough resources to support VMDq */
1047         vpool = 0;
1048         vrxq = 0;
1049 found:
1050         dev_info->max_vmdq_pools = vpool;
1051         dev_info->vmdq_queue_num = vrxq;
1052
1053         dev_info->vmdq_pool_base = 0;
1054         dev_info->vmdq_queue_base = 0;
1055
1056         return 0;
1057 }
1058
1059 /* Configure the device based on the configuration provided */
1060 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1061 {
1062         struct bnxt *bp = eth_dev->data->dev_private;
1063         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1064         int rc;
1065
1066         bp->rx_queues = (void *)eth_dev->data->rx_queues;
1067         bp->tx_queues = (void *)eth_dev->data->tx_queues;
1068         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1069         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1070
1071         rc = is_bnxt_in_error(bp);
1072         if (rc)
1073                 return rc;
1074
1075         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1076                 rc = bnxt_hwrm_check_vf_rings(bp);
1077                 if (rc) {
1078                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1079                         return -ENOSPC;
1080                 }
1081
1082                 /* If a resource has already been allocated - in this case
1083                  * it is the async completion ring, free it. Reallocate it after
1084                  * resource reservation. This will ensure the resource counts
1085                  * are calculated correctly.
1086                  */
1087
1088                 pthread_mutex_lock(&bp->def_cp_lock);
1089
1090                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1091                         bnxt_disable_int(bp);
1092                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
1093                 }
1094
1095                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1096                 if (rc) {
1097                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1098                         pthread_mutex_unlock(&bp->def_cp_lock);
1099                         return -ENOSPC;
1100                 }
1101
1102                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1103                         rc = bnxt_alloc_async_cp_ring(bp);
1104                         if (rc) {
1105                                 pthread_mutex_unlock(&bp->def_cp_lock);
1106                                 return rc;
1107                         }
1108                         bnxt_enable_int(bp);
1109                 }
1110
1111                 pthread_mutex_unlock(&bp->def_cp_lock);
1112         }
1113
1114         /* Inherit new configurations */
1115         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1116             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1117             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1118                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1119             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1120             bp->max_stat_ctx)
1121                 goto resource_error;
1122
1123         if (BNXT_HAS_RING_GRPS(bp) &&
1124             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1125                 goto resource_error;
1126
1127         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1128             bp->max_vnics < eth_dev->data->nb_rx_queues)
1129                 goto resource_error;
1130
1131         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1132         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1133
1134         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1135                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1136         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1137
1138         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1139                 eth_dev->data->mtu =
1140                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1141                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1142                         BNXT_NUM_VLANS;
1143                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1144         }
1145         return 0;
1146
1147 resource_error:
1148         PMD_DRV_LOG(ERR,
1149                     "Insufficient resources to support requested config\n");
1150         PMD_DRV_LOG(ERR,
1151                     "Num Queues Requested: Tx %d, Rx %d\n",
1152                     eth_dev->data->nb_tx_queues,
1153                     eth_dev->data->nb_rx_queues);
1154         PMD_DRV_LOG(ERR,
1155                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1156                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1157                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1158         return -ENOSPC;
1159 }
1160
1161 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1162 {
1163         struct rte_eth_link *link = &eth_dev->data->dev_link;
1164
1165         if (link->link_status)
1166                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1167                         eth_dev->data->port_id,
1168                         (uint32_t)link->link_speed,
1169                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1170                         ("full-duplex") : ("half-duplex\n"));
1171         else
1172                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1173                         eth_dev->data->port_id);
1174 }
1175
1176 /*
1177  * Determine whether the current configuration requires support for scattered
1178  * receive; return 1 if scattered receive is required and 0 if not.
1179  */
1180 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1181 {
1182         uint16_t buf_size;
1183         int i;
1184
1185         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1186                 return 1;
1187
1188         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO)
1189                 return 1;
1190
1191         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1192                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1193
1194                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1195                                       RTE_PKTMBUF_HEADROOM);
1196                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1197                         return 1;
1198         }
1199         return 0;
1200 }
1201
1202 static eth_rx_burst_t
1203 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1204 {
1205         struct bnxt *bp = eth_dev->data->dev_private;
1206
1207         /* Disable vector mode RX for Stingray2 for now */
1208         if (BNXT_CHIP_SR2(bp)) {
1209                 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1210                 return bnxt_recv_pkts;
1211         }
1212
1213 #if (defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)) && \
1214         !defined(RTE_LIBRTE_IEEE1588)
1215
1216         /* Vector mode receive cannot be enabled if scattered rx is in use. */
1217         if (eth_dev->data->scattered_rx)
1218                 goto use_scalar_rx;
1219
1220         /*
1221          * Vector mode receive cannot be enabled if Truflow is enabled or if
1222          * asynchronous completions and receive completions can be placed in
1223          * the same completion ring.
1224          */
1225         if (BNXT_TRUFLOW_EN(bp) || !BNXT_NUM_ASYNC_CPR(bp))
1226                 goto use_scalar_rx;
1227
1228         /*
1229          * Vector mode receive cannot be enabled if any receive offloads outside
1230          * a limited subset have been enabled.
1231          */
1232         if (eth_dev->data->dev_conf.rxmode.offloads &
1233                 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1234                   DEV_RX_OFFLOAD_KEEP_CRC |
1235                   DEV_RX_OFFLOAD_JUMBO_FRAME |
1236                   DEV_RX_OFFLOAD_IPV4_CKSUM |
1237                   DEV_RX_OFFLOAD_UDP_CKSUM |
1238                   DEV_RX_OFFLOAD_TCP_CKSUM |
1239                   DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1240                   DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1241                   DEV_RX_OFFLOAD_RSS_HASH |
1242                   DEV_RX_OFFLOAD_VLAN_FILTER))
1243                 goto use_scalar_rx;
1244
1245 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1246         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1247             rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1248                 PMD_DRV_LOG(INFO,
1249                             "Using AVX2 vector mode receive for port %d\n",
1250                             eth_dev->data->port_id);
1251                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1252                 return bnxt_recv_pkts_vec_avx2;
1253         }
1254  #endif
1255         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1256                 PMD_DRV_LOG(INFO,
1257                             "Using SSE vector mode receive for port %d\n",
1258                             eth_dev->data->port_id);
1259                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1260                 return bnxt_recv_pkts_vec;
1261         }
1262
1263 use_scalar_rx:
1264         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1265                     eth_dev->data->port_id);
1266         PMD_DRV_LOG(INFO,
1267                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1268                     eth_dev->data->port_id,
1269                     eth_dev->data->scattered_rx,
1270                     eth_dev->data->dev_conf.rxmode.offloads);
1271 #endif
1272         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1273         return bnxt_recv_pkts;
1274 }
1275
1276 static eth_tx_burst_t
1277 bnxt_transmit_function(struct rte_eth_dev *eth_dev)
1278 {
1279         struct bnxt *bp = eth_dev->data->dev_private;
1280
1281         /* Disable vector mode TX for Stingray2 for now */
1282         if (BNXT_CHIP_SR2(bp))
1283                 return bnxt_xmit_pkts;
1284
1285 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) && \
1286         !defined(RTE_LIBRTE_IEEE1588)
1287         uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1288
1289         /*
1290          * Vector mode transmit can be enabled only if not using scatter rx
1291          * or tx offloads.
1292          */
1293         if (eth_dev->data->scattered_rx ||
1294             (offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) ||
1295             BNXT_TRUFLOW_EN(bp))
1296                 goto use_scalar_tx;
1297
1298 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1299         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1300             rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1301                 PMD_DRV_LOG(INFO,
1302                             "Using AVX2 vector mode transmit for port %d\n",
1303                             eth_dev->data->port_id);
1304                 return bnxt_xmit_pkts_vec_avx2;
1305         }
1306 #endif
1307         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1308                 PMD_DRV_LOG(INFO,
1309                             "Using SSE vector mode transmit for port %d\n",
1310                             eth_dev->data->port_id);
1311                 return bnxt_xmit_pkts_vec;
1312         }
1313
1314 use_scalar_tx:
1315         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1316                     eth_dev->data->port_id);
1317         PMD_DRV_LOG(INFO,
1318                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1319                     eth_dev->data->port_id,
1320                     eth_dev->data->scattered_rx,
1321                     offloads);
1322 #endif
1323         return bnxt_xmit_pkts;
1324 }
1325
1326 static int bnxt_handle_if_change_status(struct bnxt *bp)
1327 {
1328         int rc;
1329
1330         /* Since fw has undergone a reset and lost all contexts,
1331          * set fatal flag to not issue hwrm during cleanup
1332          */
1333         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1334         bnxt_uninit_resources(bp, true);
1335
1336         /* clear fatal flag so that re-init happens */
1337         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1338         rc = bnxt_init_resources(bp, true);
1339
1340         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1341
1342         return rc;
1343 }
1344
1345 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1346 {
1347         struct bnxt *bp = eth_dev->data->dev_private;
1348         int rc = 0;
1349
1350         if (!BNXT_SINGLE_PF(bp))
1351                 return -ENOTSUP;
1352
1353         if (!bp->link_info->link_up)
1354                 rc = bnxt_set_hwrm_link_config(bp, true);
1355         if (!rc)
1356                 eth_dev->data->dev_link.link_status = 1;
1357
1358         bnxt_print_link_info(eth_dev);
1359         return rc;
1360 }
1361
1362 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1363 {
1364         struct bnxt *bp = eth_dev->data->dev_private;
1365
1366         if (!BNXT_SINGLE_PF(bp))
1367                 return -ENOTSUP;
1368
1369         eth_dev->data->dev_link.link_status = 0;
1370         bnxt_set_hwrm_link_config(bp, false);
1371         bp->link_info->link_up = 0;
1372
1373         return 0;
1374 }
1375
1376 static void bnxt_free_switch_domain(struct bnxt *bp)
1377 {
1378         int rc = 0;
1379
1380         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)))
1381                 return;
1382
1383         rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1384         if (rc)
1385                 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1386                             bp->switch_domain_id, rc);
1387 }
1388
1389 static void bnxt_ptp_get_current_time(void *arg)
1390 {
1391         struct bnxt *bp = arg;
1392         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1393         int rc;
1394
1395         rc = is_bnxt_in_error(bp);
1396         if (rc)
1397                 return;
1398
1399         if (!ptp)
1400                 return;
1401
1402         bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1403                                 &ptp->current_time);
1404
1405         rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1406         if (rc != 0) {
1407                 PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n");
1408                 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1409         }
1410 }
1411
1412 static int bnxt_schedule_ptp_alarm(struct bnxt *bp)
1413 {
1414         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1415         int rc;
1416
1417         if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED)
1418                 return 0;
1419
1420         bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1421                                 &ptp->current_time);
1422
1423         rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1424         return rc;
1425 }
1426
1427 static void bnxt_cancel_ptp_alarm(struct bnxt *bp)
1428 {
1429         if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) {
1430                 rte_eal_alarm_cancel(bnxt_ptp_get_current_time, (void *)bp);
1431                 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1432         }
1433 }
1434
1435 static void bnxt_ptp_stop(struct bnxt *bp)
1436 {
1437         bnxt_cancel_ptp_alarm(bp);
1438         bp->flags2 &= ~BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1439 }
1440
1441 static int bnxt_ptp_start(struct bnxt *bp)
1442 {
1443         int rc;
1444
1445         rc = bnxt_schedule_ptp_alarm(bp);
1446         if (rc != 0) {
1447                 PMD_DRV_LOG(ERR, "Failed to schedule PTP alarm\n");
1448         } else {
1449                 bp->flags2 |= BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1450                 bp->flags2 |= BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1451         }
1452
1453         return rc;
1454 }
1455
1456 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev)
1457 {
1458         struct bnxt *bp = eth_dev->data->dev_private;
1459         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1460         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1461         struct rte_eth_link link;
1462         int ret;
1463
1464         eth_dev->data->dev_started = 0;
1465         eth_dev->data->scattered_rx = 0;
1466
1467         /* Prevent crashes when queues are still in use */
1468         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1469         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1470
1471         bnxt_disable_int(bp);
1472
1473         /* disable uio/vfio intr/eventfd mapping */
1474         rte_intr_disable(intr_handle);
1475
1476         /* Stop the child representors for this device */
1477         ret = bnxt_rep_stop_all(bp);
1478         if (ret != 0)
1479                 return ret;
1480
1481         /* delete the bnxt ULP port details */
1482         bnxt_ulp_port_deinit(bp);
1483
1484         bnxt_cancel_fw_health_check(bp);
1485
1486         if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1487                 bnxt_cancel_ptp_alarm(bp);
1488
1489         /* Do not bring link down during reset recovery */
1490         if (!is_bnxt_in_error(bp)) {
1491                 bnxt_dev_set_link_down_op(eth_dev);
1492                 /* Wait for link to be reset */
1493                 if (BNXT_SINGLE_PF(bp))
1494                         rte_delay_ms(500);
1495                 /* clear the recorded link status */
1496                 memset(&link, 0, sizeof(link));
1497                 rte_eth_linkstatus_set(eth_dev, &link);
1498         }
1499
1500         /* Clean queue intr-vector mapping */
1501         rte_intr_efd_disable(intr_handle);
1502         if (intr_handle->intr_vec != NULL) {
1503                 rte_free(intr_handle->intr_vec);
1504                 intr_handle->intr_vec = NULL;
1505         }
1506
1507         bnxt_hwrm_port_clr_stats(bp);
1508         bnxt_free_tx_mbufs(bp);
1509         bnxt_free_rx_mbufs(bp);
1510         /* Process any remaining notifications in default completion queue */
1511         bnxt_int_handler(eth_dev);
1512         bnxt_shutdown_nic(bp);
1513         bnxt_hwrm_if_change(bp, false);
1514
1515         bnxt_free_prev_ring_stats(bp);
1516         rte_free(bp->mark_table);
1517         bp->mark_table = NULL;
1518
1519         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1520         bp->rx_cosq_cnt = 0;
1521         /* All filters are deleted on a port stop. */
1522         if (BNXT_FLOW_XSTATS_EN(bp))
1523                 bp->flow_stat->flow_count = 0;
1524
1525         return 0;
1526 }
1527
1528 /* Unload the driver, release resources */
1529 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1530 {
1531         struct bnxt *bp = eth_dev->data->dev_private;
1532
1533         pthread_mutex_lock(&bp->err_recovery_lock);
1534         if (bp->flags & BNXT_FLAG_FW_RESET) {
1535                 PMD_DRV_LOG(ERR,
1536                             "Adapter recovering from error..Please retry\n");
1537                 pthread_mutex_unlock(&bp->err_recovery_lock);
1538                 return -EAGAIN;
1539         }
1540         pthread_mutex_unlock(&bp->err_recovery_lock);
1541
1542         return bnxt_dev_stop(eth_dev);
1543 }
1544
1545 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1546 {
1547         struct bnxt *bp = eth_dev->data->dev_private;
1548         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1549         int vlan_mask = 0;
1550         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1551
1552         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1553                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1554                 return -EINVAL;
1555         }
1556
1557         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1558                 PMD_DRV_LOG(ERR,
1559                             "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1560                             bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1561
1562         do {
1563                 rc = bnxt_hwrm_if_change(bp, true);
1564                 if (rc == 0 || rc != -EAGAIN)
1565                         break;
1566
1567                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1568         } while (retry_cnt--);
1569
1570         if (rc)
1571                 return rc;
1572
1573         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1574                 rc = bnxt_handle_if_change_status(bp);
1575                 if (rc)
1576                         return rc;
1577         }
1578
1579         bnxt_enable_int(bp);
1580
1581         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1582
1583         rc = bnxt_start_nic(bp);
1584         if (rc)
1585                 goto error;
1586
1587         rc = bnxt_alloc_prev_ring_stats(bp);
1588         if (rc)
1589                 goto error;
1590
1591         eth_dev->data->dev_started = 1;
1592
1593         bnxt_link_update_op(eth_dev, 1);
1594
1595         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1596                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1597         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1598                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1599         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1600         if (rc)
1601                 goto error;
1602
1603         /* Initialize bnxt ULP port details */
1604         rc = bnxt_ulp_port_init(bp);
1605         if (rc)
1606                 goto error;
1607
1608         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1609         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1610
1611         bnxt_schedule_fw_health_check(bp);
1612
1613         if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1614                 bnxt_schedule_ptp_alarm(bp);
1615
1616         return 0;
1617
1618 error:
1619         bnxt_dev_stop(eth_dev);
1620         return rc;
1621 }
1622
1623 static void
1624 bnxt_uninit_locks(struct bnxt *bp)
1625 {
1626         pthread_mutex_destroy(&bp->flow_lock);
1627         pthread_mutex_destroy(&bp->def_cp_lock);
1628         pthread_mutex_destroy(&bp->health_check_lock);
1629         pthread_mutex_destroy(&bp->err_recovery_lock);
1630         if (bp->rep_info) {
1631                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
1632                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
1633         }
1634 }
1635
1636 static void bnxt_drv_uninit(struct bnxt *bp)
1637 {
1638         bnxt_free_leds_info(bp);
1639         bnxt_free_cos_queues(bp);
1640         bnxt_free_link_info(bp);
1641         bnxt_free_parent_info(bp);
1642         bnxt_uninit_locks(bp);
1643
1644         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1645         bp->tx_mem_zone = NULL;
1646         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1647         bp->rx_mem_zone = NULL;
1648
1649         bnxt_free_vf_info(bp);
1650         bnxt_free_pf_info(bp);
1651
1652         rte_free(bp->grp_info);
1653         bp->grp_info = NULL;
1654 }
1655
1656 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1657 {
1658         struct bnxt *bp = eth_dev->data->dev_private;
1659         int ret = 0;
1660
1661         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1662                 return 0;
1663
1664         pthread_mutex_lock(&bp->err_recovery_lock);
1665         if (bp->flags & BNXT_FLAG_FW_RESET) {
1666                 PMD_DRV_LOG(ERR,
1667                             "Adapter recovering from error...Please retry\n");
1668                 pthread_mutex_unlock(&bp->err_recovery_lock);
1669                 return -EAGAIN;
1670         }
1671         pthread_mutex_unlock(&bp->err_recovery_lock);
1672
1673         /* cancel the recovery handler before remove dev */
1674         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1675         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1676         bnxt_cancel_fc_thread(bp);
1677
1678         if (eth_dev->data->dev_started)
1679                 ret = bnxt_dev_stop(eth_dev);
1680
1681         bnxt_uninit_resources(bp, false);
1682
1683         bnxt_drv_uninit(bp);
1684
1685         return ret;
1686 }
1687
1688 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1689                                     uint32_t index)
1690 {
1691         struct bnxt *bp = eth_dev->data->dev_private;
1692         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1693         struct bnxt_vnic_info *vnic;
1694         struct bnxt_filter_info *filter, *temp_filter;
1695         uint32_t i;
1696
1697         if (is_bnxt_in_error(bp))
1698                 return;
1699
1700         /*
1701          * Loop through all VNICs from the specified filter flow pools to
1702          * remove the corresponding MAC addr filter
1703          */
1704         for (i = 0; i < bp->nr_vnics; i++) {
1705                 if (!(pool_mask & (1ULL << i)))
1706                         continue;
1707
1708                 vnic = &bp->vnic_info[i];
1709                 filter = STAILQ_FIRST(&vnic->filter);
1710                 while (filter) {
1711                         temp_filter = STAILQ_NEXT(filter, next);
1712                         if (filter->mac_index == index) {
1713                                 STAILQ_REMOVE(&vnic->filter, filter,
1714                                                 bnxt_filter_info, next);
1715                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1716                                 bnxt_free_filter(bp, filter);
1717                         }
1718                         filter = temp_filter;
1719                 }
1720         }
1721 }
1722
1723 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1724                                struct rte_ether_addr *mac_addr, uint32_t index,
1725                                uint32_t pool)
1726 {
1727         struct bnxt_filter_info *filter;
1728         int rc = 0;
1729
1730         /* Attach requested MAC address to the new l2_filter */
1731         STAILQ_FOREACH(filter, &vnic->filter, next) {
1732                 if (filter->mac_index == index) {
1733                         PMD_DRV_LOG(DEBUG,
1734                                     "MAC addr already existed for pool %d\n",
1735                                     pool);
1736                         return 0;
1737                 }
1738         }
1739
1740         filter = bnxt_alloc_filter(bp);
1741         if (!filter) {
1742                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1743                 return -ENODEV;
1744         }
1745
1746         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1747          * if the MAC that's been programmed now is a different one, then,
1748          * copy that addr to filter->l2_addr
1749          */
1750         if (mac_addr)
1751                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1752         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1753
1754         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1755         if (!rc) {
1756                 filter->mac_index = index;
1757                 if (filter->mac_index == 0)
1758                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1759                 else
1760                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1761         } else {
1762                 bnxt_free_filter(bp, filter);
1763         }
1764
1765         return rc;
1766 }
1767
1768 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1769                                 struct rte_ether_addr *mac_addr,
1770                                 uint32_t index, uint32_t pool)
1771 {
1772         struct bnxt *bp = eth_dev->data->dev_private;
1773         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1774         int rc = 0;
1775
1776         rc = is_bnxt_in_error(bp);
1777         if (rc)
1778                 return rc;
1779
1780         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1781                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1782                 return -ENOTSUP;
1783         }
1784
1785         if (!vnic) {
1786                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1787                 return -EINVAL;
1788         }
1789
1790         /* Filter settings will get applied when port is started */
1791         if (!eth_dev->data->dev_started)
1792                 return 0;
1793
1794         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1795
1796         return rc;
1797 }
1798
1799 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1800 {
1801         int rc = 0;
1802         struct bnxt *bp = eth_dev->data->dev_private;
1803         struct rte_eth_link new;
1804         int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1805                         BNXT_MIN_LINK_WAIT_CNT;
1806
1807         rc = is_bnxt_in_error(bp);
1808         if (rc)
1809                 return rc;
1810
1811         memset(&new, 0, sizeof(new));
1812
1813         if (bp->link_info == NULL)
1814                 goto out;
1815
1816         do {
1817                 /* Retrieve link info from hardware */
1818                 rc = bnxt_get_hwrm_link_config(bp, &new);
1819                 if (rc) {
1820                         new.link_speed = ETH_LINK_SPEED_100M;
1821                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1822                         PMD_DRV_LOG(ERR,
1823                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1824                         goto out;
1825                 }
1826
1827                 if (!wait_to_complete || new.link_status)
1828                         break;
1829
1830                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1831         } while (cnt--);
1832
1833         /* Only single function PF can bring phy down.
1834          * When port is stopped, report link down for VF/MH/NPAR functions.
1835          */
1836         if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1837                 memset(&new, 0, sizeof(new));
1838
1839 out:
1840         /* Timed out or success */
1841         if (new.link_status != eth_dev->data->dev_link.link_status ||
1842             new.link_speed != eth_dev->data->dev_link.link_speed) {
1843                 rte_eth_linkstatus_set(eth_dev, &new);
1844
1845                 rte_eth_dev_callback_process(eth_dev,
1846                                              RTE_ETH_EVENT_INTR_LSC,
1847                                              NULL);
1848
1849                 bnxt_print_link_info(eth_dev);
1850         }
1851
1852         return rc;
1853 }
1854
1855 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1856 {
1857         struct bnxt *bp = eth_dev->data->dev_private;
1858         struct bnxt_vnic_info *vnic;
1859         uint32_t old_flags;
1860         int rc;
1861
1862         rc = is_bnxt_in_error(bp);
1863         if (rc)
1864                 return rc;
1865
1866         /* Filter settings will get applied when port is started */
1867         if (!eth_dev->data->dev_started)
1868                 return 0;
1869
1870         if (bp->vnic_info == NULL)
1871                 return 0;
1872
1873         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1874
1875         old_flags = vnic->flags;
1876         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1877         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1878         if (rc != 0)
1879                 vnic->flags = old_flags;
1880
1881         return rc;
1882 }
1883
1884 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1885 {
1886         struct bnxt *bp = eth_dev->data->dev_private;
1887         struct bnxt_vnic_info *vnic;
1888         uint32_t old_flags;
1889         int rc;
1890
1891         rc = is_bnxt_in_error(bp);
1892         if (rc)
1893                 return rc;
1894
1895         /* Filter settings will get applied when port is started */
1896         if (!eth_dev->data->dev_started)
1897                 return 0;
1898
1899         if (bp->vnic_info == NULL)
1900                 return 0;
1901
1902         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1903
1904         old_flags = vnic->flags;
1905         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1906         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1907         if (rc != 0)
1908                 vnic->flags = old_flags;
1909
1910         return rc;
1911 }
1912
1913 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1914 {
1915         struct bnxt *bp = eth_dev->data->dev_private;
1916         struct bnxt_vnic_info *vnic;
1917         uint32_t old_flags;
1918         int rc;
1919
1920         rc = is_bnxt_in_error(bp);
1921         if (rc)
1922                 return rc;
1923
1924         /* Filter settings will get applied when port is started */
1925         if (!eth_dev->data->dev_started)
1926                 return 0;
1927
1928         if (bp->vnic_info == NULL)
1929                 return 0;
1930
1931         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1932
1933         old_flags = vnic->flags;
1934         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1935         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1936         if (rc != 0)
1937                 vnic->flags = old_flags;
1938
1939         return rc;
1940 }
1941
1942 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1943 {
1944         struct bnxt *bp = eth_dev->data->dev_private;
1945         struct bnxt_vnic_info *vnic;
1946         uint32_t old_flags;
1947         int rc;
1948
1949         rc = is_bnxt_in_error(bp);
1950         if (rc)
1951                 return rc;
1952
1953         /* Filter settings will get applied when port is started */
1954         if (!eth_dev->data->dev_started)
1955                 return 0;
1956
1957         if (bp->vnic_info == NULL)
1958                 return 0;
1959
1960         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1961
1962         old_flags = vnic->flags;
1963         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1964         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1965         if (rc != 0)
1966                 vnic->flags = old_flags;
1967
1968         return rc;
1969 }
1970
1971 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1972 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1973 {
1974         if (qid >= bp->rx_nr_rings)
1975                 return NULL;
1976
1977         return bp->eth_dev->data->rx_queues[qid];
1978 }
1979
1980 /* Return rxq corresponding to a given rss table ring/group ID. */
1981 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1982 {
1983         struct bnxt_rx_queue *rxq;
1984         unsigned int i;
1985
1986         if (!BNXT_HAS_RING_GRPS(bp)) {
1987                 for (i = 0; i < bp->rx_nr_rings; i++) {
1988                         rxq = bp->eth_dev->data->rx_queues[i];
1989                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1990                                 return rxq->index;
1991                 }
1992         } else {
1993                 for (i = 0; i < bp->rx_nr_rings; i++) {
1994                         if (bp->grp_info[i].fw_grp_id == fwr)
1995                                 return i;
1996                 }
1997         }
1998
1999         return INVALID_HW_RING_ID;
2000 }
2001
2002 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
2003                             struct rte_eth_rss_reta_entry64 *reta_conf,
2004                             uint16_t reta_size)
2005 {
2006         struct bnxt *bp = eth_dev->data->dev_private;
2007         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2008         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2009         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
2010         uint16_t idx, sft;
2011         int i, rc;
2012
2013         rc = is_bnxt_in_error(bp);
2014         if (rc)
2015                 return rc;
2016
2017         if (!vnic->rss_table)
2018                 return -EINVAL;
2019
2020         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
2021                 return -EINVAL;
2022
2023         if (reta_size != tbl_size) {
2024                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2025                         "(%d) must equal the size supported by the hardware "
2026                         "(%d)\n", reta_size, tbl_size);
2027                 return -EINVAL;
2028         }
2029
2030         for (i = 0; i < reta_size; i++) {
2031                 struct bnxt_rx_queue *rxq;
2032
2033                 idx = i / RTE_RETA_GROUP_SIZE;
2034                 sft = i % RTE_RETA_GROUP_SIZE;
2035
2036                 if (!(reta_conf[idx].mask & (1ULL << sft)))
2037                         continue;
2038
2039                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
2040                 if (!rxq) {
2041                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
2042                         return -EINVAL;
2043                 }
2044
2045                 if (BNXT_CHIP_P5(bp)) {
2046                         vnic->rss_table[i * 2] =
2047                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
2048                         vnic->rss_table[i * 2 + 1] =
2049                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
2050                 } else {
2051                         vnic->rss_table[i] =
2052                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
2053                 }
2054         }
2055
2056         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2057         return rc;
2058 }
2059
2060 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
2061                               struct rte_eth_rss_reta_entry64 *reta_conf,
2062                               uint16_t reta_size)
2063 {
2064         struct bnxt *bp = eth_dev->data->dev_private;
2065         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2066         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
2067         uint16_t idx, sft, i;
2068         int rc;
2069
2070         rc = is_bnxt_in_error(bp);
2071         if (rc)
2072                 return rc;
2073
2074         if (!vnic)
2075                 return -EINVAL;
2076         if (!vnic->rss_table)
2077                 return -EINVAL;
2078
2079         if (reta_size != tbl_size) {
2080                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2081                         "(%d) must equal the size supported by the hardware "
2082                         "(%d)\n", reta_size, tbl_size);
2083                 return -EINVAL;
2084         }
2085
2086         for (idx = 0, i = 0; i < reta_size; i++) {
2087                 idx = i / RTE_RETA_GROUP_SIZE;
2088                 sft = i % RTE_RETA_GROUP_SIZE;
2089
2090                 if (reta_conf[idx].mask & (1ULL << sft)) {
2091                         uint16_t qid;
2092
2093                         if (BNXT_CHIP_P5(bp))
2094                                 qid = bnxt_rss_to_qid(bp,
2095                                                       vnic->rss_table[i * 2]);
2096                         else
2097                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
2098
2099                         if (qid == INVALID_HW_RING_ID) {
2100                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
2101                                 return -EINVAL;
2102                         }
2103                         reta_conf[idx].reta[sft] = qid;
2104                 }
2105         }
2106
2107         return 0;
2108 }
2109
2110 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
2111                                    struct rte_eth_rss_conf *rss_conf)
2112 {
2113         struct bnxt *bp = eth_dev->data->dev_private;
2114         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2115         struct bnxt_vnic_info *vnic;
2116         int rc;
2117
2118         rc = is_bnxt_in_error(bp);
2119         if (rc)
2120                 return rc;
2121
2122         /*
2123          * If RSS enablement were different than dev_configure,
2124          * then return -EINVAL
2125          */
2126         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
2127                 if (!rss_conf->rss_hf)
2128                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
2129         } else {
2130                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
2131                         return -EINVAL;
2132         }
2133
2134         bp->flags |= BNXT_FLAG_UPDATE_HASH;
2135         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
2136                rss_conf,
2137                sizeof(*rss_conf));
2138
2139         /* Update the default RSS VNIC(s) */
2140         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2141         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
2142         vnic->hash_mode =
2143                 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
2144                                             ETH_RSS_LEVEL(rss_conf->rss_hf));
2145
2146         /*
2147          * If hashkey is not specified, use the previously configured
2148          * hashkey
2149          */
2150         if (!rss_conf->rss_key)
2151                 goto rss_config;
2152
2153         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
2154                 PMD_DRV_LOG(ERR,
2155                             "Invalid hashkey length, should be 16 bytes\n");
2156                 return -EINVAL;
2157         }
2158         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
2159
2160 rss_config:
2161         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2162         return rc;
2163 }
2164
2165 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
2166                                      struct rte_eth_rss_conf *rss_conf)
2167 {
2168         struct bnxt *bp = eth_dev->data->dev_private;
2169         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2170         int len, rc;
2171         uint32_t hash_types;
2172
2173         rc = is_bnxt_in_error(bp);
2174         if (rc)
2175                 return rc;
2176
2177         /* RSS configuration is the same for all VNICs */
2178         if (vnic && vnic->rss_hash_key) {
2179                 if (rss_conf->rss_key) {
2180                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
2181                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
2182                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
2183                 }
2184
2185                 hash_types = vnic->hash_type;
2186                 rss_conf->rss_hf = 0;
2187                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
2188                         rss_conf->rss_hf |= ETH_RSS_IPV4;
2189                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
2190                 }
2191                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
2192                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2193                         hash_types &=
2194                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
2195                 }
2196                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
2197                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2198                         hash_types &=
2199                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
2200                 }
2201                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
2202                         rss_conf->rss_hf |= ETH_RSS_IPV6;
2203                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
2204                 }
2205                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
2206                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2207                         hash_types &=
2208                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
2209                 }
2210                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
2211                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2212                         hash_types &=
2213                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2214                 }
2215
2216                 rss_conf->rss_hf |=
2217                         bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2218
2219                 if (hash_types) {
2220                         PMD_DRV_LOG(ERR,
2221                                 "Unknown RSS config from firmware (%08x), RSS disabled",
2222                                 vnic->hash_type);
2223                         return -ENOTSUP;
2224                 }
2225         } else {
2226                 rss_conf->rss_hf = 0;
2227         }
2228         return 0;
2229 }
2230
2231 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2232                                struct rte_eth_fc_conf *fc_conf)
2233 {
2234         struct bnxt *bp = dev->data->dev_private;
2235         struct rte_eth_link link_info;
2236         int rc;
2237
2238         rc = is_bnxt_in_error(bp);
2239         if (rc)
2240                 return rc;
2241
2242         rc = bnxt_get_hwrm_link_config(bp, &link_info);
2243         if (rc)
2244                 return rc;
2245
2246         memset(fc_conf, 0, sizeof(*fc_conf));
2247         if (bp->link_info->auto_pause)
2248                 fc_conf->autoneg = 1;
2249         switch (bp->link_info->pause) {
2250         case 0:
2251                 fc_conf->mode = RTE_FC_NONE;
2252                 break;
2253         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2254                 fc_conf->mode = RTE_FC_TX_PAUSE;
2255                 break;
2256         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2257                 fc_conf->mode = RTE_FC_RX_PAUSE;
2258                 break;
2259         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2260                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2261                 fc_conf->mode = RTE_FC_FULL;
2262                 break;
2263         }
2264         return 0;
2265 }
2266
2267 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2268                                struct rte_eth_fc_conf *fc_conf)
2269 {
2270         struct bnxt *bp = dev->data->dev_private;
2271         int rc;
2272
2273         rc = is_bnxt_in_error(bp);
2274         if (rc)
2275                 return rc;
2276
2277         if (!BNXT_SINGLE_PF(bp)) {
2278                 PMD_DRV_LOG(ERR,
2279                             "Flow Control Settings cannot be modified on VF or on shared PF\n");
2280                 return -ENOTSUP;
2281         }
2282
2283         switch (fc_conf->mode) {
2284         case RTE_FC_NONE:
2285                 bp->link_info->auto_pause = 0;
2286                 bp->link_info->force_pause = 0;
2287                 break;
2288         case RTE_FC_RX_PAUSE:
2289                 if (fc_conf->autoneg) {
2290                         bp->link_info->auto_pause =
2291                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2292                         bp->link_info->force_pause = 0;
2293                 } else {
2294                         bp->link_info->auto_pause = 0;
2295                         bp->link_info->force_pause =
2296                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2297                 }
2298                 break;
2299         case RTE_FC_TX_PAUSE:
2300                 if (fc_conf->autoneg) {
2301                         bp->link_info->auto_pause =
2302                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2303                         bp->link_info->force_pause = 0;
2304                 } else {
2305                         bp->link_info->auto_pause = 0;
2306                         bp->link_info->force_pause =
2307                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2308                 }
2309                 break;
2310         case RTE_FC_FULL:
2311                 if (fc_conf->autoneg) {
2312                         bp->link_info->auto_pause =
2313                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2314                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2315                         bp->link_info->force_pause = 0;
2316                 } else {
2317                         bp->link_info->auto_pause = 0;
2318                         bp->link_info->force_pause =
2319                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2320                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2321                 }
2322                 break;
2323         }
2324         return bnxt_set_hwrm_link_config(bp, true);
2325 }
2326
2327 /* Add UDP tunneling port */
2328 static int
2329 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2330                          struct rte_eth_udp_tunnel *udp_tunnel)
2331 {
2332         struct bnxt *bp = eth_dev->data->dev_private;
2333         uint16_t tunnel_type = 0;
2334         int rc = 0;
2335
2336         rc = is_bnxt_in_error(bp);
2337         if (rc)
2338                 return rc;
2339
2340         switch (udp_tunnel->prot_type) {
2341         case RTE_TUNNEL_TYPE_VXLAN:
2342                 if (bp->vxlan_port_cnt) {
2343                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2344                                 udp_tunnel->udp_port);
2345                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2346                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2347                                 return -ENOSPC;
2348                         }
2349                         bp->vxlan_port_cnt++;
2350                         return 0;
2351                 }
2352                 tunnel_type =
2353                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2354                 bp->vxlan_port_cnt++;
2355                 break;
2356         case RTE_TUNNEL_TYPE_GENEVE:
2357                 if (bp->geneve_port_cnt) {
2358                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2359                                 udp_tunnel->udp_port);
2360                         if (bp->geneve_port != udp_tunnel->udp_port) {
2361                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2362                                 return -ENOSPC;
2363                         }
2364                         bp->geneve_port_cnt++;
2365                         return 0;
2366                 }
2367                 tunnel_type =
2368                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2369                 bp->geneve_port_cnt++;
2370                 break;
2371         default:
2372                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2373                 return -ENOTSUP;
2374         }
2375         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2376                                              tunnel_type);
2377         return rc;
2378 }
2379
2380 static int
2381 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2382                          struct rte_eth_udp_tunnel *udp_tunnel)
2383 {
2384         struct bnxt *bp = eth_dev->data->dev_private;
2385         uint16_t tunnel_type = 0;
2386         uint16_t port = 0;
2387         int rc = 0;
2388
2389         rc = is_bnxt_in_error(bp);
2390         if (rc)
2391                 return rc;
2392
2393         switch (udp_tunnel->prot_type) {
2394         case RTE_TUNNEL_TYPE_VXLAN:
2395                 if (!bp->vxlan_port_cnt) {
2396                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2397                         return -EINVAL;
2398                 }
2399                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2400                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2401                                 udp_tunnel->udp_port, bp->vxlan_port);
2402                         return -EINVAL;
2403                 }
2404                 if (--bp->vxlan_port_cnt)
2405                         return 0;
2406
2407                 tunnel_type =
2408                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2409                 port = bp->vxlan_fw_dst_port_id;
2410                 break;
2411         case RTE_TUNNEL_TYPE_GENEVE:
2412                 if (!bp->geneve_port_cnt) {
2413                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2414                         return -EINVAL;
2415                 }
2416                 if (bp->geneve_port != udp_tunnel->udp_port) {
2417                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2418                                 udp_tunnel->udp_port, bp->geneve_port);
2419                         return -EINVAL;
2420                 }
2421                 if (--bp->geneve_port_cnt)
2422                         return 0;
2423
2424                 tunnel_type =
2425                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2426                 port = bp->geneve_fw_dst_port_id;
2427                 break;
2428         default:
2429                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2430                 return -ENOTSUP;
2431         }
2432
2433         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2434         return rc;
2435 }
2436
2437 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2438 {
2439         struct bnxt_filter_info *filter;
2440         struct bnxt_vnic_info *vnic;
2441         int rc = 0;
2442         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2443
2444         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2445         filter = STAILQ_FIRST(&vnic->filter);
2446         while (filter) {
2447                 /* Search for this matching MAC+VLAN filter */
2448                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2449                         /* Delete the filter */
2450                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2451                         if (rc)
2452                                 return rc;
2453                         STAILQ_REMOVE(&vnic->filter, filter,
2454                                       bnxt_filter_info, next);
2455                         bnxt_free_filter(bp, filter);
2456                         PMD_DRV_LOG(INFO,
2457                                     "Deleted vlan filter for %d\n",
2458                                     vlan_id);
2459                         return 0;
2460                 }
2461                 filter = STAILQ_NEXT(filter, next);
2462         }
2463         return -ENOENT;
2464 }
2465
2466 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2467 {
2468         struct bnxt_filter_info *filter;
2469         struct bnxt_vnic_info *vnic;
2470         int rc = 0;
2471         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2472                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2473         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2474
2475         /* Implementation notes on the use of VNIC in this command:
2476          *
2477          * By default, these filters belong to default vnic for the function.
2478          * Once these filters are set up, only destination VNIC can be modified.
2479          * If the destination VNIC is not specified in this command,
2480          * then the HWRM shall only create an l2 context id.
2481          */
2482
2483         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2484         filter = STAILQ_FIRST(&vnic->filter);
2485         /* Check if the VLAN has already been added */
2486         while (filter) {
2487                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2488                         return -EEXIST;
2489
2490                 filter = STAILQ_NEXT(filter, next);
2491         }
2492
2493         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2494          * command to create MAC+VLAN filter with the right flags, enables set.
2495          */
2496         filter = bnxt_alloc_filter(bp);
2497         if (!filter) {
2498                 PMD_DRV_LOG(ERR,
2499                             "MAC/VLAN filter alloc failed\n");
2500                 return -ENOMEM;
2501         }
2502         /* MAC + VLAN ID filter */
2503         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2504          * untagged packets are received
2505          *
2506          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2507          * packets and only the programmed vlan's packets are received
2508          */
2509         filter->l2_ivlan = vlan_id;
2510         filter->l2_ivlan_mask = 0x0FFF;
2511         filter->enables |= en;
2512         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2513
2514         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2515         if (rc) {
2516                 /* Free the newly allocated filter as we were
2517                  * not able to create the filter in hardware.
2518                  */
2519                 bnxt_free_filter(bp, filter);
2520                 return rc;
2521         }
2522
2523         filter->mac_index = 0;
2524         /* Add this new filter to the list */
2525         if (vlan_id == 0)
2526                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2527         else
2528                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2529
2530         PMD_DRV_LOG(INFO,
2531                     "Added Vlan filter for %d\n", vlan_id);
2532         return rc;
2533 }
2534
2535 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2536                 uint16_t vlan_id, int on)
2537 {
2538         struct bnxt *bp = eth_dev->data->dev_private;
2539         int rc;
2540
2541         rc = is_bnxt_in_error(bp);
2542         if (rc)
2543                 return rc;
2544
2545         if (!eth_dev->data->dev_started) {
2546                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2547                 return -EINVAL;
2548         }
2549
2550         /* These operations apply to ALL existing MAC/VLAN filters */
2551         if (on)
2552                 return bnxt_add_vlan_filter(bp, vlan_id);
2553         else
2554                 return bnxt_del_vlan_filter(bp, vlan_id);
2555 }
2556
2557 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2558                                     struct bnxt_vnic_info *vnic)
2559 {
2560         struct bnxt_filter_info *filter;
2561         int rc;
2562
2563         filter = STAILQ_FIRST(&vnic->filter);
2564         while (filter) {
2565                 if (filter->mac_index == 0 &&
2566                     !memcmp(filter->l2_addr, bp->mac_addr,
2567                             RTE_ETHER_ADDR_LEN)) {
2568                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2569                         if (!rc) {
2570                                 STAILQ_REMOVE(&vnic->filter, filter,
2571                                               bnxt_filter_info, next);
2572                                 bnxt_free_filter(bp, filter);
2573                         }
2574                         return rc;
2575                 }
2576                 filter = STAILQ_NEXT(filter, next);
2577         }
2578         return 0;
2579 }
2580
2581 static int
2582 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2583 {
2584         struct bnxt_vnic_info *vnic;
2585         unsigned int i;
2586         int rc;
2587
2588         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2589         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2590                 /* Remove any VLAN filters programmed */
2591                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2592                         bnxt_del_vlan_filter(bp, i);
2593
2594                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2595                 if (rc)
2596                         return rc;
2597         } else {
2598                 /* Default filter will allow packets that match the
2599                  * dest mac. So, it has to be deleted, otherwise, we
2600                  * will endup receiving vlan packets for which the
2601                  * filter is not programmed, when hw-vlan-filter
2602                  * configuration is ON
2603                  */
2604                 bnxt_del_dflt_mac_filter(bp, vnic);
2605                 /* This filter will allow only untagged packets */
2606                 bnxt_add_vlan_filter(bp, 0);
2607         }
2608         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2609                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2610
2611         return 0;
2612 }
2613
2614 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2615 {
2616         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2617         unsigned int i;
2618         int rc;
2619
2620         /* Destroy vnic filters and vnic */
2621         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2622             DEV_RX_OFFLOAD_VLAN_FILTER) {
2623                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2624                         bnxt_del_vlan_filter(bp, i);
2625         }
2626         bnxt_del_dflt_mac_filter(bp, vnic);
2627
2628         rc = bnxt_hwrm_vnic_ctx_free(bp, vnic);
2629         if (rc)
2630                 return rc;
2631
2632         rc = bnxt_hwrm_vnic_free(bp, vnic);
2633         if (rc)
2634                 return rc;
2635
2636         rte_free(vnic->fw_grp_ids);
2637         vnic->fw_grp_ids = NULL;
2638
2639         vnic->rx_queue_cnt = 0;
2640
2641         return 0;
2642 }
2643
2644 static int
2645 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2646 {
2647         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2648         int rc;
2649
2650         /* Destroy, recreate and reconfigure the default vnic */
2651         rc = bnxt_free_one_vnic(bp, 0);
2652         if (rc)
2653                 return rc;
2654
2655         /* default vnic 0 */
2656         rc = bnxt_setup_one_vnic(bp, 0);
2657         if (rc)
2658                 return rc;
2659
2660         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2661             DEV_RX_OFFLOAD_VLAN_FILTER) {
2662                 rc = bnxt_add_vlan_filter(bp, 0);
2663                 if (rc)
2664                         return rc;
2665                 rc = bnxt_restore_vlan_filters(bp);
2666                 if (rc)
2667                         return rc;
2668         } else {
2669                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2670                 if (rc)
2671                         return rc;
2672         }
2673
2674         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2675         if (rc)
2676                 return rc;
2677
2678         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2679                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2680
2681         return rc;
2682 }
2683
2684 static int
2685 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2686 {
2687         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2688         struct bnxt *bp = dev->data->dev_private;
2689         int rc;
2690
2691         rc = is_bnxt_in_error(bp);
2692         if (rc)
2693                 return rc;
2694
2695         /* Filter settings will get applied when port is started */
2696         if (!dev->data->dev_started)
2697                 return 0;
2698
2699         if (mask & ETH_VLAN_FILTER_MASK) {
2700                 /* Enable or disable VLAN filtering */
2701                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2702                 if (rc)
2703                         return rc;
2704         }
2705
2706         if (mask & ETH_VLAN_STRIP_MASK) {
2707                 /* Enable or disable VLAN stripping */
2708                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2709                 if (rc)
2710                         return rc;
2711         }
2712
2713         if (mask & ETH_VLAN_EXTEND_MASK) {
2714                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2715                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2716                 else
2717                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2718         }
2719
2720         return 0;
2721 }
2722
2723 static int
2724 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2725                       uint16_t tpid)
2726 {
2727         struct bnxt *bp = dev->data->dev_private;
2728         int qinq = dev->data->dev_conf.rxmode.offloads &
2729                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2730
2731         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2732             vlan_type != ETH_VLAN_TYPE_OUTER) {
2733                 PMD_DRV_LOG(ERR,
2734                             "Unsupported vlan type.");
2735                 return -EINVAL;
2736         }
2737         if (!qinq) {
2738                 PMD_DRV_LOG(ERR,
2739                             "QinQ not enabled. Needs to be ON as we can "
2740                             "accelerate only outer vlan\n");
2741                 return -EINVAL;
2742         }
2743
2744         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2745                 switch (tpid) {
2746                 case RTE_ETHER_TYPE_QINQ:
2747                         bp->outer_tpid_bd =
2748                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2749                                 break;
2750                 case RTE_ETHER_TYPE_VLAN:
2751                         bp->outer_tpid_bd =
2752                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2753                                 break;
2754                 case RTE_ETHER_TYPE_QINQ1:
2755                         bp->outer_tpid_bd =
2756                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2757                                 break;
2758                 case RTE_ETHER_TYPE_QINQ2:
2759                         bp->outer_tpid_bd =
2760                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2761                                 break;
2762                 case RTE_ETHER_TYPE_QINQ3:
2763                         bp->outer_tpid_bd =
2764                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2765                                 break;
2766                 default:
2767                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2768                         return -EINVAL;
2769                 }
2770                 bp->outer_tpid_bd |= tpid;
2771                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2772         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2773                 PMD_DRV_LOG(ERR,
2774                             "Can accelerate only outer vlan in QinQ\n");
2775                 return -EINVAL;
2776         }
2777
2778         return 0;
2779 }
2780
2781 static int
2782 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2783                              struct rte_ether_addr *addr)
2784 {
2785         struct bnxt *bp = dev->data->dev_private;
2786         /* Default Filter is tied to VNIC 0 */
2787         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2788         int rc;
2789
2790         rc = is_bnxt_in_error(bp);
2791         if (rc)
2792                 return rc;
2793
2794         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2795                 return -EPERM;
2796
2797         if (rte_is_zero_ether_addr(addr))
2798                 return -EINVAL;
2799
2800         /* Filter settings will get applied when port is started */
2801         if (!dev->data->dev_started)
2802                 return 0;
2803
2804         /* Check if the requested MAC is already added */
2805         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2806                 return 0;
2807
2808         /* Destroy filter and re-create it */
2809         bnxt_del_dflt_mac_filter(bp, vnic);
2810
2811         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2812         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2813                 /* This filter will allow only untagged packets */
2814                 rc = bnxt_add_vlan_filter(bp, 0);
2815         } else {
2816                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2817         }
2818
2819         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2820         return rc;
2821 }
2822
2823 static int
2824 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2825                           struct rte_ether_addr *mc_addr_set,
2826                           uint32_t nb_mc_addr)
2827 {
2828         struct bnxt *bp = eth_dev->data->dev_private;
2829         char *mc_addr_list = (char *)mc_addr_set;
2830         struct bnxt_vnic_info *vnic;
2831         uint32_t off = 0, i = 0;
2832         int rc;
2833
2834         rc = is_bnxt_in_error(bp);
2835         if (rc)
2836                 return rc;
2837
2838         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2839
2840         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2841                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2842                 goto allmulti;
2843         }
2844
2845         /* TODO Check for Duplicate mcast addresses */
2846         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2847         for (i = 0; i < nb_mc_addr; i++) {
2848                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2849                         RTE_ETHER_ADDR_LEN);
2850                 off += RTE_ETHER_ADDR_LEN;
2851         }
2852
2853         vnic->mc_addr_cnt = i;
2854         if (vnic->mc_addr_cnt)
2855                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2856         else
2857                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2858
2859 allmulti:
2860         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2861 }
2862
2863 static int
2864 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2865 {
2866         struct bnxt *bp = dev->data->dev_private;
2867         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2868         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2869         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2870         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2871         int ret;
2872
2873         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2874                         fw_major, fw_minor, fw_updt, fw_rsvd);
2875         if (ret < 0)
2876                 return -EINVAL;
2877
2878         ret += 1; /* add the size of '\0' */
2879         if (fw_size < (size_t)ret)
2880                 return ret;
2881         else
2882                 return 0;
2883 }
2884
2885 static void
2886 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2887         struct rte_eth_rxq_info *qinfo)
2888 {
2889         struct bnxt *bp = dev->data->dev_private;
2890         struct bnxt_rx_queue *rxq;
2891
2892         if (is_bnxt_in_error(bp))
2893                 return;
2894
2895         rxq = dev->data->rx_queues[queue_id];
2896
2897         qinfo->mp = rxq->mb_pool;
2898         qinfo->scattered_rx = dev->data->scattered_rx;
2899         qinfo->nb_desc = rxq->nb_rx_desc;
2900
2901         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2902         qinfo->conf.rx_drop_en = rxq->drop_en;
2903         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2904         qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2905 }
2906
2907 static void
2908 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2909         struct rte_eth_txq_info *qinfo)
2910 {
2911         struct bnxt *bp = dev->data->dev_private;
2912         struct bnxt_tx_queue *txq;
2913
2914         if (is_bnxt_in_error(bp))
2915                 return;
2916
2917         txq = dev->data->tx_queues[queue_id];
2918
2919         qinfo->nb_desc = txq->nb_tx_desc;
2920
2921         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2922         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2923         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2924
2925         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2926         qinfo->conf.tx_rs_thresh = 0;
2927         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2928         qinfo->conf.offloads = txq->offloads;
2929 }
2930
2931 static const struct {
2932         eth_rx_burst_t pkt_burst;
2933         const char *info;
2934 } bnxt_rx_burst_info[] = {
2935         {bnxt_recv_pkts,                "Scalar"},
2936 #if defined(RTE_ARCH_X86)
2937         {bnxt_recv_pkts_vec,            "Vector SSE"},
2938 #endif
2939 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2940         {bnxt_recv_pkts_vec_avx2,       "Vector AVX2"},
2941 #endif
2942 #if defined(RTE_ARCH_ARM64)
2943         {bnxt_recv_pkts_vec,            "Vector Neon"},
2944 #endif
2945 };
2946
2947 static int
2948 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2949                        struct rte_eth_burst_mode *mode)
2950 {
2951         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2952         size_t i;
2953
2954         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2955                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2956                         snprintf(mode->info, sizeof(mode->info), "%s",
2957                                  bnxt_rx_burst_info[i].info);
2958                         return 0;
2959                 }
2960         }
2961
2962         return -EINVAL;
2963 }
2964
2965 static const struct {
2966         eth_tx_burst_t pkt_burst;
2967         const char *info;
2968 } bnxt_tx_burst_info[] = {
2969         {bnxt_xmit_pkts,                "Scalar"},
2970 #if defined(RTE_ARCH_X86)
2971         {bnxt_xmit_pkts_vec,            "Vector SSE"},
2972 #endif
2973 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2974         {bnxt_xmit_pkts_vec_avx2,       "Vector AVX2"},
2975 #endif
2976 #if defined(RTE_ARCH_ARM64)
2977         {bnxt_xmit_pkts_vec,            "Vector Neon"},
2978 #endif
2979 };
2980
2981 static int
2982 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2983                        struct rte_eth_burst_mode *mode)
2984 {
2985         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2986         size_t i;
2987
2988         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2989                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2990                         snprintf(mode->info, sizeof(mode->info), "%s",
2991                                  bnxt_tx_burst_info[i].info);
2992                         return 0;
2993                 }
2994         }
2995
2996         return -EINVAL;
2997 }
2998
2999 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
3000 {
3001         struct bnxt *bp = eth_dev->data->dev_private;
3002         uint32_t new_pkt_size;
3003         uint32_t rc = 0;
3004         uint32_t i;
3005
3006         rc = is_bnxt_in_error(bp);
3007         if (rc)
3008                 return rc;
3009
3010         /* Exit if receive queues are not configured yet */
3011         if (!eth_dev->data->nb_rx_queues)
3012                 return rc;
3013
3014         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
3015                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
3016
3017         /*
3018          * Disallow any MTU change that would require scattered receive support
3019          * if it is not already enabled.
3020          */
3021         if (eth_dev->data->dev_started &&
3022             !eth_dev->data->scattered_rx &&
3023             (new_pkt_size >
3024              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
3025                 PMD_DRV_LOG(ERR,
3026                             "MTU change would require scattered rx support. ");
3027                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
3028                 return -EINVAL;
3029         }
3030
3031         if (new_mtu > RTE_ETHER_MTU) {
3032                 bp->flags |= BNXT_FLAG_JUMBO;
3033                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
3034                         DEV_RX_OFFLOAD_JUMBO_FRAME;
3035         } else {
3036                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
3037                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3038                 bp->flags &= ~BNXT_FLAG_JUMBO;
3039         }
3040
3041         /* Is there a change in mtu setting? */
3042         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
3043                 return rc;
3044
3045         for (i = 0; i < bp->nr_vnics; i++) {
3046                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3047                 uint16_t size = 0;
3048
3049                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
3050                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
3051                 if (rc)
3052                         break;
3053
3054                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
3055                 size -= RTE_PKTMBUF_HEADROOM;
3056
3057                 if (size < new_mtu) {
3058                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
3059                         if (rc)
3060                                 return rc;
3061                 }
3062         }
3063
3064         if (!rc)
3065                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
3066
3067         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
3068
3069         return rc;
3070 }
3071
3072 static int
3073 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
3074 {
3075         struct bnxt *bp = dev->data->dev_private;
3076         uint16_t vlan = bp->vlan;
3077         int rc;
3078
3079         rc = is_bnxt_in_error(bp);
3080         if (rc)
3081                 return rc;
3082
3083         if (!BNXT_SINGLE_PF(bp)) {
3084                 PMD_DRV_LOG(ERR, "PVID cannot be modified on VF or on shared PF\n");
3085                 return -ENOTSUP;
3086         }
3087         bp->vlan = on ? pvid : 0;
3088
3089         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
3090         if (rc)
3091                 bp->vlan = vlan;
3092         return rc;
3093 }
3094
3095 static int
3096 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
3097 {
3098         struct bnxt *bp = dev->data->dev_private;
3099         int rc;
3100
3101         rc = is_bnxt_in_error(bp);
3102         if (rc)
3103                 return rc;
3104
3105         return bnxt_hwrm_port_led_cfg(bp, true);
3106 }
3107
3108 static int
3109 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
3110 {
3111         struct bnxt *bp = dev->data->dev_private;
3112         int rc;
3113
3114         rc = is_bnxt_in_error(bp);
3115         if (rc)
3116                 return rc;
3117
3118         return bnxt_hwrm_port_led_cfg(bp, false);
3119 }
3120
3121 static uint32_t
3122 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3123 {
3124         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
3125         struct bnxt_cp_ring_info *cpr;
3126         uint32_t desc = 0, raw_cons;
3127         struct bnxt_rx_queue *rxq;
3128         struct rx_pkt_cmpl *rxcmp;
3129         int rc;
3130
3131         rc = is_bnxt_in_error(bp);
3132         if (rc)
3133                 return rc;
3134
3135         rxq = dev->data->rx_queues[rx_queue_id];
3136         cpr = rxq->cp_ring;
3137         raw_cons = cpr->cp_raw_cons;
3138
3139         while (1) {
3140                 uint32_t agg_cnt, cons, cmpl_type;
3141
3142                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3143                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3144
3145                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3146                         break;
3147
3148                 cmpl_type = CMP_TYPE(rxcmp);
3149
3150                 switch (cmpl_type) {
3151                 case CMPL_BASE_TYPE_RX_L2:
3152                 case CMPL_BASE_TYPE_RX_L2_V2:
3153                         agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3154                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3155                         desc++;
3156                         break;
3157
3158                 case CMPL_BASE_TYPE_RX_TPA_END:
3159                         if (BNXT_CHIP_P5(rxq->bp)) {
3160                                 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3161
3162                                 p5_tpa_end = (void *)rxcmp;
3163                                 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3164                         } else {
3165                                 struct rx_tpa_end_cmpl *tpa_end;
3166
3167                                 tpa_end = (void *)rxcmp;
3168                                 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3169                         }
3170
3171                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3172                         desc++;
3173                         break;
3174
3175                 default:
3176                         raw_cons += CMP_LEN(cmpl_type);
3177                 }
3178         }
3179
3180         return desc;
3181 }
3182
3183 static int
3184 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
3185 {
3186         struct bnxt_rx_queue *rxq = rx_queue;
3187         struct bnxt_cp_ring_info *cpr;
3188         struct bnxt_rx_ring_info *rxr;
3189         uint32_t desc, raw_cons;
3190         struct bnxt *bp = rxq->bp;
3191         struct rx_pkt_cmpl *rxcmp;
3192         int rc;
3193
3194         rc = is_bnxt_in_error(bp);
3195         if (rc)
3196                 return rc;
3197
3198         if (offset >= rxq->nb_rx_desc)
3199                 return -EINVAL;
3200
3201         rxr = rxq->rx_ring;
3202         cpr = rxq->cp_ring;
3203
3204         /*
3205          * For the vector receive case, the completion at the requested
3206          * offset can be indexed directly.
3207          */
3208 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
3209         if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) {
3210                 struct rx_pkt_cmpl *rxcmp;
3211                 uint32_t cons;
3212
3213                 /* Check status of completion descriptor. */
3214                 raw_cons = cpr->cp_raw_cons +
3215                            offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2);
3216                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3217                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3218
3219                 if (CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3220                         return RTE_ETH_RX_DESC_DONE;
3221
3222                 /* Check whether rx desc has an mbuf attached. */
3223                 cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2);
3224                 if (cons >= rxq->rxrearm_start &&
3225                     cons < rxq->rxrearm_start + rxq->rxrearm_nb) {
3226                         return RTE_ETH_RX_DESC_UNAVAIL;
3227                 }
3228
3229                 return RTE_ETH_RX_DESC_AVAIL;
3230         }
3231 #endif
3232
3233         /*
3234          * For the non-vector receive case, scan the completion ring to
3235          * locate the completion descriptor for the requested offset.
3236          */
3237         raw_cons = cpr->cp_raw_cons;
3238         desc = 0;
3239         while (1) {
3240                 uint32_t agg_cnt, cons, cmpl_type;
3241
3242                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3243                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3244
3245                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3246                         break;
3247
3248                 cmpl_type = CMP_TYPE(rxcmp);
3249
3250                 switch (cmpl_type) {
3251                 case CMPL_BASE_TYPE_RX_L2:
3252                 case CMPL_BASE_TYPE_RX_L2_V2:
3253                         if (desc == offset) {
3254                                 cons = rxcmp->opaque;
3255                                 if (rxr->rx_buf_ring[cons])
3256                                         return RTE_ETH_RX_DESC_DONE;
3257                                 else
3258                                         return RTE_ETH_RX_DESC_UNAVAIL;
3259                         }
3260                         agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3261                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3262                         desc++;
3263                         break;
3264
3265                 case CMPL_BASE_TYPE_RX_TPA_END:
3266                         if (desc == offset)
3267                                 return RTE_ETH_RX_DESC_DONE;
3268
3269                         if (BNXT_CHIP_P5(rxq->bp)) {
3270                                 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3271
3272                                 p5_tpa_end = (void *)rxcmp;
3273                                 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3274                         } else {
3275                                 struct rx_tpa_end_cmpl *tpa_end;
3276
3277                                 tpa_end = (void *)rxcmp;
3278                                 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3279                         }
3280
3281                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3282                         desc++;
3283                         break;
3284
3285                 default:
3286                         raw_cons += CMP_LEN(cmpl_type);
3287                 }
3288         }
3289
3290         return RTE_ETH_RX_DESC_AVAIL;
3291 }
3292
3293 static int
3294 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
3295 {
3296         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
3297         struct bnxt_tx_ring_info *txr;
3298         struct bnxt_cp_ring_info *cpr;
3299         struct rte_mbuf **tx_buf;
3300         struct tx_pkt_cmpl *txcmp;
3301         uint32_t cons, cp_cons;
3302         int rc;
3303
3304         if (!txq)
3305                 return -EINVAL;
3306
3307         rc = is_bnxt_in_error(txq->bp);
3308         if (rc)
3309                 return rc;
3310
3311         cpr = txq->cp_ring;
3312         txr = txq->tx_ring;
3313
3314         if (offset >= txq->nb_tx_desc)
3315                 return -EINVAL;
3316
3317         cons = RING_CMP(cpr->cp_ring_struct, offset);
3318         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3319         cp_cons = cpr->cp_raw_cons;
3320
3321         if (cons > cp_cons) {
3322                 if (CMPL_VALID(txcmp, cpr->valid))
3323                         return RTE_ETH_TX_DESC_UNAVAIL;
3324         } else {
3325                 if (CMPL_VALID(txcmp, !cpr->valid))
3326                         return RTE_ETH_TX_DESC_UNAVAIL;
3327         }
3328         tx_buf = &txr->tx_buf_ring[cons];
3329         if (*tx_buf == NULL)
3330                 return RTE_ETH_TX_DESC_DONE;
3331
3332         return RTE_ETH_TX_DESC_FULL;
3333 }
3334
3335 int
3336 bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
3337                      const struct rte_flow_ops **ops)
3338 {
3339         struct bnxt *bp = dev->data->dev_private;
3340         int ret = 0;
3341
3342         if (!bp)
3343                 return -EIO;
3344
3345         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3346                 struct bnxt_representor *vfr = dev->data->dev_private;
3347                 bp = vfr->parent_dev->data->dev_private;
3348                 /* parent is deleted while children are still valid */
3349                 if (!bp) {
3350                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error\n",
3351                                     dev->data->port_id);
3352                         return -EIO;
3353                 }
3354         }
3355
3356         ret = is_bnxt_in_error(bp);
3357         if (ret)
3358                 return ret;
3359
3360         /* PMD supports thread-safe flow operations.  rte_flow API
3361          * functions can avoid mutex for multi-thread safety.
3362          */
3363         dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3364
3365         if (BNXT_TRUFLOW_EN(bp))
3366                 *ops = &bnxt_ulp_rte_flow_ops;
3367         else
3368                 *ops = &bnxt_flow_ops;
3369
3370         return ret;
3371 }
3372
3373 static const uint32_t *
3374 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3375 {
3376         static const uint32_t ptypes[] = {
3377                 RTE_PTYPE_L2_ETHER_VLAN,
3378                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3379                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3380                 RTE_PTYPE_L4_ICMP,
3381                 RTE_PTYPE_L4_TCP,
3382                 RTE_PTYPE_L4_UDP,
3383                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3384                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3385                 RTE_PTYPE_INNER_L4_ICMP,
3386                 RTE_PTYPE_INNER_L4_TCP,
3387                 RTE_PTYPE_INNER_L4_UDP,
3388                 RTE_PTYPE_UNKNOWN
3389         };
3390
3391         if (!dev->rx_pkt_burst)
3392                 return NULL;
3393
3394         return ptypes;
3395 }
3396
3397 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3398                          int reg_win)
3399 {
3400         uint32_t reg_base = *reg_arr & 0xfffff000;
3401         uint32_t win_off;
3402         int i;
3403
3404         for (i = 0; i < count; i++) {
3405                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3406                         return -ERANGE;
3407         }
3408         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3409         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3410         return 0;
3411 }
3412
3413 static int bnxt_map_ptp_regs(struct bnxt *bp)
3414 {
3415         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3416         uint32_t *reg_arr;
3417         int rc, i;
3418
3419         reg_arr = ptp->rx_regs;
3420         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3421         if (rc)
3422                 return rc;
3423
3424         reg_arr = ptp->tx_regs;
3425         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3426         if (rc)
3427                 return rc;
3428
3429         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3430                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3431
3432         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3433                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3434
3435         return 0;
3436 }
3437
3438 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3439 {
3440         rte_write32(0, (uint8_t *)bp->bar0 +
3441                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3442         rte_write32(0, (uint8_t *)bp->bar0 +
3443                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3444 }
3445
3446 static uint64_t bnxt_cc_read(struct bnxt *bp)
3447 {
3448         uint64_t ns;
3449
3450         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3451                               BNXT_GRCPF_REG_SYNC_TIME));
3452         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3453                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3454         return ns;
3455 }
3456
3457 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3458 {
3459         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3460         uint32_t fifo;
3461
3462         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3463                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3464         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3465                 return -EAGAIN;
3466
3467         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3468                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3469         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3470                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3471         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3472                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3473         rte_read32((uint8_t *)bp->bar0 + ptp->tx_mapped_regs[BNXT_PTP_TX_SEQ]);
3474
3475         return 0;
3476 }
3477
3478 static int bnxt_clr_rx_ts(struct bnxt *bp, uint64_t *last_ts)
3479 {
3480         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3481         struct bnxt_pf_info *pf = bp->pf;
3482         uint16_t port_id;
3483         int i = 0;
3484         uint32_t fifo;
3485
3486         if (!ptp || (bp->flags & BNXT_FLAG_CHIP_P5))
3487                 return -EINVAL;
3488
3489         port_id = pf->port_id;
3490         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3491                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3492         while ((fifo & BNXT_PTP_RX_FIFO_PENDING) && (i < BNXT_PTP_RX_PND_CNT)) {
3493                 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3494                             ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3495                 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3496                                         ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3497                 *last_ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3498                                         ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3499                 *last_ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3500                                         ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3501                 i++;
3502         }
3503
3504         if (i >= BNXT_PTP_RX_PND_CNT)
3505                 return -EBUSY;
3506
3507         return 0;
3508 }
3509
3510 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3511 {
3512         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3513         struct bnxt_pf_info *pf = bp->pf;
3514         uint16_t port_id;
3515         uint32_t fifo;
3516
3517         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3518                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3519         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3520                 return -EAGAIN;
3521
3522         port_id = pf->port_id;
3523         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3524                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3525
3526         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3527                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3528         if (fifo & BNXT_PTP_RX_FIFO_PENDING)
3529                 return bnxt_clr_rx_ts(bp, ts);
3530
3531         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3532                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3533         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3534                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3535
3536         return 0;
3537 }
3538
3539 static int
3540 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3541 {
3542         uint64_t ns;
3543         struct bnxt *bp = dev->data->dev_private;
3544         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3545
3546         if (!ptp)
3547                 return -ENOTSUP;
3548
3549         ns = rte_timespec_to_ns(ts);
3550         /* Set the timecounters to a new value. */
3551         ptp->tc.nsec = ns;
3552         ptp->tx_tstamp_tc.nsec = ns;
3553         ptp->rx_tstamp_tc.nsec = ns;
3554
3555         return 0;
3556 }
3557
3558 static int
3559 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3560 {
3561         struct bnxt *bp = dev->data->dev_private;
3562         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3563         uint64_t ns, systime_cycles = 0;
3564         int rc = 0;
3565
3566         if (!ptp)
3567                 return -ENOTSUP;
3568
3569         if (BNXT_CHIP_P5(bp))
3570                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3571                                              &systime_cycles);
3572         else
3573                 systime_cycles = bnxt_cc_read(bp);
3574
3575         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3576         *ts = rte_ns_to_timespec(ns);
3577
3578         return rc;
3579 }
3580 static int
3581 bnxt_timesync_enable(struct rte_eth_dev *dev)
3582 {
3583         struct bnxt *bp = dev->data->dev_private;
3584         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3585         uint32_t shift = 0;
3586         int rc;
3587
3588         if (!ptp)
3589                 return -ENOTSUP;
3590
3591         ptp->rx_filter = 1;
3592         ptp->tx_tstamp_en = 1;
3593         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3594
3595         rc = bnxt_hwrm_ptp_cfg(bp);
3596         if (rc)
3597                 return rc;
3598
3599         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3600         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3601         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3602
3603         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3604         ptp->tc.cc_shift = shift;
3605         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3606
3607         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3608         ptp->rx_tstamp_tc.cc_shift = shift;
3609         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3610
3611         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3612         ptp->tx_tstamp_tc.cc_shift = shift;
3613         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3614
3615         if (!BNXT_CHIP_P5(bp))
3616                 bnxt_map_ptp_regs(bp);
3617         else
3618                 rc = bnxt_ptp_start(bp);
3619
3620         return rc;
3621 }
3622
3623 static int
3624 bnxt_timesync_disable(struct rte_eth_dev *dev)
3625 {
3626         struct bnxt *bp = dev->data->dev_private;
3627         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3628
3629         if (!ptp)
3630                 return -ENOTSUP;
3631
3632         ptp->rx_filter = 0;
3633         ptp->tx_tstamp_en = 0;
3634         ptp->rxctl = 0;
3635
3636         bnxt_hwrm_ptp_cfg(bp);
3637
3638         if (!BNXT_CHIP_P5(bp))
3639                 bnxt_unmap_ptp_regs(bp);
3640         else
3641                 bnxt_ptp_stop(bp);
3642
3643         return 0;
3644 }
3645
3646 static int
3647 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3648                                  struct timespec *timestamp,
3649                                  uint32_t flags __rte_unused)
3650 {
3651         struct bnxt *bp = dev->data->dev_private;
3652         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3653         uint64_t rx_tstamp_cycles = 0;
3654         uint64_t ns;
3655
3656         if (!ptp)
3657                 return -ENOTSUP;
3658
3659         if (BNXT_CHIP_P5(bp))
3660                 rx_tstamp_cycles = ptp->rx_timestamp;
3661         else
3662                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3663
3664         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3665         *timestamp = rte_ns_to_timespec(ns);
3666         return  0;
3667 }
3668
3669 static int
3670 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3671                                  struct timespec *timestamp)
3672 {
3673         struct bnxt *bp = dev->data->dev_private;
3674         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3675         uint64_t tx_tstamp_cycles = 0;
3676         uint64_t ns;
3677         int rc = 0;
3678
3679         if (!ptp)
3680                 return -ENOTSUP;
3681
3682         if (BNXT_CHIP_P5(bp))
3683                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3684                                              &tx_tstamp_cycles);
3685         else
3686                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3687
3688         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3689         *timestamp = rte_ns_to_timespec(ns);
3690
3691         return rc;
3692 }
3693
3694 static int
3695 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3696 {
3697         struct bnxt *bp = dev->data->dev_private;
3698         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3699
3700         if (!ptp)
3701                 return -ENOTSUP;
3702
3703         ptp->tc.nsec += delta;
3704         ptp->tx_tstamp_tc.nsec += delta;
3705         ptp->rx_tstamp_tc.nsec += delta;
3706
3707         return 0;
3708 }
3709
3710 static int
3711 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3712 {
3713         struct bnxt *bp = dev->data->dev_private;
3714         int rc;
3715         uint32_t dir_entries;
3716         uint32_t entry_length;
3717
3718         rc = is_bnxt_in_error(bp);
3719         if (rc)
3720                 return rc;
3721
3722         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3723                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3724                     bp->pdev->addr.devid, bp->pdev->addr.function);
3725
3726         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3727         if (rc != 0)
3728                 return rc;
3729
3730         return dir_entries * entry_length;
3731 }
3732
3733 static int
3734 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3735                 struct rte_dev_eeprom_info *in_eeprom)
3736 {
3737         struct bnxt *bp = dev->data->dev_private;
3738         uint32_t index;
3739         uint32_t offset;
3740         int rc;
3741
3742         rc = is_bnxt_in_error(bp);
3743         if (rc)
3744                 return rc;
3745
3746         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3747                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3748                     bp->pdev->addr.devid, bp->pdev->addr.function,
3749                     in_eeprom->offset, in_eeprom->length);
3750
3751         if (in_eeprom->offset == 0) /* special offset value to get directory */
3752                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3753                                                 in_eeprom->data);
3754
3755         index = in_eeprom->offset >> 24;
3756         offset = in_eeprom->offset & 0xffffff;
3757
3758         if (index != 0)
3759                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3760                                            in_eeprom->length, in_eeprom->data);
3761
3762         return 0;
3763 }
3764
3765 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3766 {
3767         switch (dir_type) {
3768         case BNX_DIR_TYPE_CHIMP_PATCH:
3769         case BNX_DIR_TYPE_BOOTCODE:
3770         case BNX_DIR_TYPE_BOOTCODE_2:
3771         case BNX_DIR_TYPE_APE_FW:
3772         case BNX_DIR_TYPE_APE_PATCH:
3773         case BNX_DIR_TYPE_KONG_FW:
3774         case BNX_DIR_TYPE_KONG_PATCH:
3775         case BNX_DIR_TYPE_BONO_FW:
3776         case BNX_DIR_TYPE_BONO_PATCH:
3777                 /* FALLTHROUGH */
3778                 return true;
3779         }
3780
3781         return false;
3782 }
3783
3784 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3785 {
3786         switch (dir_type) {
3787         case BNX_DIR_TYPE_AVS:
3788         case BNX_DIR_TYPE_EXP_ROM_MBA:
3789         case BNX_DIR_TYPE_PCIE:
3790         case BNX_DIR_TYPE_TSCF_UCODE:
3791         case BNX_DIR_TYPE_EXT_PHY:
3792         case BNX_DIR_TYPE_CCM:
3793         case BNX_DIR_TYPE_ISCSI_BOOT:
3794         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3795         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3796                 /* FALLTHROUGH */
3797                 return true;
3798         }
3799
3800         return false;
3801 }
3802
3803 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3804 {
3805         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3806                 bnxt_dir_type_is_other_exec_format(dir_type);
3807 }
3808
3809 static int
3810 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3811                 struct rte_dev_eeprom_info *in_eeprom)
3812 {
3813         struct bnxt *bp = dev->data->dev_private;
3814         uint8_t index, dir_op;
3815         uint16_t type, ext, ordinal, attr;
3816         int rc;
3817
3818         rc = is_bnxt_in_error(bp);
3819         if (rc)
3820                 return rc;
3821
3822         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3823                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3824                     bp->pdev->addr.devid, bp->pdev->addr.function,
3825                     in_eeprom->offset, in_eeprom->length);
3826
3827         if (!BNXT_PF(bp)) {
3828                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3829                 return -EINVAL;
3830         }
3831
3832         type = in_eeprom->magic >> 16;
3833
3834         if (type == 0xffff) { /* special value for directory operations */
3835                 index = in_eeprom->magic & 0xff;
3836                 dir_op = in_eeprom->magic >> 8;
3837                 if (index == 0)
3838                         return -EINVAL;
3839                 switch (dir_op) {
3840                 case 0x0e: /* erase */
3841                         if (in_eeprom->offset != ~in_eeprom->magic)
3842                                 return -EINVAL;
3843                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3844                 default:
3845                         return -EINVAL;
3846                 }
3847         }
3848
3849         /* Create or re-write an NVM item: */
3850         if (bnxt_dir_type_is_executable(type) == true)
3851                 return -EOPNOTSUPP;
3852         ext = in_eeprom->magic & 0xffff;
3853         ordinal = in_eeprom->offset >> 16;
3854         attr = in_eeprom->offset & 0xffff;
3855
3856         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3857                                      in_eeprom->data, in_eeprom->length);
3858 }
3859
3860 static int bnxt_get_module_info(struct rte_eth_dev *dev,
3861                                 struct rte_eth_dev_module_info *modinfo)
3862 {
3863         uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1];
3864         struct bnxt *bp = dev->data->dev_private;
3865         int rc;
3866
3867         /* No point in going further if phy status indicates
3868          * module is not inserted or if it is powered down or
3869          * if it is of type 10GBase-T
3870          */
3871         if (bp->link_info->module_status >
3872             HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG) {
3873                 PMD_DRV_LOG(NOTICE, "Port %u : Module is not inserted or is powered down\n",
3874                             dev->data->port_id);
3875                 return -ENOTSUP;
3876         }
3877
3878         /* This feature is not supported in older firmware versions */
3879         if (bp->hwrm_spec_code < 0x10202) {
3880                 PMD_DRV_LOG(NOTICE, "Port %u : Feature is not supported in older firmware\n",
3881                             dev->data->port_id);
3882                 return -ENOTSUP;
3883         }
3884
3885         rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
3886                                                    SFF_DIAG_SUPPORT_OFFSET + 1,
3887                                                    module_info);
3888
3889         if (rc)
3890                 return rc;
3891
3892         switch (module_info[0]) {
3893         case SFF_MODULE_ID_SFP:
3894                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
3895                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
3896                 if (module_info[SFF_DIAG_SUPPORT_OFFSET] == 0)
3897                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN;
3898                 break;
3899         case SFF_MODULE_ID_QSFP:
3900         case SFF_MODULE_ID_QSFP_PLUS:
3901                 modinfo->type = RTE_ETH_MODULE_SFF_8436;
3902                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN;
3903                 break;
3904         case SFF_MODULE_ID_QSFP28:
3905                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
3906                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
3907                 if (module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK)
3908                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_LEN;
3909                 break;
3910         default:
3911                 PMD_DRV_LOG(NOTICE, "Port %u : Unsupported module\n", dev->data->port_id);
3912                 return -ENOTSUP;
3913         }
3914
3915         PMD_DRV_LOG(INFO, "Port %u : modinfo->type = %d modinfo->eeprom_len = %d\n",
3916                     dev->data->port_id, modinfo->type, modinfo->eeprom_len);
3917
3918         return 0;
3919 }
3920
3921 static int bnxt_get_module_eeprom(struct rte_eth_dev *dev,
3922                                   struct rte_dev_eeprom_info *info)
3923 {
3924         uint8_t pg_addr[5] = { I2C_DEV_ADDR_A0, I2C_DEV_ADDR_A0 };
3925         uint32_t offset = info->offset, length = info->length;
3926         uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1];
3927         struct bnxt *bp = dev->data->dev_private;
3928         uint8_t *data = info->data;
3929         uint8_t page = offset >> 7;
3930         uint8_t max_pages = 2;
3931         uint8_t opt_pages;
3932         int rc;
3933
3934         rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
3935                                                    SFF_DIAG_SUPPORT_OFFSET + 1,
3936                                                    module_info);
3937         if (rc)
3938                 return rc;
3939
3940         switch (module_info[0]) {
3941         case SFF_MODULE_ID_SFP:
3942                 module_info[SFF_DIAG_SUPPORT_OFFSET] = 0;
3943                 if (module_info[SFF_DIAG_SUPPORT_OFFSET]) {
3944                         pg_addr[2] = I2C_DEV_ADDR_A2;
3945                         pg_addr[3] = I2C_DEV_ADDR_A2;
3946                         max_pages = 4;
3947                 }
3948                 break;
3949         case SFF_MODULE_ID_QSFP28:
3950                 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0,
3951                                                            SFF8636_OPT_PAGES_OFFSET,
3952                                                            1, &opt_pages);
3953                 if (rc)
3954                         return rc;
3955
3956                 if (opt_pages & SFF8636_PAGE1_MASK) {
3957                         pg_addr[2] = I2C_DEV_ADDR_A0;
3958                         max_pages = 3;
3959                 }
3960                 if (opt_pages & SFF8636_PAGE2_MASK) {
3961                         pg_addr[3] = I2C_DEV_ADDR_A0;
3962                         max_pages = 4;
3963                 }
3964                 if (~module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK) {
3965                         pg_addr[4] = I2C_DEV_ADDR_A0;
3966                         max_pages = 5;
3967                 }
3968                 break;
3969         default:
3970                 break;
3971         }
3972
3973         memset(data, 0, length);
3974
3975         offset &= 0xff;
3976         while (length && page < max_pages) {
3977                 uint8_t raw_page = page ? page - 1 : 0;
3978                 uint16_t chunk;
3979
3980                 if (pg_addr[page] == I2C_DEV_ADDR_A2)
3981                         raw_page = 0;
3982                 else if (page)
3983                         offset |= 0x80;
3984                 chunk = RTE_MIN(length, 256 - offset);
3985
3986                 if (pg_addr[page]) {
3987                         rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, pg_addr[page],
3988                                                                    raw_page, offset,
3989                                                                    chunk, data);
3990                         if (rc)
3991                                 return rc;
3992                 }
3993
3994                 data += chunk;
3995                 length -= chunk;
3996                 offset = 0;
3997                 page += 1 + (chunk > 128);
3998         }
3999
4000         return length ? -EINVAL : 0;
4001 }
4002
4003 /*
4004  * Initialization
4005  */
4006
4007 static const struct eth_dev_ops bnxt_dev_ops = {
4008         .dev_infos_get = bnxt_dev_info_get_op,
4009         .dev_close = bnxt_dev_close_op,
4010         .dev_configure = bnxt_dev_configure_op,
4011         .dev_start = bnxt_dev_start_op,
4012         .dev_stop = bnxt_dev_stop_op,
4013         .dev_set_link_up = bnxt_dev_set_link_up_op,
4014         .dev_set_link_down = bnxt_dev_set_link_down_op,
4015         .stats_get = bnxt_stats_get_op,
4016         .stats_reset = bnxt_stats_reset_op,
4017         .rx_queue_setup = bnxt_rx_queue_setup_op,
4018         .rx_queue_release = bnxt_rx_queue_release_op,
4019         .tx_queue_setup = bnxt_tx_queue_setup_op,
4020         .tx_queue_release = bnxt_tx_queue_release_op,
4021         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4022         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4023         .reta_update = bnxt_reta_update_op,
4024         .reta_query = bnxt_reta_query_op,
4025         .rss_hash_update = bnxt_rss_hash_update_op,
4026         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4027         .link_update = bnxt_link_update_op,
4028         .promiscuous_enable = bnxt_promiscuous_enable_op,
4029         .promiscuous_disable = bnxt_promiscuous_disable_op,
4030         .allmulticast_enable = bnxt_allmulticast_enable_op,
4031         .allmulticast_disable = bnxt_allmulticast_disable_op,
4032         .mac_addr_add = bnxt_mac_addr_add_op,
4033         .mac_addr_remove = bnxt_mac_addr_remove_op,
4034         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4035         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4036         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4037         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4038         .vlan_filter_set = bnxt_vlan_filter_set_op,
4039         .vlan_offload_set = bnxt_vlan_offload_set_op,
4040         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4041         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4042         .mtu_set = bnxt_mtu_set_op,
4043         .mac_addr_set = bnxt_set_default_mac_addr_op,
4044         .xstats_get = bnxt_dev_xstats_get_op,
4045         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4046         .xstats_reset = bnxt_dev_xstats_reset_op,
4047         .fw_version_get = bnxt_fw_version_get,
4048         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4049         .rxq_info_get = bnxt_rxq_info_get_op,
4050         .txq_info_get = bnxt_txq_info_get_op,
4051         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4052         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4053         .dev_led_on = bnxt_dev_led_on_op,
4054         .dev_led_off = bnxt_dev_led_off_op,
4055         .rx_queue_start = bnxt_rx_queue_start,
4056         .rx_queue_stop = bnxt_rx_queue_stop,
4057         .tx_queue_start = bnxt_tx_queue_start,
4058         .tx_queue_stop = bnxt_tx_queue_stop,
4059         .flow_ops_get = bnxt_flow_ops_get_op,
4060         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4061         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4062         .get_eeprom           = bnxt_get_eeprom_op,
4063         .set_eeprom           = bnxt_set_eeprom_op,
4064         .get_module_info = bnxt_get_module_info,
4065         .get_module_eeprom = bnxt_get_module_eeprom,
4066         .timesync_enable      = bnxt_timesync_enable,
4067         .timesync_disable     = bnxt_timesync_disable,
4068         .timesync_read_time   = bnxt_timesync_read_time,
4069         .timesync_write_time   = bnxt_timesync_write_time,
4070         .timesync_adjust_time = bnxt_timesync_adjust_time,
4071         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4072         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4073 };
4074
4075 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4076 {
4077         uint32_t offset;
4078
4079         /* Only pre-map the reset GRC registers using window 3 */
4080         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4081                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4082
4083         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4084
4085         return offset;
4086 }
4087
4088 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4089 {
4090         struct bnxt_error_recovery_info *info = bp->recovery_info;
4091         uint32_t reg_base = 0xffffffff;
4092         int i;
4093
4094         /* Only pre-map the monitoring GRC registers using window 2 */
4095         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4096                 uint32_t reg = info->status_regs[i];
4097
4098                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4099                         continue;
4100
4101                 if (reg_base == 0xffffffff)
4102                         reg_base = reg & 0xfffff000;
4103                 if ((reg & 0xfffff000) != reg_base)
4104                         return -ERANGE;
4105
4106                 /* Use mask 0xffc as the Lower 2 bits indicates
4107                  * address space location
4108                  */
4109                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4110                                                 (reg & 0xffc);
4111         }
4112
4113         if (reg_base == 0xffffffff)
4114                 return 0;
4115
4116         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4117                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4118
4119         return 0;
4120 }
4121
4122 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4123 {
4124         struct bnxt_error_recovery_info *info = bp->recovery_info;
4125         uint32_t delay = info->delay_after_reset[index];
4126         uint32_t val = info->reset_reg_val[index];
4127         uint32_t reg = info->reset_reg[index];
4128         uint32_t type, offset;
4129         int ret;
4130
4131         type = BNXT_FW_STATUS_REG_TYPE(reg);
4132         offset = BNXT_FW_STATUS_REG_OFF(reg);
4133
4134         switch (type) {
4135         case BNXT_FW_STATUS_REG_TYPE_CFG:
4136                 ret = rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4137                 if (ret < 0) {
4138                         PMD_DRV_LOG(ERR, "Failed to write %#x at PCI offset %#x",
4139                                     val, offset);
4140                         return;
4141                 }
4142                 break;
4143         case BNXT_FW_STATUS_REG_TYPE_GRC:
4144                 offset = bnxt_map_reset_regs(bp, offset);
4145                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4146                 break;
4147         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4148                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4149                 break;
4150         }
4151         /* wait on a specific interval of time until core reset is complete */
4152         if (delay)
4153                 rte_delay_ms(delay);
4154 }
4155
4156 static void bnxt_dev_cleanup(struct bnxt *bp)
4157 {
4158         bp->eth_dev->data->dev_link.link_status = 0;
4159         bp->link_info->link_up = 0;
4160         if (bp->eth_dev->data->dev_started)
4161                 bnxt_dev_stop(bp->eth_dev);
4162
4163         bnxt_uninit_resources(bp, true);
4164 }
4165
4166 static int
4167 bnxt_check_fw_reset_done(struct bnxt *bp)
4168 {
4169         int timeout = bp->fw_reset_max_msecs;
4170         uint16_t val = 0;
4171         int rc;
4172
4173         do {
4174                 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4175                 if (rc < 0) {
4176                         PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4177                         return rc;
4178                 }
4179                 if (val != 0xffff)
4180                         break;
4181                 rte_delay_ms(1);
4182         } while (timeout--);
4183
4184         if (val == 0xffff) {
4185                 PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n");
4186                 return -1;
4187         }
4188
4189         return 0;
4190 }
4191
4192 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4193 {
4194         struct rte_eth_dev *dev = bp->eth_dev;
4195         struct rte_vlan_filter_conf *vfc;
4196         int vidx, vbit, rc;
4197         uint16_t vlan_id;
4198
4199         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4200                 vfc = &dev->data->vlan_filter_conf;
4201                 vidx = vlan_id / 64;
4202                 vbit = vlan_id % 64;
4203
4204                 /* Each bit corresponds to a VLAN id */
4205                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4206                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4207                         if (rc)
4208                                 return rc;
4209                 }
4210         }
4211
4212         return 0;
4213 }
4214
4215 static int bnxt_restore_mac_filters(struct bnxt *bp)
4216 {
4217         struct rte_eth_dev *dev = bp->eth_dev;
4218         struct rte_eth_dev_info dev_info;
4219         struct rte_ether_addr *addr;
4220         uint64_t pool_mask;
4221         uint32_t pool = 0;
4222         uint32_t i;
4223         int rc;
4224
4225         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4226                 return 0;
4227
4228         rc = bnxt_dev_info_get_op(dev, &dev_info);
4229         if (rc)
4230                 return rc;
4231
4232         /* replay MAC address configuration */
4233         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4234                 addr = &dev->data->mac_addrs[i];
4235
4236                 /* skip zero address */
4237                 if (rte_is_zero_ether_addr(addr))
4238                         continue;
4239
4240                 pool = 0;
4241                 pool_mask = dev->data->mac_pool_sel[i];
4242
4243                 do {
4244                         if (pool_mask & 1ULL) {
4245                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4246                                 if (rc)
4247                                         return rc;
4248                         }
4249                         pool_mask >>= 1;
4250                         pool++;
4251                 } while (pool_mask);
4252         }
4253
4254         return 0;
4255 }
4256
4257 static int bnxt_restore_filters(struct bnxt *bp)
4258 {
4259         struct rte_eth_dev *dev = bp->eth_dev;
4260         int ret = 0;
4261
4262         if (dev->data->all_multicast) {
4263                 ret = bnxt_allmulticast_enable_op(dev);
4264                 if (ret)
4265                         return ret;
4266         }
4267         if (dev->data->promiscuous) {
4268                 ret = bnxt_promiscuous_enable_op(dev);
4269                 if (ret)
4270                         return ret;
4271         }
4272
4273         ret = bnxt_restore_mac_filters(bp);
4274         if (ret)
4275                 return ret;
4276
4277         ret = bnxt_restore_vlan_filters(bp);
4278         /* TODO restore other filters as well */
4279         return ret;
4280 }
4281
4282 static int bnxt_check_fw_ready(struct bnxt *bp)
4283 {
4284         int timeout = bp->fw_reset_max_msecs;
4285         int rc = 0;
4286
4287         do {
4288                 rc = bnxt_hwrm_poll_ver_get(bp);
4289                 if (rc == 0)
4290                         break;
4291                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4292                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4293         } while (rc && timeout > 0);
4294
4295         if (rc)
4296                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4297
4298         return rc;
4299 }
4300
4301 static void bnxt_dev_recover(void *arg)
4302 {
4303         struct bnxt *bp = arg;
4304         int rc = 0;
4305
4306         pthread_mutex_lock(&bp->err_recovery_lock);
4307
4308         if (!bp->fw_reset_min_msecs) {
4309                 rc = bnxt_check_fw_reset_done(bp);
4310                 if (rc)
4311                         goto err;
4312         }
4313
4314         /* Clear Error flag so that device re-init should happen */
4315         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4316
4317         rc = bnxt_check_fw_ready(bp);
4318         if (rc)
4319                 goto err;
4320
4321         rc = bnxt_init_resources(bp, true);
4322         if (rc) {
4323                 PMD_DRV_LOG(ERR,
4324                             "Failed to initialize resources after reset\n");
4325                 goto err;
4326         }
4327         /* clear reset flag as the device is initialized now */
4328         bp->flags &= ~BNXT_FLAG_FW_RESET;
4329
4330         rc = bnxt_dev_start_op(bp->eth_dev);
4331         if (rc) {
4332                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4333                 goto err_start;
4334         }
4335
4336         rc = bnxt_restore_filters(bp);
4337         if (rc)
4338                 goto err_start;
4339
4340         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4341         pthread_mutex_unlock(&bp->err_recovery_lock);
4342
4343         return;
4344 err_start:
4345         bnxt_dev_stop(bp->eth_dev);
4346 err:
4347         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4348         bnxt_uninit_resources(bp, false);
4349         pthread_mutex_unlock(&bp->err_recovery_lock);
4350         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4351 }
4352
4353 void bnxt_dev_reset_and_resume(void *arg)
4354 {
4355         struct bnxt *bp = arg;
4356         uint32_t us = US_PER_MS * bp->fw_reset_min_msecs;
4357         uint16_t val = 0;
4358         int rc;
4359
4360         bnxt_dev_cleanup(bp);
4361
4362         bnxt_wait_for_device_shutdown(bp);
4363
4364         /* During some fatal firmware error conditions, the PCI config space
4365          * register 0x2e which normally contains the subsystem ID will become
4366          * 0xffff. This register will revert back to the normal value after
4367          * the chip has completed core reset. If we detect this condition,
4368          * we can poll this config register immediately for the value to revert.
4369          */
4370         if (bp->flags & BNXT_FLAG_FATAL_ERROR) {
4371                 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4372                 if (rc < 0) {
4373                         PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4374                         return;
4375                 }
4376                 if (val == 0xffff) {
4377                         bp->fw_reset_min_msecs = 0;
4378                         us = 1;
4379                 }
4380         }
4381
4382         rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp);
4383         if (rc)
4384                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4385 }
4386
4387 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4388 {
4389         struct bnxt_error_recovery_info *info = bp->recovery_info;
4390         uint32_t reg = info->status_regs[index];
4391         uint32_t type, offset, val = 0;
4392         int ret = 0;
4393
4394         type = BNXT_FW_STATUS_REG_TYPE(reg);
4395         offset = BNXT_FW_STATUS_REG_OFF(reg);
4396
4397         switch (type) {
4398         case BNXT_FW_STATUS_REG_TYPE_CFG:
4399                 ret = rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4400                 if (ret < 0)
4401                         PMD_DRV_LOG(ERR, "Failed to read PCI offset %#x",
4402                                     offset);
4403                 break;
4404         case BNXT_FW_STATUS_REG_TYPE_GRC:
4405                 offset = info->mapped_status_regs[index];
4406                 /* FALLTHROUGH */
4407         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4408                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4409                                        offset));
4410                 break;
4411         }
4412
4413         return val;
4414 }
4415
4416 static int bnxt_fw_reset_all(struct bnxt *bp)
4417 {
4418         struct bnxt_error_recovery_info *info = bp->recovery_info;
4419         uint32_t i;
4420         int rc = 0;
4421
4422         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4423                 /* Reset through master function driver */
4424                 for (i = 0; i < info->reg_array_cnt; i++)
4425                         bnxt_write_fw_reset_reg(bp, i);
4426                 /* Wait for time specified by FW after triggering reset */
4427                 rte_delay_ms(info->master_func_wait_period_after_reset);
4428         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4429                 /* Reset with the help of Kong processor */
4430                 rc = bnxt_hwrm_fw_reset(bp);
4431                 if (rc)
4432                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4433         }
4434
4435         return rc;
4436 }
4437
4438 static void bnxt_fw_reset_cb(void *arg)
4439 {
4440         struct bnxt *bp = arg;
4441         struct bnxt_error_recovery_info *info = bp->recovery_info;
4442         int rc = 0;
4443
4444         /* Only Master function can do FW reset */
4445         if (bnxt_is_master_func(bp) &&
4446             bnxt_is_recovery_enabled(bp)) {
4447                 rc = bnxt_fw_reset_all(bp);
4448                 if (rc) {
4449                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4450                         return;
4451                 }
4452         }
4453
4454         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4455          * EXCEPTION_FATAL_ASYNC event to all the functions
4456          * (including MASTER FUNC). After receiving this Async, all the active
4457          * drivers should treat this case as FW initiated recovery
4458          */
4459         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4460                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4461                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4462
4463                 /* To recover from error */
4464                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4465                                   (void *)bp);
4466         }
4467 }
4468
4469 /* Driver should poll FW heartbeat, reset_counter with the frequency
4470  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4471  * When the driver detects heartbeat stop or change in reset_counter,
4472  * it has to trigger a reset to recover from the error condition.
4473  * A “master PF” is the function who will have the privilege to
4474  * initiate the chimp reset. The master PF will be elected by the
4475  * firmware and will be notified through async message.
4476  */
4477 static void bnxt_check_fw_health(void *arg)
4478 {
4479         struct bnxt *bp = arg;
4480         struct bnxt_error_recovery_info *info = bp->recovery_info;
4481         uint32_t val = 0, wait_msec;
4482
4483         if (!info || !bnxt_is_recovery_enabled(bp) ||
4484             is_bnxt_in_error(bp))
4485                 return;
4486
4487         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4488         if (val == info->last_heart_beat)
4489                 goto reset;
4490
4491         info->last_heart_beat = val;
4492
4493         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4494         if (val != info->last_reset_counter)
4495                 goto reset;
4496
4497         info->last_reset_counter = val;
4498
4499         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4500                           bnxt_check_fw_health, (void *)bp);
4501
4502         return;
4503 reset:
4504         /* Stop DMA to/from device */
4505         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4506         bp->flags |= BNXT_FLAG_FW_RESET;
4507
4508         bnxt_stop_rxtx(bp);
4509
4510         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4511
4512         if (bnxt_is_master_func(bp))
4513                 wait_msec = info->master_func_wait_period;
4514         else
4515                 wait_msec = info->normal_func_wait_period;
4516
4517         rte_eal_alarm_set(US_PER_MS * wait_msec,
4518                           bnxt_fw_reset_cb, (void *)bp);
4519 }
4520
4521 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4522 {
4523         uint32_t polling_freq;
4524
4525         pthread_mutex_lock(&bp->health_check_lock);
4526
4527         if (!bnxt_is_recovery_enabled(bp))
4528                 goto done;
4529
4530         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4531                 goto done;
4532
4533         polling_freq = bp->recovery_info->driver_polling_freq;
4534
4535         rte_eal_alarm_set(US_PER_MS * polling_freq,
4536                           bnxt_check_fw_health, (void *)bp);
4537         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4538
4539 done:
4540         pthread_mutex_unlock(&bp->health_check_lock);
4541 }
4542
4543 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4544 {
4545         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4546         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4547 }
4548
4549 static bool bnxt_vf_pciid(uint16_t device_id)
4550 {
4551         switch (device_id) {
4552         case BROADCOM_DEV_ID_57304_VF:
4553         case BROADCOM_DEV_ID_57406_VF:
4554         case BROADCOM_DEV_ID_5731X_VF:
4555         case BROADCOM_DEV_ID_5741X_VF:
4556         case BROADCOM_DEV_ID_57414_VF:
4557         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4558         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4559         case BROADCOM_DEV_ID_58802_VF:
4560         case BROADCOM_DEV_ID_57500_VF1:
4561         case BROADCOM_DEV_ID_57500_VF2:
4562         case BROADCOM_DEV_ID_58818_VF:
4563                 /* FALLTHROUGH */
4564                 return true;
4565         default:
4566                 return false;
4567         }
4568 }
4569
4570 /* Phase 5 device */
4571 static bool bnxt_p5_device(uint16_t device_id)
4572 {
4573         switch (device_id) {
4574         case BROADCOM_DEV_ID_57508:
4575         case BROADCOM_DEV_ID_57504:
4576         case BROADCOM_DEV_ID_57502:
4577         case BROADCOM_DEV_ID_57508_MF1:
4578         case BROADCOM_DEV_ID_57504_MF1:
4579         case BROADCOM_DEV_ID_57502_MF1:
4580         case BROADCOM_DEV_ID_57508_MF2:
4581         case BROADCOM_DEV_ID_57504_MF2:
4582         case BROADCOM_DEV_ID_57502_MF2:
4583         case BROADCOM_DEV_ID_57500_VF1:
4584         case BROADCOM_DEV_ID_57500_VF2:
4585         case BROADCOM_DEV_ID_58812:
4586         case BROADCOM_DEV_ID_58814:
4587         case BROADCOM_DEV_ID_58818:
4588         case BROADCOM_DEV_ID_58818_VF:
4589                 /* FALLTHROUGH */
4590                 return true;
4591         default:
4592                 return false;
4593         }
4594 }
4595
4596 bool bnxt_stratus_device(struct bnxt *bp)
4597 {
4598         uint16_t device_id = bp->pdev->id.device_id;
4599
4600         switch (device_id) {
4601         case BROADCOM_DEV_ID_STRATUS_NIC:
4602         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4603         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4604                 /* FALLTHROUGH */
4605                 return true;
4606         default:
4607                 return false;
4608         }
4609 }
4610
4611 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev)
4612 {
4613         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4614         struct bnxt *bp = eth_dev->data->dev_private;
4615
4616         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4617         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4618         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4619         if (!bp->bar0 || !bp->doorbell_base) {
4620                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4621                 return -ENODEV;
4622         }
4623
4624         bp->eth_dev = eth_dev;
4625         bp->pdev = pci_dev;
4626
4627         return 0;
4628 }
4629
4630 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4631                                   struct bnxt_ctx_pg_info *ctx_pg,
4632                                   uint32_t mem_size,
4633                                   const char *suffix,
4634                                   uint16_t idx)
4635 {
4636         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4637         const struct rte_memzone *mz = NULL;
4638         char mz_name[RTE_MEMZONE_NAMESIZE];
4639         rte_iova_t mz_phys_addr;
4640         uint64_t valid_bits = 0;
4641         uint32_t sz;
4642         int i;
4643
4644         if (!mem_size)
4645                 return 0;
4646
4647         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4648                          BNXT_PAGE_SIZE;
4649         rmem->page_size = BNXT_PAGE_SIZE;
4650         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4651         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4652         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4653
4654         valid_bits = PTU_PTE_VALID;
4655
4656         if (rmem->nr_pages > 1) {
4657                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4658                          "bnxt_ctx_pg_tbl%s_%x_%d",
4659                          suffix, idx, bp->eth_dev->data->port_id);
4660                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4661                 mz = rte_memzone_lookup(mz_name);
4662                 if (!mz) {
4663                         mz = rte_memzone_reserve_aligned(mz_name,
4664                                                 rmem->nr_pages * 8,
4665                                                 SOCKET_ID_ANY,
4666                                                 RTE_MEMZONE_2MB |
4667                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4668                                                 RTE_MEMZONE_IOVA_CONTIG,
4669                                                 BNXT_PAGE_SIZE);
4670                         if (mz == NULL)
4671                                 return -ENOMEM;
4672                 }
4673
4674                 memset(mz->addr, 0, mz->len);
4675                 mz_phys_addr = mz->iova;
4676
4677                 rmem->pg_tbl = mz->addr;
4678                 rmem->pg_tbl_map = mz_phys_addr;
4679                 rmem->pg_tbl_mz = mz;
4680         }
4681
4682         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4683                  suffix, idx, bp->eth_dev->data->port_id);
4684         mz = rte_memzone_lookup(mz_name);
4685         if (!mz) {
4686                 mz = rte_memzone_reserve_aligned(mz_name,
4687                                                  mem_size,
4688                                                  SOCKET_ID_ANY,
4689                                                  RTE_MEMZONE_1GB |
4690                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4691                                                  RTE_MEMZONE_IOVA_CONTIG,
4692                                                  BNXT_PAGE_SIZE);
4693                 if (mz == NULL)
4694                         return -ENOMEM;
4695         }
4696
4697         memset(mz->addr, 0, mz->len);
4698         mz_phys_addr = mz->iova;
4699
4700         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4701                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4702                 rmem->dma_arr[i] = mz_phys_addr + sz;
4703
4704                 if (rmem->nr_pages > 1) {
4705                         if (i == rmem->nr_pages - 2 &&
4706                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4707                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4708                         else if (i == rmem->nr_pages - 1 &&
4709                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4710                                 valid_bits |= PTU_PTE_LAST;
4711
4712                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4713                                                            valid_bits);
4714                 }
4715         }
4716
4717         rmem->mz = mz;
4718         if (rmem->vmem_size)
4719                 rmem->vmem = (void **)mz->addr;
4720         rmem->dma_arr[0] = mz_phys_addr;
4721         return 0;
4722 }
4723
4724 static void bnxt_free_ctx_mem(struct bnxt *bp)
4725 {
4726         int i;
4727
4728         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4729                 return;
4730
4731         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4732         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4733         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4734         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4735         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4736         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4737         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4738         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4739         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4740         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4741         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4742
4743         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4744                 if (bp->ctx->tqm_mem[i])
4745                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4746         }
4747
4748         rte_free(bp->ctx);
4749         bp->ctx = NULL;
4750 }
4751
4752 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4753
4754 #define min_t(type, x, y) ({                    \
4755         type __min1 = (x);                      \
4756         type __min2 = (y);                      \
4757         __min1 < __min2 ? __min1 : __min2; })
4758
4759 #define max_t(type, x, y) ({                    \
4760         type __max1 = (x);                      \
4761         type __max2 = (y);                      \
4762         __max1 > __max2 ? __max1 : __max2; })
4763
4764 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4765
4766 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4767 {
4768         struct bnxt_ctx_pg_info *ctx_pg;
4769         struct bnxt_ctx_mem_info *ctx;
4770         uint32_t mem_size, ena, entries;
4771         uint32_t entries_sp, min;
4772         int i, rc;
4773
4774         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4775         if (rc) {
4776                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4777                 return rc;
4778         }
4779         ctx = bp->ctx;
4780         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4781                 return 0;
4782
4783         ctx_pg = &ctx->qp_mem;
4784         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4785         if (ctx->qp_entry_size) {
4786                 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4787                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4788                 if (rc)
4789                         return rc;
4790         }
4791
4792         ctx_pg = &ctx->srq_mem;
4793         ctx_pg->entries = ctx->srq_max_l2_entries;
4794         if (ctx->srq_entry_size) {
4795                 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4796                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4797                 if (rc)
4798                         return rc;
4799         }
4800
4801         ctx_pg = &ctx->cq_mem;
4802         ctx_pg->entries = ctx->cq_max_l2_entries;
4803         if (ctx->cq_entry_size) {
4804                 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4805                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4806                 if (rc)
4807                         return rc;
4808         }
4809
4810         ctx_pg = &ctx->vnic_mem;
4811         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4812                 ctx->vnic_max_ring_table_entries;
4813         if (ctx->vnic_entry_size) {
4814                 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4815                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4816                 if (rc)
4817                         return rc;
4818         }
4819
4820         ctx_pg = &ctx->stat_mem;
4821         ctx_pg->entries = ctx->stat_max_entries;
4822         if (ctx->stat_entry_size) {
4823                 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4824                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4825                 if (rc)
4826                         return rc;
4827         }
4828
4829         min = ctx->tqm_min_entries_per_ring;
4830
4831         entries_sp = ctx->qp_max_l2_entries +
4832                      ctx->vnic_max_vnic_entries +
4833                      2 * ctx->qp_min_qp1_entries + min;
4834         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4835
4836         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4837         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4838         entries = clamp_t(uint32_t, entries, min,
4839                           ctx->tqm_max_entries_per_ring);
4840         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4841                 /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7.
4842                  * i > 8 is other ext rings.
4843                  */
4844                 ctx_pg = ctx->tqm_mem[i];
4845                 ctx_pg->entries = i ? entries : entries_sp;
4846                 if (ctx->tqm_entry_size) {
4847                         mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4848                         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size,
4849                                                     "tqm_mem", i);
4850                         if (rc)
4851                                 return rc;
4852                 }
4853                 if (i < BNXT_MAX_TQM_LEGACY_RINGS)
4854                         ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4855                 else
4856                         ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8;
4857         }
4858
4859         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4860         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4861         if (rc)
4862                 PMD_DRV_LOG(ERR,
4863                             "Failed to configure context mem: rc = %d\n", rc);
4864         else
4865                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4866
4867         return rc;
4868 }
4869
4870 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4871 {
4872         struct rte_pci_device *pci_dev = bp->pdev;
4873         char mz_name[RTE_MEMZONE_NAMESIZE];
4874         const struct rte_memzone *mz = NULL;
4875         uint32_t total_alloc_len;
4876         rte_iova_t mz_phys_addr;
4877
4878         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4879                 return 0;
4880
4881         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4882                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4883                  pci_dev->addr.bus, pci_dev->addr.devid,
4884                  pci_dev->addr.function, "rx_port_stats");
4885         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4886         mz = rte_memzone_lookup(mz_name);
4887         total_alloc_len =
4888                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4889                                        sizeof(struct rx_port_stats_ext) + 512);
4890         if (!mz) {
4891                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4892                                          SOCKET_ID_ANY,
4893                                          RTE_MEMZONE_2MB |
4894                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4895                                          RTE_MEMZONE_IOVA_CONTIG);
4896                 if (mz == NULL)
4897                         return -ENOMEM;
4898         }
4899         memset(mz->addr, 0, mz->len);
4900         mz_phys_addr = mz->iova;
4901
4902         bp->rx_mem_zone = (const void *)mz;
4903         bp->hw_rx_port_stats = mz->addr;
4904         bp->hw_rx_port_stats_map = mz_phys_addr;
4905
4906         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4907                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4908                  pci_dev->addr.bus, pci_dev->addr.devid,
4909                  pci_dev->addr.function, "tx_port_stats");
4910         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4911         mz = rte_memzone_lookup(mz_name);
4912         total_alloc_len =
4913                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4914                                        sizeof(struct tx_port_stats_ext) + 512);
4915         if (!mz) {
4916                 mz = rte_memzone_reserve(mz_name,
4917                                          total_alloc_len,
4918                                          SOCKET_ID_ANY,
4919                                          RTE_MEMZONE_2MB |
4920                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4921                                          RTE_MEMZONE_IOVA_CONTIG);
4922                 if (mz == NULL)
4923                         return -ENOMEM;
4924         }
4925         memset(mz->addr, 0, mz->len);
4926         mz_phys_addr = mz->iova;
4927
4928         bp->tx_mem_zone = (const void *)mz;
4929         bp->hw_tx_port_stats = mz->addr;
4930         bp->hw_tx_port_stats_map = mz_phys_addr;
4931         bp->flags |= BNXT_FLAG_PORT_STATS;
4932
4933         /* Display extended statistics if FW supports it */
4934         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4935             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4936             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4937                 return 0;
4938
4939         bp->hw_rx_port_stats_ext = (void *)
4940                 ((uint8_t *)bp->hw_rx_port_stats +
4941                  sizeof(struct rx_port_stats));
4942         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4943                 sizeof(struct rx_port_stats);
4944         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4945
4946         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4947             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4948                 bp->hw_tx_port_stats_ext = (void *)
4949                         ((uint8_t *)bp->hw_tx_port_stats +
4950                          sizeof(struct tx_port_stats));
4951                 bp->hw_tx_port_stats_ext_map =
4952                         bp->hw_tx_port_stats_map +
4953                         sizeof(struct tx_port_stats);
4954                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4955         }
4956
4957         return 0;
4958 }
4959
4960 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4961 {
4962         struct bnxt *bp = eth_dev->data->dev_private;
4963         int rc = 0;
4964
4965         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4966                                                RTE_ETHER_ADDR_LEN *
4967                                                bp->max_l2_ctx,
4968                                                0);
4969         if (eth_dev->data->mac_addrs == NULL) {
4970                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4971                 return -ENOMEM;
4972         }
4973
4974         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4975                 if (BNXT_PF(bp))
4976                         return -EINVAL;
4977
4978                 /* Generate a random MAC address, if none was assigned by PF */
4979                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4980                 bnxt_eth_hw_addr_random(bp->mac_addr);
4981                 PMD_DRV_LOG(INFO,
4982                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4983                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4984                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4985
4986                 rc = bnxt_hwrm_set_mac(bp);
4987                 if (rc)
4988                         return rc;
4989         }
4990
4991         /* Copy the permanent MAC from the FUNC_QCAPS response */
4992         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4993
4994         return rc;
4995 }
4996
4997 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4998 {
4999         int rc = 0;
5000
5001         /* MAC is already configured in FW */
5002         if (BNXT_HAS_DFLT_MAC_SET(bp))
5003                 return 0;
5004
5005         /* Restore the old MAC configured */
5006         rc = bnxt_hwrm_set_mac(bp);
5007         if (rc)
5008                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5009
5010         return rc;
5011 }
5012
5013 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5014 {
5015         if (!BNXT_PF(bp))
5016                 return;
5017
5018         memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5019
5020         if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
5021                 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
5022         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
5023         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
5024         BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
5025         BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
5026 }
5027
5028 struct bnxt *
5029 bnxt_get_bp(uint16_t port)
5030 {
5031         struct bnxt *bp;
5032         struct rte_eth_dev *dev;
5033
5034         if (!rte_eth_dev_is_valid_port(port)) {
5035                 PMD_DRV_LOG(ERR, "Invalid port %d\n", port);
5036                 return NULL;
5037         }
5038
5039         dev = &rte_eth_devices[port];
5040         if (!is_bnxt_supported(dev)) {
5041                 PMD_DRV_LOG(ERR, "Device %d not supported\n", port);
5042                 return NULL;
5043         }
5044
5045         bp = (struct bnxt *)dev->data->dev_private;
5046         if (!BNXT_TRUFLOW_EN(bp)) {
5047                 PMD_DRV_LOG(ERR, "TRUFLOW not enabled\n");
5048                 return NULL;
5049         }
5050
5051         return bp;
5052 }
5053
5054 uint16_t
5055 bnxt_get_svif(uint16_t port_id, bool func_svif,
5056               enum bnxt_ulp_intf_type type)
5057 {
5058         struct rte_eth_dev *eth_dev;
5059         struct bnxt *bp;
5060
5061         eth_dev = &rte_eth_devices[port_id];
5062         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5063                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5064                 if (!vfr)
5065                         return 0;
5066
5067                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5068                         return vfr->svif;
5069
5070                 eth_dev = vfr->parent_dev;
5071         }
5072
5073         bp = eth_dev->data->dev_private;
5074
5075         return func_svif ? bp->func_svif : bp->port_svif;
5076 }
5077
5078 void
5079 bnxt_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type,
5080                    uint8_t *mac, uint8_t *parent_mac)
5081 {
5082         struct rte_eth_dev *eth_dev;
5083         struct bnxt *bp;
5084
5085         if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF &&
5086             type != BNXT_ULP_INTF_TYPE_PF)
5087                 return;
5088
5089         eth_dev = &rte_eth_devices[port];
5090         bp = eth_dev->data->dev_private;
5091         memcpy(mac, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5092
5093         if (type == BNXT_ULP_INTF_TYPE_TRUSTED_VF)
5094                 memcpy(parent_mac, bp->parent->mac_addr, RTE_ETHER_ADDR_LEN);
5095 }
5096
5097 uint16_t
5098 bnxt_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5099 {
5100         struct rte_eth_dev *eth_dev;
5101         struct bnxt *bp;
5102
5103         if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF)
5104                 return 0;
5105
5106         eth_dev = &rte_eth_devices[port];
5107         bp = eth_dev->data->dev_private;
5108
5109         return bp->parent->vnic;
5110 }
5111 uint16_t
5112 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5113 {
5114         struct rte_eth_dev *eth_dev;
5115         struct bnxt_vnic_info *vnic;
5116         struct bnxt *bp;
5117
5118         eth_dev = &rte_eth_devices[port];
5119         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5120                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5121                 if (!vfr)
5122                         return 0;
5123
5124                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5125                         return vfr->dflt_vnic_id;
5126
5127                 eth_dev = vfr->parent_dev;
5128         }
5129
5130         bp = eth_dev->data->dev_private;
5131
5132         vnic = BNXT_GET_DEFAULT_VNIC(bp);
5133
5134         return vnic->fw_vnic_id;
5135 }
5136
5137 uint16_t
5138 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5139 {
5140         struct rte_eth_dev *eth_dev;
5141         struct bnxt *bp;
5142
5143         eth_dev = &rte_eth_devices[port];
5144         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5145                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5146                 if (!vfr)
5147                         return 0;
5148
5149                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5150                         return vfr->fw_fid;
5151
5152                 eth_dev = vfr->parent_dev;
5153         }
5154
5155         bp = eth_dev->data->dev_private;
5156
5157         return bp->fw_fid;
5158 }
5159
5160 enum bnxt_ulp_intf_type
5161 bnxt_get_interface_type(uint16_t port)
5162 {
5163         struct rte_eth_dev *eth_dev;
5164         struct bnxt *bp;
5165
5166         eth_dev = &rte_eth_devices[port];
5167         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5168                 return BNXT_ULP_INTF_TYPE_VF_REP;
5169
5170         bp = eth_dev->data->dev_private;
5171         if (BNXT_PF(bp))
5172                 return BNXT_ULP_INTF_TYPE_PF;
5173         else if (BNXT_VF_IS_TRUSTED(bp))
5174                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5175         else if (BNXT_VF(bp))
5176                 return BNXT_ULP_INTF_TYPE_VF;
5177
5178         return BNXT_ULP_INTF_TYPE_INVALID;
5179 }
5180
5181 uint16_t
5182 bnxt_get_phy_port_id(uint16_t port_id)
5183 {
5184         struct bnxt_representor *vfr;
5185         struct rte_eth_dev *eth_dev;
5186         struct bnxt *bp;
5187
5188         eth_dev = &rte_eth_devices[port_id];
5189         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5190                 vfr = eth_dev->data->dev_private;
5191                 if (!vfr)
5192                         return 0;
5193
5194                 eth_dev = vfr->parent_dev;
5195         }
5196
5197         bp = eth_dev->data->dev_private;
5198
5199         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5200 }
5201
5202 uint16_t
5203 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5204 {
5205         struct rte_eth_dev *eth_dev;
5206         struct bnxt *bp;
5207
5208         eth_dev = &rte_eth_devices[port_id];
5209         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5210                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5211                 if (!vfr)
5212                         return 0;
5213
5214                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5215                         return vfr->fw_fid - 1;
5216
5217                 eth_dev = vfr->parent_dev;
5218         }
5219
5220         bp = eth_dev->data->dev_private;
5221
5222         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5223 }
5224
5225 uint16_t
5226 bnxt_get_vport(uint16_t port_id)
5227 {
5228         return (1 << bnxt_get_phy_port_id(port_id));
5229 }
5230
5231 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5232 {
5233         struct bnxt_error_recovery_info *info = bp->recovery_info;
5234
5235         if (info) {
5236                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5237                         memset(info, 0, sizeof(*info));
5238                 return;
5239         }
5240
5241         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5242                 return;
5243
5244         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5245                            sizeof(*info), 0);
5246         if (!info)
5247                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5248
5249         bp->recovery_info = info;
5250 }
5251
5252 static void bnxt_check_fw_status(struct bnxt *bp)
5253 {
5254         uint32_t fw_status;
5255
5256         if (!(bp->recovery_info &&
5257               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5258                 return;
5259
5260         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5261         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5262                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5263                             fw_status);
5264 }
5265
5266 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5267 {
5268         struct bnxt_error_recovery_info *info = bp->recovery_info;
5269         uint32_t status_loc;
5270         uint32_t sig_ver;
5271
5272         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5273                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5274         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5275                                    BNXT_GRCP_WINDOW_2_BASE +
5276                                    offsetof(struct hcomm_status,
5277                                             sig_ver)));
5278         /* If the signature is absent, then FW does not support this feature */
5279         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5280             HCOMM_STATUS_SIGNATURE_VAL)
5281                 return 0;
5282
5283         if (!info) {
5284                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5285                                    sizeof(*info), 0);
5286                 if (!info)
5287                         return -ENOMEM;
5288                 bp->recovery_info = info;
5289         } else {
5290                 memset(info, 0, sizeof(*info));
5291         }
5292
5293         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5294                                       BNXT_GRCP_WINDOW_2_BASE +
5295                                       offsetof(struct hcomm_status,
5296                                                fw_status_loc)));
5297
5298         /* Only pre-map the FW health status GRC register */
5299         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5300                 return 0;
5301
5302         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5303         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5304                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5305
5306         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5307                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5308
5309         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5310
5311         return 0;
5312 }
5313
5314 /* This function gets the FW version along with the
5315  * capabilities(MAX and current) of the function, vnic,
5316  * error recovery, phy and other chip related info
5317  */
5318 static int bnxt_get_config(struct bnxt *bp)
5319 {
5320         uint16_t mtu;
5321         int rc = 0;
5322
5323         bp->fw_cap = 0;
5324
5325         rc = bnxt_map_hcomm_fw_status_reg(bp);
5326         if (rc)
5327                 return rc;
5328
5329         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5330         if (rc) {
5331                 bnxt_check_fw_status(bp);
5332                 return rc;
5333         }
5334
5335         rc = bnxt_hwrm_func_reset(bp);
5336         if (rc)
5337                 return -EIO;
5338
5339         rc = bnxt_hwrm_vnic_qcaps(bp);
5340         if (rc)
5341                 return rc;
5342
5343         rc = bnxt_hwrm_queue_qportcfg(bp);
5344         if (rc)
5345                 return rc;
5346
5347         /* Get the MAX capabilities for this function.
5348          * This function also allocates context memory for TQM rings and
5349          * informs the firmware about this allocated backing store memory.
5350          */
5351         rc = bnxt_hwrm_func_qcaps(bp);
5352         if (rc)
5353                 return rc;
5354
5355         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5356         if (rc)
5357                 return rc;
5358
5359         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5360         if (rc)
5361                 return rc;
5362
5363         bnxt_hwrm_port_mac_qcfg(bp);
5364
5365         bnxt_hwrm_parent_pf_qcfg(bp);
5366
5367         bnxt_hwrm_port_phy_qcaps(bp);
5368
5369         bnxt_alloc_error_recovery_info(bp);
5370         /* Get the adapter error recovery support info */
5371         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5372         if (rc)
5373                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5374
5375         bnxt_hwrm_port_led_qcaps(bp);
5376
5377         return 0;
5378 }
5379
5380 static int
5381 bnxt_init_locks(struct bnxt *bp)
5382 {
5383         int err;
5384
5385         err = pthread_mutex_init(&bp->flow_lock, NULL);
5386         if (err) {
5387                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5388                 return err;
5389         }
5390
5391         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5392         if (err) {
5393                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5394                 return err;
5395         }
5396
5397         err = pthread_mutex_init(&bp->health_check_lock, NULL);
5398         if (err) {
5399                 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5400                 return err;
5401         }
5402
5403         err = pthread_mutex_init(&bp->err_recovery_lock, NULL);
5404         if (err)
5405                 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n");
5406
5407         return err;
5408 }
5409
5410 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5411 {
5412         int rc = 0;
5413
5414         rc = bnxt_get_config(bp);
5415         if (rc)
5416                 return rc;
5417
5418         if (!reconfig_dev) {
5419                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5420                 if (rc)
5421                         return rc;
5422         } else {
5423                 rc = bnxt_restore_dflt_mac(bp);
5424                 if (rc)
5425                         return rc;
5426         }
5427
5428         bnxt_config_vf_req_fwd(bp);
5429
5430         rc = bnxt_hwrm_func_driver_register(bp);
5431         if (rc) {
5432                 PMD_DRV_LOG(ERR, "Failed to register driver");
5433                 return -EBUSY;
5434         }
5435
5436         if (BNXT_PF(bp)) {
5437                 if (bp->pdev->max_vfs) {
5438                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5439                         if (rc) {
5440                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5441                                 return rc;
5442                         }
5443                 } else {
5444                         rc = bnxt_hwrm_allocate_pf_only(bp);
5445                         if (rc) {
5446                                 PMD_DRV_LOG(ERR,
5447                                             "Failed to allocate PF resources");
5448                                 return rc;
5449                         }
5450                 }
5451         }
5452
5453         rc = bnxt_alloc_mem(bp, reconfig_dev);
5454         if (rc)
5455                 return rc;
5456
5457         rc = bnxt_setup_int(bp);
5458         if (rc)
5459                 return rc;
5460
5461         rc = bnxt_request_int(bp);
5462         if (rc)
5463                 return rc;
5464
5465         rc = bnxt_init_ctx_mem(bp);
5466         if (rc) {
5467                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5468                 return rc;
5469         }
5470
5471         return 0;
5472 }
5473
5474 static int
5475 bnxt_parse_devarg_accum_stats(__rte_unused const char *key,
5476                               const char *value, void *opaque_arg)
5477 {
5478         struct bnxt *bp = opaque_arg;
5479         unsigned long accum_stats;
5480         char *end = NULL;
5481
5482         if (!value || !opaque_arg) {
5483                 PMD_DRV_LOG(ERR,
5484                             "Invalid parameter passed to accum-stats devargs.\n");
5485                 return -EINVAL;
5486         }
5487
5488         accum_stats = strtoul(value, &end, 10);
5489         if (end == NULL || *end != '\0' ||
5490             (accum_stats == ULONG_MAX && errno == ERANGE)) {
5491                 PMD_DRV_LOG(ERR,
5492                             "Invalid parameter passed to accum-stats devargs.\n");
5493                 return -EINVAL;
5494         }
5495
5496         if (BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats)) {
5497                 PMD_DRV_LOG(ERR,
5498                             "Invalid value passed to accum-stats devargs.\n");
5499                 return -EINVAL;
5500         }
5501
5502         if (accum_stats) {
5503                 bp->flags2 |= BNXT_FLAGS2_ACCUM_STATS_EN;
5504                 PMD_DRV_LOG(INFO, "Host-based accum-stats feature enabled.\n");
5505         } else {
5506                 bp->flags2 &= ~BNXT_FLAGS2_ACCUM_STATS_EN;
5507                 PMD_DRV_LOG(INFO, "Host-based accum-stats feature disabled.\n");
5508         }
5509
5510         return 0;
5511 }
5512
5513 static int
5514 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5515                              const char *value, void *opaque_arg)
5516 {
5517         struct bnxt *bp = opaque_arg;
5518         unsigned long flow_xstat;
5519         char *end = NULL;
5520
5521         if (!value || !opaque_arg) {
5522                 PMD_DRV_LOG(ERR,
5523                             "Invalid parameter passed to flow_xstat devarg.\n");
5524                 return -EINVAL;
5525         }
5526
5527         flow_xstat = strtoul(value, &end, 10);
5528         if (end == NULL || *end != '\0' ||
5529             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5530                 PMD_DRV_LOG(ERR,
5531                             "Invalid parameter passed to flow_xstat devarg.\n");
5532                 return -EINVAL;
5533         }
5534
5535         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5536                 PMD_DRV_LOG(ERR,
5537                             "Invalid value passed to flow_xstat devarg.\n");
5538                 return -EINVAL;
5539         }
5540
5541         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5542         if (BNXT_FLOW_XSTATS_EN(bp))
5543                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5544
5545         return 0;
5546 }
5547
5548 static int
5549 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5550                                         const char *value, void *opaque_arg)
5551 {
5552         struct bnxt *bp = opaque_arg;
5553         unsigned long max_num_kflows;
5554         char *end = NULL;
5555
5556         if (!value || !opaque_arg) {
5557                 PMD_DRV_LOG(ERR,
5558                         "Invalid parameter passed to max_num_kflows devarg.\n");
5559                 return -EINVAL;
5560         }
5561
5562         max_num_kflows = strtoul(value, &end, 10);
5563         if (end == NULL || *end != '\0' ||
5564                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5565                 PMD_DRV_LOG(ERR,
5566                         "Invalid parameter passed to max_num_kflows devarg.\n");
5567                 return -EINVAL;
5568         }
5569
5570         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5571                 PMD_DRV_LOG(ERR,
5572                         "Invalid value passed to max_num_kflows devarg.\n");
5573                 return -EINVAL;
5574         }
5575
5576         bp->max_num_kflows = max_num_kflows;
5577         if (bp->max_num_kflows)
5578                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5579                                 max_num_kflows);
5580
5581         return 0;
5582 }
5583
5584 static int
5585 bnxt_parse_devarg_app_id(__rte_unused const char *key,
5586                                  const char *value, void *opaque_arg)
5587 {
5588         struct bnxt *bp = opaque_arg;
5589         unsigned long app_id;
5590         char *end = NULL;
5591
5592         if (!value || !opaque_arg) {
5593                 PMD_DRV_LOG(ERR,
5594                             "Invalid parameter passed to app-id "
5595                             "devargs.\n");
5596                 return -EINVAL;
5597         }
5598
5599         app_id = strtoul(value, &end, 10);
5600         if (end == NULL || *end != '\0' ||
5601             (app_id == ULONG_MAX && errno == ERANGE)) {
5602                 PMD_DRV_LOG(ERR,
5603                             "Invalid parameter passed to app_id "
5604                             "devargs.\n");
5605                 return -EINVAL;
5606         }
5607
5608         if (BNXT_DEVARG_APP_ID_INVALID(app_id)) {
5609                 PMD_DRV_LOG(ERR, "Invalid app-id(%d) devargs.\n",
5610                             (uint16_t)app_id);
5611                 return -EINVAL;
5612         }
5613
5614         bp->app_id = app_id;
5615         PMD_DRV_LOG(INFO, "app-id=%d feature enabled.\n", (uint16_t)app_id);
5616
5617         return 0;
5618 }
5619
5620 static int
5621 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5622                             const char *value, void *opaque_arg)
5623 {
5624         struct bnxt_representor *vfr_bp = opaque_arg;
5625         unsigned long rep_is_pf;
5626         char *end = NULL;
5627
5628         if (!value || !opaque_arg) {
5629                 PMD_DRV_LOG(ERR,
5630                             "Invalid parameter passed to rep_is_pf devargs.\n");
5631                 return -EINVAL;
5632         }
5633
5634         rep_is_pf = strtoul(value, &end, 10);
5635         if (end == NULL || *end != '\0' ||
5636             (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5637                 PMD_DRV_LOG(ERR,
5638                             "Invalid parameter passed to rep_is_pf devargs.\n");
5639                 return -EINVAL;
5640         }
5641
5642         if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5643                 PMD_DRV_LOG(ERR,
5644                             "Invalid value passed to rep_is_pf devargs.\n");
5645                 return -EINVAL;
5646         }
5647
5648         vfr_bp->flags |= rep_is_pf;
5649         if (BNXT_REP_PF(vfr_bp))
5650                 PMD_DRV_LOG(INFO, "PF representor\n");
5651         else
5652                 PMD_DRV_LOG(INFO, "VF representor\n");
5653
5654         return 0;
5655 }
5656
5657 static int
5658 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5659                                const char *value, void *opaque_arg)
5660 {
5661         struct bnxt_representor *vfr_bp = opaque_arg;
5662         unsigned long rep_based_pf;
5663         char *end = NULL;
5664
5665         if (!value || !opaque_arg) {
5666                 PMD_DRV_LOG(ERR,
5667                             "Invalid parameter passed to rep_based_pf "
5668                             "devargs.\n");
5669                 return -EINVAL;
5670         }
5671
5672         rep_based_pf = strtoul(value, &end, 10);
5673         if (end == NULL || *end != '\0' ||
5674             (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5675                 PMD_DRV_LOG(ERR,
5676                             "Invalid parameter passed to rep_based_pf "
5677                             "devargs.\n");
5678                 return -EINVAL;
5679         }
5680
5681         if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5682                 PMD_DRV_LOG(ERR,
5683                             "Invalid value passed to rep_based_pf devargs.\n");
5684                 return -EINVAL;
5685         }
5686
5687         vfr_bp->rep_based_pf = rep_based_pf;
5688         vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
5689
5690         PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5691
5692         return 0;
5693 }
5694
5695 static int
5696 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5697                             const char *value, void *opaque_arg)
5698 {
5699         struct bnxt_representor *vfr_bp = opaque_arg;
5700         unsigned long rep_q_r2f;
5701         char *end = NULL;
5702
5703         if (!value || !opaque_arg) {
5704                 PMD_DRV_LOG(ERR,
5705                             "Invalid parameter passed to rep_q_r2f "
5706                             "devargs.\n");
5707                 return -EINVAL;
5708         }
5709
5710         rep_q_r2f = strtoul(value, &end, 10);
5711         if (end == NULL || *end != '\0' ||
5712             (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5713                 PMD_DRV_LOG(ERR,
5714                             "Invalid parameter passed to rep_q_r2f "
5715                             "devargs.\n");
5716                 return -EINVAL;
5717         }
5718
5719         if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5720                 PMD_DRV_LOG(ERR,
5721                             "Invalid value passed to rep_q_r2f devargs.\n");
5722                 return -EINVAL;
5723         }
5724
5725         vfr_bp->rep_q_r2f = rep_q_r2f;
5726         vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5727         PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5728
5729         return 0;
5730 }
5731
5732 static int
5733 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5734                             const char *value, void *opaque_arg)
5735 {
5736         struct bnxt_representor *vfr_bp = opaque_arg;
5737         unsigned long rep_q_f2r;
5738         char *end = NULL;
5739
5740         if (!value || !opaque_arg) {
5741                 PMD_DRV_LOG(ERR,
5742                             "Invalid parameter passed to rep_q_f2r "
5743                             "devargs.\n");
5744                 return -EINVAL;
5745         }
5746
5747         rep_q_f2r = strtoul(value, &end, 10);
5748         if (end == NULL || *end != '\0' ||
5749             (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5750                 PMD_DRV_LOG(ERR,
5751                             "Invalid parameter passed to rep_q_f2r "
5752                             "devargs.\n");
5753                 return -EINVAL;
5754         }
5755
5756         if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5757                 PMD_DRV_LOG(ERR,
5758                             "Invalid value passed to rep_q_f2r devargs.\n");
5759                 return -EINVAL;
5760         }
5761
5762         vfr_bp->rep_q_f2r = rep_q_f2r;
5763         vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5764         PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5765
5766         return 0;
5767 }
5768
5769 static int
5770 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5771                              const char *value, void *opaque_arg)
5772 {
5773         struct bnxt_representor *vfr_bp = opaque_arg;
5774         unsigned long rep_fc_r2f;
5775         char *end = NULL;
5776
5777         if (!value || !opaque_arg) {
5778                 PMD_DRV_LOG(ERR,
5779                             "Invalid parameter passed to rep_fc_r2f "
5780                             "devargs.\n");
5781                 return -EINVAL;
5782         }
5783
5784         rep_fc_r2f = strtoul(value, &end, 10);
5785         if (end == NULL || *end != '\0' ||
5786             (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5787                 PMD_DRV_LOG(ERR,
5788                             "Invalid parameter passed to rep_fc_r2f "
5789                             "devargs.\n");
5790                 return -EINVAL;
5791         }
5792
5793         if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5794                 PMD_DRV_LOG(ERR,
5795                             "Invalid value passed to rep_fc_r2f devargs.\n");
5796                 return -EINVAL;
5797         }
5798
5799         vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5800         vfr_bp->rep_fc_r2f = rep_fc_r2f;
5801         PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5802
5803         return 0;
5804 }
5805
5806 static int
5807 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5808                              const char *value, void *opaque_arg)
5809 {
5810         struct bnxt_representor *vfr_bp = opaque_arg;
5811         unsigned long rep_fc_f2r;
5812         char *end = NULL;
5813
5814         if (!value || !opaque_arg) {
5815                 PMD_DRV_LOG(ERR,
5816                             "Invalid parameter passed to rep_fc_f2r "
5817                             "devargs.\n");
5818                 return -EINVAL;
5819         }
5820
5821         rep_fc_f2r = strtoul(value, &end, 10);
5822         if (end == NULL || *end != '\0' ||
5823             (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5824                 PMD_DRV_LOG(ERR,
5825                             "Invalid parameter passed to rep_fc_f2r "
5826                             "devargs.\n");
5827                 return -EINVAL;
5828         }
5829
5830         if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5831                 PMD_DRV_LOG(ERR,
5832                             "Invalid value passed to rep_fc_f2r devargs.\n");
5833                 return -EINVAL;
5834         }
5835
5836         vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5837         vfr_bp->rep_fc_f2r = rep_fc_f2r;
5838         PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5839
5840         return 0;
5841 }
5842
5843 static int
5844 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5845 {
5846         struct rte_kvargs *kvlist;
5847         int ret;
5848
5849         if (devargs == NULL)
5850                 return 0;
5851
5852         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5853         if (kvlist == NULL)
5854                 return -EINVAL;
5855
5856         /*
5857          * Handler for "flow_xstat" devarg.
5858          * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5859          */
5860         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5861                                  bnxt_parse_devarg_flow_xstat, bp);
5862         if (ret)
5863                 goto err;
5864
5865         /*
5866          * Handler for "accum-stats" devarg.
5867          * Invoked as for ex: "-a 0000:00:0d.0,accum-stats=1"
5868          */
5869         rte_kvargs_process(kvlist, BNXT_DEVARG_ACCUM_STATS,
5870                            bnxt_parse_devarg_accum_stats, bp);
5871         /*
5872          * Handler for "max_num_kflows" devarg.
5873          * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5874          */
5875         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5876                                  bnxt_parse_devarg_max_num_kflows, bp);
5877         if (ret)
5878                 goto err;
5879
5880 err:
5881         /*
5882          * Handler for "app-id" devarg.
5883          * Invoked as for ex: "-a 000:00:0d.0,app-id=1"
5884          */
5885         rte_kvargs_process(kvlist, BNXT_DEVARG_APP_ID,
5886                            bnxt_parse_devarg_app_id, bp);
5887
5888         rte_kvargs_free(kvlist);
5889         return ret;
5890 }
5891
5892 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5893 {
5894         int rc = 0;
5895
5896         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5897                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5898                 if (rc)
5899                         PMD_DRV_LOG(ERR,
5900                                     "Failed to alloc switch domain: %d\n", rc);
5901                 else
5902                         PMD_DRV_LOG(INFO,
5903                                     "Switch domain allocated %d\n",
5904                                     bp->switch_domain_id);
5905         }
5906
5907         return rc;
5908 }
5909
5910 /* Allocate and initialize various fields in bnxt struct that
5911  * need to be allocated/destroyed only once in the lifetime of the driver
5912  */
5913 static int bnxt_drv_init(struct rte_eth_dev *eth_dev)
5914 {
5915         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5916         struct bnxt *bp = eth_dev->data->dev_private;
5917         int rc = 0;
5918
5919         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5920
5921         if (bnxt_vf_pciid(pci_dev->id.device_id))
5922                 bp->flags |= BNXT_FLAG_VF;
5923
5924         if (bnxt_p5_device(pci_dev->id.device_id))
5925                 bp->flags |= BNXT_FLAG_CHIP_P5;
5926
5927         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5928             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5929             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5930             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5931                 bp->flags |= BNXT_FLAG_STINGRAY;
5932
5933         if (BNXT_TRUFLOW_EN(bp)) {
5934                 /* extra mbuf field is required to store CFA code from mark */
5935                 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5936                         .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5937                         .size = sizeof(bnxt_cfa_code_dynfield_t),
5938                         .align = __alignof__(bnxt_cfa_code_dynfield_t),
5939                 };
5940                 bnxt_cfa_code_dynfield_offset =
5941                         rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5942                 if (bnxt_cfa_code_dynfield_offset < 0) {
5943                         PMD_DRV_LOG(ERR,
5944                             "Failed to register mbuf field for TruFlow mark\n");
5945                         return -rte_errno;
5946                 }
5947         }
5948
5949         rc = bnxt_map_pci_bars(eth_dev);
5950         if (rc) {
5951                 PMD_DRV_LOG(ERR,
5952                             "Failed to initialize board rc: %x\n", rc);
5953                 return rc;
5954         }
5955
5956         rc = bnxt_alloc_pf_info(bp);
5957         if (rc)
5958                 return rc;
5959
5960         rc = bnxt_alloc_link_info(bp);
5961         if (rc)
5962                 return rc;
5963
5964         rc = bnxt_alloc_parent_info(bp);
5965         if (rc)
5966                 return rc;
5967
5968         rc = bnxt_alloc_hwrm_resources(bp);
5969         if (rc) {
5970                 PMD_DRV_LOG(ERR,
5971                             "Failed to allocate response buffer rc: %x\n", rc);
5972                 return rc;
5973         }
5974         rc = bnxt_alloc_leds_info(bp);
5975         if (rc)
5976                 return rc;
5977
5978         rc = bnxt_alloc_cos_queues(bp);
5979         if (rc)
5980                 return rc;
5981
5982         rc = bnxt_init_locks(bp);
5983         if (rc)
5984                 return rc;
5985
5986         rc = bnxt_alloc_switch_domain(bp);
5987         if (rc)
5988                 return rc;
5989
5990         return rc;
5991 }
5992
5993 static int
5994 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5995 {
5996         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5997         static int version_printed;
5998         struct bnxt *bp;
5999         int rc;
6000
6001         if (version_printed++ == 0)
6002                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
6003
6004         eth_dev->dev_ops = &bnxt_dev_ops;
6005         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
6006         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
6007         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
6008         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
6009         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
6010
6011         /*
6012          * For secondary processes, we don't initialise any further
6013          * as primary has already done this work.
6014          */
6015         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6016                 return 0;
6017
6018         rte_eth_copy_pci_info(eth_dev, pci_dev);
6019         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
6020
6021         bp = eth_dev->data->dev_private;
6022
6023         /* Parse dev arguments passed on when starting the DPDK application. */
6024         rc = bnxt_parse_dev_args(bp, pci_dev->device.devargs);
6025         if (rc)
6026                 goto error_free;
6027
6028         rc = bnxt_drv_init(eth_dev);
6029         if (rc)
6030                 goto error_free;
6031
6032         rc = bnxt_init_resources(bp, false);
6033         if (rc)
6034                 goto error_free;
6035
6036         rc = bnxt_alloc_stats_mem(bp);
6037         if (rc)
6038                 goto error_free;
6039
6040         PMD_DRV_LOG(INFO,
6041                     "Found %s device at mem %" PRIX64 ", node addr %pM\n",
6042                     DRV_MODULE_NAME,
6043                     pci_dev->mem_resource[0].phys_addr,
6044                     pci_dev->mem_resource[0].addr);
6045
6046         return 0;
6047
6048 error_free:
6049         bnxt_dev_uninit(eth_dev);
6050         return rc;
6051 }
6052
6053
6054 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
6055 {
6056         if (!ctx)
6057                 return;
6058
6059         if (ctx->va)
6060                 rte_free(ctx->va);
6061
6062         ctx->va = NULL;
6063         ctx->dma = RTE_BAD_IOVA;
6064         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
6065 }
6066
6067 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
6068 {
6069         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
6070                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6071                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
6072                                   bp->flow_stat->max_fc,
6073                                   false);
6074
6075         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
6076                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6077                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
6078                                   bp->flow_stat->max_fc,
6079                                   false);
6080
6081         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6082                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
6083         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6084
6085         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6086                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
6087         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6088
6089         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6090                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
6091         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6092
6093         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6094                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
6095         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6096 }
6097
6098 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
6099 {
6100         bnxt_unregister_fc_ctx_mem(bp);
6101
6102         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
6103         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
6104         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
6105         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
6106 }
6107
6108 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
6109 {
6110         if (BNXT_FLOW_XSTATS_EN(bp))
6111                 bnxt_uninit_fc_ctx_mem(bp);
6112 }
6113
6114 static void
6115 bnxt_free_error_recovery_info(struct bnxt *bp)
6116 {
6117         rte_free(bp->recovery_info);
6118         bp->recovery_info = NULL;
6119         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
6120 }
6121
6122 static int
6123 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
6124 {
6125         int rc;
6126
6127         bnxt_free_int(bp);
6128         bnxt_free_mem(bp, reconfig_dev);
6129
6130         bnxt_hwrm_func_buf_unrgtr(bp);
6131         if (bp->pf != NULL) {
6132                 rte_free(bp->pf->vf_req_buf);
6133                 bp->pf->vf_req_buf = NULL;
6134         }
6135
6136         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
6137         bp->flags &= ~BNXT_FLAG_REGISTERED;
6138         bnxt_free_ctx_mem(bp);
6139         if (!reconfig_dev) {
6140                 bnxt_free_hwrm_resources(bp);
6141                 bnxt_free_error_recovery_info(bp);
6142         }
6143
6144         bnxt_uninit_ctx_mem(bp);
6145
6146         bnxt_free_flow_stats_info(bp);
6147         if (bp->rep_info != NULL)
6148                 bnxt_free_switch_domain(bp);
6149         bnxt_free_rep_info(bp);
6150         rte_free(bp->ptp_cfg);
6151         bp->ptp_cfg = NULL;
6152         return rc;
6153 }
6154
6155 static int
6156 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
6157 {
6158         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6159                 return -EPERM;
6160
6161         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
6162
6163         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
6164                 bnxt_dev_close_op(eth_dev);
6165
6166         return 0;
6167 }
6168
6169 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
6170 {
6171         struct bnxt *bp = eth_dev->data->dev_private;
6172         struct rte_eth_dev *vf_rep_eth_dev;
6173         int ret = 0, i;
6174
6175         if (!bp)
6176                 return -EINVAL;
6177
6178         for (i = 0; i < bp->num_reps; i++) {
6179                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
6180                 if (!vf_rep_eth_dev)
6181                         continue;
6182                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
6183                             vf_rep_eth_dev->data->port_id);
6184                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
6185         }
6186         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
6187                     eth_dev->data->port_id);
6188         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
6189
6190         return ret;
6191 }
6192
6193 static void bnxt_free_rep_info(struct bnxt *bp)
6194 {
6195         rte_free(bp->rep_info);
6196         bp->rep_info = NULL;
6197         rte_free(bp->cfa_code_map);
6198         bp->cfa_code_map = NULL;
6199 }
6200
6201 static int bnxt_init_rep_info(struct bnxt *bp)
6202 {
6203         int i = 0, rc;
6204
6205         if (bp->rep_info)
6206                 return 0;
6207
6208         bp->rep_info = rte_zmalloc("bnxt_rep_info",
6209                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
6210                                    0);
6211         if (!bp->rep_info) {
6212                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
6213                 return -ENOMEM;
6214         }
6215         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
6216                                        sizeof(*bp->cfa_code_map) *
6217                                        BNXT_MAX_CFA_CODE, 0);
6218         if (!bp->cfa_code_map) {
6219                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
6220                 bnxt_free_rep_info(bp);
6221                 return -ENOMEM;
6222         }
6223
6224         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
6225                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
6226
6227         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
6228         if (rc) {
6229                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
6230                 bnxt_free_rep_info(bp);
6231                 return rc;
6232         }
6233
6234         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
6235         if (rc) {
6236                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
6237                 bnxt_free_rep_info(bp);
6238                 return rc;
6239         }
6240
6241         return rc;
6242 }
6243
6244 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
6245                                struct rte_eth_devargs *eth_da,
6246                                struct rte_eth_dev *backing_eth_dev,
6247                                const char *dev_args)
6248 {
6249         struct rte_eth_dev *vf_rep_eth_dev;
6250         char name[RTE_ETH_NAME_MAX_LEN];
6251         struct bnxt *backing_bp;
6252         uint16_t num_rep;
6253         int i, ret = 0;
6254         struct rte_kvargs *kvlist = NULL;
6255
6256         if (eth_da->type == RTE_ETH_REPRESENTOR_NONE)
6257                 return 0;
6258         if (eth_da->type != RTE_ETH_REPRESENTOR_VF) {
6259                 PMD_DRV_LOG(ERR, "unsupported representor type %d\n",
6260                             eth_da->type);
6261                 return -ENOTSUP;
6262         }
6263         num_rep = eth_da->nb_representor_ports;
6264         if (num_rep > BNXT_MAX_VF_REPS) {
6265                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
6266                             num_rep, BNXT_MAX_VF_REPS);
6267                 return -EINVAL;
6268         }
6269
6270         if (num_rep >= RTE_MAX_ETHPORTS) {
6271                 PMD_DRV_LOG(ERR,
6272                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6273                             num_rep, RTE_MAX_ETHPORTS);
6274                 return -EINVAL;
6275         }
6276
6277         backing_bp = backing_eth_dev->data->dev_private;
6278
6279         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6280                 PMD_DRV_LOG(ERR,
6281                             "Not a PF or trusted VF. No Representor support\n");
6282                 /* Returning an error is not an option.
6283                  * Applications are not handling this correctly
6284                  */
6285                 return 0;
6286         }
6287
6288         if (bnxt_init_rep_info(backing_bp))
6289                 return 0;
6290
6291         for (i = 0; i < num_rep; i++) {
6292                 struct bnxt_representor representor = {
6293                         .vf_id = eth_da->representor_ports[i],
6294                         .switch_domain_id = backing_bp->switch_domain_id,
6295                         .parent_dev = backing_eth_dev
6296                 };
6297
6298                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6299                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6300                                     representor.vf_id, BNXT_MAX_VF_REPS);
6301                         continue;
6302                 }
6303
6304                 /* representor port net_bdf_port */
6305                 snprintf(name, sizeof(name), "net_%s_representor_%d",
6306                          pci_dev->device.name, eth_da->representor_ports[i]);
6307
6308                 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
6309                 if (kvlist) {
6310                         /*
6311                          * Handler for "rep_is_pf" devarg.
6312                          * Invoked as for ex: "-a 000:00:0d.0,
6313                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6314                          */
6315                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
6316                                                  bnxt_parse_devarg_rep_is_pf,
6317                                                  (void *)&representor);
6318                         if (ret) {
6319                                 ret = -EINVAL;
6320                                 goto err;
6321                         }
6322                         /*
6323                          * Handler for "rep_based_pf" devarg.
6324                          * Invoked as for ex: "-a 000:00:0d.0,
6325                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6326                          */
6327                         ret = rte_kvargs_process(kvlist,
6328                                                  BNXT_DEVARG_REP_BASED_PF,
6329                                                  bnxt_parse_devarg_rep_based_pf,
6330                                                  (void *)&representor);
6331                         if (ret) {
6332                                 ret = -EINVAL;
6333                                 goto err;
6334                         }
6335                         /*
6336                          * Handler for "rep_based_pf" devarg.
6337                          * Invoked as for ex: "-a 000:00:0d.0,
6338                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6339                          */
6340                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
6341                                                  bnxt_parse_devarg_rep_q_r2f,
6342                                                  (void *)&representor);
6343                         if (ret) {
6344                                 ret = -EINVAL;
6345                                 goto err;
6346                         }
6347                         /*
6348                          * Handler for "rep_based_pf" devarg.
6349                          * Invoked as for ex: "-a 000:00:0d.0,
6350                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6351                          */
6352                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
6353                                                  bnxt_parse_devarg_rep_q_f2r,
6354                                                  (void *)&representor);
6355                         if (ret) {
6356                                 ret = -EINVAL;
6357                                 goto err;
6358                         }
6359                         /*
6360                          * Handler for "rep_based_pf" devarg.
6361                          * Invoked as for ex: "-a 000:00:0d.0,
6362                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6363                          */
6364                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
6365                                                  bnxt_parse_devarg_rep_fc_r2f,
6366                                                  (void *)&representor);
6367                         if (ret) {
6368                                 ret = -EINVAL;
6369                                 goto err;
6370                         }
6371                         /*
6372                          * Handler for "rep_based_pf" devarg.
6373                          * Invoked as for ex: "-a 000:00:0d.0,
6374                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6375                          */
6376                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
6377                                                  bnxt_parse_devarg_rep_fc_f2r,
6378                                                  (void *)&representor);
6379                         if (ret) {
6380                                 ret = -EINVAL;
6381                                 goto err;
6382                         }
6383                 }
6384
6385                 ret = rte_eth_dev_create(&pci_dev->device, name,
6386                                          sizeof(struct bnxt_representor),
6387                                          NULL, NULL,
6388                                          bnxt_representor_init,
6389                                          &representor);
6390                 if (ret) {
6391                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6392                                     "representor %s.", name);
6393                         goto err;
6394                 }
6395
6396                 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6397                 if (!vf_rep_eth_dev) {
6398                         PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6399                                     " for VF-Rep: %s.", name);
6400                         ret = -ENODEV;
6401                         goto err;
6402                 }
6403
6404                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6405                             backing_eth_dev->data->port_id);
6406                 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6407                                                          vf_rep_eth_dev;
6408                 backing_bp->num_reps++;
6409
6410         }
6411
6412         rte_kvargs_free(kvlist);
6413         return 0;
6414
6415 err:
6416         /* If num_rep > 1, then rollback already created
6417          * ports, since we'll be failing the probe anyway
6418          */
6419         if (num_rep > 1)
6420                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6421         rte_errno = -ret;
6422         rte_kvargs_free(kvlist);
6423
6424         return ret;
6425 }
6426
6427 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6428                           struct rte_pci_device *pci_dev)
6429 {
6430         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6431         struct rte_eth_dev *backing_eth_dev;
6432         uint16_t num_rep;
6433         int ret = 0;
6434
6435         if (pci_dev->device.devargs) {
6436                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6437                                             &eth_da);
6438                 if (ret)
6439                         return ret;
6440         }
6441
6442         num_rep = eth_da.nb_representor_ports;
6443         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6444                     num_rep);
6445
6446         /* We could come here after first level of probe is already invoked
6447          * as part of an application bringup(OVS-DPDK vswitchd), so first check
6448          * for already allocated eth_dev for the backing device (PF/Trusted VF)
6449          */
6450         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6451         if (backing_eth_dev == NULL) {
6452                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6453                                          sizeof(struct bnxt),
6454                                          eth_dev_pci_specific_init, pci_dev,
6455                                          bnxt_dev_init, NULL);
6456
6457                 if (ret || !num_rep)
6458                         return ret;
6459
6460                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6461         }
6462         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6463                     backing_eth_dev->data->port_id);
6464
6465         if (!num_rep)
6466                 return ret;
6467
6468         /* probe representor ports now */
6469         ret = bnxt_rep_port_probe(pci_dev, &eth_da, backing_eth_dev,
6470                                   pci_dev->device.devargs->args);
6471
6472         return ret;
6473 }
6474
6475 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6476 {
6477         struct rte_eth_dev *eth_dev;
6478
6479         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6480         if (!eth_dev)
6481                 return 0; /* Invoked typically only by OVS-DPDK, by the
6482                            * time it comes here the eth_dev is already
6483                            * deleted by rte_eth_dev_close(), so returning
6484                            * +ve value will at least help in proper cleanup
6485                            */
6486
6487         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6488         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6489                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6490                         return rte_eth_dev_destroy(eth_dev,
6491                                                    bnxt_representor_uninit);
6492                 else
6493                         return rte_eth_dev_destroy(eth_dev,
6494                                                    bnxt_dev_uninit);
6495         } else {
6496                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6497         }
6498 }
6499
6500 static struct rte_pci_driver bnxt_rte_pmd = {
6501         .id_table = bnxt_pci_id_map,
6502         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6503                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6504                                                   * and OVS-DPDK
6505                                                   */
6506         .probe = bnxt_pci_probe,
6507         .remove = bnxt_pci_remove,
6508 };
6509
6510 static bool
6511 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6512 {
6513         if (strcmp(dev->device->driver->name, drv->driver.name))
6514                 return false;
6515
6516         return true;
6517 }
6518
6519 bool is_bnxt_supported(struct rte_eth_dev *dev)
6520 {
6521         return is_device_supported(dev, &bnxt_rte_pmd);
6522 }
6523
6524 RTE_LOG_REGISTER_SUFFIX(bnxt_logtype_driver, driver, NOTICE);
6525 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6526 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6527 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");