drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <ethdev_driver.h>
  11 #include <ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16 #include <rte_vect.h>
  17
  18 #include "bnxt.h"
  19 #include "bnxt_filter.h"
  20 #include "bnxt_hwrm.h"
  21 #include "bnxt_irq.h"
  22 #include "bnxt_reps.h"
  23 #include "bnxt_ring.h"
  24 #include "bnxt_rxq.h"
  25 #include "bnxt_rxr.h"
  26 #include "bnxt_stats.h"
  27 #include "bnxt_txq.h"
  28 #include "bnxt_txr.h"
  29 #include "bnxt_vnic.h"
  30 #include "hsi_struct_def_dpdk.h"
  31 #include "bnxt_nvm_defs.h"
  32 #include "bnxt_tf_common.h"
  33 #include "ulp_flow_db.h"
  34 #include "rte_pmd_bnxt.h"
  35
  36 #define DRV_MODULE_NAME         "bnxt"
  37 static const char bnxt_version[] =
  38         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  39
  40 /*
  41  * The set of PCI devices this driver supports
  42  */
  43 static const struct rte_pci_id bnxt_pci_id_map[] = {
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  47                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
  87         { .vendor_id = 0, /* sentinel */ },
  88 };
  89
  90 #define BNXT_DEVARG_ACCUM_STATS "accum-stats"
  91 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
  92 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
  93 #define BNXT_DEVARG_REPRESENTOR "representor"
  94 #define BNXT_DEVARG_REP_BASED_PF  "rep-based-pf"
  95 #define BNXT_DEVARG_REP_IS_PF  "rep-is-pf"
  96 #define BNXT_DEVARG_REP_Q_R2F  "rep-q-r2f"
  97 #define BNXT_DEVARG_REP_Q_F2R  "rep-q-f2r"
  98 #define BNXT_DEVARG_REP_FC_R2F  "rep-fc-r2f"
  99 #define BNXT_DEVARG_REP_FC_F2R  "rep-fc-f2r"
 100 #define BNXT_DEVARG_APP_ID      "app-id"
 101
 102 static const char *const bnxt_dev_args[] = {
 103         BNXT_DEVARG_REPRESENTOR,
 104         BNXT_DEVARG_ACCUM_STATS,
 105         BNXT_DEVARG_FLOW_XSTAT,
 106         BNXT_DEVARG_MAX_NUM_KFLOWS,
 107         BNXT_DEVARG_REP_BASED_PF,
 108         BNXT_DEVARG_REP_IS_PF,
 109         BNXT_DEVARG_REP_Q_R2F,
 110         BNXT_DEVARG_REP_Q_F2R,
 111         BNXT_DEVARG_REP_FC_R2F,
 112         BNXT_DEVARG_REP_FC_F2R,
 113         BNXT_DEVARG_APP_ID,
 114         NULL
 115 };
 116
 117 /*
 118  * accum-stats == false to disable flow counter accumulation
 119  * accum-stats == true to enable flow counter accumulation
 120  */
 121 #define BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats)    ((accum_stats) > 1)
 122
 123 /*
 124  * app-id = an non-negative 8-bit number
 125  */
 126 #define BNXT_DEVARG_APP_ID_INVALID(val)                 ((val) > 255)
 127
 128 /*
 129  * flow_xstat == false to disable the feature
 130  * flow_xstat == true to enable the feature
 131  */
 132 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 133
 134 /*
 135  * rep_is_pf == false to indicate VF representor
 136  * rep_is_pf == true to indicate PF representor
 137  */
 138 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)        ((rep_is_pf) > 1)
 139
 140 /*
 141  * rep_based_pf == Physical index of the PF
 142  */
 143 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)  ((rep_based_pf) > 15)
 144 /*
 145  * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
 146  */
 147 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)        ((rep_q_r2f) > 3)
 148
 149 /*
 150  * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
 151  */
 152 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)        ((rep_q_f2r) > 3)
 153
 154 /*
 155  * rep_fc_r2f == Flow control for the representor to endpoint direction
 156  */
 157 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)      ((rep_fc_r2f) > 1)
 158
 159 /*
 160  * rep_fc_f2r == Flow control for the endpoint to representor direction
 161  */
 162 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)      ((rep_fc_f2r) > 1)
 163
 164 int bnxt_cfa_code_dynfield_offset = -1;
 165
 166 /*
 167  * max_num_kflows must be >= 32
 168  * and must be a power-of-2 supported value
 169  * return: 1 -> invalid
 170  *         0 -> valid
 171  */
 172 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 173 {
 174         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 175                 return 1;
 176         return 0;
 177 }
 178
 179 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 180 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 181 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 182 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 183 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 184 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 185 static void bnxt_dev_recover(void *arg);
 186 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 187 static void bnxt_free_rep_info(struct bnxt *bp);
 188
 189 int is_bnxt_in_error(struct bnxt *bp)
 190 {
 191         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 192                 return -EIO;
 193         if (bp->flags & BNXT_FLAG_FW_RESET)
 194                 return -EBUSY;
 195
 196         return 0;
 197 }
 198
 199 /***********************/
 200
 201 /*
 202  * High level utility functions
 203  */
 204
 205 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 206 {
 207         unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
 208                                              BNXT_RSS_TBL_SIZE_P5);
 209
 210         if (!BNXT_CHIP_P5(bp))
 211                 return 1;
 212
 213         return RTE_ALIGN_MUL_CEIL(num_rss_rings,
 214                                   BNXT_RSS_ENTRIES_PER_CTX_P5) /
 215                                   BNXT_RSS_ENTRIES_PER_CTX_P5;
 216 }
 217
 218 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 219 {
 220         if (!BNXT_CHIP_P5(bp))
 221                 return HW_HASH_INDEX_SIZE;
 222
 223         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
 224 }
 225
 226 static void bnxt_free_parent_info(struct bnxt *bp)
 227 {
 228         rte_free(bp->parent);
 229         bp->parent = NULL;
 230 }
 231
 232 static void bnxt_free_pf_info(struct bnxt *bp)
 233 {
 234         rte_free(bp->pf);
 235         bp->pf = NULL;
 236 }
 237
 238 static void bnxt_free_link_info(struct bnxt *bp)
 239 {
 240         rte_free(bp->link_info);
 241         bp->link_info = NULL;
 242 }
 243
 244 static void bnxt_free_leds_info(struct bnxt *bp)
 245 {
 246         if (BNXT_VF(bp))
 247                 return;
 248
 249         rte_free(bp->leds);
 250         bp->leds = NULL;
 251 }
 252
 253 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 254 {
 255         rte_free(bp->flow_stat);
 256         bp->flow_stat = NULL;
 257 }
 258
 259 static void bnxt_free_cos_queues(struct bnxt *bp)
 260 {
 261         rte_free(bp->rx_cos_queue);
 262         bp->rx_cos_queue = NULL;
 263         rte_free(bp->tx_cos_queue);
 264         bp->tx_cos_queue = NULL;
 265 }
 266
 267 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 268 {
 269         bnxt_free_filter_mem(bp);
 270         bnxt_free_vnic_attributes(bp);
 271         bnxt_free_vnic_mem(bp);
 272
 273         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 274          * If the number of rings change across fw update,
 275          * we don't have much choice except to warn the user.
 276          */
 277         if (!reconfig) {
 278                 bnxt_free_stats(bp);
 279                 bnxt_free_tx_rings(bp);
 280                 bnxt_free_rx_rings(bp);
 281         }
 282         bnxt_free_async_cp_ring(bp);
 283         bnxt_free_rxtx_nq_ring(bp);
 284
 285         rte_free(bp->grp_info);
 286         bp->grp_info = NULL;
 287 }
 288
 289 static int bnxt_alloc_parent_info(struct bnxt *bp)
 290 {
 291         bp->parent = rte_zmalloc("bnxt_parent_info",
 292                                  sizeof(struct bnxt_parent_info), 0);
 293         if (bp->parent == NULL)
 294                 return -ENOMEM;
 295
 296         return 0;
 297 }
 298
 299 static int bnxt_alloc_pf_info(struct bnxt *bp)
 300 {
 301         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 302         if (bp->pf == NULL)
 303                 return -ENOMEM;
 304
 305         return 0;
 306 }
 307
 308 static int bnxt_alloc_link_info(struct bnxt *bp)
 309 {
 310         bp->link_info =
 311                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 312         if (bp->link_info == NULL)
 313                 return -ENOMEM;
 314
 315         return 0;
 316 }
 317
 318 static int bnxt_alloc_leds_info(struct bnxt *bp)
 319 {
 320         if (BNXT_VF(bp))
 321                 return 0;
 322
 323         bp->leds = rte_zmalloc("bnxt_leds",
 324                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 325                                0);
 326         if (bp->leds == NULL)
 327                 return -ENOMEM;
 328
 329         return 0;
 330 }
 331
 332 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 333 {
 334         bp->rx_cos_queue =
 335                 rte_zmalloc("bnxt_rx_cosq",
 336                             BNXT_COS_QUEUE_COUNT *
 337                             sizeof(struct bnxt_cos_queue_info),
 338                             0);
 339         if (bp->rx_cos_queue == NULL)
 340                 return -ENOMEM;
 341
 342         bp->tx_cos_queue =
 343                 rte_zmalloc("bnxt_tx_cosq",
 344                             BNXT_COS_QUEUE_COUNT *
 345                             sizeof(struct bnxt_cos_queue_info),
 346                             0);
 347         if (bp->tx_cos_queue == NULL)
 348                 return -ENOMEM;
 349
 350         return 0;
 351 }
 352
 353 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 354 {
 355         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 356                                     sizeof(struct bnxt_flow_stat_info), 0);
 357         if (bp->flow_stat == NULL)
 358                 return -ENOMEM;
 359
 360         return 0;
 361 }
 362
 363 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 364 {
 365         int rc;
 366
 367         rc = bnxt_alloc_ring_grps(bp);
 368         if (rc)
 369                 goto alloc_mem_err;
 370
 371         rc = bnxt_alloc_async_ring_struct(bp);
 372         if (rc)
 373                 goto alloc_mem_err;
 374
 375         rc = bnxt_alloc_vnic_mem(bp);
 376         if (rc)
 377                 goto alloc_mem_err;
 378
 379         rc = bnxt_alloc_vnic_attributes(bp);
 380         if (rc)
 381                 goto alloc_mem_err;
 382
 383         rc = bnxt_alloc_filter_mem(bp);
 384         if (rc)
 385                 goto alloc_mem_err;
 386
 387         rc = bnxt_alloc_async_cp_ring(bp);
 388         if (rc)
 389                 goto alloc_mem_err;
 390
 391         rc = bnxt_alloc_rxtx_nq_ring(bp);
 392         if (rc)
 393                 goto alloc_mem_err;
 394
 395         if (BNXT_FLOW_XSTATS_EN(bp)) {
 396                 rc = bnxt_alloc_flow_stats_info(bp);
 397                 if (rc)
 398                         goto alloc_mem_err;
 399         }
 400
 401         return 0;
 402
 403 alloc_mem_err:
 404         bnxt_free_mem(bp, reconfig);
 405         return rc;
 406 }
 407
 408 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 409 {
 410         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 411         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 412         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 413         struct bnxt_rx_queue *rxq;
 414         unsigned int j;
 415         int rc;
 416
 417         rc = bnxt_vnic_grp_alloc(bp, vnic);
 418         if (rc)
 419                 goto err_out;
 420
 421         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 422                     vnic_id, vnic, vnic->fw_grp_ids);
 423
 424         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 425         if (rc)
 426                 goto err_out;
 427
 428         /* Alloc RSS context only if RSS mode is enabled */
 429         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 430                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 431
 432                 /* RSS table size in Thor is 512.
 433                  * Cap max Rx rings to same value
 434                  */
 435                 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
 436                         PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
 437                                     bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
 438                         goto err_out;
 439                 }
 440
 441                 rc = 0;
 442                 for (j = 0; j < nr_ctxs; j++) {
 443                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 444                         if (rc)
 445                                 break;
 446                 }
 447                 if (rc) {
 448                         PMD_DRV_LOG(ERR,
 449                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 450                                     vnic_id, j, rc);
 451                         goto err_out;
 452                 }
 453                 vnic->num_lb_ctxts = nr_ctxs;
 454         }
 455
 456         /*
 457          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 458          * setting is not available at this time, it will not be
 459          * configured correctly in the CFA.
 460          */
 461         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 462                 vnic->vlan_strip = true;
 463         else
 464                 vnic->vlan_strip = false;
 465
 466         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 467         if (rc)
 468                 goto err_out;
 469
 470         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 471         if (rc)
 472                 goto err_out;
 473
 474         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 475                 rxq = bp->eth_dev->data->rx_queues[j];
 476
 477                 PMD_DRV_LOG(DEBUG,
 478                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 479                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 480
 481                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 482                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 483                 else
 484                         vnic->rx_queue_cnt++;
 485         }
 486
 487         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 488
 489         rc = bnxt_vnic_rss_configure(bp, vnic);
 490         if (rc)
 491                 goto err_out;
 492
 493         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 494
 495         rc = bnxt_hwrm_vnic_tpa_cfg(bp, vnic,
 496                                     (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) ?
 497                                     true : false);
 498         if (rc)
 499                 goto err_out;
 500
 501         return 0;
 502 err_out:
 503         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 504                     vnic_id, rc);
 505         return rc;
 506 }
 507
 508 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 509 {
 510         int rc = 0;
 511
 512         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 513                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 514         if (rc)
 515                 return rc;
 516
 517         PMD_DRV_LOG(DEBUG,
 518                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 519                     " rx_fc_in_tbl.ctx_id = %d\n",
 520                     bp->flow_stat->rx_fc_in_tbl.va,
 521                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 522                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 523
 524         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 525                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 526         if (rc)
 527                 return rc;
 528
 529         PMD_DRV_LOG(DEBUG,
 530                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 531                     " rx_fc_out_tbl.ctx_id = %d\n",
 532                     bp->flow_stat->rx_fc_out_tbl.va,
 533                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 534                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 535
 536         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 537                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 538         if (rc)
 539                 return rc;
 540
 541         PMD_DRV_LOG(DEBUG,
 542                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 543                     " tx_fc_in_tbl.ctx_id = %d\n",
 544                     bp->flow_stat->tx_fc_in_tbl.va,
 545                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 546                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 547
 548         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 549                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 550         if (rc)
 551                 return rc;
 552
 553         PMD_DRV_LOG(DEBUG,
 554                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 555                     " tx_fc_out_tbl.ctx_id = %d\n",
 556                     bp->flow_stat->tx_fc_out_tbl.va,
 557                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 558                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 559
 560         memset(bp->flow_stat->rx_fc_out_tbl.va,
 561                0,
 562                bp->flow_stat->rx_fc_out_tbl.size);
 563         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 564                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 565                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 566                                        bp->flow_stat->max_fc,
 567                                        true);
 568         if (rc)
 569                 return rc;
 570
 571         memset(bp->flow_stat->tx_fc_out_tbl.va,
 572                0,
 573                bp->flow_stat->tx_fc_out_tbl.size);
 574         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 575                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 576                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 577                                        bp->flow_stat->max_fc,
 578                                        true);
 579
 580         return rc;
 581 }
 582
 583 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 584                                   struct bnxt_ctx_mem_buf_info *ctx)
 585 {
 586         if (!ctx)
 587                 return -EINVAL;
 588
 589         ctx->va = rte_zmalloc(type, size, 0);
 590         if (ctx->va == NULL)
 591                 return -ENOMEM;
 592         rte_mem_lock_page(ctx->va);
 593         ctx->size = size;
 594         ctx->dma = rte_mem_virt2iova(ctx->va);
 595         if (ctx->dma == RTE_BAD_IOVA)
 596                 return -ENOMEM;
 597
 598         return 0;
 599 }
 600
 601 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 602 {
 603         struct rte_pci_device *pdev = bp->pdev;
 604         char type[RTE_MEMZONE_NAMESIZE];
 605         uint16_t max_fc;
 606         int rc = 0;
 607
 608         max_fc = bp->flow_stat->max_fc;
 609
 610         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 611                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 612         /* 4 bytes for each counter-id */
 613         rc = bnxt_alloc_ctx_mem_buf(type,
 614                                     max_fc * 4,
 615                                     &bp->flow_stat->rx_fc_in_tbl);
 616         if (rc)
 617                 return rc;
 618
 619         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 620                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 621         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 622         rc = bnxt_alloc_ctx_mem_buf(type,
 623                                     max_fc * 16,
 624                                     &bp->flow_stat->rx_fc_out_tbl);
 625         if (rc)
 626                 return rc;
 627
 628         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 629                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 630         /* 4 bytes for each counter-id */
 631         rc = bnxt_alloc_ctx_mem_buf(type,
 632                                     max_fc * 4,
 633                                     &bp->flow_stat->tx_fc_in_tbl);
 634         if (rc)
 635                 return rc;
 636
 637         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 638                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 639         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 640         rc = bnxt_alloc_ctx_mem_buf(type,
 641                                     max_fc * 16,
 642                                     &bp->flow_stat->tx_fc_out_tbl);
 643         if (rc)
 644                 return rc;
 645
 646         rc = bnxt_register_fc_ctx_mem(bp);
 647
 648         return rc;
 649 }
 650
 651 static int bnxt_init_ctx_mem(struct bnxt *bp)
 652 {
 653         int rc = 0;
 654
 655         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 656             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 657             !BNXT_FLOW_XSTATS_EN(bp))
 658                 return 0;
 659
 660         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 661         if (rc)
 662                 return rc;
 663
 664         rc = bnxt_init_fc_ctx_mem(bp);
 665
 666         return rc;
 667 }
 668
 669 static int bnxt_update_phy_setting(struct bnxt *bp)
 670 {
 671         struct rte_eth_link new;
 672         int rc;
 673
 674         rc = bnxt_get_hwrm_link_config(bp, &new);
 675         if (rc) {
 676                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 677                 return rc;
 678         }
 679
 680         /*
 681          * On BCM957508-N2100 adapters, FW will not allow any user other
 682          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 683          * always returns link up. Force phy update always in that case.
 684          */
 685         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 686                 rc = bnxt_set_hwrm_link_config(bp, true);
 687                 if (rc) {
 688                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 689                         return rc;
 690                 }
 691         }
 692
 693         return rc;
 694 }
 695
 696 static void bnxt_free_prev_ring_stats(struct bnxt *bp)
 697 {
 698         rte_free(bp->prev_rx_ring_stats);
 699         rte_free(bp->prev_tx_ring_stats);
 700
 701         bp->prev_rx_ring_stats = NULL;
 702         bp->prev_tx_ring_stats = NULL;
 703 }
 704
 705 static int bnxt_alloc_prev_ring_stats(struct bnxt *bp)
 706 {
 707         bp->prev_rx_ring_stats =  rte_zmalloc("bnxt_prev_rx_ring_stats",
 708                                               sizeof(struct bnxt_ring_stats) *
 709                                               bp->rx_cp_nr_rings,
 710                                               0);
 711         if (bp->prev_rx_ring_stats == NULL)
 712                 return -ENOMEM;
 713
 714         bp->prev_tx_ring_stats = rte_zmalloc("bnxt_prev_tx_ring_stats",
 715                                              sizeof(struct bnxt_ring_stats) *
 716                                              bp->tx_cp_nr_rings,
 717                                              0);
 718         if (bp->prev_tx_ring_stats == NULL)
 719                 goto error;
 720
 721         return 0;
 722
 723 error:
 724         bnxt_free_prev_ring_stats(bp);
 725         return -ENOMEM;
 726 }
 727
 728 static int bnxt_start_nic(struct bnxt *bp)
 729 {
 730         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 731         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 732         uint32_t intr_vector = 0;
 733         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 734         uint32_t vec = BNXT_MISC_VEC_ID;
 735         unsigned int i, j;
 736         int rc;
 737
 738         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 739                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 740                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 741                 bp->flags |= BNXT_FLAG_JUMBO;
 742         } else {
 743                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 744                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 745                 bp->flags &= ~BNXT_FLAG_JUMBO;
 746         }
 747
 748         /* THOR does not support ring groups.
 749          * But we will use the array to save RSS context IDs.
 750          */
 751         if (BNXT_CHIP_P5(bp))
 752                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
 753
 754         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 755         if (rc) {
 756                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 757                 goto err_out;
 758         }
 759
 760         rc = bnxt_alloc_hwrm_rings(bp);
 761         if (rc) {
 762                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 763                 goto err_out;
 764         }
 765
 766         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 767         if (rc) {
 768                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 769                 goto err_out;
 770         }
 771
 772         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 773                 goto skip_cosq_cfg;
 774
 775         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 776                 if (bp->rx_cos_queue[i].id != 0xff) {
 777                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 778
 779                         if (!vnic) {
 780                                 PMD_DRV_LOG(ERR,
 781                                             "Num pools more than FW profile\n");
 782                                 rc = -EINVAL;
 783                                 goto err_out;
 784                         }
 785                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 786                         bp->rx_cosq_cnt++;
 787                 }
 788         }
 789
 790 skip_cosq_cfg:
 791         rc = bnxt_mq_rx_configure(bp);
 792         if (rc) {
 793                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 794                 goto err_out;
 795         }
 796
 797         /* default vnic 0 */
 798         rc = bnxt_setup_one_vnic(bp, 0);
 799         if (rc)
 800                 goto err_out;
 801         /* VNIC configuration */
 802         if (BNXT_RFS_NEEDS_VNIC(bp)) {
 803                 for (i = 1; i < bp->nr_vnics; i++) {
 804                         rc = bnxt_setup_one_vnic(bp, i);
 805                         if (rc)
 806                                 goto err_out;
 807                 }
 808         }
 809
 810         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 811         if (rc) {
 812                 PMD_DRV_LOG(ERR,
 813                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 814                 goto err_out;
 815         }
 816
 817         /* check and configure queue intr-vector mapping */
 818         if ((rte_intr_cap_multiple(intr_handle) ||
 819              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 820             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 821                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 822                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 823                 if (intr_vector > bp->rx_cp_nr_rings) {
 824                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 825                                         bp->rx_cp_nr_rings);
 826                         return -ENOTSUP;
 827                 }
 828                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 829                 if (rc)
 830                         return rc;
 831         }
 832
 833         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 834                 intr_handle->intr_vec =
 835                         rte_zmalloc("intr_vec",
 836                                     bp->eth_dev->data->nb_rx_queues *
 837                                     sizeof(int), 0);
 838                 if (intr_handle->intr_vec == NULL) {
 839                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 840                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 841                         rc = -ENOMEM;
 842                         goto err_out;
 843                 }
 844                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 845                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 846                          intr_handle->intr_vec, intr_handle->nb_efd,
 847                         intr_handle->max_intr);
 848                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 849                      queue_id++) {
 850                         intr_handle->intr_vec[queue_id] =
 851                                                         vec + BNXT_RX_VEC_START;
 852                         if (vec < base + intr_handle->nb_efd - 1)
 853                                 vec++;
 854                 }
 855         }
 856
 857         /* enable uio/vfio intr/eventfd mapping */
 858         rc = rte_intr_enable(intr_handle);
 859 #ifndef RTE_EXEC_ENV_FREEBSD
 860         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 861         if (rc)
 862                 goto err_out;
 863 #endif
 864
 865         rc = bnxt_update_phy_setting(bp);
 866         if (rc)
 867                 goto err_out;
 868
 869         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 870         if (!bp->mark_table)
 871                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 872
 873         return 0;
 874
 875 err_out:
 876         /* Some of the error status returned by FW may not be from errno.h */
 877         if (rc > 0)
 878                 rc = -EIO;
 879
 880         return rc;
 881 }
 882
 883 static int bnxt_shutdown_nic(struct bnxt *bp)
 884 {
 885         bnxt_free_all_hwrm_resources(bp);
 886         bnxt_free_all_filters(bp);
 887         bnxt_free_all_vnics(bp);
 888         return 0;
 889 }
 890
 891 /*
 892  * Device configuration and status function
 893  */
 894
 895 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 896 {
 897         uint32_t link_speed = 0;
 898         uint32_t speed_capa = 0;
 899
 900         if (bp->link_info == NULL)
 901                 return 0;
 902
 903         link_speed = bp->link_info->support_speeds;
 904
 905         /* If PAM4 is configured, use PAM4 supported speed */
 906         if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
 907                 link_speed = bp->link_info->support_pam4_speeds;
 908
 909         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 910                 speed_capa |= ETH_LINK_SPEED_100M;
 911         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 912                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 913         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 914                 speed_capa |= ETH_LINK_SPEED_1G;
 915         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 916                 speed_capa |= ETH_LINK_SPEED_2_5G;
 917         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 918                 speed_capa |= ETH_LINK_SPEED_10G;
 919         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 920                 speed_capa |= ETH_LINK_SPEED_20G;
 921         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 922                 speed_capa |= ETH_LINK_SPEED_25G;
 923         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 924                 speed_capa |= ETH_LINK_SPEED_40G;
 925         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 926                 speed_capa |= ETH_LINK_SPEED_50G;
 927         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 928                 speed_capa |= ETH_LINK_SPEED_100G;
 929         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
 930                 speed_capa |= ETH_LINK_SPEED_50G;
 931         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
 932                 speed_capa |= ETH_LINK_SPEED_100G;
 933         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
 934                 speed_capa |= ETH_LINK_SPEED_200G;
 935
 936         if (bp->link_info->auto_mode ==
 937             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 938                 speed_capa |= ETH_LINK_SPEED_FIXED;
 939
 940         return speed_capa;
 941 }
 942
 943 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 944                                 struct rte_eth_dev_info *dev_info)
 945 {
 946         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 947         struct bnxt *bp = eth_dev->data->dev_private;
 948         uint16_t max_vnics, i, j, vpool, vrxq;
 949         unsigned int max_rx_rings;
 950         int rc;
 951
 952         rc = is_bnxt_in_error(bp);
 953         if (rc)
 954                 return rc;
 955
 956         /* MAC Specifics */
 957         dev_info->max_mac_addrs = bp->max_l2_ctx;
 958         dev_info->max_hash_mac_addrs = 0;
 959
 960         /* PF/VF specifics */
 961         if (BNXT_PF(bp))
 962                 dev_info->max_vfs = pdev->max_vfs;
 963
 964         max_rx_rings = bnxt_max_rings(bp);
 965         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 966         dev_info->max_rx_queues = max_rx_rings;
 967         dev_info->max_tx_queues = max_rx_rings;
 968         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 969         dev_info->hash_key_size = HW_HASH_KEY_SIZE;
 970         max_vnics = bp->max_vnics;
 971
 972         /* MTU specifics */
 973         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 974         dev_info->max_mtu = BNXT_MAX_MTU;
 975
 976         /* Fast path specifics */
 977         dev_info->min_rx_bufsize = 1;
 978         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 979
 980         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 981         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 982                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 983         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 984         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
 985                                     dev_info->tx_queue_offload_capa;
 986         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 987
 988         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 989
 990         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 991                 .rx_thresh = {
 992                         .pthresh = 8,
 993                         .hthresh = 8,
 994                         .wthresh = 0,
 995                 },
 996                 .rx_free_thresh = 32,
 997                 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
 998         };
 999
1000         dev_info->default_txconf = (struct rte_eth_txconf) {
1001                 .tx_thresh = {
1002                         .pthresh = 32,
1003                         .hthresh = 0,
1004                         .wthresh = 0,
1005                 },
1006                 .tx_free_thresh = 32,
1007                 .tx_rs_thresh = 32,
1008         };
1009         eth_dev->data->dev_conf.intr_conf.lsc = 1;
1010
1011         eth_dev->data->dev_conf.intr_conf.rxq = 1;
1012         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
1013         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
1014         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
1015         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
1016
1017         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
1018                 dev_info->switch_info.name = eth_dev->device->name;
1019                 dev_info->switch_info.domain_id = bp->switch_domain_id;
1020                 dev_info->switch_info.port_id =
1021                                 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
1022                                     BNXT_SWITCH_PORT_ID_TRUSTED_VF;
1023         }
1024
1025         /*
1026          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
1027          *       need further investigation.
1028          */
1029
1030         /* VMDq resources */
1031         vpool = 64; /* ETH_64_POOLS */
1032         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
1033         for (i = 0; i < 4; vpool >>= 1, i++) {
1034                 if (max_vnics > vpool) {
1035                         for (j = 0; j < 5; vrxq >>= 1, j++) {
1036                                 if (dev_info->max_rx_queues > vrxq) {
1037                                         if (vpool > vrxq)
1038                                                 vpool = vrxq;
1039                                         goto found;
1040                                 }
1041                         }
1042                         /* Not enough resources to support VMDq */
1043                         break;
1044                 }
1045         }
1046         /* Not enough resources to support VMDq */
1047         vpool = 0;
1048         vrxq = 0;
1049 found:
1050         dev_info->max_vmdq_pools = vpool;
1051         dev_info->vmdq_queue_num = vrxq;
1052
1053         dev_info->vmdq_pool_base = 0;
1054         dev_info->vmdq_queue_base = 0;
1055
1056         return 0;
1057 }
1058
1059 /* Configure the device based on the configuration provided */
1060 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1061 {
1062         struct bnxt *bp = eth_dev->data->dev_private;
1063         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1064         int rc;
1065
1066         bp->rx_queues = (void *)eth_dev->data->rx_queues;
1067         bp->tx_queues = (void *)eth_dev->data->tx_queues;
1068         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1069         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1070
1071         rc = is_bnxt_in_error(bp);
1072         if (rc)
1073                 return rc;
1074
1075         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1076                 rc = bnxt_hwrm_check_vf_rings(bp);
1077                 if (rc) {
1078                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1079                         return -ENOSPC;
1080                 }
1081
1082                 /* If a resource has already been allocated - in this case
1083                  * it is the async completion ring, free it. Reallocate it after
1084                  * resource reservation. This will ensure the resource counts
1085                  * are calculated correctly.
1086                  */
1087
1088                 pthread_mutex_lock(&bp->def_cp_lock);
1089
1090                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1091                         bnxt_disable_int(bp);
1092                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
1093                 }
1094
1095                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1096                 if (rc) {
1097                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1098                         pthread_mutex_unlock(&bp->def_cp_lock);
1099                         return -ENOSPC;
1100                 }
1101
1102                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1103                         rc = bnxt_alloc_async_cp_ring(bp);
1104                         if (rc) {
1105                                 pthread_mutex_unlock(&bp->def_cp_lock);
1106                                 return rc;
1107                         }
1108                         bnxt_enable_int(bp);
1109                 }
1110
1111                 pthread_mutex_unlock(&bp->def_cp_lock);
1112         }
1113
1114         /* Inherit new configurations */
1115         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1116             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1117             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1118                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1119             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1120             bp->max_stat_ctx)
1121                 goto resource_error;
1122
1123         if (BNXT_HAS_RING_GRPS(bp) &&
1124             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1125                 goto resource_error;
1126
1127         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1128             bp->max_vnics < eth_dev->data->nb_rx_queues)
1129                 goto resource_error;
1130
1131         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1132         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1133
1134         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1135                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1136         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1137
1138         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1139                 eth_dev->data->mtu =
1140                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1141                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1142                         BNXT_NUM_VLANS;
1143                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1144         }
1145         return 0;
1146
1147 resource_error:
1148         PMD_DRV_LOG(ERR,
1149                     "Insufficient resources to support requested config\n");
1150         PMD_DRV_LOG(ERR,
1151                     "Num Queues Requested: Tx %d, Rx %d\n",
1152                     eth_dev->data->nb_tx_queues,
1153                     eth_dev->data->nb_rx_queues);
1154         PMD_DRV_LOG(ERR,
1155                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1156                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1157                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1158         return -ENOSPC;
1159 }
1160
1161 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1162 {
1163         struct rte_eth_link *link = &eth_dev->data->dev_link;
1164
1165         if (link->link_status)
1166                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1167                         eth_dev->data->port_id,
1168                         (uint32_t)link->link_speed,
1169                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1170                         ("full-duplex") : ("half-duplex\n"));
1171         else
1172                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1173                         eth_dev->data->port_id);
1174 }
1175
1176 /*
1177  * Determine whether the current configuration requires support for scattered
1178  * receive; return 1 if scattered receive is required and 0 if not.
1179  */
1180 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1181 {
1182         uint16_t buf_size;
1183         int i;
1184
1185         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1186                 return 1;
1187
1188         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO)
1189                 return 1;
1190
1191         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1192                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1193
1194                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1195                                       RTE_PKTMBUF_HEADROOM);
1196                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1197                         return 1;
1198         }
1199         return 0;
1200 }
1201
1202 static eth_rx_burst_t
1203 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1204 {
1205         struct bnxt *bp = eth_dev->data->dev_private;
1206
1207         /* Disable vector mode RX for Stingray2 for now */
1208         if (BNXT_CHIP_SR2(bp)) {
1209                 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1210                 return bnxt_recv_pkts;
1211         }
1212
1213 #if (defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)) && \
1214         !defined(RTE_LIBRTE_IEEE1588)
1215
1216         /* Vector mode receive cannot be enabled if scattered rx is in use. */
1217         if (eth_dev->data->scattered_rx)
1218                 goto use_scalar_rx;
1219
1220         /*
1221          * Vector mode receive cannot be enabled if Truflow is enabled or if
1222          * asynchronous completions and receive completions can be placed in
1223          * the same completion ring.
1224          */
1225         if (BNXT_TRUFLOW_EN(bp) || !BNXT_NUM_ASYNC_CPR(bp))
1226                 goto use_scalar_rx;
1227
1228         /*
1229          * Vector mode receive cannot be enabled if any receive offloads outside
1230          * a limited subset have been enabled.
1231          */
1232         if (eth_dev->data->dev_conf.rxmode.offloads &
1233                 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1234                   DEV_RX_OFFLOAD_KEEP_CRC |
1235                   DEV_RX_OFFLOAD_JUMBO_FRAME |
1236                   DEV_RX_OFFLOAD_IPV4_CKSUM |
1237                   DEV_RX_OFFLOAD_UDP_CKSUM |
1238                   DEV_RX_OFFLOAD_TCP_CKSUM |
1239                   DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1240                   DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1241                   DEV_RX_OFFLOAD_RSS_HASH |
1242                   DEV_RX_OFFLOAD_VLAN_FILTER))
1243                 goto use_scalar_rx;
1244
1245 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1246         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1247             rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1248                 PMD_DRV_LOG(INFO,
1249                             "Using AVX2 vector mode receive for port %d\n",
1250                             eth_dev->data->port_id);
1251                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1252                 return bnxt_recv_pkts_vec_avx2;
1253         }
1254  #endif
1255         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1256                 PMD_DRV_LOG(INFO,
1257                             "Using SSE vector mode receive for port %d\n",
1258                             eth_dev->data->port_id);
1259                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1260                 return bnxt_recv_pkts_vec;
1261         }
1262
1263 use_scalar_rx:
1264         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1265                     eth_dev->data->port_id);
1266         PMD_DRV_LOG(INFO,
1267                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1268                     eth_dev->data->port_id,
1269                     eth_dev->data->scattered_rx,
1270                     eth_dev->data->dev_conf.rxmode.offloads);
1271 #endif
1272         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1273         return bnxt_recv_pkts;
1274 }
1275
1276 static eth_tx_burst_t
1277 bnxt_transmit_function(struct rte_eth_dev *eth_dev)
1278 {
1279         struct bnxt *bp = eth_dev->data->dev_private;
1280
1281         /* Disable vector mode TX for Stingray2 for now */
1282         if (BNXT_CHIP_SR2(bp))
1283                 return bnxt_xmit_pkts;
1284
1285 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) && \
1286         !defined(RTE_LIBRTE_IEEE1588)
1287         uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1288
1289         /*
1290          * Vector mode transmit can be enabled only if not using scatter rx
1291          * or tx offloads.
1292          */
1293         if (eth_dev->data->scattered_rx ||
1294             (offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) ||
1295             BNXT_TRUFLOW_EN(bp))
1296                 goto use_scalar_tx;
1297
1298 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1299         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1300             rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1301                 PMD_DRV_LOG(INFO,
1302                             "Using AVX2 vector mode transmit for port %d\n",
1303                             eth_dev->data->port_id);
1304                 return bnxt_xmit_pkts_vec_avx2;
1305         }
1306 #endif
1307         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1308                 PMD_DRV_LOG(INFO,
1309                             "Using SSE vector mode transmit for port %d\n",
1310                             eth_dev->data->port_id);
1311                 return bnxt_xmit_pkts_vec;
1312         }
1313
1314 use_scalar_tx:
1315         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1316                     eth_dev->data->port_id);
1317         PMD_DRV_LOG(INFO,
1318                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1319                     eth_dev->data->port_id,
1320                     eth_dev->data->scattered_rx,
1321                     offloads);
1322 #endif
1323         return bnxt_xmit_pkts;
1324 }
1325
1326 static int bnxt_handle_if_change_status(struct bnxt *bp)
1327 {
1328         int rc;
1329
1330         /* Since fw has undergone a reset and lost all contexts,
1331          * set fatal flag to not issue hwrm during cleanup
1332          */
1333         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1334         bnxt_uninit_resources(bp, true);
1335
1336         /* clear fatal flag so that re-init happens */
1337         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1338         rc = bnxt_init_resources(bp, true);
1339
1340         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1341
1342         return rc;
1343 }
1344
1345 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1346 {
1347         struct bnxt *bp = eth_dev->data->dev_private;
1348         int rc = 0;
1349
1350         if (!BNXT_SINGLE_PF(bp))
1351                 return -ENOTSUP;
1352
1353         if (!bp->link_info->link_up)
1354                 rc = bnxt_set_hwrm_link_config(bp, true);
1355         if (!rc)
1356                 eth_dev->data->dev_link.link_status = 1;
1357
1358         bnxt_print_link_info(eth_dev);
1359         return rc;
1360 }
1361
1362 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1363 {
1364         struct bnxt *bp = eth_dev->data->dev_private;
1365
1366         if (!BNXT_SINGLE_PF(bp))
1367                 return -ENOTSUP;
1368
1369         eth_dev->data->dev_link.link_status = 0;
1370         bnxt_set_hwrm_link_config(bp, false);
1371         bp->link_info->link_up = 0;
1372
1373         return 0;
1374 }
1375
1376 static void bnxt_free_switch_domain(struct bnxt *bp)
1377 {
1378         int rc = 0;
1379
1380         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)))
1381                 return;
1382
1383         rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1384         if (rc)
1385                 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1386                             bp->switch_domain_id, rc);
1387 }
1388
1389 static void bnxt_ptp_get_current_time(void *arg)
1390 {
1391         struct bnxt *bp = arg;
1392         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1393         int rc;
1394
1395         rc = is_bnxt_in_error(bp);
1396         if (rc)
1397                 return;
1398
1399         if (!ptp)
1400                 return;
1401
1402         bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1403                                 &ptp->current_time);
1404
1405         rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1406         if (rc != 0) {
1407                 PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n");
1408                 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1409         }
1410 }
1411
1412 static int bnxt_schedule_ptp_alarm(struct bnxt *bp)
1413 {
1414         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1415         int rc;
1416
1417         if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED)
1418                 return 0;
1419
1420         bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1421                                 &ptp->current_time);
1422
1423         rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1424         return rc;
1425 }
1426
1427 static void bnxt_cancel_ptp_alarm(struct bnxt *bp)
1428 {
1429         if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) {
1430                 rte_eal_alarm_cancel(bnxt_ptp_get_current_time, (void *)bp);
1431                 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1432         }
1433 }
1434
1435 static void bnxt_ptp_stop(struct bnxt *bp)
1436 {
1437         bnxt_cancel_ptp_alarm(bp);
1438         bp->flags2 &= ~BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1439 }
1440
1441 static int bnxt_ptp_start(struct bnxt *bp)
1442 {
1443         int rc;
1444
1445         rc = bnxt_schedule_ptp_alarm(bp);
1446         if (rc != 0) {
1447                 PMD_DRV_LOG(ERR, "Failed to schedule PTP alarm\n");
1448         } else {
1449                 bp->flags2 |= BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1450                 bp->flags2 |= BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1451         }
1452
1453         return rc;
1454 }
1455
1456 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev)
1457 {
1458         struct bnxt *bp = eth_dev->data->dev_private;
1459         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1460         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1461         struct rte_eth_link link;
1462         int ret;
1463
1464         eth_dev->data->dev_started = 0;
1465         eth_dev->data->scattered_rx = 0;
1466
1467         /* Prevent crashes when queues are still in use */
1468         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1469         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1470
1471         bnxt_disable_int(bp);
1472
1473         /* disable uio/vfio intr/eventfd mapping */
1474         rte_intr_disable(intr_handle);
1475
1476         /* Stop the child representors for this device */
1477         ret = bnxt_rep_stop_all(bp);
1478         if (ret != 0)
1479                 return ret;
1480
1481         /* delete the bnxt ULP port details */
1482         bnxt_ulp_port_deinit(bp);
1483
1484         bnxt_cancel_fw_health_check(bp);
1485
1486         if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1487                 bnxt_cancel_ptp_alarm(bp);
1488
1489         /* Do not bring link down during reset recovery */
1490         if (!is_bnxt_in_error(bp)) {
1491                 bnxt_dev_set_link_down_op(eth_dev);
1492                 /* Wait for link to be reset */
1493                 if (BNXT_SINGLE_PF(bp))
1494                         rte_delay_ms(500);
1495                 /* clear the recorded link status */
1496                 memset(&link, 0, sizeof(link));
1497                 rte_eth_linkstatus_set(eth_dev, &link);
1498         }
1499
1500         /* Clean queue intr-vector mapping */
1501         rte_intr_efd_disable(intr_handle);
1502         if (intr_handle->intr_vec != NULL) {
1503                 rte_free(intr_handle->intr_vec);
1504                 intr_handle->intr_vec = NULL;
1505         }
1506
1507         bnxt_hwrm_port_clr_stats(bp);
1508         bnxt_free_tx_mbufs(bp);
1509         bnxt_free_rx_mbufs(bp);
1510         /* Process any remaining notifications in default completion queue */
1511         bnxt_int_handler(eth_dev);
1512         bnxt_shutdown_nic(bp);
1513         bnxt_hwrm_if_change(bp, false);
1514
1515         bnxt_free_prev_ring_stats(bp);
1516         rte_free(bp->mark_table);
1517         bp->mark_table = NULL;
1518
1519         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1520         bp->rx_cosq_cnt = 0;
1521         /* All filters are deleted on a port stop. */
1522         if (BNXT_FLOW_XSTATS_EN(bp))
1523                 bp->flow_stat->flow_count = 0;
1524
1525         return 0;
1526 }
1527
1528 /* Unload the driver, release resources */
1529 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1530 {
1531         struct bnxt *bp = eth_dev->data->dev_private;
1532
1533         pthread_mutex_lock(&bp->err_recovery_lock);
1534         if (bp->flags & BNXT_FLAG_FW_RESET) {
1535                 PMD_DRV_LOG(ERR,
1536                             "Adapter recovering from error..Please retry\n");
1537                 pthread_mutex_unlock(&bp->err_recovery_lock);
1538                 return -EAGAIN;
1539         }
1540         pthread_mutex_unlock(&bp->err_recovery_lock);
1541
1542         return bnxt_dev_stop(eth_dev);
1543 }
1544
1545 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1546 {
1547         struct bnxt *bp = eth_dev->data->dev_private;
1548         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1549         int vlan_mask = 0;
1550         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1551
1552         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1553                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1554                 return -EINVAL;
1555         }
1556
1557         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1558                 PMD_DRV_LOG(ERR,
1559                             "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1560                             bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1561
1562         do {
1563                 rc = bnxt_hwrm_if_change(bp, true);
1564                 if (rc == 0 || rc != -EAGAIN)
1565                         break;
1566
1567                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1568         } while (retry_cnt--);
1569
1570         if (rc)
1571                 return rc;
1572
1573         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1574                 rc = bnxt_handle_if_change_status(bp);
1575                 if (rc)
1576                         return rc;
1577         }
1578
1579         bnxt_enable_int(bp);
1580
1581         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1582
1583         rc = bnxt_start_nic(bp);
1584         if (rc)
1585                 goto error;
1586
1587         rc = bnxt_alloc_prev_ring_stats(bp);
1588         if (rc)
1589                 goto error;
1590
1591         eth_dev->data->dev_started = 1;
1592
1593         bnxt_link_update_op(eth_dev, 1);
1594
1595         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1596                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1597         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1598                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1599         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1600         if (rc)
1601                 goto error;
1602
1603         /* Initialize bnxt ULP port details */
1604         rc = bnxt_ulp_port_init(bp);
1605         if (rc)
1606                 goto error;
1607
1608         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1609         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1610
1611         bnxt_schedule_fw_health_check(bp);
1612
1613         if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1614                 bnxt_schedule_ptp_alarm(bp);
1615
1616         return 0;
1617
1618 error:
1619         bnxt_dev_stop(eth_dev);
1620         return rc;
1621 }
1622
1623 static void
1624 bnxt_uninit_locks(struct bnxt *bp)
1625 {
1626         pthread_mutex_destroy(&bp->flow_lock);
1627         pthread_mutex_destroy(&bp->def_cp_lock);
1628         pthread_mutex_destroy(&bp->health_check_lock);
1629         pthread_mutex_destroy(&bp->err_recovery_lock);
1630         if (bp->rep_info) {
1631                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
1632                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
1633         }
1634 }
1635
1636 static void bnxt_drv_uninit(struct bnxt *bp)
1637 {
1638         bnxt_free_leds_info(bp);
1639         bnxt_free_cos_queues(bp);
1640         bnxt_free_link_info(bp);
1641         bnxt_free_parent_info(bp);
1642         bnxt_uninit_locks(bp);
1643
1644         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1645         bp->tx_mem_zone = NULL;
1646         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1647         bp->rx_mem_zone = NULL;
1648
1649         bnxt_free_vf_info(bp);
1650         bnxt_free_pf_info(bp);
1651
1652         rte_free(bp->grp_info);
1653         bp->grp_info = NULL;
1654 }
1655
1656 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1657 {
1658         struct bnxt *bp = eth_dev->data->dev_private;
1659         int ret = 0;
1660
1661         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1662                 return 0;
1663
1664         pthread_mutex_lock(&bp->err_recovery_lock);
1665         if (bp->flags & BNXT_FLAG_FW_RESET) {
1666                 PMD_DRV_LOG(ERR,
1667                             "Adapter recovering from error...Please retry\n");
1668                 pthread_mutex_unlock(&bp->err_recovery_lock);
1669                 return -EAGAIN;
1670         }
1671         pthread_mutex_unlock(&bp->err_recovery_lock);
1672
1673         /* cancel the recovery handler before remove dev */
1674         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1675         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1676         bnxt_cancel_fc_thread(bp);
1677
1678         if (eth_dev->data->dev_started)
1679                 ret = bnxt_dev_stop(eth_dev);
1680
1681         bnxt_uninit_resources(bp, false);
1682
1683         bnxt_drv_uninit(bp);
1684
1685         return ret;
1686 }
1687
1688 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1689                                     uint32_t index)
1690 {
1691         struct bnxt *bp = eth_dev->data->dev_private;
1692         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1693         struct bnxt_vnic_info *vnic;
1694         struct bnxt_filter_info *filter, *temp_filter;
1695         uint32_t i;
1696
1697         if (is_bnxt_in_error(bp))
1698                 return;
1699
1700         /*
1701          * Loop through all VNICs from the specified filter flow pools to
1702          * remove the corresponding MAC addr filter
1703          */
1704         for (i = 0; i < bp->nr_vnics; i++) {
1705                 if (!(pool_mask & (1ULL << i)))
1706                         continue;
1707
1708                 vnic = &bp->vnic_info[i];
1709                 filter = STAILQ_FIRST(&vnic->filter);
1710                 while (filter) {
1711                         temp_filter = STAILQ_NEXT(filter, next);
1712                         if (filter->mac_index == index) {
1713                                 STAILQ_REMOVE(&vnic->filter, filter,
1714                                                 bnxt_filter_info, next);
1715                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1716                                 bnxt_free_filter(bp, filter);
1717                         }
1718                         filter = temp_filter;
1719                 }
1720         }
1721 }
1722
1723 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1724                                struct rte_ether_addr *mac_addr, uint32_t index,
1725                                uint32_t pool)
1726 {
1727         struct bnxt_filter_info *filter;
1728         int rc = 0;
1729
1730         /* Attach requested MAC address to the new l2_filter */
1731         STAILQ_FOREACH(filter, &vnic->filter, next) {
1732                 if (filter->mac_index == index) {
1733                         PMD_DRV_LOG(DEBUG,
1734                                     "MAC addr already existed for pool %d\n",
1735                                     pool);
1736                         return 0;
1737                 }
1738         }
1739
1740         filter = bnxt_alloc_filter(bp);
1741         if (!filter) {
1742                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1743                 return -ENODEV;
1744         }
1745
1746         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1747          * if the MAC that's been programmed now is a different one, then,
1748          * copy that addr to filter->l2_addr
1749          */
1750         if (mac_addr)
1751                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1752         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1753
1754         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1755         if (!rc) {
1756                 filter->mac_index = index;
1757                 if (filter->mac_index == 0)
1758                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1759                 else
1760                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1761         } else {
1762                 bnxt_free_filter(bp, filter);
1763         }
1764
1765         return rc;
1766 }
1767
1768 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1769                                 struct rte_ether_addr *mac_addr,
1770                                 uint32_t index, uint32_t pool)
1771 {
1772         struct bnxt *bp = eth_dev->data->dev_private;
1773         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1774         int rc = 0;
1775
1776         rc = is_bnxt_in_error(bp);
1777         if (rc)
1778                 return rc;
1779
1780         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1781                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1782                 return -ENOTSUP;
1783         }
1784
1785         if (!vnic) {
1786                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1787                 return -EINVAL;
1788         }
1789
1790         /* Filter settings will get applied when port is started */
1791         if (!eth_dev->data->dev_started)
1792                 return 0;
1793
1794         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1795
1796         return rc;
1797 }
1798
1799 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1800 {
1801         int rc = 0;
1802         struct bnxt *bp = eth_dev->data->dev_private;
1803         struct rte_eth_link new;
1804         int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1805                         BNXT_MIN_LINK_WAIT_CNT;
1806
1807         rc = is_bnxt_in_error(bp);
1808         if (rc)
1809                 return rc;
1810
1811         memset(&new, 0, sizeof(new));
1812
1813         if (bp->link_info == NULL)
1814                 goto out;
1815
1816         do {
1817                 /* Retrieve link info from hardware */
1818                 rc = bnxt_get_hwrm_link_config(bp, &new);
1819                 if (rc) {
1820                         new.link_speed = ETH_LINK_SPEED_100M;
1821                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1822                         PMD_DRV_LOG(ERR,
1823                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1824                         goto out;
1825                 }
1826
1827                 if (!wait_to_complete || new.link_status)
1828                         break;
1829
1830                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1831         } while (cnt--);
1832
1833         /* Only single function PF can bring phy down.
1834          * When port is stopped, report link down for VF/MH/NPAR functions.
1835          */
1836         if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1837                 memset(&new, 0, sizeof(new));
1838
1839 out:
1840         /* Timed out or success */
1841         if (new.link_status != eth_dev->data->dev_link.link_status ||
1842             new.link_speed != eth_dev->data->dev_link.link_speed) {
1843                 rte_eth_linkstatus_set(eth_dev, &new);
1844
1845                 rte_eth_dev_callback_process(eth_dev,
1846                                              RTE_ETH_EVENT_INTR_LSC,
1847                                              NULL);
1848
1849                 bnxt_print_link_info(eth_dev);
1850         }
1851
1852         return rc;
1853 }
1854
1855 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1856 {
1857         struct bnxt *bp = eth_dev->data->dev_private;
1858         struct bnxt_vnic_info *vnic;
1859         uint32_t old_flags;
1860         int rc;
1861
1862         rc = is_bnxt_in_error(bp);
1863         if (rc)
1864                 return rc;
1865
1866         /* Filter settings will get applied when port is started */
1867         if (!eth_dev->data->dev_started)
1868                 return 0;
1869
1870         if (bp->vnic_info == NULL)
1871                 return 0;
1872
1873         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1874
1875         old_flags = vnic->flags;
1876         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1877         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1878         if (rc != 0)
1879                 vnic->flags = old_flags;
1880
1881         return rc;
1882 }
1883
1884 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1885 {
1886         struct bnxt *bp = eth_dev->data->dev_private;
1887         struct bnxt_vnic_info *vnic;
1888         uint32_t old_flags;
1889         int rc;
1890
1891         rc = is_bnxt_in_error(bp);
1892         if (rc)
1893                 return rc;
1894
1895         /* Filter settings will get applied when port is started */
1896         if (!eth_dev->data->dev_started)
1897                 return 0;
1898
1899         if (bp->vnic_info == NULL)
1900                 return 0;
1901
1902         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1903
1904         old_flags = vnic->flags;
1905         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1906         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1907         if (rc != 0)
1908                 vnic->flags = old_flags;
1909
1910         return rc;
1911 }
1912
1913 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1914 {
1915         struct bnxt *bp = eth_dev->data->dev_private;
1916         struct bnxt_vnic_info *vnic;
1917         uint32_t old_flags;
1918         int rc;
1919
1920         rc = is_bnxt_in_error(bp);
1921         if (rc)
1922                 return rc;
1923
1924         /* Filter settings will get applied when port is started */
1925         if (!eth_dev->data->dev_started)
1926                 return 0;
1927
1928         if (bp->vnic_info == NULL)
1929                 return 0;
1930
1931         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1932
1933         old_flags = vnic->flags;
1934         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1935         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1936         if (rc != 0)
1937                 vnic->flags = old_flags;
1938
1939         return rc;
1940 }
1941
1942 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1943 {
1944         struct bnxt *bp = eth_dev->data->dev_private;
1945         struct bnxt_vnic_info *vnic;
1946         uint32_t old_flags;
1947         int rc;
1948
1949         rc = is_bnxt_in_error(bp);
1950         if (rc)
1951                 return rc;
1952
1953         /* Filter settings will get applied when port is started */
1954         if (!eth_dev->data->dev_started)
1955                 return 0;
1956
1957         if (bp->vnic_info == NULL)
1958                 return 0;
1959
1960         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1961
1962         old_flags = vnic->flags;
1963         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1964         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1965         if (rc != 0)
1966                 vnic->flags = old_flags;
1967
1968         return rc;
1969 }
1970
1971 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1972 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1973 {
1974         if (qid >= bp->rx_nr_rings)
1975                 return NULL;
1976
1977         return bp->eth_dev->data->rx_queues[qid];
1978 }
1979
1980 /* Return rxq corresponding to a given rss table ring/group ID. */
1981 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1982 {
1983         struct bnxt_rx_queue *rxq;
1984         unsigned int i;
1985
1986         if (!BNXT_HAS_RING_GRPS(bp)) {
1987                 for (i = 0; i < bp->rx_nr_rings; i++) {
1988                         rxq = bp->eth_dev->data->rx_queues[i];
1989                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1990                                 return rxq->index;
1991                 }
1992         } else {
1993                 for (i = 0; i < bp->rx_nr_rings; i++) {
1994                         if (bp->grp_info[i].fw_grp_id == fwr)
1995                                 return i;
1996                 }
1997         }
1998
1999         return INVALID_HW_RING_ID;
2000 }
2001
2002 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
2003                             struct rte_eth_rss_reta_entry64 *reta_conf,
2004                             uint16_t reta_size)
2005 {
2006         struct bnxt *bp = eth_dev->data->dev_private;
2007         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2008         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2009         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
2010         uint16_t idx, sft;
2011         int i, rc;
2012
2013         rc = is_bnxt_in_error(bp);
2014         if (rc)
2015                 return rc;
2016
2017         if (!vnic->rss_table)
2018                 return -EINVAL;
2019
2020         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
2021                 return -EINVAL;
2022
2023         if (reta_size != tbl_size) {
2024                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2025                         "(%d) must equal the size supported by the hardware "
2026                         "(%d)\n", reta_size, tbl_size);
2027                 return -EINVAL;
2028         }
2029
2030         for (i = 0; i < reta_size; i++) {
2031                 struct bnxt_rx_queue *rxq;
2032
2033                 idx = i / RTE_RETA_GROUP_SIZE;
2034                 sft = i % RTE_RETA_GROUP_SIZE;
2035
2036                 if (!(reta_conf[idx].mask & (1ULL << sft)))
2037                         continue;
2038
2039                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
2040                 if (!rxq) {
2041                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
2042                         return -EINVAL;
2043                 }
2044
2045                 if (BNXT_CHIP_P5(bp)) {
2046                         vnic->rss_table[i * 2] =
2047                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
2048                         vnic->rss_table[i * 2 + 1] =
2049                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
2050                 } else {
2051                         vnic->rss_table[i] =
2052                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
2053                 }
2054         }
2055
2056         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2057         return rc;
2058 }
2059
2060 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
2061                               struct rte_eth_rss_reta_entry64 *reta_conf,
2062                               uint16_t reta_size)
2063 {
2064         struct bnxt *bp = eth_dev->data->dev_private;
2065         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2066         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
2067         uint16_t idx, sft, i;
2068         int rc;
2069
2070         rc = is_bnxt_in_error(bp);
2071         if (rc)
2072                 return rc;
2073
2074         if (!vnic)
2075                 return -EINVAL;
2076         if (!vnic->rss_table)
2077                 return -EINVAL;
2078
2079         if (reta_size != tbl_size) {
2080                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2081                         "(%d) must equal the size supported by the hardware "
2082                         "(%d)\n", reta_size, tbl_size);
2083                 return -EINVAL;
2084         }
2085
2086         for (idx = 0, i = 0; i < reta_size; i++) {
2087                 idx = i / RTE_RETA_GROUP_SIZE;
2088                 sft = i % RTE_RETA_GROUP_SIZE;
2089
2090                 if (reta_conf[idx].mask & (1ULL << sft)) {
2091                         uint16_t qid;
2092
2093                         if (BNXT_CHIP_P5(bp))
2094                                 qid = bnxt_rss_to_qid(bp,
2095                                                       vnic->rss_table[i * 2]);
2096                         else
2097                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
2098
2099                         if (qid == INVALID_HW_RING_ID) {
2100                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
2101                                 return -EINVAL;
2102                         }
2103                         reta_conf[idx].reta[sft] = qid;
2104                 }
2105         }
2106
2107         return 0;
2108 }
2109
2110 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
2111                                    struct rte_eth_rss_conf *rss_conf)
2112 {
2113         struct bnxt *bp = eth_dev->data->dev_private;
2114         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2115         struct bnxt_vnic_info *vnic;
2116         int rc;
2117
2118         rc = is_bnxt_in_error(bp);
2119         if (rc)
2120                 return rc;
2121
2122         /*
2123          * If RSS enablement were different than dev_configure,
2124          * then return -EINVAL
2125          */
2126         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
2127                 if (!rss_conf->rss_hf)
2128                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
2129         } else {
2130                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
2131                         return -EINVAL;
2132         }
2133
2134         bp->flags |= BNXT_FLAG_UPDATE_HASH;
2135         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
2136                rss_conf,
2137                sizeof(*rss_conf));
2138
2139         /* Update the default RSS VNIC(s) */
2140         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2141         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
2142         vnic->hash_mode =
2143                 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
2144                                             ETH_RSS_LEVEL(rss_conf->rss_hf));
2145
2146         /*
2147          * If hashkey is not specified, use the previously configured
2148          * hashkey
2149          */
2150         if (!rss_conf->rss_key)
2151                 goto rss_config;
2152
2153         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
2154                 PMD_DRV_LOG(ERR,
2155                             "Invalid hashkey length, should be %d bytes\n",
2156                             HW_HASH_KEY_SIZE);
2157                 return -EINVAL;
2158         }
2159         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
2160
2161 rss_config:
2162         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2163         return rc;
2164 }
2165
2166 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
2167                                      struct rte_eth_rss_conf *rss_conf)
2168 {
2169         struct bnxt *bp = eth_dev->data->dev_private;
2170         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2171         int len, rc;
2172         uint32_t hash_types;
2173
2174         rc = is_bnxt_in_error(bp);
2175         if (rc)
2176                 return rc;
2177
2178         /* RSS configuration is the same for all VNICs */
2179         if (vnic && vnic->rss_hash_key) {
2180                 if (rss_conf->rss_key) {
2181                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
2182                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
2183                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
2184                 }
2185
2186                 hash_types = vnic->hash_type;
2187                 rss_conf->rss_hf = 0;
2188                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
2189                         rss_conf->rss_hf |= ETH_RSS_IPV4;
2190                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
2191                 }
2192                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
2193                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2194                         hash_types &=
2195                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
2196                 }
2197                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
2198                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2199                         hash_types &=
2200                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
2201                 }
2202                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
2203                         rss_conf->rss_hf |= ETH_RSS_IPV6;
2204                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
2205                 }
2206                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
2207                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2208                         hash_types &=
2209                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
2210                 }
2211                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
2212                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2213                         hash_types &=
2214                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2215                 }
2216
2217                 rss_conf->rss_hf |=
2218                         bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2219
2220                 if (hash_types) {
2221                         PMD_DRV_LOG(ERR,
2222                                 "Unknown RSS config from firmware (%08x), RSS disabled",
2223                                 vnic->hash_type);
2224                         return -ENOTSUP;
2225                 }
2226         } else {
2227                 rss_conf->rss_hf = 0;
2228         }
2229         return 0;
2230 }
2231
2232 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2233                                struct rte_eth_fc_conf *fc_conf)
2234 {
2235         struct bnxt *bp = dev->data->dev_private;
2236         struct rte_eth_link link_info;
2237         int rc;
2238
2239         rc = is_bnxt_in_error(bp);
2240         if (rc)
2241                 return rc;
2242
2243         rc = bnxt_get_hwrm_link_config(bp, &link_info);
2244         if (rc)
2245                 return rc;
2246
2247         memset(fc_conf, 0, sizeof(*fc_conf));
2248         if (bp->link_info->auto_pause)
2249                 fc_conf->autoneg = 1;
2250         switch (bp->link_info->pause) {
2251         case 0:
2252                 fc_conf->mode = RTE_FC_NONE;
2253                 break;
2254         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2255                 fc_conf->mode = RTE_FC_TX_PAUSE;
2256                 break;
2257         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2258                 fc_conf->mode = RTE_FC_RX_PAUSE;
2259                 break;
2260         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2261                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2262                 fc_conf->mode = RTE_FC_FULL;
2263                 break;
2264         }
2265         return 0;
2266 }
2267
2268 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2269                                struct rte_eth_fc_conf *fc_conf)
2270 {
2271         struct bnxt *bp = dev->data->dev_private;
2272         int rc;
2273
2274         rc = is_bnxt_in_error(bp);
2275         if (rc)
2276                 return rc;
2277
2278         if (!BNXT_SINGLE_PF(bp)) {
2279                 PMD_DRV_LOG(ERR,
2280                             "Flow Control Settings cannot be modified on VF or on shared PF\n");
2281                 return -ENOTSUP;
2282         }
2283
2284         switch (fc_conf->mode) {
2285         case RTE_FC_NONE:
2286                 bp->link_info->auto_pause = 0;
2287                 bp->link_info->force_pause = 0;
2288                 break;
2289         case RTE_FC_RX_PAUSE:
2290                 if (fc_conf->autoneg) {
2291                         bp->link_info->auto_pause =
2292                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2293                         bp->link_info->force_pause = 0;
2294                 } else {
2295                         bp->link_info->auto_pause = 0;
2296                         bp->link_info->force_pause =
2297                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2298                 }
2299                 break;
2300         case RTE_FC_TX_PAUSE:
2301                 if (fc_conf->autoneg) {
2302                         bp->link_info->auto_pause =
2303                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2304                         bp->link_info->force_pause = 0;
2305                 } else {
2306                         bp->link_info->auto_pause = 0;
2307                         bp->link_info->force_pause =
2308                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2309                 }
2310                 break;
2311         case RTE_FC_FULL:
2312                 if (fc_conf->autoneg) {
2313                         bp->link_info->auto_pause =
2314                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2315                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2316                         bp->link_info->force_pause = 0;
2317                 } else {
2318                         bp->link_info->auto_pause = 0;
2319                         bp->link_info->force_pause =
2320                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2321                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2322                 }
2323                 break;
2324         }
2325         return bnxt_set_hwrm_link_config(bp, true);
2326 }
2327
2328 /* Add UDP tunneling port */
2329 static int
2330 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2331                          struct rte_eth_udp_tunnel *udp_tunnel)
2332 {
2333         struct bnxt *bp = eth_dev->data->dev_private;
2334         uint16_t tunnel_type = 0;
2335         int rc = 0;
2336
2337         rc = is_bnxt_in_error(bp);
2338         if (rc)
2339                 return rc;
2340
2341         switch (udp_tunnel->prot_type) {
2342         case RTE_TUNNEL_TYPE_VXLAN:
2343                 if (bp->vxlan_port_cnt) {
2344                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2345                                 udp_tunnel->udp_port);
2346                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2347                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2348                                 return -ENOSPC;
2349                         }
2350                         bp->vxlan_port_cnt++;
2351                         return 0;
2352                 }
2353                 tunnel_type =
2354                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2355                 bp->vxlan_port_cnt++;
2356                 break;
2357         case RTE_TUNNEL_TYPE_GENEVE:
2358                 if (bp->geneve_port_cnt) {
2359                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2360                                 udp_tunnel->udp_port);
2361                         if (bp->geneve_port != udp_tunnel->udp_port) {
2362                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2363                                 return -ENOSPC;
2364                         }
2365                         bp->geneve_port_cnt++;
2366                         return 0;
2367                 }
2368                 tunnel_type =
2369                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2370                 bp->geneve_port_cnt++;
2371                 break;
2372         default:
2373                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2374                 return -ENOTSUP;
2375         }
2376         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2377                                              tunnel_type);
2378         return rc;
2379 }
2380
2381 static int
2382 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2383                          struct rte_eth_udp_tunnel *udp_tunnel)
2384 {
2385         struct bnxt *bp = eth_dev->data->dev_private;
2386         uint16_t tunnel_type = 0;
2387         uint16_t port = 0;
2388         int rc = 0;
2389
2390         rc = is_bnxt_in_error(bp);
2391         if (rc)
2392                 return rc;
2393
2394         switch (udp_tunnel->prot_type) {
2395         case RTE_TUNNEL_TYPE_VXLAN:
2396                 if (!bp->vxlan_port_cnt) {
2397                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2398                         return -EINVAL;
2399                 }
2400                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2401                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2402                                 udp_tunnel->udp_port, bp->vxlan_port);
2403                         return -EINVAL;
2404                 }
2405                 if (--bp->vxlan_port_cnt)
2406                         return 0;
2407
2408                 tunnel_type =
2409                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2410                 port = bp->vxlan_fw_dst_port_id;
2411                 break;
2412         case RTE_TUNNEL_TYPE_GENEVE:
2413                 if (!bp->geneve_port_cnt) {
2414                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2415                         return -EINVAL;
2416                 }
2417                 if (bp->geneve_port != udp_tunnel->udp_port) {
2418                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2419                                 udp_tunnel->udp_port, bp->geneve_port);
2420                         return -EINVAL;
2421                 }
2422                 if (--bp->geneve_port_cnt)
2423                         return 0;
2424
2425                 tunnel_type =
2426                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2427                 port = bp->geneve_fw_dst_port_id;
2428                 break;
2429         default:
2430                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2431                 return -ENOTSUP;
2432         }
2433
2434         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2435         return rc;
2436 }
2437
2438 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2439 {
2440         struct bnxt_filter_info *filter;
2441         struct bnxt_vnic_info *vnic;
2442         int rc = 0;
2443         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2444
2445         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2446         filter = STAILQ_FIRST(&vnic->filter);
2447         while (filter) {
2448                 /* Search for this matching MAC+VLAN filter */
2449                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2450                         /* Delete the filter */
2451                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2452                         if (rc)
2453                                 return rc;
2454                         STAILQ_REMOVE(&vnic->filter, filter,
2455                                       bnxt_filter_info, next);
2456                         bnxt_free_filter(bp, filter);
2457                         PMD_DRV_LOG(INFO,
2458                                     "Deleted vlan filter for %d\n",
2459                                     vlan_id);
2460                         return 0;
2461                 }
2462                 filter = STAILQ_NEXT(filter, next);
2463         }
2464         return -ENOENT;
2465 }
2466
2467 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2468 {
2469         struct bnxt_filter_info *filter;
2470         struct bnxt_vnic_info *vnic;
2471         int rc = 0;
2472         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2473                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2474         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2475
2476         /* Implementation notes on the use of VNIC in this command:
2477          *
2478          * By default, these filters belong to default vnic for the function.
2479          * Once these filters are set up, only destination VNIC can be modified.
2480          * If the destination VNIC is not specified in this command,
2481          * then the HWRM shall only create an l2 context id.
2482          */
2483
2484         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2485         filter = STAILQ_FIRST(&vnic->filter);
2486         /* Check if the VLAN has already been added */
2487         while (filter) {
2488                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2489                         return -EEXIST;
2490
2491                 filter = STAILQ_NEXT(filter, next);
2492         }
2493
2494         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2495          * command to create MAC+VLAN filter with the right flags, enables set.
2496          */
2497         filter = bnxt_alloc_filter(bp);
2498         if (!filter) {
2499                 PMD_DRV_LOG(ERR,
2500                             "MAC/VLAN filter alloc failed\n");
2501                 return -ENOMEM;
2502         }
2503         /* MAC + VLAN ID filter */
2504         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2505          * untagged packets are received
2506          *
2507          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2508          * packets and only the programmed vlan's packets are received
2509          */
2510         filter->l2_ivlan = vlan_id;
2511         filter->l2_ivlan_mask = 0x0FFF;
2512         filter->enables |= en;
2513         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2514
2515         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2516         if (rc) {
2517                 /* Free the newly allocated filter as we were
2518                  * not able to create the filter in hardware.
2519                  */
2520                 bnxt_free_filter(bp, filter);
2521                 return rc;
2522         }
2523
2524         filter->mac_index = 0;
2525         /* Add this new filter to the list */
2526         if (vlan_id == 0)
2527                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2528         else
2529                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2530
2531         PMD_DRV_LOG(INFO,
2532                     "Added Vlan filter for %d\n", vlan_id);
2533         return rc;
2534 }
2535
2536 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2537                 uint16_t vlan_id, int on)
2538 {
2539         struct bnxt *bp = eth_dev->data->dev_private;
2540         int rc;
2541
2542         rc = is_bnxt_in_error(bp);
2543         if (rc)
2544                 return rc;
2545
2546         if (!eth_dev->data->dev_started) {
2547                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2548                 return -EINVAL;
2549         }
2550
2551         /* These operations apply to ALL existing MAC/VLAN filters */
2552         if (on)
2553                 return bnxt_add_vlan_filter(bp, vlan_id);
2554         else
2555                 return bnxt_del_vlan_filter(bp, vlan_id);
2556 }
2557
2558 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2559                                     struct bnxt_vnic_info *vnic)
2560 {
2561         struct bnxt_filter_info *filter;
2562         int rc;
2563
2564         filter = STAILQ_FIRST(&vnic->filter);
2565         while (filter) {
2566                 if (filter->mac_index == 0 &&
2567                     !memcmp(filter->l2_addr, bp->mac_addr,
2568                             RTE_ETHER_ADDR_LEN)) {
2569                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2570                         if (!rc) {
2571                                 STAILQ_REMOVE(&vnic->filter, filter,
2572                                               bnxt_filter_info, next);
2573                                 bnxt_free_filter(bp, filter);
2574                         }
2575                         return rc;
2576                 }
2577                 filter = STAILQ_NEXT(filter, next);
2578         }
2579         return 0;
2580 }
2581
2582 static int
2583 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2584 {
2585         struct bnxt_vnic_info *vnic;
2586         unsigned int i;
2587         int rc;
2588
2589         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2590         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2591                 /* Remove any VLAN filters programmed */
2592                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2593                         bnxt_del_vlan_filter(bp, i);
2594
2595                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2596                 if (rc)
2597                         return rc;
2598         } else {
2599                 /* Default filter will allow packets that match the
2600                  * dest mac. So, it has to be deleted, otherwise, we
2601                  * will endup receiving vlan packets for which the
2602                  * filter is not programmed, when hw-vlan-filter
2603                  * configuration is ON
2604                  */
2605                 bnxt_del_dflt_mac_filter(bp, vnic);
2606                 /* This filter will allow only untagged packets */
2607                 bnxt_add_vlan_filter(bp, 0);
2608         }
2609         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2610                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2611
2612         return 0;
2613 }
2614
2615 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2616 {
2617         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2618         unsigned int i;
2619         int rc;
2620
2621         /* Destroy vnic filters and vnic */
2622         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2623             DEV_RX_OFFLOAD_VLAN_FILTER) {
2624                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2625                         bnxt_del_vlan_filter(bp, i);
2626         }
2627         bnxt_del_dflt_mac_filter(bp, vnic);
2628
2629         rc = bnxt_hwrm_vnic_ctx_free(bp, vnic);
2630         if (rc)
2631                 return rc;
2632
2633         rc = bnxt_hwrm_vnic_free(bp, vnic);
2634         if (rc)
2635                 return rc;
2636
2637         rte_free(vnic->fw_grp_ids);
2638         vnic->fw_grp_ids = NULL;
2639
2640         vnic->rx_queue_cnt = 0;
2641
2642         return 0;
2643 }
2644
2645 static int
2646 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2647 {
2648         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2649         int rc;
2650
2651         /* Destroy, recreate and reconfigure the default vnic */
2652         rc = bnxt_free_one_vnic(bp, 0);
2653         if (rc)
2654                 return rc;
2655
2656         /* default vnic 0 */
2657         rc = bnxt_setup_one_vnic(bp, 0);
2658         if (rc)
2659                 return rc;
2660
2661         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2662             DEV_RX_OFFLOAD_VLAN_FILTER) {
2663                 rc = bnxt_add_vlan_filter(bp, 0);
2664                 if (rc)
2665                         return rc;
2666                 rc = bnxt_restore_vlan_filters(bp);
2667                 if (rc)
2668                         return rc;
2669         } else {
2670                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2671                 if (rc)
2672                         return rc;
2673         }
2674
2675         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2676         if (rc)
2677                 return rc;
2678
2679         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2680                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2681
2682         return rc;
2683 }
2684
2685 static int
2686 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2687 {
2688         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2689         struct bnxt *bp = dev->data->dev_private;
2690         int rc;
2691
2692         rc = is_bnxt_in_error(bp);
2693         if (rc)
2694                 return rc;
2695
2696         /* Filter settings will get applied when port is started */
2697         if (!dev->data->dev_started)
2698                 return 0;
2699
2700         if (mask & ETH_VLAN_FILTER_MASK) {
2701                 /* Enable or disable VLAN filtering */
2702                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2703                 if (rc)
2704                         return rc;
2705         }
2706
2707         if (mask & ETH_VLAN_STRIP_MASK) {
2708                 /* Enable or disable VLAN stripping */
2709                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2710                 if (rc)
2711                         return rc;
2712         }
2713
2714         if (mask & ETH_VLAN_EXTEND_MASK) {
2715                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2716                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2717                 else
2718                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2719         }
2720
2721         return 0;
2722 }
2723
2724 static int
2725 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2726                       uint16_t tpid)
2727 {
2728         struct bnxt *bp = dev->data->dev_private;
2729         int qinq = dev->data->dev_conf.rxmode.offloads &
2730                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2731
2732         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2733             vlan_type != ETH_VLAN_TYPE_OUTER) {
2734                 PMD_DRV_LOG(ERR,
2735                             "Unsupported vlan type.");
2736                 return -EINVAL;
2737         }
2738         if (!qinq) {
2739                 PMD_DRV_LOG(ERR,
2740                             "QinQ not enabled. Needs to be ON as we can "
2741                             "accelerate only outer vlan\n");
2742                 return -EINVAL;
2743         }
2744
2745         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2746                 switch (tpid) {
2747                 case RTE_ETHER_TYPE_QINQ:
2748                         bp->outer_tpid_bd =
2749                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2750                                 break;
2751                 case RTE_ETHER_TYPE_VLAN:
2752                         bp->outer_tpid_bd =
2753                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2754                                 break;
2755                 case RTE_ETHER_TYPE_QINQ1:
2756                         bp->outer_tpid_bd =
2757                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2758                                 break;
2759                 case RTE_ETHER_TYPE_QINQ2:
2760                         bp->outer_tpid_bd =
2761                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2762                                 break;
2763                 case RTE_ETHER_TYPE_QINQ3:
2764                         bp->outer_tpid_bd =
2765                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2766                                 break;
2767                 default:
2768                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2769                         return -EINVAL;
2770                 }
2771                 bp->outer_tpid_bd |= tpid;
2772                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2773         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2774                 PMD_DRV_LOG(ERR,
2775                             "Can accelerate only outer vlan in QinQ\n");
2776                 return -EINVAL;
2777         }
2778
2779         return 0;
2780 }
2781
2782 static int
2783 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2784                              struct rte_ether_addr *addr)
2785 {
2786         struct bnxt *bp = dev->data->dev_private;
2787         /* Default Filter is tied to VNIC 0 */
2788         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2789         int rc;
2790
2791         rc = is_bnxt_in_error(bp);
2792         if (rc)
2793                 return rc;
2794
2795         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2796                 return -EPERM;
2797
2798         if (rte_is_zero_ether_addr(addr))
2799                 return -EINVAL;
2800
2801         /* Filter settings will get applied when port is started */
2802         if (!dev->data->dev_started)
2803                 return 0;
2804
2805         /* Check if the requested MAC is already added */
2806         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2807                 return 0;
2808
2809         /* Destroy filter and re-create it */
2810         bnxt_del_dflt_mac_filter(bp, vnic);
2811
2812         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2813         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2814                 /* This filter will allow only untagged packets */
2815                 rc = bnxt_add_vlan_filter(bp, 0);
2816         } else {
2817                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2818         }
2819
2820         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2821         return rc;
2822 }
2823
2824 static int
2825 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2826                           struct rte_ether_addr *mc_addr_set,
2827                           uint32_t nb_mc_addr)
2828 {
2829         struct bnxt *bp = eth_dev->data->dev_private;
2830         char *mc_addr_list = (char *)mc_addr_set;
2831         struct bnxt_vnic_info *vnic;
2832         uint32_t off = 0, i = 0;
2833         int rc;
2834
2835         rc = is_bnxt_in_error(bp);
2836         if (rc)
2837                 return rc;
2838
2839         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2840
2841         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2842                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2843                 goto allmulti;
2844         }
2845
2846         /* TODO Check for Duplicate mcast addresses */
2847         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2848         for (i = 0; i < nb_mc_addr; i++) {
2849                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2850                         RTE_ETHER_ADDR_LEN);
2851                 off += RTE_ETHER_ADDR_LEN;
2852         }
2853
2854         vnic->mc_addr_cnt = i;
2855         if (vnic->mc_addr_cnt)
2856                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2857         else
2858                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2859
2860 allmulti:
2861         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2862 }
2863
2864 static int
2865 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2866 {
2867         struct bnxt *bp = dev->data->dev_private;
2868         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2869         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2870         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2871         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2872         int ret;
2873
2874         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2875                         fw_major, fw_minor, fw_updt, fw_rsvd);
2876         if (ret < 0)
2877                 return -EINVAL;
2878
2879         ret += 1; /* add the size of '\0' */
2880         if (fw_size < (size_t)ret)
2881                 return ret;
2882         else
2883                 return 0;
2884 }
2885
2886 static void
2887 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2888         struct rte_eth_rxq_info *qinfo)
2889 {
2890         struct bnxt *bp = dev->data->dev_private;
2891         struct bnxt_rx_queue *rxq;
2892
2893         if (is_bnxt_in_error(bp))
2894                 return;
2895
2896         rxq = dev->data->rx_queues[queue_id];
2897
2898         qinfo->mp = rxq->mb_pool;
2899         qinfo->scattered_rx = dev->data->scattered_rx;
2900         qinfo->nb_desc = rxq->nb_rx_desc;
2901
2902         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2903         qinfo->conf.rx_drop_en = rxq->drop_en;
2904         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2905         qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2906 }
2907
2908 static void
2909 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2910         struct rte_eth_txq_info *qinfo)
2911 {
2912         struct bnxt *bp = dev->data->dev_private;
2913         struct bnxt_tx_queue *txq;
2914
2915         if (is_bnxt_in_error(bp))
2916                 return;
2917
2918         txq = dev->data->tx_queues[queue_id];
2919
2920         qinfo->nb_desc = txq->nb_tx_desc;
2921
2922         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2923         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2924         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2925
2926         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2927         qinfo->conf.tx_rs_thresh = 0;
2928         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2929         qinfo->conf.offloads = txq->offloads;
2930 }
2931
2932 static const struct {
2933         eth_rx_burst_t pkt_burst;
2934         const char *info;
2935 } bnxt_rx_burst_info[] = {
2936         {bnxt_recv_pkts,                "Scalar"},
2937 #if defined(RTE_ARCH_X86)
2938         {bnxt_recv_pkts_vec,            "Vector SSE"},
2939 #endif
2940 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2941         {bnxt_recv_pkts_vec_avx2,       "Vector AVX2"},
2942 #endif
2943 #if defined(RTE_ARCH_ARM64)
2944         {bnxt_recv_pkts_vec,            "Vector Neon"},
2945 #endif
2946 };
2947
2948 static int
2949 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2950                        struct rte_eth_burst_mode *mode)
2951 {
2952         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2953         size_t i;
2954
2955         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2956                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2957                         snprintf(mode->info, sizeof(mode->info), "%s",
2958                                  bnxt_rx_burst_info[i].info);
2959                         return 0;
2960                 }
2961         }
2962
2963         return -EINVAL;
2964 }
2965
2966 static const struct {
2967         eth_tx_burst_t pkt_burst;
2968         const char *info;
2969 } bnxt_tx_burst_info[] = {
2970         {bnxt_xmit_pkts,                "Scalar"},
2971 #if defined(RTE_ARCH_X86)
2972         {bnxt_xmit_pkts_vec,            "Vector SSE"},
2973 #endif
2974 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2975         {bnxt_xmit_pkts_vec_avx2,       "Vector AVX2"},
2976 #endif
2977 #if defined(RTE_ARCH_ARM64)
2978         {bnxt_xmit_pkts_vec,            "Vector Neon"},
2979 #endif
2980 };
2981
2982 static int
2983 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2984                        struct rte_eth_burst_mode *mode)
2985 {
2986         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2987         size_t i;
2988
2989         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2990                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2991                         snprintf(mode->info, sizeof(mode->info), "%s",
2992                                  bnxt_tx_burst_info[i].info);
2993                         return 0;
2994                 }
2995         }
2996
2997         return -EINVAL;
2998 }
2999
3000 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
3001 {
3002         struct bnxt *bp = eth_dev->data->dev_private;
3003         uint32_t new_pkt_size;
3004         uint32_t rc = 0;
3005         uint32_t i;
3006
3007         rc = is_bnxt_in_error(bp);
3008         if (rc)
3009                 return rc;
3010
3011         /* Exit if receive queues are not configured yet */
3012         if (!eth_dev->data->nb_rx_queues)
3013                 return rc;
3014
3015         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
3016                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
3017
3018         /*
3019          * Disallow any MTU change that would require scattered receive support
3020          * if it is not already enabled.
3021          */
3022         if (eth_dev->data->dev_started &&
3023             !eth_dev->data->scattered_rx &&
3024             (new_pkt_size >
3025              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
3026                 PMD_DRV_LOG(ERR,
3027                             "MTU change would require scattered rx support. ");
3028                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
3029                 return -EINVAL;
3030         }
3031
3032         if (new_mtu > RTE_ETHER_MTU) {
3033                 bp->flags |= BNXT_FLAG_JUMBO;
3034                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
3035                         DEV_RX_OFFLOAD_JUMBO_FRAME;
3036         } else {
3037                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
3038                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3039                 bp->flags &= ~BNXT_FLAG_JUMBO;
3040         }
3041
3042         /* Is there a change in mtu setting? */
3043         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
3044                 return rc;
3045
3046         for (i = 0; i < bp->nr_vnics; i++) {
3047                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3048                 uint16_t size = 0;
3049
3050                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
3051                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
3052                 if (rc)
3053                         break;
3054
3055                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
3056                 size -= RTE_PKTMBUF_HEADROOM;
3057
3058                 if (size < new_mtu) {
3059                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
3060                         if (rc)
3061                                 return rc;
3062                 }
3063         }
3064
3065         if (!rc)
3066                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
3067
3068         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
3069
3070         return rc;
3071 }
3072
3073 static int
3074 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
3075 {
3076         struct bnxt *bp = dev->data->dev_private;
3077         uint16_t vlan = bp->vlan;
3078         int rc;
3079
3080         rc = is_bnxt_in_error(bp);
3081         if (rc)
3082                 return rc;
3083
3084         if (!BNXT_SINGLE_PF(bp)) {
3085                 PMD_DRV_LOG(ERR, "PVID cannot be modified on VF or on shared PF\n");
3086                 return -ENOTSUP;
3087         }
3088         bp->vlan = on ? pvid : 0;
3089
3090         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
3091         if (rc)
3092                 bp->vlan = vlan;
3093         return rc;
3094 }
3095
3096 static int
3097 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
3098 {
3099         struct bnxt *bp = dev->data->dev_private;
3100         int rc;
3101
3102         rc = is_bnxt_in_error(bp);
3103         if (rc)
3104                 return rc;
3105
3106         return bnxt_hwrm_port_led_cfg(bp, true);
3107 }
3108
3109 static int
3110 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
3111 {
3112         struct bnxt *bp = dev->data->dev_private;
3113         int rc;
3114
3115         rc = is_bnxt_in_error(bp);
3116         if (rc)
3117                 return rc;
3118
3119         return bnxt_hwrm_port_led_cfg(bp, false);
3120 }
3121
3122 static uint32_t
3123 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3124 {
3125         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
3126         struct bnxt_cp_ring_info *cpr;
3127         uint32_t desc = 0, raw_cons;
3128         struct bnxt_rx_queue *rxq;
3129         struct rx_pkt_cmpl *rxcmp;
3130         int rc;
3131
3132         rc = is_bnxt_in_error(bp);
3133         if (rc)
3134                 return rc;
3135
3136         rxq = dev->data->rx_queues[rx_queue_id];
3137         cpr = rxq->cp_ring;
3138         raw_cons = cpr->cp_raw_cons;
3139
3140         while (1) {
3141                 uint32_t agg_cnt, cons, cmpl_type;
3142
3143                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3144                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3145
3146                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3147                         break;
3148
3149                 cmpl_type = CMP_TYPE(rxcmp);
3150
3151                 switch (cmpl_type) {
3152                 case CMPL_BASE_TYPE_RX_L2:
3153                 case CMPL_BASE_TYPE_RX_L2_V2:
3154                         agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3155                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3156                         desc++;
3157                         break;
3158
3159                 case CMPL_BASE_TYPE_RX_TPA_END:
3160                         if (BNXT_CHIP_P5(rxq->bp)) {
3161                                 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3162
3163                                 p5_tpa_end = (void *)rxcmp;
3164                                 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3165                         } else {
3166                                 struct rx_tpa_end_cmpl *tpa_end;
3167
3168                                 tpa_end = (void *)rxcmp;
3169                                 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3170                         }
3171
3172                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3173                         desc++;
3174                         break;
3175
3176                 default:
3177                         raw_cons += CMP_LEN(cmpl_type);
3178                 }
3179         }
3180
3181         return desc;
3182 }
3183
3184 static int
3185 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
3186 {
3187         struct bnxt_rx_queue *rxq = rx_queue;
3188         struct bnxt_cp_ring_info *cpr;
3189         struct bnxt_rx_ring_info *rxr;
3190         uint32_t desc, raw_cons;
3191         struct bnxt *bp = rxq->bp;
3192         struct rx_pkt_cmpl *rxcmp;
3193         int rc;
3194
3195         rc = is_bnxt_in_error(bp);
3196         if (rc)
3197                 return rc;
3198
3199         if (offset >= rxq->nb_rx_desc)
3200                 return -EINVAL;
3201
3202         rxr = rxq->rx_ring;
3203         cpr = rxq->cp_ring;
3204
3205         /*
3206          * For the vector receive case, the completion at the requested
3207          * offset can be indexed directly.
3208          */
3209 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
3210         if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) {
3211                 struct rx_pkt_cmpl *rxcmp;
3212                 uint32_t cons;
3213
3214                 /* Check status of completion descriptor. */
3215                 raw_cons = cpr->cp_raw_cons +
3216                            offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2);
3217                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3218                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3219
3220                 if (CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3221                         return RTE_ETH_RX_DESC_DONE;
3222
3223                 /* Check whether rx desc has an mbuf attached. */
3224                 cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2);
3225                 if (cons >= rxq->rxrearm_start &&
3226                     cons < rxq->rxrearm_start + rxq->rxrearm_nb) {
3227                         return RTE_ETH_RX_DESC_UNAVAIL;
3228                 }
3229
3230                 return RTE_ETH_RX_DESC_AVAIL;
3231         }
3232 #endif
3233
3234         /*
3235          * For the non-vector receive case, scan the completion ring to
3236          * locate the completion descriptor for the requested offset.
3237          */
3238         raw_cons = cpr->cp_raw_cons;
3239         desc = 0;
3240         while (1) {
3241                 uint32_t agg_cnt, cons, cmpl_type;
3242
3243                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3244                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3245
3246                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3247                         break;
3248
3249                 cmpl_type = CMP_TYPE(rxcmp);
3250
3251                 switch (cmpl_type) {
3252                 case CMPL_BASE_TYPE_RX_L2:
3253                 case CMPL_BASE_TYPE_RX_L2_V2:
3254                         if (desc == offset) {
3255                                 cons = rxcmp->opaque;
3256                                 if (rxr->rx_buf_ring[cons])
3257                                         return RTE_ETH_RX_DESC_DONE;
3258                                 else
3259                                         return RTE_ETH_RX_DESC_UNAVAIL;
3260                         }
3261                         agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3262                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3263                         desc++;
3264                         break;
3265
3266                 case CMPL_BASE_TYPE_RX_TPA_END:
3267                         if (desc == offset)
3268                                 return RTE_ETH_RX_DESC_DONE;
3269
3270                         if (BNXT_CHIP_P5(rxq->bp)) {
3271                                 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3272
3273                                 p5_tpa_end = (void *)rxcmp;
3274                                 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3275                         } else {
3276                                 struct rx_tpa_end_cmpl *tpa_end;
3277
3278                                 tpa_end = (void *)rxcmp;
3279                                 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3280                         }
3281
3282                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3283                         desc++;
3284                         break;
3285
3286                 default:
3287                         raw_cons += CMP_LEN(cmpl_type);
3288                 }
3289         }
3290
3291         return RTE_ETH_RX_DESC_AVAIL;
3292 }
3293
3294 static int
3295 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
3296 {
3297         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
3298         struct bnxt_tx_ring_info *txr;
3299         struct bnxt_cp_ring_info *cpr;
3300         struct rte_mbuf **tx_buf;
3301         struct tx_pkt_cmpl *txcmp;
3302         uint32_t cons, cp_cons;
3303         int rc;
3304
3305         if (!txq)
3306                 return -EINVAL;
3307
3308         rc = is_bnxt_in_error(txq->bp);
3309         if (rc)
3310                 return rc;
3311
3312         cpr = txq->cp_ring;
3313         txr = txq->tx_ring;
3314
3315         if (offset >= txq->nb_tx_desc)
3316                 return -EINVAL;
3317
3318         cons = RING_CMP(cpr->cp_ring_struct, offset);
3319         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3320         cp_cons = cpr->cp_raw_cons;
3321
3322         if (cons > cp_cons) {
3323                 if (CMPL_VALID(txcmp, cpr->valid))
3324                         return RTE_ETH_TX_DESC_UNAVAIL;
3325         } else {
3326                 if (CMPL_VALID(txcmp, !cpr->valid))
3327                         return RTE_ETH_TX_DESC_UNAVAIL;
3328         }
3329         tx_buf = &txr->tx_buf_ring[cons];
3330         if (*tx_buf == NULL)
3331                 return RTE_ETH_TX_DESC_DONE;
3332
3333         return RTE_ETH_TX_DESC_FULL;
3334 }
3335
3336 int
3337 bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
3338                      const struct rte_flow_ops **ops)
3339 {
3340         struct bnxt *bp = dev->data->dev_private;
3341         int ret = 0;
3342
3343         if (!bp)
3344                 return -EIO;
3345
3346         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3347                 struct bnxt_representor *vfr = dev->data->dev_private;
3348                 bp = vfr->parent_dev->data->dev_private;
3349                 /* parent is deleted while children are still valid */
3350                 if (!bp) {
3351                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error\n",
3352                                     dev->data->port_id);
3353                         return -EIO;
3354                 }
3355         }
3356
3357         ret = is_bnxt_in_error(bp);
3358         if (ret)
3359                 return ret;
3360
3361         /* PMD supports thread-safe flow operations.  rte_flow API
3362          * functions can avoid mutex for multi-thread safety.
3363          */
3364         dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3365
3366         if (BNXT_TRUFLOW_EN(bp))
3367                 *ops = &bnxt_ulp_rte_flow_ops;
3368         else
3369                 *ops = &bnxt_flow_ops;
3370
3371         return ret;
3372 }
3373
3374 static const uint32_t *
3375 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3376 {
3377         static const uint32_t ptypes[] = {
3378                 RTE_PTYPE_L2_ETHER_VLAN,
3379                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3380                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3381                 RTE_PTYPE_L4_ICMP,
3382                 RTE_PTYPE_L4_TCP,
3383                 RTE_PTYPE_L4_UDP,
3384                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3385                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3386                 RTE_PTYPE_INNER_L4_ICMP,
3387                 RTE_PTYPE_INNER_L4_TCP,
3388                 RTE_PTYPE_INNER_L4_UDP,
3389                 RTE_PTYPE_UNKNOWN
3390         };
3391
3392         if (!dev->rx_pkt_burst)
3393                 return NULL;
3394
3395         return ptypes;
3396 }
3397
3398 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3399                          int reg_win)
3400 {
3401         uint32_t reg_base = *reg_arr & 0xfffff000;
3402         uint32_t win_off;
3403         int i;
3404
3405         for (i = 0; i < count; i++) {
3406                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3407                         return -ERANGE;
3408         }
3409         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3410         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3411         return 0;
3412 }
3413
3414 static int bnxt_map_ptp_regs(struct bnxt *bp)
3415 {
3416         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3417         uint32_t *reg_arr;
3418         int rc, i;
3419
3420         reg_arr = ptp->rx_regs;
3421         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3422         if (rc)
3423                 return rc;
3424
3425         reg_arr = ptp->tx_regs;
3426         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3427         if (rc)
3428                 return rc;
3429
3430         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3431                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3432
3433         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3434                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3435
3436         return 0;
3437 }
3438
3439 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3440 {
3441         rte_write32(0, (uint8_t *)bp->bar0 +
3442                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3443         rte_write32(0, (uint8_t *)bp->bar0 +
3444                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3445 }
3446
3447 static uint64_t bnxt_cc_read(struct bnxt *bp)
3448 {
3449         uint64_t ns;
3450
3451         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3452                               BNXT_GRCPF_REG_SYNC_TIME));
3453         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3454                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3455         return ns;
3456 }
3457
3458 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3459 {
3460         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3461         uint32_t fifo;
3462
3463         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3464                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3465         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3466                 return -EAGAIN;
3467
3468         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3469                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3470         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3471                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3472         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3473                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3474         rte_read32((uint8_t *)bp->bar0 + ptp->tx_mapped_regs[BNXT_PTP_TX_SEQ]);
3475
3476         return 0;
3477 }
3478
3479 static int bnxt_clr_rx_ts(struct bnxt *bp, uint64_t *last_ts)
3480 {
3481         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3482         struct bnxt_pf_info *pf = bp->pf;
3483         uint16_t port_id;
3484         int i = 0;
3485         uint32_t fifo;
3486
3487         if (!ptp || (bp->flags & BNXT_FLAG_CHIP_P5))
3488                 return -EINVAL;
3489
3490         port_id = pf->port_id;
3491         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3492                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3493         while ((fifo & BNXT_PTP_RX_FIFO_PENDING) && (i < BNXT_PTP_RX_PND_CNT)) {
3494                 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3495                             ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3496                 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3497                                         ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3498                 *last_ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3499                                         ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3500                 *last_ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3501                                         ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3502                 i++;
3503         }
3504
3505         if (i >= BNXT_PTP_RX_PND_CNT)
3506                 return -EBUSY;
3507
3508         return 0;
3509 }
3510
3511 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3512 {
3513         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3514         struct bnxt_pf_info *pf = bp->pf;
3515         uint16_t port_id;
3516         uint32_t fifo;
3517
3518         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3519                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3520         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3521                 return -EAGAIN;
3522
3523         port_id = pf->port_id;
3524         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3525                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3526
3527         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3528                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3529         if (fifo & BNXT_PTP_RX_FIFO_PENDING)
3530                 return bnxt_clr_rx_ts(bp, ts);
3531
3532         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3533                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3534         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3535                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3536
3537         return 0;
3538 }
3539
3540 static int
3541 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3542 {
3543         uint64_t ns;
3544         struct bnxt *bp = dev->data->dev_private;
3545         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3546
3547         if (!ptp)
3548                 return -ENOTSUP;
3549
3550         ns = rte_timespec_to_ns(ts);
3551         /* Set the timecounters to a new value. */
3552         ptp->tc.nsec = ns;
3553         ptp->tx_tstamp_tc.nsec = ns;
3554         ptp->rx_tstamp_tc.nsec = ns;
3555
3556         return 0;
3557 }
3558
3559 static int
3560 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3561 {
3562         struct bnxt *bp = dev->data->dev_private;
3563         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3564         uint64_t ns, systime_cycles = 0;
3565         int rc = 0;
3566
3567         if (!ptp)
3568                 return -ENOTSUP;
3569
3570         if (BNXT_CHIP_P5(bp))
3571                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3572                                              &systime_cycles);
3573         else
3574                 systime_cycles = bnxt_cc_read(bp);
3575
3576         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3577         *ts = rte_ns_to_timespec(ns);
3578
3579         return rc;
3580 }
3581 static int
3582 bnxt_timesync_enable(struct rte_eth_dev *dev)
3583 {
3584         struct bnxt *bp = dev->data->dev_private;
3585         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3586         uint32_t shift = 0;
3587         int rc;
3588
3589         if (!ptp)
3590                 return -ENOTSUP;
3591
3592         ptp->rx_filter = 1;
3593         ptp->tx_tstamp_en = 1;
3594         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3595
3596         rc = bnxt_hwrm_ptp_cfg(bp);
3597         if (rc)
3598                 return rc;
3599
3600         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3601         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3602         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3603
3604         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3605         ptp->tc.cc_shift = shift;
3606         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3607
3608         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3609         ptp->rx_tstamp_tc.cc_shift = shift;
3610         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3611
3612         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3613         ptp->tx_tstamp_tc.cc_shift = shift;
3614         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3615
3616         if (!BNXT_CHIP_P5(bp))
3617                 bnxt_map_ptp_regs(bp);
3618         else
3619                 rc = bnxt_ptp_start(bp);
3620
3621         return rc;
3622 }
3623
3624 static int
3625 bnxt_timesync_disable(struct rte_eth_dev *dev)
3626 {
3627         struct bnxt *bp = dev->data->dev_private;
3628         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3629
3630         if (!ptp)
3631                 return -ENOTSUP;
3632
3633         ptp->rx_filter = 0;
3634         ptp->tx_tstamp_en = 0;
3635         ptp->rxctl = 0;
3636
3637         bnxt_hwrm_ptp_cfg(bp);
3638
3639         if (!BNXT_CHIP_P5(bp))
3640                 bnxt_unmap_ptp_regs(bp);
3641         else
3642                 bnxt_ptp_stop(bp);
3643
3644         return 0;
3645 }
3646
3647 static int
3648 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3649                                  struct timespec *timestamp,
3650                                  uint32_t flags __rte_unused)
3651 {
3652         struct bnxt *bp = dev->data->dev_private;
3653         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3654         uint64_t rx_tstamp_cycles = 0;
3655         uint64_t ns;
3656
3657         if (!ptp)
3658                 return -ENOTSUP;
3659
3660         if (BNXT_CHIP_P5(bp))
3661                 rx_tstamp_cycles = ptp->rx_timestamp;
3662         else
3663                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3664
3665         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3666         *timestamp = rte_ns_to_timespec(ns);
3667         return  0;
3668 }
3669
3670 static int
3671 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3672                                  struct timespec *timestamp)
3673 {
3674         struct bnxt *bp = dev->data->dev_private;
3675         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3676         uint64_t tx_tstamp_cycles = 0;
3677         uint64_t ns;
3678         int rc = 0;
3679
3680         if (!ptp)
3681                 return -ENOTSUP;
3682
3683         if (BNXT_CHIP_P5(bp))
3684                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3685                                              &tx_tstamp_cycles);
3686         else
3687                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3688
3689         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3690         *timestamp = rte_ns_to_timespec(ns);
3691
3692         return rc;
3693 }
3694
3695 static int
3696 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3697 {
3698         struct bnxt *bp = dev->data->dev_private;
3699         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3700
3701         if (!ptp)
3702                 return -ENOTSUP;
3703
3704         ptp->tc.nsec += delta;
3705         ptp->tx_tstamp_tc.nsec += delta;
3706         ptp->rx_tstamp_tc.nsec += delta;
3707
3708         return 0;
3709 }
3710
3711 static int
3712 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3713 {
3714         struct bnxt *bp = dev->data->dev_private;
3715         int rc;
3716         uint32_t dir_entries;
3717         uint32_t entry_length;
3718
3719         rc = is_bnxt_in_error(bp);
3720         if (rc)
3721                 return rc;
3722
3723         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3724                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3725                     bp->pdev->addr.devid, bp->pdev->addr.function);
3726
3727         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3728         if (rc != 0)
3729                 return rc;
3730
3731         return dir_entries * entry_length;
3732 }
3733
3734 static int
3735 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3736                 struct rte_dev_eeprom_info *in_eeprom)
3737 {
3738         struct bnxt *bp = dev->data->dev_private;
3739         uint32_t index;
3740         uint32_t offset;
3741         int rc;
3742
3743         rc = is_bnxt_in_error(bp);
3744         if (rc)
3745                 return rc;
3746
3747         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3748                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3749                     bp->pdev->addr.devid, bp->pdev->addr.function,
3750                     in_eeprom->offset, in_eeprom->length);
3751
3752         if (in_eeprom->offset == 0) /* special offset value to get directory */
3753                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3754                                                 in_eeprom->data);
3755
3756         index = in_eeprom->offset >> 24;
3757         offset = in_eeprom->offset & 0xffffff;
3758
3759         if (index != 0)
3760                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3761                                            in_eeprom->length, in_eeprom->data);
3762
3763         return 0;
3764 }
3765
3766 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3767 {
3768         switch (dir_type) {
3769         case BNX_DIR_TYPE_CHIMP_PATCH:
3770         case BNX_DIR_TYPE_BOOTCODE:
3771         case BNX_DIR_TYPE_BOOTCODE_2:
3772         case BNX_DIR_TYPE_APE_FW:
3773         case BNX_DIR_TYPE_APE_PATCH:
3774         case BNX_DIR_TYPE_KONG_FW:
3775         case BNX_DIR_TYPE_KONG_PATCH:
3776         case BNX_DIR_TYPE_BONO_FW:
3777         case BNX_DIR_TYPE_BONO_PATCH:
3778                 /* FALLTHROUGH */
3779                 return true;
3780         }
3781
3782         return false;
3783 }
3784
3785 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3786 {
3787         switch (dir_type) {
3788         case BNX_DIR_TYPE_AVS:
3789         case BNX_DIR_TYPE_EXP_ROM_MBA:
3790         case BNX_DIR_TYPE_PCIE:
3791         case BNX_DIR_TYPE_TSCF_UCODE:
3792         case BNX_DIR_TYPE_EXT_PHY:
3793         case BNX_DIR_TYPE_CCM:
3794         case BNX_DIR_TYPE_ISCSI_BOOT:
3795         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3796         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3797                 /* FALLTHROUGH */
3798                 return true;
3799         }
3800
3801         return false;
3802 }
3803
3804 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3805 {
3806         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3807                 bnxt_dir_type_is_other_exec_format(dir_type);
3808 }
3809
3810 static int
3811 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3812                 struct rte_dev_eeprom_info *in_eeprom)
3813 {
3814         struct bnxt *bp = dev->data->dev_private;
3815         uint8_t index, dir_op;
3816         uint16_t type, ext, ordinal, attr;
3817         int rc;
3818
3819         rc = is_bnxt_in_error(bp);
3820         if (rc)
3821                 return rc;
3822
3823         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3824                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3825                     bp->pdev->addr.devid, bp->pdev->addr.function,
3826                     in_eeprom->offset, in_eeprom->length);
3827
3828         if (!BNXT_PF(bp)) {
3829                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3830                 return -EINVAL;
3831         }
3832
3833         type = in_eeprom->magic >> 16;
3834
3835         if (type == 0xffff) { /* special value for directory operations */
3836                 index = in_eeprom->magic & 0xff;
3837                 dir_op = in_eeprom->magic >> 8;
3838                 if (index == 0)
3839                         return -EINVAL;
3840                 switch (dir_op) {
3841                 case 0x0e: /* erase */
3842                         if (in_eeprom->offset != ~in_eeprom->magic)
3843                                 return -EINVAL;
3844                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3845                 default:
3846                         return -EINVAL;
3847                 }
3848         }
3849
3850         /* Create or re-write an NVM item: */
3851         if (bnxt_dir_type_is_executable(type) == true)
3852                 return -EOPNOTSUPP;
3853         ext = in_eeprom->magic & 0xffff;
3854         ordinal = in_eeprom->offset >> 16;
3855         attr = in_eeprom->offset & 0xffff;
3856
3857         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3858                                      in_eeprom->data, in_eeprom->length);
3859 }
3860
3861 static int bnxt_get_module_info(struct rte_eth_dev *dev,
3862                                 struct rte_eth_dev_module_info *modinfo)
3863 {
3864         uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1];
3865         struct bnxt *bp = dev->data->dev_private;
3866         int rc;
3867
3868         /* No point in going further if phy status indicates
3869          * module is not inserted or if it is powered down or
3870          * if it is of type 10GBase-T
3871          */
3872         if (bp->link_info->module_status >
3873             HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG) {
3874                 PMD_DRV_LOG(NOTICE, "Port %u : Module is not inserted or is powered down\n",
3875                             dev->data->port_id);
3876                 return -ENOTSUP;
3877         }
3878
3879         /* This feature is not supported in older firmware versions */
3880         if (bp->hwrm_spec_code < 0x10202) {
3881                 PMD_DRV_LOG(NOTICE, "Port %u : Feature is not supported in older firmware\n",
3882                             dev->data->port_id);
3883                 return -ENOTSUP;
3884         }
3885
3886         rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
3887                                                    SFF_DIAG_SUPPORT_OFFSET + 1,
3888                                                    module_info);
3889
3890         if (rc)
3891                 return rc;
3892
3893         switch (module_info[0]) {
3894         case SFF_MODULE_ID_SFP:
3895                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
3896                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
3897                 if (module_info[SFF_DIAG_SUPPORT_OFFSET] == 0)
3898                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN;
3899                 break;
3900         case SFF_MODULE_ID_QSFP:
3901         case SFF_MODULE_ID_QSFP_PLUS:
3902                 modinfo->type = RTE_ETH_MODULE_SFF_8436;
3903                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN;
3904                 break;
3905         case SFF_MODULE_ID_QSFP28:
3906                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
3907                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
3908                 if (module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK)
3909                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_LEN;
3910                 break;
3911         default:
3912                 PMD_DRV_LOG(NOTICE, "Port %u : Unsupported module\n", dev->data->port_id);
3913                 return -ENOTSUP;
3914         }
3915
3916         PMD_DRV_LOG(INFO, "Port %u : modinfo->type = %d modinfo->eeprom_len = %d\n",
3917                     dev->data->port_id, modinfo->type, modinfo->eeprom_len);
3918
3919         return 0;
3920 }
3921
3922 static int bnxt_get_module_eeprom(struct rte_eth_dev *dev,
3923                                   struct rte_dev_eeprom_info *info)
3924 {
3925         uint8_t pg_addr[5] = { I2C_DEV_ADDR_A0, I2C_DEV_ADDR_A0 };
3926         uint32_t offset = info->offset, length = info->length;
3927         uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1];
3928         struct bnxt *bp = dev->data->dev_private;
3929         uint8_t *data = info->data;
3930         uint8_t page = offset >> 7;
3931         uint8_t max_pages = 2;
3932         uint8_t opt_pages;
3933         int rc;
3934
3935         rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
3936                                                    SFF_DIAG_SUPPORT_OFFSET + 1,
3937                                                    module_info);
3938         if (rc)
3939                 return rc;
3940
3941         switch (module_info[0]) {
3942         case SFF_MODULE_ID_SFP:
3943                 module_info[SFF_DIAG_SUPPORT_OFFSET] = 0;
3944                 if (module_info[SFF_DIAG_SUPPORT_OFFSET]) {
3945                         pg_addr[2] = I2C_DEV_ADDR_A2;
3946                         pg_addr[3] = I2C_DEV_ADDR_A2;
3947                         max_pages = 4;
3948                 }
3949                 break;
3950         case SFF_MODULE_ID_QSFP28:
3951                 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0,
3952                                                            SFF8636_OPT_PAGES_OFFSET,
3953                                                            1, &opt_pages);
3954                 if (rc)
3955                         return rc;
3956
3957                 if (opt_pages & SFF8636_PAGE1_MASK) {
3958                         pg_addr[2] = I2C_DEV_ADDR_A0;
3959                         max_pages = 3;
3960                 }
3961                 if (opt_pages & SFF8636_PAGE2_MASK) {
3962                         pg_addr[3] = I2C_DEV_ADDR_A0;
3963                         max_pages = 4;
3964                 }
3965                 if (~module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK) {
3966                         pg_addr[4] = I2C_DEV_ADDR_A0;
3967                         max_pages = 5;
3968                 }
3969                 break;
3970         default:
3971                 break;
3972         }
3973
3974         memset(data, 0, length);
3975
3976         offset &= 0xff;
3977         while (length && page < max_pages) {
3978                 uint8_t raw_page = page ? page - 1 : 0;
3979                 uint16_t chunk;
3980
3981                 if (pg_addr[page] == I2C_DEV_ADDR_A2)
3982                         raw_page = 0;
3983                 else if (page)
3984                         offset |= 0x80;
3985                 chunk = RTE_MIN(length, 256 - offset);
3986
3987                 if (pg_addr[page]) {
3988                         rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, pg_addr[page],
3989                                                                    raw_page, offset,
3990                                                                    chunk, data);
3991                         if (rc)
3992                                 return rc;
3993                 }
3994
3995                 data += chunk;
3996                 length -= chunk;
3997                 offset = 0;
3998                 page += 1 + (chunk > 128);
3999         }
4000
4001         return length ? -EINVAL : 0;
4002 }
4003
4004 /*
4005  * Initialization
4006  */
4007
4008 static const struct eth_dev_ops bnxt_dev_ops = {
4009         .dev_infos_get = bnxt_dev_info_get_op,
4010         .dev_close = bnxt_dev_close_op,
4011         .dev_configure = bnxt_dev_configure_op,
4012         .dev_start = bnxt_dev_start_op,
4013         .dev_stop = bnxt_dev_stop_op,
4014         .dev_set_link_up = bnxt_dev_set_link_up_op,
4015         .dev_set_link_down = bnxt_dev_set_link_down_op,
4016         .stats_get = bnxt_stats_get_op,
4017         .stats_reset = bnxt_stats_reset_op,
4018         .rx_queue_setup = bnxt_rx_queue_setup_op,
4019         .rx_queue_release = bnxt_rx_queue_release_op,
4020         .tx_queue_setup = bnxt_tx_queue_setup_op,
4021         .tx_queue_release = bnxt_tx_queue_release_op,
4022         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4023         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4024         .reta_update = bnxt_reta_update_op,
4025         .reta_query = bnxt_reta_query_op,
4026         .rss_hash_update = bnxt_rss_hash_update_op,
4027         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4028         .link_update = bnxt_link_update_op,
4029         .promiscuous_enable = bnxt_promiscuous_enable_op,
4030         .promiscuous_disable = bnxt_promiscuous_disable_op,
4031         .allmulticast_enable = bnxt_allmulticast_enable_op,
4032         .allmulticast_disable = bnxt_allmulticast_disable_op,
4033         .mac_addr_add = bnxt_mac_addr_add_op,
4034         .mac_addr_remove = bnxt_mac_addr_remove_op,
4035         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4036         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4037         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4038         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4039         .vlan_filter_set = bnxt_vlan_filter_set_op,
4040         .vlan_offload_set = bnxt_vlan_offload_set_op,
4041         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4042         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4043         .mtu_set = bnxt_mtu_set_op,
4044         .mac_addr_set = bnxt_set_default_mac_addr_op,
4045         .xstats_get = bnxt_dev_xstats_get_op,
4046         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4047         .xstats_reset = bnxt_dev_xstats_reset_op,
4048         .fw_version_get = bnxt_fw_version_get,
4049         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4050         .rxq_info_get = bnxt_rxq_info_get_op,
4051         .txq_info_get = bnxt_txq_info_get_op,
4052         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4053         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4054         .dev_led_on = bnxt_dev_led_on_op,
4055         .dev_led_off = bnxt_dev_led_off_op,
4056         .rx_queue_start = bnxt_rx_queue_start,
4057         .rx_queue_stop = bnxt_rx_queue_stop,
4058         .tx_queue_start = bnxt_tx_queue_start,
4059         .tx_queue_stop = bnxt_tx_queue_stop,
4060         .flow_ops_get = bnxt_flow_ops_get_op,
4061         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4062         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4063         .get_eeprom           = bnxt_get_eeprom_op,
4064         .set_eeprom           = bnxt_set_eeprom_op,
4065         .get_module_info = bnxt_get_module_info,
4066         .get_module_eeprom = bnxt_get_module_eeprom,
4067         .timesync_enable      = bnxt_timesync_enable,
4068         .timesync_disable     = bnxt_timesync_disable,
4069         .timesync_read_time   = bnxt_timesync_read_time,
4070         .timesync_write_time   = bnxt_timesync_write_time,
4071         .timesync_adjust_time = bnxt_timesync_adjust_time,
4072         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4073         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4074 };
4075
4076 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4077 {
4078         uint32_t offset;
4079
4080         /* Only pre-map the reset GRC registers using window 3 */
4081         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4082                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4083
4084         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4085
4086         return offset;
4087 }
4088
4089 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4090 {
4091         struct bnxt_error_recovery_info *info = bp->recovery_info;
4092         uint32_t reg_base = 0xffffffff;
4093         int i;
4094
4095         /* Only pre-map the monitoring GRC registers using window 2 */
4096         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4097                 uint32_t reg = info->status_regs[i];
4098
4099                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4100                         continue;
4101
4102                 if (reg_base == 0xffffffff)
4103                         reg_base = reg & 0xfffff000;
4104                 if ((reg & 0xfffff000) != reg_base)
4105                         return -ERANGE;
4106
4107                 /* Use mask 0xffc as the Lower 2 bits indicates
4108                  * address space location
4109                  */
4110                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4111                                                 (reg & 0xffc);
4112         }
4113
4114         if (reg_base == 0xffffffff)
4115                 return 0;
4116
4117         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4118                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4119
4120         return 0;
4121 }
4122
4123 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4124 {
4125         struct bnxt_error_recovery_info *info = bp->recovery_info;
4126         uint32_t delay = info->delay_after_reset[index];
4127         uint32_t val = info->reset_reg_val[index];
4128         uint32_t reg = info->reset_reg[index];
4129         uint32_t type, offset;
4130         int ret;
4131
4132         type = BNXT_FW_STATUS_REG_TYPE(reg);
4133         offset = BNXT_FW_STATUS_REG_OFF(reg);
4134
4135         switch (type) {
4136         case BNXT_FW_STATUS_REG_TYPE_CFG:
4137                 ret = rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4138                 if (ret < 0) {
4139                         PMD_DRV_LOG(ERR, "Failed to write %#x at PCI offset %#x",
4140                                     val, offset);
4141                         return;
4142                 }
4143                 break;
4144         case BNXT_FW_STATUS_REG_TYPE_GRC:
4145                 offset = bnxt_map_reset_regs(bp, offset);
4146                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4147                 break;
4148         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4149                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4150                 break;
4151         }
4152         /* wait on a specific interval of time until core reset is complete */
4153         if (delay)
4154                 rte_delay_ms(delay);
4155 }
4156
4157 static void bnxt_dev_cleanup(struct bnxt *bp)
4158 {
4159         bp->eth_dev->data->dev_link.link_status = 0;
4160         bp->link_info->link_up = 0;
4161         if (bp->eth_dev->data->dev_started)
4162                 bnxt_dev_stop(bp->eth_dev);
4163
4164         bnxt_uninit_resources(bp, true);
4165 }
4166
4167 static int
4168 bnxt_check_fw_reset_done(struct bnxt *bp)
4169 {
4170         int timeout = bp->fw_reset_max_msecs;
4171         uint16_t val = 0;
4172         int rc;
4173
4174         do {
4175                 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4176                 if (rc < 0) {
4177                         PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4178                         return rc;
4179                 }
4180                 if (val != 0xffff)
4181                         break;
4182                 rte_delay_ms(1);
4183         } while (timeout--);
4184
4185         if (val == 0xffff) {
4186                 PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n");
4187                 return -1;
4188         }
4189
4190         return 0;
4191 }
4192
4193 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4194 {
4195         struct rte_eth_dev *dev = bp->eth_dev;
4196         struct rte_vlan_filter_conf *vfc;
4197         int vidx, vbit, rc;
4198         uint16_t vlan_id;
4199
4200         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4201                 vfc = &dev->data->vlan_filter_conf;
4202                 vidx = vlan_id / 64;
4203                 vbit = vlan_id % 64;
4204
4205                 /* Each bit corresponds to a VLAN id */
4206                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4207                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4208                         if (rc)
4209                                 return rc;
4210                 }
4211         }
4212
4213         return 0;
4214 }
4215
4216 static int bnxt_restore_mac_filters(struct bnxt *bp)
4217 {
4218         struct rte_eth_dev *dev = bp->eth_dev;
4219         struct rte_eth_dev_info dev_info;
4220         struct rte_ether_addr *addr;
4221         uint64_t pool_mask;
4222         uint32_t pool = 0;
4223         uint32_t i;
4224         int rc;
4225
4226         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4227                 return 0;
4228
4229         rc = bnxt_dev_info_get_op(dev, &dev_info);
4230         if (rc)
4231                 return rc;
4232
4233         /* replay MAC address configuration */
4234         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4235                 addr = &dev->data->mac_addrs[i];
4236
4237                 /* skip zero address */
4238                 if (rte_is_zero_ether_addr(addr))
4239                         continue;
4240
4241                 pool = 0;
4242                 pool_mask = dev->data->mac_pool_sel[i];
4243
4244                 do {
4245                         if (pool_mask & 1ULL) {
4246                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4247                                 if (rc)
4248                                         return rc;
4249                         }
4250                         pool_mask >>= 1;
4251                         pool++;
4252                 } while (pool_mask);
4253         }
4254
4255         return 0;
4256 }
4257
4258 static int bnxt_restore_filters(struct bnxt *bp)
4259 {
4260         struct rte_eth_dev *dev = bp->eth_dev;
4261         int ret = 0;
4262
4263         if (dev->data->all_multicast) {
4264                 ret = bnxt_allmulticast_enable_op(dev);
4265                 if (ret)
4266                         return ret;
4267         }
4268         if (dev->data->promiscuous) {
4269                 ret = bnxt_promiscuous_enable_op(dev);
4270                 if (ret)
4271                         return ret;
4272         }
4273
4274         ret = bnxt_restore_mac_filters(bp);
4275         if (ret)
4276                 return ret;
4277
4278         ret = bnxt_restore_vlan_filters(bp);
4279         /* TODO restore other filters as well */
4280         return ret;
4281 }
4282
4283 static int bnxt_check_fw_ready(struct bnxt *bp)
4284 {
4285         int timeout = bp->fw_reset_max_msecs;
4286         int rc = 0;
4287
4288         do {
4289                 rc = bnxt_hwrm_poll_ver_get(bp);
4290                 if (rc == 0)
4291                         break;
4292                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4293                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4294         } while (rc && timeout > 0);
4295
4296         if (rc)
4297                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4298
4299         return rc;
4300 }
4301
4302 static void bnxt_dev_recover(void *arg)
4303 {
4304         struct bnxt *bp = arg;
4305         int rc = 0;
4306
4307         pthread_mutex_lock(&bp->err_recovery_lock);
4308
4309         if (!bp->fw_reset_min_msecs) {
4310                 rc = bnxt_check_fw_reset_done(bp);
4311                 if (rc)
4312                         goto err;
4313         }
4314
4315         /* Clear Error flag so that device re-init should happen */
4316         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4317
4318         rc = bnxt_check_fw_ready(bp);
4319         if (rc)
4320                 goto err;
4321
4322         rc = bnxt_init_resources(bp, true);
4323         if (rc) {
4324                 PMD_DRV_LOG(ERR,
4325                             "Failed to initialize resources after reset\n");
4326                 goto err;
4327         }
4328         /* clear reset flag as the device is initialized now */
4329         bp->flags &= ~BNXT_FLAG_FW_RESET;
4330
4331         rc = bnxt_dev_start_op(bp->eth_dev);
4332         if (rc) {
4333                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4334                 goto err_start;
4335         }
4336
4337         rc = bnxt_restore_filters(bp);
4338         if (rc)
4339                 goto err_start;
4340
4341         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4342         pthread_mutex_unlock(&bp->err_recovery_lock);
4343
4344         return;
4345 err_start:
4346         bnxt_dev_stop(bp->eth_dev);
4347 err:
4348         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4349         bnxt_uninit_resources(bp, false);
4350         if (bp->eth_dev->data->dev_conf.intr_conf.rmv)
4351                 rte_eth_dev_callback_process(bp->eth_dev,
4352                                              RTE_ETH_EVENT_INTR_RMV,
4353                                              NULL);
4354         pthread_mutex_unlock(&bp->err_recovery_lock);
4355         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4356 }
4357
4358 void bnxt_dev_reset_and_resume(void *arg)
4359 {
4360         struct bnxt *bp = arg;
4361         uint32_t us = US_PER_MS * bp->fw_reset_min_msecs;
4362         uint16_t val = 0;
4363         int rc;
4364
4365         bnxt_dev_cleanup(bp);
4366
4367         bnxt_wait_for_device_shutdown(bp);
4368
4369         /* During some fatal firmware error conditions, the PCI config space
4370          * register 0x2e which normally contains the subsystem ID will become
4371          * 0xffff. This register will revert back to the normal value after
4372          * the chip has completed core reset. If we detect this condition,
4373          * we can poll this config register immediately for the value to revert.
4374          */
4375         if (bp->flags & BNXT_FLAG_FATAL_ERROR) {
4376                 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4377                 if (rc < 0) {
4378                         PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4379                         return;
4380                 }
4381                 if (val == 0xffff) {
4382                         bp->fw_reset_min_msecs = 0;
4383                         us = 1;
4384                 }
4385         }
4386
4387         rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp);
4388         if (rc)
4389                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4390 }
4391
4392 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4393 {
4394         struct bnxt_error_recovery_info *info = bp->recovery_info;
4395         uint32_t reg = info->status_regs[index];
4396         uint32_t type, offset, val = 0;
4397         int ret = 0;
4398
4399         type = BNXT_FW_STATUS_REG_TYPE(reg);
4400         offset = BNXT_FW_STATUS_REG_OFF(reg);
4401
4402         switch (type) {
4403         case BNXT_FW_STATUS_REG_TYPE_CFG:
4404                 ret = rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4405                 if (ret < 0)
4406                         PMD_DRV_LOG(ERR, "Failed to read PCI offset %#x",
4407                                     offset);
4408                 break;
4409         case BNXT_FW_STATUS_REG_TYPE_GRC:
4410                 offset = info->mapped_status_regs[index];
4411                 /* FALLTHROUGH */
4412         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4413                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4414                                        offset));
4415                 break;
4416         }
4417
4418         return val;
4419 }
4420
4421 static int bnxt_fw_reset_all(struct bnxt *bp)
4422 {
4423         struct bnxt_error_recovery_info *info = bp->recovery_info;
4424         uint32_t i;
4425         int rc = 0;
4426
4427         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4428                 /* Reset through master function driver */
4429                 for (i = 0; i < info->reg_array_cnt; i++)
4430                         bnxt_write_fw_reset_reg(bp, i);
4431                 /* Wait for time specified by FW after triggering reset */
4432                 rte_delay_ms(info->master_func_wait_period_after_reset);
4433         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4434                 /* Reset with the help of Kong processor */
4435                 rc = bnxt_hwrm_fw_reset(bp);
4436                 if (rc)
4437                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4438         }
4439
4440         return rc;
4441 }
4442
4443 static void bnxt_fw_reset_cb(void *arg)
4444 {
4445         struct bnxt *bp = arg;
4446         struct bnxt_error_recovery_info *info = bp->recovery_info;
4447         int rc = 0;
4448
4449         /* Only Master function can do FW reset */
4450         if (bnxt_is_master_func(bp) &&
4451             bnxt_is_recovery_enabled(bp)) {
4452                 rc = bnxt_fw_reset_all(bp);
4453                 if (rc) {
4454                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4455                         return;
4456                 }
4457         }
4458
4459         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4460          * EXCEPTION_FATAL_ASYNC event to all the functions
4461          * (including MASTER FUNC). After receiving this Async, all the active
4462          * drivers should treat this case as FW initiated recovery
4463          */
4464         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4465                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4466                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4467
4468                 /* To recover from error */
4469                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4470                                   (void *)bp);
4471         }
4472 }
4473
4474 /* Driver should poll FW heartbeat, reset_counter with the frequency
4475  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4476  * When the driver detects heartbeat stop or change in reset_counter,
4477  * it has to trigger a reset to recover from the error condition.
4478  * A “master PF” is the function who will have the privilege to
4479  * initiate the chimp reset. The master PF will be elected by the
4480  * firmware and will be notified through async message.
4481  */
4482 static void bnxt_check_fw_health(void *arg)
4483 {
4484         struct bnxt *bp = arg;
4485         struct bnxt_error_recovery_info *info = bp->recovery_info;
4486         uint32_t val = 0, wait_msec;
4487
4488         if (!info || !bnxt_is_recovery_enabled(bp) ||
4489             is_bnxt_in_error(bp))
4490                 return;
4491
4492         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4493         if (val == info->last_heart_beat)
4494                 goto reset;
4495
4496         info->last_heart_beat = val;
4497
4498         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4499         if (val != info->last_reset_counter)
4500                 goto reset;
4501
4502         info->last_reset_counter = val;
4503
4504         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4505                           bnxt_check_fw_health, (void *)bp);
4506
4507         return;
4508 reset:
4509         /* Stop DMA to/from device */
4510         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4511         bp->flags |= BNXT_FLAG_FW_RESET;
4512
4513         bnxt_stop_rxtx(bp);
4514
4515         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4516
4517         if (bnxt_is_master_func(bp))
4518                 wait_msec = info->master_func_wait_period;
4519         else
4520                 wait_msec = info->normal_func_wait_period;
4521
4522         rte_eal_alarm_set(US_PER_MS * wait_msec,
4523                           bnxt_fw_reset_cb, (void *)bp);
4524 }
4525
4526 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4527 {
4528         uint32_t polling_freq;
4529
4530         pthread_mutex_lock(&bp->health_check_lock);
4531
4532         if (!bnxt_is_recovery_enabled(bp))
4533                 goto done;
4534
4535         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4536                 goto done;
4537
4538         polling_freq = bp->recovery_info->driver_polling_freq;
4539
4540         rte_eal_alarm_set(US_PER_MS * polling_freq,
4541                           bnxt_check_fw_health, (void *)bp);
4542         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4543
4544 done:
4545         pthread_mutex_unlock(&bp->health_check_lock);
4546 }
4547
4548 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4549 {
4550         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4551         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4552 }
4553
4554 static bool bnxt_vf_pciid(uint16_t device_id)
4555 {
4556         switch (device_id) {
4557         case BROADCOM_DEV_ID_57304_VF:
4558         case BROADCOM_DEV_ID_57406_VF:
4559         case BROADCOM_DEV_ID_5731X_VF:
4560         case BROADCOM_DEV_ID_5741X_VF:
4561         case BROADCOM_DEV_ID_57414_VF:
4562         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4563         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4564         case BROADCOM_DEV_ID_58802_VF:
4565         case BROADCOM_DEV_ID_57500_VF1:
4566         case BROADCOM_DEV_ID_57500_VF2:
4567         case BROADCOM_DEV_ID_58818_VF:
4568                 /* FALLTHROUGH */
4569                 return true;
4570         default:
4571                 return false;
4572         }
4573 }
4574
4575 /* Phase 5 device */
4576 static bool bnxt_p5_device(uint16_t device_id)
4577 {
4578         switch (device_id) {
4579         case BROADCOM_DEV_ID_57508:
4580         case BROADCOM_DEV_ID_57504:
4581         case BROADCOM_DEV_ID_57502:
4582         case BROADCOM_DEV_ID_57508_MF1:
4583         case BROADCOM_DEV_ID_57504_MF1:
4584         case BROADCOM_DEV_ID_57502_MF1:
4585         case BROADCOM_DEV_ID_57508_MF2:
4586         case BROADCOM_DEV_ID_57504_MF2:
4587         case BROADCOM_DEV_ID_57502_MF2:
4588         case BROADCOM_DEV_ID_57500_VF1:
4589         case BROADCOM_DEV_ID_57500_VF2:
4590         case BROADCOM_DEV_ID_58812:
4591         case BROADCOM_DEV_ID_58814:
4592         case BROADCOM_DEV_ID_58818:
4593         case BROADCOM_DEV_ID_58818_VF:
4594                 /* FALLTHROUGH */
4595                 return true;
4596         default:
4597                 return false;
4598         }
4599 }
4600
4601 bool bnxt_stratus_device(struct bnxt *bp)
4602 {
4603         uint16_t device_id = bp->pdev->id.device_id;
4604
4605         switch (device_id) {
4606         case BROADCOM_DEV_ID_STRATUS_NIC:
4607         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4608         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4609                 /* FALLTHROUGH */
4610                 return true;
4611         default:
4612                 return false;
4613         }
4614 }
4615
4616 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev)
4617 {
4618         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4619         struct bnxt *bp = eth_dev->data->dev_private;
4620
4621         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4622         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4623         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4624         if (!bp->bar0 || !bp->doorbell_base) {
4625                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4626                 return -ENODEV;
4627         }
4628
4629         bp->eth_dev = eth_dev;
4630         bp->pdev = pci_dev;
4631
4632         return 0;
4633 }
4634
4635 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4636                                   struct bnxt_ctx_pg_info *ctx_pg,
4637                                   uint32_t mem_size,
4638                                   const char *suffix,
4639                                   uint16_t idx)
4640 {
4641         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4642         const struct rte_memzone *mz = NULL;
4643         char mz_name[RTE_MEMZONE_NAMESIZE];
4644         rte_iova_t mz_phys_addr;
4645         uint64_t valid_bits = 0;
4646         uint32_t sz;
4647         int i;
4648
4649         if (!mem_size)
4650                 return 0;
4651
4652         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4653                          BNXT_PAGE_SIZE;
4654         rmem->page_size = BNXT_PAGE_SIZE;
4655         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4656         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4657         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4658
4659         valid_bits = PTU_PTE_VALID;
4660
4661         if (rmem->nr_pages > 1) {
4662                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4663                          "bnxt_ctx_pg_tbl%s_%x_%d",
4664                          suffix, idx, bp->eth_dev->data->port_id);
4665                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4666                 mz = rte_memzone_lookup(mz_name);
4667                 if (!mz) {
4668                         mz = rte_memzone_reserve_aligned(mz_name,
4669                                                 rmem->nr_pages * 8,
4670                                                 SOCKET_ID_ANY,
4671                                                 RTE_MEMZONE_2MB |
4672                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4673                                                 RTE_MEMZONE_IOVA_CONTIG,
4674                                                 BNXT_PAGE_SIZE);
4675                         if (mz == NULL)
4676                                 return -ENOMEM;
4677                 }
4678
4679                 memset(mz->addr, 0, mz->len);
4680                 mz_phys_addr = mz->iova;
4681
4682                 rmem->pg_tbl = mz->addr;
4683                 rmem->pg_tbl_map = mz_phys_addr;
4684                 rmem->pg_tbl_mz = mz;
4685         }
4686
4687         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4688                  suffix, idx, bp->eth_dev->data->port_id);
4689         mz = rte_memzone_lookup(mz_name);
4690         if (!mz) {
4691                 mz = rte_memzone_reserve_aligned(mz_name,
4692                                                  mem_size,
4693                                                  SOCKET_ID_ANY,
4694                                                  RTE_MEMZONE_1GB |
4695                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4696                                                  RTE_MEMZONE_IOVA_CONTIG,
4697                                                  BNXT_PAGE_SIZE);
4698                 if (mz == NULL)
4699                         return -ENOMEM;
4700         }
4701
4702         memset(mz->addr, 0, mz->len);
4703         mz_phys_addr = mz->iova;
4704
4705         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4706                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4707                 rmem->dma_arr[i] = mz_phys_addr + sz;
4708
4709                 if (rmem->nr_pages > 1) {
4710                         if (i == rmem->nr_pages - 2 &&
4711                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4712                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4713                         else if (i == rmem->nr_pages - 1 &&
4714                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4715                                 valid_bits |= PTU_PTE_LAST;
4716
4717                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4718                                                            valid_bits);
4719                 }
4720         }
4721
4722         rmem->mz = mz;
4723         if (rmem->vmem_size)
4724                 rmem->vmem = (void **)mz->addr;
4725         rmem->dma_arr[0] = mz_phys_addr;
4726         return 0;
4727 }
4728
4729 static void bnxt_free_ctx_mem(struct bnxt *bp)
4730 {
4731         int i;
4732
4733         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4734                 return;
4735
4736         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4737         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4738         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4739         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4740         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4741         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4742         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4743         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4744         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4745         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4746         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4747
4748         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4749                 if (bp->ctx->tqm_mem[i])
4750                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4751         }
4752
4753         rte_free(bp->ctx);
4754         bp->ctx = NULL;
4755 }
4756
4757 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4758
4759 #define min_t(type, x, y) ({                    \
4760         type __min1 = (x);                      \
4761         type __min2 = (y);                      \
4762         __min1 < __min2 ? __min1 : __min2; })
4763
4764 #define max_t(type, x, y) ({                    \
4765         type __max1 = (x);                      \
4766         type __max2 = (y);                      \
4767         __max1 > __max2 ? __max1 : __max2; })
4768
4769 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4770
4771 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4772 {
4773         struct bnxt_ctx_pg_info *ctx_pg;
4774         struct bnxt_ctx_mem_info *ctx;
4775         uint32_t mem_size, ena, entries;
4776         uint32_t entries_sp, min;
4777         int i, rc;
4778
4779         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4780         if (rc) {
4781                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4782                 return rc;
4783         }
4784         ctx = bp->ctx;
4785         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4786                 return 0;
4787
4788         ctx_pg = &ctx->qp_mem;
4789         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4790         if (ctx->qp_entry_size) {
4791                 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4792                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4793                 if (rc)
4794                         return rc;
4795         }
4796
4797         ctx_pg = &ctx->srq_mem;
4798         ctx_pg->entries = ctx->srq_max_l2_entries;
4799         if (ctx->srq_entry_size) {
4800                 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4801                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4802                 if (rc)
4803                         return rc;
4804         }
4805
4806         ctx_pg = &ctx->cq_mem;
4807         ctx_pg->entries = ctx->cq_max_l2_entries;
4808         if (ctx->cq_entry_size) {
4809                 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4810                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4811                 if (rc)
4812                         return rc;
4813         }
4814
4815         ctx_pg = &ctx->vnic_mem;
4816         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4817                 ctx->vnic_max_ring_table_entries;
4818         if (ctx->vnic_entry_size) {
4819                 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4820                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4821                 if (rc)
4822                         return rc;
4823         }
4824
4825         ctx_pg = &ctx->stat_mem;
4826         ctx_pg->entries = ctx->stat_max_entries;
4827         if (ctx->stat_entry_size) {
4828                 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4829                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4830                 if (rc)
4831                         return rc;
4832         }
4833
4834         min = ctx->tqm_min_entries_per_ring;
4835
4836         entries_sp = ctx->qp_max_l2_entries +
4837                      ctx->vnic_max_vnic_entries +
4838                      2 * ctx->qp_min_qp1_entries + min;
4839         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4840
4841         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4842         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4843         entries = clamp_t(uint32_t, entries, min,
4844                           ctx->tqm_max_entries_per_ring);
4845         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4846                 /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7.
4847                  * i > 8 is other ext rings.
4848                  */
4849                 ctx_pg = ctx->tqm_mem[i];
4850                 ctx_pg->entries = i ? entries : entries_sp;
4851                 if (ctx->tqm_entry_size) {
4852                         mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4853                         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size,
4854                                                     "tqm_mem", i);
4855                         if (rc)
4856                                 return rc;
4857                 }
4858                 if (i < BNXT_MAX_TQM_LEGACY_RINGS)
4859                         ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4860                 else
4861                         ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8;
4862         }
4863
4864         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4865         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4866         if (rc)
4867                 PMD_DRV_LOG(ERR,
4868                             "Failed to configure context mem: rc = %d\n", rc);
4869         else
4870                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4871
4872         return rc;
4873 }
4874
4875 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4876 {
4877         struct rte_pci_device *pci_dev = bp->pdev;
4878         char mz_name[RTE_MEMZONE_NAMESIZE];
4879         const struct rte_memzone *mz = NULL;
4880         uint32_t total_alloc_len;
4881         rte_iova_t mz_phys_addr;
4882
4883         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4884                 return 0;
4885
4886         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4887                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4888                  pci_dev->addr.bus, pci_dev->addr.devid,
4889                  pci_dev->addr.function, "rx_port_stats");
4890         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4891         mz = rte_memzone_lookup(mz_name);
4892         total_alloc_len =
4893                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4894                                        sizeof(struct rx_port_stats_ext) + 512);
4895         if (!mz) {
4896                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4897                                          SOCKET_ID_ANY,
4898                                          RTE_MEMZONE_2MB |
4899                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4900                                          RTE_MEMZONE_IOVA_CONTIG);
4901                 if (mz == NULL)
4902                         return -ENOMEM;
4903         }
4904         memset(mz->addr, 0, mz->len);
4905         mz_phys_addr = mz->iova;
4906
4907         bp->rx_mem_zone = (const void *)mz;
4908         bp->hw_rx_port_stats = mz->addr;
4909         bp->hw_rx_port_stats_map = mz_phys_addr;
4910
4911         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4912                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4913                  pci_dev->addr.bus, pci_dev->addr.devid,
4914                  pci_dev->addr.function, "tx_port_stats");
4915         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4916         mz = rte_memzone_lookup(mz_name);
4917         total_alloc_len =
4918                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4919                                        sizeof(struct tx_port_stats_ext) + 512);
4920         if (!mz) {
4921                 mz = rte_memzone_reserve(mz_name,
4922                                          total_alloc_len,
4923                                          SOCKET_ID_ANY,
4924                                          RTE_MEMZONE_2MB |
4925                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4926                                          RTE_MEMZONE_IOVA_CONTIG);
4927                 if (mz == NULL)
4928                         return -ENOMEM;
4929         }
4930         memset(mz->addr, 0, mz->len);
4931         mz_phys_addr = mz->iova;
4932
4933         bp->tx_mem_zone = (const void *)mz;
4934         bp->hw_tx_port_stats = mz->addr;
4935         bp->hw_tx_port_stats_map = mz_phys_addr;
4936         bp->flags |= BNXT_FLAG_PORT_STATS;
4937
4938         /* Display extended statistics if FW supports it */
4939         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4940             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4941             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4942                 return 0;
4943
4944         bp->hw_rx_port_stats_ext = (void *)
4945                 ((uint8_t *)bp->hw_rx_port_stats +
4946                  sizeof(struct rx_port_stats));
4947         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4948                 sizeof(struct rx_port_stats);
4949         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4950
4951         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4952             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4953                 bp->hw_tx_port_stats_ext = (void *)
4954                         ((uint8_t *)bp->hw_tx_port_stats +
4955                          sizeof(struct tx_port_stats));
4956                 bp->hw_tx_port_stats_ext_map =
4957                         bp->hw_tx_port_stats_map +
4958                         sizeof(struct tx_port_stats);
4959                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4960         }
4961
4962         return 0;
4963 }
4964
4965 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4966 {
4967         struct bnxt *bp = eth_dev->data->dev_private;
4968         int rc = 0;
4969
4970         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4971                                                RTE_ETHER_ADDR_LEN *
4972                                                bp->max_l2_ctx,
4973                                                0);
4974         if (eth_dev->data->mac_addrs == NULL) {
4975                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4976                 return -ENOMEM;
4977         }
4978
4979         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4980                 if (BNXT_PF(bp))
4981                         return -EINVAL;
4982
4983                 /* Generate a random MAC address, if none was assigned by PF */
4984                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4985                 bnxt_eth_hw_addr_random(bp->mac_addr);
4986                 PMD_DRV_LOG(INFO,
4987                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4988                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4989                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4990
4991                 rc = bnxt_hwrm_set_mac(bp);
4992                 if (rc)
4993                         return rc;
4994         }
4995
4996         /* Copy the permanent MAC from the FUNC_QCAPS response */
4997         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4998
4999         return rc;
5000 }
5001
5002 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5003 {
5004         int rc = 0;
5005
5006         /* MAC is already configured in FW */
5007         if (BNXT_HAS_DFLT_MAC_SET(bp))
5008                 return 0;
5009
5010         /* Restore the old MAC configured */
5011         rc = bnxt_hwrm_set_mac(bp);
5012         if (rc)
5013                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5014
5015         return rc;
5016 }
5017
5018 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5019 {
5020         if (!BNXT_PF(bp))
5021                 return;
5022
5023         memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5024
5025         if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
5026                 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
5027         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
5028         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
5029         BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
5030         BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
5031 }
5032
5033 struct bnxt *
5034 bnxt_get_bp(uint16_t port)
5035 {
5036         struct bnxt *bp;
5037         struct rte_eth_dev *dev;
5038
5039         if (!rte_eth_dev_is_valid_port(port)) {
5040                 PMD_DRV_LOG(ERR, "Invalid port %d\n", port);
5041                 return NULL;
5042         }
5043
5044         dev = &rte_eth_devices[port];
5045         if (!is_bnxt_supported(dev)) {
5046                 PMD_DRV_LOG(ERR, "Device %d not supported\n", port);
5047                 return NULL;
5048         }
5049
5050         bp = (struct bnxt *)dev->data->dev_private;
5051         if (!BNXT_TRUFLOW_EN(bp)) {
5052                 PMD_DRV_LOG(ERR, "TRUFLOW not enabled\n");
5053                 return NULL;
5054         }
5055
5056         return bp;
5057 }
5058
5059 uint16_t
5060 bnxt_get_svif(uint16_t port_id, bool func_svif,
5061               enum bnxt_ulp_intf_type type)
5062 {
5063         struct rte_eth_dev *eth_dev;
5064         struct bnxt *bp;
5065
5066         eth_dev = &rte_eth_devices[port_id];
5067         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5068                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5069                 if (!vfr)
5070                         return 0;
5071
5072                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5073                         return vfr->svif;
5074
5075                 eth_dev = vfr->parent_dev;
5076         }
5077
5078         bp = eth_dev->data->dev_private;
5079
5080         return func_svif ? bp->func_svif : bp->port_svif;
5081 }
5082
5083 void
5084 bnxt_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type,
5085                    uint8_t *mac, uint8_t *parent_mac)
5086 {
5087         struct rte_eth_dev *eth_dev;
5088         struct bnxt *bp;
5089
5090         if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF &&
5091             type != BNXT_ULP_INTF_TYPE_PF)
5092                 return;
5093
5094         eth_dev = &rte_eth_devices[port];
5095         bp = eth_dev->data->dev_private;
5096         memcpy(mac, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5097
5098         if (type == BNXT_ULP_INTF_TYPE_TRUSTED_VF)
5099                 memcpy(parent_mac, bp->parent->mac_addr, RTE_ETHER_ADDR_LEN);
5100 }
5101
5102 uint16_t
5103 bnxt_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5104 {
5105         struct rte_eth_dev *eth_dev;
5106         struct bnxt *bp;
5107
5108         if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF)
5109                 return 0;
5110
5111         eth_dev = &rte_eth_devices[port];
5112         bp = eth_dev->data->dev_private;
5113
5114         return bp->parent->vnic;
5115 }
5116 uint16_t
5117 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5118 {
5119         struct rte_eth_dev *eth_dev;
5120         struct bnxt_vnic_info *vnic;
5121         struct bnxt *bp;
5122
5123         eth_dev = &rte_eth_devices[port];
5124         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5125                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5126                 if (!vfr)
5127                         return 0;
5128
5129                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5130                         return vfr->dflt_vnic_id;
5131
5132                 eth_dev = vfr->parent_dev;
5133         }
5134
5135         bp = eth_dev->data->dev_private;
5136
5137         vnic = BNXT_GET_DEFAULT_VNIC(bp);
5138
5139         return vnic->fw_vnic_id;
5140 }
5141
5142 uint16_t
5143 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5144 {
5145         struct rte_eth_dev *eth_dev;
5146         struct bnxt *bp;
5147
5148         eth_dev = &rte_eth_devices[port];
5149         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5150                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5151                 if (!vfr)
5152                         return 0;
5153
5154                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5155                         return vfr->fw_fid;
5156
5157                 eth_dev = vfr->parent_dev;
5158         }
5159
5160         bp = eth_dev->data->dev_private;
5161
5162         return bp->fw_fid;
5163 }
5164
5165 enum bnxt_ulp_intf_type
5166 bnxt_get_interface_type(uint16_t port)
5167 {
5168         struct rte_eth_dev *eth_dev;
5169         struct bnxt *bp;
5170
5171         eth_dev = &rte_eth_devices[port];
5172         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5173                 return BNXT_ULP_INTF_TYPE_VF_REP;
5174
5175         bp = eth_dev->data->dev_private;
5176         if (BNXT_PF(bp))
5177                 return BNXT_ULP_INTF_TYPE_PF;
5178         else if (BNXT_VF_IS_TRUSTED(bp))
5179                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5180         else if (BNXT_VF(bp))
5181                 return BNXT_ULP_INTF_TYPE_VF;
5182
5183         return BNXT_ULP_INTF_TYPE_INVALID;
5184 }
5185
5186 uint16_t
5187 bnxt_get_phy_port_id(uint16_t port_id)
5188 {
5189         struct bnxt_representor *vfr;
5190         struct rte_eth_dev *eth_dev;
5191         struct bnxt *bp;
5192
5193         eth_dev = &rte_eth_devices[port_id];
5194         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5195                 vfr = eth_dev->data->dev_private;
5196                 if (!vfr)
5197                         return 0;
5198
5199                 eth_dev = vfr->parent_dev;
5200         }
5201
5202         bp = eth_dev->data->dev_private;
5203
5204         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5205 }
5206
5207 uint16_t
5208 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5209 {
5210         struct rte_eth_dev *eth_dev;
5211         struct bnxt *bp;
5212
5213         eth_dev = &rte_eth_devices[port_id];
5214         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5215                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5216                 if (!vfr)
5217                         return 0;
5218
5219                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5220                         return vfr->fw_fid - 1;
5221
5222                 eth_dev = vfr->parent_dev;
5223         }
5224
5225         bp = eth_dev->data->dev_private;
5226
5227         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5228 }
5229
5230 uint16_t
5231 bnxt_get_vport(uint16_t port_id)
5232 {
5233         return (1 << bnxt_get_phy_port_id(port_id));
5234 }
5235
5236 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5237 {
5238         struct bnxt_error_recovery_info *info = bp->recovery_info;
5239
5240         if (info) {
5241                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5242                         memset(info, 0, sizeof(*info));
5243                 return;
5244         }
5245
5246         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5247                 return;
5248
5249         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5250                            sizeof(*info), 0);
5251         if (!info)
5252                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5253
5254         bp->recovery_info = info;
5255 }
5256
5257 static void bnxt_check_fw_status(struct bnxt *bp)
5258 {
5259         uint32_t fw_status;
5260
5261         if (!(bp->recovery_info &&
5262               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5263                 return;
5264
5265         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5266         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5267                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5268                             fw_status);
5269 }
5270
5271 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5272 {
5273         struct bnxt_error_recovery_info *info = bp->recovery_info;
5274         uint32_t status_loc;
5275         uint32_t sig_ver;
5276
5277         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5278                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5279         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5280                                    BNXT_GRCP_WINDOW_2_BASE +
5281                                    offsetof(struct hcomm_status,
5282                                             sig_ver)));
5283         /* If the signature is absent, then FW does not support this feature */
5284         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5285             HCOMM_STATUS_SIGNATURE_VAL)
5286                 return 0;
5287
5288         if (!info) {
5289                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5290                                    sizeof(*info), 0);
5291                 if (!info)
5292                         return -ENOMEM;
5293                 bp->recovery_info = info;
5294         } else {
5295                 memset(info, 0, sizeof(*info));
5296         }
5297
5298         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5299                                       BNXT_GRCP_WINDOW_2_BASE +
5300                                       offsetof(struct hcomm_status,
5301                                                fw_status_loc)));
5302
5303         /* Only pre-map the FW health status GRC register */
5304         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5305                 return 0;
5306
5307         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5308         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5309                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5310
5311         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5312                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5313
5314         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5315
5316         return 0;
5317 }
5318
5319 /* This function gets the FW version along with the
5320  * capabilities(MAX and current) of the function, vnic,
5321  * error recovery, phy and other chip related info
5322  */
5323 static int bnxt_get_config(struct bnxt *bp)
5324 {
5325         uint16_t mtu;
5326         int rc = 0;
5327
5328         bp->fw_cap = 0;
5329
5330         rc = bnxt_map_hcomm_fw_status_reg(bp);
5331         if (rc)
5332                 return rc;
5333
5334         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5335         if (rc) {
5336                 bnxt_check_fw_status(bp);
5337                 return rc;
5338         }
5339
5340         rc = bnxt_hwrm_func_reset(bp);
5341         if (rc)
5342                 return -EIO;
5343
5344         rc = bnxt_hwrm_vnic_qcaps(bp);
5345         if (rc)
5346                 return rc;
5347
5348         rc = bnxt_hwrm_queue_qportcfg(bp);
5349         if (rc)
5350                 return rc;
5351
5352         /* Get the MAX capabilities for this function.
5353          * This function also allocates context memory for TQM rings and
5354          * informs the firmware about this allocated backing store memory.
5355          */
5356         rc = bnxt_hwrm_func_qcaps(bp);
5357         if (rc)
5358                 return rc;
5359
5360         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5361         if (rc)
5362                 return rc;
5363
5364         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5365         if (rc)
5366                 return rc;
5367
5368         bnxt_hwrm_port_mac_qcfg(bp);
5369
5370         bnxt_hwrm_parent_pf_qcfg(bp);
5371
5372         bnxt_hwrm_port_phy_qcaps(bp);
5373
5374         bnxt_alloc_error_recovery_info(bp);
5375         /* Get the adapter error recovery support info */
5376         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5377         if (rc)
5378                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5379
5380         bnxt_hwrm_port_led_qcaps(bp);
5381
5382         return 0;
5383 }
5384
5385 static int
5386 bnxt_init_locks(struct bnxt *bp)
5387 {
5388         int err;
5389
5390         err = pthread_mutex_init(&bp->flow_lock, NULL);
5391         if (err) {
5392                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5393                 return err;
5394         }
5395
5396         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5397         if (err) {
5398                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5399                 return err;
5400         }
5401
5402         err = pthread_mutex_init(&bp->health_check_lock, NULL);
5403         if (err) {
5404                 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5405                 return err;
5406         }
5407
5408         err = pthread_mutex_init(&bp->err_recovery_lock, NULL);
5409         if (err)
5410                 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n");
5411
5412         return err;
5413 }
5414
5415 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5416 {
5417         int rc = 0;
5418
5419         rc = bnxt_get_config(bp);
5420         if (rc)
5421                 return rc;
5422
5423         if (!reconfig_dev) {
5424                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5425                 if (rc)
5426                         return rc;
5427         } else {
5428                 rc = bnxt_restore_dflt_mac(bp);
5429                 if (rc)
5430                         return rc;
5431         }
5432
5433         bnxt_config_vf_req_fwd(bp);
5434
5435         rc = bnxt_hwrm_func_driver_register(bp);
5436         if (rc) {
5437                 PMD_DRV_LOG(ERR, "Failed to register driver");
5438                 return -EBUSY;
5439         }
5440
5441         if (BNXT_PF(bp)) {
5442                 if (bp->pdev->max_vfs) {
5443                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5444                         if (rc) {
5445                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5446                                 return rc;
5447                         }
5448                 } else {
5449                         rc = bnxt_hwrm_allocate_pf_only(bp);
5450                         if (rc) {
5451                                 PMD_DRV_LOG(ERR,
5452                                             "Failed to allocate PF resources");
5453                                 return rc;
5454                         }
5455                 }
5456         }
5457
5458         rc = bnxt_alloc_mem(bp, reconfig_dev);
5459         if (rc)
5460                 return rc;
5461
5462         rc = bnxt_setup_int(bp);
5463         if (rc)
5464                 return rc;
5465
5466         rc = bnxt_request_int(bp);
5467         if (rc)
5468                 return rc;
5469
5470         rc = bnxt_init_ctx_mem(bp);
5471         if (rc) {
5472                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5473                 return rc;
5474         }
5475
5476         return 0;
5477 }
5478
5479 static int
5480 bnxt_parse_devarg_accum_stats(__rte_unused const char *key,
5481                               const char *value, void *opaque_arg)
5482 {
5483         struct bnxt *bp = opaque_arg;
5484         unsigned long accum_stats;
5485         char *end = NULL;
5486
5487         if (!value || !opaque_arg) {
5488                 PMD_DRV_LOG(ERR,
5489                             "Invalid parameter passed to accum-stats devargs.\n");
5490                 return -EINVAL;
5491         }
5492
5493         accum_stats = strtoul(value, &end, 10);
5494         if (end == NULL || *end != '\0' ||
5495             (accum_stats == ULONG_MAX && errno == ERANGE)) {
5496                 PMD_DRV_LOG(ERR,
5497                             "Invalid parameter passed to accum-stats devargs.\n");
5498                 return -EINVAL;
5499         }
5500
5501         if (BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats)) {
5502                 PMD_DRV_LOG(ERR,
5503                             "Invalid value passed to accum-stats devargs.\n");
5504                 return -EINVAL;
5505         }
5506
5507         if (accum_stats) {
5508                 bp->flags2 |= BNXT_FLAGS2_ACCUM_STATS_EN;
5509                 PMD_DRV_LOG(INFO, "Host-based accum-stats feature enabled.\n");
5510         } else {
5511                 bp->flags2 &= ~BNXT_FLAGS2_ACCUM_STATS_EN;
5512                 PMD_DRV_LOG(INFO, "Host-based accum-stats feature disabled.\n");
5513         }
5514
5515         return 0;
5516 }
5517
5518 static int
5519 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5520                              const char *value, void *opaque_arg)
5521 {
5522         struct bnxt *bp = opaque_arg;
5523         unsigned long flow_xstat;
5524         char *end = NULL;
5525
5526         if (!value || !opaque_arg) {
5527                 PMD_DRV_LOG(ERR,
5528                             "Invalid parameter passed to flow_xstat devarg.\n");
5529                 return -EINVAL;
5530         }
5531
5532         flow_xstat = strtoul(value, &end, 10);
5533         if (end == NULL || *end != '\0' ||
5534             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5535                 PMD_DRV_LOG(ERR,
5536                             "Invalid parameter passed to flow_xstat devarg.\n");
5537                 return -EINVAL;
5538         }
5539
5540         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5541                 PMD_DRV_LOG(ERR,
5542                             "Invalid value passed to flow_xstat devarg.\n");
5543                 return -EINVAL;
5544         }
5545
5546         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5547         if (BNXT_FLOW_XSTATS_EN(bp))
5548                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5549
5550         return 0;
5551 }
5552
5553 static int
5554 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5555                                         const char *value, void *opaque_arg)
5556 {
5557         struct bnxt *bp = opaque_arg;
5558         unsigned long max_num_kflows;
5559         char *end = NULL;
5560
5561         if (!value || !opaque_arg) {
5562                 PMD_DRV_LOG(ERR,
5563                         "Invalid parameter passed to max_num_kflows devarg.\n");
5564                 return -EINVAL;
5565         }
5566
5567         max_num_kflows = strtoul(value, &end, 10);
5568         if (end == NULL || *end != '\0' ||
5569                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5570                 PMD_DRV_LOG(ERR,
5571                         "Invalid parameter passed to max_num_kflows devarg.\n");
5572                 return -EINVAL;
5573         }
5574
5575         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5576                 PMD_DRV_LOG(ERR,
5577                         "Invalid value passed to max_num_kflows devarg.\n");
5578                 return -EINVAL;
5579         }
5580
5581         bp->max_num_kflows = max_num_kflows;
5582         if (bp->max_num_kflows)
5583                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5584                                 max_num_kflows);
5585
5586         return 0;
5587 }
5588
5589 static int
5590 bnxt_parse_devarg_app_id(__rte_unused const char *key,
5591                                  const char *value, void *opaque_arg)
5592 {
5593         struct bnxt *bp = opaque_arg;
5594         unsigned long app_id;
5595         char *end = NULL;
5596
5597         if (!value || !opaque_arg) {
5598                 PMD_DRV_LOG(ERR,
5599                             "Invalid parameter passed to app-id "
5600                             "devargs.\n");
5601                 return -EINVAL;
5602         }
5603
5604         app_id = strtoul(value, &end, 10);
5605         if (end == NULL || *end != '\0' ||
5606             (app_id == ULONG_MAX && errno == ERANGE)) {
5607                 PMD_DRV_LOG(ERR,
5608                             "Invalid parameter passed to app_id "
5609                             "devargs.\n");
5610                 return -EINVAL;
5611         }
5612
5613         if (BNXT_DEVARG_APP_ID_INVALID(app_id)) {
5614                 PMD_DRV_LOG(ERR, "Invalid app-id(%d) devargs.\n",
5615                             (uint16_t)app_id);
5616                 return -EINVAL;
5617         }
5618
5619         bp->app_id = app_id;
5620         PMD_DRV_LOG(INFO, "app-id=%d feature enabled.\n", (uint16_t)app_id);
5621
5622         return 0;
5623 }
5624
5625 static int
5626 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5627                             const char *value, void *opaque_arg)
5628 {
5629         struct bnxt_representor *vfr_bp = opaque_arg;
5630         unsigned long rep_is_pf;
5631         char *end = NULL;
5632
5633         if (!value || !opaque_arg) {
5634                 PMD_DRV_LOG(ERR,
5635                             "Invalid parameter passed to rep_is_pf devargs.\n");
5636                 return -EINVAL;
5637         }
5638
5639         rep_is_pf = strtoul(value, &end, 10);
5640         if (end == NULL || *end != '\0' ||
5641             (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5642                 PMD_DRV_LOG(ERR,
5643                             "Invalid parameter passed to rep_is_pf devargs.\n");
5644                 return -EINVAL;
5645         }
5646
5647         if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5648                 PMD_DRV_LOG(ERR,
5649                             "Invalid value passed to rep_is_pf devargs.\n");
5650                 return -EINVAL;
5651         }
5652
5653         vfr_bp->flags |= rep_is_pf;
5654         if (BNXT_REP_PF(vfr_bp))
5655                 PMD_DRV_LOG(INFO, "PF representor\n");
5656         else
5657                 PMD_DRV_LOG(INFO, "VF representor\n");
5658
5659         return 0;
5660 }
5661
5662 static int
5663 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5664                                const char *value, void *opaque_arg)
5665 {
5666         struct bnxt_representor *vfr_bp = opaque_arg;
5667         unsigned long rep_based_pf;
5668         char *end = NULL;
5669
5670         if (!value || !opaque_arg) {
5671                 PMD_DRV_LOG(ERR,
5672                             "Invalid parameter passed to rep_based_pf "
5673                             "devargs.\n");
5674                 return -EINVAL;
5675         }
5676
5677         rep_based_pf = strtoul(value, &end, 10);
5678         if (end == NULL || *end != '\0' ||
5679             (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5680                 PMD_DRV_LOG(ERR,
5681                             "Invalid parameter passed to rep_based_pf "
5682                             "devargs.\n");
5683                 return -EINVAL;
5684         }
5685
5686         if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5687                 PMD_DRV_LOG(ERR,
5688                             "Invalid value passed to rep_based_pf devargs.\n");
5689                 return -EINVAL;
5690         }
5691
5692         vfr_bp->rep_based_pf = rep_based_pf;
5693         vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
5694
5695         PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5696
5697         return 0;
5698 }
5699
5700 static int
5701 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5702                             const char *value, void *opaque_arg)
5703 {
5704         struct bnxt_representor *vfr_bp = opaque_arg;
5705         unsigned long rep_q_r2f;
5706         char *end = NULL;
5707
5708         if (!value || !opaque_arg) {
5709                 PMD_DRV_LOG(ERR,
5710                             "Invalid parameter passed to rep_q_r2f "
5711                             "devargs.\n");
5712                 return -EINVAL;
5713         }
5714
5715         rep_q_r2f = strtoul(value, &end, 10);
5716         if (end == NULL || *end != '\0' ||
5717             (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5718                 PMD_DRV_LOG(ERR,
5719                             "Invalid parameter passed to rep_q_r2f "
5720                             "devargs.\n");
5721                 return -EINVAL;
5722         }
5723
5724         if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5725                 PMD_DRV_LOG(ERR,
5726                             "Invalid value passed to rep_q_r2f devargs.\n");
5727                 return -EINVAL;
5728         }
5729
5730         vfr_bp->rep_q_r2f = rep_q_r2f;
5731         vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5732         PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5733
5734         return 0;
5735 }
5736
5737 static int
5738 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5739                             const char *value, void *opaque_arg)
5740 {
5741         struct bnxt_representor *vfr_bp = opaque_arg;
5742         unsigned long rep_q_f2r;
5743         char *end = NULL;
5744
5745         if (!value || !opaque_arg) {
5746                 PMD_DRV_LOG(ERR,
5747                             "Invalid parameter passed to rep_q_f2r "
5748                             "devargs.\n");
5749                 return -EINVAL;
5750         }
5751
5752         rep_q_f2r = strtoul(value, &end, 10);
5753         if (end == NULL || *end != '\0' ||
5754             (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5755                 PMD_DRV_LOG(ERR,
5756                             "Invalid parameter passed to rep_q_f2r "
5757                             "devargs.\n");
5758                 return -EINVAL;
5759         }
5760
5761         if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5762                 PMD_DRV_LOG(ERR,
5763                             "Invalid value passed to rep_q_f2r devargs.\n");
5764                 return -EINVAL;
5765         }
5766
5767         vfr_bp->rep_q_f2r = rep_q_f2r;
5768         vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5769         PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5770
5771         return 0;
5772 }
5773
5774 static int
5775 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5776                              const char *value, void *opaque_arg)
5777 {
5778         struct bnxt_representor *vfr_bp = opaque_arg;
5779         unsigned long rep_fc_r2f;
5780         char *end = NULL;
5781
5782         if (!value || !opaque_arg) {
5783                 PMD_DRV_LOG(ERR,
5784                             "Invalid parameter passed to rep_fc_r2f "
5785                             "devargs.\n");
5786                 return -EINVAL;
5787         }
5788
5789         rep_fc_r2f = strtoul(value, &end, 10);
5790         if (end == NULL || *end != '\0' ||
5791             (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5792                 PMD_DRV_LOG(ERR,
5793                             "Invalid parameter passed to rep_fc_r2f "
5794                             "devargs.\n");
5795                 return -EINVAL;
5796         }
5797
5798         if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5799                 PMD_DRV_LOG(ERR,
5800                             "Invalid value passed to rep_fc_r2f devargs.\n");
5801                 return -EINVAL;
5802         }
5803
5804         vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5805         vfr_bp->rep_fc_r2f = rep_fc_r2f;
5806         PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5807
5808         return 0;
5809 }
5810
5811 static int
5812 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5813                              const char *value, void *opaque_arg)
5814 {
5815         struct bnxt_representor *vfr_bp = opaque_arg;
5816         unsigned long rep_fc_f2r;
5817         char *end = NULL;
5818
5819         if (!value || !opaque_arg) {
5820                 PMD_DRV_LOG(ERR,
5821                             "Invalid parameter passed to rep_fc_f2r "
5822                             "devargs.\n");
5823                 return -EINVAL;
5824         }
5825
5826         rep_fc_f2r = strtoul(value, &end, 10);
5827         if (end == NULL || *end != '\0' ||
5828             (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5829                 PMD_DRV_LOG(ERR,
5830                             "Invalid parameter passed to rep_fc_f2r "
5831                             "devargs.\n");
5832                 return -EINVAL;
5833         }
5834
5835         if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5836                 PMD_DRV_LOG(ERR,
5837                             "Invalid value passed to rep_fc_f2r devargs.\n");
5838                 return -EINVAL;
5839         }
5840
5841         vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5842         vfr_bp->rep_fc_f2r = rep_fc_f2r;
5843         PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5844
5845         return 0;
5846 }
5847
5848 static int
5849 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5850 {
5851         struct rte_kvargs *kvlist;
5852         int ret;
5853
5854         if (devargs == NULL)
5855                 return 0;
5856
5857         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5858         if (kvlist == NULL)
5859                 return -EINVAL;
5860
5861         /*
5862          * Handler for "flow_xstat" devarg.
5863          * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5864          */
5865         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5866                                  bnxt_parse_devarg_flow_xstat, bp);
5867         if (ret)
5868                 goto err;
5869
5870         /*
5871          * Handler for "accum-stats" devarg.
5872          * Invoked as for ex: "-a 0000:00:0d.0,accum-stats=1"
5873          */
5874         rte_kvargs_process(kvlist, BNXT_DEVARG_ACCUM_STATS,
5875                            bnxt_parse_devarg_accum_stats, bp);
5876         /*
5877          * Handler for "max_num_kflows" devarg.
5878          * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5879          */
5880         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5881                                  bnxt_parse_devarg_max_num_kflows, bp);
5882         if (ret)
5883                 goto err;
5884
5885 err:
5886         /*
5887          * Handler for "app-id" devarg.
5888          * Invoked as for ex: "-a 000:00:0d.0,app-id=1"
5889          */
5890         rte_kvargs_process(kvlist, BNXT_DEVARG_APP_ID,
5891                            bnxt_parse_devarg_app_id, bp);
5892
5893         rte_kvargs_free(kvlist);
5894         return ret;
5895 }
5896
5897 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5898 {
5899         int rc = 0;
5900
5901         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5902                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5903                 if (rc)
5904                         PMD_DRV_LOG(ERR,
5905                                     "Failed to alloc switch domain: %d\n", rc);
5906                 else
5907                         PMD_DRV_LOG(INFO,
5908                                     "Switch domain allocated %d\n",
5909                                     bp->switch_domain_id);
5910         }
5911
5912         return rc;
5913 }
5914
5915 /* Allocate and initialize various fields in bnxt struct that
5916  * need to be allocated/destroyed only once in the lifetime of the driver
5917  */
5918 static int bnxt_drv_init(struct rte_eth_dev *eth_dev)
5919 {
5920         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5921         struct bnxt *bp = eth_dev->data->dev_private;
5922         int rc = 0;
5923
5924         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5925
5926         if (bnxt_vf_pciid(pci_dev->id.device_id))
5927                 bp->flags |= BNXT_FLAG_VF;
5928
5929         if (bnxt_p5_device(pci_dev->id.device_id))
5930                 bp->flags |= BNXT_FLAG_CHIP_P5;
5931
5932         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5933             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5934             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5935             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5936                 bp->flags |= BNXT_FLAG_STINGRAY;
5937
5938         if (BNXT_TRUFLOW_EN(bp)) {
5939                 /* extra mbuf field is required to store CFA code from mark */
5940                 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5941                         .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5942                         .size = sizeof(bnxt_cfa_code_dynfield_t),
5943                         .align = __alignof__(bnxt_cfa_code_dynfield_t),
5944                 };
5945                 bnxt_cfa_code_dynfield_offset =
5946                         rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5947                 if (bnxt_cfa_code_dynfield_offset < 0) {
5948                         PMD_DRV_LOG(ERR,
5949                             "Failed to register mbuf field for TruFlow mark\n");
5950                         return -rte_errno;
5951                 }
5952         }
5953
5954         rc = bnxt_map_pci_bars(eth_dev);
5955         if (rc) {
5956                 PMD_DRV_LOG(ERR,
5957                             "Failed to initialize board rc: %x\n", rc);
5958                 return rc;
5959         }
5960
5961         rc = bnxt_alloc_pf_info(bp);
5962         if (rc)
5963                 return rc;
5964
5965         rc = bnxt_alloc_link_info(bp);
5966         if (rc)
5967                 return rc;
5968
5969         rc = bnxt_alloc_parent_info(bp);
5970         if (rc)
5971                 return rc;
5972
5973         rc = bnxt_alloc_hwrm_resources(bp);
5974         if (rc) {
5975                 PMD_DRV_LOG(ERR,
5976                             "Failed to allocate response buffer rc: %x\n", rc);
5977                 return rc;
5978         }
5979         rc = bnxt_alloc_leds_info(bp);
5980         if (rc)
5981                 return rc;
5982
5983         rc = bnxt_alloc_cos_queues(bp);
5984         if (rc)
5985                 return rc;
5986
5987         rc = bnxt_init_locks(bp);
5988         if (rc)
5989                 return rc;
5990
5991         rc = bnxt_alloc_switch_domain(bp);
5992         if (rc)
5993                 return rc;
5994
5995         return rc;
5996 }
5997
5998 static int
5999 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
6000 {
6001         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
6002         static int version_printed;
6003         struct bnxt *bp;
6004         int rc;
6005
6006         if (version_printed++ == 0)
6007                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
6008
6009         eth_dev->dev_ops = &bnxt_dev_ops;
6010         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
6011         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
6012         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
6013         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
6014         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
6015
6016         /*
6017          * For secondary processes, we don't initialise any further
6018          * as primary has already done this work.
6019          */
6020         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6021                 return 0;
6022
6023         rte_eth_copy_pci_info(eth_dev, pci_dev);
6024         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
6025
6026         bp = eth_dev->data->dev_private;
6027
6028         /* Parse dev arguments passed on when starting the DPDK application. */
6029         rc = bnxt_parse_dev_args(bp, pci_dev->device.devargs);
6030         if (rc)
6031                 goto error_free;
6032
6033         rc = bnxt_drv_init(eth_dev);
6034         if (rc)
6035                 goto error_free;
6036
6037         rc = bnxt_init_resources(bp, false);
6038         if (rc)
6039                 goto error_free;
6040
6041         rc = bnxt_alloc_stats_mem(bp);
6042         if (rc)
6043                 goto error_free;
6044
6045         PMD_DRV_LOG(INFO,
6046                     "Found %s device at mem %" PRIX64 ", node addr %pM\n",
6047                     DRV_MODULE_NAME,
6048                     pci_dev->mem_resource[0].phys_addr,
6049                     pci_dev->mem_resource[0].addr);
6050
6051         return 0;
6052
6053 error_free:
6054         bnxt_dev_uninit(eth_dev);
6055         return rc;
6056 }
6057
6058
6059 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
6060 {
6061         if (!ctx)
6062                 return;
6063
6064         if (ctx->va)
6065                 rte_free(ctx->va);
6066
6067         ctx->va = NULL;
6068         ctx->dma = RTE_BAD_IOVA;
6069         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
6070 }
6071
6072 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
6073 {
6074         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
6075                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6076                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
6077                                   bp->flow_stat->max_fc,
6078                                   false);
6079
6080         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
6081                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6082                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
6083                                   bp->flow_stat->max_fc,
6084                                   false);
6085
6086         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6087                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
6088         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6089
6090         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6091                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
6092         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6093
6094         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6095                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
6096         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6097
6098         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6099                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
6100         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6101 }
6102
6103 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
6104 {
6105         bnxt_unregister_fc_ctx_mem(bp);
6106
6107         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
6108         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
6109         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
6110         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
6111 }
6112
6113 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
6114 {
6115         if (BNXT_FLOW_XSTATS_EN(bp))
6116                 bnxt_uninit_fc_ctx_mem(bp);
6117 }
6118
6119 static void
6120 bnxt_free_error_recovery_info(struct bnxt *bp)
6121 {
6122         rte_free(bp->recovery_info);
6123         bp->recovery_info = NULL;
6124         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
6125 }
6126
6127 static int
6128 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
6129 {
6130         int rc;
6131
6132         bnxt_free_int(bp);
6133         bnxt_free_mem(bp, reconfig_dev);
6134
6135         bnxt_hwrm_func_buf_unrgtr(bp);
6136         if (bp->pf != NULL) {
6137                 rte_free(bp->pf->vf_req_buf);
6138                 bp->pf->vf_req_buf = NULL;
6139         }
6140
6141         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
6142         bp->flags &= ~BNXT_FLAG_REGISTERED;
6143         bnxt_free_ctx_mem(bp);
6144         if (!reconfig_dev) {
6145                 bnxt_free_hwrm_resources(bp);
6146                 bnxt_free_error_recovery_info(bp);
6147         }
6148
6149         bnxt_uninit_ctx_mem(bp);
6150
6151         bnxt_free_flow_stats_info(bp);
6152         if (bp->rep_info != NULL)
6153                 bnxt_free_switch_domain(bp);
6154         bnxt_free_rep_info(bp);
6155         rte_free(bp->ptp_cfg);
6156         bp->ptp_cfg = NULL;
6157         return rc;
6158 }
6159
6160 static int
6161 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
6162 {
6163         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6164                 return -EPERM;
6165
6166         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
6167
6168         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
6169                 bnxt_dev_close_op(eth_dev);
6170
6171         return 0;
6172 }
6173
6174 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
6175 {
6176         struct bnxt *bp = eth_dev->data->dev_private;
6177         struct rte_eth_dev *vf_rep_eth_dev;
6178         int ret = 0, i;
6179
6180         if (!bp)
6181                 return -EINVAL;
6182
6183         for (i = 0; i < bp->num_reps; i++) {
6184                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
6185                 if (!vf_rep_eth_dev)
6186                         continue;
6187                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
6188                             vf_rep_eth_dev->data->port_id);
6189                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
6190         }
6191         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
6192                     eth_dev->data->port_id);
6193         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
6194
6195         return ret;
6196 }
6197
6198 static void bnxt_free_rep_info(struct bnxt *bp)
6199 {
6200         rte_free(bp->rep_info);
6201         bp->rep_info = NULL;
6202         rte_free(bp->cfa_code_map);
6203         bp->cfa_code_map = NULL;
6204 }
6205
6206 static int bnxt_init_rep_info(struct bnxt *bp)
6207 {
6208         int i = 0, rc;
6209
6210         if (bp->rep_info)
6211                 return 0;
6212
6213         bp->rep_info = rte_zmalloc("bnxt_rep_info",
6214                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
6215                                    0);
6216         if (!bp->rep_info) {
6217                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
6218                 return -ENOMEM;
6219         }
6220         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
6221                                        sizeof(*bp->cfa_code_map) *
6222                                        BNXT_MAX_CFA_CODE, 0);
6223         if (!bp->cfa_code_map) {
6224                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
6225                 bnxt_free_rep_info(bp);
6226                 return -ENOMEM;
6227         }
6228
6229         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
6230                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
6231
6232         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
6233         if (rc) {
6234                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
6235                 bnxt_free_rep_info(bp);
6236                 return rc;
6237         }
6238
6239         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
6240         if (rc) {
6241                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
6242                 bnxt_free_rep_info(bp);
6243                 return rc;
6244         }
6245
6246         return rc;
6247 }
6248
6249 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
6250                                struct rte_eth_devargs *eth_da,
6251                                struct rte_eth_dev *backing_eth_dev,
6252                                const char *dev_args)
6253 {
6254         struct rte_eth_dev *vf_rep_eth_dev;
6255         char name[RTE_ETH_NAME_MAX_LEN];
6256         struct bnxt *backing_bp;
6257         uint16_t num_rep;
6258         int i, ret = 0;
6259         struct rte_kvargs *kvlist = NULL;
6260
6261         if (eth_da->type == RTE_ETH_REPRESENTOR_NONE)
6262                 return 0;
6263         if (eth_da->type != RTE_ETH_REPRESENTOR_VF) {
6264                 PMD_DRV_LOG(ERR, "unsupported representor type %d\n",
6265                             eth_da->type);
6266                 return -ENOTSUP;
6267         }
6268         num_rep = eth_da->nb_representor_ports;
6269         if (num_rep > BNXT_MAX_VF_REPS) {
6270                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
6271                             num_rep, BNXT_MAX_VF_REPS);
6272                 return -EINVAL;
6273         }
6274
6275         if (num_rep >= RTE_MAX_ETHPORTS) {
6276                 PMD_DRV_LOG(ERR,
6277                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6278                             num_rep, RTE_MAX_ETHPORTS);
6279                 return -EINVAL;
6280         }
6281
6282         backing_bp = backing_eth_dev->data->dev_private;
6283
6284         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6285                 PMD_DRV_LOG(ERR,
6286                             "Not a PF or trusted VF. No Representor support\n");
6287                 /* Returning an error is not an option.
6288                  * Applications are not handling this correctly
6289                  */
6290                 return 0;
6291         }
6292
6293         if (bnxt_init_rep_info(backing_bp))
6294                 return 0;
6295
6296         for (i = 0; i < num_rep; i++) {
6297                 struct bnxt_representor representor = {
6298                         .vf_id = eth_da->representor_ports[i],
6299                         .switch_domain_id = backing_bp->switch_domain_id,
6300                         .parent_dev = backing_eth_dev
6301                 };
6302
6303                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6304                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6305                                     representor.vf_id, BNXT_MAX_VF_REPS);
6306                         continue;
6307                 }
6308
6309                 /* representor port net_bdf_port */
6310                 snprintf(name, sizeof(name), "net_%s_representor_%d",
6311                          pci_dev->device.name, eth_da->representor_ports[i]);
6312
6313                 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
6314                 if (kvlist) {
6315                         /*
6316                          * Handler for "rep_is_pf" devarg.
6317                          * Invoked as for ex: "-a 000:00:0d.0,
6318                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6319                          */
6320                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
6321                                                  bnxt_parse_devarg_rep_is_pf,
6322                                                  (void *)&representor);
6323                         if (ret) {
6324                                 ret = -EINVAL;
6325                                 goto err;
6326                         }
6327                         /*
6328                          * Handler for "rep_based_pf" devarg.
6329                          * Invoked as for ex: "-a 000:00:0d.0,
6330                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6331                          */
6332                         ret = rte_kvargs_process(kvlist,
6333                                                  BNXT_DEVARG_REP_BASED_PF,
6334                                                  bnxt_parse_devarg_rep_based_pf,
6335                                                  (void *)&representor);
6336                         if (ret) {
6337                                 ret = -EINVAL;
6338                                 goto err;
6339                         }
6340                         /*
6341                          * Handler for "rep_based_pf" devarg.
6342                          * Invoked as for ex: "-a 000:00:0d.0,
6343                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6344                          */
6345                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
6346                                                  bnxt_parse_devarg_rep_q_r2f,
6347                                                  (void *)&representor);
6348                         if (ret) {
6349                                 ret = -EINVAL;
6350                                 goto err;
6351                         }
6352                         /*
6353                          * Handler for "rep_based_pf" devarg.
6354                          * Invoked as for ex: "-a 000:00:0d.0,
6355                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6356                          */
6357                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
6358                                                  bnxt_parse_devarg_rep_q_f2r,
6359                                                  (void *)&representor);
6360                         if (ret) {
6361                                 ret = -EINVAL;
6362                                 goto err;
6363                         }
6364                         /*
6365                          * Handler for "rep_based_pf" devarg.
6366                          * Invoked as for ex: "-a 000:00:0d.0,
6367                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6368                          */
6369                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
6370                                                  bnxt_parse_devarg_rep_fc_r2f,
6371                                                  (void *)&representor);
6372                         if (ret) {
6373                                 ret = -EINVAL;
6374                                 goto err;
6375                         }
6376                         /*
6377                          * Handler for "rep_based_pf" devarg.
6378                          * Invoked as for ex: "-a 000:00:0d.0,
6379                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6380                          */
6381                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
6382                                                  bnxt_parse_devarg_rep_fc_f2r,
6383                                                  (void *)&representor);
6384                         if (ret) {
6385                                 ret = -EINVAL;
6386                                 goto err;
6387                         }
6388                 }
6389
6390                 ret = rte_eth_dev_create(&pci_dev->device, name,
6391                                          sizeof(struct bnxt_representor),
6392                                          NULL, NULL,
6393                                          bnxt_representor_init,
6394                                          &representor);
6395                 if (ret) {
6396                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6397                                     "representor %s.", name);
6398                         goto err;
6399                 }
6400
6401                 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6402                 if (!vf_rep_eth_dev) {
6403                         PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6404                                     " for VF-Rep: %s.", name);
6405                         ret = -ENODEV;
6406                         goto err;
6407                 }
6408
6409                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6410                             backing_eth_dev->data->port_id);
6411                 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6412                                                          vf_rep_eth_dev;
6413                 backing_bp->num_reps++;
6414
6415         }
6416
6417         rte_kvargs_free(kvlist);
6418         return 0;
6419
6420 err:
6421         /* If num_rep > 1, then rollback already created
6422          * ports, since we'll be failing the probe anyway
6423          */
6424         if (num_rep > 1)
6425                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6426         rte_errno = -ret;
6427         rte_kvargs_free(kvlist);
6428
6429         return ret;
6430 }
6431
6432 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6433                           struct rte_pci_device *pci_dev)
6434 {
6435         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6436         struct rte_eth_dev *backing_eth_dev;
6437         uint16_t num_rep;
6438         int ret = 0;
6439
6440         if (pci_dev->device.devargs) {
6441                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6442                                             &eth_da);
6443                 if (ret)
6444                         return ret;
6445         }
6446
6447         num_rep = eth_da.nb_representor_ports;
6448         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6449                     num_rep);
6450
6451         /* We could come here after first level of probe is already invoked
6452          * as part of an application bringup(OVS-DPDK vswitchd), so first check
6453          * for already allocated eth_dev for the backing device (PF/Trusted VF)
6454          */
6455         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6456         if (backing_eth_dev == NULL) {
6457                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6458                                          sizeof(struct bnxt),
6459                                          eth_dev_pci_specific_init, pci_dev,
6460                                          bnxt_dev_init, NULL);
6461
6462                 if (ret || !num_rep)
6463                         return ret;
6464
6465                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6466         }
6467         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6468                     backing_eth_dev->data->port_id);
6469
6470         if (!num_rep)
6471                 return ret;
6472
6473         /* probe representor ports now */
6474         ret = bnxt_rep_port_probe(pci_dev, &eth_da, backing_eth_dev,
6475                                   pci_dev->device.devargs->args);
6476
6477         return ret;
6478 }
6479
6480 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6481 {
6482         struct rte_eth_dev *eth_dev;
6483
6484         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6485         if (!eth_dev)
6486                 return 0; /* Invoked typically only by OVS-DPDK, by the
6487                            * time it comes here the eth_dev is already
6488                            * deleted by rte_eth_dev_close(), so returning
6489                            * +ve value will at least help in proper cleanup
6490                            */
6491
6492         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6493         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6494                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6495                         return rte_eth_dev_destroy(eth_dev,
6496                                                    bnxt_representor_uninit);
6497                 else
6498                         return rte_eth_dev_destroy(eth_dev,
6499                                                    bnxt_dev_uninit);
6500         } else {
6501                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6502         }
6503 }
6504
6505 static struct rte_pci_driver bnxt_rte_pmd = {
6506         .id_table = bnxt_pci_id_map,
6507         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6508                         RTE_PCI_DRV_INTR_RMV |
6509                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6510                                                   * and OVS-DPDK
6511                                                   */
6512         .probe = bnxt_pci_probe,
6513         .remove = bnxt_pci_remove,
6514 };
6515
6516 static bool
6517 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6518 {
6519         if (strcmp(dev->device->driver->name, drv->driver.name))
6520                 return false;
6521
6522         return true;
6523 }
6524
6525 bool is_bnxt_supported(struct rte_eth_dev *dev)
6526 {
6527         return is_device_supported(dev, &bnxt_rte_pmd);
6528 }
6529
6530 RTE_LOG_REGISTER_SUFFIX(bnxt_logtype_driver, driver, NOTICE);
6531 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6532 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6533 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");