1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
15 #include <rte_kvargs.h>
18 #include "bnxt_filter.h"
19 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_stats.h"
27 #include "bnxt_vnic.h"
28 #include "hsi_struct_def_dpdk.h"
29 #include "bnxt_nvm_defs.h"
31 #define DRV_MODULE_NAME "bnxt"
32 static const char bnxt_version[] =
33 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
34 int bnxt_logtype_driver;
37 * The set of PCI devices this driver supports
39 static const struct rte_pci_id bnxt_pci_id_map[] = {
40 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
41 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
42 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
43 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
45 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
47 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
93 { .vendor_id = 0, /* sentinel */ },
96 #define BNXT_ETH_RSS_SUPPORT ( \
98 ETH_RSS_NONFRAG_IPV4_TCP | \
99 ETH_RSS_NONFRAG_IPV4_UDP | \
101 ETH_RSS_NONFRAG_IPV6_TCP | \
102 ETH_RSS_NONFRAG_IPV6_UDP)
104 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
105 DEV_TX_OFFLOAD_IPV4_CKSUM | \
106 DEV_TX_OFFLOAD_TCP_CKSUM | \
107 DEV_TX_OFFLOAD_UDP_CKSUM | \
108 DEV_TX_OFFLOAD_TCP_TSO | \
109 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
110 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
111 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
112 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
113 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
114 DEV_TX_OFFLOAD_QINQ_INSERT | \
115 DEV_TX_OFFLOAD_MULTI_SEGS)
117 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
118 DEV_RX_OFFLOAD_VLAN_STRIP | \
119 DEV_RX_OFFLOAD_IPV4_CKSUM | \
120 DEV_RX_OFFLOAD_UDP_CKSUM | \
121 DEV_RX_OFFLOAD_TCP_CKSUM | \
122 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
123 DEV_RX_OFFLOAD_JUMBO_FRAME | \
124 DEV_RX_OFFLOAD_KEEP_CRC | \
125 DEV_RX_OFFLOAD_VLAN_EXTEND | \
126 DEV_RX_OFFLOAD_TCP_LRO | \
127 DEV_RX_OFFLOAD_SCATTER | \
128 DEV_RX_OFFLOAD_RSS_HASH)
130 #define BNXT_DEVARG_TRUFLOW "host-based-truflow"
131 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat"
132 static const char *const bnxt_dev_args[] = {
134 BNXT_DEVARG_FLOW_XSTAT,
139 * truflow == false to disable the feature
140 * truflow == true to enable the feature
142 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1)
145 * flow_xstat == false to disable the feature
146 * flow_xstat == true to enable the feature
148 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1)
150 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
151 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
152 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
153 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
154 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
155 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
156 static int bnxt_restore_vlan_filters(struct bnxt *bp);
157 static void bnxt_dev_recover(void *arg);
159 int is_bnxt_in_error(struct bnxt *bp)
161 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
163 if (bp->flags & BNXT_FLAG_FW_RESET)
169 /***********************/
172 * High level utility functions
175 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
177 if (!BNXT_CHIP_THOR(bp))
180 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
181 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
182 BNXT_RSS_ENTRIES_PER_CTX_THOR;
185 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
187 if (!BNXT_CHIP_THOR(bp))
188 return HW_HASH_INDEX_SIZE;
190 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
193 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
195 bnxt_free_filter_mem(bp);
196 bnxt_free_vnic_attributes(bp);
197 bnxt_free_vnic_mem(bp);
199 /* tx/rx rings are configured as part of *_queue_setup callbacks.
200 * If the number of rings change across fw update,
201 * we don't have much choice except to warn the user.
205 bnxt_free_tx_rings(bp);
206 bnxt_free_rx_rings(bp);
208 bnxt_free_async_cp_ring(bp);
209 bnxt_free_rxtx_nq_ring(bp);
211 rte_free(bp->grp_info);
215 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
219 rc = bnxt_alloc_ring_grps(bp);
223 rc = bnxt_alloc_async_ring_struct(bp);
227 rc = bnxt_alloc_vnic_mem(bp);
231 rc = bnxt_alloc_vnic_attributes(bp);
235 rc = bnxt_alloc_filter_mem(bp);
239 rc = bnxt_alloc_async_cp_ring(bp);
243 rc = bnxt_alloc_rxtx_nq_ring(bp);
250 bnxt_free_mem(bp, reconfig);
254 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
256 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
257 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
258 uint64_t rx_offloads = dev_conf->rxmode.offloads;
259 struct bnxt_rx_queue *rxq;
263 rc = bnxt_vnic_grp_alloc(bp, vnic);
267 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
268 vnic_id, vnic, vnic->fw_grp_ids);
270 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
274 /* Alloc RSS context only if RSS mode is enabled */
275 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
276 int j, nr_ctxs = bnxt_rss_ctxts(bp);
279 for (j = 0; j < nr_ctxs; j++) {
280 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
286 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
290 vnic->num_lb_ctxts = nr_ctxs;
294 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
295 * setting is not available at this time, it will not be
296 * configured correctly in the CFA.
298 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
299 vnic->vlan_strip = true;
301 vnic->vlan_strip = false;
303 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
307 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
311 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
312 rxq = bp->eth_dev->data->rx_queues[j];
315 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
316 j, rxq->vnic, rxq->vnic->fw_grp_ids);
318 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
319 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
321 vnic->rx_queue_cnt++;
324 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
326 rc = bnxt_vnic_rss_configure(bp, vnic);
330 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
332 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
333 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
335 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
339 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
344 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
348 rc = bnxt_hwrm_ctx_rgtr(bp, bp->rx_fc_in_tbl.dma,
349 &bp->rx_fc_in_tbl.ctx_id);
354 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
355 " rx_fc_in_tbl.ctx_id = %d\n",
357 (void *)((uintptr_t)bp->rx_fc_in_tbl.dma),
358 bp->rx_fc_in_tbl.ctx_id);
360 rc = bnxt_hwrm_ctx_rgtr(bp, bp->rx_fc_out_tbl.dma,
361 &bp->rx_fc_out_tbl.ctx_id);
366 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
367 " rx_fc_out_tbl.ctx_id = %d\n",
368 bp->rx_fc_out_tbl.va,
369 (void *)((uintptr_t)bp->rx_fc_out_tbl.dma),
370 bp->rx_fc_out_tbl.ctx_id);
372 rc = bnxt_hwrm_ctx_rgtr(bp, bp->tx_fc_in_tbl.dma,
373 &bp->tx_fc_in_tbl.ctx_id);
378 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
379 " tx_fc_in_tbl.ctx_id = %d\n",
381 (void *)((uintptr_t)bp->tx_fc_in_tbl.dma),
382 bp->tx_fc_in_tbl.ctx_id);
384 rc = bnxt_hwrm_ctx_rgtr(bp, bp->tx_fc_out_tbl.dma,
385 &bp->tx_fc_out_tbl.ctx_id);
390 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
391 " tx_fc_out_tbl.ctx_id = %d\n",
392 bp->tx_fc_out_tbl.va,
393 (void *)((uintptr_t)bp->tx_fc_out_tbl.dma),
394 bp->tx_fc_out_tbl.ctx_id);
396 memset(bp->rx_fc_out_tbl.va, 0, bp->rx_fc_out_tbl.size);
397 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
398 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
399 bp->rx_fc_out_tbl.ctx_id,
405 memset(bp->tx_fc_out_tbl.va, 0, bp->tx_fc_out_tbl.size);
406 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
407 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
408 bp->tx_fc_out_tbl.ctx_id,
415 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
416 struct bnxt_ctx_mem_buf_info *ctx)
421 ctx->va = rte_zmalloc(type, size, 0);
424 rte_mem_lock_page(ctx->va);
426 ctx->dma = rte_mem_virt2iova(ctx->va);
427 if (ctx->dma == RTE_BAD_IOVA)
433 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
435 struct rte_pci_device *pdev = bp->pdev;
436 char type[RTE_MEMZONE_NAMESIZE];
442 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
443 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
444 /* 4 bytes for each counter-id */
445 rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 4, &bp->rx_fc_in_tbl);
449 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
450 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
451 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
452 rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 16, &bp->rx_fc_out_tbl);
456 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
457 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
458 /* 4 bytes for each counter-id */
459 rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 4, &bp->tx_fc_in_tbl);
463 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
464 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
465 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
466 rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 16, &bp->tx_fc_out_tbl);
470 rc = bnxt_register_fc_ctx_mem(bp);
475 static int bnxt_init_ctx_mem(struct bnxt *bp)
479 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
480 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)))
483 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->max_fc);
487 rc = bnxt_init_fc_ctx_mem(bp);
492 static int bnxt_init_chip(struct bnxt *bp)
494 struct rte_eth_link new;
495 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
496 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
497 uint32_t intr_vector = 0;
498 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
499 uint32_t vec = BNXT_MISC_VEC_ID;
503 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
504 bp->eth_dev->data->dev_conf.rxmode.offloads |=
505 DEV_RX_OFFLOAD_JUMBO_FRAME;
506 bp->flags |= BNXT_FLAG_JUMBO;
508 bp->eth_dev->data->dev_conf.rxmode.offloads &=
509 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
510 bp->flags &= ~BNXT_FLAG_JUMBO;
513 /* THOR does not support ring groups.
514 * But we will use the array to save RSS context IDs.
516 if (BNXT_CHIP_THOR(bp))
517 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
519 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
521 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
525 rc = bnxt_alloc_hwrm_rings(bp);
527 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
531 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
533 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
537 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
540 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
541 if (bp->rx_cos_queue[i].id != 0xff) {
542 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
546 "Num pools more than FW profile\n");
550 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
556 rc = bnxt_mq_rx_configure(bp);
558 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
562 /* VNIC configuration */
563 for (i = 0; i < bp->nr_vnics; i++) {
564 rc = bnxt_setup_one_vnic(bp, i);
569 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
572 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
576 /* check and configure queue intr-vector mapping */
577 if ((rte_intr_cap_multiple(intr_handle) ||
578 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
579 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
580 intr_vector = bp->eth_dev->data->nb_rx_queues;
581 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
582 if (intr_vector > bp->rx_cp_nr_rings) {
583 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
587 rc = rte_intr_efd_enable(intr_handle, intr_vector);
592 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
593 intr_handle->intr_vec =
594 rte_zmalloc("intr_vec",
595 bp->eth_dev->data->nb_rx_queues *
597 if (intr_handle->intr_vec == NULL) {
598 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
599 " intr_vec", bp->eth_dev->data->nb_rx_queues);
603 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
604 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
605 intr_handle->intr_vec, intr_handle->nb_efd,
606 intr_handle->max_intr);
607 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
609 intr_handle->intr_vec[queue_id] =
610 vec + BNXT_RX_VEC_START;
611 if (vec < base + intr_handle->nb_efd - 1)
616 /* enable uio/vfio intr/eventfd mapping */
617 rc = rte_intr_enable(intr_handle);
618 #ifndef RTE_EXEC_ENV_FREEBSD
619 /* In FreeBSD OS, nic_uio driver does not support interrupts */
624 rc = bnxt_get_hwrm_link_config(bp, &new);
626 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
630 if (!bp->link_info.link_up) {
631 rc = bnxt_set_hwrm_link_config(bp, true);
634 "HWRM link config failure rc: %x\n", rc);
638 bnxt_print_link_info(bp->eth_dev);
640 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
642 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
647 rte_free(intr_handle->intr_vec);
649 rte_intr_efd_disable(intr_handle);
651 /* Some of the error status returned by FW may not be from errno.h */
658 static int bnxt_shutdown_nic(struct bnxt *bp)
660 bnxt_free_all_hwrm_resources(bp);
661 bnxt_free_all_filters(bp);
662 bnxt_free_all_vnics(bp);
667 * Device configuration and status function
670 static uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
672 uint32_t link_speed = bp->link_info.support_speeds;
673 uint32_t speed_capa = 0;
675 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
676 speed_capa |= ETH_LINK_SPEED_100M;
677 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
678 speed_capa |= ETH_LINK_SPEED_100M_HD;
679 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
680 speed_capa |= ETH_LINK_SPEED_1G;
681 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
682 speed_capa |= ETH_LINK_SPEED_2_5G;
683 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
684 speed_capa |= ETH_LINK_SPEED_10G;
685 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
686 speed_capa |= ETH_LINK_SPEED_20G;
687 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
688 speed_capa |= ETH_LINK_SPEED_25G;
689 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
690 speed_capa |= ETH_LINK_SPEED_40G;
691 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
692 speed_capa |= ETH_LINK_SPEED_50G;
693 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
694 speed_capa |= ETH_LINK_SPEED_100G;
696 if (bp->link_info.auto_mode == HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
697 speed_capa |= ETH_LINK_SPEED_FIXED;
699 speed_capa |= ETH_LINK_SPEED_AUTONEG;
704 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
705 struct rte_eth_dev_info *dev_info)
707 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
708 struct bnxt *bp = eth_dev->data->dev_private;
709 uint16_t max_vnics, i, j, vpool, vrxq;
710 unsigned int max_rx_rings;
713 rc = is_bnxt_in_error(bp);
718 dev_info->max_mac_addrs = bp->max_l2_ctx;
719 dev_info->max_hash_mac_addrs = 0;
721 /* PF/VF specifics */
723 dev_info->max_vfs = pdev->max_vfs;
725 max_rx_rings = BNXT_MAX_RINGS(bp);
726 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
727 dev_info->max_rx_queues = max_rx_rings;
728 dev_info->max_tx_queues = max_rx_rings;
729 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
730 dev_info->hash_key_size = 40;
731 max_vnics = bp->max_vnics;
734 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
735 dev_info->max_mtu = BNXT_MAX_MTU;
737 /* Fast path specifics */
738 dev_info->min_rx_bufsize = 1;
739 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
741 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
742 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
743 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
744 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
745 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
747 dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
750 dev_info->default_rxconf = (struct rte_eth_rxconf) {
756 .rx_free_thresh = 32,
757 /* If no descriptors available, pkts are dropped by default */
761 dev_info->default_txconf = (struct rte_eth_txconf) {
767 .tx_free_thresh = 32,
770 eth_dev->data->dev_conf.intr_conf.lsc = 1;
772 eth_dev->data->dev_conf.intr_conf.rxq = 1;
773 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
774 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
775 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
776 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
781 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
782 * need further investigation.
786 vpool = 64; /* ETH_64_POOLS */
787 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
788 for (i = 0; i < 4; vpool >>= 1, i++) {
789 if (max_vnics > vpool) {
790 for (j = 0; j < 5; vrxq >>= 1, j++) {
791 if (dev_info->max_rx_queues > vrxq) {
797 /* Not enough resources to support VMDq */
801 /* Not enough resources to support VMDq */
805 dev_info->max_vmdq_pools = vpool;
806 dev_info->vmdq_queue_num = vrxq;
808 dev_info->vmdq_pool_base = 0;
809 dev_info->vmdq_queue_base = 0;
814 /* Configure the device based on the configuration provided */
815 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
817 struct bnxt *bp = eth_dev->data->dev_private;
818 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
821 bp->rx_queues = (void *)eth_dev->data->rx_queues;
822 bp->tx_queues = (void *)eth_dev->data->tx_queues;
823 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
824 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
826 rc = is_bnxt_in_error(bp);
830 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
831 rc = bnxt_hwrm_check_vf_rings(bp);
833 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
837 /* If a resource has already been allocated - in this case
838 * it is the async completion ring, free it. Reallocate it after
839 * resource reservation. This will ensure the resource counts
840 * are calculated correctly.
843 pthread_mutex_lock(&bp->def_cp_lock);
845 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
846 bnxt_disable_int(bp);
847 bnxt_free_cp_ring(bp, bp->async_cp_ring);
850 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
852 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
853 pthread_mutex_unlock(&bp->def_cp_lock);
857 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
858 rc = bnxt_alloc_async_cp_ring(bp);
860 pthread_mutex_unlock(&bp->def_cp_lock);
866 pthread_mutex_unlock(&bp->def_cp_lock);
868 /* legacy driver needs to get updated values */
869 rc = bnxt_hwrm_func_qcaps(bp);
871 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
876 /* Inherit new configurations */
877 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
878 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
879 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
880 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
881 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
885 if (BNXT_HAS_RING_GRPS(bp) &&
886 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
889 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
890 bp->max_vnics < eth_dev->data->nb_rx_queues)
893 bp->rx_cp_nr_rings = bp->rx_nr_rings;
894 bp->tx_cp_nr_rings = bp->tx_nr_rings;
896 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
897 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
898 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
900 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
902 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
903 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
905 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
911 "Insufficient resources to support requested config\n");
913 "Num Queues Requested: Tx %d, Rx %d\n",
914 eth_dev->data->nb_tx_queues,
915 eth_dev->data->nb_rx_queues);
917 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
918 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
919 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
923 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
925 struct rte_eth_link *link = ð_dev->data->dev_link;
927 if (link->link_status)
928 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
929 eth_dev->data->port_id,
930 (uint32_t)link->link_speed,
931 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
932 ("full-duplex") : ("half-duplex\n"));
934 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
935 eth_dev->data->port_id);
939 * Determine whether the current configuration requires support for scattered
940 * receive; return 1 if scattered receive is required and 0 if not.
942 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
947 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
950 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
951 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
953 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
954 RTE_PKTMBUF_HEADROOM);
955 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
961 static eth_rx_burst_t
962 bnxt_receive_function(struct rte_eth_dev *eth_dev)
964 struct bnxt *bp = eth_dev->data->dev_private;
967 #ifndef RTE_LIBRTE_IEEE1588
969 * Vector mode receive can be enabled only if scatter rx is not
970 * in use and rx offloads are limited to VLAN stripping and
973 if (!eth_dev->data->scattered_rx &&
974 !(eth_dev->data->dev_conf.rxmode.offloads &
975 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
976 DEV_RX_OFFLOAD_KEEP_CRC |
977 DEV_RX_OFFLOAD_JUMBO_FRAME |
978 DEV_RX_OFFLOAD_IPV4_CKSUM |
979 DEV_RX_OFFLOAD_UDP_CKSUM |
980 DEV_RX_OFFLOAD_TCP_CKSUM |
981 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
982 DEV_RX_OFFLOAD_RSS_HASH |
983 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
985 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
986 eth_dev->data->port_id);
987 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
988 return bnxt_recv_pkts_vec;
990 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
991 eth_dev->data->port_id);
993 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
994 eth_dev->data->port_id,
995 eth_dev->data->scattered_rx,
996 eth_dev->data->dev_conf.rxmode.offloads);
999 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1000 return bnxt_recv_pkts;
1003 static eth_tx_burst_t
1004 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1007 #ifndef RTE_LIBRTE_IEEE1588
1009 * Vector mode transmit can be enabled only if not using scatter rx
1012 if (!eth_dev->data->scattered_rx &&
1013 !eth_dev->data->dev_conf.txmode.offloads) {
1014 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1015 eth_dev->data->port_id);
1016 return bnxt_xmit_pkts_vec;
1018 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1019 eth_dev->data->port_id);
1021 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1022 eth_dev->data->port_id,
1023 eth_dev->data->scattered_rx,
1024 eth_dev->data->dev_conf.txmode.offloads);
1027 return bnxt_xmit_pkts;
1030 static int bnxt_handle_if_change_status(struct bnxt *bp)
1034 /* Since fw has undergone a reset and lost all contexts,
1035 * set fatal flag to not issue hwrm during cleanup
1037 bp->flags |= BNXT_FLAG_FATAL_ERROR;
1038 bnxt_uninit_resources(bp, true);
1040 /* clear fatal flag so that re-init happens */
1041 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1042 rc = bnxt_init_resources(bp, true);
1044 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1049 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1051 struct bnxt *bp = eth_dev->data->dev_private;
1052 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1054 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1056 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1057 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1061 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1063 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1064 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1068 rc = bnxt_hwrm_if_change(bp, true);
1069 if (rc == 0 || rc != -EAGAIN)
1072 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1073 } while (retry_cnt--);
1078 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1079 rc = bnxt_handle_if_change_status(bp);
1084 bnxt_enable_int(bp);
1086 rc = bnxt_init_chip(bp);
1090 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1091 eth_dev->data->dev_started = 1;
1093 bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1095 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1096 vlan_mask |= ETH_VLAN_FILTER_MASK;
1097 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1098 vlan_mask |= ETH_VLAN_STRIP_MASK;
1099 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1103 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1104 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1106 pthread_mutex_lock(&bp->def_cp_lock);
1107 bnxt_schedule_fw_health_check(bp);
1108 pthread_mutex_unlock(&bp->def_cp_lock);
1116 bnxt_shutdown_nic(bp);
1117 bnxt_free_tx_mbufs(bp);
1118 bnxt_free_rx_mbufs(bp);
1119 bnxt_hwrm_if_change(bp, false);
1120 eth_dev->data->dev_started = 0;
1124 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1126 struct bnxt *bp = eth_dev->data->dev_private;
1129 if (!bp->link_info.link_up)
1130 rc = bnxt_set_hwrm_link_config(bp, true);
1132 eth_dev->data->dev_link.link_status = 1;
1134 bnxt_print_link_info(eth_dev);
1138 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1140 struct bnxt *bp = eth_dev->data->dev_private;
1142 eth_dev->data->dev_link.link_status = 0;
1143 bnxt_set_hwrm_link_config(bp, false);
1144 bp->link_info.link_up = 0;
1149 /* Unload the driver, release resources */
1150 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1152 struct bnxt *bp = eth_dev->data->dev_private;
1153 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1154 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1157 bnxt_ulp_deinit(bp);
1159 eth_dev->data->dev_started = 0;
1160 /* Prevent crashes when queues are still in use */
1161 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1162 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1164 bnxt_disable_int(bp);
1166 /* disable uio/vfio intr/eventfd mapping */
1167 rte_intr_disable(intr_handle);
1169 bnxt_cancel_fw_health_check(bp);
1171 bnxt_dev_set_link_down_op(eth_dev);
1173 /* Wait for link to be reset and the async notification to process.
1174 * During reset recovery, there is no need to wait and
1175 * VF/NPAR functions do not have privilege to change PHY config.
1177 if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1178 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1180 /* Clean queue intr-vector mapping */
1181 rte_intr_efd_disable(intr_handle);
1182 if (intr_handle->intr_vec != NULL) {
1183 rte_free(intr_handle->intr_vec);
1184 intr_handle->intr_vec = NULL;
1187 bnxt_hwrm_port_clr_stats(bp);
1188 bnxt_free_tx_mbufs(bp);
1189 bnxt_free_rx_mbufs(bp);
1190 /* Process any remaining notifications in default completion queue */
1191 bnxt_int_handler(eth_dev);
1192 bnxt_shutdown_nic(bp);
1193 bnxt_hwrm_if_change(bp, false);
1195 rte_free(bp->mark_table);
1196 bp->mark_table = NULL;
1198 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1199 bp->rx_cosq_cnt = 0;
1202 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1204 struct bnxt *bp = eth_dev->data->dev_private;
1206 /* cancel the recovery handler before remove dev */
1207 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1208 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1209 bnxt_cancel_fc_thread(bp);
1211 if (eth_dev->data->dev_started)
1212 bnxt_dev_stop_op(eth_dev);
1214 bnxt_uninit_resources(bp, false);
1216 eth_dev->dev_ops = NULL;
1217 eth_dev->rx_pkt_burst = NULL;
1218 eth_dev->tx_pkt_burst = NULL;
1220 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1221 bp->tx_mem_zone = NULL;
1222 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1223 bp->rx_mem_zone = NULL;
1225 rte_free(bp->pf.vf_info);
1226 bp->pf.vf_info = NULL;
1228 rte_free(bp->grp_info);
1229 bp->grp_info = NULL;
1232 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1235 struct bnxt *bp = eth_dev->data->dev_private;
1236 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1237 struct bnxt_vnic_info *vnic;
1238 struct bnxt_filter_info *filter, *temp_filter;
1241 if (is_bnxt_in_error(bp))
1245 * Loop through all VNICs from the specified filter flow pools to
1246 * remove the corresponding MAC addr filter
1248 for (i = 0; i < bp->nr_vnics; i++) {
1249 if (!(pool_mask & (1ULL << i)))
1252 vnic = &bp->vnic_info[i];
1253 filter = STAILQ_FIRST(&vnic->filter);
1255 temp_filter = STAILQ_NEXT(filter, next);
1256 if (filter->mac_index == index) {
1257 STAILQ_REMOVE(&vnic->filter, filter,
1258 bnxt_filter_info, next);
1259 bnxt_hwrm_clear_l2_filter(bp, filter);
1260 bnxt_free_filter(bp, filter);
1262 filter = temp_filter;
1267 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1268 struct rte_ether_addr *mac_addr, uint32_t index,
1271 struct bnxt_filter_info *filter;
1274 /* Attach requested MAC address to the new l2_filter */
1275 STAILQ_FOREACH(filter, &vnic->filter, next) {
1276 if (filter->mac_index == index) {
1278 "MAC addr already existed for pool %d\n",
1284 filter = bnxt_alloc_filter(bp);
1286 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1290 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1291 * if the MAC that's been programmed now is a different one, then,
1292 * copy that addr to filter->l2_addr
1295 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1296 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1298 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1300 filter->mac_index = index;
1301 if (filter->mac_index == 0)
1302 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1304 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1306 bnxt_free_filter(bp, filter);
1312 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1313 struct rte_ether_addr *mac_addr,
1314 uint32_t index, uint32_t pool)
1316 struct bnxt *bp = eth_dev->data->dev_private;
1317 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1320 rc = is_bnxt_in_error(bp);
1324 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1325 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1330 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1334 /* Filter settings will get applied when port is started */
1335 if (!eth_dev->data->dev_started)
1338 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1343 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1344 bool exp_link_status)
1347 struct bnxt *bp = eth_dev->data->dev_private;
1348 struct rte_eth_link new;
1349 int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1350 BNXT_LINK_DOWN_WAIT_CNT;
1352 rc = is_bnxt_in_error(bp);
1356 memset(&new, 0, sizeof(new));
1358 /* Retrieve link info from hardware */
1359 rc = bnxt_get_hwrm_link_config(bp, &new);
1361 new.link_speed = ETH_LINK_SPEED_100M;
1362 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1364 "Failed to retrieve link rc = 0x%x!\n", rc);
1368 if (!wait_to_complete || new.link_status == exp_link_status)
1371 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1375 /* Timed out or success */
1376 if (new.link_status != eth_dev->data->dev_link.link_status ||
1377 new.link_speed != eth_dev->data->dev_link.link_speed) {
1378 rte_eth_linkstatus_set(eth_dev, &new);
1380 _rte_eth_dev_callback_process(eth_dev,
1381 RTE_ETH_EVENT_INTR_LSC,
1384 bnxt_print_link_info(eth_dev);
1390 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1391 int wait_to_complete)
1393 return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1396 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1398 struct bnxt *bp = eth_dev->data->dev_private;
1399 struct bnxt_vnic_info *vnic;
1403 rc = is_bnxt_in_error(bp);
1407 /* Filter settings will get applied when port is started */
1408 if (!eth_dev->data->dev_started)
1411 if (bp->vnic_info == NULL)
1414 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1416 old_flags = vnic->flags;
1417 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1418 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1420 vnic->flags = old_flags;
1425 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1427 struct bnxt *bp = eth_dev->data->dev_private;
1428 struct bnxt_vnic_info *vnic;
1432 rc = is_bnxt_in_error(bp);
1436 /* Filter settings will get applied when port is started */
1437 if (!eth_dev->data->dev_started)
1440 if (bp->vnic_info == NULL)
1443 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1445 old_flags = vnic->flags;
1446 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1447 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1449 vnic->flags = old_flags;
1454 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1456 struct bnxt *bp = eth_dev->data->dev_private;
1457 struct bnxt_vnic_info *vnic;
1461 rc = is_bnxt_in_error(bp);
1465 /* Filter settings will get applied when port is started */
1466 if (!eth_dev->data->dev_started)
1469 if (bp->vnic_info == NULL)
1472 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1474 old_flags = vnic->flags;
1475 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1476 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1478 vnic->flags = old_flags;
1483 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1485 struct bnxt *bp = eth_dev->data->dev_private;
1486 struct bnxt_vnic_info *vnic;
1490 rc = is_bnxt_in_error(bp);
1494 /* Filter settings will get applied when port is started */
1495 if (!eth_dev->data->dev_started)
1498 if (bp->vnic_info == NULL)
1501 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1503 old_flags = vnic->flags;
1504 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1505 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1507 vnic->flags = old_flags;
1512 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1513 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1515 if (qid >= bp->rx_nr_rings)
1518 return bp->eth_dev->data->rx_queues[qid];
1521 /* Return rxq corresponding to a given rss table ring/group ID. */
1522 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1524 struct bnxt_rx_queue *rxq;
1527 if (!BNXT_HAS_RING_GRPS(bp)) {
1528 for (i = 0; i < bp->rx_nr_rings; i++) {
1529 rxq = bp->eth_dev->data->rx_queues[i];
1530 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1534 for (i = 0; i < bp->rx_nr_rings; i++) {
1535 if (bp->grp_info[i].fw_grp_id == fwr)
1540 return INVALID_HW_RING_ID;
1543 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1544 struct rte_eth_rss_reta_entry64 *reta_conf,
1547 struct bnxt *bp = eth_dev->data->dev_private;
1548 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1549 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1550 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1554 rc = is_bnxt_in_error(bp);
1558 if (!vnic->rss_table)
1561 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1564 if (reta_size != tbl_size) {
1565 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1566 "(%d) must equal the size supported by the hardware "
1567 "(%d)\n", reta_size, tbl_size);
1571 for (i = 0; i < reta_size; i++) {
1572 struct bnxt_rx_queue *rxq;
1574 idx = i / RTE_RETA_GROUP_SIZE;
1575 sft = i % RTE_RETA_GROUP_SIZE;
1577 if (!(reta_conf[idx].mask & (1ULL << sft)))
1580 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1582 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1586 if (BNXT_CHIP_THOR(bp)) {
1587 vnic->rss_table[i * 2] =
1588 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1589 vnic->rss_table[i * 2 + 1] =
1590 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1592 vnic->rss_table[i] =
1593 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1597 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1601 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1602 struct rte_eth_rss_reta_entry64 *reta_conf,
1605 struct bnxt *bp = eth_dev->data->dev_private;
1606 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1607 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1608 uint16_t idx, sft, i;
1611 rc = is_bnxt_in_error(bp);
1615 /* Retrieve from the default VNIC */
1618 if (!vnic->rss_table)
1621 if (reta_size != tbl_size) {
1622 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1623 "(%d) must equal the size supported by the hardware "
1624 "(%d)\n", reta_size, tbl_size);
1628 for (idx = 0, i = 0; i < reta_size; i++) {
1629 idx = i / RTE_RETA_GROUP_SIZE;
1630 sft = i % RTE_RETA_GROUP_SIZE;
1632 if (reta_conf[idx].mask & (1ULL << sft)) {
1635 if (BNXT_CHIP_THOR(bp))
1636 qid = bnxt_rss_to_qid(bp,
1637 vnic->rss_table[i * 2]);
1639 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1641 if (qid == INVALID_HW_RING_ID) {
1642 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1645 reta_conf[idx].reta[sft] = qid;
1652 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1653 struct rte_eth_rss_conf *rss_conf)
1655 struct bnxt *bp = eth_dev->data->dev_private;
1656 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1657 struct bnxt_vnic_info *vnic;
1660 rc = is_bnxt_in_error(bp);
1665 * If RSS enablement were different than dev_configure,
1666 * then return -EINVAL
1668 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1669 if (!rss_conf->rss_hf)
1670 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1672 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1676 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1677 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1679 /* Update the default RSS VNIC(s) */
1680 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1681 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1684 * If hashkey is not specified, use the previously configured
1687 if (!rss_conf->rss_key)
1690 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1692 "Invalid hashkey length, should be 16 bytes\n");
1695 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1698 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1702 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1703 struct rte_eth_rss_conf *rss_conf)
1705 struct bnxt *bp = eth_dev->data->dev_private;
1706 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1708 uint32_t hash_types;
1710 rc = is_bnxt_in_error(bp);
1714 /* RSS configuration is the same for all VNICs */
1715 if (vnic && vnic->rss_hash_key) {
1716 if (rss_conf->rss_key) {
1717 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1718 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1719 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1722 hash_types = vnic->hash_type;
1723 rss_conf->rss_hf = 0;
1724 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1725 rss_conf->rss_hf |= ETH_RSS_IPV4;
1726 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1728 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1729 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1731 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1733 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1734 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1736 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1738 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1739 rss_conf->rss_hf |= ETH_RSS_IPV6;
1740 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1742 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1743 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1745 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1747 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1748 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1750 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1754 "Unknwon RSS config from firmware (%08x), RSS disabled",
1759 rss_conf->rss_hf = 0;
1764 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1765 struct rte_eth_fc_conf *fc_conf)
1767 struct bnxt *bp = dev->data->dev_private;
1768 struct rte_eth_link link_info;
1771 rc = is_bnxt_in_error(bp);
1775 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1779 memset(fc_conf, 0, sizeof(*fc_conf));
1780 if (bp->link_info.auto_pause)
1781 fc_conf->autoneg = 1;
1782 switch (bp->link_info.pause) {
1784 fc_conf->mode = RTE_FC_NONE;
1786 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1787 fc_conf->mode = RTE_FC_TX_PAUSE;
1789 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1790 fc_conf->mode = RTE_FC_RX_PAUSE;
1792 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1793 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1794 fc_conf->mode = RTE_FC_FULL;
1800 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1801 struct rte_eth_fc_conf *fc_conf)
1803 struct bnxt *bp = dev->data->dev_private;
1806 rc = is_bnxt_in_error(bp);
1810 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1811 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1815 switch (fc_conf->mode) {
1817 bp->link_info.auto_pause = 0;
1818 bp->link_info.force_pause = 0;
1820 case RTE_FC_RX_PAUSE:
1821 if (fc_conf->autoneg) {
1822 bp->link_info.auto_pause =
1823 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1824 bp->link_info.force_pause = 0;
1826 bp->link_info.auto_pause = 0;
1827 bp->link_info.force_pause =
1828 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1831 case RTE_FC_TX_PAUSE:
1832 if (fc_conf->autoneg) {
1833 bp->link_info.auto_pause =
1834 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1835 bp->link_info.force_pause = 0;
1837 bp->link_info.auto_pause = 0;
1838 bp->link_info.force_pause =
1839 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1843 if (fc_conf->autoneg) {
1844 bp->link_info.auto_pause =
1845 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1846 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1847 bp->link_info.force_pause = 0;
1849 bp->link_info.auto_pause = 0;
1850 bp->link_info.force_pause =
1851 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1852 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1856 return bnxt_set_hwrm_link_config(bp, true);
1859 /* Add UDP tunneling port */
1861 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1862 struct rte_eth_udp_tunnel *udp_tunnel)
1864 struct bnxt *bp = eth_dev->data->dev_private;
1865 uint16_t tunnel_type = 0;
1868 rc = is_bnxt_in_error(bp);
1872 switch (udp_tunnel->prot_type) {
1873 case RTE_TUNNEL_TYPE_VXLAN:
1874 if (bp->vxlan_port_cnt) {
1875 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1876 udp_tunnel->udp_port);
1877 if (bp->vxlan_port != udp_tunnel->udp_port) {
1878 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1881 bp->vxlan_port_cnt++;
1885 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1886 bp->vxlan_port_cnt++;
1888 case RTE_TUNNEL_TYPE_GENEVE:
1889 if (bp->geneve_port_cnt) {
1890 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1891 udp_tunnel->udp_port);
1892 if (bp->geneve_port != udp_tunnel->udp_port) {
1893 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1896 bp->geneve_port_cnt++;
1900 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1901 bp->geneve_port_cnt++;
1904 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1907 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1913 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1914 struct rte_eth_udp_tunnel *udp_tunnel)
1916 struct bnxt *bp = eth_dev->data->dev_private;
1917 uint16_t tunnel_type = 0;
1921 rc = is_bnxt_in_error(bp);
1925 switch (udp_tunnel->prot_type) {
1926 case RTE_TUNNEL_TYPE_VXLAN:
1927 if (!bp->vxlan_port_cnt) {
1928 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1931 if (bp->vxlan_port != udp_tunnel->udp_port) {
1932 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1933 udp_tunnel->udp_port, bp->vxlan_port);
1936 if (--bp->vxlan_port_cnt)
1940 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1941 port = bp->vxlan_fw_dst_port_id;
1943 case RTE_TUNNEL_TYPE_GENEVE:
1944 if (!bp->geneve_port_cnt) {
1945 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1948 if (bp->geneve_port != udp_tunnel->udp_port) {
1949 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1950 udp_tunnel->udp_port, bp->geneve_port);
1953 if (--bp->geneve_port_cnt)
1957 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1958 port = bp->geneve_fw_dst_port_id;
1961 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1965 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1968 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1971 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1972 bp->geneve_port = 0;
1977 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1979 struct bnxt_filter_info *filter;
1980 struct bnxt_vnic_info *vnic;
1982 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1984 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1985 filter = STAILQ_FIRST(&vnic->filter);
1987 /* Search for this matching MAC+VLAN filter */
1988 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
1989 /* Delete the filter */
1990 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1993 STAILQ_REMOVE(&vnic->filter, filter,
1994 bnxt_filter_info, next);
1995 bnxt_free_filter(bp, filter);
1997 "Deleted vlan filter for %d\n",
2001 filter = STAILQ_NEXT(filter, next);
2006 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2008 struct bnxt_filter_info *filter;
2009 struct bnxt_vnic_info *vnic;
2011 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2012 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2013 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2015 /* Implementation notes on the use of VNIC in this command:
2017 * By default, these filters belong to default vnic for the function.
2018 * Once these filters are set up, only destination VNIC can be modified.
2019 * If the destination VNIC is not specified in this command,
2020 * then the HWRM shall only create an l2 context id.
2023 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2024 filter = STAILQ_FIRST(&vnic->filter);
2025 /* Check if the VLAN has already been added */
2027 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2030 filter = STAILQ_NEXT(filter, next);
2033 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2034 * command to create MAC+VLAN filter with the right flags, enables set.
2036 filter = bnxt_alloc_filter(bp);
2039 "MAC/VLAN filter alloc failed\n");
2042 /* MAC + VLAN ID filter */
2043 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2044 * untagged packets are received
2046 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2047 * packets and only the programmed vlan's packets are received
2049 filter->l2_ivlan = vlan_id;
2050 filter->l2_ivlan_mask = 0x0FFF;
2051 filter->enables |= en;
2052 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2054 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2056 /* Free the newly allocated filter as we were
2057 * not able to create the filter in hardware.
2059 bnxt_free_filter(bp, filter);
2063 filter->mac_index = 0;
2064 /* Add this new filter to the list */
2066 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2068 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2071 "Added Vlan filter for %d\n", vlan_id);
2075 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2076 uint16_t vlan_id, int on)
2078 struct bnxt *bp = eth_dev->data->dev_private;
2081 rc = is_bnxt_in_error(bp);
2085 if (!eth_dev->data->dev_started) {
2086 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2090 /* These operations apply to ALL existing MAC/VLAN filters */
2092 return bnxt_add_vlan_filter(bp, vlan_id);
2094 return bnxt_del_vlan_filter(bp, vlan_id);
2097 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2098 struct bnxt_vnic_info *vnic)
2100 struct bnxt_filter_info *filter;
2103 filter = STAILQ_FIRST(&vnic->filter);
2105 if (filter->mac_index == 0 &&
2106 !memcmp(filter->l2_addr, bp->mac_addr,
2107 RTE_ETHER_ADDR_LEN)) {
2108 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2110 STAILQ_REMOVE(&vnic->filter, filter,
2111 bnxt_filter_info, next);
2112 bnxt_free_filter(bp, filter);
2116 filter = STAILQ_NEXT(filter, next);
2122 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2124 struct bnxt_vnic_info *vnic;
2128 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2129 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2130 /* Remove any VLAN filters programmed */
2131 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2132 bnxt_del_vlan_filter(bp, i);
2134 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2138 /* Default filter will allow packets that match the
2139 * dest mac. So, it has to be deleted, otherwise, we
2140 * will endup receiving vlan packets for which the
2141 * filter is not programmed, when hw-vlan-filter
2142 * configuration is ON
2144 bnxt_del_dflt_mac_filter(bp, vnic);
2145 /* This filter will allow only untagged packets */
2146 bnxt_add_vlan_filter(bp, 0);
2148 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2149 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2154 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2156 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2160 /* Destroy vnic filters and vnic */
2161 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2162 DEV_RX_OFFLOAD_VLAN_FILTER) {
2163 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2164 bnxt_del_vlan_filter(bp, i);
2166 bnxt_del_dflt_mac_filter(bp, vnic);
2168 rc = bnxt_hwrm_vnic_free(bp, vnic);
2172 rte_free(vnic->fw_grp_ids);
2173 vnic->fw_grp_ids = NULL;
2179 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2181 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2184 /* Destroy, recreate and reconfigure the default vnic */
2185 rc = bnxt_free_one_vnic(bp, 0);
2189 /* default vnic 0 */
2190 rc = bnxt_setup_one_vnic(bp, 0);
2194 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2195 DEV_RX_OFFLOAD_VLAN_FILTER) {
2196 rc = bnxt_add_vlan_filter(bp, 0);
2199 rc = bnxt_restore_vlan_filters(bp);
2203 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2208 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2212 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2213 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2219 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2221 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2222 struct bnxt *bp = dev->data->dev_private;
2225 rc = is_bnxt_in_error(bp);
2229 /* Filter settings will get applied when port is started */
2230 if (!dev->data->dev_started)
2233 if (mask & ETH_VLAN_FILTER_MASK) {
2234 /* Enable or disable VLAN filtering */
2235 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2240 if (mask & ETH_VLAN_STRIP_MASK) {
2241 /* Enable or disable VLAN stripping */
2242 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2247 if (mask & ETH_VLAN_EXTEND_MASK) {
2248 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2249 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2251 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2258 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2261 struct bnxt *bp = dev->data->dev_private;
2262 int qinq = dev->data->dev_conf.rxmode.offloads &
2263 DEV_RX_OFFLOAD_VLAN_EXTEND;
2265 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2266 vlan_type != ETH_VLAN_TYPE_OUTER) {
2268 "Unsupported vlan type.");
2273 "QinQ not enabled. Needs to be ON as we can "
2274 "accelerate only outer vlan\n");
2278 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2280 case RTE_ETHER_TYPE_QINQ:
2282 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2284 case RTE_ETHER_TYPE_VLAN:
2286 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2290 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2294 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2298 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2301 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2304 bp->outer_tpid_bd |= tpid;
2305 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2306 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2308 "Can accelerate only outer vlan in QinQ\n");
2316 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2317 struct rte_ether_addr *addr)
2319 struct bnxt *bp = dev->data->dev_private;
2320 /* Default Filter is tied to VNIC 0 */
2321 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2324 rc = is_bnxt_in_error(bp);
2328 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2331 if (rte_is_zero_ether_addr(addr))
2334 /* Filter settings will get applied when port is started */
2335 if (!dev->data->dev_started)
2338 /* Check if the requested MAC is already added */
2339 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2342 /* Destroy filter and re-create it */
2343 bnxt_del_dflt_mac_filter(bp, vnic);
2345 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2346 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2347 /* This filter will allow only untagged packets */
2348 rc = bnxt_add_vlan_filter(bp, 0);
2350 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2353 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2358 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2359 struct rte_ether_addr *mc_addr_set,
2360 uint32_t nb_mc_addr)
2362 struct bnxt *bp = eth_dev->data->dev_private;
2363 char *mc_addr_list = (char *)mc_addr_set;
2364 struct bnxt_vnic_info *vnic;
2365 uint32_t off = 0, i = 0;
2368 rc = is_bnxt_in_error(bp);
2372 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2374 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2375 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2379 /* TODO Check for Duplicate mcast addresses */
2380 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2381 for (i = 0; i < nb_mc_addr; i++) {
2382 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2383 RTE_ETHER_ADDR_LEN);
2384 off += RTE_ETHER_ADDR_LEN;
2387 vnic->mc_addr_cnt = i;
2388 if (vnic->mc_addr_cnt)
2389 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2391 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2394 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2398 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2400 struct bnxt *bp = dev->data->dev_private;
2401 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2402 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2403 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2406 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2407 fw_major, fw_minor, fw_updt);
2409 ret += 1; /* add the size of '\0' */
2410 if (fw_size < (uint32_t)ret)
2417 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2418 struct rte_eth_rxq_info *qinfo)
2420 struct bnxt *bp = dev->data->dev_private;
2421 struct bnxt_rx_queue *rxq;
2423 if (is_bnxt_in_error(bp))
2426 rxq = dev->data->rx_queues[queue_id];
2428 qinfo->mp = rxq->mb_pool;
2429 qinfo->scattered_rx = dev->data->scattered_rx;
2430 qinfo->nb_desc = rxq->nb_rx_desc;
2432 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2433 qinfo->conf.rx_drop_en = 0;
2434 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2438 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2439 struct rte_eth_txq_info *qinfo)
2441 struct bnxt *bp = dev->data->dev_private;
2442 struct bnxt_tx_queue *txq;
2444 if (is_bnxt_in_error(bp))
2447 txq = dev->data->tx_queues[queue_id];
2449 qinfo->nb_desc = txq->nb_tx_desc;
2451 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2452 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2453 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2455 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2456 qinfo->conf.tx_rs_thresh = 0;
2457 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2460 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2462 struct bnxt *bp = eth_dev->data->dev_private;
2463 uint32_t new_pkt_size;
2467 rc = is_bnxt_in_error(bp);
2471 /* Exit if receive queues are not configured yet */
2472 if (!eth_dev->data->nb_rx_queues)
2475 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2476 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2480 * If vector-mode tx/rx is active, disallow any MTU change that would
2481 * require scattered receive support.
2483 if (eth_dev->data->dev_started &&
2484 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2485 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2487 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2489 "MTU change would require scattered rx support. ");
2490 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2495 if (new_mtu > RTE_ETHER_MTU) {
2496 bp->flags |= BNXT_FLAG_JUMBO;
2497 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2498 DEV_RX_OFFLOAD_JUMBO_FRAME;
2500 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2501 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2502 bp->flags &= ~BNXT_FLAG_JUMBO;
2505 /* Is there a change in mtu setting? */
2506 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2509 for (i = 0; i < bp->nr_vnics; i++) {
2510 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2513 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2514 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2518 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2519 size -= RTE_PKTMBUF_HEADROOM;
2521 if (size < new_mtu) {
2522 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2529 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2531 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2537 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2539 struct bnxt *bp = dev->data->dev_private;
2540 uint16_t vlan = bp->vlan;
2543 rc = is_bnxt_in_error(bp);
2547 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2549 "PVID cannot be modified for this function\n");
2552 bp->vlan = on ? pvid : 0;
2554 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2561 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2563 struct bnxt *bp = dev->data->dev_private;
2566 rc = is_bnxt_in_error(bp);
2570 return bnxt_hwrm_port_led_cfg(bp, true);
2574 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2576 struct bnxt *bp = dev->data->dev_private;
2579 rc = is_bnxt_in_error(bp);
2583 return bnxt_hwrm_port_led_cfg(bp, false);
2587 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2589 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2590 uint32_t desc = 0, raw_cons = 0, cons;
2591 struct bnxt_cp_ring_info *cpr;
2592 struct bnxt_rx_queue *rxq;
2593 struct rx_pkt_cmpl *rxcmp;
2596 rc = is_bnxt_in_error(bp);
2600 rxq = dev->data->rx_queues[rx_queue_id];
2602 raw_cons = cpr->cp_raw_cons;
2605 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2606 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2607 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2609 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2621 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2623 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2624 struct bnxt_rx_ring_info *rxr;
2625 struct bnxt_cp_ring_info *cpr;
2626 struct bnxt_sw_rx_bd *rx_buf;
2627 struct rx_pkt_cmpl *rxcmp;
2628 uint32_t cons, cp_cons;
2634 rc = is_bnxt_in_error(rxq->bp);
2641 if (offset >= rxq->nb_rx_desc)
2644 cons = RING_CMP(cpr->cp_ring_struct, offset);
2645 cp_cons = cpr->cp_raw_cons;
2646 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2648 if (cons > cp_cons) {
2649 if (CMPL_VALID(rxcmp, cpr->valid))
2650 return RTE_ETH_RX_DESC_DONE;
2652 if (CMPL_VALID(rxcmp, !cpr->valid))
2653 return RTE_ETH_RX_DESC_DONE;
2655 rx_buf = &rxr->rx_buf_ring[cons];
2656 if (rx_buf->mbuf == NULL)
2657 return RTE_ETH_RX_DESC_UNAVAIL;
2660 return RTE_ETH_RX_DESC_AVAIL;
2664 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2666 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2667 struct bnxt_tx_ring_info *txr;
2668 struct bnxt_cp_ring_info *cpr;
2669 struct bnxt_sw_tx_bd *tx_buf;
2670 struct tx_pkt_cmpl *txcmp;
2671 uint32_t cons, cp_cons;
2677 rc = is_bnxt_in_error(txq->bp);
2684 if (offset >= txq->nb_tx_desc)
2687 cons = RING_CMP(cpr->cp_ring_struct, offset);
2688 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2689 cp_cons = cpr->cp_raw_cons;
2691 if (cons > cp_cons) {
2692 if (CMPL_VALID(txcmp, cpr->valid))
2693 return RTE_ETH_TX_DESC_UNAVAIL;
2695 if (CMPL_VALID(txcmp, !cpr->valid))
2696 return RTE_ETH_TX_DESC_UNAVAIL;
2698 tx_buf = &txr->tx_buf_ring[cons];
2699 if (tx_buf->mbuf == NULL)
2700 return RTE_ETH_TX_DESC_DONE;
2702 return RTE_ETH_TX_DESC_FULL;
2705 static struct bnxt_filter_info *
2706 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2707 struct rte_eth_ethertype_filter *efilter,
2708 struct bnxt_vnic_info *vnic0,
2709 struct bnxt_vnic_info *vnic,
2712 struct bnxt_filter_info *mfilter = NULL;
2716 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2717 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2718 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2719 " ethertype filter.", efilter->ether_type);
2723 if (efilter->queue >= bp->rx_nr_rings) {
2724 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2729 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2730 vnic = &bp->vnic_info[efilter->queue];
2732 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2737 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2738 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2739 if ((!memcmp(efilter->mac_addr.addr_bytes,
2740 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2742 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2743 mfilter->ethertype == efilter->ether_type)) {
2749 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2750 if ((!memcmp(efilter->mac_addr.addr_bytes,
2751 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2752 mfilter->ethertype == efilter->ether_type &&
2754 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2768 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2769 enum rte_filter_op filter_op,
2772 struct bnxt *bp = dev->data->dev_private;
2773 struct rte_eth_ethertype_filter *efilter =
2774 (struct rte_eth_ethertype_filter *)arg;
2775 struct bnxt_filter_info *bfilter, *filter1;
2776 struct bnxt_vnic_info *vnic, *vnic0;
2779 if (filter_op == RTE_ETH_FILTER_NOP)
2783 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2788 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2789 vnic = &bp->vnic_info[efilter->queue];
2791 switch (filter_op) {
2792 case RTE_ETH_FILTER_ADD:
2793 bnxt_match_and_validate_ether_filter(bp, efilter,
2798 bfilter = bnxt_get_unused_filter(bp);
2799 if (bfilter == NULL) {
2801 "Not enough resources for a new filter.\n");
2804 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2805 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2806 RTE_ETHER_ADDR_LEN);
2807 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2808 RTE_ETHER_ADDR_LEN);
2809 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2810 bfilter->ethertype = efilter->ether_type;
2811 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2813 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2814 if (filter1 == NULL) {
2819 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2820 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2822 bfilter->dst_id = vnic->fw_vnic_id;
2824 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2826 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2829 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2832 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2834 case RTE_ETH_FILTER_DELETE:
2835 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2837 if (ret == -EEXIST) {
2838 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2840 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2842 bnxt_free_filter(bp, filter1);
2843 } else if (ret == 0) {
2844 PMD_DRV_LOG(ERR, "No matching filter found\n");
2848 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2854 bnxt_free_filter(bp, bfilter);
2860 parse_ntuple_filter(struct bnxt *bp,
2861 struct rte_eth_ntuple_filter *nfilter,
2862 struct bnxt_filter_info *bfilter)
2866 if (nfilter->queue >= bp->rx_nr_rings) {
2867 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2871 switch (nfilter->dst_port_mask) {
2873 bfilter->dst_port_mask = -1;
2874 bfilter->dst_port = nfilter->dst_port;
2875 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2876 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2879 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2883 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2884 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2886 switch (nfilter->proto_mask) {
2888 if (nfilter->proto == 17) /* IPPROTO_UDP */
2889 bfilter->ip_protocol = 17;
2890 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2891 bfilter->ip_protocol = 6;
2894 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2897 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2901 switch (nfilter->dst_ip_mask) {
2903 bfilter->dst_ipaddr_mask[0] = -1;
2904 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2905 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2906 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2909 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2913 switch (nfilter->src_ip_mask) {
2915 bfilter->src_ipaddr_mask[0] = -1;
2916 bfilter->src_ipaddr[0] = nfilter->src_ip;
2917 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2918 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2921 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2925 switch (nfilter->src_port_mask) {
2927 bfilter->src_port_mask = -1;
2928 bfilter->src_port = nfilter->src_port;
2929 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2930 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2933 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2937 bfilter->enables = en;
2941 static struct bnxt_filter_info*
2942 bnxt_match_ntuple_filter(struct bnxt *bp,
2943 struct bnxt_filter_info *bfilter,
2944 struct bnxt_vnic_info **mvnic)
2946 struct bnxt_filter_info *mfilter = NULL;
2949 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2950 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2951 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2952 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2953 bfilter->src_ipaddr_mask[0] ==
2954 mfilter->src_ipaddr_mask[0] &&
2955 bfilter->src_port == mfilter->src_port &&
2956 bfilter->src_port_mask == mfilter->src_port_mask &&
2957 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2958 bfilter->dst_ipaddr_mask[0] ==
2959 mfilter->dst_ipaddr_mask[0] &&
2960 bfilter->dst_port == mfilter->dst_port &&
2961 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2962 bfilter->flags == mfilter->flags &&
2963 bfilter->enables == mfilter->enables) {
2974 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2975 struct rte_eth_ntuple_filter *nfilter,
2976 enum rte_filter_op filter_op)
2978 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2979 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2982 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2983 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2987 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2988 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2992 bfilter = bnxt_get_unused_filter(bp);
2993 if (bfilter == NULL) {
2995 "Not enough resources for a new filter.\n");
2998 ret = parse_ntuple_filter(bp, nfilter, bfilter);
3002 vnic = &bp->vnic_info[nfilter->queue];
3003 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3004 filter1 = STAILQ_FIRST(&vnic0->filter);
3005 if (filter1 == NULL) {
3010 bfilter->dst_id = vnic->fw_vnic_id;
3011 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3013 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3014 bfilter->ethertype = 0x800;
3015 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3017 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3019 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3020 bfilter->dst_id == mfilter->dst_id) {
3021 PMD_DRV_LOG(ERR, "filter exists.\n");
3024 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3025 bfilter->dst_id != mfilter->dst_id) {
3026 mfilter->dst_id = vnic->fw_vnic_id;
3027 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3028 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3029 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3030 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3031 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3034 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3035 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3040 if (filter_op == RTE_ETH_FILTER_ADD) {
3041 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3042 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3045 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3047 if (mfilter == NULL) {
3048 /* This should not happen. But for Coverity! */
3052 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3054 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3055 bnxt_free_filter(bp, mfilter);
3056 bnxt_free_filter(bp, bfilter);
3061 bnxt_free_filter(bp, bfilter);
3066 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3067 enum rte_filter_op filter_op,
3070 struct bnxt *bp = dev->data->dev_private;
3073 if (filter_op == RTE_ETH_FILTER_NOP)
3077 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3082 switch (filter_op) {
3083 case RTE_ETH_FILTER_ADD:
3084 ret = bnxt_cfg_ntuple_filter(bp,
3085 (struct rte_eth_ntuple_filter *)arg,
3088 case RTE_ETH_FILTER_DELETE:
3089 ret = bnxt_cfg_ntuple_filter(bp,
3090 (struct rte_eth_ntuple_filter *)arg,
3094 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3102 bnxt_parse_fdir_filter(struct bnxt *bp,
3103 struct rte_eth_fdir_filter *fdir,
3104 struct bnxt_filter_info *filter)
3106 enum rte_fdir_mode fdir_mode =
3107 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3108 struct bnxt_vnic_info *vnic0, *vnic;
3109 struct bnxt_filter_info *filter1;
3113 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3116 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3117 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3119 switch (fdir->input.flow_type) {
3120 case RTE_ETH_FLOW_IPV4:
3121 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3123 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3124 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3125 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3126 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3127 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3128 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3129 filter->ip_addr_type =
3130 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3131 filter->src_ipaddr_mask[0] = 0xffffffff;
3132 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3133 filter->dst_ipaddr_mask[0] = 0xffffffff;
3134 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3135 filter->ethertype = 0x800;
3136 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3138 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3139 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3140 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3141 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3142 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3143 filter->dst_port_mask = 0xffff;
3144 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3145 filter->src_port_mask = 0xffff;
3146 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3147 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3148 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3149 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3150 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3151 filter->ip_protocol = 6;
3152 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3153 filter->ip_addr_type =
3154 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3155 filter->src_ipaddr_mask[0] = 0xffffffff;
3156 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3157 filter->dst_ipaddr_mask[0] = 0xffffffff;
3158 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3159 filter->ethertype = 0x800;
3160 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3162 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3163 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3164 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3165 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3166 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3167 filter->dst_port_mask = 0xffff;
3168 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3169 filter->src_port_mask = 0xffff;
3170 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3171 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3172 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3173 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3174 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3175 filter->ip_protocol = 17;
3176 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3177 filter->ip_addr_type =
3178 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3179 filter->src_ipaddr_mask[0] = 0xffffffff;
3180 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3181 filter->dst_ipaddr_mask[0] = 0xffffffff;
3182 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3183 filter->ethertype = 0x800;
3184 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3186 case RTE_ETH_FLOW_IPV6:
3187 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3189 filter->ip_addr_type =
3190 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3191 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3192 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3193 rte_memcpy(filter->src_ipaddr,
3194 fdir->input.flow.ipv6_flow.src_ip, 16);
3195 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3196 rte_memcpy(filter->dst_ipaddr,
3197 fdir->input.flow.ipv6_flow.dst_ip, 16);
3198 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3199 memset(filter->dst_ipaddr_mask, 0xff, 16);
3200 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3201 memset(filter->src_ipaddr_mask, 0xff, 16);
3202 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3203 filter->ethertype = 0x86dd;
3204 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3206 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3207 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3208 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3209 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3210 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3211 filter->dst_port_mask = 0xffff;
3212 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3213 filter->src_port_mask = 0xffff;
3214 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3215 filter->ip_addr_type =
3216 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3217 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3218 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3219 rte_memcpy(filter->src_ipaddr,
3220 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3221 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3222 rte_memcpy(filter->dst_ipaddr,
3223 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3224 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3225 memset(filter->dst_ipaddr_mask, 0xff, 16);
3226 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3227 memset(filter->src_ipaddr_mask, 0xff, 16);
3228 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3229 filter->ethertype = 0x86dd;
3230 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3232 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3233 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3234 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3235 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3236 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3237 filter->dst_port_mask = 0xffff;
3238 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3239 filter->src_port_mask = 0xffff;
3240 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3241 filter->ip_addr_type =
3242 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3243 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3244 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3245 rte_memcpy(filter->src_ipaddr,
3246 fdir->input.flow.udp6_flow.ip.src_ip, 16);
3247 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3248 rte_memcpy(filter->dst_ipaddr,
3249 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3250 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3251 memset(filter->dst_ipaddr_mask, 0xff, 16);
3252 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3253 memset(filter->src_ipaddr_mask, 0xff, 16);
3254 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3255 filter->ethertype = 0x86dd;
3256 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3258 case RTE_ETH_FLOW_L2_PAYLOAD:
3259 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3260 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3262 case RTE_ETH_FLOW_VXLAN:
3263 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3265 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3266 filter->tunnel_type =
3267 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3268 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3270 case RTE_ETH_FLOW_NVGRE:
3271 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3273 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3274 filter->tunnel_type =
3275 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3276 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3278 case RTE_ETH_FLOW_UNKNOWN:
3279 case RTE_ETH_FLOW_RAW:
3280 case RTE_ETH_FLOW_FRAG_IPV4:
3281 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3282 case RTE_ETH_FLOW_FRAG_IPV6:
3283 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3284 case RTE_ETH_FLOW_IPV6_EX:
3285 case RTE_ETH_FLOW_IPV6_TCP_EX:
3286 case RTE_ETH_FLOW_IPV6_UDP_EX:
3287 case RTE_ETH_FLOW_GENEVE:
3293 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3294 vnic = &bp->vnic_info[fdir->action.rx_queue];
3296 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3300 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3301 rte_memcpy(filter->dst_macaddr,
3302 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3303 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3306 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3307 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3308 filter1 = STAILQ_FIRST(&vnic0->filter);
3309 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3311 filter->dst_id = vnic->fw_vnic_id;
3312 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3313 if (filter->dst_macaddr[i] == 0x00)
3314 filter1 = STAILQ_FIRST(&vnic0->filter);
3316 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3319 if (filter1 == NULL)
3322 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3323 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3325 filter->enables = en;
3330 static struct bnxt_filter_info *
3331 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3332 struct bnxt_vnic_info **mvnic)
3334 struct bnxt_filter_info *mf = NULL;
3337 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3338 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3340 STAILQ_FOREACH(mf, &vnic->filter, next) {
3341 if (mf->filter_type == nf->filter_type &&
3342 mf->flags == nf->flags &&
3343 mf->src_port == nf->src_port &&
3344 mf->src_port_mask == nf->src_port_mask &&
3345 mf->dst_port == nf->dst_port &&
3346 mf->dst_port_mask == nf->dst_port_mask &&
3347 mf->ip_protocol == nf->ip_protocol &&
3348 mf->ip_addr_type == nf->ip_addr_type &&
3349 mf->ethertype == nf->ethertype &&
3350 mf->vni == nf->vni &&
3351 mf->tunnel_type == nf->tunnel_type &&
3352 mf->l2_ovlan == nf->l2_ovlan &&
3353 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3354 mf->l2_ivlan == nf->l2_ivlan &&
3355 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3356 !memcmp(mf->l2_addr, nf->l2_addr,
3357 RTE_ETHER_ADDR_LEN) &&
3358 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3359 RTE_ETHER_ADDR_LEN) &&
3360 !memcmp(mf->src_macaddr, nf->src_macaddr,
3361 RTE_ETHER_ADDR_LEN) &&
3362 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3363 RTE_ETHER_ADDR_LEN) &&
3364 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3365 sizeof(nf->src_ipaddr)) &&
3366 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3367 sizeof(nf->src_ipaddr_mask)) &&
3368 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3369 sizeof(nf->dst_ipaddr)) &&
3370 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3371 sizeof(nf->dst_ipaddr_mask))) {
3382 bnxt_fdir_filter(struct rte_eth_dev *dev,
3383 enum rte_filter_op filter_op,
3386 struct bnxt *bp = dev->data->dev_private;
3387 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
3388 struct bnxt_filter_info *filter, *match;
3389 struct bnxt_vnic_info *vnic, *mvnic;
3392 if (filter_op == RTE_ETH_FILTER_NOP)
3395 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3398 switch (filter_op) {
3399 case RTE_ETH_FILTER_ADD:
3400 case RTE_ETH_FILTER_DELETE:
3402 filter = bnxt_get_unused_filter(bp);
3403 if (filter == NULL) {
3405 "Not enough resources for a new flow.\n");
3409 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3412 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3414 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3415 vnic = &bp->vnic_info[0];
3417 vnic = &bp->vnic_info[fdir->action.rx_queue];
3419 match = bnxt_match_fdir(bp, filter, &mvnic);
3420 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3421 if (match->dst_id == vnic->fw_vnic_id) {
3422 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3426 match->dst_id = vnic->fw_vnic_id;
3427 ret = bnxt_hwrm_set_ntuple_filter(bp,
3430 STAILQ_REMOVE(&mvnic->filter, match,
3431 bnxt_filter_info, next);
3432 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3434 "Filter with matching pattern exist\n");
3436 "Updated it to new destination q\n");
3440 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3441 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3446 if (filter_op == RTE_ETH_FILTER_ADD) {
3447 ret = bnxt_hwrm_set_ntuple_filter(bp,
3452 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3454 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3455 STAILQ_REMOVE(&vnic->filter, match,
3456 bnxt_filter_info, next);
3457 bnxt_free_filter(bp, match);
3458 bnxt_free_filter(bp, filter);
3461 case RTE_ETH_FILTER_FLUSH:
3462 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3463 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3465 STAILQ_FOREACH(filter, &vnic->filter, next) {
3466 if (filter->filter_type ==
3467 HWRM_CFA_NTUPLE_FILTER) {
3469 bnxt_hwrm_clear_ntuple_filter(bp,
3471 STAILQ_REMOVE(&vnic->filter, filter,
3472 bnxt_filter_info, next);
3477 case RTE_ETH_FILTER_UPDATE:
3478 case RTE_ETH_FILTER_STATS:
3479 case RTE_ETH_FILTER_INFO:
3480 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3483 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3490 bnxt_free_filter(bp, filter);
3495 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3496 enum rte_filter_type filter_type,
3497 enum rte_filter_op filter_op, void *arg)
3499 struct bnxt *bp = dev->data->dev_private;
3502 ret = is_bnxt_in_error(dev->data->dev_private);
3506 switch (filter_type) {
3507 case RTE_ETH_FILTER_TUNNEL:
3509 "filter type: %d: To be implemented\n", filter_type);
3511 case RTE_ETH_FILTER_FDIR:
3512 ret = bnxt_fdir_filter(dev, filter_op, arg);
3514 case RTE_ETH_FILTER_NTUPLE:
3515 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3517 case RTE_ETH_FILTER_ETHERTYPE:
3518 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3520 case RTE_ETH_FILTER_GENERIC:
3521 if (filter_op != RTE_ETH_FILTER_GET)
3524 *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3526 *(const void **)arg = &bnxt_flow_ops;
3530 "Filter type (%d) not supported", filter_type);
3537 static const uint32_t *
3538 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3540 static const uint32_t ptypes[] = {
3541 RTE_PTYPE_L2_ETHER_VLAN,
3542 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3543 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3547 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3548 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3549 RTE_PTYPE_INNER_L4_ICMP,
3550 RTE_PTYPE_INNER_L4_TCP,
3551 RTE_PTYPE_INNER_L4_UDP,
3555 if (!dev->rx_pkt_burst)
3561 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3564 uint32_t reg_base = *reg_arr & 0xfffff000;
3568 for (i = 0; i < count; i++) {
3569 if ((reg_arr[i] & 0xfffff000) != reg_base)
3572 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3573 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3577 static int bnxt_map_ptp_regs(struct bnxt *bp)
3579 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3583 reg_arr = ptp->rx_regs;
3584 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3588 reg_arr = ptp->tx_regs;
3589 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3593 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3594 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3596 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3597 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3602 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3604 rte_write32(0, (uint8_t *)bp->bar0 +
3605 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3606 rte_write32(0, (uint8_t *)bp->bar0 +
3607 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3610 static uint64_t bnxt_cc_read(struct bnxt *bp)
3614 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3615 BNXT_GRCPF_REG_SYNC_TIME));
3616 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3617 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3621 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3623 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3626 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3627 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3628 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3631 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3632 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3633 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3634 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3635 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3636 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3641 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3643 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3644 struct bnxt_pf_info *pf = &bp->pf;
3651 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3652 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3653 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3656 port_id = pf->port_id;
3657 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3658 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3660 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3661 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3662 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3663 /* bnxt_clr_rx_ts(bp); TBD */
3667 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3668 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3669 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3670 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3676 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3679 struct bnxt *bp = dev->data->dev_private;
3680 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3685 ns = rte_timespec_to_ns(ts);
3686 /* Set the timecounters to a new value. */
3693 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3695 struct bnxt *bp = dev->data->dev_private;
3696 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3697 uint64_t ns, systime_cycles = 0;
3703 if (BNXT_CHIP_THOR(bp))
3704 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3707 systime_cycles = bnxt_cc_read(bp);
3709 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3710 *ts = rte_ns_to_timespec(ns);
3715 bnxt_timesync_enable(struct rte_eth_dev *dev)
3717 struct bnxt *bp = dev->data->dev_private;
3718 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3726 ptp->tx_tstamp_en = 1;
3727 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3729 rc = bnxt_hwrm_ptp_cfg(bp);
3733 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3734 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3735 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3737 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3738 ptp->tc.cc_shift = shift;
3739 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3741 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3742 ptp->rx_tstamp_tc.cc_shift = shift;
3743 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3745 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3746 ptp->tx_tstamp_tc.cc_shift = shift;
3747 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3749 if (!BNXT_CHIP_THOR(bp))
3750 bnxt_map_ptp_regs(bp);
3756 bnxt_timesync_disable(struct rte_eth_dev *dev)
3758 struct bnxt *bp = dev->data->dev_private;
3759 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3765 ptp->tx_tstamp_en = 0;
3768 bnxt_hwrm_ptp_cfg(bp);
3770 if (!BNXT_CHIP_THOR(bp))
3771 bnxt_unmap_ptp_regs(bp);
3777 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3778 struct timespec *timestamp,
3779 uint32_t flags __rte_unused)
3781 struct bnxt *bp = dev->data->dev_private;
3782 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3783 uint64_t rx_tstamp_cycles = 0;
3789 if (BNXT_CHIP_THOR(bp))
3790 rx_tstamp_cycles = ptp->rx_timestamp;
3792 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3794 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3795 *timestamp = rte_ns_to_timespec(ns);
3800 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3801 struct timespec *timestamp)
3803 struct bnxt *bp = dev->data->dev_private;
3804 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3805 uint64_t tx_tstamp_cycles = 0;
3812 if (BNXT_CHIP_THOR(bp))
3813 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3816 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3818 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3819 *timestamp = rte_ns_to_timespec(ns);
3825 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3827 struct bnxt *bp = dev->data->dev_private;
3828 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3833 ptp->tc.nsec += delta;
3839 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3841 struct bnxt *bp = dev->data->dev_private;
3843 uint32_t dir_entries;
3844 uint32_t entry_length;
3846 rc = is_bnxt_in_error(bp);
3850 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3851 bp->pdev->addr.domain, bp->pdev->addr.bus,
3852 bp->pdev->addr.devid, bp->pdev->addr.function);
3854 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3858 return dir_entries * entry_length;
3862 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3863 struct rte_dev_eeprom_info *in_eeprom)
3865 struct bnxt *bp = dev->data->dev_private;
3870 rc = is_bnxt_in_error(bp);
3874 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3875 bp->pdev->addr.domain, bp->pdev->addr.bus,
3876 bp->pdev->addr.devid, bp->pdev->addr.function,
3877 in_eeprom->offset, in_eeprom->length);
3879 if (in_eeprom->offset == 0) /* special offset value to get directory */
3880 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3883 index = in_eeprom->offset >> 24;
3884 offset = in_eeprom->offset & 0xffffff;
3887 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3888 in_eeprom->length, in_eeprom->data);
3893 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3896 case BNX_DIR_TYPE_CHIMP_PATCH:
3897 case BNX_DIR_TYPE_BOOTCODE:
3898 case BNX_DIR_TYPE_BOOTCODE_2:
3899 case BNX_DIR_TYPE_APE_FW:
3900 case BNX_DIR_TYPE_APE_PATCH:
3901 case BNX_DIR_TYPE_KONG_FW:
3902 case BNX_DIR_TYPE_KONG_PATCH:
3903 case BNX_DIR_TYPE_BONO_FW:
3904 case BNX_DIR_TYPE_BONO_PATCH:
3912 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3915 case BNX_DIR_TYPE_AVS:
3916 case BNX_DIR_TYPE_EXP_ROM_MBA:
3917 case BNX_DIR_TYPE_PCIE:
3918 case BNX_DIR_TYPE_TSCF_UCODE:
3919 case BNX_DIR_TYPE_EXT_PHY:
3920 case BNX_DIR_TYPE_CCM:
3921 case BNX_DIR_TYPE_ISCSI_BOOT:
3922 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3923 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3931 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3933 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3934 bnxt_dir_type_is_other_exec_format(dir_type);
3938 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3939 struct rte_dev_eeprom_info *in_eeprom)
3941 struct bnxt *bp = dev->data->dev_private;
3942 uint8_t index, dir_op;
3943 uint16_t type, ext, ordinal, attr;
3946 rc = is_bnxt_in_error(bp);
3950 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3951 bp->pdev->addr.domain, bp->pdev->addr.bus,
3952 bp->pdev->addr.devid, bp->pdev->addr.function,
3953 in_eeprom->offset, in_eeprom->length);
3956 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3960 type = in_eeprom->magic >> 16;
3962 if (type == 0xffff) { /* special value for directory operations */
3963 index = in_eeprom->magic & 0xff;
3964 dir_op = in_eeprom->magic >> 8;
3968 case 0x0e: /* erase */
3969 if (in_eeprom->offset != ~in_eeprom->magic)
3971 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3977 /* Create or re-write an NVM item: */
3978 if (bnxt_dir_type_is_executable(type) == true)
3980 ext = in_eeprom->magic & 0xffff;
3981 ordinal = in_eeprom->offset >> 16;
3982 attr = in_eeprom->offset & 0xffff;
3984 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3985 in_eeprom->data, in_eeprom->length);
3992 static const struct eth_dev_ops bnxt_dev_ops = {
3993 .dev_infos_get = bnxt_dev_info_get_op,
3994 .dev_close = bnxt_dev_close_op,
3995 .dev_configure = bnxt_dev_configure_op,
3996 .dev_start = bnxt_dev_start_op,
3997 .dev_stop = bnxt_dev_stop_op,
3998 .dev_set_link_up = bnxt_dev_set_link_up_op,
3999 .dev_set_link_down = bnxt_dev_set_link_down_op,
4000 .stats_get = bnxt_stats_get_op,
4001 .stats_reset = bnxt_stats_reset_op,
4002 .rx_queue_setup = bnxt_rx_queue_setup_op,
4003 .rx_queue_release = bnxt_rx_queue_release_op,
4004 .tx_queue_setup = bnxt_tx_queue_setup_op,
4005 .tx_queue_release = bnxt_tx_queue_release_op,
4006 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4007 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4008 .reta_update = bnxt_reta_update_op,
4009 .reta_query = bnxt_reta_query_op,
4010 .rss_hash_update = bnxt_rss_hash_update_op,
4011 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4012 .link_update = bnxt_link_update_op,
4013 .promiscuous_enable = bnxt_promiscuous_enable_op,
4014 .promiscuous_disable = bnxt_promiscuous_disable_op,
4015 .allmulticast_enable = bnxt_allmulticast_enable_op,
4016 .allmulticast_disable = bnxt_allmulticast_disable_op,
4017 .mac_addr_add = bnxt_mac_addr_add_op,
4018 .mac_addr_remove = bnxt_mac_addr_remove_op,
4019 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4020 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4021 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
4022 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
4023 .vlan_filter_set = bnxt_vlan_filter_set_op,
4024 .vlan_offload_set = bnxt_vlan_offload_set_op,
4025 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4026 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4027 .mtu_set = bnxt_mtu_set_op,
4028 .mac_addr_set = bnxt_set_default_mac_addr_op,
4029 .xstats_get = bnxt_dev_xstats_get_op,
4030 .xstats_get_names = bnxt_dev_xstats_get_names_op,
4031 .xstats_reset = bnxt_dev_xstats_reset_op,
4032 .fw_version_get = bnxt_fw_version_get,
4033 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4034 .rxq_info_get = bnxt_rxq_info_get_op,
4035 .txq_info_get = bnxt_txq_info_get_op,
4036 .dev_led_on = bnxt_dev_led_on_op,
4037 .dev_led_off = bnxt_dev_led_off_op,
4038 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4039 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4040 .rx_queue_count = bnxt_rx_queue_count_op,
4041 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
4042 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
4043 .rx_queue_start = bnxt_rx_queue_start,
4044 .rx_queue_stop = bnxt_rx_queue_stop,
4045 .tx_queue_start = bnxt_tx_queue_start,
4046 .tx_queue_stop = bnxt_tx_queue_stop,
4047 .filter_ctrl = bnxt_filter_ctrl_op,
4048 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4049 .get_eeprom_length = bnxt_get_eeprom_length_op,
4050 .get_eeprom = bnxt_get_eeprom_op,
4051 .set_eeprom = bnxt_set_eeprom_op,
4052 .timesync_enable = bnxt_timesync_enable,
4053 .timesync_disable = bnxt_timesync_disable,
4054 .timesync_read_time = bnxt_timesync_read_time,
4055 .timesync_write_time = bnxt_timesync_write_time,
4056 .timesync_adjust_time = bnxt_timesync_adjust_time,
4057 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4058 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4061 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4065 /* Only pre-map the reset GRC registers using window 3 */
4066 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4067 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4069 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4074 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4076 struct bnxt_error_recovery_info *info = bp->recovery_info;
4077 uint32_t reg_base = 0xffffffff;
4080 /* Only pre-map the monitoring GRC registers using window 2 */
4081 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4082 uint32_t reg = info->status_regs[i];
4084 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4087 if (reg_base == 0xffffffff)
4088 reg_base = reg & 0xfffff000;
4089 if ((reg & 0xfffff000) != reg_base)
4092 /* Use mask 0xffc as the Lower 2 bits indicates
4093 * address space location
4095 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4099 if (reg_base == 0xffffffff)
4102 rte_write32(reg_base, (uint8_t *)bp->bar0 +
4103 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4108 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4110 struct bnxt_error_recovery_info *info = bp->recovery_info;
4111 uint32_t delay = info->delay_after_reset[index];
4112 uint32_t val = info->reset_reg_val[index];
4113 uint32_t reg = info->reset_reg[index];
4114 uint32_t type, offset;
4116 type = BNXT_FW_STATUS_REG_TYPE(reg);
4117 offset = BNXT_FW_STATUS_REG_OFF(reg);
4120 case BNXT_FW_STATUS_REG_TYPE_CFG:
4121 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4123 case BNXT_FW_STATUS_REG_TYPE_GRC:
4124 offset = bnxt_map_reset_regs(bp, offset);
4125 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4127 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4128 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4131 /* wait on a specific interval of time until core reset is complete */
4133 rte_delay_ms(delay);
4136 static void bnxt_dev_cleanup(struct bnxt *bp)
4138 bnxt_set_hwrm_link_config(bp, false);
4139 bp->link_info.link_up = 0;
4140 if (bp->eth_dev->data->dev_started)
4141 bnxt_dev_stop_op(bp->eth_dev);
4143 bnxt_uninit_resources(bp, true);
4146 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4148 struct rte_eth_dev *dev = bp->eth_dev;
4149 struct rte_vlan_filter_conf *vfc;
4153 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4154 vfc = &dev->data->vlan_filter_conf;
4155 vidx = vlan_id / 64;
4156 vbit = vlan_id % 64;
4158 /* Each bit corresponds to a VLAN id */
4159 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4160 rc = bnxt_add_vlan_filter(bp, vlan_id);
4169 static int bnxt_restore_mac_filters(struct bnxt *bp)
4171 struct rte_eth_dev *dev = bp->eth_dev;
4172 struct rte_eth_dev_info dev_info;
4173 struct rte_ether_addr *addr;
4179 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
4182 rc = bnxt_dev_info_get_op(dev, &dev_info);
4186 /* replay MAC address configuration */
4187 for (i = 1; i < dev_info.max_mac_addrs; i++) {
4188 addr = &dev->data->mac_addrs[i];
4190 /* skip zero address */
4191 if (rte_is_zero_ether_addr(addr))
4195 pool_mask = dev->data->mac_pool_sel[i];
4198 if (pool_mask & 1ULL) {
4199 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4205 } while (pool_mask);
4211 static int bnxt_restore_filters(struct bnxt *bp)
4213 struct rte_eth_dev *dev = bp->eth_dev;
4216 if (dev->data->all_multicast) {
4217 ret = bnxt_allmulticast_enable_op(dev);
4221 if (dev->data->promiscuous) {
4222 ret = bnxt_promiscuous_enable_op(dev);
4227 ret = bnxt_restore_mac_filters(bp);
4231 ret = bnxt_restore_vlan_filters(bp);
4232 /* TODO restore other filters as well */
4236 static void bnxt_dev_recover(void *arg)
4238 struct bnxt *bp = arg;
4239 int timeout = bp->fw_reset_max_msecs;
4242 /* Clear Error flag so that device re-init should happen */
4243 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4246 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4249 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4250 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4251 } while (rc && timeout);
4254 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4258 rc = bnxt_init_resources(bp, true);
4261 "Failed to initialize resources after reset\n");
4264 /* clear reset flag as the device is initialized now */
4265 bp->flags &= ~BNXT_FLAG_FW_RESET;
4267 rc = bnxt_dev_start_op(bp->eth_dev);
4269 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4273 rc = bnxt_restore_filters(bp);
4277 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4280 bnxt_dev_stop_op(bp->eth_dev);
4282 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4283 bnxt_uninit_resources(bp, false);
4284 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4287 void bnxt_dev_reset_and_resume(void *arg)
4289 struct bnxt *bp = arg;
4292 bnxt_dev_cleanup(bp);
4294 bnxt_wait_for_device_shutdown(bp);
4296 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4297 bnxt_dev_recover, (void *)bp);
4299 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4302 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4304 struct bnxt_error_recovery_info *info = bp->recovery_info;
4305 uint32_t reg = info->status_regs[index];
4306 uint32_t type, offset, val = 0;
4308 type = BNXT_FW_STATUS_REG_TYPE(reg);
4309 offset = BNXT_FW_STATUS_REG_OFF(reg);
4312 case BNXT_FW_STATUS_REG_TYPE_CFG:
4313 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4315 case BNXT_FW_STATUS_REG_TYPE_GRC:
4316 offset = info->mapped_status_regs[index];
4318 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4319 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4327 static int bnxt_fw_reset_all(struct bnxt *bp)
4329 struct bnxt_error_recovery_info *info = bp->recovery_info;
4333 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4334 /* Reset through master function driver */
4335 for (i = 0; i < info->reg_array_cnt; i++)
4336 bnxt_write_fw_reset_reg(bp, i);
4337 /* Wait for time specified by FW after triggering reset */
4338 rte_delay_ms(info->master_func_wait_period_after_reset);
4339 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4340 /* Reset with the help of Kong processor */
4341 rc = bnxt_hwrm_fw_reset(bp);
4343 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4349 static void bnxt_fw_reset_cb(void *arg)
4351 struct bnxt *bp = arg;
4352 struct bnxt_error_recovery_info *info = bp->recovery_info;
4355 /* Only Master function can do FW reset */
4356 if (bnxt_is_master_func(bp) &&
4357 bnxt_is_recovery_enabled(bp)) {
4358 rc = bnxt_fw_reset_all(bp);
4360 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4365 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4366 * EXCEPTION_FATAL_ASYNC event to all the functions
4367 * (including MASTER FUNC). After receiving this Async, all the active
4368 * drivers should treat this case as FW initiated recovery
4370 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4371 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4372 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4374 /* To recover from error */
4375 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4380 /* Driver should poll FW heartbeat, reset_counter with the frequency
4381 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4382 * When the driver detects heartbeat stop or change in reset_counter,
4383 * it has to trigger a reset to recover from the error condition.
4384 * A “master PF” is the function who will have the privilege to
4385 * initiate the chimp reset. The master PF will be elected by the
4386 * firmware and will be notified through async message.
4388 static void bnxt_check_fw_health(void *arg)
4390 struct bnxt *bp = arg;
4391 struct bnxt_error_recovery_info *info = bp->recovery_info;
4392 uint32_t val = 0, wait_msec;
4394 if (!info || !bnxt_is_recovery_enabled(bp) ||
4395 is_bnxt_in_error(bp))
4398 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4399 if (val == info->last_heart_beat)
4402 info->last_heart_beat = val;
4404 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4405 if (val != info->last_reset_counter)
4408 info->last_reset_counter = val;
4410 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4411 bnxt_check_fw_health, (void *)bp);
4415 /* Stop DMA to/from device */
4416 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4417 bp->flags |= BNXT_FLAG_FW_RESET;
4419 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4421 if (bnxt_is_master_func(bp))
4422 wait_msec = info->master_func_wait_period;
4424 wait_msec = info->normal_func_wait_period;
4426 rte_eal_alarm_set(US_PER_MS * wait_msec,
4427 bnxt_fw_reset_cb, (void *)bp);
4430 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4432 uint32_t polling_freq;
4434 if (!bnxt_is_recovery_enabled(bp))
4437 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4440 polling_freq = bp->recovery_info->driver_polling_freq;
4442 rte_eal_alarm_set(US_PER_MS * polling_freq,
4443 bnxt_check_fw_health, (void *)bp);
4444 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4447 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4449 if (!bnxt_is_recovery_enabled(bp))
4452 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4453 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4456 static bool bnxt_vf_pciid(uint16_t device_id)
4458 switch (device_id) {
4459 case BROADCOM_DEV_ID_57304_VF:
4460 case BROADCOM_DEV_ID_57406_VF:
4461 case BROADCOM_DEV_ID_5731X_VF:
4462 case BROADCOM_DEV_ID_5741X_VF:
4463 case BROADCOM_DEV_ID_57414_VF:
4464 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4465 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4466 case BROADCOM_DEV_ID_58802_VF:
4467 case BROADCOM_DEV_ID_57500_VF1:
4468 case BROADCOM_DEV_ID_57500_VF2:
4476 static bool bnxt_thor_device(uint16_t device_id)
4478 switch (device_id) {
4479 case BROADCOM_DEV_ID_57508:
4480 case BROADCOM_DEV_ID_57504:
4481 case BROADCOM_DEV_ID_57502:
4482 case BROADCOM_DEV_ID_57508_MF1:
4483 case BROADCOM_DEV_ID_57504_MF1:
4484 case BROADCOM_DEV_ID_57502_MF1:
4485 case BROADCOM_DEV_ID_57508_MF2:
4486 case BROADCOM_DEV_ID_57504_MF2:
4487 case BROADCOM_DEV_ID_57502_MF2:
4488 case BROADCOM_DEV_ID_57500_VF1:
4489 case BROADCOM_DEV_ID_57500_VF2:
4497 bool bnxt_stratus_device(struct bnxt *bp)
4499 uint16_t device_id = bp->pdev->id.device_id;
4501 switch (device_id) {
4502 case BROADCOM_DEV_ID_STRATUS_NIC:
4503 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4504 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4512 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4514 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4515 struct bnxt *bp = eth_dev->data->dev_private;
4517 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4518 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4519 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4520 if (!bp->bar0 || !bp->doorbell_base) {
4521 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4525 bp->eth_dev = eth_dev;
4531 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4532 struct bnxt_ctx_pg_info *ctx_pg,
4537 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4538 const struct rte_memzone *mz = NULL;
4539 char mz_name[RTE_MEMZONE_NAMESIZE];
4540 rte_iova_t mz_phys_addr;
4541 uint64_t valid_bits = 0;
4548 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4550 rmem->page_size = BNXT_PAGE_SIZE;
4551 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4552 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4553 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4555 valid_bits = PTU_PTE_VALID;
4557 if (rmem->nr_pages > 1) {
4558 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4559 "bnxt_ctx_pg_tbl%s_%x_%d",
4560 suffix, idx, bp->eth_dev->data->port_id);
4561 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4562 mz = rte_memzone_lookup(mz_name);
4564 mz = rte_memzone_reserve_aligned(mz_name,
4568 RTE_MEMZONE_SIZE_HINT_ONLY |
4569 RTE_MEMZONE_IOVA_CONTIG,
4575 memset(mz->addr, 0, mz->len);
4576 mz_phys_addr = mz->iova;
4578 rmem->pg_tbl = mz->addr;
4579 rmem->pg_tbl_map = mz_phys_addr;
4580 rmem->pg_tbl_mz = mz;
4583 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4584 suffix, idx, bp->eth_dev->data->port_id);
4585 mz = rte_memzone_lookup(mz_name);
4587 mz = rte_memzone_reserve_aligned(mz_name,
4591 RTE_MEMZONE_SIZE_HINT_ONLY |
4592 RTE_MEMZONE_IOVA_CONTIG,
4598 memset(mz->addr, 0, mz->len);
4599 mz_phys_addr = mz->iova;
4601 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4602 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4603 rmem->dma_arr[i] = mz_phys_addr + sz;
4605 if (rmem->nr_pages > 1) {
4606 if (i == rmem->nr_pages - 2 &&
4607 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4608 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4609 else if (i == rmem->nr_pages - 1 &&
4610 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4611 valid_bits |= PTU_PTE_LAST;
4613 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4619 if (rmem->vmem_size)
4620 rmem->vmem = (void **)mz->addr;
4621 rmem->dma_arr[0] = mz_phys_addr;
4625 static void bnxt_free_ctx_mem(struct bnxt *bp)
4629 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4632 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4633 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4634 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4635 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4636 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4637 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4638 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4639 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4640 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4641 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4642 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4644 for (i = 0; i < BNXT_MAX_Q; i++) {
4645 if (bp->ctx->tqm_mem[i])
4646 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4653 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4655 #define min_t(type, x, y) ({ \
4656 type __min1 = (x); \
4657 type __min2 = (y); \
4658 __min1 < __min2 ? __min1 : __min2; })
4660 #define max_t(type, x, y) ({ \
4661 type __max1 = (x); \
4662 type __max2 = (y); \
4663 __max1 > __max2 ? __max1 : __max2; })
4665 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4667 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4669 struct bnxt_ctx_pg_info *ctx_pg;
4670 struct bnxt_ctx_mem_info *ctx;
4671 uint32_t mem_size, ena, entries;
4674 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4676 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4680 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4683 ctx_pg = &ctx->qp_mem;
4684 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4685 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4686 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4690 ctx_pg = &ctx->srq_mem;
4691 ctx_pg->entries = ctx->srq_max_l2_entries;
4692 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4693 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4697 ctx_pg = &ctx->cq_mem;
4698 ctx_pg->entries = ctx->cq_max_l2_entries;
4699 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4700 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4704 ctx_pg = &ctx->vnic_mem;
4705 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4706 ctx->vnic_max_ring_table_entries;
4707 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4708 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4712 ctx_pg = &ctx->stat_mem;
4713 ctx_pg->entries = ctx->stat_max_entries;
4714 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4715 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4719 entries = ctx->qp_max_l2_entries +
4720 ctx->vnic_max_vnic_entries +
4721 ctx->tqm_min_entries_per_ring;
4722 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4723 entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4724 ctx->tqm_max_entries_per_ring);
4725 for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4726 ctx_pg = ctx->tqm_mem[i];
4727 /* use min tqm entries for now. */
4728 ctx_pg->entries = entries;
4729 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4730 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4733 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4736 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4737 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4740 "Failed to configure context mem: rc = %d\n", rc);
4742 ctx->flags |= BNXT_CTX_FLAG_INITED;
4747 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4749 struct rte_pci_device *pci_dev = bp->pdev;
4750 char mz_name[RTE_MEMZONE_NAMESIZE];
4751 const struct rte_memzone *mz = NULL;
4752 uint32_t total_alloc_len;
4753 rte_iova_t mz_phys_addr;
4755 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4758 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4759 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4760 pci_dev->addr.bus, pci_dev->addr.devid,
4761 pci_dev->addr.function, "rx_port_stats");
4762 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4763 mz = rte_memzone_lookup(mz_name);
4765 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4766 sizeof(struct rx_port_stats_ext) + 512);
4768 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4771 RTE_MEMZONE_SIZE_HINT_ONLY |
4772 RTE_MEMZONE_IOVA_CONTIG);
4776 memset(mz->addr, 0, mz->len);
4777 mz_phys_addr = mz->iova;
4779 bp->rx_mem_zone = (const void *)mz;
4780 bp->hw_rx_port_stats = mz->addr;
4781 bp->hw_rx_port_stats_map = mz_phys_addr;
4783 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4784 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4785 pci_dev->addr.bus, pci_dev->addr.devid,
4786 pci_dev->addr.function, "tx_port_stats");
4787 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4788 mz = rte_memzone_lookup(mz_name);
4790 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4791 sizeof(struct tx_port_stats_ext) + 512);
4793 mz = rte_memzone_reserve(mz_name,
4797 RTE_MEMZONE_SIZE_HINT_ONLY |
4798 RTE_MEMZONE_IOVA_CONTIG);
4802 memset(mz->addr, 0, mz->len);
4803 mz_phys_addr = mz->iova;
4805 bp->tx_mem_zone = (const void *)mz;
4806 bp->hw_tx_port_stats = mz->addr;
4807 bp->hw_tx_port_stats_map = mz_phys_addr;
4808 bp->flags |= BNXT_FLAG_PORT_STATS;
4810 /* Display extended statistics if FW supports it */
4811 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4812 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4813 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4816 bp->hw_rx_port_stats_ext = (void *)
4817 ((uint8_t *)bp->hw_rx_port_stats +
4818 sizeof(struct rx_port_stats));
4819 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4820 sizeof(struct rx_port_stats);
4821 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4823 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4824 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4825 bp->hw_tx_port_stats_ext = (void *)
4826 ((uint8_t *)bp->hw_tx_port_stats +
4827 sizeof(struct tx_port_stats));
4828 bp->hw_tx_port_stats_ext_map =
4829 bp->hw_tx_port_stats_map +
4830 sizeof(struct tx_port_stats);
4831 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4837 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4839 struct bnxt *bp = eth_dev->data->dev_private;
4842 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4843 RTE_ETHER_ADDR_LEN *
4846 if (eth_dev->data->mac_addrs == NULL) {
4847 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4851 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4855 /* Generate a random MAC address, if none was assigned by PF */
4856 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4857 bnxt_eth_hw_addr_random(bp->mac_addr);
4859 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4860 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4861 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4863 rc = bnxt_hwrm_set_mac(bp);
4865 memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4866 RTE_ETHER_ADDR_LEN);
4870 /* Copy the permanent MAC from the FUNC_QCAPS response */
4871 memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4872 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4877 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4881 /* MAC is already configured in FW */
4882 if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4885 /* Restore the old MAC configured */
4886 rc = bnxt_hwrm_set_mac(bp);
4888 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4893 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4898 #define ALLOW_FUNC(x) \
4900 uint32_t arg = (x); \
4901 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4902 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4905 /* Forward all requests if firmware is new enough */
4906 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4907 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4908 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4909 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4911 PMD_DRV_LOG(WARNING,
4912 "Firmware too old for VF mailbox functionality\n");
4913 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4917 * The following are used for driver cleanup. If we disallow these,
4918 * VF drivers can't clean up cleanly.
4920 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4921 ALLOW_FUNC(HWRM_VNIC_FREE);
4922 ALLOW_FUNC(HWRM_RING_FREE);
4923 ALLOW_FUNC(HWRM_RING_GRP_FREE);
4924 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4925 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4926 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4927 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4928 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4932 bnxt_get_svif(uint16_t port_id, bool func_svif)
4934 struct rte_eth_dev *eth_dev;
4937 eth_dev = &rte_eth_devices[port_id];
4938 bp = eth_dev->data->dev_private;
4940 return func_svif ? bp->func_svif : bp->port_svif;
4944 bnxt_get_vnic_id(uint16_t port)
4946 struct rte_eth_dev *eth_dev;
4947 struct bnxt_vnic_info *vnic;
4950 eth_dev = &rte_eth_devices[port];
4951 bp = eth_dev->data->dev_private;
4953 vnic = BNXT_GET_DEFAULT_VNIC(bp);
4955 return vnic->fw_vnic_id;
4959 bnxt_get_fw_func_id(uint16_t port)
4961 struct rte_eth_dev *eth_dev;
4964 eth_dev = &rte_eth_devices[port];
4965 bp = eth_dev->data->dev_private;
4970 static int bnxt_init_fw(struct bnxt *bp)
4977 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
4981 rc = bnxt_hwrm_func_reset(bp);
4985 rc = bnxt_hwrm_vnic_qcaps(bp);
4989 rc = bnxt_hwrm_queue_qportcfg(bp);
4993 /* Get the MAX capabilities for this function.
4994 * This function also allocates context memory for TQM rings and
4995 * informs the firmware about this allocated backing store memory.
4997 rc = bnxt_hwrm_func_qcaps(bp);
5001 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5005 bnxt_hwrm_port_mac_qcfg(bp);
5007 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5011 /* Get the adapter error recovery support info */
5012 rc = bnxt_hwrm_error_recovery_qcfg(bp);
5014 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5016 bnxt_hwrm_port_led_qcaps(bp);
5022 bnxt_init_locks(struct bnxt *bp)
5026 err = pthread_mutex_init(&bp->flow_lock, NULL);
5028 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5032 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5034 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5038 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5042 rc = bnxt_init_fw(bp);
5046 if (!reconfig_dev) {
5047 rc = bnxt_setup_mac_addr(bp->eth_dev);
5051 rc = bnxt_restore_dflt_mac(bp);
5056 bnxt_config_vf_req_fwd(bp);
5058 rc = bnxt_hwrm_func_driver_register(bp);
5060 PMD_DRV_LOG(ERR, "Failed to register driver");
5065 if (bp->pdev->max_vfs) {
5066 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5068 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5072 rc = bnxt_hwrm_allocate_pf_only(bp);
5075 "Failed to allocate PF resources");
5081 rc = bnxt_alloc_mem(bp, reconfig_dev);
5085 rc = bnxt_setup_int(bp);
5089 rc = bnxt_request_int(bp);
5093 rc = bnxt_init_ctx_mem(bp);
5095 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5099 rc = bnxt_init_locks(bp);
5107 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5108 const char *value, void *opaque_arg)
5110 struct bnxt *bp = opaque_arg;
5111 unsigned long truflow;
5114 if (!value || !opaque_arg) {
5116 "Invalid parameter passed to truflow devargs.\n");
5120 truflow = strtoul(value, &end, 10);
5121 if (end == NULL || *end != '\0' ||
5122 (truflow == ULONG_MAX && errno == ERANGE)) {
5124 "Invalid parameter passed to truflow devargs.\n");
5128 if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5130 "Invalid value passed to truflow devargs.\n");
5134 bp->truflow = truflow;
5136 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5142 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5143 const char *value, void *opaque_arg)
5145 struct bnxt *bp = opaque_arg;
5146 unsigned long flow_xstat;
5149 if (!value || !opaque_arg) {
5151 "Invalid parameter passed to flow_xstat devarg.\n");
5155 flow_xstat = strtoul(value, &end, 10);
5156 if (end == NULL || *end != '\0' ||
5157 (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5159 "Invalid parameter passed to flow_xstat devarg.\n");
5163 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5165 "Invalid value passed to flow_xstat devarg.\n");
5169 bp->flow_xstat = flow_xstat;
5171 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5177 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5179 struct rte_kvargs *kvlist;
5181 if (devargs == NULL)
5184 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5189 * Handler for "truflow" devarg.
5190 * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1”
5192 rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5193 bnxt_parse_devarg_truflow, bp);
5196 * Handler for "flow_xstat" devarg.
5197 * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1”
5199 rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5200 bnxt_parse_devarg_flow_xstat, bp);
5202 rte_kvargs_free(kvlist);
5206 bnxt_dev_init(struct rte_eth_dev *eth_dev)
5208 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5209 static int version_printed;
5213 if (version_printed++ == 0)
5214 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5216 eth_dev->dev_ops = &bnxt_dev_ops;
5217 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5218 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5221 * For secondary processes, we don't initialise any further
5222 * as primary has already done this work.
5224 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5227 rte_eth_copy_pci_info(eth_dev, pci_dev);
5229 bp = eth_dev->data->dev_private;
5231 /* Parse dev arguments passed on when starting the DPDK application. */
5232 bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5234 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5236 if (bnxt_vf_pciid(pci_dev->id.device_id))
5237 bp->flags |= BNXT_FLAG_VF;
5239 if (bnxt_thor_device(pci_dev->id.device_id))
5240 bp->flags |= BNXT_FLAG_THOR_CHIP;
5242 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5243 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5244 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5245 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5246 bp->flags |= BNXT_FLAG_STINGRAY;
5248 rc = bnxt_init_board(eth_dev);
5251 "Failed to initialize board rc: %x\n", rc);
5255 rc = bnxt_alloc_hwrm_resources(bp);
5258 "Failed to allocate hwrm resource rc: %x\n", rc);
5261 rc = bnxt_init_resources(bp, false);
5265 rc = bnxt_alloc_stats_mem(bp);
5269 /* Pass the information to the rte_eth_dev_close() that it should also
5270 * release the private port resources.
5272 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5275 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5276 pci_dev->mem_resource[0].phys_addr,
5277 pci_dev->mem_resource[0].addr);
5282 bnxt_dev_uninit(eth_dev);
5287 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5296 ctx->dma = RTE_BAD_IOVA;
5297 ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5300 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5302 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5303 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5304 bp->rx_fc_out_tbl.ctx_id,
5308 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5309 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5310 bp->tx_fc_out_tbl.ctx_id,
5314 if (bp->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5315 bnxt_hwrm_ctx_unrgtr(bp, bp->rx_fc_in_tbl.ctx_id);
5316 bp->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5318 if (bp->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5319 bnxt_hwrm_ctx_unrgtr(bp, bp->rx_fc_out_tbl.ctx_id);
5320 bp->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5322 if (bp->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5323 bnxt_hwrm_ctx_unrgtr(bp, bp->tx_fc_in_tbl.ctx_id);
5324 bp->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5326 if (bp->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5327 bnxt_hwrm_ctx_unrgtr(bp, bp->tx_fc_out_tbl.ctx_id);
5328 bp->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5331 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5333 bnxt_unregister_fc_ctx_mem(bp);
5335 bnxt_free_ctx_mem_buf(&bp->rx_fc_in_tbl);
5336 bnxt_free_ctx_mem_buf(&bp->rx_fc_out_tbl);
5337 bnxt_free_ctx_mem_buf(&bp->tx_fc_in_tbl);
5338 bnxt_free_ctx_mem_buf(&bp->tx_fc_out_tbl);
5341 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5343 bnxt_uninit_fc_ctx_mem(bp);
5347 bnxt_uninit_locks(struct bnxt *bp)
5349 pthread_mutex_destroy(&bp->flow_lock);
5350 pthread_mutex_destroy(&bp->def_cp_lock);
5354 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5359 bnxt_free_mem(bp, reconfig_dev);
5360 bnxt_hwrm_func_buf_unrgtr(bp);
5361 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5362 bp->flags &= ~BNXT_FLAG_REGISTERED;
5363 bnxt_free_ctx_mem(bp);
5364 if (!reconfig_dev) {
5365 bnxt_free_hwrm_resources(bp);
5367 if (bp->recovery_info != NULL) {
5368 rte_free(bp->recovery_info);
5369 bp->recovery_info = NULL;
5373 bnxt_uninit_ctx_mem(bp);
5375 bnxt_uninit_locks(bp);
5376 rte_free(bp->ptp_cfg);
5382 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5384 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5387 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5389 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5390 bnxt_dev_close_op(eth_dev);
5395 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5396 struct rte_pci_device *pci_dev)
5398 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
5402 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5404 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
5405 return rte_eth_dev_pci_generic_remove(pci_dev,
5408 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5411 static struct rte_pci_driver bnxt_rte_pmd = {
5412 .id_table = bnxt_pci_id_map,
5413 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5414 .probe = bnxt_pci_probe,
5415 .remove = bnxt_pci_remove,
5419 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5421 if (strcmp(dev->device->driver->name, drv->driver.name))
5427 bool is_bnxt_supported(struct rte_eth_dev *dev)
5429 return is_device_supported(dev, &bnxt_rte_pmd);
5432 RTE_INIT(bnxt_init_log)
5434 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
5435 if (bnxt_logtype_driver >= 0)
5436 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
5439 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5440 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5441 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");