1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
20 #include "bnxt_ring.h"
23 #include "bnxt_stats.h"
26 #include "bnxt_vnic.h"
27 #include "hsi_struct_def_dpdk.h"
28 #include "bnxt_nvm_defs.h"
30 #define DRV_MODULE_NAME "bnxt"
31 static const char bnxt_version[] =
32 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
33 int bnxt_logtype_driver;
36 * The set of PCI devices this driver supports
38 static const struct rte_pci_id bnxt_pci_id_map[] = {
39 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
40 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
41 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
42 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
43 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
45 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
47 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
92 { .vendor_id = 0, /* sentinel */ },
95 #define BNXT_ETH_RSS_SUPPORT ( \
97 ETH_RSS_NONFRAG_IPV4_TCP | \
98 ETH_RSS_NONFRAG_IPV4_UDP | \
100 ETH_RSS_NONFRAG_IPV6_TCP | \
101 ETH_RSS_NONFRAG_IPV6_UDP)
103 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
104 DEV_TX_OFFLOAD_IPV4_CKSUM | \
105 DEV_TX_OFFLOAD_TCP_CKSUM | \
106 DEV_TX_OFFLOAD_UDP_CKSUM | \
107 DEV_TX_OFFLOAD_TCP_TSO | \
108 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
109 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
110 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
111 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
112 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
113 DEV_TX_OFFLOAD_QINQ_INSERT | \
114 DEV_TX_OFFLOAD_MULTI_SEGS)
116 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
117 DEV_RX_OFFLOAD_VLAN_STRIP | \
118 DEV_RX_OFFLOAD_IPV4_CKSUM | \
119 DEV_RX_OFFLOAD_UDP_CKSUM | \
120 DEV_RX_OFFLOAD_TCP_CKSUM | \
121 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
122 DEV_RX_OFFLOAD_JUMBO_FRAME | \
123 DEV_RX_OFFLOAD_KEEP_CRC | \
124 DEV_RX_OFFLOAD_VLAN_EXTEND | \
125 DEV_RX_OFFLOAD_TCP_LRO | \
126 DEV_RX_OFFLOAD_SCATTER | \
127 DEV_RX_OFFLOAD_RSS_HASH)
129 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
130 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
131 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
132 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
133 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
134 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
136 int is_bnxt_in_error(struct bnxt *bp)
138 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
140 if (bp->flags & BNXT_FLAG_FW_RESET)
146 /***********************/
149 * High level utility functions
152 uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
154 if (!BNXT_CHIP_THOR(bp))
157 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
158 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
159 BNXT_RSS_ENTRIES_PER_CTX_THOR;
162 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
164 if (!BNXT_CHIP_THOR(bp))
165 return HW_HASH_INDEX_SIZE;
167 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
170 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
172 bnxt_free_filter_mem(bp);
173 bnxt_free_vnic_attributes(bp);
174 bnxt_free_vnic_mem(bp);
176 /* tx/rx rings are configured as part of *_queue_setup callbacks.
177 * If the number of rings change across fw update,
178 * we don't have much choice except to warn the user.
182 bnxt_free_tx_rings(bp);
183 bnxt_free_rx_rings(bp);
185 bnxt_free_async_cp_ring(bp);
186 bnxt_free_rxtx_nq_ring(bp);
188 rte_free(bp->grp_info);
192 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
196 rc = bnxt_alloc_ring_grps(bp);
200 rc = bnxt_alloc_async_ring_struct(bp);
204 rc = bnxt_alloc_vnic_mem(bp);
208 rc = bnxt_alloc_vnic_attributes(bp);
212 rc = bnxt_alloc_filter_mem(bp);
216 rc = bnxt_alloc_async_cp_ring(bp);
220 rc = bnxt_alloc_rxtx_nq_ring(bp);
227 bnxt_free_mem(bp, reconfig);
231 static int bnxt_init_chip(struct bnxt *bp)
233 struct bnxt_rx_queue *rxq;
234 struct rte_eth_link new;
235 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
236 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
237 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
238 uint64_t rx_offloads = dev_conf->rxmode.offloads;
239 uint32_t intr_vector = 0;
240 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
241 uint32_t vec = BNXT_MISC_VEC_ID;
245 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
246 bp->eth_dev->data->dev_conf.rxmode.offloads |=
247 DEV_RX_OFFLOAD_JUMBO_FRAME;
248 bp->flags |= BNXT_FLAG_JUMBO;
250 bp->eth_dev->data->dev_conf.rxmode.offloads &=
251 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
252 bp->flags &= ~BNXT_FLAG_JUMBO;
255 /* THOR does not support ring groups.
256 * But we will use the array to save RSS context IDs.
258 if (BNXT_CHIP_THOR(bp))
259 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
261 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
263 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
267 rc = bnxt_alloc_hwrm_rings(bp);
269 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
273 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
275 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
279 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
282 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
283 if (bp->rx_cos_queue[i].id != 0xff) {
284 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
288 "Num pools more than FW profile\n");
292 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
298 rc = bnxt_mq_rx_configure(bp);
300 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
304 /* VNIC configuration */
305 for (i = 0; i < bp->nr_vnics; i++) {
306 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
307 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
309 rc = bnxt_vnic_grp_alloc(bp, vnic);
313 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
314 i, vnic, vnic->fw_grp_ids);
316 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
318 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
323 /* Alloc RSS context only if RSS mode is enabled */
324 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
325 int j, nr_ctxs = bnxt_rss_ctxts(bp);
328 for (j = 0; j < nr_ctxs; j++) {
329 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
335 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
339 vnic->num_lb_ctxts = nr_ctxs;
343 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
344 * setting is not available at this time, it will not be
345 * configured correctly in the CFA.
347 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
348 vnic->vlan_strip = true;
350 vnic->vlan_strip = false;
352 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
354 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
359 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
362 "HWRM vnic %d filter failure rc: %x\n",
367 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
368 rxq = bp->eth_dev->data->rx_queues[j];
371 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
372 j, rxq->vnic, rxq->vnic->fw_grp_ids);
374 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
375 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
378 rc = bnxt_vnic_rss_configure(bp, vnic);
381 "HWRM vnic set RSS failure rc: %x\n", rc);
385 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
387 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
388 DEV_RX_OFFLOAD_TCP_LRO)
389 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
391 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
393 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
396 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
400 /* check and configure queue intr-vector mapping */
401 if ((rte_intr_cap_multiple(intr_handle) ||
402 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
403 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
404 intr_vector = bp->eth_dev->data->nb_rx_queues;
405 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
406 if (intr_vector > bp->rx_cp_nr_rings) {
407 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
411 rc = rte_intr_efd_enable(intr_handle, intr_vector);
416 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
417 intr_handle->intr_vec =
418 rte_zmalloc("intr_vec",
419 bp->eth_dev->data->nb_rx_queues *
421 if (intr_handle->intr_vec == NULL) {
422 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
423 " intr_vec", bp->eth_dev->data->nb_rx_queues);
427 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
428 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
429 intr_handle->intr_vec, intr_handle->nb_efd,
430 intr_handle->max_intr);
431 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
433 intr_handle->intr_vec[queue_id] =
434 vec + BNXT_RX_VEC_START;
435 if (vec < base + intr_handle->nb_efd - 1)
440 /* enable uio/vfio intr/eventfd mapping */
441 rc = rte_intr_enable(intr_handle);
442 #ifndef RTE_EXEC_ENV_FREEBSD
443 /* In FreeBSD OS, nic_uio driver does not support interrupts */
448 rc = bnxt_get_hwrm_link_config(bp, &new);
450 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
454 if (!bp->link_info.link_up) {
455 rc = bnxt_set_hwrm_link_config(bp, true);
458 "HWRM link config failure rc: %x\n", rc);
462 bnxt_print_link_info(bp->eth_dev);
464 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
466 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
471 rte_free(intr_handle->intr_vec);
473 rte_intr_efd_disable(intr_handle);
475 /* Some of the error status returned by FW may not be from errno.h */
482 static int bnxt_shutdown_nic(struct bnxt *bp)
484 bnxt_free_all_hwrm_resources(bp);
485 bnxt_free_all_filters(bp);
486 bnxt_free_all_vnics(bp);
491 * Device configuration and status function
494 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
495 struct rte_eth_dev_info *dev_info)
497 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
498 struct bnxt *bp = eth_dev->data->dev_private;
499 uint16_t max_vnics, i, j, vpool, vrxq;
500 unsigned int max_rx_rings;
503 rc = is_bnxt_in_error(bp);
508 dev_info->max_mac_addrs = bp->max_l2_ctx;
509 dev_info->max_hash_mac_addrs = 0;
511 /* PF/VF specifics */
513 dev_info->max_vfs = pdev->max_vfs;
515 max_rx_rings = BNXT_MAX_RINGS(bp);
516 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
517 dev_info->max_rx_queues = max_rx_rings;
518 dev_info->max_tx_queues = max_rx_rings;
519 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
520 dev_info->hash_key_size = 40;
521 max_vnics = bp->max_vnics;
524 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
525 dev_info->max_mtu = BNXT_MAX_MTU;
527 /* Fast path specifics */
528 dev_info->min_rx_bufsize = 1;
529 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
531 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
532 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
533 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
534 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
535 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
538 dev_info->default_rxconf = (struct rte_eth_rxconf) {
544 .rx_free_thresh = 32,
545 /* If no descriptors available, pkts are dropped by default */
549 dev_info->default_txconf = (struct rte_eth_txconf) {
555 .tx_free_thresh = 32,
558 eth_dev->data->dev_conf.intr_conf.lsc = 1;
560 eth_dev->data->dev_conf.intr_conf.rxq = 1;
561 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
562 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
563 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
564 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
569 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
570 * need further investigation.
574 vpool = 64; /* ETH_64_POOLS */
575 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
576 for (i = 0; i < 4; vpool >>= 1, i++) {
577 if (max_vnics > vpool) {
578 for (j = 0; j < 5; vrxq >>= 1, j++) {
579 if (dev_info->max_rx_queues > vrxq) {
585 /* Not enough resources to support VMDq */
589 /* Not enough resources to support VMDq */
593 dev_info->max_vmdq_pools = vpool;
594 dev_info->vmdq_queue_num = vrxq;
596 dev_info->vmdq_pool_base = 0;
597 dev_info->vmdq_queue_base = 0;
602 /* Configure the device based on the configuration provided */
603 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
605 struct bnxt *bp = eth_dev->data->dev_private;
606 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
609 bp->rx_queues = (void *)eth_dev->data->rx_queues;
610 bp->tx_queues = (void *)eth_dev->data->tx_queues;
611 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
612 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
614 rc = is_bnxt_in_error(bp);
618 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
619 rc = bnxt_hwrm_check_vf_rings(bp);
621 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
625 /* If a resource has already been allocated - in this case
626 * it is the async completion ring, free it. Reallocate it after
627 * resource reservation. This will ensure the resource counts
628 * are calculated correctly.
631 pthread_mutex_lock(&bp->def_cp_lock);
633 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
634 bnxt_disable_int(bp);
635 bnxt_free_cp_ring(bp, bp->async_cp_ring);
638 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
640 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
641 pthread_mutex_unlock(&bp->def_cp_lock);
645 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
646 rc = bnxt_alloc_async_cp_ring(bp);
648 pthread_mutex_unlock(&bp->def_cp_lock);
654 pthread_mutex_unlock(&bp->def_cp_lock);
656 /* legacy driver needs to get updated values */
657 rc = bnxt_hwrm_func_qcaps(bp);
659 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
664 /* Inherit new configurations */
665 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
666 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
667 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
668 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
669 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
673 if (BNXT_HAS_RING_GRPS(bp) &&
674 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
677 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
678 bp->max_vnics < eth_dev->data->nb_rx_queues)
681 bp->rx_cp_nr_rings = bp->rx_nr_rings;
682 bp->tx_cp_nr_rings = bp->tx_nr_rings;
684 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
685 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
686 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
688 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
690 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
691 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
693 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
699 "Insufficient resources to support requested config\n");
701 "Num Queues Requested: Tx %d, Rx %d\n",
702 eth_dev->data->nb_tx_queues,
703 eth_dev->data->nb_rx_queues);
705 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
706 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
707 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
711 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
713 struct rte_eth_link *link = ð_dev->data->dev_link;
715 if (link->link_status)
716 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
717 eth_dev->data->port_id,
718 (uint32_t)link->link_speed,
719 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
720 ("full-duplex") : ("half-duplex\n"));
722 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
723 eth_dev->data->port_id);
727 * Determine whether the current configuration requires support for scattered
728 * receive; return 1 if scattered receive is required and 0 if not.
730 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
735 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
738 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
739 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
741 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
742 RTE_PKTMBUF_HEADROOM);
743 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
749 static eth_rx_burst_t
750 bnxt_receive_function(struct rte_eth_dev *eth_dev)
752 struct bnxt *bp = eth_dev->data->dev_private;
755 #ifndef RTE_LIBRTE_IEEE1588
757 * Vector mode receive can be enabled only if scatter rx is not
758 * in use and rx offloads are limited to VLAN stripping and
761 if (!eth_dev->data->scattered_rx &&
762 !(eth_dev->data->dev_conf.rxmode.offloads &
763 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
764 DEV_RX_OFFLOAD_KEEP_CRC |
765 DEV_RX_OFFLOAD_JUMBO_FRAME |
766 DEV_RX_OFFLOAD_IPV4_CKSUM |
767 DEV_RX_OFFLOAD_UDP_CKSUM |
768 DEV_RX_OFFLOAD_TCP_CKSUM |
769 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
770 DEV_RX_OFFLOAD_RSS_HASH |
771 DEV_RX_OFFLOAD_VLAN_FILTER))) {
772 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
773 eth_dev->data->port_id);
774 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
775 return bnxt_recv_pkts_vec;
777 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
778 eth_dev->data->port_id);
780 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
781 eth_dev->data->port_id,
782 eth_dev->data->scattered_rx,
783 eth_dev->data->dev_conf.rxmode.offloads);
786 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
787 return bnxt_recv_pkts;
790 static eth_tx_burst_t
791 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
794 #ifndef RTE_LIBRTE_IEEE1588
796 * Vector mode transmit can be enabled only if not using scatter rx
799 if (!eth_dev->data->scattered_rx &&
800 !eth_dev->data->dev_conf.txmode.offloads) {
801 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
802 eth_dev->data->port_id);
803 return bnxt_xmit_pkts_vec;
805 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
806 eth_dev->data->port_id);
808 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
809 eth_dev->data->port_id,
810 eth_dev->data->scattered_rx,
811 eth_dev->data->dev_conf.txmode.offloads);
814 return bnxt_xmit_pkts;
817 static int bnxt_handle_if_change_status(struct bnxt *bp)
821 /* Since fw has undergone a reset and lost all contexts,
822 * set fatal flag to not issue hwrm during cleanup
824 bp->flags |= BNXT_FLAG_FATAL_ERROR;
825 bnxt_uninit_resources(bp, true);
827 /* clear fatal flag so that re-init happens */
828 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
829 rc = bnxt_init_resources(bp, true);
831 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
836 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
838 struct bnxt *bp = eth_dev->data->dev_private;
839 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
843 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
844 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
848 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
850 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
851 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
854 rc = bnxt_hwrm_if_change(bp, 1);
856 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
857 rc = bnxt_handle_if_change_status(bp);
864 rc = bnxt_init_chip(bp);
868 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
870 bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
872 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
873 vlan_mask |= ETH_VLAN_FILTER_MASK;
874 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
875 vlan_mask |= ETH_VLAN_STRIP_MASK;
876 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
880 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
881 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
883 bp->flags |= BNXT_FLAG_INIT_DONE;
884 eth_dev->data->dev_started = 1;
886 pthread_mutex_lock(&bp->def_cp_lock);
887 bnxt_schedule_fw_health_check(bp);
888 pthread_mutex_unlock(&bp->def_cp_lock);
892 bnxt_hwrm_if_change(bp, 0);
893 bnxt_shutdown_nic(bp);
894 bnxt_free_tx_mbufs(bp);
895 bnxt_free_rx_mbufs(bp);
899 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
901 struct bnxt *bp = eth_dev->data->dev_private;
904 if (!bp->link_info.link_up)
905 rc = bnxt_set_hwrm_link_config(bp, true);
907 eth_dev->data->dev_link.link_status = 1;
909 bnxt_print_link_info(eth_dev);
913 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
915 struct bnxt *bp = eth_dev->data->dev_private;
917 eth_dev->data->dev_link.link_status = 0;
918 bnxt_set_hwrm_link_config(bp, false);
919 bp->link_info.link_up = 0;
924 /* Unload the driver, release resources */
925 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
927 struct bnxt *bp = eth_dev->data->dev_private;
928 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
929 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
931 eth_dev->data->dev_started = 0;
932 /* Prevent crashes when queues are still in use */
933 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
934 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
936 bnxt_disable_int(bp);
938 /* disable uio/vfio intr/eventfd mapping */
939 rte_intr_disable(intr_handle);
941 bnxt_cancel_fw_health_check(bp);
943 bp->flags &= ~BNXT_FLAG_INIT_DONE;
944 if (bp->eth_dev->data->dev_started) {
945 /* TBD: STOP HW queues DMA */
946 eth_dev->data->dev_link.link_status = 0;
948 bnxt_dev_set_link_down_op(eth_dev);
950 /* Wait for link to be reset and the async notification to process.
951 * During reset recovery, there is no need to wait
953 if (!is_bnxt_in_error(bp))
954 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
956 /* Clean queue intr-vector mapping */
957 rte_intr_efd_disable(intr_handle);
958 if (intr_handle->intr_vec != NULL) {
959 rte_free(intr_handle->intr_vec);
960 intr_handle->intr_vec = NULL;
963 bnxt_hwrm_port_clr_stats(bp);
964 bnxt_free_tx_mbufs(bp);
965 bnxt_free_rx_mbufs(bp);
966 /* Process any remaining notifications in default completion queue */
967 bnxt_int_handler(eth_dev);
968 bnxt_shutdown_nic(bp);
969 bnxt_hwrm_if_change(bp, 0);
970 memset(bp->mark_table, 0, BNXT_MARK_TABLE_SZ);
971 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
976 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
978 struct bnxt *bp = eth_dev->data->dev_private;
980 if (bp->dev_stopped == 0)
981 bnxt_dev_stop_op(eth_dev);
983 if (eth_dev->data->mac_addrs != NULL) {
984 rte_free(eth_dev->data->mac_addrs);
985 eth_dev->data->mac_addrs = NULL;
987 if (bp->grp_info != NULL) {
988 rte_free(bp->grp_info);
992 rte_free(bp->mark_table);
993 bp->mark_table = NULL;
995 bnxt_dev_uninit(eth_dev);
998 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1001 struct bnxt *bp = eth_dev->data->dev_private;
1002 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1003 struct bnxt_vnic_info *vnic;
1004 struct bnxt_filter_info *filter, *temp_filter;
1007 if (is_bnxt_in_error(bp))
1011 * Loop through all VNICs from the specified filter flow pools to
1012 * remove the corresponding MAC addr filter
1014 for (i = 0; i < bp->nr_vnics; i++) {
1015 if (!(pool_mask & (1ULL << i)))
1018 vnic = &bp->vnic_info[i];
1019 filter = STAILQ_FIRST(&vnic->filter);
1021 temp_filter = STAILQ_NEXT(filter, next);
1022 if (filter->mac_index == index) {
1023 STAILQ_REMOVE(&vnic->filter, filter,
1024 bnxt_filter_info, next);
1025 bnxt_hwrm_clear_l2_filter(bp, filter);
1026 bnxt_free_filter(bp, filter);
1028 filter = temp_filter;
1033 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1034 struct rte_ether_addr *mac_addr, uint32_t index,
1037 struct bnxt_filter_info *filter;
1040 /* Attach requested MAC address to the new l2_filter */
1041 STAILQ_FOREACH(filter, &vnic->filter, next) {
1042 if (filter->mac_index == index) {
1044 "MAC addr already existed for pool %d\n",
1050 filter = bnxt_alloc_filter(bp);
1052 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1056 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1057 * if the MAC that's been programmed now is a different one, then,
1058 * copy that addr to filter->l2_addr
1061 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1062 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1064 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1066 filter->mac_index = index;
1067 if (filter->mac_index == 0)
1068 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1070 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1072 bnxt_free_filter(bp, filter);
1078 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1079 struct rte_ether_addr *mac_addr,
1080 uint32_t index, uint32_t pool)
1082 struct bnxt *bp = eth_dev->data->dev_private;
1083 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1086 rc = is_bnxt_in_error(bp);
1090 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1091 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1096 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1100 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1105 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1106 bool exp_link_status)
1109 struct bnxt *bp = eth_dev->data->dev_private;
1110 struct rte_eth_link new;
1111 int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1112 BNXT_LINK_DOWN_WAIT_CNT;
1114 rc = is_bnxt_in_error(bp);
1118 memset(&new, 0, sizeof(new));
1120 /* Retrieve link info from hardware */
1121 rc = bnxt_get_hwrm_link_config(bp, &new);
1123 new.link_speed = ETH_LINK_SPEED_100M;
1124 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1126 "Failed to retrieve link rc = 0x%x!\n", rc);
1130 if (!wait_to_complete || new.link_status == exp_link_status)
1133 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1137 /* Timed out or success */
1138 if (new.link_status != eth_dev->data->dev_link.link_status ||
1139 new.link_speed != eth_dev->data->dev_link.link_speed) {
1140 rte_eth_linkstatus_set(eth_dev, &new);
1142 _rte_eth_dev_callback_process(eth_dev,
1143 RTE_ETH_EVENT_INTR_LSC,
1146 bnxt_print_link_info(eth_dev);
1152 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1153 int wait_to_complete)
1155 return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1158 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1160 struct bnxt *bp = eth_dev->data->dev_private;
1161 struct bnxt_vnic_info *vnic;
1165 rc = is_bnxt_in_error(bp);
1169 if (bp->vnic_info == NULL)
1172 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1174 old_flags = vnic->flags;
1175 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1176 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1178 vnic->flags = old_flags;
1183 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1185 struct bnxt *bp = eth_dev->data->dev_private;
1186 struct bnxt_vnic_info *vnic;
1190 rc = is_bnxt_in_error(bp);
1194 if (bp->vnic_info == NULL)
1197 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1199 old_flags = vnic->flags;
1200 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1201 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1203 vnic->flags = old_flags;
1208 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1210 struct bnxt *bp = eth_dev->data->dev_private;
1211 struct bnxt_vnic_info *vnic;
1215 rc = is_bnxt_in_error(bp);
1219 if (bp->vnic_info == NULL)
1222 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1224 old_flags = vnic->flags;
1225 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1226 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1228 vnic->flags = old_flags;
1233 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1235 struct bnxt *bp = eth_dev->data->dev_private;
1236 struct bnxt_vnic_info *vnic;
1240 rc = is_bnxt_in_error(bp);
1244 if (bp->vnic_info == NULL)
1247 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1249 old_flags = vnic->flags;
1250 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1251 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1253 vnic->flags = old_flags;
1258 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1259 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1261 if (qid >= bp->rx_nr_rings)
1264 return bp->eth_dev->data->rx_queues[qid];
1267 /* Return rxq corresponding to a given rss table ring/group ID. */
1268 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1270 struct bnxt_rx_queue *rxq;
1273 if (!BNXT_HAS_RING_GRPS(bp)) {
1274 for (i = 0; i < bp->rx_nr_rings; i++) {
1275 rxq = bp->eth_dev->data->rx_queues[i];
1276 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1280 for (i = 0; i < bp->rx_nr_rings; i++) {
1281 if (bp->grp_info[i].fw_grp_id == fwr)
1286 return INVALID_HW_RING_ID;
1289 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1290 struct rte_eth_rss_reta_entry64 *reta_conf,
1293 struct bnxt *bp = eth_dev->data->dev_private;
1294 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1295 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1296 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1300 rc = is_bnxt_in_error(bp);
1304 if (!vnic->rss_table)
1307 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1310 if (reta_size != tbl_size) {
1311 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1312 "(%d) must equal the size supported by the hardware "
1313 "(%d)\n", reta_size, tbl_size);
1317 for (i = 0; i < reta_size; i++) {
1318 struct bnxt_rx_queue *rxq;
1320 idx = i / RTE_RETA_GROUP_SIZE;
1321 sft = i % RTE_RETA_GROUP_SIZE;
1323 if (!(reta_conf[idx].mask & (1ULL << sft)))
1326 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1328 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1332 if (BNXT_CHIP_THOR(bp)) {
1333 vnic->rss_table[i * 2] =
1334 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1335 vnic->rss_table[i * 2 + 1] =
1336 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1338 vnic->rss_table[i] =
1339 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1343 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1347 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1348 struct rte_eth_rss_reta_entry64 *reta_conf,
1351 struct bnxt *bp = eth_dev->data->dev_private;
1352 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1353 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1354 uint16_t idx, sft, i;
1357 rc = is_bnxt_in_error(bp);
1361 /* Retrieve from the default VNIC */
1364 if (!vnic->rss_table)
1367 if (reta_size != tbl_size) {
1368 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1369 "(%d) must equal the size supported by the hardware "
1370 "(%d)\n", reta_size, tbl_size);
1374 for (idx = 0, i = 0; i < reta_size; i++) {
1375 idx = i / RTE_RETA_GROUP_SIZE;
1376 sft = i % RTE_RETA_GROUP_SIZE;
1378 if (reta_conf[idx].mask & (1ULL << sft)) {
1381 if (BNXT_CHIP_THOR(bp))
1382 qid = bnxt_rss_to_qid(bp,
1383 vnic->rss_table[i * 2]);
1385 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1387 if (qid == INVALID_HW_RING_ID) {
1388 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1391 reta_conf[idx].reta[sft] = qid;
1398 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1399 struct rte_eth_rss_conf *rss_conf)
1401 struct bnxt *bp = eth_dev->data->dev_private;
1402 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1403 struct bnxt_vnic_info *vnic;
1406 rc = is_bnxt_in_error(bp);
1411 * If RSS enablement were different than dev_configure,
1412 * then return -EINVAL
1414 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1415 if (!rss_conf->rss_hf)
1416 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1418 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1422 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1423 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1425 /* Update the default RSS VNIC(s) */
1426 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1427 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1430 * If hashkey is not specified, use the previously configured
1433 if (!rss_conf->rss_key)
1436 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1438 "Invalid hashkey length, should be 16 bytes\n");
1441 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1444 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1448 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1449 struct rte_eth_rss_conf *rss_conf)
1451 struct bnxt *bp = eth_dev->data->dev_private;
1452 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1454 uint32_t hash_types;
1456 rc = is_bnxt_in_error(bp);
1460 /* RSS configuration is the same for all VNICs */
1461 if (vnic && vnic->rss_hash_key) {
1462 if (rss_conf->rss_key) {
1463 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1464 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1465 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1468 hash_types = vnic->hash_type;
1469 rss_conf->rss_hf = 0;
1470 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1471 rss_conf->rss_hf |= ETH_RSS_IPV4;
1472 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1474 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1475 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1477 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1479 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1480 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1482 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1484 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1485 rss_conf->rss_hf |= ETH_RSS_IPV6;
1486 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1488 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1489 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1491 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1493 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1494 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1496 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1500 "Unknwon RSS config from firmware (%08x), RSS disabled",
1505 rss_conf->rss_hf = 0;
1510 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1511 struct rte_eth_fc_conf *fc_conf)
1513 struct bnxt *bp = dev->data->dev_private;
1514 struct rte_eth_link link_info;
1517 rc = is_bnxt_in_error(bp);
1521 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1525 memset(fc_conf, 0, sizeof(*fc_conf));
1526 if (bp->link_info.auto_pause)
1527 fc_conf->autoneg = 1;
1528 switch (bp->link_info.pause) {
1530 fc_conf->mode = RTE_FC_NONE;
1532 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1533 fc_conf->mode = RTE_FC_TX_PAUSE;
1535 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1536 fc_conf->mode = RTE_FC_RX_PAUSE;
1538 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1539 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1540 fc_conf->mode = RTE_FC_FULL;
1546 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1547 struct rte_eth_fc_conf *fc_conf)
1549 struct bnxt *bp = dev->data->dev_private;
1552 rc = is_bnxt_in_error(bp);
1556 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1557 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1561 switch (fc_conf->mode) {
1563 bp->link_info.auto_pause = 0;
1564 bp->link_info.force_pause = 0;
1566 case RTE_FC_RX_PAUSE:
1567 if (fc_conf->autoneg) {
1568 bp->link_info.auto_pause =
1569 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1570 bp->link_info.force_pause = 0;
1572 bp->link_info.auto_pause = 0;
1573 bp->link_info.force_pause =
1574 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1577 case RTE_FC_TX_PAUSE:
1578 if (fc_conf->autoneg) {
1579 bp->link_info.auto_pause =
1580 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1581 bp->link_info.force_pause = 0;
1583 bp->link_info.auto_pause = 0;
1584 bp->link_info.force_pause =
1585 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1589 if (fc_conf->autoneg) {
1590 bp->link_info.auto_pause =
1591 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1592 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1593 bp->link_info.force_pause = 0;
1595 bp->link_info.auto_pause = 0;
1596 bp->link_info.force_pause =
1597 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1598 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1602 return bnxt_set_hwrm_link_config(bp, true);
1605 /* Add UDP tunneling port */
1607 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1608 struct rte_eth_udp_tunnel *udp_tunnel)
1610 struct bnxt *bp = eth_dev->data->dev_private;
1611 uint16_t tunnel_type = 0;
1614 rc = is_bnxt_in_error(bp);
1618 switch (udp_tunnel->prot_type) {
1619 case RTE_TUNNEL_TYPE_VXLAN:
1620 if (bp->vxlan_port_cnt) {
1621 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1622 udp_tunnel->udp_port);
1623 if (bp->vxlan_port != udp_tunnel->udp_port) {
1624 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1627 bp->vxlan_port_cnt++;
1631 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1632 bp->vxlan_port_cnt++;
1634 case RTE_TUNNEL_TYPE_GENEVE:
1635 if (bp->geneve_port_cnt) {
1636 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1637 udp_tunnel->udp_port);
1638 if (bp->geneve_port != udp_tunnel->udp_port) {
1639 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1642 bp->geneve_port_cnt++;
1646 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1647 bp->geneve_port_cnt++;
1650 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1653 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1659 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1660 struct rte_eth_udp_tunnel *udp_tunnel)
1662 struct bnxt *bp = eth_dev->data->dev_private;
1663 uint16_t tunnel_type = 0;
1667 rc = is_bnxt_in_error(bp);
1671 switch (udp_tunnel->prot_type) {
1672 case RTE_TUNNEL_TYPE_VXLAN:
1673 if (!bp->vxlan_port_cnt) {
1674 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1677 if (bp->vxlan_port != udp_tunnel->udp_port) {
1678 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1679 udp_tunnel->udp_port, bp->vxlan_port);
1682 if (--bp->vxlan_port_cnt)
1686 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1687 port = bp->vxlan_fw_dst_port_id;
1689 case RTE_TUNNEL_TYPE_GENEVE:
1690 if (!bp->geneve_port_cnt) {
1691 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1694 if (bp->geneve_port != udp_tunnel->udp_port) {
1695 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1696 udp_tunnel->udp_port, bp->geneve_port);
1699 if (--bp->geneve_port_cnt)
1703 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1704 port = bp->geneve_fw_dst_port_id;
1707 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1711 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1714 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1717 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1718 bp->geneve_port = 0;
1723 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1725 struct bnxt_filter_info *filter;
1726 struct bnxt_vnic_info *vnic;
1728 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1730 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1731 filter = STAILQ_FIRST(&vnic->filter);
1733 /* Search for this matching MAC+VLAN filter */
1734 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
1735 /* Delete the filter */
1736 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1739 STAILQ_REMOVE(&vnic->filter, filter,
1740 bnxt_filter_info, next);
1741 bnxt_free_filter(bp, filter);
1743 "Deleted vlan filter for %d\n",
1747 filter = STAILQ_NEXT(filter, next);
1752 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1754 struct bnxt_filter_info *filter;
1755 struct bnxt_vnic_info *vnic;
1757 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1758 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1759 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1761 /* Implementation notes on the use of VNIC in this command:
1763 * By default, these filters belong to default vnic for the function.
1764 * Once these filters are set up, only destination VNIC can be modified.
1765 * If the destination VNIC is not specified in this command,
1766 * then the HWRM shall only create an l2 context id.
1769 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1770 filter = STAILQ_FIRST(&vnic->filter);
1771 /* Check if the VLAN has already been added */
1773 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
1776 filter = STAILQ_NEXT(filter, next);
1779 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1780 * command to create MAC+VLAN filter with the right flags, enables set.
1782 filter = bnxt_alloc_filter(bp);
1785 "MAC/VLAN filter alloc failed\n");
1788 /* MAC + VLAN ID filter */
1789 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1790 * untagged packets are received
1792 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
1793 * packets and only the programmed vlan's packets are received
1795 filter->l2_ivlan = vlan_id;
1796 filter->l2_ivlan_mask = 0x0FFF;
1797 filter->enables |= en;
1798 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1800 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1802 /* Free the newly allocated filter as we were
1803 * not able to create the filter in hardware.
1805 bnxt_free_filter(bp, filter);
1809 filter->mac_index = 0;
1810 /* Add this new filter to the list */
1812 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1814 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1817 "Added Vlan filter for %d\n", vlan_id);
1821 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1822 uint16_t vlan_id, int on)
1824 struct bnxt *bp = eth_dev->data->dev_private;
1827 rc = is_bnxt_in_error(bp);
1831 /* These operations apply to ALL existing MAC/VLAN filters */
1833 return bnxt_add_vlan_filter(bp, vlan_id);
1835 return bnxt_del_vlan_filter(bp, vlan_id);
1838 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
1839 struct bnxt_vnic_info *vnic)
1841 struct bnxt_filter_info *filter;
1844 filter = STAILQ_FIRST(&vnic->filter);
1846 if (filter->mac_index == 0 &&
1847 !memcmp(filter->l2_addr, bp->mac_addr,
1848 RTE_ETHER_ADDR_LEN)) {
1849 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1851 STAILQ_REMOVE(&vnic->filter, filter,
1852 bnxt_filter_info, next);
1853 bnxt_free_filter(bp, filter);
1857 filter = STAILQ_NEXT(filter, next);
1863 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1865 struct bnxt *bp = dev->data->dev_private;
1866 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1867 struct bnxt_vnic_info *vnic;
1871 rc = is_bnxt_in_error(bp);
1875 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1876 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1877 /* Remove any VLAN filters programmed */
1878 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1879 bnxt_del_vlan_filter(bp, i);
1881 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1885 /* Default filter will allow packets that match the
1886 * dest mac. So, it has to be deleted, otherwise, we
1887 * will endup receiving vlan packets for which the
1888 * filter is not programmed, when hw-vlan-filter
1889 * configuration is ON
1891 bnxt_del_dflt_mac_filter(bp, vnic);
1892 /* This filter will allow only untagged packets */
1893 bnxt_add_vlan_filter(bp, 0);
1895 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1896 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1898 if (mask & ETH_VLAN_STRIP_MASK) {
1899 /* Enable or disable VLAN stripping */
1900 for (i = 0; i < bp->nr_vnics; i++) {
1901 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1902 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1903 vnic->vlan_strip = true;
1905 vnic->vlan_strip = false;
1906 bnxt_hwrm_vnic_cfg(bp, vnic);
1908 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1909 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1912 if (mask & ETH_VLAN_EXTEND_MASK) {
1913 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1914 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
1916 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
1923 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
1926 struct bnxt *bp = dev->data->dev_private;
1927 int qinq = dev->data->dev_conf.rxmode.offloads &
1928 DEV_RX_OFFLOAD_VLAN_EXTEND;
1930 if (vlan_type != ETH_VLAN_TYPE_INNER &&
1931 vlan_type != ETH_VLAN_TYPE_OUTER) {
1933 "Unsupported vlan type.");
1938 "QinQ not enabled. Needs to be ON as we can "
1939 "accelerate only outer vlan\n");
1943 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
1945 case RTE_ETHER_TYPE_QINQ:
1947 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
1949 case RTE_ETHER_TYPE_VLAN:
1951 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
1955 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
1959 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
1963 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
1966 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
1969 bp->outer_tpid_bd |= tpid;
1970 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
1971 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
1973 "Can accelerate only outer vlan in QinQ\n");
1981 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1982 struct rte_ether_addr *addr)
1984 struct bnxt *bp = dev->data->dev_private;
1985 /* Default Filter is tied to VNIC 0 */
1986 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1987 struct bnxt_filter_info *filter;
1990 rc = is_bnxt_in_error(bp);
1994 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1997 if (rte_is_zero_ether_addr(addr))
2000 STAILQ_FOREACH(filter, &vnic->filter, next) {
2001 /* Default Filter is at Index 0 */
2002 if (filter->mac_index != 0)
2005 memcpy(filter->l2_addr, addr, RTE_ETHER_ADDR_LEN);
2006 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
2007 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX |
2008 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2010 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
2011 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
2013 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2015 memcpy(filter->l2_addr, bp->mac_addr,
2016 RTE_ETHER_ADDR_LEN);
2020 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2021 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2029 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2030 struct rte_ether_addr *mc_addr_set,
2031 uint32_t nb_mc_addr)
2033 struct bnxt *bp = eth_dev->data->dev_private;
2034 char *mc_addr_list = (char *)mc_addr_set;
2035 struct bnxt_vnic_info *vnic;
2036 uint32_t off = 0, i = 0;
2039 rc = is_bnxt_in_error(bp);
2043 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2045 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2046 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2050 /* TODO Check for Duplicate mcast addresses */
2051 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2052 for (i = 0; i < nb_mc_addr; i++) {
2053 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2054 RTE_ETHER_ADDR_LEN);
2055 off += RTE_ETHER_ADDR_LEN;
2058 vnic->mc_addr_cnt = i;
2059 if (vnic->mc_addr_cnt)
2060 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2062 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2065 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2069 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2071 struct bnxt *bp = dev->data->dev_private;
2072 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2073 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2074 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2077 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2078 fw_major, fw_minor, fw_updt);
2080 ret += 1; /* add the size of '\0' */
2081 if (fw_size < (uint32_t)ret)
2088 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2089 struct rte_eth_rxq_info *qinfo)
2091 struct bnxt *bp = dev->data->dev_private;
2092 struct bnxt_rx_queue *rxq;
2094 if (is_bnxt_in_error(bp))
2097 rxq = dev->data->rx_queues[queue_id];
2099 qinfo->mp = rxq->mb_pool;
2100 qinfo->scattered_rx = dev->data->scattered_rx;
2101 qinfo->nb_desc = rxq->nb_rx_desc;
2103 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2104 qinfo->conf.rx_drop_en = 0;
2105 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2109 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2110 struct rte_eth_txq_info *qinfo)
2112 struct bnxt *bp = dev->data->dev_private;
2113 struct bnxt_tx_queue *txq;
2115 if (is_bnxt_in_error(bp))
2118 txq = dev->data->tx_queues[queue_id];
2120 qinfo->nb_desc = txq->nb_tx_desc;
2122 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2123 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2124 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2126 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2127 qinfo->conf.tx_rs_thresh = 0;
2128 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2131 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2133 struct bnxt *bp = eth_dev->data->dev_private;
2134 uint32_t new_pkt_size;
2138 rc = is_bnxt_in_error(bp);
2142 /* Exit if receive queues are not configured yet */
2143 if (!eth_dev->data->nb_rx_queues)
2146 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2147 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2151 * If vector-mode tx/rx is active, disallow any MTU change that would
2152 * require scattered receive support.
2154 if (eth_dev->data->dev_started &&
2155 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2156 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2158 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2160 "MTU change would require scattered rx support. ");
2161 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2166 if (new_mtu > RTE_ETHER_MTU) {
2167 bp->flags |= BNXT_FLAG_JUMBO;
2168 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2169 DEV_RX_OFFLOAD_JUMBO_FRAME;
2171 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2172 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2173 bp->flags &= ~BNXT_FLAG_JUMBO;
2176 /* Is there a change in mtu setting? */
2177 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2180 for (i = 0; i < bp->nr_vnics; i++) {
2181 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2184 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2185 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2189 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2190 size -= RTE_PKTMBUF_HEADROOM;
2192 if (size < new_mtu) {
2193 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2200 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2202 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2208 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2210 struct bnxt *bp = dev->data->dev_private;
2211 uint16_t vlan = bp->vlan;
2214 rc = is_bnxt_in_error(bp);
2218 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2220 "PVID cannot be modified for this function\n");
2223 bp->vlan = on ? pvid : 0;
2225 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2232 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2234 struct bnxt *bp = dev->data->dev_private;
2237 rc = is_bnxt_in_error(bp);
2241 return bnxt_hwrm_port_led_cfg(bp, true);
2245 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2247 struct bnxt *bp = dev->data->dev_private;
2250 rc = is_bnxt_in_error(bp);
2254 return bnxt_hwrm_port_led_cfg(bp, false);
2258 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2260 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2261 uint32_t desc = 0, raw_cons = 0, cons;
2262 struct bnxt_cp_ring_info *cpr;
2263 struct bnxt_rx_queue *rxq;
2264 struct rx_pkt_cmpl *rxcmp;
2267 rc = is_bnxt_in_error(bp);
2271 rxq = dev->data->rx_queues[rx_queue_id];
2273 raw_cons = cpr->cp_raw_cons;
2276 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2277 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2278 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2280 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2292 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2294 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2295 struct bnxt_rx_ring_info *rxr;
2296 struct bnxt_cp_ring_info *cpr;
2297 struct bnxt_sw_rx_bd *rx_buf;
2298 struct rx_pkt_cmpl *rxcmp;
2299 uint32_t cons, cp_cons;
2305 rc = is_bnxt_in_error(rxq->bp);
2312 if (offset >= rxq->nb_rx_desc)
2315 cons = RING_CMP(cpr->cp_ring_struct, offset);
2316 cp_cons = cpr->cp_raw_cons;
2317 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2319 if (cons > cp_cons) {
2320 if (CMPL_VALID(rxcmp, cpr->valid))
2321 return RTE_ETH_RX_DESC_DONE;
2323 if (CMPL_VALID(rxcmp, !cpr->valid))
2324 return RTE_ETH_RX_DESC_DONE;
2326 rx_buf = &rxr->rx_buf_ring[cons];
2327 if (rx_buf->mbuf == NULL)
2328 return RTE_ETH_RX_DESC_UNAVAIL;
2331 return RTE_ETH_RX_DESC_AVAIL;
2335 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2337 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2338 struct bnxt_tx_ring_info *txr;
2339 struct bnxt_cp_ring_info *cpr;
2340 struct bnxt_sw_tx_bd *tx_buf;
2341 struct tx_pkt_cmpl *txcmp;
2342 uint32_t cons, cp_cons;
2348 rc = is_bnxt_in_error(txq->bp);
2355 if (offset >= txq->nb_tx_desc)
2358 cons = RING_CMP(cpr->cp_ring_struct, offset);
2359 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2360 cp_cons = cpr->cp_raw_cons;
2362 if (cons > cp_cons) {
2363 if (CMPL_VALID(txcmp, cpr->valid))
2364 return RTE_ETH_TX_DESC_UNAVAIL;
2366 if (CMPL_VALID(txcmp, !cpr->valid))
2367 return RTE_ETH_TX_DESC_UNAVAIL;
2369 tx_buf = &txr->tx_buf_ring[cons];
2370 if (tx_buf->mbuf == NULL)
2371 return RTE_ETH_TX_DESC_DONE;
2373 return RTE_ETH_TX_DESC_FULL;
2376 static struct bnxt_filter_info *
2377 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2378 struct rte_eth_ethertype_filter *efilter,
2379 struct bnxt_vnic_info *vnic0,
2380 struct bnxt_vnic_info *vnic,
2383 struct bnxt_filter_info *mfilter = NULL;
2387 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2388 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2389 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2390 " ethertype filter.", efilter->ether_type);
2394 if (efilter->queue >= bp->rx_nr_rings) {
2395 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2400 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2401 vnic = &bp->vnic_info[efilter->queue];
2403 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2408 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2409 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2410 if ((!memcmp(efilter->mac_addr.addr_bytes,
2411 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2413 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2414 mfilter->ethertype == efilter->ether_type)) {
2420 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2421 if ((!memcmp(efilter->mac_addr.addr_bytes,
2422 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2423 mfilter->ethertype == efilter->ether_type &&
2425 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2439 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2440 enum rte_filter_op filter_op,
2443 struct bnxt *bp = dev->data->dev_private;
2444 struct rte_eth_ethertype_filter *efilter =
2445 (struct rte_eth_ethertype_filter *)arg;
2446 struct bnxt_filter_info *bfilter, *filter1;
2447 struct bnxt_vnic_info *vnic, *vnic0;
2450 if (filter_op == RTE_ETH_FILTER_NOP)
2454 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2459 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2460 vnic = &bp->vnic_info[efilter->queue];
2462 switch (filter_op) {
2463 case RTE_ETH_FILTER_ADD:
2464 bnxt_match_and_validate_ether_filter(bp, efilter,
2469 bfilter = bnxt_get_unused_filter(bp);
2470 if (bfilter == NULL) {
2472 "Not enough resources for a new filter.\n");
2475 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2476 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2477 RTE_ETHER_ADDR_LEN);
2478 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2479 RTE_ETHER_ADDR_LEN);
2480 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2481 bfilter->ethertype = efilter->ether_type;
2482 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2484 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2485 if (filter1 == NULL) {
2490 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2491 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2493 bfilter->dst_id = vnic->fw_vnic_id;
2495 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2497 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2500 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2503 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2505 case RTE_ETH_FILTER_DELETE:
2506 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2508 if (ret == -EEXIST) {
2509 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2511 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2513 bnxt_free_filter(bp, filter1);
2514 } else if (ret == 0) {
2515 PMD_DRV_LOG(ERR, "No matching filter found\n");
2519 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2525 bnxt_free_filter(bp, bfilter);
2531 parse_ntuple_filter(struct bnxt *bp,
2532 struct rte_eth_ntuple_filter *nfilter,
2533 struct bnxt_filter_info *bfilter)
2537 if (nfilter->queue >= bp->rx_nr_rings) {
2538 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2542 switch (nfilter->dst_port_mask) {
2544 bfilter->dst_port_mask = -1;
2545 bfilter->dst_port = nfilter->dst_port;
2546 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2547 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2550 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2554 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2555 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2557 switch (nfilter->proto_mask) {
2559 if (nfilter->proto == 17) /* IPPROTO_UDP */
2560 bfilter->ip_protocol = 17;
2561 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2562 bfilter->ip_protocol = 6;
2565 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2568 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2572 switch (nfilter->dst_ip_mask) {
2574 bfilter->dst_ipaddr_mask[0] = -1;
2575 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2576 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2577 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2580 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2584 switch (nfilter->src_ip_mask) {
2586 bfilter->src_ipaddr_mask[0] = -1;
2587 bfilter->src_ipaddr[0] = nfilter->src_ip;
2588 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2589 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2592 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2596 switch (nfilter->src_port_mask) {
2598 bfilter->src_port_mask = -1;
2599 bfilter->src_port = nfilter->src_port;
2600 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2601 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2604 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2608 bfilter->enables = en;
2612 static struct bnxt_filter_info*
2613 bnxt_match_ntuple_filter(struct bnxt *bp,
2614 struct bnxt_filter_info *bfilter,
2615 struct bnxt_vnic_info **mvnic)
2617 struct bnxt_filter_info *mfilter = NULL;
2620 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2621 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2622 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2623 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2624 bfilter->src_ipaddr_mask[0] ==
2625 mfilter->src_ipaddr_mask[0] &&
2626 bfilter->src_port == mfilter->src_port &&
2627 bfilter->src_port_mask == mfilter->src_port_mask &&
2628 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2629 bfilter->dst_ipaddr_mask[0] ==
2630 mfilter->dst_ipaddr_mask[0] &&
2631 bfilter->dst_port == mfilter->dst_port &&
2632 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2633 bfilter->flags == mfilter->flags &&
2634 bfilter->enables == mfilter->enables) {
2645 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2646 struct rte_eth_ntuple_filter *nfilter,
2647 enum rte_filter_op filter_op)
2649 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2650 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2653 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2654 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2658 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2659 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2663 bfilter = bnxt_get_unused_filter(bp);
2664 if (bfilter == NULL) {
2666 "Not enough resources for a new filter.\n");
2669 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2673 vnic = &bp->vnic_info[nfilter->queue];
2674 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2675 filter1 = STAILQ_FIRST(&vnic0->filter);
2676 if (filter1 == NULL) {
2681 bfilter->dst_id = vnic->fw_vnic_id;
2682 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2684 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2685 bfilter->ethertype = 0x800;
2686 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2688 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2690 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2691 bfilter->dst_id == mfilter->dst_id) {
2692 PMD_DRV_LOG(ERR, "filter exists.\n");
2695 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2696 bfilter->dst_id != mfilter->dst_id) {
2697 mfilter->dst_id = vnic->fw_vnic_id;
2698 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2699 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2700 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2701 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2702 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2705 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2706 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2711 if (filter_op == RTE_ETH_FILTER_ADD) {
2712 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2713 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2716 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2718 if (mfilter == NULL) {
2719 /* This should not happen. But for Coverity! */
2723 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2725 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2726 bnxt_free_filter(bp, mfilter);
2727 bnxt_free_filter(bp, bfilter);
2732 bnxt_free_filter(bp, bfilter);
2737 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2738 enum rte_filter_op filter_op,
2741 struct bnxt *bp = dev->data->dev_private;
2744 if (filter_op == RTE_ETH_FILTER_NOP)
2748 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2753 switch (filter_op) {
2754 case RTE_ETH_FILTER_ADD:
2755 ret = bnxt_cfg_ntuple_filter(bp,
2756 (struct rte_eth_ntuple_filter *)arg,
2759 case RTE_ETH_FILTER_DELETE:
2760 ret = bnxt_cfg_ntuple_filter(bp,
2761 (struct rte_eth_ntuple_filter *)arg,
2765 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2773 bnxt_parse_fdir_filter(struct bnxt *bp,
2774 struct rte_eth_fdir_filter *fdir,
2775 struct bnxt_filter_info *filter)
2777 enum rte_fdir_mode fdir_mode =
2778 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2779 struct bnxt_vnic_info *vnic0, *vnic;
2780 struct bnxt_filter_info *filter1;
2784 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2787 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2788 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2790 switch (fdir->input.flow_type) {
2791 case RTE_ETH_FLOW_IPV4:
2792 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2794 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2795 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2796 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2797 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2798 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2799 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2800 filter->ip_addr_type =
2801 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2802 filter->src_ipaddr_mask[0] = 0xffffffff;
2803 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2804 filter->dst_ipaddr_mask[0] = 0xffffffff;
2805 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2806 filter->ethertype = 0x800;
2807 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2809 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2810 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2811 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2812 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2813 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2814 filter->dst_port_mask = 0xffff;
2815 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2816 filter->src_port_mask = 0xffff;
2817 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2818 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2819 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2820 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2821 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2822 filter->ip_protocol = 6;
2823 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2824 filter->ip_addr_type =
2825 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2826 filter->src_ipaddr_mask[0] = 0xffffffff;
2827 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2828 filter->dst_ipaddr_mask[0] = 0xffffffff;
2829 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2830 filter->ethertype = 0x800;
2831 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2833 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2834 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2835 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2836 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2837 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2838 filter->dst_port_mask = 0xffff;
2839 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2840 filter->src_port_mask = 0xffff;
2841 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2842 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2843 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2844 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2845 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2846 filter->ip_protocol = 17;
2847 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2848 filter->ip_addr_type =
2849 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2850 filter->src_ipaddr_mask[0] = 0xffffffff;
2851 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2852 filter->dst_ipaddr_mask[0] = 0xffffffff;
2853 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2854 filter->ethertype = 0x800;
2855 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2857 case RTE_ETH_FLOW_IPV6:
2858 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2860 filter->ip_addr_type =
2861 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2862 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2863 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2864 rte_memcpy(filter->src_ipaddr,
2865 fdir->input.flow.ipv6_flow.src_ip, 16);
2866 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2867 rte_memcpy(filter->dst_ipaddr,
2868 fdir->input.flow.ipv6_flow.dst_ip, 16);
2869 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2870 memset(filter->dst_ipaddr_mask, 0xff, 16);
2871 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2872 memset(filter->src_ipaddr_mask, 0xff, 16);
2873 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2874 filter->ethertype = 0x86dd;
2875 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2877 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2878 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2879 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2880 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2881 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2882 filter->dst_port_mask = 0xffff;
2883 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2884 filter->src_port_mask = 0xffff;
2885 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2886 filter->ip_addr_type =
2887 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2888 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2889 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2890 rte_memcpy(filter->src_ipaddr,
2891 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2892 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2893 rte_memcpy(filter->dst_ipaddr,
2894 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2895 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2896 memset(filter->dst_ipaddr_mask, 0xff, 16);
2897 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2898 memset(filter->src_ipaddr_mask, 0xff, 16);
2899 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2900 filter->ethertype = 0x86dd;
2901 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2903 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2904 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2905 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2906 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2907 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2908 filter->dst_port_mask = 0xffff;
2909 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2910 filter->src_port_mask = 0xffff;
2911 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2912 filter->ip_addr_type =
2913 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2914 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2915 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2916 rte_memcpy(filter->src_ipaddr,
2917 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2918 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2919 rte_memcpy(filter->dst_ipaddr,
2920 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2921 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2922 memset(filter->dst_ipaddr_mask, 0xff, 16);
2923 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2924 memset(filter->src_ipaddr_mask, 0xff, 16);
2925 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2926 filter->ethertype = 0x86dd;
2927 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2929 case RTE_ETH_FLOW_L2_PAYLOAD:
2930 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2931 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2933 case RTE_ETH_FLOW_VXLAN:
2934 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2936 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2937 filter->tunnel_type =
2938 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2939 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2941 case RTE_ETH_FLOW_NVGRE:
2942 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2944 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2945 filter->tunnel_type =
2946 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2947 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2949 case RTE_ETH_FLOW_UNKNOWN:
2950 case RTE_ETH_FLOW_RAW:
2951 case RTE_ETH_FLOW_FRAG_IPV4:
2952 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2953 case RTE_ETH_FLOW_FRAG_IPV6:
2954 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2955 case RTE_ETH_FLOW_IPV6_EX:
2956 case RTE_ETH_FLOW_IPV6_TCP_EX:
2957 case RTE_ETH_FLOW_IPV6_UDP_EX:
2958 case RTE_ETH_FLOW_GENEVE:
2964 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2965 vnic = &bp->vnic_info[fdir->action.rx_queue];
2967 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2971 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2972 rte_memcpy(filter->dst_macaddr,
2973 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2974 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2977 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2978 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2979 filter1 = STAILQ_FIRST(&vnic0->filter);
2980 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2982 filter->dst_id = vnic->fw_vnic_id;
2983 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2984 if (filter->dst_macaddr[i] == 0x00)
2985 filter1 = STAILQ_FIRST(&vnic0->filter);
2987 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2990 if (filter1 == NULL)
2993 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2994 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2996 filter->enables = en;
3001 static struct bnxt_filter_info *
3002 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3003 struct bnxt_vnic_info **mvnic)
3005 struct bnxt_filter_info *mf = NULL;
3008 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3009 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3011 STAILQ_FOREACH(mf, &vnic->filter, next) {
3012 if (mf->filter_type == nf->filter_type &&
3013 mf->flags == nf->flags &&
3014 mf->src_port == nf->src_port &&
3015 mf->src_port_mask == nf->src_port_mask &&
3016 mf->dst_port == nf->dst_port &&
3017 mf->dst_port_mask == nf->dst_port_mask &&
3018 mf->ip_protocol == nf->ip_protocol &&
3019 mf->ip_addr_type == nf->ip_addr_type &&
3020 mf->ethertype == nf->ethertype &&
3021 mf->vni == nf->vni &&
3022 mf->tunnel_type == nf->tunnel_type &&
3023 mf->l2_ovlan == nf->l2_ovlan &&
3024 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3025 mf->l2_ivlan == nf->l2_ivlan &&
3026 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3027 !memcmp(mf->l2_addr, nf->l2_addr,
3028 RTE_ETHER_ADDR_LEN) &&
3029 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3030 RTE_ETHER_ADDR_LEN) &&
3031 !memcmp(mf->src_macaddr, nf->src_macaddr,
3032 RTE_ETHER_ADDR_LEN) &&
3033 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3034 RTE_ETHER_ADDR_LEN) &&
3035 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3036 sizeof(nf->src_ipaddr)) &&
3037 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3038 sizeof(nf->src_ipaddr_mask)) &&
3039 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3040 sizeof(nf->dst_ipaddr)) &&
3041 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3042 sizeof(nf->dst_ipaddr_mask))) {
3053 bnxt_fdir_filter(struct rte_eth_dev *dev,
3054 enum rte_filter_op filter_op,
3057 struct bnxt *bp = dev->data->dev_private;
3058 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
3059 struct bnxt_filter_info *filter, *match;
3060 struct bnxt_vnic_info *vnic, *mvnic;
3063 if (filter_op == RTE_ETH_FILTER_NOP)
3066 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3069 switch (filter_op) {
3070 case RTE_ETH_FILTER_ADD:
3071 case RTE_ETH_FILTER_DELETE:
3073 filter = bnxt_get_unused_filter(bp);
3074 if (filter == NULL) {
3076 "Not enough resources for a new flow.\n");
3080 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3083 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3085 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3086 vnic = &bp->vnic_info[0];
3088 vnic = &bp->vnic_info[fdir->action.rx_queue];
3090 match = bnxt_match_fdir(bp, filter, &mvnic);
3091 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3092 if (match->dst_id == vnic->fw_vnic_id) {
3093 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3097 match->dst_id = vnic->fw_vnic_id;
3098 ret = bnxt_hwrm_set_ntuple_filter(bp,
3101 STAILQ_REMOVE(&mvnic->filter, match,
3102 bnxt_filter_info, next);
3103 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3105 "Filter with matching pattern exist\n");
3107 "Updated it to new destination q\n");
3111 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3112 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3117 if (filter_op == RTE_ETH_FILTER_ADD) {
3118 ret = bnxt_hwrm_set_ntuple_filter(bp,
3123 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3125 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3126 STAILQ_REMOVE(&vnic->filter, match,
3127 bnxt_filter_info, next);
3128 bnxt_free_filter(bp, match);
3129 bnxt_free_filter(bp, filter);
3132 case RTE_ETH_FILTER_FLUSH:
3133 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3134 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3136 STAILQ_FOREACH(filter, &vnic->filter, next) {
3137 if (filter->filter_type ==
3138 HWRM_CFA_NTUPLE_FILTER) {
3140 bnxt_hwrm_clear_ntuple_filter(bp,
3142 STAILQ_REMOVE(&vnic->filter, filter,
3143 bnxt_filter_info, next);
3148 case RTE_ETH_FILTER_UPDATE:
3149 case RTE_ETH_FILTER_STATS:
3150 case RTE_ETH_FILTER_INFO:
3151 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3154 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3161 bnxt_free_filter(bp, filter);
3166 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3167 enum rte_filter_type filter_type,
3168 enum rte_filter_op filter_op, void *arg)
3172 ret = is_bnxt_in_error(dev->data->dev_private);
3176 switch (filter_type) {
3177 case RTE_ETH_FILTER_TUNNEL:
3179 "filter type: %d: To be implemented\n", filter_type);
3181 case RTE_ETH_FILTER_FDIR:
3182 ret = bnxt_fdir_filter(dev, filter_op, arg);
3184 case RTE_ETH_FILTER_NTUPLE:
3185 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3187 case RTE_ETH_FILTER_ETHERTYPE:
3188 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3190 case RTE_ETH_FILTER_GENERIC:
3191 if (filter_op != RTE_ETH_FILTER_GET)
3193 *(const void **)arg = &bnxt_flow_ops;
3197 "Filter type (%d) not supported", filter_type);
3204 static const uint32_t *
3205 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3207 static const uint32_t ptypes[] = {
3208 RTE_PTYPE_L2_ETHER_VLAN,
3209 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3210 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3214 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3215 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3216 RTE_PTYPE_INNER_L4_ICMP,
3217 RTE_PTYPE_INNER_L4_TCP,
3218 RTE_PTYPE_INNER_L4_UDP,
3222 if (!dev->rx_pkt_burst)
3228 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3231 uint32_t reg_base = *reg_arr & 0xfffff000;
3235 for (i = 0; i < count; i++) {
3236 if ((reg_arr[i] & 0xfffff000) != reg_base)
3239 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3240 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3244 static int bnxt_map_ptp_regs(struct bnxt *bp)
3246 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3250 reg_arr = ptp->rx_regs;
3251 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3255 reg_arr = ptp->tx_regs;
3256 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3260 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3261 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3263 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3264 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3269 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3271 rte_write32(0, (uint8_t *)bp->bar0 +
3272 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3273 rte_write32(0, (uint8_t *)bp->bar0 +
3274 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3277 static uint64_t bnxt_cc_read(struct bnxt *bp)
3281 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3282 BNXT_GRCPF_REG_SYNC_TIME));
3283 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3284 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3288 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3290 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3293 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3294 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3295 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3298 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3299 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3300 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3301 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3302 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3303 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3308 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3310 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3311 struct bnxt_pf_info *pf = &bp->pf;
3318 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3319 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3320 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3323 port_id = pf->port_id;
3324 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3325 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3327 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3328 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3329 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3330 /* bnxt_clr_rx_ts(bp); TBD */
3334 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3335 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3336 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3337 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3343 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3346 struct bnxt *bp = dev->data->dev_private;
3347 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3352 ns = rte_timespec_to_ns(ts);
3353 /* Set the timecounters to a new value. */
3360 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3362 struct bnxt *bp = dev->data->dev_private;
3363 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3364 uint64_t ns, systime_cycles = 0;
3370 if (BNXT_CHIP_THOR(bp))
3371 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3374 systime_cycles = bnxt_cc_read(bp);
3376 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3377 *ts = rte_ns_to_timespec(ns);
3382 bnxt_timesync_enable(struct rte_eth_dev *dev)
3384 struct bnxt *bp = dev->data->dev_private;
3385 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3393 ptp->tx_tstamp_en = 1;
3394 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3396 rc = bnxt_hwrm_ptp_cfg(bp);
3400 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3401 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3402 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3404 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3405 ptp->tc.cc_shift = shift;
3406 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3408 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3409 ptp->rx_tstamp_tc.cc_shift = shift;
3410 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3412 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3413 ptp->tx_tstamp_tc.cc_shift = shift;
3414 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3416 if (!BNXT_CHIP_THOR(bp))
3417 bnxt_map_ptp_regs(bp);
3423 bnxt_timesync_disable(struct rte_eth_dev *dev)
3425 struct bnxt *bp = dev->data->dev_private;
3426 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3432 ptp->tx_tstamp_en = 0;
3435 bnxt_hwrm_ptp_cfg(bp);
3437 if (!BNXT_CHIP_THOR(bp))
3438 bnxt_unmap_ptp_regs(bp);
3444 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3445 struct timespec *timestamp,
3446 uint32_t flags __rte_unused)
3448 struct bnxt *bp = dev->data->dev_private;
3449 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3450 uint64_t rx_tstamp_cycles = 0;
3456 if (BNXT_CHIP_THOR(bp))
3457 rx_tstamp_cycles = ptp->rx_timestamp;
3459 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3461 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3462 *timestamp = rte_ns_to_timespec(ns);
3467 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3468 struct timespec *timestamp)
3470 struct bnxt *bp = dev->data->dev_private;
3471 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3472 uint64_t tx_tstamp_cycles = 0;
3479 if (BNXT_CHIP_THOR(bp))
3480 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3483 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3485 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3486 *timestamp = rte_ns_to_timespec(ns);
3492 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3494 struct bnxt *bp = dev->data->dev_private;
3495 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3500 ptp->tc.nsec += delta;
3506 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3508 struct bnxt *bp = dev->data->dev_private;
3510 uint32_t dir_entries;
3511 uint32_t entry_length;
3513 rc = is_bnxt_in_error(bp);
3517 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3518 bp->pdev->addr.domain, bp->pdev->addr.bus,
3519 bp->pdev->addr.devid, bp->pdev->addr.function);
3521 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3525 return dir_entries * entry_length;
3529 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3530 struct rte_dev_eeprom_info *in_eeprom)
3532 struct bnxt *bp = dev->data->dev_private;
3537 rc = is_bnxt_in_error(bp);
3541 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3542 "len = %d\n", bp->pdev->addr.domain,
3543 bp->pdev->addr.bus, bp->pdev->addr.devid,
3544 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3546 if (in_eeprom->offset == 0) /* special offset value to get directory */
3547 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3550 index = in_eeprom->offset >> 24;
3551 offset = in_eeprom->offset & 0xffffff;
3554 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3555 in_eeprom->length, in_eeprom->data);
3560 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3563 case BNX_DIR_TYPE_CHIMP_PATCH:
3564 case BNX_DIR_TYPE_BOOTCODE:
3565 case BNX_DIR_TYPE_BOOTCODE_2:
3566 case BNX_DIR_TYPE_APE_FW:
3567 case BNX_DIR_TYPE_APE_PATCH:
3568 case BNX_DIR_TYPE_KONG_FW:
3569 case BNX_DIR_TYPE_KONG_PATCH:
3570 case BNX_DIR_TYPE_BONO_FW:
3571 case BNX_DIR_TYPE_BONO_PATCH:
3579 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3582 case BNX_DIR_TYPE_AVS:
3583 case BNX_DIR_TYPE_EXP_ROM_MBA:
3584 case BNX_DIR_TYPE_PCIE:
3585 case BNX_DIR_TYPE_TSCF_UCODE:
3586 case BNX_DIR_TYPE_EXT_PHY:
3587 case BNX_DIR_TYPE_CCM:
3588 case BNX_DIR_TYPE_ISCSI_BOOT:
3589 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3590 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3598 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3600 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3601 bnxt_dir_type_is_other_exec_format(dir_type);
3605 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3606 struct rte_dev_eeprom_info *in_eeprom)
3608 struct bnxt *bp = dev->data->dev_private;
3609 uint8_t index, dir_op;
3610 uint16_t type, ext, ordinal, attr;
3613 rc = is_bnxt_in_error(bp);
3617 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3618 "len = %d\n", bp->pdev->addr.domain,
3619 bp->pdev->addr.bus, bp->pdev->addr.devid,
3620 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3623 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3627 type = in_eeprom->magic >> 16;
3629 if (type == 0xffff) { /* special value for directory operations */
3630 index = in_eeprom->magic & 0xff;
3631 dir_op = in_eeprom->magic >> 8;
3635 case 0x0e: /* erase */
3636 if (in_eeprom->offset != ~in_eeprom->magic)
3638 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3644 /* Create or re-write an NVM item: */
3645 if (bnxt_dir_type_is_executable(type) == true)
3647 ext = in_eeprom->magic & 0xffff;
3648 ordinal = in_eeprom->offset >> 16;
3649 attr = in_eeprom->offset & 0xffff;
3651 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3652 in_eeprom->data, in_eeprom->length);
3659 static const struct eth_dev_ops bnxt_dev_ops = {
3660 .dev_infos_get = bnxt_dev_info_get_op,
3661 .dev_close = bnxt_dev_close_op,
3662 .dev_configure = bnxt_dev_configure_op,
3663 .dev_start = bnxt_dev_start_op,
3664 .dev_stop = bnxt_dev_stop_op,
3665 .dev_set_link_up = bnxt_dev_set_link_up_op,
3666 .dev_set_link_down = bnxt_dev_set_link_down_op,
3667 .stats_get = bnxt_stats_get_op,
3668 .stats_reset = bnxt_stats_reset_op,
3669 .rx_queue_setup = bnxt_rx_queue_setup_op,
3670 .rx_queue_release = bnxt_rx_queue_release_op,
3671 .tx_queue_setup = bnxt_tx_queue_setup_op,
3672 .tx_queue_release = bnxt_tx_queue_release_op,
3673 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3674 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3675 .reta_update = bnxt_reta_update_op,
3676 .reta_query = bnxt_reta_query_op,
3677 .rss_hash_update = bnxt_rss_hash_update_op,
3678 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3679 .link_update = bnxt_link_update_op,
3680 .promiscuous_enable = bnxt_promiscuous_enable_op,
3681 .promiscuous_disable = bnxt_promiscuous_disable_op,
3682 .allmulticast_enable = bnxt_allmulticast_enable_op,
3683 .allmulticast_disable = bnxt_allmulticast_disable_op,
3684 .mac_addr_add = bnxt_mac_addr_add_op,
3685 .mac_addr_remove = bnxt_mac_addr_remove_op,
3686 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3687 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3688 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3689 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3690 .vlan_filter_set = bnxt_vlan_filter_set_op,
3691 .vlan_offload_set = bnxt_vlan_offload_set_op,
3692 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3693 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3694 .mtu_set = bnxt_mtu_set_op,
3695 .mac_addr_set = bnxt_set_default_mac_addr_op,
3696 .xstats_get = bnxt_dev_xstats_get_op,
3697 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3698 .xstats_reset = bnxt_dev_xstats_reset_op,
3699 .fw_version_get = bnxt_fw_version_get,
3700 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3701 .rxq_info_get = bnxt_rxq_info_get_op,
3702 .txq_info_get = bnxt_txq_info_get_op,
3703 .dev_led_on = bnxt_dev_led_on_op,
3704 .dev_led_off = bnxt_dev_led_off_op,
3705 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3706 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3707 .rx_queue_count = bnxt_rx_queue_count_op,
3708 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3709 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3710 .rx_queue_start = bnxt_rx_queue_start,
3711 .rx_queue_stop = bnxt_rx_queue_stop,
3712 .tx_queue_start = bnxt_tx_queue_start,
3713 .tx_queue_stop = bnxt_tx_queue_stop,
3714 .filter_ctrl = bnxt_filter_ctrl_op,
3715 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3716 .get_eeprom_length = bnxt_get_eeprom_length_op,
3717 .get_eeprom = bnxt_get_eeprom_op,
3718 .set_eeprom = bnxt_set_eeprom_op,
3719 .timesync_enable = bnxt_timesync_enable,
3720 .timesync_disable = bnxt_timesync_disable,
3721 .timesync_read_time = bnxt_timesync_read_time,
3722 .timesync_write_time = bnxt_timesync_write_time,
3723 .timesync_adjust_time = bnxt_timesync_adjust_time,
3724 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3725 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3728 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3732 /* Only pre-map the reset GRC registers using window 3 */
3733 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3734 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3736 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3741 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3743 struct bnxt_error_recovery_info *info = bp->recovery_info;
3744 uint32_t reg_base = 0xffffffff;
3747 /* Only pre-map the monitoring GRC registers using window 2 */
3748 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3749 uint32_t reg = info->status_regs[i];
3751 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3754 if (reg_base == 0xffffffff)
3755 reg_base = reg & 0xfffff000;
3756 if ((reg & 0xfffff000) != reg_base)
3759 /* Use mask 0xffc as the Lower 2 bits indicates
3760 * address space location
3762 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3766 if (reg_base == 0xffffffff)
3769 rte_write32(reg_base, (uint8_t *)bp->bar0 +
3770 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3775 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3777 struct bnxt_error_recovery_info *info = bp->recovery_info;
3778 uint32_t delay = info->delay_after_reset[index];
3779 uint32_t val = info->reset_reg_val[index];
3780 uint32_t reg = info->reset_reg[index];
3781 uint32_t type, offset;
3783 type = BNXT_FW_STATUS_REG_TYPE(reg);
3784 offset = BNXT_FW_STATUS_REG_OFF(reg);
3787 case BNXT_FW_STATUS_REG_TYPE_CFG:
3788 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3790 case BNXT_FW_STATUS_REG_TYPE_GRC:
3791 offset = bnxt_map_reset_regs(bp, offset);
3792 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3794 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3795 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3798 /* wait on a specific interval of time until core reset is complete */
3800 rte_delay_ms(delay);
3803 static void bnxt_dev_cleanup(struct bnxt *bp)
3805 bnxt_set_hwrm_link_config(bp, false);
3806 bp->link_info.link_up = 0;
3807 if (bp->dev_stopped == 0)
3808 bnxt_dev_stop_op(bp->eth_dev);
3810 bnxt_uninit_resources(bp, true);
3813 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3815 struct rte_eth_dev *dev = bp->eth_dev;
3816 struct rte_vlan_filter_conf *vfc;
3820 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3821 vfc = &dev->data->vlan_filter_conf;
3822 vidx = vlan_id / 64;
3823 vbit = vlan_id % 64;
3825 /* Each bit corresponds to a VLAN id */
3826 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3827 rc = bnxt_add_vlan_filter(bp, vlan_id);
3836 static int bnxt_restore_mac_filters(struct bnxt *bp)
3838 struct rte_eth_dev *dev = bp->eth_dev;
3839 struct rte_eth_dev_info dev_info;
3840 struct rte_ether_addr *addr;
3846 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
3849 rc = bnxt_dev_info_get_op(dev, &dev_info);
3853 /* replay MAC address configuration */
3854 for (i = 1; i < dev_info.max_mac_addrs; i++) {
3855 addr = &dev->data->mac_addrs[i];
3857 /* skip zero address */
3858 if (rte_is_zero_ether_addr(addr))
3862 pool_mask = dev->data->mac_pool_sel[i];
3865 if (pool_mask & 1ULL) {
3866 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3872 } while (pool_mask);
3878 static int bnxt_restore_filters(struct bnxt *bp)
3880 struct rte_eth_dev *dev = bp->eth_dev;
3883 if (dev->data->all_multicast)
3884 ret = bnxt_allmulticast_enable_op(dev);
3885 if (dev->data->promiscuous)
3886 ret = bnxt_promiscuous_enable_op(dev);
3888 ret = bnxt_restore_mac_filters(bp);
3892 ret = bnxt_restore_vlan_filters(bp);
3893 /* TODO restore other filters as well */
3897 static void bnxt_dev_recover(void *arg)
3899 struct bnxt *bp = arg;
3900 int timeout = bp->fw_reset_max_msecs;
3903 /* Clear Error flag so that device re-init should happen */
3904 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3907 rc = bnxt_hwrm_ver_get(bp);
3910 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3911 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3912 } while (rc && timeout);
3915 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3919 rc = bnxt_init_resources(bp, true);
3922 "Failed to initialize resources after reset\n");
3925 /* clear reset flag as the device is initialized now */
3926 bp->flags &= ~BNXT_FLAG_FW_RESET;
3928 rc = bnxt_dev_start_op(bp->eth_dev);
3930 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3934 rc = bnxt_restore_filters(bp);
3938 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3941 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3942 bnxt_uninit_resources(bp, false);
3943 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3946 void bnxt_dev_reset_and_resume(void *arg)
3948 struct bnxt *bp = arg;
3951 bnxt_dev_cleanup(bp);
3953 bnxt_wait_for_device_shutdown(bp);
3955 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3956 bnxt_dev_recover, (void *)bp);
3958 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3961 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3963 struct bnxt_error_recovery_info *info = bp->recovery_info;
3964 uint32_t reg = info->status_regs[index];
3965 uint32_t type, offset, val = 0;
3967 type = BNXT_FW_STATUS_REG_TYPE(reg);
3968 offset = BNXT_FW_STATUS_REG_OFF(reg);
3971 case BNXT_FW_STATUS_REG_TYPE_CFG:
3972 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3974 case BNXT_FW_STATUS_REG_TYPE_GRC:
3975 offset = info->mapped_status_regs[index];
3977 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3978 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3986 static int bnxt_fw_reset_all(struct bnxt *bp)
3988 struct bnxt_error_recovery_info *info = bp->recovery_info;
3992 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3993 /* Reset through master function driver */
3994 for (i = 0; i < info->reg_array_cnt; i++)
3995 bnxt_write_fw_reset_reg(bp, i);
3996 /* Wait for time specified by FW after triggering reset */
3997 rte_delay_ms(info->master_func_wait_period_after_reset);
3998 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3999 /* Reset with the help of Kong processor */
4000 rc = bnxt_hwrm_fw_reset(bp);
4002 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4008 static void bnxt_fw_reset_cb(void *arg)
4010 struct bnxt *bp = arg;
4011 struct bnxt_error_recovery_info *info = bp->recovery_info;
4014 /* Only Master function can do FW reset */
4015 if (bnxt_is_master_func(bp) &&
4016 bnxt_is_recovery_enabled(bp)) {
4017 rc = bnxt_fw_reset_all(bp);
4019 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4024 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4025 * EXCEPTION_FATAL_ASYNC event to all the functions
4026 * (including MASTER FUNC). After receiving this Async, all the active
4027 * drivers should treat this case as FW initiated recovery
4029 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4030 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4031 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4033 /* To recover from error */
4034 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4039 /* Driver should poll FW heartbeat, reset_counter with the frequency
4040 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4041 * When the driver detects heartbeat stop or change in reset_counter,
4042 * it has to trigger a reset to recover from the error condition.
4043 * A “master PF” is the function who will have the privilege to
4044 * initiate the chimp reset. The master PF will be elected by the
4045 * firmware and will be notified through async message.
4047 static void bnxt_check_fw_health(void *arg)
4049 struct bnxt *bp = arg;
4050 struct bnxt_error_recovery_info *info = bp->recovery_info;
4051 uint32_t val = 0, wait_msec;
4053 if (!info || !bnxt_is_recovery_enabled(bp) ||
4054 is_bnxt_in_error(bp))
4057 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4058 if (val == info->last_heart_beat)
4061 info->last_heart_beat = val;
4063 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4064 if (val != info->last_reset_counter)
4067 info->last_reset_counter = val;
4069 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4070 bnxt_check_fw_health, (void *)bp);
4074 /* Stop DMA to/from device */
4075 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4076 bp->flags |= BNXT_FLAG_FW_RESET;
4078 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4080 if (bnxt_is_master_func(bp))
4081 wait_msec = info->master_func_wait_period;
4083 wait_msec = info->normal_func_wait_period;
4085 rte_eal_alarm_set(US_PER_MS * wait_msec,
4086 bnxt_fw_reset_cb, (void *)bp);
4089 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4091 uint32_t polling_freq;
4093 if (!bnxt_is_recovery_enabled(bp))
4096 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4099 polling_freq = bp->recovery_info->driver_polling_freq;
4101 rte_eal_alarm_set(US_PER_MS * polling_freq,
4102 bnxt_check_fw_health, (void *)bp);
4103 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4106 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4108 if (!bnxt_is_recovery_enabled(bp))
4111 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4112 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4115 static bool bnxt_vf_pciid(uint16_t device_id)
4117 switch (device_id) {
4118 case BROADCOM_DEV_ID_57304_VF:
4119 case BROADCOM_DEV_ID_57406_VF:
4120 case BROADCOM_DEV_ID_5731X_VF:
4121 case BROADCOM_DEV_ID_5741X_VF:
4122 case BROADCOM_DEV_ID_57414_VF:
4123 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4124 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4125 case BROADCOM_DEV_ID_58802_VF:
4126 case BROADCOM_DEV_ID_57500_VF1:
4127 case BROADCOM_DEV_ID_57500_VF2:
4135 static bool bnxt_thor_device(uint16_t device_id)
4137 switch (device_id) {
4138 case BROADCOM_DEV_ID_57508:
4139 case BROADCOM_DEV_ID_57504:
4140 case BROADCOM_DEV_ID_57502:
4141 case BROADCOM_DEV_ID_57508_MF1:
4142 case BROADCOM_DEV_ID_57504_MF1:
4143 case BROADCOM_DEV_ID_57502_MF1:
4144 case BROADCOM_DEV_ID_57508_MF2:
4145 case BROADCOM_DEV_ID_57504_MF2:
4146 case BROADCOM_DEV_ID_57502_MF2:
4147 case BROADCOM_DEV_ID_57500_VF1:
4148 case BROADCOM_DEV_ID_57500_VF2:
4156 bool bnxt_stratus_device(struct bnxt *bp)
4158 uint16_t device_id = bp->pdev->id.device_id;
4160 switch (device_id) {
4161 case BROADCOM_DEV_ID_STRATUS_NIC:
4162 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4163 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4171 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4173 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4174 struct bnxt *bp = eth_dev->data->dev_private;
4176 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4177 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4178 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4179 if (!bp->bar0 || !bp->doorbell_base) {
4180 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4184 bp->eth_dev = eth_dev;
4190 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4191 struct bnxt_ctx_pg_info *ctx_pg,
4196 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4197 const struct rte_memzone *mz = NULL;
4198 char mz_name[RTE_MEMZONE_NAMESIZE];
4199 rte_iova_t mz_phys_addr;
4200 uint64_t valid_bits = 0;
4207 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4209 rmem->page_size = BNXT_PAGE_SIZE;
4210 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4211 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4212 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4214 valid_bits = PTU_PTE_VALID;
4216 if (rmem->nr_pages > 1) {
4217 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4218 "bnxt_ctx_pg_tbl%s_%x_%d",
4219 suffix, idx, bp->eth_dev->data->port_id);
4220 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4221 mz = rte_memzone_lookup(mz_name);
4223 mz = rte_memzone_reserve_aligned(mz_name,
4227 RTE_MEMZONE_SIZE_HINT_ONLY |
4228 RTE_MEMZONE_IOVA_CONTIG,
4234 memset(mz->addr, 0, mz->len);
4235 mz_phys_addr = mz->iova;
4237 rmem->pg_tbl = mz->addr;
4238 rmem->pg_tbl_map = mz_phys_addr;
4239 rmem->pg_tbl_mz = mz;
4242 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4243 suffix, idx, bp->eth_dev->data->port_id);
4244 mz = rte_memzone_lookup(mz_name);
4246 mz = rte_memzone_reserve_aligned(mz_name,
4250 RTE_MEMZONE_SIZE_HINT_ONLY |
4251 RTE_MEMZONE_IOVA_CONTIG,
4257 memset(mz->addr, 0, mz->len);
4258 mz_phys_addr = mz->iova;
4260 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4261 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4262 rmem->dma_arr[i] = mz_phys_addr + sz;
4264 if (rmem->nr_pages > 1) {
4265 if (i == rmem->nr_pages - 2 &&
4266 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4267 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4268 else if (i == rmem->nr_pages - 1 &&
4269 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4270 valid_bits |= PTU_PTE_LAST;
4272 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4278 if (rmem->vmem_size)
4279 rmem->vmem = (void **)mz->addr;
4280 rmem->dma_arr[0] = mz_phys_addr;
4284 static void bnxt_free_ctx_mem(struct bnxt *bp)
4288 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4291 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4292 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4293 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4294 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4295 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4296 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4297 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4298 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4299 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4300 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4301 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4303 for (i = 0; i < BNXT_MAX_Q; i++) {
4304 if (bp->ctx->tqm_mem[i])
4305 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4312 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4314 #define min_t(type, x, y) ({ \
4315 type __min1 = (x); \
4316 type __min2 = (y); \
4317 __min1 < __min2 ? __min1 : __min2; })
4319 #define max_t(type, x, y) ({ \
4320 type __max1 = (x); \
4321 type __max2 = (y); \
4322 __max1 > __max2 ? __max1 : __max2; })
4324 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4326 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4328 struct bnxt_ctx_pg_info *ctx_pg;
4329 struct bnxt_ctx_mem_info *ctx;
4330 uint32_t mem_size, ena, entries;
4333 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4335 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4339 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4342 ctx_pg = &ctx->qp_mem;
4343 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4344 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4345 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4349 ctx_pg = &ctx->srq_mem;
4350 ctx_pg->entries = ctx->srq_max_l2_entries;
4351 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4352 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4356 ctx_pg = &ctx->cq_mem;
4357 ctx_pg->entries = ctx->cq_max_l2_entries;
4358 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4359 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4363 ctx_pg = &ctx->vnic_mem;
4364 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4365 ctx->vnic_max_ring_table_entries;
4366 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4367 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4371 ctx_pg = &ctx->stat_mem;
4372 ctx_pg->entries = ctx->stat_max_entries;
4373 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4374 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4378 entries = ctx->qp_max_l2_entries +
4379 ctx->vnic_max_vnic_entries +
4380 ctx->tqm_min_entries_per_ring;
4381 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4382 entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4383 ctx->tqm_max_entries_per_ring);
4384 for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4385 ctx_pg = ctx->tqm_mem[i];
4386 /* use min tqm entries for now. */
4387 ctx_pg->entries = entries;
4388 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4389 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4392 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4395 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4396 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4399 "Failed to configure context mem: rc = %d\n", rc);
4401 ctx->flags |= BNXT_CTX_FLAG_INITED;
4406 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4408 struct rte_pci_device *pci_dev = bp->pdev;
4409 char mz_name[RTE_MEMZONE_NAMESIZE];
4410 const struct rte_memzone *mz = NULL;
4411 uint32_t total_alloc_len;
4412 rte_iova_t mz_phys_addr;
4414 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4417 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4418 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4419 pci_dev->addr.bus, pci_dev->addr.devid,
4420 pci_dev->addr.function, "rx_port_stats");
4421 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4422 mz = rte_memzone_lookup(mz_name);
4424 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4425 sizeof(struct rx_port_stats_ext) + 512);
4427 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4430 RTE_MEMZONE_SIZE_HINT_ONLY |
4431 RTE_MEMZONE_IOVA_CONTIG);
4435 memset(mz->addr, 0, mz->len);
4436 mz_phys_addr = mz->iova;
4438 bp->rx_mem_zone = (const void *)mz;
4439 bp->hw_rx_port_stats = mz->addr;
4440 bp->hw_rx_port_stats_map = mz_phys_addr;
4442 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4443 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4444 pci_dev->addr.bus, pci_dev->addr.devid,
4445 pci_dev->addr.function, "tx_port_stats");
4446 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4447 mz = rte_memzone_lookup(mz_name);
4449 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4450 sizeof(struct tx_port_stats_ext) + 512);
4452 mz = rte_memzone_reserve(mz_name,
4456 RTE_MEMZONE_SIZE_HINT_ONLY |
4457 RTE_MEMZONE_IOVA_CONTIG);
4461 memset(mz->addr, 0, mz->len);
4462 mz_phys_addr = mz->iova;
4464 bp->tx_mem_zone = (const void *)mz;
4465 bp->hw_tx_port_stats = mz->addr;
4466 bp->hw_tx_port_stats_map = mz_phys_addr;
4467 bp->flags |= BNXT_FLAG_PORT_STATS;
4469 /* Display extended statistics if FW supports it */
4470 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4471 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4472 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4475 bp->hw_rx_port_stats_ext = (void *)
4476 ((uint8_t *)bp->hw_rx_port_stats +
4477 sizeof(struct rx_port_stats));
4478 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4479 sizeof(struct rx_port_stats);
4480 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4482 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4483 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4484 bp->hw_tx_port_stats_ext = (void *)
4485 ((uint8_t *)bp->hw_tx_port_stats +
4486 sizeof(struct tx_port_stats));
4487 bp->hw_tx_port_stats_ext_map =
4488 bp->hw_tx_port_stats_map +
4489 sizeof(struct tx_port_stats);
4490 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4496 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4498 struct bnxt *bp = eth_dev->data->dev_private;
4501 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4502 RTE_ETHER_ADDR_LEN *
4505 if (eth_dev->data->mac_addrs == NULL) {
4506 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4510 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4514 /* Generate a random MAC address, if none was assigned by PF */
4515 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4516 bnxt_eth_hw_addr_random(bp->mac_addr);
4518 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4519 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4520 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4522 rc = bnxt_hwrm_set_mac(bp);
4524 memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4525 RTE_ETHER_ADDR_LEN);
4529 /* Copy the permanent MAC from the FUNC_QCAPS response */
4530 memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4531 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4536 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4540 /* MAC is already configured in FW */
4541 if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4544 /* Restore the old MAC configured */
4545 rc = bnxt_hwrm_set_mac(bp);
4547 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4552 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4557 #define ALLOW_FUNC(x) \
4559 uint32_t arg = (x); \
4560 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4561 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4564 /* Forward all requests if firmware is new enough */
4565 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4566 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4567 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4568 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4570 PMD_DRV_LOG(WARNING,
4571 "Firmware too old for VF mailbox functionality\n");
4572 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4576 * The following are used for driver cleanup. If we disallow these,
4577 * VF drivers can't clean up cleanly.
4579 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4580 ALLOW_FUNC(HWRM_VNIC_FREE);
4581 ALLOW_FUNC(HWRM_RING_FREE);
4582 ALLOW_FUNC(HWRM_RING_GRP_FREE);
4583 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4584 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4585 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4586 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4587 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4590 static int bnxt_init_fw(struct bnxt *bp)
4597 rc = bnxt_hwrm_ver_get(bp);
4601 rc = bnxt_hwrm_func_reset(bp);
4605 rc = bnxt_hwrm_vnic_qcaps(bp);
4609 rc = bnxt_hwrm_queue_qportcfg(bp);
4613 /* Get the MAX capabilities for this function.
4614 * This function also allocates context memory for TQM rings and
4615 * informs the firmware about this allocated backing store memory.
4617 rc = bnxt_hwrm_func_qcaps(bp);
4621 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4625 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4629 /* Get the adapter error recovery support info */
4630 rc = bnxt_hwrm_error_recovery_qcfg(bp);
4632 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4634 bnxt_hwrm_port_led_qcaps(bp);
4640 bnxt_init_locks(struct bnxt *bp)
4644 err = pthread_mutex_init(&bp->flow_lock, NULL);
4646 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4650 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4652 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4656 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4660 rc = bnxt_init_fw(bp);
4664 if (!reconfig_dev) {
4665 rc = bnxt_setup_mac_addr(bp->eth_dev);
4669 rc = bnxt_restore_dflt_mac(bp);
4674 bnxt_config_vf_req_fwd(bp);
4676 rc = bnxt_hwrm_func_driver_register(bp);
4678 PMD_DRV_LOG(ERR, "Failed to register driver");
4683 if (bp->pdev->max_vfs) {
4684 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4686 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4690 rc = bnxt_hwrm_allocate_pf_only(bp);
4693 "Failed to allocate PF resources");
4699 rc = bnxt_alloc_mem(bp, reconfig_dev);
4703 rc = bnxt_setup_int(bp);
4707 rc = bnxt_request_int(bp);
4711 rc = bnxt_init_locks(bp);
4719 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4721 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4722 static int version_printed;
4726 if (version_printed++ == 0)
4727 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4729 eth_dev->dev_ops = &bnxt_dev_ops;
4730 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4731 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4734 * For secondary processes, we don't initialise any further
4735 * as primary has already done this work.
4737 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4740 rte_eth_copy_pci_info(eth_dev, pci_dev);
4742 bp = eth_dev->data->dev_private;
4744 bp->dev_stopped = 1;
4745 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
4747 if (bnxt_vf_pciid(pci_dev->id.device_id))
4748 bp->flags |= BNXT_FLAG_VF;
4750 if (bnxt_thor_device(pci_dev->id.device_id))
4751 bp->flags |= BNXT_FLAG_THOR_CHIP;
4753 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4754 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4755 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4756 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4757 bp->flags |= BNXT_FLAG_STINGRAY;
4759 rc = bnxt_init_board(eth_dev);
4762 "Failed to initialize board rc: %x\n", rc);
4766 rc = bnxt_alloc_hwrm_resources(bp);
4769 "Failed to allocate hwrm resource rc: %x\n", rc);
4772 rc = bnxt_init_resources(bp, false);
4776 rc = bnxt_alloc_stats_mem(bp);
4781 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4782 pci_dev->mem_resource[0].phys_addr,
4783 pci_dev->mem_resource[0].addr);
4788 bnxt_dev_uninit(eth_dev);
4793 bnxt_uninit_locks(struct bnxt *bp)
4795 pthread_mutex_destroy(&bp->flow_lock);
4796 pthread_mutex_destroy(&bp->def_cp_lock);
4800 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4805 bnxt_free_mem(bp, reconfig_dev);
4806 bnxt_hwrm_func_buf_unrgtr(bp);
4807 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4808 bp->flags &= ~BNXT_FLAG_REGISTERED;
4809 bnxt_free_ctx_mem(bp);
4810 if (!reconfig_dev) {
4811 bnxt_free_hwrm_resources(bp);
4813 if (bp->recovery_info != NULL) {
4814 rte_free(bp->recovery_info);
4815 bp->recovery_info = NULL;
4819 bnxt_uninit_locks(bp);
4820 rte_free(bp->ptp_cfg);
4826 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4828 struct bnxt *bp = eth_dev->data->dev_private;
4831 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4834 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4836 rc = bnxt_uninit_resources(bp, false);
4838 if (bp->tx_mem_zone) {
4839 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4840 bp->tx_mem_zone = NULL;
4843 if (bp->rx_mem_zone) {
4844 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4845 bp->rx_mem_zone = NULL;
4848 if (bp->dev_stopped == 0)
4849 bnxt_dev_close_op(eth_dev);
4851 rte_free(bp->pf.vf_info);
4852 eth_dev->dev_ops = NULL;
4853 eth_dev->rx_pkt_burst = NULL;
4854 eth_dev->tx_pkt_burst = NULL;
4859 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4860 struct rte_pci_device *pci_dev)
4862 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4866 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4868 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4869 return rte_eth_dev_pci_generic_remove(pci_dev,
4872 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4875 static struct rte_pci_driver bnxt_rte_pmd = {
4876 .id_table = bnxt_pci_id_map,
4877 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4878 .probe = bnxt_pci_probe,
4879 .remove = bnxt_pci_remove,
4883 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4885 if (strcmp(dev->device->driver->name, drv->driver.name))
4891 bool is_bnxt_supported(struct rte_eth_dev *dev)
4893 return is_device_supported(dev, &bnxt_rte_pmd);
4896 RTE_INIT(bnxt_init_log)
4898 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4899 if (bnxt_logtype_driver >= 0)
4900 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4903 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4904 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4905 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");