drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <ethdev_driver.h>
  11 #include <ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16 #include <rte_vect.h>
  17
  18 #include "bnxt.h"
  19 #include "bnxt_filter.h"
  20 #include "bnxt_hwrm.h"
  21 #include "bnxt_irq.h"
  22 #include "bnxt_reps.h"
  23 #include "bnxt_ring.h"
  24 #include "bnxt_rxq.h"
  25 #include "bnxt_rxr.h"
  26 #include "bnxt_stats.h"
  27 #include "bnxt_txq.h"
  28 #include "bnxt_txr.h"
  29 #include "bnxt_vnic.h"
  30 #include "hsi_struct_def_dpdk.h"
  31 #include "bnxt_nvm_defs.h"
  32 #include "bnxt_tf_common.h"
  33 #include "ulp_flow_db.h"
  34 #include "rte_pmd_bnxt.h"
  35
  36 #define DRV_MODULE_NAME         "bnxt"
  37 static const char bnxt_version[] =
  38         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  39
  40 /*
  41  * The set of PCI devices this driver supports
  42  */
  43 static const struct rte_pci_id bnxt_pci_id_map[] = {
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  47                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
  87         { .vendor_id = 0, /* sentinel */ },
  88 };
  89
  90 #define BNXT_DEVARG_ACCUM_STATS "accum-stats"
  91 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
  92 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
  93 #define BNXT_DEVARG_REPRESENTOR "representor"
  94 #define BNXT_DEVARG_REP_BASED_PF  "rep-based-pf"
  95 #define BNXT_DEVARG_REP_IS_PF  "rep-is-pf"
  96 #define BNXT_DEVARG_REP_Q_R2F  "rep-q-r2f"
  97 #define BNXT_DEVARG_REP_Q_F2R  "rep-q-f2r"
  98 #define BNXT_DEVARG_REP_FC_R2F  "rep-fc-r2f"
  99 #define BNXT_DEVARG_REP_FC_F2R  "rep-fc-f2r"
 100 #define BNXT_DEVARG_APP_ID      "app-id"
 101
 102 static const char *const bnxt_dev_args[] = {
 103         BNXT_DEVARG_REPRESENTOR,
 104         BNXT_DEVARG_ACCUM_STATS,
 105         BNXT_DEVARG_FLOW_XSTAT,
 106         BNXT_DEVARG_MAX_NUM_KFLOWS,
 107         BNXT_DEVARG_REP_BASED_PF,
 108         BNXT_DEVARG_REP_IS_PF,
 109         BNXT_DEVARG_REP_Q_R2F,
 110         BNXT_DEVARG_REP_Q_F2R,
 111         BNXT_DEVARG_REP_FC_R2F,
 112         BNXT_DEVARG_REP_FC_F2R,
 113         BNXT_DEVARG_APP_ID,
 114         NULL
 115 };
 116
 117 /*
 118  * accum-stats == false to disable flow counter accumulation
 119  * accum-stats == true to enable flow counter accumulation
 120  */
 121 #define BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats)    ((accum_stats) > 1)
 122
 123 /*
 124  * app-id = an non-negative 8-bit number
 125  */
 126 #define BNXT_DEVARG_APP_ID_INVALID(val)                 ((val) > 255)
 127
 128 /*
 129  * flow_xstat == false to disable the feature
 130  * flow_xstat == true to enable the feature
 131  */
 132 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 133
 134 /*
 135  * rep_is_pf == false to indicate VF representor
 136  * rep_is_pf == true to indicate PF representor
 137  */
 138 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)        ((rep_is_pf) > 1)
 139
 140 /*
 141  * rep_based_pf == Physical index of the PF
 142  */
 143 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)  ((rep_based_pf) > 15)
 144 /*
 145  * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
 146  */
 147 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)        ((rep_q_r2f) > 3)
 148
 149 /*
 150  * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
 151  */
 152 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)        ((rep_q_f2r) > 3)
 153
 154 /*
 155  * rep_fc_r2f == Flow control for the representor to endpoint direction
 156  */
 157 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)      ((rep_fc_r2f) > 1)
 158
 159 /*
 160  * rep_fc_f2r == Flow control for the endpoint to representor direction
 161  */
 162 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)      ((rep_fc_f2r) > 1)
 163
 164 int bnxt_cfa_code_dynfield_offset = -1;
 165
 166 /*
 167  * max_num_kflows must be >= 32
 168  * and must be a power-of-2 supported value
 169  * return: 1 -> invalid
 170  *         0 -> valid
 171  */
 172 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 173 {
 174         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 175                 return 1;
 176         return 0;
 177 }
 178
 179 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 180 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 181 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 182 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 183 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 184 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 185 static void bnxt_dev_recover(void *arg);
 186 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 187 static void bnxt_free_rep_info(struct bnxt *bp);
 188
 189 int is_bnxt_in_error(struct bnxt *bp)
 190 {
 191         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 192                 return -EIO;
 193         if (bp->flags & BNXT_FLAG_FW_RESET)
 194                 return -EBUSY;
 195
 196         return 0;
 197 }
 198
 199 /***********************/
 200
 201 /*
 202  * High level utility functions
 203  */
 204
 205 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 206 {
 207         unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
 208                                              BNXT_RSS_TBL_SIZE_P5);
 209
 210         if (!BNXT_CHIP_P5(bp))
 211                 return 1;
 212
 213         return RTE_ALIGN_MUL_CEIL(num_rss_rings,
 214                                   BNXT_RSS_ENTRIES_PER_CTX_P5) /
 215                                   BNXT_RSS_ENTRIES_PER_CTX_P5;
 216 }
 217
 218 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 219 {
 220         if (!BNXT_CHIP_P5(bp))
 221                 return HW_HASH_INDEX_SIZE;
 222
 223         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
 224 }
 225
 226 static void bnxt_free_parent_info(struct bnxt *bp)
 227 {
 228         rte_free(bp->parent);
 229         bp->parent = NULL;
 230 }
 231
 232 static void bnxt_free_pf_info(struct bnxt *bp)
 233 {
 234         rte_free(bp->pf);
 235         bp->pf = NULL;
 236 }
 237
 238 static void bnxt_free_link_info(struct bnxt *bp)
 239 {
 240         rte_free(bp->link_info);
 241         bp->link_info = NULL;
 242 }
 243
 244 static void bnxt_free_leds_info(struct bnxt *bp)
 245 {
 246         if (BNXT_VF(bp))
 247                 return;
 248
 249         rte_free(bp->leds);
 250         bp->leds = NULL;
 251 }
 252
 253 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 254 {
 255         rte_free(bp->flow_stat);
 256         bp->flow_stat = NULL;
 257 }
 258
 259 static void bnxt_free_cos_queues(struct bnxt *bp)
 260 {
 261         rte_free(bp->rx_cos_queue);
 262         bp->rx_cos_queue = NULL;
 263         rte_free(bp->tx_cos_queue);
 264         bp->tx_cos_queue = NULL;
 265 }
 266
 267 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 268 {
 269         bnxt_free_filter_mem(bp);
 270         bnxt_free_vnic_attributes(bp);
 271         bnxt_free_vnic_mem(bp);
 272
 273         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 274          * If the number of rings change across fw update,
 275          * we don't have much choice except to warn the user.
 276          */
 277         if (!reconfig) {
 278                 bnxt_free_stats(bp);
 279                 bnxt_free_tx_rings(bp);
 280                 bnxt_free_rx_rings(bp);
 281         }
 282         bnxt_free_async_cp_ring(bp);
 283         bnxt_free_rxtx_nq_ring(bp);
 284
 285         rte_free(bp->grp_info);
 286         bp->grp_info = NULL;
 287 }
 288
 289 static int bnxt_alloc_parent_info(struct bnxt *bp)
 290 {
 291         bp->parent = rte_zmalloc("bnxt_parent_info",
 292                                  sizeof(struct bnxt_parent_info), 0);
 293         if (bp->parent == NULL)
 294                 return -ENOMEM;
 295
 296         return 0;
 297 }
 298
 299 static int bnxt_alloc_pf_info(struct bnxt *bp)
 300 {
 301         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 302         if (bp->pf == NULL)
 303                 return -ENOMEM;
 304
 305         return 0;
 306 }
 307
 308 static int bnxt_alloc_link_info(struct bnxt *bp)
 309 {
 310         bp->link_info =
 311                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 312         if (bp->link_info == NULL)
 313                 return -ENOMEM;
 314
 315         return 0;
 316 }
 317
 318 static int bnxt_alloc_leds_info(struct bnxt *bp)
 319 {
 320         if (BNXT_VF(bp))
 321                 return 0;
 322
 323         bp->leds = rte_zmalloc("bnxt_leds",
 324                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 325                                0);
 326         if (bp->leds == NULL)
 327                 return -ENOMEM;
 328
 329         return 0;
 330 }
 331
 332 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 333 {
 334         bp->rx_cos_queue =
 335                 rte_zmalloc("bnxt_rx_cosq",
 336                             BNXT_COS_QUEUE_COUNT *
 337                             sizeof(struct bnxt_cos_queue_info),
 338                             0);
 339         if (bp->rx_cos_queue == NULL)
 340                 return -ENOMEM;
 341
 342         bp->tx_cos_queue =
 343                 rte_zmalloc("bnxt_tx_cosq",
 344                             BNXT_COS_QUEUE_COUNT *
 345                             sizeof(struct bnxt_cos_queue_info),
 346                             0);
 347         if (bp->tx_cos_queue == NULL)
 348                 return -ENOMEM;
 349
 350         return 0;
 351 }
 352
 353 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 354 {
 355         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 356                                     sizeof(struct bnxt_flow_stat_info), 0);
 357         if (bp->flow_stat == NULL)
 358                 return -ENOMEM;
 359
 360         return 0;
 361 }
 362
 363 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 364 {
 365         int rc;
 366
 367         rc = bnxt_alloc_ring_grps(bp);
 368         if (rc)
 369                 goto alloc_mem_err;
 370
 371         rc = bnxt_alloc_async_ring_struct(bp);
 372         if (rc)
 373                 goto alloc_mem_err;
 374
 375         rc = bnxt_alloc_vnic_mem(bp);
 376         if (rc)
 377                 goto alloc_mem_err;
 378
 379         rc = bnxt_alloc_vnic_attributes(bp);
 380         if (rc)
 381                 goto alloc_mem_err;
 382
 383         rc = bnxt_alloc_filter_mem(bp);
 384         if (rc)
 385                 goto alloc_mem_err;
 386
 387         rc = bnxt_alloc_async_cp_ring(bp);
 388         if (rc)
 389                 goto alloc_mem_err;
 390
 391         rc = bnxt_alloc_rxtx_nq_ring(bp);
 392         if (rc)
 393                 goto alloc_mem_err;
 394
 395         if (BNXT_FLOW_XSTATS_EN(bp)) {
 396                 rc = bnxt_alloc_flow_stats_info(bp);
 397                 if (rc)
 398                         goto alloc_mem_err;
 399         }
 400
 401         return 0;
 402
 403 alloc_mem_err:
 404         bnxt_free_mem(bp, reconfig);
 405         return rc;
 406 }
 407
 408 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 409 {
 410         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 411         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 412         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 413         struct bnxt_rx_queue *rxq;
 414         unsigned int j;
 415         int rc;
 416
 417         rc = bnxt_vnic_grp_alloc(bp, vnic);
 418         if (rc)
 419                 goto err_out;
 420
 421         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 422                     vnic_id, vnic, vnic->fw_grp_ids);
 423
 424         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 425         if (rc)
 426                 goto err_out;
 427
 428         /* Alloc RSS context only if RSS mode is enabled */
 429         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 430                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 431
 432                 /* RSS table size in Thor is 512.
 433                  * Cap max Rx rings to same value
 434                  */
 435                 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
 436                         PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
 437                                     bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
 438                         goto err_out;
 439                 }
 440
 441                 rc = 0;
 442                 for (j = 0; j < nr_ctxs; j++) {
 443                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 444                         if (rc)
 445                                 break;
 446                 }
 447                 if (rc) {
 448                         PMD_DRV_LOG(ERR,
 449                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 450                                     vnic_id, j, rc);
 451                         goto err_out;
 452                 }
 453                 vnic->num_lb_ctxts = nr_ctxs;
 454         }
 455
 456         /*
 457          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 458          * setting is not available at this time, it will not be
 459          * configured correctly in the CFA.
 460          */
 461         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 462                 vnic->vlan_strip = true;
 463         else
 464                 vnic->vlan_strip = false;
 465
 466         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 467         if (rc)
 468                 goto err_out;
 469
 470         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 471         if (rc)
 472                 goto err_out;
 473
 474         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 475                 rxq = bp->eth_dev->data->rx_queues[j];
 476
 477                 PMD_DRV_LOG(DEBUG,
 478                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 479                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 480
 481                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 482                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 483                 else
 484                         vnic->rx_queue_cnt++;
 485         }
 486
 487         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 488
 489         rc = bnxt_vnic_rss_configure(bp, vnic);
 490         if (rc)
 491                 goto err_out;
 492
 493         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 494
 495         rc = bnxt_hwrm_vnic_tpa_cfg(bp, vnic,
 496                                     (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) ?
 497                                     true : false);
 498         if (rc)
 499                 goto err_out;
 500
 501         return 0;
 502 err_out:
 503         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 504                     vnic_id, rc);
 505         return rc;
 506 }
 507
 508 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 509 {
 510         int rc = 0;
 511
 512         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 513                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 514         if (rc)
 515                 return rc;
 516
 517         PMD_DRV_LOG(DEBUG,
 518                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 519                     " rx_fc_in_tbl.ctx_id = %d\n",
 520                     bp->flow_stat->rx_fc_in_tbl.va,
 521                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 522                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 523
 524         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 525                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 526         if (rc)
 527                 return rc;
 528
 529         PMD_DRV_LOG(DEBUG,
 530                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 531                     " rx_fc_out_tbl.ctx_id = %d\n",
 532                     bp->flow_stat->rx_fc_out_tbl.va,
 533                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 534                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 535
 536         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 537                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 538         if (rc)
 539                 return rc;
 540
 541         PMD_DRV_LOG(DEBUG,
 542                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 543                     " tx_fc_in_tbl.ctx_id = %d\n",
 544                     bp->flow_stat->tx_fc_in_tbl.va,
 545                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 546                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 547
 548         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 549                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 550         if (rc)
 551                 return rc;
 552
 553         PMD_DRV_LOG(DEBUG,
 554                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 555                     " tx_fc_out_tbl.ctx_id = %d\n",
 556                     bp->flow_stat->tx_fc_out_tbl.va,
 557                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 558                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 559
 560         memset(bp->flow_stat->rx_fc_out_tbl.va,
 561                0,
 562                bp->flow_stat->rx_fc_out_tbl.size);
 563         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 564                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 565                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 566                                        bp->flow_stat->max_fc,
 567                                        true);
 568         if (rc)
 569                 return rc;
 570
 571         memset(bp->flow_stat->tx_fc_out_tbl.va,
 572                0,
 573                bp->flow_stat->tx_fc_out_tbl.size);
 574         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 575                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 576                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 577                                        bp->flow_stat->max_fc,
 578                                        true);
 579
 580         return rc;
 581 }
 582
 583 static int bnxt_alloc_ctx_mem_buf(struct bnxt *bp, char *type, size_t size,
 584                                   struct bnxt_ctx_mem_buf_info *ctx)
 585 {
 586         if (!ctx)
 587                 return -EINVAL;
 588
 589         ctx->va = rte_zmalloc_socket(type, size, 0,
 590                                      bp->eth_dev->device->numa_node);
 591         if (ctx->va == NULL)
 592                 return -ENOMEM;
 593         rte_mem_lock_page(ctx->va);
 594         ctx->size = size;
 595         ctx->dma = rte_mem_virt2iova(ctx->va);
 596         if (ctx->dma == RTE_BAD_IOVA)
 597                 return -ENOMEM;
 598
 599         return 0;
 600 }
 601
 602 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 603 {
 604         struct rte_pci_device *pdev = bp->pdev;
 605         char type[RTE_MEMZONE_NAMESIZE];
 606         uint16_t max_fc;
 607         int rc = 0;
 608
 609         max_fc = bp->flow_stat->max_fc;
 610
 611         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 612                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 613         /* 4 bytes for each counter-id */
 614         rc = bnxt_alloc_ctx_mem_buf(bp, type,
 615                                     max_fc * 4,
 616                                     &bp->flow_stat->rx_fc_in_tbl);
 617         if (rc)
 618                 return rc;
 619
 620         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 621                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 622         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 623         rc = bnxt_alloc_ctx_mem_buf(bp, type,
 624                                     max_fc * 16,
 625                                     &bp->flow_stat->rx_fc_out_tbl);
 626         if (rc)
 627                 return rc;
 628
 629         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 630                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 631         /* 4 bytes for each counter-id */
 632         rc = bnxt_alloc_ctx_mem_buf(bp, type,
 633                                     max_fc * 4,
 634                                     &bp->flow_stat->tx_fc_in_tbl);
 635         if (rc)
 636                 return rc;
 637
 638         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 639                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 640         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 641         rc = bnxt_alloc_ctx_mem_buf(bp, type,
 642                                     max_fc * 16,
 643                                     &bp->flow_stat->tx_fc_out_tbl);
 644         if (rc)
 645                 return rc;
 646
 647         rc = bnxt_register_fc_ctx_mem(bp);
 648
 649         return rc;
 650 }
 651
 652 static int bnxt_init_ctx_mem(struct bnxt *bp)
 653 {
 654         int rc = 0;
 655
 656         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 657             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 658             !BNXT_FLOW_XSTATS_EN(bp))
 659                 return 0;
 660
 661         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 662         if (rc)
 663                 return rc;
 664
 665         rc = bnxt_init_fc_ctx_mem(bp);
 666
 667         return rc;
 668 }
 669
 670 static int bnxt_update_phy_setting(struct bnxt *bp)
 671 {
 672         struct rte_eth_link new;
 673         int rc;
 674
 675         rc = bnxt_get_hwrm_link_config(bp, &new);
 676         if (rc) {
 677                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 678                 return rc;
 679         }
 680
 681         /*
 682          * On BCM957508-N2100 adapters, FW will not allow any user other
 683          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 684          * always returns link up. Force phy update always in that case.
 685          */
 686         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 687                 rc = bnxt_set_hwrm_link_config(bp, true);
 688                 if (rc) {
 689                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 690                         return rc;
 691                 }
 692         }
 693
 694         return rc;
 695 }
 696
 697 static void bnxt_free_prev_ring_stats(struct bnxt *bp)
 698 {
 699         rte_free(bp->prev_rx_ring_stats);
 700         rte_free(bp->prev_tx_ring_stats);
 701
 702         bp->prev_rx_ring_stats = NULL;
 703         bp->prev_tx_ring_stats = NULL;
 704 }
 705
 706 static int bnxt_alloc_prev_ring_stats(struct bnxt *bp)
 707 {
 708         bp->prev_rx_ring_stats =  rte_zmalloc("bnxt_prev_rx_ring_stats",
 709                                               sizeof(struct bnxt_ring_stats) *
 710                                               bp->rx_cp_nr_rings,
 711                                               0);
 712         if (bp->prev_rx_ring_stats == NULL)
 713                 return -ENOMEM;
 714
 715         bp->prev_tx_ring_stats = rte_zmalloc("bnxt_prev_tx_ring_stats",
 716                                              sizeof(struct bnxt_ring_stats) *
 717                                              bp->tx_cp_nr_rings,
 718                                              0);
 719         if (bp->prev_tx_ring_stats == NULL)
 720                 goto error;
 721
 722         return 0;
 723
 724 error:
 725         bnxt_free_prev_ring_stats(bp);
 726         return -ENOMEM;
 727 }
 728
 729 static int bnxt_start_nic(struct bnxt *bp)
 730 {
 731         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 732         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 733         uint32_t intr_vector = 0;
 734         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 735         uint32_t vec = BNXT_MISC_VEC_ID;
 736         unsigned int i, j;
 737         int rc;
 738
 739         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 740                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 741                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 742                 bp->flags |= BNXT_FLAG_JUMBO;
 743         } else {
 744                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 745                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 746                 bp->flags &= ~BNXT_FLAG_JUMBO;
 747         }
 748
 749         /* THOR does not support ring groups.
 750          * But we will use the array to save RSS context IDs.
 751          */
 752         if (BNXT_CHIP_P5(bp))
 753                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
 754
 755         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 756         if (rc) {
 757                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 758                 goto err_out;
 759         }
 760
 761         rc = bnxt_alloc_hwrm_rings(bp);
 762         if (rc) {
 763                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 764                 goto err_out;
 765         }
 766
 767         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 768         if (rc) {
 769                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 770                 goto err_out;
 771         }
 772
 773         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 774                 goto skip_cosq_cfg;
 775
 776         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 777                 if (bp->rx_cos_queue[i].id != 0xff) {
 778                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 779
 780                         if (!vnic) {
 781                                 PMD_DRV_LOG(ERR,
 782                                             "Num pools more than FW profile\n");
 783                                 rc = -EINVAL;
 784                                 goto err_out;
 785                         }
 786                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 787                         bp->rx_cosq_cnt++;
 788                 }
 789         }
 790
 791 skip_cosq_cfg:
 792         rc = bnxt_mq_rx_configure(bp);
 793         if (rc) {
 794                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 795                 goto err_out;
 796         }
 797
 798         /* default vnic 0 */
 799         rc = bnxt_setup_one_vnic(bp, 0);
 800         if (rc)
 801                 goto err_out;
 802         /* VNIC configuration */
 803         if (BNXT_RFS_NEEDS_VNIC(bp)) {
 804                 for (i = 1; i < bp->nr_vnics; i++) {
 805                         rc = bnxt_setup_one_vnic(bp, i);
 806                         if (rc)
 807                                 goto err_out;
 808                 }
 809         }
 810
 811         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 812         if (rc) {
 813                 PMD_DRV_LOG(ERR,
 814                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 815                 goto err_out;
 816         }
 817
 818         /* check and configure queue intr-vector mapping */
 819         if ((rte_intr_cap_multiple(intr_handle) ||
 820              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 821             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 822                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 823                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 824                 if (intr_vector > bp->rx_cp_nr_rings) {
 825                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 826                                         bp->rx_cp_nr_rings);
 827                         return -ENOTSUP;
 828                 }
 829                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 830                 if (rc)
 831                         return rc;
 832         }
 833
 834         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 835                 intr_handle->intr_vec =
 836                         rte_zmalloc("intr_vec",
 837                                     bp->eth_dev->data->nb_rx_queues *
 838                                     sizeof(int), 0);
 839                 if (intr_handle->intr_vec == NULL) {
 840                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 841                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 842                         rc = -ENOMEM;
 843                         goto err_out;
 844                 }
 845                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 846                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 847                          intr_handle->intr_vec, intr_handle->nb_efd,
 848                         intr_handle->max_intr);
 849                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 850                      queue_id++) {
 851                         intr_handle->intr_vec[queue_id] =
 852                                                         vec + BNXT_RX_VEC_START;
 853                         if (vec < base + intr_handle->nb_efd - 1)
 854                                 vec++;
 855                 }
 856         }
 857
 858         /* enable uio/vfio intr/eventfd mapping */
 859         rc = rte_intr_enable(intr_handle);
 860 #ifndef RTE_EXEC_ENV_FREEBSD
 861         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 862         if (rc)
 863                 goto err_out;
 864 #endif
 865
 866         rc = bnxt_update_phy_setting(bp);
 867         if (rc)
 868                 goto err_out;
 869
 870         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 871         if (!bp->mark_table)
 872                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 873
 874         return 0;
 875
 876 err_out:
 877         /* Some of the error status returned by FW may not be from errno.h */
 878         if (rc > 0)
 879                 rc = -EIO;
 880
 881         return rc;
 882 }
 883
 884 static int bnxt_shutdown_nic(struct bnxt *bp)
 885 {
 886         bnxt_free_all_hwrm_resources(bp);
 887         bnxt_free_all_filters(bp);
 888         bnxt_free_all_vnics(bp);
 889         return 0;
 890 }
 891
 892 /*
 893  * Device configuration and status function
 894  */
 895
 896 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 897 {
 898         uint32_t link_speed = 0;
 899         uint32_t speed_capa = 0;
 900
 901         if (bp->link_info == NULL)
 902                 return 0;
 903
 904         link_speed = bp->link_info->support_speeds;
 905
 906         /* If PAM4 is configured, use PAM4 supported speed */
 907         if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
 908                 link_speed = bp->link_info->support_pam4_speeds;
 909
 910         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 911                 speed_capa |= ETH_LINK_SPEED_100M;
 912         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 913                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 914         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 915                 speed_capa |= ETH_LINK_SPEED_1G;
 916         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 917                 speed_capa |= ETH_LINK_SPEED_2_5G;
 918         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 919                 speed_capa |= ETH_LINK_SPEED_10G;
 920         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 921                 speed_capa |= ETH_LINK_SPEED_20G;
 922         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 923                 speed_capa |= ETH_LINK_SPEED_25G;
 924         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 925                 speed_capa |= ETH_LINK_SPEED_40G;
 926         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 927                 speed_capa |= ETH_LINK_SPEED_50G;
 928         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 929                 speed_capa |= ETH_LINK_SPEED_100G;
 930         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
 931                 speed_capa |= ETH_LINK_SPEED_50G;
 932         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
 933                 speed_capa |= ETH_LINK_SPEED_100G;
 934         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
 935                 speed_capa |= ETH_LINK_SPEED_200G;
 936
 937         if (bp->link_info->auto_mode ==
 938             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 939                 speed_capa |= ETH_LINK_SPEED_FIXED;
 940
 941         return speed_capa;
 942 }
 943
 944 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 945                                 struct rte_eth_dev_info *dev_info)
 946 {
 947         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 948         struct bnxt *bp = eth_dev->data->dev_private;
 949         uint16_t max_vnics, i, j, vpool, vrxq;
 950         unsigned int max_rx_rings;
 951         int rc;
 952
 953         rc = is_bnxt_in_error(bp);
 954         if (rc)
 955                 return rc;
 956
 957         /* MAC Specifics */
 958         dev_info->max_mac_addrs = bp->max_l2_ctx;
 959         dev_info->max_hash_mac_addrs = 0;
 960
 961         /* PF/VF specifics */
 962         if (BNXT_PF(bp))
 963                 dev_info->max_vfs = pdev->max_vfs;
 964
 965         max_rx_rings = bnxt_max_rings(bp);
 966         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 967         dev_info->max_rx_queues = max_rx_rings;
 968         dev_info->max_tx_queues = max_rx_rings;
 969         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 970         dev_info->hash_key_size = HW_HASH_KEY_SIZE;
 971         max_vnics = bp->max_vnics;
 972
 973         /* MTU specifics */
 974         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 975         dev_info->max_mtu = BNXT_MAX_MTU;
 976
 977         /* Fast path specifics */
 978         dev_info->min_rx_bufsize = 1;
 979         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 980
 981         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 982         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 983                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 984         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 985         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
 986                                     dev_info->tx_queue_offload_capa;
 987         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 988
 989         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 990         dev_info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
 991                              RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
 992
 993         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 994                 .rx_thresh = {
 995                         .pthresh = 8,
 996                         .hthresh = 8,
 997                         .wthresh = 0,
 998                 },
 999                 .rx_free_thresh = 32,
1000                 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
1001         };
1002
1003         dev_info->default_txconf = (struct rte_eth_txconf) {
1004                 .tx_thresh = {
1005                         .pthresh = 32,
1006                         .hthresh = 0,
1007                         .wthresh = 0,
1008                 },
1009                 .tx_free_thresh = 32,
1010                 .tx_rs_thresh = 32,
1011         };
1012         eth_dev->data->dev_conf.intr_conf.lsc = 1;
1013
1014         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
1015         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
1016         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
1017         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
1018
1019         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
1020                 dev_info->switch_info.name = eth_dev->device->name;
1021                 dev_info->switch_info.domain_id = bp->switch_domain_id;
1022                 dev_info->switch_info.port_id =
1023                                 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
1024                                     BNXT_SWITCH_PORT_ID_TRUSTED_VF;
1025         }
1026
1027         /*
1028          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
1029          *       need further investigation.
1030          */
1031
1032         /* VMDq resources */
1033         vpool = 64; /* ETH_64_POOLS */
1034         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
1035         for (i = 0; i < 4; vpool >>= 1, i++) {
1036                 if (max_vnics > vpool) {
1037                         for (j = 0; j < 5; vrxq >>= 1, j++) {
1038                                 if (dev_info->max_rx_queues > vrxq) {
1039                                         if (vpool > vrxq)
1040                                                 vpool = vrxq;
1041                                         goto found;
1042                                 }
1043                         }
1044                         /* Not enough resources to support VMDq */
1045                         break;
1046                 }
1047         }
1048         /* Not enough resources to support VMDq */
1049         vpool = 0;
1050         vrxq = 0;
1051 found:
1052         dev_info->max_vmdq_pools = vpool;
1053         dev_info->vmdq_queue_num = vrxq;
1054
1055         dev_info->vmdq_pool_base = 0;
1056         dev_info->vmdq_queue_base = 0;
1057
1058         return 0;
1059 }
1060
1061 /* Configure the device based on the configuration provided */
1062 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1063 {
1064         struct bnxt *bp = eth_dev->data->dev_private;
1065         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1066         int rc;
1067
1068         bp->rx_queues = (void *)eth_dev->data->rx_queues;
1069         bp->tx_queues = (void *)eth_dev->data->tx_queues;
1070         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1071         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1072
1073         rc = is_bnxt_in_error(bp);
1074         if (rc)
1075                 return rc;
1076
1077         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1078                 rc = bnxt_hwrm_check_vf_rings(bp);
1079                 if (rc) {
1080                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1081                         return -ENOSPC;
1082                 }
1083
1084                 /* If a resource has already been allocated - in this case
1085                  * it is the async completion ring, free it. Reallocate it after
1086                  * resource reservation. This will ensure the resource counts
1087                  * are calculated correctly.
1088                  */
1089
1090                 pthread_mutex_lock(&bp->def_cp_lock);
1091
1092                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1093                         bnxt_disable_int(bp);
1094                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
1095                 }
1096
1097                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1098                 if (rc) {
1099                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1100                         pthread_mutex_unlock(&bp->def_cp_lock);
1101                         return -ENOSPC;
1102                 }
1103
1104                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1105                         rc = bnxt_alloc_async_cp_ring(bp);
1106                         if (rc) {
1107                                 pthread_mutex_unlock(&bp->def_cp_lock);
1108                                 return rc;
1109                         }
1110                         bnxt_enable_int(bp);
1111                 }
1112
1113                 pthread_mutex_unlock(&bp->def_cp_lock);
1114         }
1115
1116         /* Inherit new configurations */
1117         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1118             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1119             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1120                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1121             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1122             bp->max_stat_ctx)
1123                 goto resource_error;
1124
1125         if (BNXT_HAS_RING_GRPS(bp) &&
1126             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1127                 goto resource_error;
1128
1129         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1130             bp->max_vnics < eth_dev->data->nb_rx_queues)
1131                 goto resource_error;
1132
1133         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1134         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1135
1136         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1137                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1138         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1139
1140         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1141                 eth_dev->data->mtu =
1142                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1143                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1144                         BNXT_NUM_VLANS;
1145                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1146         }
1147         return 0;
1148
1149 resource_error:
1150         PMD_DRV_LOG(ERR,
1151                     "Insufficient resources to support requested config\n");
1152         PMD_DRV_LOG(ERR,
1153                     "Num Queues Requested: Tx %d, Rx %d\n",
1154                     eth_dev->data->nb_tx_queues,
1155                     eth_dev->data->nb_rx_queues);
1156         PMD_DRV_LOG(ERR,
1157                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1158                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1159                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1160         return -ENOSPC;
1161 }
1162
1163 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1164 {
1165         struct rte_eth_link *link = &eth_dev->data->dev_link;
1166
1167         if (link->link_status)
1168                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1169                         eth_dev->data->port_id,
1170                         (uint32_t)link->link_speed,
1171                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1172                         ("full-duplex") : ("half-duplex\n"));
1173         else
1174                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1175                         eth_dev->data->port_id);
1176 }
1177
1178 /*
1179  * Determine whether the current configuration requires support for scattered
1180  * receive; return 1 if scattered receive is required and 0 if not.
1181  */
1182 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1183 {
1184         uint16_t buf_size;
1185         int i;
1186
1187         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1188                 return 1;
1189
1190         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO)
1191                 return 1;
1192
1193         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1194                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1195
1196                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1197                                       RTE_PKTMBUF_HEADROOM);
1198                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1199                         return 1;
1200         }
1201         return 0;
1202 }
1203
1204 static eth_rx_burst_t
1205 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1206 {
1207         struct bnxt *bp = eth_dev->data->dev_private;
1208
1209         /* Disable vector mode RX for Stingray2 for now */
1210         if (BNXT_CHIP_SR2(bp)) {
1211                 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1212                 return bnxt_recv_pkts;
1213         }
1214
1215 #if (defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)) && \
1216         !defined(RTE_LIBRTE_IEEE1588)
1217
1218         /* Vector mode receive cannot be enabled if scattered rx is in use. */
1219         if (eth_dev->data->scattered_rx)
1220                 goto use_scalar_rx;
1221
1222         /*
1223          * Vector mode receive cannot be enabled if Truflow is enabled or if
1224          * asynchronous completions and receive completions can be placed in
1225          * the same completion ring.
1226          */
1227         if (BNXT_TRUFLOW_EN(bp) || !BNXT_NUM_ASYNC_CPR(bp))
1228                 goto use_scalar_rx;
1229
1230         /*
1231          * Vector mode receive cannot be enabled if any receive offloads outside
1232          * a limited subset have been enabled.
1233          */
1234         if (eth_dev->data->dev_conf.rxmode.offloads &
1235                 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1236                   DEV_RX_OFFLOAD_KEEP_CRC |
1237                   DEV_RX_OFFLOAD_JUMBO_FRAME |
1238                   DEV_RX_OFFLOAD_IPV4_CKSUM |
1239                   DEV_RX_OFFLOAD_UDP_CKSUM |
1240                   DEV_RX_OFFLOAD_TCP_CKSUM |
1241                   DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1242                   DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1243                   DEV_RX_OFFLOAD_RSS_HASH |
1244                   DEV_RX_OFFLOAD_VLAN_FILTER))
1245                 goto use_scalar_rx;
1246
1247 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1248         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1249             rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1250                 PMD_DRV_LOG(INFO,
1251                             "Using AVX2 vector mode receive for port %d\n",
1252                             eth_dev->data->port_id);
1253                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1254                 return bnxt_recv_pkts_vec_avx2;
1255         }
1256  #endif
1257         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1258                 PMD_DRV_LOG(INFO,
1259                             "Using SSE vector mode receive for port %d\n",
1260                             eth_dev->data->port_id);
1261                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1262                 return bnxt_recv_pkts_vec;
1263         }
1264
1265 use_scalar_rx:
1266         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1267                     eth_dev->data->port_id);
1268         PMD_DRV_LOG(INFO,
1269                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1270                     eth_dev->data->port_id,
1271                     eth_dev->data->scattered_rx,
1272                     eth_dev->data->dev_conf.rxmode.offloads);
1273 #endif
1274         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1275         return bnxt_recv_pkts;
1276 }
1277
1278 static eth_tx_burst_t
1279 bnxt_transmit_function(struct rte_eth_dev *eth_dev)
1280 {
1281         struct bnxt *bp = eth_dev->data->dev_private;
1282
1283         /* Disable vector mode TX for Stingray2 for now */
1284         if (BNXT_CHIP_SR2(bp))
1285                 return bnxt_xmit_pkts;
1286
1287 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) && \
1288         !defined(RTE_LIBRTE_IEEE1588)
1289         uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1290
1291         /*
1292          * Vector mode transmit can be enabled only if not using scatter rx
1293          * or tx offloads.
1294          */
1295         if (eth_dev->data->scattered_rx ||
1296             (offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) ||
1297             BNXT_TRUFLOW_EN(bp))
1298                 goto use_scalar_tx;
1299
1300 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1301         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1302             rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1303                 PMD_DRV_LOG(INFO,
1304                             "Using AVX2 vector mode transmit for port %d\n",
1305                             eth_dev->data->port_id);
1306                 return bnxt_xmit_pkts_vec_avx2;
1307         }
1308 #endif
1309         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1310                 PMD_DRV_LOG(INFO,
1311                             "Using SSE vector mode transmit for port %d\n",
1312                             eth_dev->data->port_id);
1313                 return bnxt_xmit_pkts_vec;
1314         }
1315
1316 use_scalar_tx:
1317         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1318                     eth_dev->data->port_id);
1319         PMD_DRV_LOG(INFO,
1320                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1321                     eth_dev->data->port_id,
1322                     eth_dev->data->scattered_rx,
1323                     offloads);
1324 #endif
1325         return bnxt_xmit_pkts;
1326 }
1327
1328 static int bnxt_handle_if_change_status(struct bnxt *bp)
1329 {
1330         int rc;
1331
1332         /* Since fw has undergone a reset and lost all contexts,
1333          * set fatal flag to not issue hwrm during cleanup
1334          */
1335         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1336         bnxt_uninit_resources(bp, true);
1337
1338         /* clear fatal flag so that re-init happens */
1339         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1340         rc = bnxt_init_resources(bp, true);
1341
1342         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1343
1344         return rc;
1345 }
1346
1347 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1348 {
1349         struct bnxt *bp = eth_dev->data->dev_private;
1350         int rc = 0;
1351
1352         if (!BNXT_SINGLE_PF(bp))
1353                 return -ENOTSUP;
1354
1355         if (!bp->link_info->link_up)
1356                 rc = bnxt_set_hwrm_link_config(bp, true);
1357         if (!rc)
1358                 eth_dev->data->dev_link.link_status = 1;
1359
1360         bnxt_print_link_info(eth_dev);
1361         return rc;
1362 }
1363
1364 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1365 {
1366         struct bnxt *bp = eth_dev->data->dev_private;
1367
1368         if (!BNXT_SINGLE_PF(bp))
1369                 return -ENOTSUP;
1370
1371         eth_dev->data->dev_link.link_status = 0;
1372         bnxt_set_hwrm_link_config(bp, false);
1373         bp->link_info->link_up = 0;
1374
1375         return 0;
1376 }
1377
1378 static void bnxt_free_switch_domain(struct bnxt *bp)
1379 {
1380         int rc = 0;
1381
1382         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)))
1383                 return;
1384
1385         rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1386         if (rc)
1387                 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1388                             bp->switch_domain_id, rc);
1389 }
1390
1391 static void bnxt_ptp_get_current_time(void *arg)
1392 {
1393         struct bnxt *bp = arg;
1394         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1395         int rc;
1396
1397         rc = is_bnxt_in_error(bp);
1398         if (rc)
1399                 return;
1400
1401         if (!ptp)
1402                 return;
1403
1404         bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1405                                 &ptp->current_time);
1406
1407         rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1408         if (rc != 0) {
1409                 PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n");
1410                 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1411         }
1412 }
1413
1414 static int bnxt_schedule_ptp_alarm(struct bnxt *bp)
1415 {
1416         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1417         int rc;
1418
1419         if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED)
1420                 return 0;
1421
1422         bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1423                                 &ptp->current_time);
1424
1425         rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1426         return rc;
1427 }
1428
1429 static void bnxt_cancel_ptp_alarm(struct bnxt *bp)
1430 {
1431         if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) {
1432                 rte_eal_alarm_cancel(bnxt_ptp_get_current_time, (void *)bp);
1433                 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1434         }
1435 }
1436
1437 static void bnxt_ptp_stop(struct bnxt *bp)
1438 {
1439         bnxt_cancel_ptp_alarm(bp);
1440         bp->flags2 &= ~BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1441 }
1442
1443 static int bnxt_ptp_start(struct bnxt *bp)
1444 {
1445         int rc;
1446
1447         rc = bnxt_schedule_ptp_alarm(bp);
1448         if (rc != 0) {
1449                 PMD_DRV_LOG(ERR, "Failed to schedule PTP alarm\n");
1450         } else {
1451                 bp->flags2 |= BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1452                 bp->flags2 |= BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1453         }
1454
1455         return rc;
1456 }
1457
1458 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev)
1459 {
1460         struct bnxt *bp = eth_dev->data->dev_private;
1461         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1462         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1463         struct rte_eth_link link;
1464         int ret;
1465
1466         eth_dev->data->dev_started = 0;
1467         eth_dev->data->scattered_rx = 0;
1468
1469         /* Prevent crashes when queues are still in use */
1470         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1471         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1472
1473         bnxt_disable_int(bp);
1474
1475         /* disable uio/vfio intr/eventfd mapping */
1476         rte_intr_disable(intr_handle);
1477
1478         /* Stop the child representors for this device */
1479         ret = bnxt_rep_stop_all(bp);
1480         if (ret != 0)
1481                 return ret;
1482
1483         /* delete the bnxt ULP port details */
1484         bnxt_ulp_port_deinit(bp);
1485
1486         bnxt_cancel_fw_health_check(bp);
1487
1488         if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1489                 bnxt_cancel_ptp_alarm(bp);
1490
1491         /* Do not bring link down during reset recovery */
1492         if (!is_bnxt_in_error(bp)) {
1493                 bnxt_dev_set_link_down_op(eth_dev);
1494                 /* Wait for link to be reset */
1495                 if (BNXT_SINGLE_PF(bp))
1496                         rte_delay_ms(500);
1497                 /* clear the recorded link status */
1498                 memset(&link, 0, sizeof(link));
1499                 rte_eth_linkstatus_set(eth_dev, &link);
1500         }
1501
1502         /* Clean queue intr-vector mapping */
1503         rte_intr_efd_disable(intr_handle);
1504         if (intr_handle->intr_vec != NULL) {
1505                 rte_free(intr_handle->intr_vec);
1506                 intr_handle->intr_vec = NULL;
1507         }
1508
1509         bnxt_hwrm_port_clr_stats(bp);
1510         bnxt_free_tx_mbufs(bp);
1511         bnxt_free_rx_mbufs(bp);
1512         /* Process any remaining notifications in default completion queue */
1513         bnxt_int_handler(eth_dev);
1514         bnxt_shutdown_nic(bp);
1515         bnxt_hwrm_if_change(bp, false);
1516
1517         bnxt_free_prev_ring_stats(bp);
1518         rte_free(bp->mark_table);
1519         bp->mark_table = NULL;
1520
1521         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1522         bp->rx_cosq_cnt = 0;
1523         /* All filters are deleted on a port stop. */
1524         if (BNXT_FLOW_XSTATS_EN(bp))
1525                 bp->flow_stat->flow_count = 0;
1526
1527         return 0;
1528 }
1529
1530 /* Unload the driver, release resources */
1531 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1532 {
1533         struct bnxt *bp = eth_dev->data->dev_private;
1534
1535         pthread_mutex_lock(&bp->err_recovery_lock);
1536         if (bp->flags & BNXT_FLAG_FW_RESET) {
1537                 PMD_DRV_LOG(ERR,
1538                             "Adapter recovering from error..Please retry\n");
1539                 pthread_mutex_unlock(&bp->err_recovery_lock);
1540                 return -EAGAIN;
1541         }
1542         pthread_mutex_unlock(&bp->err_recovery_lock);
1543
1544         return bnxt_dev_stop(eth_dev);
1545 }
1546
1547 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1548 {
1549         struct bnxt *bp = eth_dev->data->dev_private;
1550         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1551         int vlan_mask = 0;
1552         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1553
1554         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1555                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1556                 return -EINVAL;
1557         }
1558
1559         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1560                 PMD_DRV_LOG(ERR,
1561                             "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1562                             bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1563
1564         do {
1565                 rc = bnxt_hwrm_if_change(bp, true);
1566                 if (rc == 0 || rc != -EAGAIN)
1567                         break;
1568
1569                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1570         } while (retry_cnt--);
1571
1572         if (rc)
1573                 return rc;
1574
1575         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1576                 rc = bnxt_handle_if_change_status(bp);
1577                 if (rc)
1578                         return rc;
1579         }
1580
1581         bnxt_enable_int(bp);
1582
1583         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1584
1585         rc = bnxt_start_nic(bp);
1586         if (rc)
1587                 goto error;
1588
1589         rc = bnxt_alloc_prev_ring_stats(bp);
1590         if (rc)
1591                 goto error;
1592
1593         eth_dev->data->dev_started = 1;
1594
1595         bnxt_link_update_op(eth_dev, 1);
1596
1597         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1598                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1599         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1600                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1601         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1602         if (rc)
1603                 goto error;
1604
1605         /* Initialize bnxt ULP port details */
1606         rc = bnxt_ulp_port_init(bp);
1607         if (rc)
1608                 goto error;
1609
1610         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1611         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1612
1613         bnxt_schedule_fw_health_check(bp);
1614
1615         if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1616                 bnxt_schedule_ptp_alarm(bp);
1617
1618         return 0;
1619
1620 error:
1621         bnxt_dev_stop(eth_dev);
1622         return rc;
1623 }
1624
1625 static void
1626 bnxt_uninit_locks(struct bnxt *bp)
1627 {
1628         pthread_mutex_destroy(&bp->flow_lock);
1629         pthread_mutex_destroy(&bp->def_cp_lock);
1630         pthread_mutex_destroy(&bp->health_check_lock);
1631         pthread_mutex_destroy(&bp->err_recovery_lock);
1632         if (bp->rep_info) {
1633                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
1634                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
1635         }
1636 }
1637
1638 static void bnxt_drv_uninit(struct bnxt *bp)
1639 {
1640         bnxt_free_leds_info(bp);
1641         bnxt_free_cos_queues(bp);
1642         bnxt_free_link_info(bp);
1643         bnxt_free_parent_info(bp);
1644         bnxt_uninit_locks(bp);
1645
1646         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1647         bp->tx_mem_zone = NULL;
1648         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1649         bp->rx_mem_zone = NULL;
1650
1651         bnxt_free_vf_info(bp);
1652         bnxt_free_pf_info(bp);
1653
1654         rte_free(bp->grp_info);
1655         bp->grp_info = NULL;
1656 }
1657
1658 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1659 {
1660         struct bnxt *bp = eth_dev->data->dev_private;
1661         int ret = 0;
1662
1663         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1664                 return 0;
1665
1666         pthread_mutex_lock(&bp->err_recovery_lock);
1667         if (bp->flags & BNXT_FLAG_FW_RESET) {
1668                 PMD_DRV_LOG(ERR,
1669                             "Adapter recovering from error...Please retry\n");
1670                 pthread_mutex_unlock(&bp->err_recovery_lock);
1671                 return -EAGAIN;
1672         }
1673         pthread_mutex_unlock(&bp->err_recovery_lock);
1674
1675         /* cancel the recovery handler before remove dev */
1676         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1677         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1678         bnxt_cancel_fc_thread(bp);
1679
1680         if (eth_dev->data->dev_started)
1681                 ret = bnxt_dev_stop(eth_dev);
1682
1683         bnxt_uninit_resources(bp, false);
1684
1685         bnxt_drv_uninit(bp);
1686
1687         return ret;
1688 }
1689
1690 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1691                                     uint32_t index)
1692 {
1693         struct bnxt *bp = eth_dev->data->dev_private;
1694         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1695         struct bnxt_vnic_info *vnic;
1696         struct bnxt_filter_info *filter, *temp_filter;
1697         uint32_t i;
1698
1699         if (is_bnxt_in_error(bp))
1700                 return;
1701
1702         /*
1703          * Loop through all VNICs from the specified filter flow pools to
1704          * remove the corresponding MAC addr filter
1705          */
1706         for (i = 0; i < bp->nr_vnics; i++) {
1707                 if (!(pool_mask & (1ULL << i)))
1708                         continue;
1709
1710                 vnic = &bp->vnic_info[i];
1711                 filter = STAILQ_FIRST(&vnic->filter);
1712                 while (filter) {
1713                         temp_filter = STAILQ_NEXT(filter, next);
1714                         if (filter->mac_index == index) {
1715                                 STAILQ_REMOVE(&vnic->filter, filter,
1716                                                 bnxt_filter_info, next);
1717                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1718                                 bnxt_free_filter(bp, filter);
1719                         }
1720                         filter = temp_filter;
1721                 }
1722         }
1723 }
1724
1725 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1726                                struct rte_ether_addr *mac_addr, uint32_t index,
1727                                uint32_t pool)
1728 {
1729         struct bnxt_filter_info *filter;
1730         int rc = 0;
1731
1732         /* Attach requested MAC address to the new l2_filter */
1733         STAILQ_FOREACH(filter, &vnic->filter, next) {
1734                 if (filter->mac_index == index) {
1735                         PMD_DRV_LOG(DEBUG,
1736                                     "MAC addr already existed for pool %d\n",
1737                                     pool);
1738                         return 0;
1739                 }
1740         }
1741
1742         filter = bnxt_alloc_filter(bp);
1743         if (!filter) {
1744                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1745                 return -ENODEV;
1746         }
1747
1748         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1749          * if the MAC that's been programmed now is a different one, then,
1750          * copy that addr to filter->l2_addr
1751          */
1752         if (mac_addr)
1753                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1754         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1755
1756         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1757         if (!rc) {
1758                 filter->mac_index = index;
1759                 if (filter->mac_index == 0)
1760                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1761                 else
1762                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1763         } else {
1764                 bnxt_free_filter(bp, filter);
1765         }
1766
1767         return rc;
1768 }
1769
1770 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1771                                 struct rte_ether_addr *mac_addr,
1772                                 uint32_t index, uint32_t pool)
1773 {
1774         struct bnxt *bp = eth_dev->data->dev_private;
1775         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1776         int rc = 0;
1777
1778         rc = is_bnxt_in_error(bp);
1779         if (rc)
1780                 return rc;
1781
1782         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1783                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1784                 return -ENOTSUP;
1785         }
1786
1787         if (!vnic) {
1788                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1789                 return -EINVAL;
1790         }
1791
1792         /* Filter settings will get applied when port is started */
1793         if (!eth_dev->data->dev_started)
1794                 return 0;
1795
1796         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1797
1798         return rc;
1799 }
1800
1801 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1802 {
1803         int rc = 0;
1804         struct bnxt *bp = eth_dev->data->dev_private;
1805         struct rte_eth_link new;
1806         int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1807                         BNXT_MIN_LINK_WAIT_CNT;
1808
1809         rc = is_bnxt_in_error(bp);
1810         if (rc)
1811                 return rc;
1812
1813         memset(&new, 0, sizeof(new));
1814
1815         if (bp->link_info == NULL)
1816                 goto out;
1817
1818         do {
1819                 /* Retrieve link info from hardware */
1820                 rc = bnxt_get_hwrm_link_config(bp, &new);
1821                 if (rc) {
1822                         new.link_speed = ETH_LINK_SPEED_100M;
1823                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1824                         PMD_DRV_LOG(ERR,
1825                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1826                         goto out;
1827                 }
1828
1829                 if (!wait_to_complete || new.link_status)
1830                         break;
1831
1832                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1833         } while (cnt--);
1834
1835         /* Only single function PF can bring phy down.
1836          * When port is stopped, report link down for VF/MH/NPAR functions.
1837          */
1838         if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1839                 memset(&new, 0, sizeof(new));
1840
1841 out:
1842         /* Timed out or success */
1843         if (new.link_status != eth_dev->data->dev_link.link_status ||
1844             new.link_speed != eth_dev->data->dev_link.link_speed) {
1845                 rte_eth_linkstatus_set(eth_dev, &new);
1846                 bnxt_print_link_info(eth_dev);
1847         }
1848
1849         return rc;
1850 }
1851
1852 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1853 {
1854         struct bnxt *bp = eth_dev->data->dev_private;
1855         struct bnxt_vnic_info *vnic;
1856         uint32_t old_flags;
1857         int rc;
1858
1859         rc = is_bnxt_in_error(bp);
1860         if (rc)
1861                 return rc;
1862
1863         /* Filter settings will get applied when port is started */
1864         if (!eth_dev->data->dev_started)
1865                 return 0;
1866
1867         if (bp->vnic_info == NULL)
1868                 return 0;
1869
1870         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1871
1872         old_flags = vnic->flags;
1873         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1874         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1875         if (rc != 0)
1876                 vnic->flags = old_flags;
1877
1878         return rc;
1879 }
1880
1881 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1882 {
1883         struct bnxt *bp = eth_dev->data->dev_private;
1884         struct bnxt_vnic_info *vnic;
1885         uint32_t old_flags;
1886         int rc;
1887
1888         rc = is_bnxt_in_error(bp);
1889         if (rc)
1890                 return rc;
1891
1892         /* Filter settings will get applied when port is started */
1893         if (!eth_dev->data->dev_started)
1894                 return 0;
1895
1896         if (bp->vnic_info == NULL)
1897                 return 0;
1898
1899         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1900
1901         old_flags = vnic->flags;
1902         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1903         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1904         if (rc != 0)
1905                 vnic->flags = old_flags;
1906
1907         return rc;
1908 }
1909
1910 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1911 {
1912         struct bnxt *bp = eth_dev->data->dev_private;
1913         struct bnxt_vnic_info *vnic;
1914         uint32_t old_flags;
1915         int rc;
1916
1917         rc = is_bnxt_in_error(bp);
1918         if (rc)
1919                 return rc;
1920
1921         /* Filter settings will get applied when port is started */
1922         if (!eth_dev->data->dev_started)
1923                 return 0;
1924
1925         if (bp->vnic_info == NULL)
1926                 return 0;
1927
1928         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1929
1930         old_flags = vnic->flags;
1931         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1932         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1933         if (rc != 0)
1934                 vnic->flags = old_flags;
1935
1936         return rc;
1937 }
1938
1939 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1940 {
1941         struct bnxt *bp = eth_dev->data->dev_private;
1942         struct bnxt_vnic_info *vnic;
1943         uint32_t old_flags;
1944         int rc;
1945
1946         rc = is_bnxt_in_error(bp);
1947         if (rc)
1948                 return rc;
1949
1950         /* Filter settings will get applied when port is started */
1951         if (!eth_dev->data->dev_started)
1952                 return 0;
1953
1954         if (bp->vnic_info == NULL)
1955                 return 0;
1956
1957         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1958
1959         old_flags = vnic->flags;
1960         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1961         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1962         if (rc != 0)
1963                 vnic->flags = old_flags;
1964
1965         return rc;
1966 }
1967
1968 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1969 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1970 {
1971         if (qid >= bp->rx_nr_rings)
1972                 return NULL;
1973
1974         return bp->eth_dev->data->rx_queues[qid];
1975 }
1976
1977 /* Return rxq corresponding to a given rss table ring/group ID. */
1978 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1979 {
1980         struct bnxt_rx_queue *rxq;
1981         unsigned int i;
1982
1983         if (!BNXT_HAS_RING_GRPS(bp)) {
1984                 for (i = 0; i < bp->rx_nr_rings; i++) {
1985                         rxq = bp->eth_dev->data->rx_queues[i];
1986                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1987                                 return rxq->index;
1988                 }
1989         } else {
1990                 for (i = 0; i < bp->rx_nr_rings; i++) {
1991                         if (bp->grp_info[i].fw_grp_id == fwr)
1992                                 return i;
1993                 }
1994         }
1995
1996         return INVALID_HW_RING_ID;
1997 }
1998
1999 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
2000                             struct rte_eth_rss_reta_entry64 *reta_conf,
2001                             uint16_t reta_size)
2002 {
2003         struct bnxt *bp = eth_dev->data->dev_private;
2004         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2005         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2006         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
2007         uint16_t idx, sft;
2008         int i, rc;
2009
2010         rc = is_bnxt_in_error(bp);
2011         if (rc)
2012                 return rc;
2013
2014         if (!vnic->rss_table)
2015                 return -EINVAL;
2016
2017         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
2018                 return -EINVAL;
2019
2020         if (reta_size != tbl_size) {
2021                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2022                         "(%d) must equal the size supported by the hardware "
2023                         "(%d)\n", reta_size, tbl_size);
2024                 return -EINVAL;
2025         }
2026
2027         for (i = 0; i < reta_size; i++) {
2028                 struct bnxt_rx_queue *rxq;
2029
2030                 idx = i / RTE_RETA_GROUP_SIZE;
2031                 sft = i % RTE_RETA_GROUP_SIZE;
2032
2033                 if (!(reta_conf[idx].mask & (1ULL << sft)))
2034                         continue;
2035
2036                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
2037                 if (!rxq) {
2038                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
2039                         return -EINVAL;
2040                 }
2041
2042                 if (BNXT_CHIP_P5(bp)) {
2043                         vnic->rss_table[i * 2] =
2044                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
2045                         vnic->rss_table[i * 2 + 1] =
2046                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
2047                 } else {
2048                         vnic->rss_table[i] =
2049                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
2050                 }
2051         }
2052
2053         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2054         return rc;
2055 }
2056
2057 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
2058                               struct rte_eth_rss_reta_entry64 *reta_conf,
2059                               uint16_t reta_size)
2060 {
2061         struct bnxt *bp = eth_dev->data->dev_private;
2062         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2063         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
2064         uint16_t idx, sft, i;
2065         int rc;
2066
2067         rc = is_bnxt_in_error(bp);
2068         if (rc)
2069                 return rc;
2070
2071         if (!vnic)
2072                 return -EINVAL;
2073         if (!vnic->rss_table)
2074                 return -EINVAL;
2075
2076         if (reta_size != tbl_size) {
2077                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2078                         "(%d) must equal the size supported by the hardware "
2079                         "(%d)\n", reta_size, tbl_size);
2080                 return -EINVAL;
2081         }
2082
2083         for (idx = 0, i = 0; i < reta_size; i++) {
2084                 idx = i / RTE_RETA_GROUP_SIZE;
2085                 sft = i % RTE_RETA_GROUP_SIZE;
2086
2087                 if (reta_conf[idx].mask & (1ULL << sft)) {
2088                         uint16_t qid;
2089
2090                         if (BNXT_CHIP_P5(bp))
2091                                 qid = bnxt_rss_to_qid(bp,
2092                                                       vnic->rss_table[i * 2]);
2093                         else
2094                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
2095
2096                         if (qid == INVALID_HW_RING_ID) {
2097                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
2098                                 return -EINVAL;
2099                         }
2100                         reta_conf[idx].reta[sft] = qid;
2101                 }
2102         }
2103
2104         return 0;
2105 }
2106
2107 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
2108                                    struct rte_eth_rss_conf *rss_conf)
2109 {
2110         struct bnxt *bp = eth_dev->data->dev_private;
2111         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2112         struct bnxt_vnic_info *vnic;
2113         int rc;
2114
2115         rc = is_bnxt_in_error(bp);
2116         if (rc)
2117                 return rc;
2118
2119         /*
2120          * If RSS enablement were different than dev_configure,
2121          * then return -EINVAL
2122          */
2123         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
2124                 if (!rss_conf->rss_hf)
2125                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
2126         } else {
2127                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
2128                         return -EINVAL;
2129         }
2130
2131         bp->flags |= BNXT_FLAG_UPDATE_HASH;
2132         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
2133                rss_conf,
2134                sizeof(*rss_conf));
2135
2136         /* Update the default RSS VNIC(s) */
2137         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2138         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
2139         vnic->hash_mode =
2140                 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
2141                                             ETH_RSS_LEVEL(rss_conf->rss_hf));
2142
2143         /*
2144          * If hashkey is not specified, use the previously configured
2145          * hashkey
2146          */
2147         if (!rss_conf->rss_key)
2148                 goto rss_config;
2149
2150         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
2151                 PMD_DRV_LOG(ERR,
2152                             "Invalid hashkey length, should be %d bytes\n",
2153                             HW_HASH_KEY_SIZE);
2154                 return -EINVAL;
2155         }
2156         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
2157
2158 rss_config:
2159         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2160         return rc;
2161 }
2162
2163 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
2164                                      struct rte_eth_rss_conf *rss_conf)
2165 {
2166         struct bnxt *bp = eth_dev->data->dev_private;
2167         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2168         int len, rc;
2169         uint32_t hash_types;
2170
2171         rc = is_bnxt_in_error(bp);
2172         if (rc)
2173                 return rc;
2174
2175         /* RSS configuration is the same for all VNICs */
2176         if (vnic && vnic->rss_hash_key) {
2177                 if (rss_conf->rss_key) {
2178                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
2179                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
2180                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
2181                 }
2182
2183                 hash_types = vnic->hash_type;
2184                 rss_conf->rss_hf = 0;
2185                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
2186                         rss_conf->rss_hf |= ETH_RSS_IPV4;
2187                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
2188                 }
2189                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
2190                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2191                         hash_types &=
2192                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
2193                 }
2194                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
2195                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2196                         hash_types &=
2197                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
2198                 }
2199                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
2200                         rss_conf->rss_hf |= ETH_RSS_IPV6;
2201                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
2202                 }
2203                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
2204                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2205                         hash_types &=
2206                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
2207                 }
2208                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
2209                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2210                         hash_types &=
2211                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2212                 }
2213
2214                 rss_conf->rss_hf |=
2215                         bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2216
2217                 if (hash_types) {
2218                         PMD_DRV_LOG(ERR,
2219                                 "Unknown RSS config from firmware (%08x), RSS disabled",
2220                                 vnic->hash_type);
2221                         return -ENOTSUP;
2222                 }
2223         } else {
2224                 rss_conf->rss_hf = 0;
2225         }
2226         return 0;
2227 }
2228
2229 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2230                                struct rte_eth_fc_conf *fc_conf)
2231 {
2232         struct bnxt *bp = dev->data->dev_private;
2233         struct rte_eth_link link_info;
2234         int rc;
2235
2236         rc = is_bnxt_in_error(bp);
2237         if (rc)
2238                 return rc;
2239
2240         rc = bnxt_get_hwrm_link_config(bp, &link_info);
2241         if (rc)
2242                 return rc;
2243
2244         memset(fc_conf, 0, sizeof(*fc_conf));
2245         if (bp->link_info->auto_pause)
2246                 fc_conf->autoneg = 1;
2247         switch (bp->link_info->pause) {
2248         case 0:
2249                 fc_conf->mode = RTE_FC_NONE;
2250                 break;
2251         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2252                 fc_conf->mode = RTE_FC_TX_PAUSE;
2253                 break;
2254         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2255                 fc_conf->mode = RTE_FC_RX_PAUSE;
2256                 break;
2257         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2258                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2259                 fc_conf->mode = RTE_FC_FULL;
2260                 break;
2261         }
2262         return 0;
2263 }
2264
2265 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2266                                struct rte_eth_fc_conf *fc_conf)
2267 {
2268         struct bnxt *bp = dev->data->dev_private;
2269         int rc;
2270
2271         rc = is_bnxt_in_error(bp);
2272         if (rc)
2273                 return rc;
2274
2275         if (!BNXT_SINGLE_PF(bp)) {
2276                 PMD_DRV_LOG(ERR,
2277                             "Flow Control Settings cannot be modified on VF or on shared PF\n");
2278                 return -ENOTSUP;
2279         }
2280
2281         switch (fc_conf->mode) {
2282         case RTE_FC_NONE:
2283                 bp->link_info->auto_pause = 0;
2284                 bp->link_info->force_pause = 0;
2285                 break;
2286         case RTE_FC_RX_PAUSE:
2287                 if (fc_conf->autoneg) {
2288                         bp->link_info->auto_pause =
2289                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2290                         bp->link_info->force_pause = 0;
2291                 } else {
2292                         bp->link_info->auto_pause = 0;
2293                         bp->link_info->force_pause =
2294                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2295                 }
2296                 break;
2297         case RTE_FC_TX_PAUSE:
2298                 if (fc_conf->autoneg) {
2299                         bp->link_info->auto_pause =
2300                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2301                         bp->link_info->force_pause = 0;
2302                 } else {
2303                         bp->link_info->auto_pause = 0;
2304                         bp->link_info->force_pause =
2305                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2306                 }
2307                 break;
2308         case RTE_FC_FULL:
2309                 if (fc_conf->autoneg) {
2310                         bp->link_info->auto_pause =
2311                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2312                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2313                         bp->link_info->force_pause = 0;
2314                 } else {
2315                         bp->link_info->auto_pause = 0;
2316                         bp->link_info->force_pause =
2317                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2318                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2319                 }
2320                 break;
2321         }
2322         return bnxt_set_hwrm_link_config(bp, true);
2323 }
2324
2325 /* Add UDP tunneling port */
2326 static int
2327 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2328                          struct rte_eth_udp_tunnel *udp_tunnel)
2329 {
2330         struct bnxt *bp = eth_dev->data->dev_private;
2331         uint16_t tunnel_type = 0;
2332         int rc = 0;
2333
2334         rc = is_bnxt_in_error(bp);
2335         if (rc)
2336                 return rc;
2337
2338         switch (udp_tunnel->prot_type) {
2339         case RTE_TUNNEL_TYPE_VXLAN:
2340                 if (bp->vxlan_port_cnt) {
2341                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2342                                 udp_tunnel->udp_port);
2343                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2344                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2345                                 return -ENOSPC;
2346                         }
2347                         bp->vxlan_port_cnt++;
2348                         return 0;
2349                 }
2350                 tunnel_type =
2351                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2352                 bp->vxlan_port_cnt++;
2353                 break;
2354         case RTE_TUNNEL_TYPE_GENEVE:
2355                 if (bp->geneve_port_cnt) {
2356                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2357                                 udp_tunnel->udp_port);
2358                         if (bp->geneve_port != udp_tunnel->udp_port) {
2359                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2360                                 return -ENOSPC;
2361                         }
2362                         bp->geneve_port_cnt++;
2363                         return 0;
2364                 }
2365                 tunnel_type =
2366                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2367                 bp->geneve_port_cnt++;
2368                 break;
2369         default:
2370                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2371                 return -ENOTSUP;
2372         }
2373         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2374                                              tunnel_type);
2375         return rc;
2376 }
2377
2378 static int
2379 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2380                          struct rte_eth_udp_tunnel *udp_tunnel)
2381 {
2382         struct bnxt *bp = eth_dev->data->dev_private;
2383         uint16_t tunnel_type = 0;
2384         uint16_t port = 0;
2385         int rc = 0;
2386
2387         rc = is_bnxt_in_error(bp);
2388         if (rc)
2389                 return rc;
2390
2391         switch (udp_tunnel->prot_type) {
2392         case RTE_TUNNEL_TYPE_VXLAN:
2393                 if (!bp->vxlan_port_cnt) {
2394                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2395                         return -EINVAL;
2396                 }
2397                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2398                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2399                                 udp_tunnel->udp_port, bp->vxlan_port);
2400                         return -EINVAL;
2401                 }
2402                 if (--bp->vxlan_port_cnt)
2403                         return 0;
2404
2405                 tunnel_type =
2406                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2407                 port = bp->vxlan_fw_dst_port_id;
2408                 break;
2409         case RTE_TUNNEL_TYPE_GENEVE:
2410                 if (!bp->geneve_port_cnt) {
2411                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2412                         return -EINVAL;
2413                 }
2414                 if (bp->geneve_port != udp_tunnel->udp_port) {
2415                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2416                                 udp_tunnel->udp_port, bp->geneve_port);
2417                         return -EINVAL;
2418                 }
2419                 if (--bp->geneve_port_cnt)
2420                         return 0;
2421
2422                 tunnel_type =
2423                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2424                 port = bp->geneve_fw_dst_port_id;
2425                 break;
2426         default:
2427                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2428                 return -ENOTSUP;
2429         }
2430
2431         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2432         return rc;
2433 }
2434
2435 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2436 {
2437         struct bnxt_filter_info *filter;
2438         struct bnxt_vnic_info *vnic;
2439         int rc = 0;
2440         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2441
2442         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2443         filter = STAILQ_FIRST(&vnic->filter);
2444         while (filter) {
2445                 /* Search for this matching MAC+VLAN filter */
2446                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2447                         /* Delete the filter */
2448                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2449                         if (rc)
2450                                 return rc;
2451                         STAILQ_REMOVE(&vnic->filter, filter,
2452                                       bnxt_filter_info, next);
2453                         bnxt_free_filter(bp, filter);
2454                         PMD_DRV_LOG(INFO,
2455                                     "Deleted vlan filter for %d\n",
2456                                     vlan_id);
2457                         return 0;
2458                 }
2459                 filter = STAILQ_NEXT(filter, next);
2460         }
2461         return -ENOENT;
2462 }
2463
2464 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2465 {
2466         struct bnxt_filter_info *filter;
2467         struct bnxt_vnic_info *vnic;
2468         int rc = 0;
2469         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2470                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2471         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2472
2473         /* Implementation notes on the use of VNIC in this command:
2474          *
2475          * By default, these filters belong to default vnic for the function.
2476          * Once these filters are set up, only destination VNIC can be modified.
2477          * If the destination VNIC is not specified in this command,
2478          * then the HWRM shall only create an l2 context id.
2479          */
2480
2481         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2482         filter = STAILQ_FIRST(&vnic->filter);
2483         /* Check if the VLAN has already been added */
2484         while (filter) {
2485                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2486                         return -EEXIST;
2487
2488                 filter = STAILQ_NEXT(filter, next);
2489         }
2490
2491         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2492          * command to create MAC+VLAN filter with the right flags, enables set.
2493          */
2494         filter = bnxt_alloc_filter(bp);
2495         if (!filter) {
2496                 PMD_DRV_LOG(ERR,
2497                             "MAC/VLAN filter alloc failed\n");
2498                 return -ENOMEM;
2499         }
2500         /* MAC + VLAN ID filter */
2501         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2502          * untagged packets are received
2503          *
2504          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2505          * packets and only the programmed vlan's packets are received
2506          */
2507         filter->l2_ivlan = vlan_id;
2508         filter->l2_ivlan_mask = 0x0FFF;
2509         filter->enables |= en;
2510         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2511
2512         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2513         if (rc) {
2514                 /* Free the newly allocated filter as we were
2515                  * not able to create the filter in hardware.
2516                  */
2517                 bnxt_free_filter(bp, filter);
2518                 return rc;
2519         }
2520
2521         filter->mac_index = 0;
2522         /* Add this new filter to the list */
2523         if (vlan_id == 0)
2524                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2525         else
2526                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2527
2528         PMD_DRV_LOG(INFO,
2529                     "Added Vlan filter for %d\n", vlan_id);
2530         return rc;
2531 }
2532
2533 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2534                 uint16_t vlan_id, int on)
2535 {
2536         struct bnxt *bp = eth_dev->data->dev_private;
2537         int rc;
2538
2539         rc = is_bnxt_in_error(bp);
2540         if (rc)
2541                 return rc;
2542
2543         if (!eth_dev->data->dev_started) {
2544                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2545                 return -EINVAL;
2546         }
2547
2548         /* These operations apply to ALL existing MAC/VLAN filters */
2549         if (on)
2550                 return bnxt_add_vlan_filter(bp, vlan_id);
2551         else
2552                 return bnxt_del_vlan_filter(bp, vlan_id);
2553 }
2554
2555 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2556                                     struct bnxt_vnic_info *vnic)
2557 {
2558         struct bnxt_filter_info *filter;
2559         int rc;
2560
2561         filter = STAILQ_FIRST(&vnic->filter);
2562         while (filter) {
2563                 if (filter->mac_index == 0 &&
2564                     !memcmp(filter->l2_addr, bp->mac_addr,
2565                             RTE_ETHER_ADDR_LEN)) {
2566                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2567                         if (!rc) {
2568                                 STAILQ_REMOVE(&vnic->filter, filter,
2569                                               bnxt_filter_info, next);
2570                                 bnxt_free_filter(bp, filter);
2571                         }
2572                         return rc;
2573                 }
2574                 filter = STAILQ_NEXT(filter, next);
2575         }
2576         return 0;
2577 }
2578
2579 static int
2580 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2581 {
2582         struct bnxt_vnic_info *vnic;
2583         unsigned int i;
2584         int rc;
2585
2586         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2587         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2588                 /* Remove any VLAN filters programmed */
2589                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2590                         bnxt_del_vlan_filter(bp, i);
2591
2592                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2593                 if (rc)
2594                         return rc;
2595         } else {
2596                 /* Default filter will allow packets that match the
2597                  * dest mac. So, it has to be deleted, otherwise, we
2598                  * will endup receiving vlan packets for which the
2599                  * filter is not programmed, when hw-vlan-filter
2600                  * configuration is ON
2601                  */
2602                 bnxt_del_dflt_mac_filter(bp, vnic);
2603                 /* This filter will allow only untagged packets */
2604                 bnxt_add_vlan_filter(bp, 0);
2605         }
2606         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2607                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2608
2609         return 0;
2610 }
2611
2612 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2613 {
2614         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2615         unsigned int i;
2616         int rc;
2617
2618         /* Destroy vnic filters and vnic */
2619         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2620             DEV_RX_OFFLOAD_VLAN_FILTER) {
2621                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2622                         bnxt_del_vlan_filter(bp, i);
2623         }
2624         bnxt_del_dflt_mac_filter(bp, vnic);
2625
2626         rc = bnxt_hwrm_vnic_ctx_free(bp, vnic);
2627         if (rc)
2628                 return rc;
2629
2630         rc = bnxt_hwrm_vnic_free(bp, vnic);
2631         if (rc)
2632                 return rc;
2633
2634         rte_free(vnic->fw_grp_ids);
2635         vnic->fw_grp_ids = NULL;
2636
2637         vnic->rx_queue_cnt = 0;
2638
2639         return 0;
2640 }
2641
2642 static int
2643 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2644 {
2645         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2646         int rc;
2647
2648         /* Destroy, recreate and reconfigure the default vnic */
2649         rc = bnxt_free_one_vnic(bp, 0);
2650         if (rc)
2651                 return rc;
2652
2653         /* default vnic 0 */
2654         rc = bnxt_setup_one_vnic(bp, 0);
2655         if (rc)
2656                 return rc;
2657
2658         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2659             DEV_RX_OFFLOAD_VLAN_FILTER) {
2660                 rc = bnxt_add_vlan_filter(bp, 0);
2661                 if (rc)
2662                         return rc;
2663                 rc = bnxt_restore_vlan_filters(bp);
2664                 if (rc)
2665                         return rc;
2666         } else {
2667                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2668                 if (rc)
2669                         return rc;
2670         }
2671
2672         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2673         if (rc)
2674                 return rc;
2675
2676         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2677                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2678
2679         return rc;
2680 }
2681
2682 static int
2683 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2684 {
2685         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2686         struct bnxt *bp = dev->data->dev_private;
2687         int rc;
2688
2689         rc = is_bnxt_in_error(bp);
2690         if (rc)
2691                 return rc;
2692
2693         /* Filter settings will get applied when port is started */
2694         if (!dev->data->dev_started)
2695                 return 0;
2696
2697         if (mask & ETH_VLAN_FILTER_MASK) {
2698                 /* Enable or disable VLAN filtering */
2699                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2700                 if (rc)
2701                         return rc;
2702         }
2703
2704         if (mask & ETH_VLAN_STRIP_MASK) {
2705                 /* Enable or disable VLAN stripping */
2706                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2707                 if (rc)
2708                         return rc;
2709         }
2710
2711         if (mask & ETH_VLAN_EXTEND_MASK) {
2712                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2713                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2714                 else
2715                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2716         }
2717
2718         return 0;
2719 }
2720
2721 static int
2722 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2723                       uint16_t tpid)
2724 {
2725         struct bnxt *bp = dev->data->dev_private;
2726         int qinq = dev->data->dev_conf.rxmode.offloads &
2727                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2728
2729         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2730             vlan_type != ETH_VLAN_TYPE_OUTER) {
2731                 PMD_DRV_LOG(ERR,
2732                             "Unsupported vlan type.");
2733                 return -EINVAL;
2734         }
2735         if (!qinq) {
2736                 PMD_DRV_LOG(ERR,
2737                             "QinQ not enabled. Needs to be ON as we can "
2738                             "accelerate only outer vlan\n");
2739                 return -EINVAL;
2740         }
2741
2742         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2743                 switch (tpid) {
2744                 case RTE_ETHER_TYPE_QINQ:
2745                         bp->outer_tpid_bd =
2746                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2747                                 break;
2748                 case RTE_ETHER_TYPE_VLAN:
2749                         bp->outer_tpid_bd =
2750                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2751                                 break;
2752                 case RTE_ETHER_TYPE_QINQ1:
2753                         bp->outer_tpid_bd =
2754                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2755                                 break;
2756                 case RTE_ETHER_TYPE_QINQ2:
2757                         bp->outer_tpid_bd =
2758                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2759                                 break;
2760                 case RTE_ETHER_TYPE_QINQ3:
2761                         bp->outer_tpid_bd =
2762                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2763                                 break;
2764                 default:
2765                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2766                         return -EINVAL;
2767                 }
2768                 bp->outer_tpid_bd |= tpid;
2769                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2770         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2771                 PMD_DRV_LOG(ERR,
2772                             "Can accelerate only outer vlan in QinQ\n");
2773                 return -EINVAL;
2774         }
2775
2776         return 0;
2777 }
2778
2779 static int
2780 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2781                              struct rte_ether_addr *addr)
2782 {
2783         struct bnxt *bp = dev->data->dev_private;
2784         /* Default Filter is tied to VNIC 0 */
2785         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2786         int rc;
2787
2788         rc = is_bnxt_in_error(bp);
2789         if (rc)
2790                 return rc;
2791
2792         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2793                 return -EPERM;
2794
2795         if (rte_is_zero_ether_addr(addr))
2796                 return -EINVAL;
2797
2798         /* Filter settings will get applied when port is started */
2799         if (!dev->data->dev_started)
2800                 return 0;
2801
2802         /* Check if the requested MAC is already added */
2803         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2804                 return 0;
2805
2806         /* Destroy filter and re-create it */
2807         bnxt_del_dflt_mac_filter(bp, vnic);
2808
2809         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2810         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2811                 /* This filter will allow only untagged packets */
2812                 rc = bnxt_add_vlan_filter(bp, 0);
2813         } else {
2814                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2815         }
2816
2817         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2818         return rc;
2819 }
2820
2821 static int
2822 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2823                           struct rte_ether_addr *mc_addr_set,
2824                           uint32_t nb_mc_addr)
2825 {
2826         struct bnxt *bp = eth_dev->data->dev_private;
2827         char *mc_addr_list = (char *)mc_addr_set;
2828         struct bnxt_vnic_info *vnic;
2829         uint32_t off = 0, i = 0;
2830         int rc;
2831
2832         rc = is_bnxt_in_error(bp);
2833         if (rc)
2834                 return rc;
2835
2836         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2837
2838         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2839                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2840                 goto allmulti;
2841         }
2842
2843         /* TODO Check for Duplicate mcast addresses */
2844         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2845         for (i = 0; i < nb_mc_addr; i++) {
2846                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2847                         RTE_ETHER_ADDR_LEN);
2848                 off += RTE_ETHER_ADDR_LEN;
2849         }
2850
2851         vnic->mc_addr_cnt = i;
2852         if (vnic->mc_addr_cnt)
2853                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2854         else
2855                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2856
2857 allmulti:
2858         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2859 }
2860
2861 static int
2862 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2863 {
2864         struct bnxt *bp = dev->data->dev_private;
2865         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2866         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2867         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2868         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2869         int ret;
2870
2871         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2872                         fw_major, fw_minor, fw_updt, fw_rsvd);
2873         if (ret < 0)
2874                 return -EINVAL;
2875
2876         ret += 1; /* add the size of '\0' */
2877         if (fw_size < (size_t)ret)
2878                 return ret;
2879         else
2880                 return 0;
2881 }
2882
2883 static void
2884 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2885         struct rte_eth_rxq_info *qinfo)
2886 {
2887         struct bnxt *bp = dev->data->dev_private;
2888         struct bnxt_rx_queue *rxq;
2889
2890         if (is_bnxt_in_error(bp))
2891                 return;
2892
2893         rxq = dev->data->rx_queues[queue_id];
2894
2895         qinfo->mp = rxq->mb_pool;
2896         qinfo->scattered_rx = dev->data->scattered_rx;
2897         qinfo->nb_desc = rxq->nb_rx_desc;
2898
2899         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2900         qinfo->conf.rx_drop_en = rxq->drop_en;
2901         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2902         qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2903 }
2904
2905 static void
2906 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2907         struct rte_eth_txq_info *qinfo)
2908 {
2909         struct bnxt *bp = dev->data->dev_private;
2910         struct bnxt_tx_queue *txq;
2911
2912         if (is_bnxt_in_error(bp))
2913                 return;
2914
2915         txq = dev->data->tx_queues[queue_id];
2916
2917         qinfo->nb_desc = txq->nb_tx_desc;
2918
2919         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2920         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2921         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2922
2923         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2924         qinfo->conf.tx_rs_thresh = 0;
2925         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2926         qinfo->conf.offloads = txq->offloads;
2927 }
2928
2929 static const struct {
2930         eth_rx_burst_t pkt_burst;
2931         const char *info;
2932 } bnxt_rx_burst_info[] = {
2933         {bnxt_recv_pkts,                "Scalar"},
2934 #if defined(RTE_ARCH_X86)
2935         {bnxt_recv_pkts_vec,            "Vector SSE"},
2936 #endif
2937 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2938         {bnxt_recv_pkts_vec_avx2,       "Vector AVX2"},
2939 #endif
2940 #if defined(RTE_ARCH_ARM64)
2941         {bnxt_recv_pkts_vec,            "Vector Neon"},
2942 #endif
2943 };
2944
2945 static int
2946 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2947                        struct rte_eth_burst_mode *mode)
2948 {
2949         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2950         size_t i;
2951
2952         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2953                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2954                         snprintf(mode->info, sizeof(mode->info), "%s",
2955                                  bnxt_rx_burst_info[i].info);
2956                         return 0;
2957                 }
2958         }
2959
2960         return -EINVAL;
2961 }
2962
2963 static const struct {
2964         eth_tx_burst_t pkt_burst;
2965         const char *info;
2966 } bnxt_tx_burst_info[] = {
2967         {bnxt_xmit_pkts,                "Scalar"},
2968 #if defined(RTE_ARCH_X86)
2969         {bnxt_xmit_pkts_vec,            "Vector SSE"},
2970 #endif
2971 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2972         {bnxt_xmit_pkts_vec_avx2,       "Vector AVX2"},
2973 #endif
2974 #if defined(RTE_ARCH_ARM64)
2975         {bnxt_xmit_pkts_vec,            "Vector Neon"},
2976 #endif
2977 };
2978
2979 static int
2980 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2981                        struct rte_eth_burst_mode *mode)
2982 {
2983         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2984         size_t i;
2985
2986         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2987                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2988                         snprintf(mode->info, sizeof(mode->info), "%s",
2989                                  bnxt_tx_burst_info[i].info);
2990                         return 0;
2991                 }
2992         }
2993
2994         return -EINVAL;
2995 }
2996
2997 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2998 {
2999         struct bnxt *bp = eth_dev->data->dev_private;
3000         uint32_t new_pkt_size;
3001         uint32_t rc = 0;
3002         uint32_t i;
3003
3004         rc = is_bnxt_in_error(bp);
3005         if (rc)
3006                 return rc;
3007
3008         /* Exit if receive queues are not configured yet */
3009         if (!eth_dev->data->nb_rx_queues)
3010                 return rc;
3011
3012         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
3013                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
3014
3015         /*
3016          * Disallow any MTU change that would require scattered receive support
3017          * if it is not already enabled.
3018          */
3019         if (eth_dev->data->dev_started &&
3020             !eth_dev->data->scattered_rx &&
3021             (new_pkt_size >
3022              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
3023                 PMD_DRV_LOG(ERR,
3024                             "MTU change would require scattered rx support. ");
3025                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
3026                 return -EINVAL;
3027         }
3028
3029         if (new_mtu > RTE_ETHER_MTU) {
3030                 bp->flags |= BNXT_FLAG_JUMBO;
3031                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
3032                         DEV_RX_OFFLOAD_JUMBO_FRAME;
3033         } else {
3034                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
3035                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3036                 bp->flags &= ~BNXT_FLAG_JUMBO;
3037         }
3038
3039         /* Is there a change in mtu setting? */
3040         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
3041                 return rc;
3042
3043         for (i = 0; i < bp->nr_vnics; i++) {
3044                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3045                 uint16_t size = 0;
3046
3047                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
3048                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
3049                 if (rc)
3050                         break;
3051
3052                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
3053                 size -= RTE_PKTMBUF_HEADROOM;
3054
3055                 if (size < new_mtu) {
3056                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
3057                         if (rc)
3058                                 return rc;
3059                 }
3060         }
3061
3062         if (!rc)
3063                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
3064
3065         if (bnxt_hwrm_config_host_mtu(bp))
3066                 PMD_DRV_LOG(WARNING, "Failed to configure host MTU\n");
3067
3068         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
3069
3070         return rc;
3071 }
3072
3073 static int
3074 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
3075 {
3076         struct bnxt *bp = dev->data->dev_private;
3077         uint16_t vlan = bp->vlan;
3078         int rc;
3079
3080         rc = is_bnxt_in_error(bp);
3081         if (rc)
3082                 return rc;
3083
3084         if (!BNXT_SINGLE_PF(bp)) {
3085                 PMD_DRV_LOG(ERR, "PVID cannot be modified on VF or on shared PF\n");
3086                 return -ENOTSUP;
3087         }
3088         bp->vlan = on ? pvid : 0;
3089
3090         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
3091         if (rc)
3092                 bp->vlan = vlan;
3093         return rc;
3094 }
3095
3096 static int
3097 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
3098 {
3099         struct bnxt *bp = dev->data->dev_private;
3100         int rc;
3101
3102         rc = is_bnxt_in_error(bp);
3103         if (rc)
3104                 return rc;
3105
3106         return bnxt_hwrm_port_led_cfg(bp, true);
3107 }
3108
3109 static int
3110 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
3111 {
3112         struct bnxt *bp = dev->data->dev_private;
3113         int rc;
3114
3115         rc = is_bnxt_in_error(bp);
3116         if (rc)
3117                 return rc;
3118
3119         return bnxt_hwrm_port_led_cfg(bp, false);
3120 }
3121
3122 static uint32_t
3123 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3124 {
3125         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
3126         struct bnxt_cp_ring_info *cpr;
3127         uint32_t desc = 0, raw_cons, cp_ring_size;
3128         struct bnxt_rx_queue *rxq;
3129         struct rx_pkt_cmpl *rxcmp;
3130         int rc;
3131
3132         rc = is_bnxt_in_error(bp);
3133         if (rc)
3134                 return rc;
3135
3136         rxq = dev->data->rx_queues[rx_queue_id];
3137         cpr = rxq->cp_ring;
3138         raw_cons = cpr->cp_raw_cons;
3139         cp_ring_size = cpr->cp_ring_struct->ring_size;
3140
3141         while (1) {
3142                 uint32_t agg_cnt, cons, cmpl_type;
3143
3144                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3145                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3146
3147                 if (!bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size))
3148                         break;
3149
3150                 cmpl_type = CMP_TYPE(rxcmp);
3151
3152                 switch (cmpl_type) {
3153                 case CMPL_BASE_TYPE_RX_L2:
3154                 case CMPL_BASE_TYPE_RX_L2_V2:
3155                         agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3156                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3157                         desc++;
3158                         break;
3159
3160                 case CMPL_BASE_TYPE_RX_TPA_END:
3161                         if (BNXT_CHIP_P5(rxq->bp)) {
3162                                 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3163
3164                                 p5_tpa_end = (void *)rxcmp;
3165                                 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3166                         } else {
3167                                 struct rx_tpa_end_cmpl *tpa_end;
3168
3169                                 tpa_end = (void *)rxcmp;
3170                                 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3171                         }
3172
3173                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3174                         desc++;
3175                         break;
3176
3177                 default:
3178                         raw_cons += CMP_LEN(cmpl_type);
3179                 }
3180         }
3181
3182         return desc;
3183 }
3184
3185 static int
3186 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
3187 {
3188         struct bnxt_rx_queue *rxq = rx_queue;
3189         struct bnxt_cp_ring_info *cpr;
3190         struct bnxt_rx_ring_info *rxr;
3191         uint32_t desc, raw_cons, cp_ring_size;
3192         struct bnxt *bp = rxq->bp;
3193         struct rx_pkt_cmpl *rxcmp;
3194         int rc;
3195
3196         rc = is_bnxt_in_error(bp);
3197         if (rc)
3198                 return rc;
3199
3200         if (offset >= rxq->nb_rx_desc)
3201                 return -EINVAL;
3202
3203         rxr = rxq->rx_ring;
3204         cpr = rxq->cp_ring;
3205         cp_ring_size = cpr->cp_ring_struct->ring_size;
3206
3207         /*
3208          * For the vector receive case, the completion at the requested
3209          * offset can be indexed directly.
3210          */
3211 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
3212         if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) {
3213                 struct rx_pkt_cmpl *rxcmp;
3214                 uint32_t cons;
3215
3216                 /* Check status of completion descriptor. */
3217                 raw_cons = cpr->cp_raw_cons +
3218                            offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2);
3219                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3220                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3221
3222                 if (bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size))
3223                         return RTE_ETH_RX_DESC_DONE;
3224
3225                 /* Check whether rx desc has an mbuf attached. */
3226                 cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2);
3227                 if (cons >= rxq->rxrearm_start &&
3228                     cons < rxq->rxrearm_start + rxq->rxrearm_nb) {
3229                         return RTE_ETH_RX_DESC_UNAVAIL;
3230                 }
3231
3232                 return RTE_ETH_RX_DESC_AVAIL;
3233         }
3234 #endif
3235
3236         /*
3237          * For the non-vector receive case, scan the completion ring to
3238          * locate the completion descriptor for the requested offset.
3239          */
3240         raw_cons = cpr->cp_raw_cons;
3241         desc = 0;
3242         while (1) {
3243                 uint32_t agg_cnt, cons, cmpl_type;
3244
3245                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3246                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3247
3248                 if (!bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size))
3249                         break;
3250
3251                 cmpl_type = CMP_TYPE(rxcmp);
3252
3253                 switch (cmpl_type) {
3254                 case CMPL_BASE_TYPE_RX_L2:
3255                 case CMPL_BASE_TYPE_RX_L2_V2:
3256                         if (desc == offset) {
3257                                 cons = rxcmp->opaque;
3258                                 if (rxr->rx_buf_ring[cons])
3259                                         return RTE_ETH_RX_DESC_DONE;
3260                                 else
3261                                         return RTE_ETH_RX_DESC_UNAVAIL;
3262                         }
3263                         agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3264                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3265                         desc++;
3266                         break;
3267
3268                 case CMPL_BASE_TYPE_RX_TPA_END:
3269                         if (desc == offset)
3270                                 return RTE_ETH_RX_DESC_DONE;
3271
3272                         if (BNXT_CHIP_P5(rxq->bp)) {
3273                                 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3274
3275                                 p5_tpa_end = (void *)rxcmp;
3276                                 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3277                         } else {
3278                                 struct rx_tpa_end_cmpl *tpa_end;
3279
3280                                 tpa_end = (void *)rxcmp;
3281                                 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3282                         }
3283
3284                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3285                         desc++;
3286                         break;
3287
3288                 default:
3289                         raw_cons += CMP_LEN(cmpl_type);
3290                 }
3291         }
3292
3293         return RTE_ETH_RX_DESC_AVAIL;
3294 }
3295
3296 static int
3297 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
3298 {
3299         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
3300         struct bnxt_cp_ring_info *cpr = txq->cp_ring;
3301         uint32_t ring_mask, raw_cons, nb_tx_pkts = 0;
3302         struct cmpl_base *cp_desc_ring;
3303         int rc;
3304
3305         rc = is_bnxt_in_error(txq->bp);
3306         if (rc)
3307                 return rc;
3308
3309         if (offset >= txq->nb_tx_desc)
3310                 return -EINVAL;
3311
3312         /* Return "desc done" if descriptor is available for use. */
3313         if (bnxt_tx_bds_in_hw(txq) <= offset)
3314                 return RTE_ETH_TX_DESC_DONE;
3315
3316         raw_cons = cpr->cp_raw_cons;
3317         cp_desc_ring = cpr->cp_desc_ring;
3318         ring_mask = cpr->cp_ring_struct->ring_mask;
3319
3320         /* Check to see if hw has posted a completion for the descriptor. */
3321         while (1) {
3322                 struct tx_cmpl *txcmp;
3323                 uint32_t cons;
3324
3325                 cons = RING_CMPL(ring_mask, raw_cons);
3326                 txcmp = (struct tx_cmpl *)&cp_desc_ring[cons];
3327
3328                 if (!bnxt_cpr_cmp_valid(txcmp, raw_cons, ring_mask + 1))
3329                         break;
3330
3331                 if (CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2)
3332                         nb_tx_pkts += rte_le_to_cpu_32(txcmp->opaque);
3333
3334                 if (nb_tx_pkts > offset)
3335                         return RTE_ETH_TX_DESC_DONE;
3336
3337                 raw_cons = NEXT_RAW_CMP(raw_cons);
3338         }
3339
3340         /* Descriptor is pending transmit, not yet completed by hardware. */
3341         return RTE_ETH_TX_DESC_FULL;
3342 }
3343
3344 int
3345 bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
3346                      const struct rte_flow_ops **ops)
3347 {
3348         struct bnxt *bp = dev->data->dev_private;
3349         int ret = 0;
3350
3351         if (!bp)
3352                 return -EIO;
3353
3354         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3355                 struct bnxt_representor *vfr = dev->data->dev_private;
3356                 bp = vfr->parent_dev->data->dev_private;
3357                 /* parent is deleted while children are still valid */
3358                 if (!bp) {
3359                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error\n",
3360                                     dev->data->port_id);
3361                         return -EIO;
3362                 }
3363         }
3364
3365         ret = is_bnxt_in_error(bp);
3366         if (ret)
3367                 return ret;
3368
3369         /* PMD supports thread-safe flow operations.  rte_flow API
3370          * functions can avoid mutex for multi-thread safety.
3371          */
3372         dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3373
3374         if (BNXT_TRUFLOW_EN(bp))
3375                 *ops = &bnxt_ulp_rte_flow_ops;
3376         else
3377                 *ops = &bnxt_flow_ops;
3378
3379         return ret;
3380 }
3381
3382 static const uint32_t *
3383 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3384 {
3385         static const uint32_t ptypes[] = {
3386                 RTE_PTYPE_L2_ETHER_VLAN,
3387                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3388                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3389                 RTE_PTYPE_L4_ICMP,
3390                 RTE_PTYPE_L4_TCP,
3391                 RTE_PTYPE_L4_UDP,
3392                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3393                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3394                 RTE_PTYPE_INNER_L4_ICMP,
3395                 RTE_PTYPE_INNER_L4_TCP,
3396                 RTE_PTYPE_INNER_L4_UDP,
3397                 RTE_PTYPE_UNKNOWN
3398         };
3399
3400         if (!dev->rx_pkt_burst)
3401                 return NULL;
3402
3403         return ptypes;
3404 }
3405
3406 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3407                          int reg_win)
3408 {
3409         uint32_t reg_base = *reg_arr & 0xfffff000;
3410         uint32_t win_off;
3411         int i;
3412
3413         for (i = 0; i < count; i++) {
3414                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3415                         return -ERANGE;
3416         }
3417         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3418         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3419         return 0;
3420 }
3421
3422 static int bnxt_map_ptp_regs(struct bnxt *bp)
3423 {
3424         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3425         uint32_t *reg_arr;
3426         int rc, i;
3427
3428         reg_arr = ptp->rx_regs;
3429         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3430         if (rc)
3431                 return rc;
3432
3433         reg_arr = ptp->tx_regs;
3434         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3435         if (rc)
3436                 return rc;
3437
3438         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3439                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3440
3441         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3442                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3443
3444         return 0;
3445 }
3446
3447 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3448 {
3449         rte_write32(0, (uint8_t *)bp->bar0 +
3450                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3451         rte_write32(0, (uint8_t *)bp->bar0 +
3452                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3453 }
3454
3455 static uint64_t bnxt_cc_read(struct bnxt *bp)
3456 {
3457         uint64_t ns;
3458
3459         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3460                               BNXT_GRCPF_REG_SYNC_TIME));
3461         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3462                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3463         return ns;
3464 }
3465
3466 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3467 {
3468         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3469         uint32_t fifo;
3470
3471         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3472                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3473         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3474                 return -EAGAIN;
3475
3476         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3477                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3478         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3479                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3480         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3481                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3482         rte_read32((uint8_t *)bp->bar0 + ptp->tx_mapped_regs[BNXT_PTP_TX_SEQ]);
3483
3484         return 0;
3485 }
3486
3487 static int bnxt_clr_rx_ts(struct bnxt *bp, uint64_t *last_ts)
3488 {
3489         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3490         struct bnxt_pf_info *pf = bp->pf;
3491         uint16_t port_id;
3492         int i = 0;
3493         uint32_t fifo;
3494
3495         if (!ptp || (bp->flags & BNXT_FLAG_CHIP_P5))
3496                 return -EINVAL;
3497
3498         port_id = pf->port_id;
3499         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3500                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3501         while ((fifo & BNXT_PTP_RX_FIFO_PENDING) && (i < BNXT_PTP_RX_PND_CNT)) {
3502                 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3503                             ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3504                 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3505                                         ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3506                 *last_ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3507                                         ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3508                 *last_ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3509                                         ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3510                 i++;
3511         }
3512
3513         if (i >= BNXT_PTP_RX_PND_CNT)
3514                 return -EBUSY;
3515
3516         return 0;
3517 }
3518
3519 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3520 {
3521         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3522         struct bnxt_pf_info *pf = bp->pf;
3523         uint16_t port_id;
3524         uint32_t fifo;
3525
3526         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3527                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3528         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3529                 return -EAGAIN;
3530
3531         port_id = pf->port_id;
3532         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3533                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3534
3535         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3536                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3537         if (fifo & BNXT_PTP_RX_FIFO_PENDING)
3538                 return bnxt_clr_rx_ts(bp, ts);
3539
3540         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3541                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3542         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3543                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3544
3545         return 0;
3546 }
3547
3548 static int
3549 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3550 {
3551         uint64_t ns;
3552         struct bnxt *bp = dev->data->dev_private;
3553         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3554
3555         if (!ptp)
3556                 return -ENOTSUP;
3557
3558         ns = rte_timespec_to_ns(ts);
3559         /* Set the timecounters to a new value. */
3560         ptp->tc.nsec = ns;
3561         ptp->tx_tstamp_tc.nsec = ns;
3562         ptp->rx_tstamp_tc.nsec = ns;
3563
3564         return 0;
3565 }
3566
3567 static int
3568 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3569 {
3570         struct bnxt *bp = dev->data->dev_private;
3571         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3572         uint64_t ns, systime_cycles = 0;
3573         int rc = 0;
3574
3575         if (!ptp)
3576                 return -ENOTSUP;
3577
3578         if (BNXT_CHIP_P5(bp))
3579                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3580                                              &systime_cycles);
3581         else
3582                 systime_cycles = bnxt_cc_read(bp);
3583
3584         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3585         *ts = rte_ns_to_timespec(ns);
3586
3587         return rc;
3588 }
3589 static int
3590 bnxt_timesync_enable(struct rte_eth_dev *dev)
3591 {
3592         struct bnxt *bp = dev->data->dev_private;
3593         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3594         uint32_t shift = 0;
3595         int rc;
3596
3597         if (!ptp)
3598                 return -ENOTSUP;
3599
3600         ptp->rx_filter = 1;
3601         ptp->tx_tstamp_en = 1;
3602         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3603
3604         rc = bnxt_hwrm_ptp_cfg(bp);
3605         if (rc)
3606                 return rc;
3607
3608         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3609         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3610         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3611
3612         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3613         ptp->tc.cc_shift = shift;
3614         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3615
3616         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3617         ptp->rx_tstamp_tc.cc_shift = shift;
3618         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3619
3620         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3621         ptp->tx_tstamp_tc.cc_shift = shift;
3622         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3623
3624         if (!BNXT_CHIP_P5(bp))
3625                 bnxt_map_ptp_regs(bp);
3626         else
3627                 rc = bnxt_ptp_start(bp);
3628
3629         return rc;
3630 }
3631
3632 static int
3633 bnxt_timesync_disable(struct rte_eth_dev *dev)
3634 {
3635         struct bnxt *bp = dev->data->dev_private;
3636         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3637
3638         if (!ptp)
3639                 return -ENOTSUP;
3640
3641         ptp->rx_filter = 0;
3642         ptp->tx_tstamp_en = 0;
3643         ptp->rxctl = 0;
3644
3645         bnxt_hwrm_ptp_cfg(bp);
3646
3647         if (!BNXT_CHIP_P5(bp))
3648                 bnxt_unmap_ptp_regs(bp);
3649         else
3650                 bnxt_ptp_stop(bp);
3651
3652         return 0;
3653 }
3654
3655 static int
3656 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3657                                  struct timespec *timestamp,
3658                                  uint32_t flags __rte_unused)
3659 {
3660         struct bnxt *bp = dev->data->dev_private;
3661         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3662         uint64_t rx_tstamp_cycles = 0;
3663         uint64_t ns;
3664
3665         if (!ptp)
3666                 return -ENOTSUP;
3667
3668         if (BNXT_CHIP_P5(bp))
3669                 rx_tstamp_cycles = ptp->rx_timestamp;
3670         else
3671                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3672
3673         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3674         *timestamp = rte_ns_to_timespec(ns);
3675         return  0;
3676 }
3677
3678 static int
3679 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3680                                  struct timespec *timestamp)
3681 {
3682         struct bnxt *bp = dev->data->dev_private;
3683         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3684         uint64_t tx_tstamp_cycles = 0;
3685         uint64_t ns;
3686         int rc = 0;
3687
3688         if (!ptp)
3689                 return -ENOTSUP;
3690
3691         if (BNXT_CHIP_P5(bp))
3692                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3693                                              &tx_tstamp_cycles);
3694         else
3695                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3696
3697         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3698         *timestamp = rte_ns_to_timespec(ns);
3699
3700         return rc;
3701 }
3702
3703 static int
3704 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3705 {
3706         struct bnxt *bp = dev->data->dev_private;
3707         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3708
3709         if (!ptp)
3710                 return -ENOTSUP;
3711
3712         ptp->tc.nsec += delta;
3713         ptp->tx_tstamp_tc.nsec += delta;
3714         ptp->rx_tstamp_tc.nsec += delta;
3715
3716         return 0;
3717 }
3718
3719 static int
3720 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3721 {
3722         struct bnxt *bp = dev->data->dev_private;
3723         int rc;
3724         uint32_t dir_entries;
3725         uint32_t entry_length;
3726
3727         rc = is_bnxt_in_error(bp);
3728         if (rc)
3729                 return rc;
3730
3731         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3732                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3733                     bp->pdev->addr.devid, bp->pdev->addr.function);
3734
3735         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3736         if (rc != 0)
3737                 return rc;
3738
3739         return dir_entries * entry_length;
3740 }
3741
3742 static int
3743 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3744                 struct rte_dev_eeprom_info *in_eeprom)
3745 {
3746         struct bnxt *bp = dev->data->dev_private;
3747         uint32_t index;
3748         uint32_t offset;
3749         int rc;
3750
3751         rc = is_bnxt_in_error(bp);
3752         if (rc)
3753                 return rc;
3754
3755         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3756                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3757                     bp->pdev->addr.devid, bp->pdev->addr.function,
3758                     in_eeprom->offset, in_eeprom->length);
3759
3760         if (in_eeprom->offset == 0) /* special offset value to get directory */
3761                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3762                                                 in_eeprom->data);
3763
3764         index = in_eeprom->offset >> 24;
3765         offset = in_eeprom->offset & 0xffffff;
3766
3767         if (index != 0)
3768                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3769                                            in_eeprom->length, in_eeprom->data);
3770
3771         return 0;
3772 }
3773
3774 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3775 {
3776         switch (dir_type) {
3777         case BNX_DIR_TYPE_CHIMP_PATCH:
3778         case BNX_DIR_TYPE_BOOTCODE:
3779         case BNX_DIR_TYPE_BOOTCODE_2:
3780         case BNX_DIR_TYPE_APE_FW:
3781         case BNX_DIR_TYPE_APE_PATCH:
3782         case BNX_DIR_TYPE_KONG_FW:
3783         case BNX_DIR_TYPE_KONG_PATCH:
3784         case BNX_DIR_TYPE_BONO_FW:
3785         case BNX_DIR_TYPE_BONO_PATCH:
3786                 /* FALLTHROUGH */
3787                 return true;
3788         }
3789
3790         return false;
3791 }
3792
3793 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3794 {
3795         switch (dir_type) {
3796         case BNX_DIR_TYPE_AVS:
3797         case BNX_DIR_TYPE_EXP_ROM_MBA:
3798         case BNX_DIR_TYPE_PCIE:
3799         case BNX_DIR_TYPE_TSCF_UCODE:
3800         case BNX_DIR_TYPE_EXT_PHY:
3801         case BNX_DIR_TYPE_CCM:
3802         case BNX_DIR_TYPE_ISCSI_BOOT:
3803         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3804         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3805                 /* FALLTHROUGH */
3806                 return true;
3807         }
3808
3809         return false;
3810 }
3811
3812 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3813 {
3814         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3815                 bnxt_dir_type_is_other_exec_format(dir_type);
3816 }
3817
3818 static int
3819 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3820                 struct rte_dev_eeprom_info *in_eeprom)
3821 {
3822         struct bnxt *bp = dev->data->dev_private;
3823         uint8_t index, dir_op;
3824         uint16_t type, ext, ordinal, attr;
3825         int rc;
3826
3827         rc = is_bnxt_in_error(bp);
3828         if (rc)
3829                 return rc;
3830
3831         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3832                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3833                     bp->pdev->addr.devid, bp->pdev->addr.function,
3834                     in_eeprom->offset, in_eeprom->length);
3835
3836         if (!BNXT_PF(bp)) {
3837                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3838                 return -EINVAL;
3839         }
3840
3841         type = in_eeprom->magic >> 16;
3842
3843         if (type == 0xffff) { /* special value for directory operations */
3844                 index = in_eeprom->magic & 0xff;
3845                 dir_op = in_eeprom->magic >> 8;
3846                 if (index == 0)
3847                         return -EINVAL;
3848                 switch (dir_op) {
3849                 case 0x0e: /* erase */
3850                         if (in_eeprom->offset != ~in_eeprom->magic)
3851                                 return -EINVAL;
3852                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3853                 default:
3854                         return -EINVAL;
3855                 }
3856         }
3857
3858         /* Create or re-write an NVM item: */
3859         if (bnxt_dir_type_is_executable(type) == true)
3860                 return -EOPNOTSUPP;
3861         ext = in_eeprom->magic & 0xffff;
3862         ordinal = in_eeprom->offset >> 16;
3863         attr = in_eeprom->offset & 0xffff;
3864
3865         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3866                                      in_eeprom->data, in_eeprom->length);
3867 }
3868
3869 static int bnxt_get_module_info(struct rte_eth_dev *dev,
3870                                 struct rte_eth_dev_module_info *modinfo)
3871 {
3872         uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1];
3873         struct bnxt *bp = dev->data->dev_private;
3874         int rc;
3875
3876         /* No point in going further if phy status indicates
3877          * module is not inserted or if it is powered down or
3878          * if it is of type 10GBase-T
3879          */
3880         if (bp->link_info->module_status >
3881             HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG) {
3882                 PMD_DRV_LOG(NOTICE, "Port %u : Module is not inserted or is powered down\n",
3883                             dev->data->port_id);
3884                 return -ENOTSUP;
3885         }
3886
3887         /* This feature is not supported in older firmware versions */
3888         if (bp->hwrm_spec_code < 0x10202) {
3889                 PMD_DRV_LOG(NOTICE, "Port %u : Feature is not supported in older firmware\n",
3890                             dev->data->port_id);
3891                 return -ENOTSUP;
3892         }
3893
3894         rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
3895                                                    SFF_DIAG_SUPPORT_OFFSET + 1,
3896                                                    module_info);
3897
3898         if (rc)
3899                 return rc;
3900
3901         switch (module_info[0]) {
3902         case SFF_MODULE_ID_SFP:
3903                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
3904                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
3905                 if (module_info[SFF_DIAG_SUPPORT_OFFSET] == 0)
3906                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN;
3907                 break;
3908         case SFF_MODULE_ID_QSFP:
3909         case SFF_MODULE_ID_QSFP_PLUS:
3910                 modinfo->type = RTE_ETH_MODULE_SFF_8436;
3911                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN;
3912                 break;
3913         case SFF_MODULE_ID_QSFP28:
3914                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
3915                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
3916                 if (module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK)
3917                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_LEN;
3918                 break;
3919         default:
3920                 PMD_DRV_LOG(NOTICE, "Port %u : Unsupported module\n", dev->data->port_id);
3921                 return -ENOTSUP;
3922         }
3923
3924         PMD_DRV_LOG(INFO, "Port %u : modinfo->type = %d modinfo->eeprom_len = %d\n",
3925                     dev->data->port_id, modinfo->type, modinfo->eeprom_len);
3926
3927         return 0;
3928 }
3929
3930 static int bnxt_get_module_eeprom(struct rte_eth_dev *dev,
3931                                   struct rte_dev_eeprom_info *info)
3932 {
3933         uint8_t pg_addr[5] = { I2C_DEV_ADDR_A0, I2C_DEV_ADDR_A0 };
3934         uint32_t offset = info->offset, length = info->length;
3935         uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1];
3936         struct bnxt *bp = dev->data->dev_private;
3937         uint8_t *data = info->data;
3938         uint8_t page = offset >> 7;
3939         uint8_t max_pages = 2;
3940         uint8_t opt_pages;
3941         int rc;
3942
3943         rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
3944                                                    SFF_DIAG_SUPPORT_OFFSET + 1,
3945                                                    module_info);
3946         if (rc)
3947                 return rc;
3948
3949         switch (module_info[0]) {
3950         case SFF_MODULE_ID_SFP:
3951                 module_info[SFF_DIAG_SUPPORT_OFFSET] = 0;
3952                 if (module_info[SFF_DIAG_SUPPORT_OFFSET]) {
3953                         pg_addr[2] = I2C_DEV_ADDR_A2;
3954                         pg_addr[3] = I2C_DEV_ADDR_A2;
3955                         max_pages = 4;
3956                 }
3957                 break;
3958         case SFF_MODULE_ID_QSFP28:
3959                 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0,
3960                                                            SFF8636_OPT_PAGES_OFFSET,
3961                                                            1, &opt_pages);
3962                 if (rc)
3963                         return rc;
3964
3965                 if (opt_pages & SFF8636_PAGE1_MASK) {
3966                         pg_addr[2] = I2C_DEV_ADDR_A0;
3967                         max_pages = 3;
3968                 }
3969                 if (opt_pages & SFF8636_PAGE2_MASK) {
3970                         pg_addr[3] = I2C_DEV_ADDR_A0;
3971                         max_pages = 4;
3972                 }
3973                 if (~module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK) {
3974                         pg_addr[4] = I2C_DEV_ADDR_A0;
3975                         max_pages = 5;
3976                 }
3977                 break;
3978         default:
3979                 break;
3980         }
3981
3982         memset(data, 0, length);
3983
3984         offset &= 0xff;
3985         while (length && page < max_pages) {
3986                 uint8_t raw_page = page ? page - 1 : 0;
3987                 uint16_t chunk;
3988
3989                 if (pg_addr[page] == I2C_DEV_ADDR_A2)
3990                         raw_page = 0;
3991                 else if (page)
3992                         offset |= 0x80;
3993                 chunk = RTE_MIN(length, 256 - offset);
3994
3995                 if (pg_addr[page]) {
3996                         rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, pg_addr[page],
3997                                                                    raw_page, offset,
3998                                                                    chunk, data);
3999                         if (rc)
4000                                 return rc;
4001                 }
4002
4003                 data += chunk;
4004                 length -= chunk;
4005                 offset = 0;
4006                 page += 1 + (chunk > 128);
4007         }
4008
4009         return length ? -EINVAL : 0;
4010 }
4011
4012 /*
4013  * Initialization
4014  */
4015
4016 static const struct eth_dev_ops bnxt_dev_ops = {
4017         .dev_infos_get = bnxt_dev_info_get_op,
4018         .dev_close = bnxt_dev_close_op,
4019         .dev_configure = bnxt_dev_configure_op,
4020         .dev_start = bnxt_dev_start_op,
4021         .dev_stop = bnxt_dev_stop_op,
4022         .dev_set_link_up = bnxt_dev_set_link_up_op,
4023         .dev_set_link_down = bnxt_dev_set_link_down_op,
4024         .stats_get = bnxt_stats_get_op,
4025         .stats_reset = bnxt_stats_reset_op,
4026         .rx_queue_setup = bnxt_rx_queue_setup_op,
4027         .rx_queue_release = bnxt_rx_queue_release_op,
4028         .tx_queue_setup = bnxt_tx_queue_setup_op,
4029         .tx_queue_release = bnxt_tx_queue_release_op,
4030         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4031         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4032         .reta_update = bnxt_reta_update_op,
4033         .reta_query = bnxt_reta_query_op,
4034         .rss_hash_update = bnxt_rss_hash_update_op,
4035         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4036         .link_update = bnxt_link_update_op,
4037         .promiscuous_enable = bnxt_promiscuous_enable_op,
4038         .promiscuous_disable = bnxt_promiscuous_disable_op,
4039         .allmulticast_enable = bnxt_allmulticast_enable_op,
4040         .allmulticast_disable = bnxt_allmulticast_disable_op,
4041         .mac_addr_add = bnxt_mac_addr_add_op,
4042         .mac_addr_remove = bnxt_mac_addr_remove_op,
4043         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4044         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4045         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4046         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4047         .vlan_filter_set = bnxt_vlan_filter_set_op,
4048         .vlan_offload_set = bnxt_vlan_offload_set_op,
4049         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4050         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4051         .mtu_set = bnxt_mtu_set_op,
4052         .mac_addr_set = bnxt_set_default_mac_addr_op,
4053         .xstats_get = bnxt_dev_xstats_get_op,
4054         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4055         .xstats_reset = bnxt_dev_xstats_reset_op,
4056         .fw_version_get = bnxt_fw_version_get,
4057         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4058         .rxq_info_get = bnxt_rxq_info_get_op,
4059         .txq_info_get = bnxt_txq_info_get_op,
4060         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4061         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4062         .dev_led_on = bnxt_dev_led_on_op,
4063         .dev_led_off = bnxt_dev_led_off_op,
4064         .rx_queue_start = bnxt_rx_queue_start,
4065         .rx_queue_stop = bnxt_rx_queue_stop,
4066         .tx_queue_start = bnxt_tx_queue_start,
4067         .tx_queue_stop = bnxt_tx_queue_stop,
4068         .flow_ops_get = bnxt_flow_ops_get_op,
4069         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4070         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4071         .get_eeprom           = bnxt_get_eeprom_op,
4072         .set_eeprom           = bnxt_set_eeprom_op,
4073         .get_module_info = bnxt_get_module_info,
4074         .get_module_eeprom = bnxt_get_module_eeprom,
4075         .timesync_enable      = bnxt_timesync_enable,
4076         .timesync_disable     = bnxt_timesync_disable,
4077         .timesync_read_time   = bnxt_timesync_read_time,
4078         .timesync_write_time   = bnxt_timesync_write_time,
4079         .timesync_adjust_time = bnxt_timesync_adjust_time,
4080         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4081         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4082 };
4083
4084 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4085 {
4086         uint32_t offset;
4087
4088         /* Only pre-map the reset GRC registers using window 3 */
4089         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4090                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4091
4092         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4093
4094         return offset;
4095 }
4096
4097 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4098 {
4099         struct bnxt_error_recovery_info *info = bp->recovery_info;
4100         uint32_t reg_base = 0xffffffff;
4101         int i;
4102
4103         /* Only pre-map the monitoring GRC registers using window 2 */
4104         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4105                 uint32_t reg = info->status_regs[i];
4106
4107                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4108                         continue;
4109
4110                 if (reg_base == 0xffffffff)
4111                         reg_base = reg & 0xfffff000;
4112                 if ((reg & 0xfffff000) != reg_base)
4113                         return -ERANGE;
4114
4115                 /* Use mask 0xffc as the Lower 2 bits indicates
4116                  * address space location
4117                  */
4118                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4119                                                 (reg & 0xffc);
4120         }
4121
4122         if (reg_base == 0xffffffff)
4123                 return 0;
4124
4125         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4126                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4127
4128         return 0;
4129 }
4130
4131 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4132 {
4133         struct bnxt_error_recovery_info *info = bp->recovery_info;
4134         uint32_t delay = info->delay_after_reset[index];
4135         uint32_t val = info->reset_reg_val[index];
4136         uint32_t reg = info->reset_reg[index];
4137         uint32_t type, offset;
4138         int ret;
4139
4140         type = BNXT_FW_STATUS_REG_TYPE(reg);
4141         offset = BNXT_FW_STATUS_REG_OFF(reg);
4142
4143         switch (type) {
4144         case BNXT_FW_STATUS_REG_TYPE_CFG:
4145                 ret = rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4146                 if (ret < 0) {
4147                         PMD_DRV_LOG(ERR, "Failed to write %#x at PCI offset %#x",
4148                                     val, offset);
4149                         return;
4150                 }
4151                 break;
4152         case BNXT_FW_STATUS_REG_TYPE_GRC:
4153                 offset = bnxt_map_reset_regs(bp, offset);
4154                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4155                 break;
4156         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4157                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4158                 break;
4159         }
4160         /* wait on a specific interval of time until core reset is complete */
4161         if (delay)
4162                 rte_delay_ms(delay);
4163 }
4164
4165 static void bnxt_dev_cleanup(struct bnxt *bp)
4166 {
4167         bp->eth_dev->data->dev_link.link_status = 0;
4168         bp->link_info->link_up = 0;
4169         if (bp->eth_dev->data->dev_started)
4170                 bnxt_dev_stop(bp->eth_dev);
4171
4172         bnxt_uninit_resources(bp, true);
4173 }
4174
4175 static int
4176 bnxt_check_fw_reset_done(struct bnxt *bp)
4177 {
4178         int timeout = bp->fw_reset_max_msecs;
4179         uint16_t val = 0;
4180         int rc;
4181
4182         do {
4183                 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4184                 if (rc < 0) {
4185                         PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4186                         return rc;
4187                 }
4188                 if (val != 0xffff)
4189                         break;
4190                 rte_delay_ms(1);
4191         } while (timeout--);
4192
4193         if (val == 0xffff) {
4194                 PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n");
4195                 return -1;
4196         }
4197
4198         return 0;
4199 }
4200
4201 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4202 {
4203         struct rte_eth_dev *dev = bp->eth_dev;
4204         struct rte_vlan_filter_conf *vfc;
4205         int vidx, vbit, rc;
4206         uint16_t vlan_id;
4207
4208         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4209                 vfc = &dev->data->vlan_filter_conf;
4210                 vidx = vlan_id / 64;
4211                 vbit = vlan_id % 64;
4212
4213                 /* Each bit corresponds to a VLAN id */
4214                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4215                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4216                         if (rc)
4217                                 return rc;
4218                 }
4219         }
4220
4221         return 0;
4222 }
4223
4224 static int bnxt_restore_mac_filters(struct bnxt *bp)
4225 {
4226         struct rte_eth_dev *dev = bp->eth_dev;
4227         struct rte_eth_dev_info dev_info;
4228         struct rte_ether_addr *addr;
4229         uint64_t pool_mask;
4230         uint32_t pool = 0;
4231         uint32_t i;
4232         int rc;
4233
4234         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4235                 return 0;
4236
4237         rc = bnxt_dev_info_get_op(dev, &dev_info);
4238         if (rc)
4239                 return rc;
4240
4241         /* replay MAC address configuration */
4242         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4243                 addr = &dev->data->mac_addrs[i];
4244
4245                 /* skip zero address */
4246                 if (rte_is_zero_ether_addr(addr))
4247                         continue;
4248
4249                 pool = 0;
4250                 pool_mask = dev->data->mac_pool_sel[i];
4251
4252                 do {
4253                         if (pool_mask & 1ULL) {
4254                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4255                                 if (rc)
4256                                         return rc;
4257                         }
4258                         pool_mask >>= 1;
4259                         pool++;
4260                 } while (pool_mask);
4261         }
4262
4263         return 0;
4264 }
4265
4266 static int bnxt_restore_filters(struct bnxt *bp)
4267 {
4268         struct rte_eth_dev *dev = bp->eth_dev;
4269         int ret = 0;
4270
4271         if (dev->data->all_multicast) {
4272                 ret = bnxt_allmulticast_enable_op(dev);
4273                 if (ret)
4274                         return ret;
4275         }
4276         if (dev->data->promiscuous) {
4277                 ret = bnxt_promiscuous_enable_op(dev);
4278                 if (ret)
4279                         return ret;
4280         }
4281
4282         ret = bnxt_restore_mac_filters(bp);
4283         if (ret)
4284                 return ret;
4285
4286         ret = bnxt_restore_vlan_filters(bp);
4287         /* TODO restore other filters as well */
4288         return ret;
4289 }
4290
4291 static int bnxt_check_fw_ready(struct bnxt *bp)
4292 {
4293         int timeout = bp->fw_reset_max_msecs;
4294         int rc = 0;
4295
4296         do {
4297                 rc = bnxt_hwrm_poll_ver_get(bp);
4298                 if (rc == 0)
4299                         break;
4300                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4301                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4302         } while (rc && timeout > 0);
4303
4304         if (rc)
4305                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4306
4307         return rc;
4308 }
4309
4310 static void bnxt_dev_recover(void *arg)
4311 {
4312         struct bnxt *bp = arg;
4313         int rc = 0;
4314
4315         pthread_mutex_lock(&bp->err_recovery_lock);
4316
4317         if (!bp->fw_reset_min_msecs) {
4318                 rc = bnxt_check_fw_reset_done(bp);
4319                 if (rc)
4320                         goto err;
4321         }
4322
4323         /* Clear Error flag so that device re-init should happen */
4324         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4325
4326         rc = bnxt_check_fw_ready(bp);
4327         if (rc)
4328                 goto err;
4329
4330         rc = bnxt_init_resources(bp, true);
4331         if (rc) {
4332                 PMD_DRV_LOG(ERR,
4333                             "Failed to initialize resources after reset\n");
4334                 goto err;
4335         }
4336         /* clear reset flag as the device is initialized now */
4337         bp->flags &= ~BNXT_FLAG_FW_RESET;
4338
4339         rc = bnxt_dev_start_op(bp->eth_dev);
4340         if (rc) {
4341                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4342                 goto err_start;
4343         }
4344
4345         rc = bnxt_restore_filters(bp);
4346         if (rc)
4347                 goto err_start;
4348
4349         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4350         pthread_mutex_unlock(&bp->err_recovery_lock);
4351
4352         return;
4353 err_start:
4354         bnxt_dev_stop(bp->eth_dev);
4355 err:
4356         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4357         bnxt_uninit_resources(bp, false);
4358         if (bp->eth_dev->data->dev_conf.intr_conf.rmv)
4359                 rte_eth_dev_callback_process(bp->eth_dev,
4360                                              RTE_ETH_EVENT_INTR_RMV,
4361                                              NULL);
4362         pthread_mutex_unlock(&bp->err_recovery_lock);
4363         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4364 }
4365
4366 void bnxt_dev_reset_and_resume(void *arg)
4367 {
4368         struct bnxt *bp = arg;
4369         uint32_t us = US_PER_MS * bp->fw_reset_min_msecs;
4370         uint16_t val = 0;
4371         int rc;
4372
4373         bnxt_dev_cleanup(bp);
4374
4375         bnxt_wait_for_device_shutdown(bp);
4376
4377         /* During some fatal firmware error conditions, the PCI config space
4378          * register 0x2e which normally contains the subsystem ID will become
4379          * 0xffff. This register will revert back to the normal value after
4380          * the chip has completed core reset. If we detect this condition,
4381          * we can poll this config register immediately for the value to revert.
4382          */
4383         if (bp->flags & BNXT_FLAG_FATAL_ERROR) {
4384                 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4385                 if (rc < 0) {
4386                         PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4387                         return;
4388                 }
4389                 if (val == 0xffff) {
4390                         bp->fw_reset_min_msecs = 0;
4391                         us = 1;
4392                 }
4393         }
4394
4395         rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp);
4396         if (rc)
4397                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4398 }
4399
4400 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4401 {
4402         struct bnxt_error_recovery_info *info = bp->recovery_info;
4403         uint32_t reg = info->status_regs[index];
4404         uint32_t type, offset, val = 0;
4405         int ret = 0;
4406
4407         type = BNXT_FW_STATUS_REG_TYPE(reg);
4408         offset = BNXT_FW_STATUS_REG_OFF(reg);
4409
4410         switch (type) {
4411         case BNXT_FW_STATUS_REG_TYPE_CFG:
4412                 ret = rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4413                 if (ret < 0)
4414                         PMD_DRV_LOG(ERR, "Failed to read PCI offset %#x",
4415                                     offset);
4416                 break;
4417         case BNXT_FW_STATUS_REG_TYPE_GRC:
4418                 offset = info->mapped_status_regs[index];
4419                 /* FALLTHROUGH */
4420         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4421                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4422                                        offset));
4423                 break;
4424         }
4425
4426         return val;
4427 }
4428
4429 static int bnxt_fw_reset_all(struct bnxt *bp)
4430 {
4431         struct bnxt_error_recovery_info *info = bp->recovery_info;
4432         uint32_t i;
4433         int rc = 0;
4434
4435         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4436                 /* Reset through master function driver */
4437                 for (i = 0; i < info->reg_array_cnt; i++)
4438                         bnxt_write_fw_reset_reg(bp, i);
4439                 /* Wait for time specified by FW after triggering reset */
4440                 rte_delay_ms(info->master_func_wait_period_after_reset);
4441         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4442                 /* Reset with the help of Kong processor */
4443                 rc = bnxt_hwrm_fw_reset(bp);
4444                 if (rc)
4445                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4446         }
4447
4448         return rc;
4449 }
4450
4451 static void bnxt_fw_reset_cb(void *arg)
4452 {
4453         struct bnxt *bp = arg;
4454         struct bnxt_error_recovery_info *info = bp->recovery_info;
4455         int rc = 0;
4456
4457         /* Only Master function can do FW reset */
4458         if (bnxt_is_master_func(bp) &&
4459             bnxt_is_recovery_enabled(bp)) {
4460                 rc = bnxt_fw_reset_all(bp);
4461                 if (rc) {
4462                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4463                         return;
4464                 }
4465         }
4466
4467         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4468          * EXCEPTION_FATAL_ASYNC event to all the functions
4469          * (including MASTER FUNC). After receiving this Async, all the active
4470          * drivers should treat this case as FW initiated recovery
4471          */
4472         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4473                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4474                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4475
4476                 /* To recover from error */
4477                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4478                                   (void *)bp);
4479         }
4480 }
4481
4482 /* Driver should poll FW heartbeat, reset_counter with the frequency
4483  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4484  * When the driver detects heartbeat stop or change in reset_counter,
4485  * it has to trigger a reset to recover from the error condition.
4486  * A “master PF” is the function who will have the privilege to
4487  * initiate the chimp reset. The master PF will be elected by the
4488  * firmware and will be notified through async message.
4489  */
4490 static void bnxt_check_fw_health(void *arg)
4491 {
4492         struct bnxt *bp = arg;
4493         struct bnxt_error_recovery_info *info = bp->recovery_info;
4494         uint32_t val = 0, wait_msec;
4495
4496         if (!info || !bnxt_is_recovery_enabled(bp) ||
4497             is_bnxt_in_error(bp))
4498                 return;
4499
4500         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4501         if (val == info->last_heart_beat)
4502                 goto reset;
4503
4504         info->last_heart_beat = val;
4505
4506         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4507         if (val != info->last_reset_counter)
4508                 goto reset;
4509
4510         info->last_reset_counter = val;
4511
4512         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4513                           bnxt_check_fw_health, (void *)bp);
4514
4515         return;
4516 reset:
4517         /* Stop DMA to/from device */
4518         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4519         bp->flags |= BNXT_FLAG_FW_RESET;
4520
4521         bnxt_stop_rxtx(bp);
4522
4523         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4524
4525         if (bnxt_is_master_func(bp))
4526                 wait_msec = info->master_func_wait_period;
4527         else
4528                 wait_msec = info->normal_func_wait_period;
4529
4530         rte_eal_alarm_set(US_PER_MS * wait_msec,
4531                           bnxt_fw_reset_cb, (void *)bp);
4532 }
4533
4534 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4535 {
4536         uint32_t polling_freq;
4537
4538         pthread_mutex_lock(&bp->health_check_lock);
4539
4540         if (!bnxt_is_recovery_enabled(bp))
4541                 goto done;
4542
4543         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4544                 goto done;
4545
4546         polling_freq = bp->recovery_info->driver_polling_freq;
4547
4548         rte_eal_alarm_set(US_PER_MS * polling_freq,
4549                           bnxt_check_fw_health, (void *)bp);
4550         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4551
4552 done:
4553         pthread_mutex_unlock(&bp->health_check_lock);
4554 }
4555
4556 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4557 {
4558         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4559         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4560 }
4561
4562 static bool bnxt_vf_pciid(uint16_t device_id)
4563 {
4564         switch (device_id) {
4565         case BROADCOM_DEV_ID_57304_VF:
4566         case BROADCOM_DEV_ID_57406_VF:
4567         case BROADCOM_DEV_ID_5731X_VF:
4568         case BROADCOM_DEV_ID_5741X_VF:
4569         case BROADCOM_DEV_ID_57414_VF:
4570         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4571         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4572         case BROADCOM_DEV_ID_58802_VF:
4573         case BROADCOM_DEV_ID_57500_VF1:
4574         case BROADCOM_DEV_ID_57500_VF2:
4575         case BROADCOM_DEV_ID_58818_VF:
4576                 /* FALLTHROUGH */
4577                 return true;
4578         default:
4579                 return false;
4580         }
4581 }
4582
4583 /* Phase 5 device */
4584 static bool bnxt_p5_device(uint16_t device_id)
4585 {
4586         switch (device_id) {
4587         case BROADCOM_DEV_ID_57508:
4588         case BROADCOM_DEV_ID_57504:
4589         case BROADCOM_DEV_ID_57502:
4590         case BROADCOM_DEV_ID_57508_MF1:
4591         case BROADCOM_DEV_ID_57504_MF1:
4592         case BROADCOM_DEV_ID_57502_MF1:
4593         case BROADCOM_DEV_ID_57508_MF2:
4594         case BROADCOM_DEV_ID_57504_MF2:
4595         case BROADCOM_DEV_ID_57502_MF2:
4596         case BROADCOM_DEV_ID_57500_VF1:
4597         case BROADCOM_DEV_ID_57500_VF2:
4598         case BROADCOM_DEV_ID_58812:
4599         case BROADCOM_DEV_ID_58814:
4600         case BROADCOM_DEV_ID_58818:
4601         case BROADCOM_DEV_ID_58818_VF:
4602                 /* FALLTHROUGH */
4603                 return true;
4604         default:
4605                 return false;
4606         }
4607 }
4608
4609 bool bnxt_stratus_device(struct bnxt *bp)
4610 {
4611         uint16_t device_id = bp->pdev->id.device_id;
4612
4613         switch (device_id) {
4614         case BROADCOM_DEV_ID_STRATUS_NIC:
4615         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4616         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4617                 /* FALLTHROUGH */
4618                 return true;
4619         default:
4620                 return false;
4621         }
4622 }
4623
4624 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev)
4625 {
4626         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4627         struct bnxt *bp = eth_dev->data->dev_private;
4628
4629         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4630         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4631         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4632         if (!bp->bar0 || !bp->doorbell_base) {
4633                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4634                 return -ENODEV;
4635         }
4636
4637         bp->eth_dev = eth_dev;
4638         bp->pdev = pci_dev;
4639
4640         return 0;
4641 }
4642
4643 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4644                                   struct bnxt_ctx_pg_info *ctx_pg,
4645                                   uint32_t mem_size,
4646                                   const char *suffix,
4647                                   uint16_t idx)
4648 {
4649         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4650         const struct rte_memzone *mz = NULL;
4651         char mz_name[RTE_MEMZONE_NAMESIZE];
4652         rte_iova_t mz_phys_addr;
4653         uint64_t valid_bits = 0;
4654         uint32_t sz;
4655         int i;
4656
4657         if (!mem_size)
4658                 return 0;
4659
4660         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4661                          BNXT_PAGE_SIZE;
4662         rmem->page_size = BNXT_PAGE_SIZE;
4663         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4664         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4665         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4666
4667         valid_bits = PTU_PTE_VALID;
4668
4669         if (rmem->nr_pages > 1) {
4670                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4671                          "bnxt_ctx_pg_tbl%s_%x_%d",
4672                          suffix, idx, bp->eth_dev->data->port_id);
4673                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4674                 mz = rte_memzone_lookup(mz_name);
4675                 if (!mz) {
4676                         mz = rte_memzone_reserve_aligned(mz_name,
4677                                                 rmem->nr_pages * 8,
4678                                                 bp->eth_dev->device->numa_node,
4679                                                 RTE_MEMZONE_2MB |
4680                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4681                                                 RTE_MEMZONE_IOVA_CONTIG,
4682                                                 BNXT_PAGE_SIZE);
4683                         if (mz == NULL)
4684                                 return -ENOMEM;
4685                 }
4686
4687                 memset(mz->addr, 0, mz->len);
4688                 mz_phys_addr = mz->iova;
4689
4690                 rmem->pg_tbl = mz->addr;
4691                 rmem->pg_tbl_map = mz_phys_addr;
4692                 rmem->pg_tbl_mz = mz;
4693         }
4694
4695         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4696                  suffix, idx, bp->eth_dev->data->port_id);
4697         mz = rte_memzone_lookup(mz_name);
4698         if (!mz) {
4699                 mz = rte_memzone_reserve_aligned(mz_name,
4700                                                  mem_size,
4701                                                  bp->eth_dev->device->numa_node,
4702                                                  RTE_MEMZONE_1GB |
4703                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4704                                                  RTE_MEMZONE_IOVA_CONTIG,
4705                                                  BNXT_PAGE_SIZE);
4706                 if (mz == NULL)
4707                         return -ENOMEM;
4708         }
4709
4710         memset(mz->addr, 0, mz->len);
4711         mz_phys_addr = mz->iova;
4712
4713         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4714                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4715                 rmem->dma_arr[i] = mz_phys_addr + sz;
4716
4717                 if (rmem->nr_pages > 1) {
4718                         if (i == rmem->nr_pages - 2 &&
4719                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4720                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4721                         else if (i == rmem->nr_pages - 1 &&
4722                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4723                                 valid_bits |= PTU_PTE_LAST;
4724
4725                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4726                                                            valid_bits);
4727                 }
4728         }
4729
4730         rmem->mz = mz;
4731         if (rmem->vmem_size)
4732                 rmem->vmem = (void **)mz->addr;
4733         rmem->dma_arr[0] = mz_phys_addr;
4734         return 0;
4735 }
4736
4737 static void bnxt_free_ctx_mem(struct bnxt *bp)
4738 {
4739         int i;
4740
4741         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4742                 return;
4743
4744         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4745         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4746         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4747         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4748         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4749         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4750         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4751         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4752         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4753         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4754         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4755
4756         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4757                 if (bp->ctx->tqm_mem[i])
4758                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4759         }
4760
4761         rte_free(bp->ctx);
4762         bp->ctx = NULL;
4763 }
4764
4765 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4766
4767 #define min_t(type, x, y) ({                    \
4768         type __min1 = (x);                      \
4769         type __min2 = (y);                      \
4770         __min1 < __min2 ? __min1 : __min2; })
4771
4772 #define max_t(type, x, y) ({                    \
4773         type __max1 = (x);                      \
4774         type __max2 = (y);                      \
4775         __max1 > __max2 ? __max1 : __max2; })
4776
4777 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4778
4779 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4780 {
4781         struct bnxt_ctx_pg_info *ctx_pg;
4782         struct bnxt_ctx_mem_info *ctx;
4783         uint32_t mem_size, ena, entries;
4784         uint32_t entries_sp, min;
4785         int i, rc;
4786
4787         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4788         if (rc) {
4789                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4790                 return rc;
4791         }
4792         ctx = bp->ctx;
4793         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4794                 return 0;
4795
4796         ctx_pg = &ctx->qp_mem;
4797         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4798         if (ctx->qp_entry_size) {
4799                 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4800                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4801                 if (rc)
4802                         return rc;
4803         }
4804
4805         ctx_pg = &ctx->srq_mem;
4806         ctx_pg->entries = ctx->srq_max_l2_entries;
4807         if (ctx->srq_entry_size) {
4808                 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4809                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4810                 if (rc)
4811                         return rc;
4812         }
4813
4814         ctx_pg = &ctx->cq_mem;
4815         ctx_pg->entries = ctx->cq_max_l2_entries;
4816         if (ctx->cq_entry_size) {
4817                 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4818                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4819                 if (rc)
4820                         return rc;
4821         }
4822
4823         ctx_pg = &ctx->vnic_mem;
4824         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4825                 ctx->vnic_max_ring_table_entries;
4826         if (ctx->vnic_entry_size) {
4827                 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4828                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4829                 if (rc)
4830                         return rc;
4831         }
4832
4833         ctx_pg = &ctx->stat_mem;
4834         ctx_pg->entries = ctx->stat_max_entries;
4835         if (ctx->stat_entry_size) {
4836                 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4837                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4838                 if (rc)
4839                         return rc;
4840         }
4841
4842         min = ctx->tqm_min_entries_per_ring;
4843
4844         entries_sp = ctx->qp_max_l2_entries +
4845                      ctx->vnic_max_vnic_entries +
4846                      2 * ctx->qp_min_qp1_entries + min;
4847         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4848
4849         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4850         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4851         entries = clamp_t(uint32_t, entries, min,
4852                           ctx->tqm_max_entries_per_ring);
4853         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4854                 /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7.
4855                  * i > 8 is other ext rings.
4856                  */
4857                 ctx_pg = ctx->tqm_mem[i];
4858                 ctx_pg->entries = i ? entries : entries_sp;
4859                 if (ctx->tqm_entry_size) {
4860                         mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4861                         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size,
4862                                                     "tqm_mem", i);
4863                         if (rc)
4864                                 return rc;
4865                 }
4866                 if (i < BNXT_MAX_TQM_LEGACY_RINGS)
4867                         ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4868                 else
4869                         ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8;
4870         }
4871
4872         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4873         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4874         if (rc)
4875                 PMD_DRV_LOG(ERR,
4876                             "Failed to configure context mem: rc = %d\n", rc);
4877         else
4878                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4879
4880         return rc;
4881 }
4882
4883 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4884 {
4885         struct rte_pci_device *pci_dev = bp->pdev;
4886         char mz_name[RTE_MEMZONE_NAMESIZE];
4887         const struct rte_memzone *mz = NULL;
4888         uint32_t total_alloc_len;
4889         rte_iova_t mz_phys_addr;
4890
4891         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4892                 return 0;
4893
4894         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4895                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4896                  pci_dev->addr.bus, pci_dev->addr.devid,
4897                  pci_dev->addr.function, "rx_port_stats");
4898         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4899         mz = rte_memzone_lookup(mz_name);
4900         total_alloc_len =
4901                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4902                                        sizeof(struct rx_port_stats_ext) + 512);
4903         if (!mz) {
4904                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4905                                          SOCKET_ID_ANY,
4906                                          RTE_MEMZONE_2MB |
4907                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4908                                          RTE_MEMZONE_IOVA_CONTIG);
4909                 if (mz == NULL)
4910                         return -ENOMEM;
4911         }
4912         memset(mz->addr, 0, mz->len);
4913         mz_phys_addr = mz->iova;
4914
4915         bp->rx_mem_zone = (const void *)mz;
4916         bp->hw_rx_port_stats = mz->addr;
4917         bp->hw_rx_port_stats_map = mz_phys_addr;
4918
4919         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4920                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4921                  pci_dev->addr.bus, pci_dev->addr.devid,
4922                  pci_dev->addr.function, "tx_port_stats");
4923         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4924         mz = rte_memzone_lookup(mz_name);
4925         total_alloc_len =
4926                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4927                                        sizeof(struct tx_port_stats_ext) + 512);
4928         if (!mz) {
4929                 mz = rte_memzone_reserve(mz_name,
4930                                          total_alloc_len,
4931                                          SOCKET_ID_ANY,
4932                                          RTE_MEMZONE_2MB |
4933                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4934                                          RTE_MEMZONE_IOVA_CONTIG);
4935                 if (mz == NULL)
4936                         return -ENOMEM;
4937         }
4938         memset(mz->addr, 0, mz->len);
4939         mz_phys_addr = mz->iova;
4940
4941         bp->tx_mem_zone = (const void *)mz;
4942         bp->hw_tx_port_stats = mz->addr;
4943         bp->hw_tx_port_stats_map = mz_phys_addr;
4944         bp->flags |= BNXT_FLAG_PORT_STATS;
4945
4946         /* Display extended statistics if FW supports it */
4947         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4948             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4949             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4950                 return 0;
4951
4952         bp->hw_rx_port_stats_ext = (void *)
4953                 ((uint8_t *)bp->hw_rx_port_stats +
4954                  sizeof(struct rx_port_stats));
4955         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4956                 sizeof(struct rx_port_stats);
4957         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4958
4959         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4960             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4961                 bp->hw_tx_port_stats_ext = (void *)
4962                         ((uint8_t *)bp->hw_tx_port_stats +
4963                          sizeof(struct tx_port_stats));
4964                 bp->hw_tx_port_stats_ext_map =
4965                         bp->hw_tx_port_stats_map +
4966                         sizeof(struct tx_port_stats);
4967                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4968         }
4969
4970         return 0;
4971 }
4972
4973 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4974 {
4975         struct bnxt *bp = eth_dev->data->dev_private;
4976         int rc = 0;
4977
4978         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4979                                                RTE_ETHER_ADDR_LEN *
4980                                                bp->max_l2_ctx,
4981                                                0);
4982         if (eth_dev->data->mac_addrs == NULL) {
4983                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4984                 return -ENOMEM;
4985         }
4986
4987         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4988                 if (BNXT_PF(bp))
4989                         return -EINVAL;
4990
4991                 /* Generate a random MAC address, if none was assigned by PF */
4992                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4993                 bnxt_eth_hw_addr_random(bp->mac_addr);
4994                 PMD_DRV_LOG(INFO,
4995                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4996                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4997                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4998
4999                 rc = bnxt_hwrm_set_mac(bp);
5000                 if (rc)
5001                         return rc;
5002         }
5003
5004         /* Copy the permanent MAC from the FUNC_QCAPS response */
5005         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5006
5007         return rc;
5008 }
5009
5010 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5011 {
5012         int rc = 0;
5013
5014         /* MAC is already configured in FW */
5015         if (BNXT_HAS_DFLT_MAC_SET(bp))
5016                 return 0;
5017
5018         /* Restore the old MAC configured */
5019         rc = bnxt_hwrm_set_mac(bp);
5020         if (rc)
5021                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5022
5023         return rc;
5024 }
5025
5026 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5027 {
5028         if (!BNXT_PF(bp))
5029                 return;
5030
5031         memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5032
5033         if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
5034                 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
5035         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
5036         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
5037         BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
5038         BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
5039 }
5040
5041 struct bnxt *
5042 bnxt_get_bp(uint16_t port)
5043 {
5044         struct bnxt *bp;
5045         struct rte_eth_dev *dev;
5046
5047         if (!rte_eth_dev_is_valid_port(port)) {
5048                 PMD_DRV_LOG(ERR, "Invalid port %d\n", port);
5049                 return NULL;
5050         }
5051
5052         dev = &rte_eth_devices[port];
5053         if (!is_bnxt_supported(dev)) {
5054                 PMD_DRV_LOG(ERR, "Device %d not supported\n", port);
5055                 return NULL;
5056         }
5057
5058         bp = (struct bnxt *)dev->data->dev_private;
5059         if (!BNXT_TRUFLOW_EN(bp)) {
5060                 PMD_DRV_LOG(ERR, "TRUFLOW not enabled\n");
5061                 return NULL;
5062         }
5063
5064         return bp;
5065 }
5066
5067 uint16_t
5068 bnxt_get_svif(uint16_t port_id, bool func_svif,
5069               enum bnxt_ulp_intf_type type)
5070 {
5071         struct rte_eth_dev *eth_dev;
5072         struct bnxt *bp;
5073
5074         eth_dev = &rte_eth_devices[port_id];
5075         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5076                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5077                 if (!vfr)
5078                         return 0;
5079
5080                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5081                         return vfr->svif;
5082
5083                 eth_dev = vfr->parent_dev;
5084         }
5085
5086         bp = eth_dev->data->dev_private;
5087
5088         return func_svif ? bp->func_svif : bp->port_svif;
5089 }
5090
5091 void
5092 bnxt_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type,
5093                    uint8_t *mac, uint8_t *parent_mac)
5094 {
5095         struct rte_eth_dev *eth_dev;
5096         struct bnxt *bp;
5097
5098         if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF &&
5099             type != BNXT_ULP_INTF_TYPE_PF)
5100                 return;
5101
5102         eth_dev = &rte_eth_devices[port];
5103         bp = eth_dev->data->dev_private;
5104         memcpy(mac, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5105
5106         if (type == BNXT_ULP_INTF_TYPE_TRUSTED_VF)
5107                 memcpy(parent_mac, bp->parent->mac_addr, RTE_ETHER_ADDR_LEN);
5108 }
5109
5110 uint16_t
5111 bnxt_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5112 {
5113         struct rte_eth_dev *eth_dev;
5114         struct bnxt *bp;
5115
5116         if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF)
5117                 return 0;
5118
5119         eth_dev = &rte_eth_devices[port];
5120         bp = eth_dev->data->dev_private;
5121
5122         return bp->parent->vnic;
5123 }
5124 uint16_t
5125 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5126 {
5127         struct rte_eth_dev *eth_dev;
5128         struct bnxt_vnic_info *vnic;
5129         struct bnxt *bp;
5130
5131         eth_dev = &rte_eth_devices[port];
5132         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5133                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5134                 if (!vfr)
5135                         return 0;
5136
5137                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5138                         return vfr->dflt_vnic_id;
5139
5140                 eth_dev = vfr->parent_dev;
5141         }
5142
5143         bp = eth_dev->data->dev_private;
5144
5145         vnic = BNXT_GET_DEFAULT_VNIC(bp);
5146
5147         return vnic->fw_vnic_id;
5148 }
5149
5150 uint16_t
5151 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5152 {
5153         struct rte_eth_dev *eth_dev;
5154         struct bnxt *bp;
5155
5156         eth_dev = &rte_eth_devices[port];
5157         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5158                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5159                 if (!vfr)
5160                         return 0;
5161
5162                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5163                         return vfr->fw_fid;
5164
5165                 eth_dev = vfr->parent_dev;
5166         }
5167
5168         bp = eth_dev->data->dev_private;
5169
5170         return bp->fw_fid;
5171 }
5172
5173 enum bnxt_ulp_intf_type
5174 bnxt_get_interface_type(uint16_t port)
5175 {
5176         struct rte_eth_dev *eth_dev;
5177         struct bnxt *bp;
5178
5179         eth_dev = &rte_eth_devices[port];
5180         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5181                 return BNXT_ULP_INTF_TYPE_VF_REP;
5182
5183         bp = eth_dev->data->dev_private;
5184         if (BNXT_PF(bp))
5185                 return BNXT_ULP_INTF_TYPE_PF;
5186         else if (BNXT_VF_IS_TRUSTED(bp))
5187                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5188         else if (BNXT_VF(bp))
5189                 return BNXT_ULP_INTF_TYPE_VF;
5190
5191         return BNXT_ULP_INTF_TYPE_INVALID;
5192 }
5193
5194 uint16_t
5195 bnxt_get_phy_port_id(uint16_t port_id)
5196 {
5197         struct bnxt_representor *vfr;
5198         struct rte_eth_dev *eth_dev;
5199         struct bnxt *bp;
5200
5201         eth_dev = &rte_eth_devices[port_id];
5202         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5203                 vfr = eth_dev->data->dev_private;
5204                 if (!vfr)
5205                         return 0;
5206
5207                 eth_dev = vfr->parent_dev;
5208         }
5209
5210         bp = eth_dev->data->dev_private;
5211
5212         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5213 }
5214
5215 uint16_t
5216 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5217 {
5218         struct rte_eth_dev *eth_dev;
5219         struct bnxt *bp;
5220
5221         eth_dev = &rte_eth_devices[port_id];
5222         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5223                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5224                 if (!vfr)
5225                         return 0;
5226
5227                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5228                         return vfr->fw_fid - 1;
5229
5230                 eth_dev = vfr->parent_dev;
5231         }
5232
5233         bp = eth_dev->data->dev_private;
5234
5235         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5236 }
5237
5238 uint16_t
5239 bnxt_get_vport(uint16_t port_id)
5240 {
5241         return (1 << bnxt_get_phy_port_id(port_id));
5242 }
5243
5244 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5245 {
5246         struct bnxt_error_recovery_info *info = bp->recovery_info;
5247
5248         if (info) {
5249                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5250                         memset(info, 0, sizeof(*info));
5251                 return;
5252         }
5253
5254         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5255                 return;
5256
5257         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5258                            sizeof(*info), 0);
5259         if (!info)
5260                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5261
5262         bp->recovery_info = info;
5263 }
5264
5265 static void bnxt_check_fw_status(struct bnxt *bp)
5266 {
5267         uint32_t fw_status;
5268
5269         if (!(bp->recovery_info &&
5270               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5271                 return;
5272
5273         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5274         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5275                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5276                             fw_status);
5277 }
5278
5279 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5280 {
5281         struct bnxt_error_recovery_info *info = bp->recovery_info;
5282         uint32_t status_loc;
5283         uint32_t sig_ver;
5284
5285         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5286                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5287         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5288                                    BNXT_GRCP_WINDOW_2_BASE +
5289                                    offsetof(struct hcomm_status,
5290                                             sig_ver)));
5291         /* If the signature is absent, then FW does not support this feature */
5292         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5293             HCOMM_STATUS_SIGNATURE_VAL)
5294                 return 0;
5295
5296         if (!info) {
5297                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5298                                    sizeof(*info), 0);
5299                 if (!info)
5300                         return -ENOMEM;
5301                 bp->recovery_info = info;
5302         } else {
5303                 memset(info, 0, sizeof(*info));
5304         }
5305
5306         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5307                                       BNXT_GRCP_WINDOW_2_BASE +
5308                                       offsetof(struct hcomm_status,
5309                                                fw_status_loc)));
5310
5311         /* Only pre-map the FW health status GRC register */
5312         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5313                 return 0;
5314
5315         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5316         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5317                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5318
5319         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5320                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5321
5322         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5323
5324         return 0;
5325 }
5326
5327 /* This function gets the FW version along with the
5328  * capabilities(MAX and current) of the function, vnic,
5329  * error recovery, phy and other chip related info
5330  */
5331 static int bnxt_get_config(struct bnxt *bp)
5332 {
5333         uint16_t mtu;
5334         int rc = 0;
5335
5336         bp->fw_cap = 0;
5337
5338         rc = bnxt_map_hcomm_fw_status_reg(bp);
5339         if (rc)
5340                 return rc;
5341
5342         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5343         if (rc) {
5344                 bnxt_check_fw_status(bp);
5345                 return rc;
5346         }
5347
5348         rc = bnxt_hwrm_func_reset(bp);
5349         if (rc)
5350                 return -EIO;
5351
5352         rc = bnxt_hwrm_vnic_qcaps(bp);
5353         if (rc)
5354                 return rc;
5355
5356         rc = bnxt_hwrm_queue_qportcfg(bp);
5357         if (rc)
5358                 return rc;
5359
5360         /* Get the MAX capabilities for this function.
5361          * This function also allocates context memory for TQM rings and
5362          * informs the firmware about this allocated backing store memory.
5363          */
5364         rc = bnxt_hwrm_func_qcaps(bp);
5365         if (rc)
5366                 return rc;
5367
5368         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5369         if (rc)
5370                 return rc;
5371
5372         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5373         if (rc)
5374                 return rc;
5375
5376         bnxt_hwrm_port_mac_qcfg(bp);
5377
5378         bnxt_hwrm_parent_pf_qcfg(bp);
5379
5380         bnxt_hwrm_port_phy_qcaps(bp);
5381
5382         bnxt_alloc_error_recovery_info(bp);
5383         /* Get the adapter error recovery support info */
5384         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5385         if (rc)
5386                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5387
5388         bnxt_hwrm_port_led_qcaps(bp);
5389
5390         return 0;
5391 }
5392
5393 static int
5394 bnxt_init_locks(struct bnxt *bp)
5395 {
5396         int err;
5397
5398         err = pthread_mutex_init(&bp->flow_lock, NULL);
5399         if (err) {
5400                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5401                 return err;
5402         }
5403
5404         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5405         if (err) {
5406                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5407                 return err;
5408         }
5409
5410         err = pthread_mutex_init(&bp->health_check_lock, NULL);
5411         if (err) {
5412                 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5413                 return err;
5414         }
5415
5416         err = pthread_mutex_init(&bp->err_recovery_lock, NULL);
5417         if (err)
5418                 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n");
5419
5420         return err;
5421 }
5422
5423 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5424 {
5425         int rc = 0;
5426
5427         rc = bnxt_get_config(bp);
5428         if (rc)
5429                 return rc;
5430
5431         if (!reconfig_dev) {
5432                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5433                 if (rc)
5434                         return rc;
5435         } else {
5436                 rc = bnxt_restore_dflt_mac(bp);
5437                 if (rc)
5438                         return rc;
5439         }
5440
5441         bnxt_config_vf_req_fwd(bp);
5442
5443         rc = bnxt_hwrm_func_driver_register(bp);
5444         if (rc) {
5445                 PMD_DRV_LOG(ERR, "Failed to register driver");
5446                 return -EBUSY;
5447         }
5448
5449         if (BNXT_PF(bp)) {
5450                 if (bp->pdev->max_vfs) {
5451                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5452                         if (rc) {
5453                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5454                                 return rc;
5455                         }
5456                 } else {
5457                         rc = bnxt_hwrm_allocate_pf_only(bp);
5458                         if (rc) {
5459                                 PMD_DRV_LOG(ERR,
5460                                             "Failed to allocate PF resources");
5461                                 return rc;
5462                         }
5463                 }
5464         }
5465
5466         rc = bnxt_alloc_mem(bp, reconfig_dev);
5467         if (rc)
5468                 return rc;
5469
5470         rc = bnxt_setup_int(bp);
5471         if (rc)
5472                 return rc;
5473
5474         rc = bnxt_request_int(bp);
5475         if (rc)
5476                 return rc;
5477
5478         rc = bnxt_init_ctx_mem(bp);
5479         if (rc) {
5480                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5481                 return rc;
5482         }
5483
5484         return 0;
5485 }
5486
5487 static int
5488 bnxt_parse_devarg_accum_stats(__rte_unused const char *key,
5489                               const char *value, void *opaque_arg)
5490 {
5491         struct bnxt *bp = opaque_arg;
5492         unsigned long accum_stats;
5493         char *end = NULL;
5494
5495         if (!value || !opaque_arg) {
5496                 PMD_DRV_LOG(ERR,
5497                             "Invalid parameter passed to accum-stats devargs.\n");
5498                 return -EINVAL;
5499         }
5500
5501         accum_stats = strtoul(value, &end, 10);
5502         if (end == NULL || *end != '\0' ||
5503             (accum_stats == ULONG_MAX && errno == ERANGE)) {
5504                 PMD_DRV_LOG(ERR,
5505                             "Invalid parameter passed to accum-stats devargs.\n");
5506                 return -EINVAL;
5507         }
5508
5509         if (BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats)) {
5510                 PMD_DRV_LOG(ERR,
5511                             "Invalid value passed to accum-stats devargs.\n");
5512                 return -EINVAL;
5513         }
5514
5515         if (accum_stats) {
5516                 bp->flags2 |= BNXT_FLAGS2_ACCUM_STATS_EN;
5517                 PMD_DRV_LOG(INFO, "Host-based accum-stats feature enabled.\n");
5518         } else {
5519                 bp->flags2 &= ~BNXT_FLAGS2_ACCUM_STATS_EN;
5520                 PMD_DRV_LOG(INFO, "Host-based accum-stats feature disabled.\n");
5521         }
5522
5523         return 0;
5524 }
5525
5526 static int
5527 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5528                              const char *value, void *opaque_arg)
5529 {
5530         struct bnxt *bp = opaque_arg;
5531         unsigned long flow_xstat;
5532         char *end = NULL;
5533
5534         if (!value || !opaque_arg) {
5535                 PMD_DRV_LOG(ERR,
5536                             "Invalid parameter passed to flow_xstat devarg.\n");
5537                 return -EINVAL;
5538         }
5539
5540         flow_xstat = strtoul(value, &end, 10);
5541         if (end == NULL || *end != '\0' ||
5542             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5543                 PMD_DRV_LOG(ERR,
5544                             "Invalid parameter passed to flow_xstat devarg.\n");
5545                 return -EINVAL;
5546         }
5547
5548         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5549                 PMD_DRV_LOG(ERR,
5550                             "Invalid value passed to flow_xstat devarg.\n");
5551                 return -EINVAL;
5552         }
5553
5554         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5555         if (BNXT_FLOW_XSTATS_EN(bp))
5556                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5557
5558         return 0;
5559 }
5560
5561 static int
5562 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5563                                         const char *value, void *opaque_arg)
5564 {
5565         struct bnxt *bp = opaque_arg;
5566         unsigned long max_num_kflows;
5567         char *end = NULL;
5568
5569         if (!value || !opaque_arg) {
5570                 PMD_DRV_LOG(ERR,
5571                         "Invalid parameter passed to max_num_kflows devarg.\n");
5572                 return -EINVAL;
5573         }
5574
5575         max_num_kflows = strtoul(value, &end, 10);
5576         if (end == NULL || *end != '\0' ||
5577                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5578                 PMD_DRV_LOG(ERR,
5579                         "Invalid parameter passed to max_num_kflows devarg.\n");
5580                 return -EINVAL;
5581         }
5582
5583         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5584                 PMD_DRV_LOG(ERR,
5585                         "Invalid value passed to max_num_kflows devarg.\n");
5586                 return -EINVAL;
5587         }
5588
5589         bp->max_num_kflows = max_num_kflows;
5590         if (bp->max_num_kflows)
5591                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5592                                 max_num_kflows);
5593
5594         return 0;
5595 }
5596
5597 static int
5598 bnxt_parse_devarg_app_id(__rte_unused const char *key,
5599                                  const char *value, void *opaque_arg)
5600 {
5601         struct bnxt *bp = opaque_arg;
5602         unsigned long app_id;
5603         char *end = NULL;
5604
5605         if (!value || !opaque_arg) {
5606                 PMD_DRV_LOG(ERR,
5607                             "Invalid parameter passed to app-id "
5608                             "devargs.\n");
5609                 return -EINVAL;
5610         }
5611
5612         app_id = strtoul(value, &end, 10);
5613         if (end == NULL || *end != '\0' ||
5614             (app_id == ULONG_MAX && errno == ERANGE)) {
5615                 PMD_DRV_LOG(ERR,
5616                             "Invalid parameter passed to app_id "
5617                             "devargs.\n");
5618                 return -EINVAL;
5619         }
5620
5621         if (BNXT_DEVARG_APP_ID_INVALID(app_id)) {
5622                 PMD_DRV_LOG(ERR, "Invalid app-id(%d) devargs.\n",
5623                             (uint16_t)app_id);
5624                 return -EINVAL;
5625         }
5626
5627         bp->app_id = app_id;
5628         PMD_DRV_LOG(INFO, "app-id=%d feature enabled.\n", (uint16_t)app_id);
5629
5630         return 0;
5631 }
5632
5633 static int
5634 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5635                             const char *value, void *opaque_arg)
5636 {
5637         struct bnxt_representor *vfr_bp = opaque_arg;
5638         unsigned long rep_is_pf;
5639         char *end = NULL;
5640
5641         if (!value || !opaque_arg) {
5642                 PMD_DRV_LOG(ERR,
5643                             "Invalid parameter passed to rep_is_pf devargs.\n");
5644                 return -EINVAL;
5645         }
5646
5647         rep_is_pf = strtoul(value, &end, 10);
5648         if (end == NULL || *end != '\0' ||
5649             (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5650                 PMD_DRV_LOG(ERR,
5651                             "Invalid parameter passed to rep_is_pf devargs.\n");
5652                 return -EINVAL;
5653         }
5654
5655         if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5656                 PMD_DRV_LOG(ERR,
5657                             "Invalid value passed to rep_is_pf devargs.\n");
5658                 return -EINVAL;
5659         }
5660
5661         vfr_bp->flags |= rep_is_pf;
5662         if (BNXT_REP_PF(vfr_bp))
5663                 PMD_DRV_LOG(INFO, "PF representor\n");
5664         else
5665                 PMD_DRV_LOG(INFO, "VF representor\n");
5666
5667         return 0;
5668 }
5669
5670 static int
5671 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5672                                const char *value, void *opaque_arg)
5673 {
5674         struct bnxt_representor *vfr_bp = opaque_arg;
5675         unsigned long rep_based_pf;
5676         char *end = NULL;
5677
5678         if (!value || !opaque_arg) {
5679                 PMD_DRV_LOG(ERR,
5680                             "Invalid parameter passed to rep_based_pf "
5681                             "devargs.\n");
5682                 return -EINVAL;
5683         }
5684
5685         rep_based_pf = strtoul(value, &end, 10);
5686         if (end == NULL || *end != '\0' ||
5687             (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5688                 PMD_DRV_LOG(ERR,
5689                             "Invalid parameter passed to rep_based_pf "
5690                             "devargs.\n");
5691                 return -EINVAL;
5692         }
5693
5694         if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5695                 PMD_DRV_LOG(ERR,
5696                             "Invalid value passed to rep_based_pf devargs.\n");
5697                 return -EINVAL;
5698         }
5699
5700         vfr_bp->rep_based_pf = rep_based_pf;
5701         vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
5702
5703         PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5704
5705         return 0;
5706 }
5707
5708 static int
5709 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5710                             const char *value, void *opaque_arg)
5711 {
5712         struct bnxt_representor *vfr_bp = opaque_arg;
5713         unsigned long rep_q_r2f;
5714         char *end = NULL;
5715
5716         if (!value || !opaque_arg) {
5717                 PMD_DRV_LOG(ERR,
5718                             "Invalid parameter passed to rep_q_r2f "
5719                             "devargs.\n");
5720                 return -EINVAL;
5721         }
5722
5723         rep_q_r2f = strtoul(value, &end, 10);
5724         if (end == NULL || *end != '\0' ||
5725             (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5726                 PMD_DRV_LOG(ERR,
5727                             "Invalid parameter passed to rep_q_r2f "
5728                             "devargs.\n");
5729                 return -EINVAL;
5730         }
5731
5732         if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5733                 PMD_DRV_LOG(ERR,
5734                             "Invalid value passed to rep_q_r2f devargs.\n");
5735                 return -EINVAL;
5736         }
5737
5738         vfr_bp->rep_q_r2f = rep_q_r2f;
5739         vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5740         PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5741
5742         return 0;
5743 }
5744
5745 static int
5746 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5747                             const char *value, void *opaque_arg)
5748 {
5749         struct bnxt_representor *vfr_bp = opaque_arg;
5750         unsigned long rep_q_f2r;
5751         char *end = NULL;
5752
5753         if (!value || !opaque_arg) {
5754                 PMD_DRV_LOG(ERR,
5755                             "Invalid parameter passed to rep_q_f2r "
5756                             "devargs.\n");
5757                 return -EINVAL;
5758         }
5759
5760         rep_q_f2r = strtoul(value, &end, 10);
5761         if (end == NULL || *end != '\0' ||
5762             (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5763                 PMD_DRV_LOG(ERR,
5764                             "Invalid parameter passed to rep_q_f2r "
5765                             "devargs.\n");
5766                 return -EINVAL;
5767         }
5768
5769         if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5770                 PMD_DRV_LOG(ERR,
5771                             "Invalid value passed to rep_q_f2r devargs.\n");
5772                 return -EINVAL;
5773         }
5774
5775         vfr_bp->rep_q_f2r = rep_q_f2r;
5776         vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5777         PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5778
5779         return 0;
5780 }
5781
5782 static int
5783 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5784                              const char *value, void *opaque_arg)
5785 {
5786         struct bnxt_representor *vfr_bp = opaque_arg;
5787         unsigned long rep_fc_r2f;
5788         char *end = NULL;
5789
5790         if (!value || !opaque_arg) {
5791                 PMD_DRV_LOG(ERR,
5792                             "Invalid parameter passed to rep_fc_r2f "
5793                             "devargs.\n");
5794                 return -EINVAL;
5795         }
5796
5797         rep_fc_r2f = strtoul(value, &end, 10);
5798         if (end == NULL || *end != '\0' ||
5799             (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5800                 PMD_DRV_LOG(ERR,
5801                             "Invalid parameter passed to rep_fc_r2f "
5802                             "devargs.\n");
5803                 return -EINVAL;
5804         }
5805
5806         if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5807                 PMD_DRV_LOG(ERR,
5808                             "Invalid value passed to rep_fc_r2f devargs.\n");
5809                 return -EINVAL;
5810         }
5811
5812         vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5813         vfr_bp->rep_fc_r2f = rep_fc_r2f;
5814         PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5815
5816         return 0;
5817 }
5818
5819 static int
5820 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5821                              const char *value, void *opaque_arg)
5822 {
5823         struct bnxt_representor *vfr_bp = opaque_arg;
5824         unsigned long rep_fc_f2r;
5825         char *end = NULL;
5826
5827         if (!value || !opaque_arg) {
5828                 PMD_DRV_LOG(ERR,
5829                             "Invalid parameter passed to rep_fc_f2r "
5830                             "devargs.\n");
5831                 return -EINVAL;
5832         }
5833
5834         rep_fc_f2r = strtoul(value, &end, 10);
5835         if (end == NULL || *end != '\0' ||
5836             (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5837                 PMD_DRV_LOG(ERR,
5838                             "Invalid parameter passed to rep_fc_f2r "
5839                             "devargs.\n");
5840                 return -EINVAL;
5841         }
5842
5843         if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5844                 PMD_DRV_LOG(ERR,
5845                             "Invalid value passed to rep_fc_f2r devargs.\n");
5846                 return -EINVAL;
5847         }
5848
5849         vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5850         vfr_bp->rep_fc_f2r = rep_fc_f2r;
5851         PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5852
5853         return 0;
5854 }
5855
5856 static int
5857 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5858 {
5859         struct rte_kvargs *kvlist;
5860         int ret;
5861
5862         if (devargs == NULL)
5863                 return 0;
5864
5865         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5866         if (kvlist == NULL)
5867                 return -EINVAL;
5868
5869         /*
5870          * Handler for "flow_xstat" devarg.
5871          * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5872          */
5873         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5874                                  bnxt_parse_devarg_flow_xstat, bp);
5875         if (ret)
5876                 goto err;
5877
5878         /*
5879          * Handler for "accum-stats" devarg.
5880          * Invoked as for ex: "-a 0000:00:0d.0,accum-stats=1"
5881          */
5882         rte_kvargs_process(kvlist, BNXT_DEVARG_ACCUM_STATS,
5883                            bnxt_parse_devarg_accum_stats, bp);
5884         /*
5885          * Handler for "max_num_kflows" devarg.
5886          * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5887          */
5888         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5889                                  bnxt_parse_devarg_max_num_kflows, bp);
5890         if (ret)
5891                 goto err;
5892
5893 err:
5894         /*
5895          * Handler for "app-id" devarg.
5896          * Invoked as for ex: "-a 000:00:0d.0,app-id=1"
5897          */
5898         rte_kvargs_process(kvlist, BNXT_DEVARG_APP_ID,
5899                            bnxt_parse_devarg_app_id, bp);
5900
5901         rte_kvargs_free(kvlist);
5902         return ret;
5903 }
5904
5905 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5906 {
5907         int rc = 0;
5908
5909         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5910                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5911                 if (rc)
5912                         PMD_DRV_LOG(ERR,
5913                                     "Failed to alloc switch domain: %d\n", rc);
5914                 else
5915                         PMD_DRV_LOG(INFO,
5916                                     "Switch domain allocated %d\n",
5917                                     bp->switch_domain_id);
5918         }
5919
5920         return rc;
5921 }
5922
5923 /* Allocate and initialize various fields in bnxt struct that
5924  * need to be allocated/destroyed only once in the lifetime of the driver
5925  */
5926 static int bnxt_drv_init(struct rte_eth_dev *eth_dev)
5927 {
5928         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5929         struct bnxt *bp = eth_dev->data->dev_private;
5930         int rc = 0;
5931
5932         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5933
5934         if (bnxt_vf_pciid(pci_dev->id.device_id))
5935                 bp->flags |= BNXT_FLAG_VF;
5936
5937         if (bnxt_p5_device(pci_dev->id.device_id))
5938                 bp->flags |= BNXT_FLAG_CHIP_P5;
5939
5940         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5941             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5942             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5943             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5944                 bp->flags |= BNXT_FLAG_STINGRAY;
5945
5946         if (BNXT_TRUFLOW_EN(bp)) {
5947                 /* extra mbuf field is required to store CFA code from mark */
5948                 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5949                         .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5950                         .size = sizeof(bnxt_cfa_code_dynfield_t),
5951                         .align = __alignof__(bnxt_cfa_code_dynfield_t),
5952                 };
5953                 bnxt_cfa_code_dynfield_offset =
5954                         rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5955                 if (bnxt_cfa_code_dynfield_offset < 0) {
5956                         PMD_DRV_LOG(ERR,
5957                             "Failed to register mbuf field for TruFlow mark\n");
5958                         return -rte_errno;
5959                 }
5960         }
5961
5962         rc = bnxt_map_pci_bars(eth_dev);
5963         if (rc) {
5964                 PMD_DRV_LOG(ERR,
5965                             "Failed to initialize board rc: %x\n", rc);
5966                 return rc;
5967         }
5968
5969         rc = bnxt_alloc_pf_info(bp);
5970         if (rc)
5971                 return rc;
5972
5973         rc = bnxt_alloc_link_info(bp);
5974         if (rc)
5975                 return rc;
5976
5977         rc = bnxt_alloc_parent_info(bp);
5978         if (rc)
5979                 return rc;
5980
5981         rc = bnxt_alloc_hwrm_resources(bp);
5982         if (rc) {
5983                 PMD_DRV_LOG(ERR,
5984                             "Failed to allocate response buffer rc: %x\n", rc);
5985                 return rc;
5986         }
5987         rc = bnxt_alloc_leds_info(bp);
5988         if (rc)
5989                 return rc;
5990
5991         rc = bnxt_alloc_cos_queues(bp);
5992         if (rc)
5993                 return rc;
5994
5995         rc = bnxt_init_locks(bp);
5996         if (rc)
5997                 return rc;
5998
5999         rc = bnxt_alloc_switch_domain(bp);
6000         if (rc)
6001                 return rc;
6002
6003         return rc;
6004 }
6005
6006 static int
6007 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
6008 {
6009         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
6010         static int version_printed;
6011         struct bnxt *bp;
6012         int rc;
6013
6014         if (version_printed++ == 0)
6015                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
6016
6017         eth_dev->dev_ops = &bnxt_dev_ops;
6018         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
6019         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
6020         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
6021         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
6022         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
6023
6024         /*
6025          * For secondary processes, we don't initialise any further
6026          * as primary has already done this work.
6027          */
6028         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6029                 return 0;
6030
6031         rte_eth_copy_pci_info(eth_dev, pci_dev);
6032         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
6033
6034         bp = eth_dev->data->dev_private;
6035
6036         /* Parse dev arguments passed on when starting the DPDK application. */
6037         rc = bnxt_parse_dev_args(bp, pci_dev->device.devargs);
6038         if (rc)
6039                 goto error_free;
6040
6041         rc = bnxt_drv_init(eth_dev);
6042         if (rc)
6043                 goto error_free;
6044
6045         rc = bnxt_init_resources(bp, false);
6046         if (rc)
6047                 goto error_free;
6048
6049         rc = bnxt_alloc_stats_mem(bp);
6050         if (rc)
6051                 goto error_free;
6052
6053         PMD_DRV_LOG(INFO,
6054                     "Found %s device at mem %" PRIX64 ", node addr %pM\n",
6055                     DRV_MODULE_NAME,
6056                     pci_dev->mem_resource[0].phys_addr,
6057                     pci_dev->mem_resource[0].addr);
6058
6059         return 0;
6060
6061 error_free:
6062         bnxt_dev_uninit(eth_dev);
6063         return rc;
6064 }
6065
6066
6067 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
6068 {
6069         if (!ctx)
6070                 return;
6071
6072         if (ctx->va)
6073                 rte_free(ctx->va);
6074
6075         ctx->va = NULL;
6076         ctx->dma = RTE_BAD_IOVA;
6077         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
6078 }
6079
6080 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
6081 {
6082         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
6083                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6084                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
6085                                   bp->flow_stat->max_fc,
6086                                   false);
6087
6088         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
6089                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6090                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
6091                                   bp->flow_stat->max_fc,
6092                                   false);
6093
6094         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6095                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
6096         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6097
6098         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6099                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
6100         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6101
6102         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6103                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
6104         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6105
6106         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6107                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
6108         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6109 }
6110
6111 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
6112 {
6113         bnxt_unregister_fc_ctx_mem(bp);
6114
6115         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
6116         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
6117         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
6118         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
6119 }
6120
6121 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
6122 {
6123         if (BNXT_FLOW_XSTATS_EN(bp))
6124                 bnxt_uninit_fc_ctx_mem(bp);
6125 }
6126
6127 static void
6128 bnxt_free_error_recovery_info(struct bnxt *bp)
6129 {
6130         rte_free(bp->recovery_info);
6131         bp->recovery_info = NULL;
6132         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
6133 }
6134
6135 static int
6136 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
6137 {
6138         int rc;
6139
6140         bnxt_free_int(bp);
6141         bnxt_free_mem(bp, reconfig_dev);
6142
6143         bnxt_hwrm_func_buf_unrgtr(bp);
6144         if (bp->pf != NULL) {
6145                 rte_free(bp->pf->vf_req_buf);
6146                 bp->pf->vf_req_buf = NULL;
6147         }
6148
6149         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
6150         bp->flags &= ~BNXT_FLAG_REGISTERED;
6151         bnxt_free_ctx_mem(bp);
6152         if (!reconfig_dev) {
6153                 bnxt_free_hwrm_resources(bp);
6154                 bnxt_free_error_recovery_info(bp);
6155         }
6156
6157         bnxt_uninit_ctx_mem(bp);
6158
6159         bnxt_free_flow_stats_info(bp);
6160         if (bp->rep_info != NULL)
6161                 bnxt_free_switch_domain(bp);
6162         bnxt_free_rep_info(bp);
6163         rte_free(bp->ptp_cfg);
6164         bp->ptp_cfg = NULL;
6165         return rc;
6166 }
6167
6168 static int
6169 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
6170 {
6171         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6172                 return -EPERM;
6173
6174         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
6175
6176         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
6177                 bnxt_dev_close_op(eth_dev);
6178
6179         return 0;
6180 }
6181
6182 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
6183 {
6184         struct bnxt *bp = eth_dev->data->dev_private;
6185         struct rte_eth_dev *vf_rep_eth_dev;
6186         int ret = 0, i;
6187
6188         if (!bp)
6189                 return -EINVAL;
6190
6191         for (i = 0; i < bp->num_reps; i++) {
6192                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
6193                 if (!vf_rep_eth_dev)
6194                         continue;
6195                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
6196                             vf_rep_eth_dev->data->port_id);
6197                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
6198         }
6199         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
6200                     eth_dev->data->port_id);
6201         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
6202
6203         return ret;
6204 }
6205
6206 static void bnxt_free_rep_info(struct bnxt *bp)
6207 {
6208         rte_free(bp->rep_info);
6209         bp->rep_info = NULL;
6210         rte_free(bp->cfa_code_map);
6211         bp->cfa_code_map = NULL;
6212 }
6213
6214 static int bnxt_init_rep_info(struct bnxt *bp)
6215 {
6216         int i = 0, rc;
6217
6218         if (bp->rep_info)
6219                 return 0;
6220
6221         bp->rep_info = rte_zmalloc("bnxt_rep_info",
6222                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
6223                                    0);
6224         if (!bp->rep_info) {
6225                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
6226                 return -ENOMEM;
6227         }
6228         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
6229                                        sizeof(*bp->cfa_code_map) *
6230                                        BNXT_MAX_CFA_CODE, 0);
6231         if (!bp->cfa_code_map) {
6232                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
6233                 bnxt_free_rep_info(bp);
6234                 return -ENOMEM;
6235         }
6236
6237         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
6238                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
6239
6240         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
6241         if (rc) {
6242                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
6243                 bnxt_free_rep_info(bp);
6244                 return rc;
6245         }
6246
6247         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
6248         if (rc) {
6249                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
6250                 bnxt_free_rep_info(bp);
6251                 return rc;
6252         }
6253
6254         return rc;
6255 }
6256
6257 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
6258                                struct rte_eth_devargs *eth_da,
6259                                struct rte_eth_dev *backing_eth_dev,
6260                                const char *dev_args)
6261 {
6262         struct rte_eth_dev *vf_rep_eth_dev;
6263         char name[RTE_ETH_NAME_MAX_LEN];
6264         struct bnxt *backing_bp;
6265         uint16_t num_rep;
6266         int i, ret = 0;
6267         struct rte_kvargs *kvlist = NULL;
6268
6269         if (eth_da->type == RTE_ETH_REPRESENTOR_NONE)
6270                 return 0;
6271         if (eth_da->type != RTE_ETH_REPRESENTOR_VF) {
6272                 PMD_DRV_LOG(ERR, "unsupported representor type %d\n",
6273                             eth_da->type);
6274                 return -ENOTSUP;
6275         }
6276         num_rep = eth_da->nb_representor_ports;
6277         if (num_rep > BNXT_MAX_VF_REPS) {
6278                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
6279                             num_rep, BNXT_MAX_VF_REPS);
6280                 return -EINVAL;
6281         }
6282
6283         if (num_rep >= RTE_MAX_ETHPORTS) {
6284                 PMD_DRV_LOG(ERR,
6285                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6286                             num_rep, RTE_MAX_ETHPORTS);
6287                 return -EINVAL;
6288         }
6289
6290         backing_bp = backing_eth_dev->data->dev_private;
6291
6292         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6293                 PMD_DRV_LOG(ERR,
6294                             "Not a PF or trusted VF. No Representor support\n");
6295                 /* Returning an error is not an option.
6296                  * Applications are not handling this correctly
6297                  */
6298                 return 0;
6299         }
6300
6301         if (bnxt_init_rep_info(backing_bp))
6302                 return 0;
6303
6304         for (i = 0; i < num_rep; i++) {
6305                 struct bnxt_representor representor = {
6306                         .vf_id = eth_da->representor_ports[i],
6307                         .switch_domain_id = backing_bp->switch_domain_id,
6308                         .parent_dev = backing_eth_dev
6309                 };
6310
6311                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6312                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6313                                     representor.vf_id, BNXT_MAX_VF_REPS);
6314                         continue;
6315                 }
6316
6317                 /* representor port net_bdf_port */
6318                 snprintf(name, sizeof(name), "net_%s_representor_%d",
6319                          pci_dev->device.name, eth_da->representor_ports[i]);
6320
6321                 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
6322                 if (kvlist) {
6323                         /*
6324                          * Handler for "rep_is_pf" devarg.
6325                          * Invoked as for ex: "-a 000:00:0d.0,
6326                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6327                          */
6328                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
6329                                                  bnxt_parse_devarg_rep_is_pf,
6330                                                  (void *)&representor);
6331                         if (ret) {
6332                                 ret = -EINVAL;
6333                                 goto err;
6334                         }
6335                         /*
6336                          * Handler for "rep_based_pf" devarg.
6337                          * Invoked as for ex: "-a 000:00:0d.0,
6338                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6339                          */
6340                         ret = rte_kvargs_process(kvlist,
6341                                                  BNXT_DEVARG_REP_BASED_PF,
6342                                                  bnxt_parse_devarg_rep_based_pf,
6343                                                  (void *)&representor);
6344                         if (ret) {
6345                                 ret = -EINVAL;
6346                                 goto err;
6347                         }
6348                         /*
6349                          * Handler for "rep_based_pf" devarg.
6350                          * Invoked as for ex: "-a 000:00:0d.0,
6351                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6352                          */
6353                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
6354                                                  bnxt_parse_devarg_rep_q_r2f,
6355                                                  (void *)&representor);
6356                         if (ret) {
6357                                 ret = -EINVAL;
6358                                 goto err;
6359                         }
6360                         /*
6361                          * Handler for "rep_based_pf" devarg.
6362                          * Invoked as for ex: "-a 000:00:0d.0,
6363                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6364                          */
6365                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
6366                                                  bnxt_parse_devarg_rep_q_f2r,
6367                                                  (void *)&representor);
6368                         if (ret) {
6369                                 ret = -EINVAL;
6370                                 goto err;
6371                         }
6372                         /*
6373                          * Handler for "rep_based_pf" devarg.
6374                          * Invoked as for ex: "-a 000:00:0d.0,
6375                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6376                          */
6377                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
6378                                                  bnxt_parse_devarg_rep_fc_r2f,
6379                                                  (void *)&representor);
6380                         if (ret) {
6381                                 ret = -EINVAL;
6382                                 goto err;
6383                         }
6384                         /*
6385                          * Handler for "rep_based_pf" devarg.
6386                          * Invoked as for ex: "-a 000:00:0d.0,
6387                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6388                          */
6389                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
6390                                                  bnxt_parse_devarg_rep_fc_f2r,
6391                                                  (void *)&representor);
6392                         if (ret) {
6393                                 ret = -EINVAL;
6394                                 goto err;
6395                         }
6396                 }
6397
6398                 ret = rte_eth_dev_create(&pci_dev->device, name,
6399                                          sizeof(struct bnxt_representor),
6400                                          NULL, NULL,
6401                                          bnxt_representor_init,
6402                                          &representor);
6403                 if (ret) {
6404                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6405                                     "representor %s.", name);
6406                         goto err;
6407                 }
6408
6409                 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6410                 if (!vf_rep_eth_dev) {
6411                         PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6412                                     " for VF-Rep: %s.", name);
6413                         ret = -ENODEV;
6414                         goto err;
6415                 }
6416
6417                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6418                             backing_eth_dev->data->port_id);
6419                 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6420                                                          vf_rep_eth_dev;
6421                 backing_bp->num_reps++;
6422
6423         }
6424
6425         rte_kvargs_free(kvlist);
6426         return 0;
6427
6428 err:
6429         /* If num_rep > 1, then rollback already created
6430          * ports, since we'll be failing the probe anyway
6431          */
6432         if (num_rep > 1)
6433                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6434         rte_errno = -ret;
6435         rte_kvargs_free(kvlist);
6436
6437         return ret;
6438 }
6439
6440 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6441                           struct rte_pci_device *pci_dev)
6442 {
6443         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6444         struct rte_eth_dev *backing_eth_dev;
6445         uint16_t num_rep;
6446         int ret = 0;
6447
6448         if (pci_dev->device.devargs) {
6449                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6450                                             &eth_da);
6451                 if (ret)
6452                         return ret;
6453         }
6454
6455         num_rep = eth_da.nb_representor_ports;
6456         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6457                     num_rep);
6458
6459         /* We could come here after first level of probe is already invoked
6460          * as part of an application bringup(OVS-DPDK vswitchd), so first check
6461          * for already allocated eth_dev for the backing device (PF/Trusted VF)
6462          */
6463         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6464         if (backing_eth_dev == NULL) {
6465                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6466                                          sizeof(struct bnxt),
6467                                          eth_dev_pci_specific_init, pci_dev,
6468                                          bnxt_dev_init, NULL);
6469
6470                 if (ret || !num_rep)
6471                         return ret;
6472
6473                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6474         }
6475         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6476                     backing_eth_dev->data->port_id);
6477
6478         if (!num_rep)
6479                 return ret;
6480
6481         /* probe representor ports now */
6482         ret = bnxt_rep_port_probe(pci_dev, &eth_da, backing_eth_dev,
6483                                   pci_dev->device.devargs->args);
6484
6485         return ret;
6486 }
6487
6488 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6489 {
6490         struct rte_eth_dev *eth_dev;
6491
6492         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6493         if (!eth_dev)
6494                 return 0; /* Invoked typically only by OVS-DPDK, by the
6495                            * time it comes here the eth_dev is already
6496                            * deleted by rte_eth_dev_close(), so returning
6497                            * +ve value will at least help in proper cleanup
6498                            */
6499
6500         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6501         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6502                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6503                         return rte_eth_dev_destroy(eth_dev,
6504                                                    bnxt_representor_uninit);
6505                 else
6506                         return rte_eth_dev_destroy(eth_dev,
6507                                                    bnxt_dev_uninit);
6508         } else {
6509                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6510         }
6511 }
6512
6513 static struct rte_pci_driver bnxt_rte_pmd = {
6514         .id_table = bnxt_pci_id_map,
6515         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6516                         RTE_PCI_DRV_INTR_RMV |
6517                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6518                                                   * and OVS-DPDK
6519                                                   */
6520         .probe = bnxt_pci_probe,
6521         .remove = bnxt_pci_remove,
6522 };
6523
6524 static bool
6525 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6526 {
6527         if (strcmp(dev->device->driver->name, drv->driver.name))
6528                 return false;
6529
6530         return true;
6531 }
6532
6533 bool is_bnxt_supported(struct rte_eth_dev *dev)
6534 {
6535         return is_device_supported(dev, &bnxt_rte_pmd);
6536 }
6537
6538 RTE_LOG_REGISTER_SUFFIX(bnxt_logtype_driver, driver, NOTICE);
6539 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6540 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6541 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");