1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
15 #include <rte_kvargs.h>
19 #include "bnxt_filter.h"
20 #include "bnxt_hwrm.h"
22 #include "bnxt_reps.h"
23 #include "bnxt_ring.h"
26 #include "bnxt_stats.h"
29 #include "bnxt_vnic.h"
30 #include "hsi_struct_def_dpdk.h"
31 #include "bnxt_nvm_defs.h"
32 #include "bnxt_tf_common.h"
33 #include "ulp_flow_db.h"
34 #include "rte_pmd_bnxt.h"
36 #define DRV_MODULE_NAME "bnxt"
37 static const char bnxt_version[] =
38 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
41 * The set of PCI devices this driver supports
43 static const struct rte_pci_id bnxt_pci_id_map[] = {
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
45 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
47 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
97 { .vendor_id = 0, /* sentinel */ },
100 #define BNXT_DEVARG_TRUFLOW "host-based-truflow"
101 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat"
102 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows"
103 #define BNXT_DEVARG_REPRESENTOR "representor"
104 #define BNXT_DEVARG_REP_BASED_PF "rep-based-pf"
105 #define BNXT_DEVARG_REP_IS_PF "rep-is-pf"
106 #define BNXT_DEVARG_REP_Q_R2F "rep-q-r2f"
107 #define BNXT_DEVARG_REP_Q_F2R "rep-q-f2r"
108 #define BNXT_DEVARG_REP_FC_R2F "rep-fc-r2f"
109 #define BNXT_DEVARG_REP_FC_F2R "rep-fc-f2r"
111 static const char *const bnxt_dev_args[] = {
112 BNXT_DEVARG_REPRESENTOR,
114 BNXT_DEVARG_FLOW_XSTAT,
115 BNXT_DEVARG_MAX_NUM_KFLOWS,
116 BNXT_DEVARG_REP_BASED_PF,
117 BNXT_DEVARG_REP_IS_PF,
118 BNXT_DEVARG_REP_Q_R2F,
119 BNXT_DEVARG_REP_Q_F2R,
120 BNXT_DEVARG_REP_FC_R2F,
121 BNXT_DEVARG_REP_FC_F2R,
126 * truflow == false to disable the feature
127 * truflow == true to enable the feature
129 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1)
132 * flow_xstat == false to disable the feature
133 * flow_xstat == true to enable the feature
135 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1)
138 * rep_is_pf == false to indicate VF representor
139 * rep_is_pf == true to indicate PF representor
141 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf) ((rep_is_pf) > 1)
144 * rep_based_pf == Physical index of the PF
146 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf) ((rep_based_pf) > 15)
148 * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
150 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f) ((rep_q_r2f) > 3)
153 * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
155 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r) ((rep_q_f2r) > 3)
158 * rep_fc_r2f == Flow control for the representor to endpoint direction
160 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f) ((rep_fc_r2f) > 1)
163 * rep_fc_f2r == Flow control for the endpoint to representor direction
165 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r) ((rep_fc_f2r) > 1)
167 int bnxt_cfa_code_dynfield_offset = -1;
170 * max_num_kflows must be >= 32
171 * and must be a power-of-2 supported value
172 * return: 1 -> invalid
175 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
177 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
182 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
183 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
184 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
185 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
186 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
187 static int bnxt_restore_vlan_filters(struct bnxt *bp);
188 static void bnxt_dev_recover(void *arg);
189 static void bnxt_free_error_recovery_info(struct bnxt *bp);
190 static void bnxt_free_rep_info(struct bnxt *bp);
192 int is_bnxt_in_error(struct bnxt *bp)
194 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
196 if (bp->flags & BNXT_FLAG_FW_RESET)
202 /***********************/
205 * High level utility functions
208 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
210 if (!BNXT_CHIP_THOR(bp))
213 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
214 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
215 BNXT_RSS_ENTRIES_PER_CTX_THOR;
218 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
220 if (!BNXT_CHIP_THOR(bp))
221 return HW_HASH_INDEX_SIZE;
223 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
226 static void bnxt_free_parent_info(struct bnxt *bp)
228 rte_free(bp->parent);
231 static void bnxt_free_pf_info(struct bnxt *bp)
236 static void bnxt_free_link_info(struct bnxt *bp)
238 rte_free(bp->link_info);
241 static void bnxt_free_leds_info(struct bnxt *bp)
250 static void bnxt_free_flow_stats_info(struct bnxt *bp)
252 rte_free(bp->flow_stat);
253 bp->flow_stat = NULL;
256 static void bnxt_free_cos_queues(struct bnxt *bp)
258 rte_free(bp->rx_cos_queue);
259 rte_free(bp->tx_cos_queue);
262 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
264 bnxt_free_filter_mem(bp);
265 bnxt_free_vnic_attributes(bp);
266 bnxt_free_vnic_mem(bp);
268 /* tx/rx rings are configured as part of *_queue_setup callbacks.
269 * If the number of rings change across fw update,
270 * we don't have much choice except to warn the user.
274 bnxt_free_tx_rings(bp);
275 bnxt_free_rx_rings(bp);
277 bnxt_free_async_cp_ring(bp);
278 bnxt_free_rxtx_nq_ring(bp);
280 rte_free(bp->grp_info);
284 static int bnxt_alloc_parent_info(struct bnxt *bp)
286 bp->parent = rte_zmalloc("bnxt_parent_info",
287 sizeof(struct bnxt_parent_info), 0);
288 if (bp->parent == NULL)
294 static int bnxt_alloc_pf_info(struct bnxt *bp)
296 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
303 static int bnxt_alloc_link_info(struct bnxt *bp)
306 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
307 if (bp->link_info == NULL)
313 static int bnxt_alloc_leds_info(struct bnxt *bp)
318 bp->leds = rte_zmalloc("bnxt_leds",
319 BNXT_MAX_LED * sizeof(struct bnxt_led_info),
321 if (bp->leds == NULL)
327 static int bnxt_alloc_cos_queues(struct bnxt *bp)
330 rte_zmalloc("bnxt_rx_cosq",
331 BNXT_COS_QUEUE_COUNT *
332 sizeof(struct bnxt_cos_queue_info),
334 if (bp->rx_cos_queue == NULL)
338 rte_zmalloc("bnxt_tx_cosq",
339 BNXT_COS_QUEUE_COUNT *
340 sizeof(struct bnxt_cos_queue_info),
342 if (bp->tx_cos_queue == NULL)
348 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
350 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
351 sizeof(struct bnxt_flow_stat_info), 0);
352 if (bp->flow_stat == NULL)
358 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
362 rc = bnxt_alloc_ring_grps(bp);
366 rc = bnxt_alloc_async_ring_struct(bp);
370 rc = bnxt_alloc_vnic_mem(bp);
374 rc = bnxt_alloc_vnic_attributes(bp);
378 rc = bnxt_alloc_filter_mem(bp);
382 rc = bnxt_alloc_async_cp_ring(bp);
386 rc = bnxt_alloc_rxtx_nq_ring(bp);
390 if (BNXT_FLOW_XSTATS_EN(bp)) {
391 rc = bnxt_alloc_flow_stats_info(bp);
399 bnxt_free_mem(bp, reconfig);
403 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
405 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
406 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
407 uint64_t rx_offloads = dev_conf->rxmode.offloads;
408 struct bnxt_rx_queue *rxq;
412 rc = bnxt_vnic_grp_alloc(bp, vnic);
416 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
417 vnic_id, vnic, vnic->fw_grp_ids);
419 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
423 /* Alloc RSS context only if RSS mode is enabled */
424 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
425 int j, nr_ctxs = bnxt_rss_ctxts(bp);
428 for (j = 0; j < nr_ctxs; j++) {
429 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
435 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
439 vnic->num_lb_ctxts = nr_ctxs;
443 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
444 * setting is not available at this time, it will not be
445 * configured correctly in the CFA.
447 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
448 vnic->vlan_strip = true;
450 vnic->vlan_strip = false;
452 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
456 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
460 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
461 rxq = bp->eth_dev->data->rx_queues[j];
464 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
465 j, rxq->vnic, rxq->vnic->fw_grp_ids);
467 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
468 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
470 vnic->rx_queue_cnt++;
473 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
475 rc = bnxt_vnic_rss_configure(bp, vnic);
479 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
481 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
482 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
484 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
488 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
493 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
497 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
498 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
503 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
504 " rx_fc_in_tbl.ctx_id = %d\n",
505 bp->flow_stat->rx_fc_in_tbl.va,
506 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
507 bp->flow_stat->rx_fc_in_tbl.ctx_id);
509 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
510 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
515 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
516 " rx_fc_out_tbl.ctx_id = %d\n",
517 bp->flow_stat->rx_fc_out_tbl.va,
518 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
519 bp->flow_stat->rx_fc_out_tbl.ctx_id);
521 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
522 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
527 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
528 " tx_fc_in_tbl.ctx_id = %d\n",
529 bp->flow_stat->tx_fc_in_tbl.va,
530 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
531 bp->flow_stat->tx_fc_in_tbl.ctx_id);
533 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
534 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
539 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
540 " tx_fc_out_tbl.ctx_id = %d\n",
541 bp->flow_stat->tx_fc_out_tbl.va,
542 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
543 bp->flow_stat->tx_fc_out_tbl.ctx_id);
545 memset(bp->flow_stat->rx_fc_out_tbl.va,
547 bp->flow_stat->rx_fc_out_tbl.size);
548 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
549 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
550 bp->flow_stat->rx_fc_out_tbl.ctx_id,
551 bp->flow_stat->max_fc,
556 memset(bp->flow_stat->tx_fc_out_tbl.va,
558 bp->flow_stat->tx_fc_out_tbl.size);
559 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
560 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
561 bp->flow_stat->tx_fc_out_tbl.ctx_id,
562 bp->flow_stat->max_fc,
568 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
569 struct bnxt_ctx_mem_buf_info *ctx)
574 ctx->va = rte_zmalloc(type, size, 0);
577 rte_mem_lock_page(ctx->va);
579 ctx->dma = rte_mem_virt2iova(ctx->va);
580 if (ctx->dma == RTE_BAD_IOVA)
586 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
588 struct rte_pci_device *pdev = bp->pdev;
589 char type[RTE_MEMZONE_NAMESIZE];
593 max_fc = bp->flow_stat->max_fc;
595 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
596 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
597 /* 4 bytes for each counter-id */
598 rc = bnxt_alloc_ctx_mem_buf(type,
600 &bp->flow_stat->rx_fc_in_tbl);
604 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
605 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
606 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
607 rc = bnxt_alloc_ctx_mem_buf(type,
609 &bp->flow_stat->rx_fc_out_tbl);
613 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
614 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
615 /* 4 bytes for each counter-id */
616 rc = bnxt_alloc_ctx_mem_buf(type,
618 &bp->flow_stat->tx_fc_in_tbl);
622 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
623 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
624 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
625 rc = bnxt_alloc_ctx_mem_buf(type,
627 &bp->flow_stat->tx_fc_out_tbl);
631 rc = bnxt_register_fc_ctx_mem(bp);
636 static int bnxt_init_ctx_mem(struct bnxt *bp)
640 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
641 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
642 !BNXT_FLOW_XSTATS_EN(bp))
645 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
649 rc = bnxt_init_fc_ctx_mem(bp);
654 static int bnxt_update_phy_setting(struct bnxt *bp)
656 struct rte_eth_link new;
659 rc = bnxt_get_hwrm_link_config(bp, &new);
661 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
666 * On BCM957508-N2100 adapters, FW will not allow any user other
667 * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
668 * always returns link up. Force phy update always in that case.
670 if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
671 rc = bnxt_set_hwrm_link_config(bp, true);
673 PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
681 static int bnxt_init_chip(struct bnxt *bp)
683 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
684 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
685 uint32_t intr_vector = 0;
686 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
687 uint32_t vec = BNXT_MISC_VEC_ID;
691 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
692 bp->eth_dev->data->dev_conf.rxmode.offloads |=
693 DEV_RX_OFFLOAD_JUMBO_FRAME;
694 bp->flags |= BNXT_FLAG_JUMBO;
696 bp->eth_dev->data->dev_conf.rxmode.offloads &=
697 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
698 bp->flags &= ~BNXT_FLAG_JUMBO;
701 /* THOR does not support ring groups.
702 * But we will use the array to save RSS context IDs.
704 if (BNXT_CHIP_THOR(bp))
705 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
707 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
709 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
713 rc = bnxt_alloc_hwrm_rings(bp);
715 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
719 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
721 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
725 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
728 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
729 if (bp->rx_cos_queue[i].id != 0xff) {
730 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
734 "Num pools more than FW profile\n");
738 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
744 rc = bnxt_mq_rx_configure(bp);
746 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
750 /* VNIC configuration */
751 for (i = 0; i < bp->nr_vnics; i++) {
752 rc = bnxt_setup_one_vnic(bp, i);
757 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
760 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
764 /* check and configure queue intr-vector mapping */
765 if ((rte_intr_cap_multiple(intr_handle) ||
766 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
767 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
768 intr_vector = bp->eth_dev->data->nb_rx_queues;
769 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
770 if (intr_vector > bp->rx_cp_nr_rings) {
771 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
775 rc = rte_intr_efd_enable(intr_handle, intr_vector);
780 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
781 intr_handle->intr_vec =
782 rte_zmalloc("intr_vec",
783 bp->eth_dev->data->nb_rx_queues *
785 if (intr_handle->intr_vec == NULL) {
786 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
787 " intr_vec", bp->eth_dev->data->nb_rx_queues);
791 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
792 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
793 intr_handle->intr_vec, intr_handle->nb_efd,
794 intr_handle->max_intr);
795 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
797 intr_handle->intr_vec[queue_id] =
798 vec + BNXT_RX_VEC_START;
799 if (vec < base + intr_handle->nb_efd - 1)
804 /* enable uio/vfio intr/eventfd mapping */
805 rc = rte_intr_enable(intr_handle);
806 #ifndef RTE_EXEC_ENV_FREEBSD
807 /* In FreeBSD OS, nic_uio driver does not support interrupts */
812 rc = bnxt_update_phy_setting(bp);
816 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
818 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
823 rte_free(intr_handle->intr_vec);
825 rte_intr_efd_disable(intr_handle);
827 /* Some of the error status returned by FW may not be from errno.h */
834 static int bnxt_shutdown_nic(struct bnxt *bp)
836 bnxt_free_all_hwrm_resources(bp);
837 bnxt_free_all_filters(bp);
838 bnxt_free_all_vnics(bp);
843 * Device configuration and status function
846 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
848 uint32_t link_speed = bp->link_info->support_speeds;
849 uint32_t speed_capa = 0;
851 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
852 speed_capa |= ETH_LINK_SPEED_100M;
853 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
854 speed_capa |= ETH_LINK_SPEED_100M_HD;
855 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
856 speed_capa |= ETH_LINK_SPEED_1G;
857 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
858 speed_capa |= ETH_LINK_SPEED_2_5G;
859 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
860 speed_capa |= ETH_LINK_SPEED_10G;
861 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
862 speed_capa |= ETH_LINK_SPEED_20G;
863 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
864 speed_capa |= ETH_LINK_SPEED_25G;
865 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
866 speed_capa |= ETH_LINK_SPEED_40G;
867 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
868 speed_capa |= ETH_LINK_SPEED_50G;
869 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
870 speed_capa |= ETH_LINK_SPEED_100G;
871 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
872 speed_capa |= ETH_LINK_SPEED_50G;
873 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
874 speed_capa |= ETH_LINK_SPEED_100G;
875 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
876 speed_capa |= ETH_LINK_SPEED_200G;
878 if (bp->link_info->auto_mode ==
879 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
880 speed_capa |= ETH_LINK_SPEED_FIXED;
882 speed_capa |= ETH_LINK_SPEED_AUTONEG;
887 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
888 struct rte_eth_dev_info *dev_info)
890 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
891 struct bnxt *bp = eth_dev->data->dev_private;
892 uint16_t max_vnics, i, j, vpool, vrxq;
893 unsigned int max_rx_rings;
896 rc = is_bnxt_in_error(bp);
901 dev_info->max_mac_addrs = bp->max_l2_ctx;
902 dev_info->max_hash_mac_addrs = 0;
904 /* PF/VF specifics */
906 dev_info->max_vfs = pdev->max_vfs;
908 max_rx_rings = BNXT_MAX_RINGS(bp);
909 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
910 dev_info->max_rx_queues = max_rx_rings;
911 dev_info->max_tx_queues = max_rx_rings;
912 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
913 dev_info->hash_key_size = 40;
914 max_vnics = bp->max_vnics;
917 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
918 dev_info->max_mtu = BNXT_MAX_MTU;
920 /* Fast path specifics */
921 dev_info->min_rx_bufsize = 1;
922 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
924 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
925 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
926 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
927 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
928 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
929 dev_info->tx_queue_offload_capa;
930 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
932 dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
935 dev_info->default_rxconf = (struct rte_eth_rxconf) {
941 .rx_free_thresh = 32,
942 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
945 dev_info->default_txconf = (struct rte_eth_txconf) {
951 .tx_free_thresh = 32,
954 eth_dev->data->dev_conf.intr_conf.lsc = 1;
956 eth_dev->data->dev_conf.intr_conf.rxq = 1;
957 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
958 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
959 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
960 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
962 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
963 dev_info->switch_info.name = eth_dev->device->name;
964 dev_info->switch_info.domain_id = bp->switch_domain_id;
965 dev_info->switch_info.port_id =
966 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
967 BNXT_SWITCH_PORT_ID_TRUSTED_VF;
973 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
974 * need further investigation.
978 vpool = 64; /* ETH_64_POOLS */
979 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
980 for (i = 0; i < 4; vpool >>= 1, i++) {
981 if (max_vnics > vpool) {
982 for (j = 0; j < 5; vrxq >>= 1, j++) {
983 if (dev_info->max_rx_queues > vrxq) {
989 /* Not enough resources to support VMDq */
993 /* Not enough resources to support VMDq */
997 dev_info->max_vmdq_pools = vpool;
998 dev_info->vmdq_queue_num = vrxq;
1000 dev_info->vmdq_pool_base = 0;
1001 dev_info->vmdq_queue_base = 0;
1006 /* Configure the device based on the configuration provided */
1007 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1009 struct bnxt *bp = eth_dev->data->dev_private;
1010 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1013 bp->rx_queues = (void *)eth_dev->data->rx_queues;
1014 bp->tx_queues = (void *)eth_dev->data->tx_queues;
1015 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1016 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1018 rc = is_bnxt_in_error(bp);
1022 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1023 rc = bnxt_hwrm_check_vf_rings(bp);
1025 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1029 /* If a resource has already been allocated - in this case
1030 * it is the async completion ring, free it. Reallocate it after
1031 * resource reservation. This will ensure the resource counts
1032 * are calculated correctly.
1035 pthread_mutex_lock(&bp->def_cp_lock);
1037 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1038 bnxt_disable_int(bp);
1039 bnxt_free_cp_ring(bp, bp->async_cp_ring);
1042 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1044 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1045 pthread_mutex_unlock(&bp->def_cp_lock);
1049 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1050 rc = bnxt_alloc_async_cp_ring(bp);
1052 pthread_mutex_unlock(&bp->def_cp_lock);
1055 bnxt_enable_int(bp);
1058 pthread_mutex_unlock(&bp->def_cp_lock);
1060 /* legacy driver needs to get updated values */
1061 rc = bnxt_hwrm_func_qcaps(bp);
1063 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
1068 /* Inherit new configurations */
1069 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1070 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1071 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1072 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1073 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1075 goto resource_error;
1077 if (BNXT_HAS_RING_GRPS(bp) &&
1078 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1079 goto resource_error;
1081 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1082 bp->max_vnics < eth_dev->data->nb_rx_queues)
1083 goto resource_error;
1085 bp->rx_cp_nr_rings = bp->rx_nr_rings;
1086 bp->tx_cp_nr_rings = bp->tx_nr_rings;
1088 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1089 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1090 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1092 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1093 eth_dev->data->mtu =
1094 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1095 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1097 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1103 "Insufficient resources to support requested config\n");
1105 "Num Queues Requested: Tx %d, Rx %d\n",
1106 eth_dev->data->nb_tx_queues,
1107 eth_dev->data->nb_rx_queues);
1109 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1110 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1111 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1115 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1117 struct rte_eth_link *link = ð_dev->data->dev_link;
1119 if (link->link_status)
1120 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1121 eth_dev->data->port_id,
1122 (uint32_t)link->link_speed,
1123 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1124 ("full-duplex") : ("half-duplex\n"));
1126 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1127 eth_dev->data->port_id);
1131 * Determine whether the current configuration requires support for scattered
1132 * receive; return 1 if scattered receive is required and 0 if not.
1134 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1139 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1142 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1143 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1145 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1146 RTE_PKTMBUF_HEADROOM);
1147 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1153 static eth_rx_burst_t
1154 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1156 struct bnxt *bp = eth_dev->data->dev_private;
1158 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1159 #ifndef RTE_LIBRTE_IEEE1588
1161 * Vector mode receive can be enabled only if scatter rx is not
1162 * in use and rx offloads are limited to VLAN stripping and
1165 if (!eth_dev->data->scattered_rx &&
1166 !(eth_dev->data->dev_conf.rxmode.offloads &
1167 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1168 DEV_RX_OFFLOAD_KEEP_CRC |
1169 DEV_RX_OFFLOAD_JUMBO_FRAME |
1170 DEV_RX_OFFLOAD_IPV4_CKSUM |
1171 DEV_RX_OFFLOAD_UDP_CKSUM |
1172 DEV_RX_OFFLOAD_TCP_CKSUM |
1173 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1174 DEV_RX_OFFLOAD_RSS_HASH |
1175 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1176 !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp) &&
1177 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1178 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1179 eth_dev->data->port_id);
1180 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1181 return bnxt_recv_pkts_vec;
1183 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1184 eth_dev->data->port_id);
1186 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1187 eth_dev->data->port_id,
1188 eth_dev->data->scattered_rx,
1189 eth_dev->data->dev_conf.rxmode.offloads);
1192 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1193 return bnxt_recv_pkts;
1196 static eth_tx_burst_t
1197 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1199 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1200 #ifndef RTE_LIBRTE_IEEE1588
1201 uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1202 struct bnxt *bp = eth_dev->data->dev_private;
1205 * Vector mode transmit can be enabled only if not using scatter rx
1208 if (!eth_dev->data->scattered_rx &&
1209 !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
1210 !BNXT_TRUFLOW_EN(bp) &&
1211 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1212 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1213 eth_dev->data->port_id);
1214 return bnxt_xmit_pkts_vec;
1216 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1217 eth_dev->data->port_id);
1219 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1220 eth_dev->data->port_id,
1221 eth_dev->data->scattered_rx,
1225 return bnxt_xmit_pkts;
1228 static int bnxt_handle_if_change_status(struct bnxt *bp)
1232 /* Since fw has undergone a reset and lost all contexts,
1233 * set fatal flag to not issue hwrm during cleanup
1235 bp->flags |= BNXT_FLAG_FATAL_ERROR;
1236 bnxt_uninit_resources(bp, true);
1238 /* clear fatal flag so that re-init happens */
1239 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1240 rc = bnxt_init_resources(bp, true);
1242 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1247 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1249 struct bnxt *bp = eth_dev->data->dev_private;
1250 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1252 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1254 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1255 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1259 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1261 "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1262 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1266 rc = bnxt_hwrm_if_change(bp, true);
1267 if (rc == 0 || rc != -EAGAIN)
1270 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1271 } while (retry_cnt--);
1276 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1277 rc = bnxt_handle_if_change_status(bp);
1282 bnxt_enable_int(bp);
1284 rc = bnxt_init_chip(bp);
1288 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1289 eth_dev->data->dev_started = 1;
1291 bnxt_link_update_op(eth_dev, 1);
1293 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1294 vlan_mask |= ETH_VLAN_FILTER_MASK;
1295 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1296 vlan_mask |= ETH_VLAN_STRIP_MASK;
1297 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1301 /* Initialize bnxt ULP port details */
1302 rc = bnxt_ulp_port_init(bp);
1306 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1307 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1309 bnxt_schedule_fw_health_check(bp);
1314 bnxt_shutdown_nic(bp);
1315 bnxt_free_tx_mbufs(bp);
1316 bnxt_free_rx_mbufs(bp);
1317 bnxt_hwrm_if_change(bp, false);
1318 eth_dev->data->dev_started = 0;
1322 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1324 struct bnxt *bp = eth_dev->data->dev_private;
1327 if (!bp->link_info->link_up)
1328 rc = bnxt_set_hwrm_link_config(bp, true);
1330 eth_dev->data->dev_link.link_status = 1;
1332 bnxt_print_link_info(eth_dev);
1336 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1338 struct bnxt *bp = eth_dev->data->dev_private;
1340 eth_dev->data->dev_link.link_status = 0;
1341 bnxt_set_hwrm_link_config(bp, false);
1342 bp->link_info->link_up = 0;
1347 static void bnxt_free_switch_domain(struct bnxt *bp)
1349 if (bp->switch_domain_id)
1350 rte_eth_switch_domain_free(bp->switch_domain_id);
1353 /* Unload the driver, release resources */
1354 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1356 struct bnxt *bp = eth_dev->data->dev_private;
1357 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1358 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1359 struct rte_eth_link link;
1362 eth_dev->data->dev_started = 0;
1363 eth_dev->data->scattered_rx = 0;
1365 /* Prevent crashes when queues are still in use */
1366 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1367 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1369 bnxt_disable_int(bp);
1371 /* disable uio/vfio intr/eventfd mapping */
1372 rte_intr_disable(intr_handle);
1374 /* Stop the child representors for this device */
1375 ret = bnxt_rep_stop_all(bp);
1379 /* delete the bnxt ULP port details */
1380 bnxt_ulp_port_deinit(bp);
1382 bnxt_cancel_fw_health_check(bp);
1384 /* Do not bring link down during reset recovery */
1385 if (!is_bnxt_in_error(bp)) {
1386 bnxt_dev_set_link_down_op(eth_dev);
1387 /* Wait for link to be reset */
1388 if (BNXT_SINGLE_PF(bp))
1390 /* clear the recorded link status */
1391 memset(&link, 0, sizeof(link));
1392 rte_eth_linkstatus_set(eth_dev, &link);
1395 /* Clean queue intr-vector mapping */
1396 rte_intr_efd_disable(intr_handle);
1397 if (intr_handle->intr_vec != NULL) {
1398 rte_free(intr_handle->intr_vec);
1399 intr_handle->intr_vec = NULL;
1402 bnxt_hwrm_port_clr_stats(bp);
1403 bnxt_free_tx_mbufs(bp);
1404 bnxt_free_rx_mbufs(bp);
1405 /* Process any remaining notifications in default completion queue */
1406 bnxt_int_handler(eth_dev);
1407 bnxt_shutdown_nic(bp);
1408 bnxt_hwrm_if_change(bp, false);
1410 rte_free(bp->mark_table);
1411 bp->mark_table = NULL;
1413 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1414 bp->rx_cosq_cnt = 0;
1415 /* All filters are deleted on a port stop. */
1416 if (BNXT_FLOW_XSTATS_EN(bp))
1417 bp->flow_stat->flow_count = 0;
1422 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1424 struct bnxt *bp = eth_dev->data->dev_private;
1427 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1430 /* cancel the recovery handler before remove dev */
1431 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1432 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1433 bnxt_cancel_fc_thread(bp);
1435 if (eth_dev->data->dev_started)
1436 ret = bnxt_dev_stop_op(eth_dev);
1438 bnxt_free_switch_domain(bp);
1440 bnxt_uninit_resources(bp, false);
1442 bnxt_free_leds_info(bp);
1443 bnxt_free_cos_queues(bp);
1444 bnxt_free_link_info(bp);
1445 bnxt_free_pf_info(bp);
1446 bnxt_free_parent_info(bp);
1448 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1449 bp->tx_mem_zone = NULL;
1450 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1451 bp->rx_mem_zone = NULL;
1453 bnxt_hwrm_free_vf_info(bp);
1455 rte_free(bp->grp_info);
1456 bp->grp_info = NULL;
1461 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1464 struct bnxt *bp = eth_dev->data->dev_private;
1465 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1466 struct bnxt_vnic_info *vnic;
1467 struct bnxt_filter_info *filter, *temp_filter;
1470 if (is_bnxt_in_error(bp))
1474 * Loop through all VNICs from the specified filter flow pools to
1475 * remove the corresponding MAC addr filter
1477 for (i = 0; i < bp->nr_vnics; i++) {
1478 if (!(pool_mask & (1ULL << i)))
1481 vnic = &bp->vnic_info[i];
1482 filter = STAILQ_FIRST(&vnic->filter);
1484 temp_filter = STAILQ_NEXT(filter, next);
1485 if (filter->mac_index == index) {
1486 STAILQ_REMOVE(&vnic->filter, filter,
1487 bnxt_filter_info, next);
1488 bnxt_hwrm_clear_l2_filter(bp, filter);
1489 bnxt_free_filter(bp, filter);
1491 filter = temp_filter;
1496 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1497 struct rte_ether_addr *mac_addr, uint32_t index,
1500 struct bnxt_filter_info *filter;
1503 /* Attach requested MAC address to the new l2_filter */
1504 STAILQ_FOREACH(filter, &vnic->filter, next) {
1505 if (filter->mac_index == index) {
1507 "MAC addr already existed for pool %d\n",
1513 filter = bnxt_alloc_filter(bp);
1515 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1519 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1520 * if the MAC that's been programmed now is a different one, then,
1521 * copy that addr to filter->l2_addr
1524 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1525 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1527 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1529 filter->mac_index = index;
1530 if (filter->mac_index == 0)
1531 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1533 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1535 bnxt_free_filter(bp, filter);
1541 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1542 struct rte_ether_addr *mac_addr,
1543 uint32_t index, uint32_t pool)
1545 struct bnxt *bp = eth_dev->data->dev_private;
1546 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1549 rc = is_bnxt_in_error(bp);
1553 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1554 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1559 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1563 /* Filter settings will get applied when port is started */
1564 if (!eth_dev->data->dev_started)
1567 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1572 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1575 struct bnxt *bp = eth_dev->data->dev_private;
1576 struct rte_eth_link new;
1577 int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1578 BNXT_MIN_LINK_WAIT_CNT;
1580 rc = is_bnxt_in_error(bp);
1584 memset(&new, 0, sizeof(new));
1586 /* Retrieve link info from hardware */
1587 rc = bnxt_get_hwrm_link_config(bp, &new);
1589 new.link_speed = ETH_LINK_SPEED_100M;
1590 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1592 "Failed to retrieve link rc = 0x%x!\n", rc);
1596 if (!wait_to_complete || new.link_status)
1599 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1602 /* Only single function PF can bring phy down.
1603 * When port is stopped, report link down for VF/MH/NPAR functions.
1605 if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1606 memset(&new, 0, sizeof(new));
1609 /* Timed out or success */
1610 if (new.link_status != eth_dev->data->dev_link.link_status ||
1611 new.link_speed != eth_dev->data->dev_link.link_speed) {
1612 rte_eth_linkstatus_set(eth_dev, &new);
1614 rte_eth_dev_callback_process(eth_dev,
1615 RTE_ETH_EVENT_INTR_LSC,
1618 bnxt_print_link_info(eth_dev);
1624 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1626 struct bnxt *bp = eth_dev->data->dev_private;
1627 struct bnxt_vnic_info *vnic;
1631 rc = is_bnxt_in_error(bp);
1635 /* Filter settings will get applied when port is started */
1636 if (!eth_dev->data->dev_started)
1639 if (bp->vnic_info == NULL)
1642 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1644 old_flags = vnic->flags;
1645 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1646 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1648 vnic->flags = old_flags;
1653 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1655 struct bnxt *bp = eth_dev->data->dev_private;
1656 struct bnxt_vnic_info *vnic;
1660 rc = is_bnxt_in_error(bp);
1664 /* Filter settings will get applied when port is started */
1665 if (!eth_dev->data->dev_started)
1668 if (bp->vnic_info == NULL)
1671 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1673 old_flags = vnic->flags;
1674 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1675 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1677 vnic->flags = old_flags;
1682 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1684 struct bnxt *bp = eth_dev->data->dev_private;
1685 struct bnxt_vnic_info *vnic;
1689 rc = is_bnxt_in_error(bp);
1693 /* Filter settings will get applied when port is started */
1694 if (!eth_dev->data->dev_started)
1697 if (bp->vnic_info == NULL)
1700 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1702 old_flags = vnic->flags;
1703 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1704 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1706 vnic->flags = old_flags;
1711 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1713 struct bnxt *bp = eth_dev->data->dev_private;
1714 struct bnxt_vnic_info *vnic;
1718 rc = is_bnxt_in_error(bp);
1722 /* Filter settings will get applied when port is started */
1723 if (!eth_dev->data->dev_started)
1726 if (bp->vnic_info == NULL)
1729 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1731 old_flags = vnic->flags;
1732 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1733 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1735 vnic->flags = old_flags;
1740 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1741 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1743 if (qid >= bp->rx_nr_rings)
1746 return bp->eth_dev->data->rx_queues[qid];
1749 /* Return rxq corresponding to a given rss table ring/group ID. */
1750 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1752 struct bnxt_rx_queue *rxq;
1755 if (!BNXT_HAS_RING_GRPS(bp)) {
1756 for (i = 0; i < bp->rx_nr_rings; i++) {
1757 rxq = bp->eth_dev->data->rx_queues[i];
1758 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1762 for (i = 0; i < bp->rx_nr_rings; i++) {
1763 if (bp->grp_info[i].fw_grp_id == fwr)
1768 return INVALID_HW_RING_ID;
1771 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1772 struct rte_eth_rss_reta_entry64 *reta_conf,
1775 struct bnxt *bp = eth_dev->data->dev_private;
1776 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1777 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1778 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1782 rc = is_bnxt_in_error(bp);
1786 if (!vnic->rss_table)
1789 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1792 if (reta_size != tbl_size) {
1793 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1794 "(%d) must equal the size supported by the hardware "
1795 "(%d)\n", reta_size, tbl_size);
1799 for (i = 0; i < reta_size; i++) {
1800 struct bnxt_rx_queue *rxq;
1802 idx = i / RTE_RETA_GROUP_SIZE;
1803 sft = i % RTE_RETA_GROUP_SIZE;
1805 if (!(reta_conf[idx].mask & (1ULL << sft)))
1808 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1810 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1814 if (BNXT_CHIP_THOR(bp)) {
1815 vnic->rss_table[i * 2] =
1816 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1817 vnic->rss_table[i * 2 + 1] =
1818 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1820 vnic->rss_table[i] =
1821 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1825 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1829 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1830 struct rte_eth_rss_reta_entry64 *reta_conf,
1833 struct bnxt *bp = eth_dev->data->dev_private;
1834 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1835 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1836 uint16_t idx, sft, i;
1839 rc = is_bnxt_in_error(bp);
1843 /* Retrieve from the default VNIC */
1846 if (!vnic->rss_table)
1849 if (reta_size != tbl_size) {
1850 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1851 "(%d) must equal the size supported by the hardware "
1852 "(%d)\n", reta_size, tbl_size);
1856 for (idx = 0, i = 0; i < reta_size; i++) {
1857 idx = i / RTE_RETA_GROUP_SIZE;
1858 sft = i % RTE_RETA_GROUP_SIZE;
1860 if (reta_conf[idx].mask & (1ULL << sft)) {
1863 if (BNXT_CHIP_THOR(bp))
1864 qid = bnxt_rss_to_qid(bp,
1865 vnic->rss_table[i * 2]);
1867 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1869 if (qid == INVALID_HW_RING_ID) {
1870 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1873 reta_conf[idx].reta[sft] = qid;
1880 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1881 struct rte_eth_rss_conf *rss_conf)
1883 struct bnxt *bp = eth_dev->data->dev_private;
1884 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1885 struct bnxt_vnic_info *vnic;
1888 rc = is_bnxt_in_error(bp);
1893 * If RSS enablement were different than dev_configure,
1894 * then return -EINVAL
1896 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1897 if (!rss_conf->rss_hf)
1898 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1900 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1904 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1905 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf,
1909 /* Update the default RSS VNIC(s) */
1910 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1911 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1913 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
1914 ETH_RSS_LEVEL(rss_conf->rss_hf));
1917 * If hashkey is not specified, use the previously configured
1920 if (!rss_conf->rss_key)
1923 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1925 "Invalid hashkey length, should be 16 bytes\n");
1928 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1931 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1935 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1936 struct rte_eth_rss_conf *rss_conf)
1938 struct bnxt *bp = eth_dev->data->dev_private;
1939 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1941 uint32_t hash_types;
1943 rc = is_bnxt_in_error(bp);
1947 /* RSS configuration is the same for all VNICs */
1948 if (vnic && vnic->rss_hash_key) {
1949 if (rss_conf->rss_key) {
1950 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1951 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1952 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1955 hash_types = vnic->hash_type;
1956 rss_conf->rss_hf = 0;
1957 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1958 rss_conf->rss_hf |= ETH_RSS_IPV4;
1959 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1961 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1962 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1964 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1966 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1967 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1969 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1971 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1972 rss_conf->rss_hf |= ETH_RSS_IPV6;
1973 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1975 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1976 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1978 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1980 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1981 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1983 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1987 bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
1991 "Unknown RSS config from firmware (%08x), RSS disabled",
1996 rss_conf->rss_hf = 0;
2001 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2002 struct rte_eth_fc_conf *fc_conf)
2004 struct bnxt *bp = dev->data->dev_private;
2005 struct rte_eth_link link_info;
2008 rc = is_bnxt_in_error(bp);
2012 rc = bnxt_get_hwrm_link_config(bp, &link_info);
2016 memset(fc_conf, 0, sizeof(*fc_conf));
2017 if (bp->link_info->auto_pause)
2018 fc_conf->autoneg = 1;
2019 switch (bp->link_info->pause) {
2021 fc_conf->mode = RTE_FC_NONE;
2023 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2024 fc_conf->mode = RTE_FC_TX_PAUSE;
2026 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2027 fc_conf->mode = RTE_FC_RX_PAUSE;
2029 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2030 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2031 fc_conf->mode = RTE_FC_FULL;
2037 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2038 struct rte_eth_fc_conf *fc_conf)
2040 struct bnxt *bp = dev->data->dev_private;
2043 rc = is_bnxt_in_error(bp);
2047 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2048 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2052 switch (fc_conf->mode) {
2054 bp->link_info->auto_pause = 0;
2055 bp->link_info->force_pause = 0;
2057 case RTE_FC_RX_PAUSE:
2058 if (fc_conf->autoneg) {
2059 bp->link_info->auto_pause =
2060 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2061 bp->link_info->force_pause = 0;
2063 bp->link_info->auto_pause = 0;
2064 bp->link_info->force_pause =
2065 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2068 case RTE_FC_TX_PAUSE:
2069 if (fc_conf->autoneg) {
2070 bp->link_info->auto_pause =
2071 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2072 bp->link_info->force_pause = 0;
2074 bp->link_info->auto_pause = 0;
2075 bp->link_info->force_pause =
2076 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2080 if (fc_conf->autoneg) {
2081 bp->link_info->auto_pause =
2082 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2083 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2084 bp->link_info->force_pause = 0;
2086 bp->link_info->auto_pause = 0;
2087 bp->link_info->force_pause =
2088 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2089 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2093 return bnxt_set_hwrm_link_config(bp, true);
2096 /* Add UDP tunneling port */
2098 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2099 struct rte_eth_udp_tunnel *udp_tunnel)
2101 struct bnxt *bp = eth_dev->data->dev_private;
2102 uint16_t tunnel_type = 0;
2105 rc = is_bnxt_in_error(bp);
2109 switch (udp_tunnel->prot_type) {
2110 case RTE_TUNNEL_TYPE_VXLAN:
2111 if (bp->vxlan_port_cnt) {
2112 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2113 udp_tunnel->udp_port);
2114 if (bp->vxlan_port != udp_tunnel->udp_port) {
2115 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2118 bp->vxlan_port_cnt++;
2122 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2123 bp->vxlan_port_cnt++;
2125 case RTE_TUNNEL_TYPE_GENEVE:
2126 if (bp->geneve_port_cnt) {
2127 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2128 udp_tunnel->udp_port);
2129 if (bp->geneve_port != udp_tunnel->udp_port) {
2130 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2133 bp->geneve_port_cnt++;
2137 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2138 bp->geneve_port_cnt++;
2141 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2144 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2150 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2151 struct rte_eth_udp_tunnel *udp_tunnel)
2153 struct bnxt *bp = eth_dev->data->dev_private;
2154 uint16_t tunnel_type = 0;
2158 rc = is_bnxt_in_error(bp);
2162 switch (udp_tunnel->prot_type) {
2163 case RTE_TUNNEL_TYPE_VXLAN:
2164 if (!bp->vxlan_port_cnt) {
2165 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2168 if (bp->vxlan_port != udp_tunnel->udp_port) {
2169 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2170 udp_tunnel->udp_port, bp->vxlan_port);
2173 if (--bp->vxlan_port_cnt)
2177 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2178 port = bp->vxlan_fw_dst_port_id;
2180 case RTE_TUNNEL_TYPE_GENEVE:
2181 if (!bp->geneve_port_cnt) {
2182 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2185 if (bp->geneve_port != udp_tunnel->udp_port) {
2186 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2187 udp_tunnel->udp_port, bp->geneve_port);
2190 if (--bp->geneve_port_cnt)
2194 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2195 port = bp->geneve_fw_dst_port_id;
2198 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2202 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2206 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2208 struct bnxt_filter_info *filter;
2209 struct bnxt_vnic_info *vnic;
2211 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2213 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2214 filter = STAILQ_FIRST(&vnic->filter);
2216 /* Search for this matching MAC+VLAN filter */
2217 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2218 /* Delete the filter */
2219 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2222 STAILQ_REMOVE(&vnic->filter, filter,
2223 bnxt_filter_info, next);
2224 bnxt_free_filter(bp, filter);
2226 "Deleted vlan filter for %d\n",
2230 filter = STAILQ_NEXT(filter, next);
2235 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2237 struct bnxt_filter_info *filter;
2238 struct bnxt_vnic_info *vnic;
2240 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2241 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2242 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2244 /* Implementation notes on the use of VNIC in this command:
2246 * By default, these filters belong to default vnic for the function.
2247 * Once these filters are set up, only destination VNIC can be modified.
2248 * If the destination VNIC is not specified in this command,
2249 * then the HWRM shall only create an l2 context id.
2252 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2253 filter = STAILQ_FIRST(&vnic->filter);
2254 /* Check if the VLAN has already been added */
2256 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2259 filter = STAILQ_NEXT(filter, next);
2262 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2263 * command to create MAC+VLAN filter with the right flags, enables set.
2265 filter = bnxt_alloc_filter(bp);
2268 "MAC/VLAN filter alloc failed\n");
2271 /* MAC + VLAN ID filter */
2272 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2273 * untagged packets are received
2275 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2276 * packets and only the programmed vlan's packets are received
2278 filter->l2_ivlan = vlan_id;
2279 filter->l2_ivlan_mask = 0x0FFF;
2280 filter->enables |= en;
2281 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2283 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2285 /* Free the newly allocated filter as we were
2286 * not able to create the filter in hardware.
2288 bnxt_free_filter(bp, filter);
2292 filter->mac_index = 0;
2293 /* Add this new filter to the list */
2295 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2297 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2300 "Added Vlan filter for %d\n", vlan_id);
2304 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2305 uint16_t vlan_id, int on)
2307 struct bnxt *bp = eth_dev->data->dev_private;
2310 rc = is_bnxt_in_error(bp);
2314 if (!eth_dev->data->dev_started) {
2315 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2319 /* These operations apply to ALL existing MAC/VLAN filters */
2321 return bnxt_add_vlan_filter(bp, vlan_id);
2323 return bnxt_del_vlan_filter(bp, vlan_id);
2326 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2327 struct bnxt_vnic_info *vnic)
2329 struct bnxt_filter_info *filter;
2332 filter = STAILQ_FIRST(&vnic->filter);
2334 if (filter->mac_index == 0 &&
2335 !memcmp(filter->l2_addr, bp->mac_addr,
2336 RTE_ETHER_ADDR_LEN)) {
2337 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2339 STAILQ_REMOVE(&vnic->filter, filter,
2340 bnxt_filter_info, next);
2341 bnxt_free_filter(bp, filter);
2345 filter = STAILQ_NEXT(filter, next);
2351 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2353 struct bnxt_vnic_info *vnic;
2357 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2358 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2359 /* Remove any VLAN filters programmed */
2360 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2361 bnxt_del_vlan_filter(bp, i);
2363 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2367 /* Default filter will allow packets that match the
2368 * dest mac. So, it has to be deleted, otherwise, we
2369 * will endup receiving vlan packets for which the
2370 * filter is not programmed, when hw-vlan-filter
2371 * configuration is ON
2373 bnxt_del_dflt_mac_filter(bp, vnic);
2374 /* This filter will allow only untagged packets */
2375 bnxt_add_vlan_filter(bp, 0);
2377 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2378 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2383 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2385 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2389 /* Destroy vnic filters and vnic */
2390 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2391 DEV_RX_OFFLOAD_VLAN_FILTER) {
2392 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2393 bnxt_del_vlan_filter(bp, i);
2395 bnxt_del_dflt_mac_filter(bp, vnic);
2397 rc = bnxt_hwrm_vnic_free(bp, vnic);
2401 rte_free(vnic->fw_grp_ids);
2402 vnic->fw_grp_ids = NULL;
2404 vnic->rx_queue_cnt = 0;
2410 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2412 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2415 /* Destroy, recreate and reconfigure the default vnic */
2416 rc = bnxt_free_one_vnic(bp, 0);
2420 /* default vnic 0 */
2421 rc = bnxt_setup_one_vnic(bp, 0);
2425 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2426 DEV_RX_OFFLOAD_VLAN_FILTER) {
2427 rc = bnxt_add_vlan_filter(bp, 0);
2430 rc = bnxt_restore_vlan_filters(bp);
2434 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2439 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2443 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2444 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2450 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2452 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2453 struct bnxt *bp = dev->data->dev_private;
2456 rc = is_bnxt_in_error(bp);
2460 /* Filter settings will get applied when port is started */
2461 if (!dev->data->dev_started)
2464 if (mask & ETH_VLAN_FILTER_MASK) {
2465 /* Enable or disable VLAN filtering */
2466 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2471 if (mask & ETH_VLAN_STRIP_MASK) {
2472 /* Enable or disable VLAN stripping */
2473 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2478 if (mask & ETH_VLAN_EXTEND_MASK) {
2479 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2480 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2482 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2489 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2492 struct bnxt *bp = dev->data->dev_private;
2493 int qinq = dev->data->dev_conf.rxmode.offloads &
2494 DEV_RX_OFFLOAD_VLAN_EXTEND;
2496 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2497 vlan_type != ETH_VLAN_TYPE_OUTER) {
2499 "Unsupported vlan type.");
2504 "QinQ not enabled. Needs to be ON as we can "
2505 "accelerate only outer vlan\n");
2509 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2511 case RTE_ETHER_TYPE_QINQ:
2513 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2515 case RTE_ETHER_TYPE_VLAN:
2517 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2519 case RTE_ETHER_TYPE_QINQ1:
2521 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2523 case RTE_ETHER_TYPE_QINQ2:
2525 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2527 case RTE_ETHER_TYPE_QINQ3:
2529 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2532 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2535 bp->outer_tpid_bd |= tpid;
2536 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2537 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2539 "Can accelerate only outer vlan in QinQ\n");
2547 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2548 struct rte_ether_addr *addr)
2550 struct bnxt *bp = dev->data->dev_private;
2551 /* Default Filter is tied to VNIC 0 */
2552 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2555 rc = is_bnxt_in_error(bp);
2559 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2562 if (rte_is_zero_ether_addr(addr))
2565 /* Filter settings will get applied when port is started */
2566 if (!dev->data->dev_started)
2569 /* Check if the requested MAC is already added */
2570 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2573 /* Destroy filter and re-create it */
2574 bnxt_del_dflt_mac_filter(bp, vnic);
2576 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2577 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2578 /* This filter will allow only untagged packets */
2579 rc = bnxt_add_vlan_filter(bp, 0);
2581 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2584 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2589 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2590 struct rte_ether_addr *mc_addr_set,
2591 uint32_t nb_mc_addr)
2593 struct bnxt *bp = eth_dev->data->dev_private;
2594 char *mc_addr_list = (char *)mc_addr_set;
2595 struct bnxt_vnic_info *vnic;
2596 uint32_t off = 0, i = 0;
2599 rc = is_bnxt_in_error(bp);
2603 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2605 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2606 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2610 /* TODO Check for Duplicate mcast addresses */
2611 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2612 for (i = 0; i < nb_mc_addr; i++) {
2613 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2614 RTE_ETHER_ADDR_LEN);
2615 off += RTE_ETHER_ADDR_LEN;
2618 vnic->mc_addr_cnt = i;
2619 if (vnic->mc_addr_cnt)
2620 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2622 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2625 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2629 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2631 struct bnxt *bp = dev->data->dev_private;
2632 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2633 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2634 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2635 uint8_t fw_rsvd = bp->fw_ver & 0xff;
2638 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2639 fw_major, fw_minor, fw_updt, fw_rsvd);
2641 ret += 1; /* add the size of '\0' */
2642 if (fw_size < (uint32_t)ret)
2649 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2650 struct rte_eth_rxq_info *qinfo)
2652 struct bnxt *bp = dev->data->dev_private;
2653 struct bnxt_rx_queue *rxq;
2655 if (is_bnxt_in_error(bp))
2658 rxq = dev->data->rx_queues[queue_id];
2660 qinfo->mp = rxq->mb_pool;
2661 qinfo->scattered_rx = dev->data->scattered_rx;
2662 qinfo->nb_desc = rxq->nb_rx_desc;
2664 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2665 qinfo->conf.rx_drop_en = rxq->drop_en;
2666 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2667 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2671 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2672 struct rte_eth_txq_info *qinfo)
2674 struct bnxt *bp = dev->data->dev_private;
2675 struct bnxt_tx_queue *txq;
2677 if (is_bnxt_in_error(bp))
2680 txq = dev->data->tx_queues[queue_id];
2682 qinfo->nb_desc = txq->nb_tx_desc;
2684 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2685 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2686 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2688 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2689 qinfo->conf.tx_rs_thresh = 0;
2690 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2691 qinfo->conf.offloads = txq->offloads;
2694 static const struct {
2695 eth_rx_burst_t pkt_burst;
2697 } bnxt_rx_burst_info[] = {
2698 {bnxt_recv_pkts, "Scalar"},
2699 #if defined(RTE_ARCH_X86)
2700 {bnxt_recv_pkts_vec, "Vector SSE"},
2701 #elif defined(RTE_ARCH_ARM64)
2702 {bnxt_recv_pkts_vec, "Vector Neon"},
2707 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2708 struct rte_eth_burst_mode *mode)
2710 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2713 for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2714 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2715 snprintf(mode->info, sizeof(mode->info), "%s",
2716 bnxt_rx_burst_info[i].info);
2724 static const struct {
2725 eth_tx_burst_t pkt_burst;
2727 } bnxt_tx_burst_info[] = {
2728 {bnxt_xmit_pkts, "Scalar"},
2729 #if defined(RTE_ARCH_X86)
2730 {bnxt_xmit_pkts_vec, "Vector SSE"},
2731 #elif defined(RTE_ARCH_ARM64)
2732 {bnxt_xmit_pkts_vec, "Vector Neon"},
2737 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2738 struct rte_eth_burst_mode *mode)
2740 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2743 for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2744 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2745 snprintf(mode->info, sizeof(mode->info), "%s",
2746 bnxt_tx_burst_info[i].info);
2754 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2756 struct bnxt *bp = eth_dev->data->dev_private;
2757 uint32_t new_pkt_size;
2761 rc = is_bnxt_in_error(bp);
2765 /* Exit if receive queues are not configured yet */
2766 if (!eth_dev->data->nb_rx_queues)
2769 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2770 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2773 * Disallow any MTU change that would require scattered receive support
2774 * if it is not already enabled.
2776 if (eth_dev->data->dev_started &&
2777 !eth_dev->data->scattered_rx &&
2779 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2781 "MTU change would require scattered rx support. ");
2782 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2786 if (new_mtu > RTE_ETHER_MTU) {
2787 bp->flags |= BNXT_FLAG_JUMBO;
2788 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2789 DEV_RX_OFFLOAD_JUMBO_FRAME;
2791 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2792 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2793 bp->flags &= ~BNXT_FLAG_JUMBO;
2796 /* Is there a change in mtu setting? */
2797 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2800 for (i = 0; i < bp->nr_vnics; i++) {
2801 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2804 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2805 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2809 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2810 size -= RTE_PKTMBUF_HEADROOM;
2812 if (size < new_mtu) {
2813 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2820 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2822 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2828 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2830 struct bnxt *bp = dev->data->dev_private;
2831 uint16_t vlan = bp->vlan;
2834 rc = is_bnxt_in_error(bp);
2838 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2840 "PVID cannot be modified for this function\n");
2843 bp->vlan = on ? pvid : 0;
2845 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2852 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2854 struct bnxt *bp = dev->data->dev_private;
2857 rc = is_bnxt_in_error(bp);
2861 return bnxt_hwrm_port_led_cfg(bp, true);
2865 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2867 struct bnxt *bp = dev->data->dev_private;
2870 rc = is_bnxt_in_error(bp);
2874 return bnxt_hwrm_port_led_cfg(bp, false);
2878 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2880 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2881 uint32_t desc = 0, raw_cons = 0, cons;
2882 struct bnxt_cp_ring_info *cpr;
2883 struct bnxt_rx_queue *rxq;
2884 struct rx_pkt_cmpl *rxcmp;
2887 rc = is_bnxt_in_error(bp);
2891 rxq = dev->data->rx_queues[rx_queue_id];
2893 raw_cons = cpr->cp_raw_cons;
2896 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2897 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2898 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2900 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2912 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2914 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2915 struct bnxt_rx_ring_info *rxr;
2916 struct bnxt_cp_ring_info *cpr;
2917 struct rte_mbuf *rx_buf;
2918 struct rx_pkt_cmpl *rxcmp;
2919 uint32_t cons, cp_cons;
2925 rc = is_bnxt_in_error(rxq->bp);
2932 if (offset >= rxq->nb_rx_desc)
2935 cons = RING_CMP(cpr->cp_ring_struct, offset);
2936 cp_cons = cpr->cp_raw_cons;
2937 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2939 if (cons > cp_cons) {
2940 if (CMPL_VALID(rxcmp, cpr->valid))
2941 return RTE_ETH_RX_DESC_DONE;
2943 if (CMPL_VALID(rxcmp, !cpr->valid))
2944 return RTE_ETH_RX_DESC_DONE;
2946 rx_buf = rxr->rx_buf_ring[cons];
2947 if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf)
2948 return RTE_ETH_RX_DESC_UNAVAIL;
2951 return RTE_ETH_RX_DESC_AVAIL;
2955 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2957 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2958 struct bnxt_tx_ring_info *txr;
2959 struct bnxt_cp_ring_info *cpr;
2960 struct bnxt_sw_tx_bd *tx_buf;
2961 struct tx_pkt_cmpl *txcmp;
2962 uint32_t cons, cp_cons;
2968 rc = is_bnxt_in_error(txq->bp);
2975 if (offset >= txq->nb_tx_desc)
2978 cons = RING_CMP(cpr->cp_ring_struct, offset);
2979 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2980 cp_cons = cpr->cp_raw_cons;
2982 if (cons > cp_cons) {
2983 if (CMPL_VALID(txcmp, cpr->valid))
2984 return RTE_ETH_TX_DESC_UNAVAIL;
2986 if (CMPL_VALID(txcmp, !cpr->valid))
2987 return RTE_ETH_TX_DESC_UNAVAIL;
2989 tx_buf = &txr->tx_buf_ring[cons];
2990 if (tx_buf->mbuf == NULL)
2991 return RTE_ETH_TX_DESC_DONE;
2993 return RTE_ETH_TX_DESC_FULL;
2997 bnxt_parse_fdir_filter(struct bnxt *bp,
2998 struct rte_eth_fdir_filter *fdir,
2999 struct bnxt_filter_info *filter)
3001 enum rte_fdir_mode fdir_mode =
3002 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3003 struct bnxt_vnic_info *vnic0, *vnic;
3004 struct bnxt_filter_info *filter1;
3008 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3011 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3012 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3014 switch (fdir->input.flow_type) {
3015 case RTE_ETH_FLOW_IPV4:
3016 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3018 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3019 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3020 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3021 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3022 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3023 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3024 filter->ip_addr_type =
3025 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3026 filter->src_ipaddr_mask[0] = 0xffffffff;
3027 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3028 filter->dst_ipaddr_mask[0] = 0xffffffff;
3029 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3030 filter->ethertype = 0x800;
3031 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3033 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3034 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3035 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3036 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3037 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3038 filter->dst_port_mask = 0xffff;
3039 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3040 filter->src_port_mask = 0xffff;
3041 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3042 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3043 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3044 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3045 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3046 filter->ip_protocol = 6;
3047 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3048 filter->ip_addr_type =
3049 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3050 filter->src_ipaddr_mask[0] = 0xffffffff;
3051 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3052 filter->dst_ipaddr_mask[0] = 0xffffffff;
3053 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3054 filter->ethertype = 0x800;
3055 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3057 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3058 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3059 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3060 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3061 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3062 filter->dst_port_mask = 0xffff;
3063 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3064 filter->src_port_mask = 0xffff;
3065 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3066 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3067 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3068 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3069 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3070 filter->ip_protocol = 17;
3071 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3072 filter->ip_addr_type =
3073 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3074 filter->src_ipaddr_mask[0] = 0xffffffff;
3075 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3076 filter->dst_ipaddr_mask[0] = 0xffffffff;
3077 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3078 filter->ethertype = 0x800;
3079 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3081 case RTE_ETH_FLOW_IPV6:
3082 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3084 filter->ip_addr_type =
3085 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3086 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3087 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3088 rte_memcpy(filter->src_ipaddr,
3089 fdir->input.flow.ipv6_flow.src_ip, 16);
3090 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3091 rte_memcpy(filter->dst_ipaddr,
3092 fdir->input.flow.ipv6_flow.dst_ip, 16);
3093 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3094 memset(filter->dst_ipaddr_mask, 0xff, 16);
3095 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3096 memset(filter->src_ipaddr_mask, 0xff, 16);
3097 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3098 filter->ethertype = 0x86dd;
3099 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3101 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3102 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3103 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3104 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3105 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3106 filter->dst_port_mask = 0xffff;
3107 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3108 filter->src_port_mask = 0xffff;
3109 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3110 filter->ip_addr_type =
3111 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3112 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3113 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3114 rte_memcpy(filter->src_ipaddr,
3115 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3116 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3117 rte_memcpy(filter->dst_ipaddr,
3118 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3119 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3120 memset(filter->dst_ipaddr_mask, 0xff, 16);
3121 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3122 memset(filter->src_ipaddr_mask, 0xff, 16);
3123 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3124 filter->ethertype = 0x86dd;
3125 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3127 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3128 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3129 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3130 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3131 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3132 filter->dst_port_mask = 0xffff;
3133 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3134 filter->src_port_mask = 0xffff;
3135 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3136 filter->ip_addr_type =
3137 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3138 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3139 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3140 rte_memcpy(filter->src_ipaddr,
3141 fdir->input.flow.udp6_flow.ip.src_ip, 16);
3142 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3143 rte_memcpy(filter->dst_ipaddr,
3144 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3145 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3146 memset(filter->dst_ipaddr_mask, 0xff, 16);
3147 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3148 memset(filter->src_ipaddr_mask, 0xff, 16);
3149 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3150 filter->ethertype = 0x86dd;
3151 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3153 case RTE_ETH_FLOW_L2_PAYLOAD:
3154 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3155 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3157 case RTE_ETH_FLOW_VXLAN:
3158 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3160 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3161 filter->tunnel_type =
3162 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3163 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3165 case RTE_ETH_FLOW_NVGRE:
3166 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3168 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3169 filter->tunnel_type =
3170 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3171 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3173 case RTE_ETH_FLOW_UNKNOWN:
3174 case RTE_ETH_FLOW_RAW:
3175 case RTE_ETH_FLOW_FRAG_IPV4:
3176 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3177 case RTE_ETH_FLOW_FRAG_IPV6:
3178 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3179 case RTE_ETH_FLOW_IPV6_EX:
3180 case RTE_ETH_FLOW_IPV6_TCP_EX:
3181 case RTE_ETH_FLOW_IPV6_UDP_EX:
3182 case RTE_ETH_FLOW_GENEVE:
3188 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3189 vnic = &bp->vnic_info[fdir->action.rx_queue];
3191 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3195 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3196 rte_memcpy(filter->dst_macaddr,
3197 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3198 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3201 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3202 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3203 filter1 = STAILQ_FIRST(&vnic0->filter);
3204 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3206 filter->dst_id = vnic->fw_vnic_id;
3207 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3208 if (filter->dst_macaddr[i] == 0x00)
3209 filter1 = STAILQ_FIRST(&vnic0->filter);
3211 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3214 if (filter1 == NULL)
3217 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3218 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3220 filter->enables = en;
3225 static struct bnxt_filter_info *
3226 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3227 struct bnxt_vnic_info **mvnic)
3229 struct bnxt_filter_info *mf = NULL;
3232 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3233 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3235 STAILQ_FOREACH(mf, &vnic->filter, next) {
3236 if (mf->filter_type == nf->filter_type &&
3237 mf->flags == nf->flags &&
3238 mf->src_port == nf->src_port &&
3239 mf->src_port_mask == nf->src_port_mask &&
3240 mf->dst_port == nf->dst_port &&
3241 mf->dst_port_mask == nf->dst_port_mask &&
3242 mf->ip_protocol == nf->ip_protocol &&
3243 mf->ip_addr_type == nf->ip_addr_type &&
3244 mf->ethertype == nf->ethertype &&
3245 mf->vni == nf->vni &&
3246 mf->tunnel_type == nf->tunnel_type &&
3247 mf->l2_ovlan == nf->l2_ovlan &&
3248 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3249 mf->l2_ivlan == nf->l2_ivlan &&
3250 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3251 !memcmp(mf->l2_addr, nf->l2_addr,
3252 RTE_ETHER_ADDR_LEN) &&
3253 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3254 RTE_ETHER_ADDR_LEN) &&
3255 !memcmp(mf->src_macaddr, nf->src_macaddr,
3256 RTE_ETHER_ADDR_LEN) &&
3257 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3258 RTE_ETHER_ADDR_LEN) &&
3259 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3260 sizeof(nf->src_ipaddr)) &&
3261 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3262 sizeof(nf->src_ipaddr_mask)) &&
3263 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3264 sizeof(nf->dst_ipaddr)) &&
3265 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3266 sizeof(nf->dst_ipaddr_mask))) {
3277 bnxt_fdir_filter(struct rte_eth_dev *dev,
3278 enum rte_filter_op filter_op,
3281 struct bnxt *bp = dev->data->dev_private;
3282 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
3283 struct bnxt_filter_info *filter, *match;
3284 struct bnxt_vnic_info *vnic, *mvnic;
3287 if (filter_op == RTE_ETH_FILTER_NOP)
3290 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3293 switch (filter_op) {
3294 case RTE_ETH_FILTER_ADD:
3295 case RTE_ETH_FILTER_DELETE:
3297 filter = bnxt_get_unused_filter(bp);
3298 if (filter == NULL) {
3300 "Not enough resources for a new flow.\n");
3304 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3307 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3309 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3310 vnic = &bp->vnic_info[0];
3312 vnic = &bp->vnic_info[fdir->action.rx_queue];
3314 match = bnxt_match_fdir(bp, filter, &mvnic);
3315 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3316 if (match->dst_id == vnic->fw_vnic_id) {
3317 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3321 match->dst_id = vnic->fw_vnic_id;
3322 ret = bnxt_hwrm_set_ntuple_filter(bp,
3325 STAILQ_REMOVE(&mvnic->filter, match,
3326 bnxt_filter_info, next);
3327 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3329 "Filter with matching pattern exist\n");
3331 "Updated it to new destination q\n");
3335 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3336 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3341 if (filter_op == RTE_ETH_FILTER_ADD) {
3342 ret = bnxt_hwrm_set_ntuple_filter(bp,
3347 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3349 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3350 STAILQ_REMOVE(&vnic->filter, match,
3351 bnxt_filter_info, next);
3352 bnxt_free_filter(bp, match);
3353 bnxt_free_filter(bp, filter);
3356 case RTE_ETH_FILTER_FLUSH:
3357 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3358 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3360 STAILQ_FOREACH(filter, &vnic->filter, next) {
3361 if (filter->filter_type ==
3362 HWRM_CFA_NTUPLE_FILTER) {
3364 bnxt_hwrm_clear_ntuple_filter(bp,
3366 STAILQ_REMOVE(&vnic->filter, filter,
3367 bnxt_filter_info, next);
3372 case RTE_ETH_FILTER_UPDATE:
3373 case RTE_ETH_FILTER_STATS:
3374 case RTE_ETH_FILTER_INFO:
3375 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3378 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3385 bnxt_free_filter(bp, filter);
3390 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3391 enum rte_filter_type filter_type,
3392 enum rte_filter_op filter_op, void *arg)
3394 struct bnxt *bp = dev->data->dev_private;
3400 if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3401 struct bnxt_representor *vfr = dev->data->dev_private;
3402 bp = vfr->parent_dev->data->dev_private;
3403 /* parent is deleted while children are still valid */
3405 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n",
3413 ret = is_bnxt_in_error(bp);
3417 switch (filter_type) {
3418 case RTE_ETH_FILTER_TUNNEL:
3420 "filter type: %d: To be implemented\n", filter_type);
3422 case RTE_ETH_FILTER_FDIR:
3423 ret = bnxt_fdir_filter(dev, filter_op, arg);
3425 case RTE_ETH_FILTER_GENERIC:
3426 if (filter_op != RTE_ETH_FILTER_GET)
3429 /* PMD supports thread-safe flow operations. rte_flow API
3430 * functions can avoid mutex for multi-thread safety.
3432 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3434 if (BNXT_TRUFLOW_EN(bp))
3435 *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3437 *(const void **)arg = &bnxt_flow_ops;
3441 "Filter type (%d) not supported", filter_type);
3448 static const uint32_t *
3449 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3451 static const uint32_t ptypes[] = {
3452 RTE_PTYPE_L2_ETHER_VLAN,
3453 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3454 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3458 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3459 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3460 RTE_PTYPE_INNER_L4_ICMP,
3461 RTE_PTYPE_INNER_L4_TCP,
3462 RTE_PTYPE_INNER_L4_UDP,
3466 if (!dev->rx_pkt_burst)
3472 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3475 uint32_t reg_base = *reg_arr & 0xfffff000;
3479 for (i = 0; i < count; i++) {
3480 if ((reg_arr[i] & 0xfffff000) != reg_base)
3483 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3484 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3488 static int bnxt_map_ptp_regs(struct bnxt *bp)
3490 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3494 reg_arr = ptp->rx_regs;
3495 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3499 reg_arr = ptp->tx_regs;
3500 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3504 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3505 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3507 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3508 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3513 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3515 rte_write32(0, (uint8_t *)bp->bar0 +
3516 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3517 rte_write32(0, (uint8_t *)bp->bar0 +
3518 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3521 static uint64_t bnxt_cc_read(struct bnxt *bp)
3525 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3526 BNXT_GRCPF_REG_SYNC_TIME));
3527 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3528 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3532 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3534 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3537 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3538 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3539 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3542 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3543 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3544 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3545 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3546 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3547 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3552 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3554 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3555 struct bnxt_pf_info *pf = bp->pf;
3562 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3563 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3564 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3567 port_id = pf->port_id;
3568 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3569 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3571 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3572 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3573 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3574 /* bnxt_clr_rx_ts(bp); TBD */
3578 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3579 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3580 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3581 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3587 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3590 struct bnxt *bp = dev->data->dev_private;
3591 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3596 ns = rte_timespec_to_ns(ts);
3597 /* Set the timecounters to a new value. */
3604 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3606 struct bnxt *bp = dev->data->dev_private;
3607 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3608 uint64_t ns, systime_cycles = 0;
3614 if (BNXT_CHIP_THOR(bp))
3615 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3618 systime_cycles = bnxt_cc_read(bp);
3620 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3621 *ts = rte_ns_to_timespec(ns);
3626 bnxt_timesync_enable(struct rte_eth_dev *dev)
3628 struct bnxt *bp = dev->data->dev_private;
3629 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3637 ptp->tx_tstamp_en = 1;
3638 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3640 rc = bnxt_hwrm_ptp_cfg(bp);
3644 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3645 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3646 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3648 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3649 ptp->tc.cc_shift = shift;
3650 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3652 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3653 ptp->rx_tstamp_tc.cc_shift = shift;
3654 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3656 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3657 ptp->tx_tstamp_tc.cc_shift = shift;
3658 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3660 if (!BNXT_CHIP_THOR(bp))
3661 bnxt_map_ptp_regs(bp);
3667 bnxt_timesync_disable(struct rte_eth_dev *dev)
3669 struct bnxt *bp = dev->data->dev_private;
3670 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3676 ptp->tx_tstamp_en = 0;
3679 bnxt_hwrm_ptp_cfg(bp);
3681 if (!BNXT_CHIP_THOR(bp))
3682 bnxt_unmap_ptp_regs(bp);
3688 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3689 struct timespec *timestamp,
3690 uint32_t flags __rte_unused)
3692 struct bnxt *bp = dev->data->dev_private;
3693 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3694 uint64_t rx_tstamp_cycles = 0;
3700 if (BNXT_CHIP_THOR(bp))
3701 rx_tstamp_cycles = ptp->rx_timestamp;
3703 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3705 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3706 *timestamp = rte_ns_to_timespec(ns);
3711 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3712 struct timespec *timestamp)
3714 struct bnxt *bp = dev->data->dev_private;
3715 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3716 uint64_t tx_tstamp_cycles = 0;
3723 if (BNXT_CHIP_THOR(bp))
3724 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3727 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3729 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3730 *timestamp = rte_ns_to_timespec(ns);
3736 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3738 struct bnxt *bp = dev->data->dev_private;
3739 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3744 ptp->tc.nsec += delta;
3750 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3752 struct bnxt *bp = dev->data->dev_private;
3754 uint32_t dir_entries;
3755 uint32_t entry_length;
3757 rc = is_bnxt_in_error(bp);
3761 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3762 bp->pdev->addr.domain, bp->pdev->addr.bus,
3763 bp->pdev->addr.devid, bp->pdev->addr.function);
3765 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3769 return dir_entries * entry_length;
3773 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3774 struct rte_dev_eeprom_info *in_eeprom)
3776 struct bnxt *bp = dev->data->dev_private;
3781 rc = is_bnxt_in_error(bp);
3785 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3786 bp->pdev->addr.domain, bp->pdev->addr.bus,
3787 bp->pdev->addr.devid, bp->pdev->addr.function,
3788 in_eeprom->offset, in_eeprom->length);
3790 if (in_eeprom->offset == 0) /* special offset value to get directory */
3791 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3794 index = in_eeprom->offset >> 24;
3795 offset = in_eeprom->offset & 0xffffff;
3798 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3799 in_eeprom->length, in_eeprom->data);
3804 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3807 case BNX_DIR_TYPE_CHIMP_PATCH:
3808 case BNX_DIR_TYPE_BOOTCODE:
3809 case BNX_DIR_TYPE_BOOTCODE_2:
3810 case BNX_DIR_TYPE_APE_FW:
3811 case BNX_DIR_TYPE_APE_PATCH:
3812 case BNX_DIR_TYPE_KONG_FW:
3813 case BNX_DIR_TYPE_KONG_PATCH:
3814 case BNX_DIR_TYPE_BONO_FW:
3815 case BNX_DIR_TYPE_BONO_PATCH:
3823 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3826 case BNX_DIR_TYPE_AVS:
3827 case BNX_DIR_TYPE_EXP_ROM_MBA:
3828 case BNX_DIR_TYPE_PCIE:
3829 case BNX_DIR_TYPE_TSCF_UCODE:
3830 case BNX_DIR_TYPE_EXT_PHY:
3831 case BNX_DIR_TYPE_CCM:
3832 case BNX_DIR_TYPE_ISCSI_BOOT:
3833 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3834 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3842 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3844 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3845 bnxt_dir_type_is_other_exec_format(dir_type);
3849 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3850 struct rte_dev_eeprom_info *in_eeprom)
3852 struct bnxt *bp = dev->data->dev_private;
3853 uint8_t index, dir_op;
3854 uint16_t type, ext, ordinal, attr;
3857 rc = is_bnxt_in_error(bp);
3861 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3862 bp->pdev->addr.domain, bp->pdev->addr.bus,
3863 bp->pdev->addr.devid, bp->pdev->addr.function,
3864 in_eeprom->offset, in_eeprom->length);
3867 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3871 type = in_eeprom->magic >> 16;
3873 if (type == 0xffff) { /* special value for directory operations */
3874 index = in_eeprom->magic & 0xff;
3875 dir_op = in_eeprom->magic >> 8;
3879 case 0x0e: /* erase */
3880 if (in_eeprom->offset != ~in_eeprom->magic)
3882 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3888 /* Create or re-write an NVM item: */
3889 if (bnxt_dir_type_is_executable(type) == true)
3891 ext = in_eeprom->magic & 0xffff;
3892 ordinal = in_eeprom->offset >> 16;
3893 attr = in_eeprom->offset & 0xffff;
3895 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3896 in_eeprom->data, in_eeprom->length);
3903 static const struct eth_dev_ops bnxt_dev_ops = {
3904 .dev_infos_get = bnxt_dev_info_get_op,
3905 .dev_close = bnxt_dev_close_op,
3906 .dev_configure = bnxt_dev_configure_op,
3907 .dev_start = bnxt_dev_start_op,
3908 .dev_stop = bnxt_dev_stop_op,
3909 .dev_set_link_up = bnxt_dev_set_link_up_op,
3910 .dev_set_link_down = bnxt_dev_set_link_down_op,
3911 .stats_get = bnxt_stats_get_op,
3912 .stats_reset = bnxt_stats_reset_op,
3913 .rx_queue_setup = bnxt_rx_queue_setup_op,
3914 .rx_queue_release = bnxt_rx_queue_release_op,
3915 .tx_queue_setup = bnxt_tx_queue_setup_op,
3916 .tx_queue_release = bnxt_tx_queue_release_op,
3917 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3918 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3919 .reta_update = bnxt_reta_update_op,
3920 .reta_query = bnxt_reta_query_op,
3921 .rss_hash_update = bnxt_rss_hash_update_op,
3922 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3923 .link_update = bnxt_link_update_op,
3924 .promiscuous_enable = bnxt_promiscuous_enable_op,
3925 .promiscuous_disable = bnxt_promiscuous_disable_op,
3926 .allmulticast_enable = bnxt_allmulticast_enable_op,
3927 .allmulticast_disable = bnxt_allmulticast_disable_op,
3928 .mac_addr_add = bnxt_mac_addr_add_op,
3929 .mac_addr_remove = bnxt_mac_addr_remove_op,
3930 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3931 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3932 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3933 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3934 .vlan_filter_set = bnxt_vlan_filter_set_op,
3935 .vlan_offload_set = bnxt_vlan_offload_set_op,
3936 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3937 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3938 .mtu_set = bnxt_mtu_set_op,
3939 .mac_addr_set = bnxt_set_default_mac_addr_op,
3940 .xstats_get = bnxt_dev_xstats_get_op,
3941 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3942 .xstats_reset = bnxt_dev_xstats_reset_op,
3943 .fw_version_get = bnxt_fw_version_get,
3944 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3945 .rxq_info_get = bnxt_rxq_info_get_op,
3946 .txq_info_get = bnxt_txq_info_get_op,
3947 .rx_burst_mode_get = bnxt_rx_burst_mode_get,
3948 .tx_burst_mode_get = bnxt_tx_burst_mode_get,
3949 .dev_led_on = bnxt_dev_led_on_op,
3950 .dev_led_off = bnxt_dev_led_off_op,
3951 .rx_queue_start = bnxt_rx_queue_start,
3952 .rx_queue_stop = bnxt_rx_queue_stop,
3953 .tx_queue_start = bnxt_tx_queue_start,
3954 .tx_queue_stop = bnxt_tx_queue_stop,
3955 .filter_ctrl = bnxt_filter_ctrl_op,
3956 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3957 .get_eeprom_length = bnxt_get_eeprom_length_op,
3958 .get_eeprom = bnxt_get_eeprom_op,
3959 .set_eeprom = bnxt_set_eeprom_op,
3960 .timesync_enable = bnxt_timesync_enable,
3961 .timesync_disable = bnxt_timesync_disable,
3962 .timesync_read_time = bnxt_timesync_read_time,
3963 .timesync_write_time = bnxt_timesync_write_time,
3964 .timesync_adjust_time = bnxt_timesync_adjust_time,
3965 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3966 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3969 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3973 /* Only pre-map the reset GRC registers using window 3 */
3974 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3975 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3977 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3982 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3984 struct bnxt_error_recovery_info *info = bp->recovery_info;
3985 uint32_t reg_base = 0xffffffff;
3988 /* Only pre-map the monitoring GRC registers using window 2 */
3989 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3990 uint32_t reg = info->status_regs[i];
3992 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3995 if (reg_base == 0xffffffff)
3996 reg_base = reg & 0xfffff000;
3997 if ((reg & 0xfffff000) != reg_base)
4000 /* Use mask 0xffc as the Lower 2 bits indicates
4001 * address space location
4003 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4007 if (reg_base == 0xffffffff)
4010 rte_write32(reg_base, (uint8_t *)bp->bar0 +
4011 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4016 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4018 struct bnxt_error_recovery_info *info = bp->recovery_info;
4019 uint32_t delay = info->delay_after_reset[index];
4020 uint32_t val = info->reset_reg_val[index];
4021 uint32_t reg = info->reset_reg[index];
4022 uint32_t type, offset;
4024 type = BNXT_FW_STATUS_REG_TYPE(reg);
4025 offset = BNXT_FW_STATUS_REG_OFF(reg);
4028 case BNXT_FW_STATUS_REG_TYPE_CFG:
4029 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4031 case BNXT_FW_STATUS_REG_TYPE_GRC:
4032 offset = bnxt_map_reset_regs(bp, offset);
4033 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4035 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4036 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4039 /* wait on a specific interval of time until core reset is complete */
4041 rte_delay_ms(delay);
4044 static void bnxt_dev_cleanup(struct bnxt *bp)
4046 bp->eth_dev->data->dev_link.link_status = 0;
4047 bp->link_info->link_up = 0;
4048 if (bp->eth_dev->data->dev_started)
4049 bnxt_dev_stop_op(bp->eth_dev);
4051 bnxt_uninit_resources(bp, true);
4054 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4056 struct rte_eth_dev *dev = bp->eth_dev;
4057 struct rte_vlan_filter_conf *vfc;
4061 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4062 vfc = &dev->data->vlan_filter_conf;
4063 vidx = vlan_id / 64;
4064 vbit = vlan_id % 64;
4066 /* Each bit corresponds to a VLAN id */
4067 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4068 rc = bnxt_add_vlan_filter(bp, vlan_id);
4077 static int bnxt_restore_mac_filters(struct bnxt *bp)
4079 struct rte_eth_dev *dev = bp->eth_dev;
4080 struct rte_eth_dev_info dev_info;
4081 struct rte_ether_addr *addr;
4087 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4090 rc = bnxt_dev_info_get_op(dev, &dev_info);
4094 /* replay MAC address configuration */
4095 for (i = 1; i < dev_info.max_mac_addrs; i++) {
4096 addr = &dev->data->mac_addrs[i];
4098 /* skip zero address */
4099 if (rte_is_zero_ether_addr(addr))
4103 pool_mask = dev->data->mac_pool_sel[i];
4106 if (pool_mask & 1ULL) {
4107 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4113 } while (pool_mask);
4119 static int bnxt_restore_filters(struct bnxt *bp)
4121 struct rte_eth_dev *dev = bp->eth_dev;
4124 if (dev->data->all_multicast) {
4125 ret = bnxt_allmulticast_enable_op(dev);
4129 if (dev->data->promiscuous) {
4130 ret = bnxt_promiscuous_enable_op(dev);
4135 ret = bnxt_restore_mac_filters(bp);
4139 ret = bnxt_restore_vlan_filters(bp);
4140 /* TODO restore other filters as well */
4144 static void bnxt_dev_recover(void *arg)
4146 struct bnxt *bp = arg;
4147 int timeout = bp->fw_reset_max_msecs;
4150 /* Clear Error flag so that device re-init should happen */
4151 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4154 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4157 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4158 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4159 } while (rc && timeout);
4162 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4166 rc = bnxt_init_resources(bp, true);
4169 "Failed to initialize resources after reset\n");
4172 /* clear reset flag as the device is initialized now */
4173 bp->flags &= ~BNXT_FLAG_FW_RESET;
4175 rc = bnxt_dev_start_op(bp->eth_dev);
4177 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4181 rc = bnxt_restore_filters(bp);
4185 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4188 bnxt_dev_stop_op(bp->eth_dev);
4190 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4191 bnxt_uninit_resources(bp, false);
4192 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4195 void bnxt_dev_reset_and_resume(void *arg)
4197 struct bnxt *bp = arg;
4200 bnxt_dev_cleanup(bp);
4202 bnxt_wait_for_device_shutdown(bp);
4204 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4205 bnxt_dev_recover, (void *)bp);
4207 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4210 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4212 struct bnxt_error_recovery_info *info = bp->recovery_info;
4213 uint32_t reg = info->status_regs[index];
4214 uint32_t type, offset, val = 0;
4216 type = BNXT_FW_STATUS_REG_TYPE(reg);
4217 offset = BNXT_FW_STATUS_REG_OFF(reg);
4220 case BNXT_FW_STATUS_REG_TYPE_CFG:
4221 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4223 case BNXT_FW_STATUS_REG_TYPE_GRC:
4224 offset = info->mapped_status_regs[index];
4226 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4227 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4235 static int bnxt_fw_reset_all(struct bnxt *bp)
4237 struct bnxt_error_recovery_info *info = bp->recovery_info;
4241 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4242 /* Reset through master function driver */
4243 for (i = 0; i < info->reg_array_cnt; i++)
4244 bnxt_write_fw_reset_reg(bp, i);
4245 /* Wait for time specified by FW after triggering reset */
4246 rte_delay_ms(info->master_func_wait_period_after_reset);
4247 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4248 /* Reset with the help of Kong processor */
4249 rc = bnxt_hwrm_fw_reset(bp);
4251 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4257 static void bnxt_fw_reset_cb(void *arg)
4259 struct bnxt *bp = arg;
4260 struct bnxt_error_recovery_info *info = bp->recovery_info;
4263 /* Only Master function can do FW reset */
4264 if (bnxt_is_master_func(bp) &&
4265 bnxt_is_recovery_enabled(bp)) {
4266 rc = bnxt_fw_reset_all(bp);
4268 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4273 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4274 * EXCEPTION_FATAL_ASYNC event to all the functions
4275 * (including MASTER FUNC). After receiving this Async, all the active
4276 * drivers should treat this case as FW initiated recovery
4278 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4279 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4280 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4282 /* To recover from error */
4283 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4288 /* Driver should poll FW heartbeat, reset_counter with the frequency
4289 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4290 * When the driver detects heartbeat stop or change in reset_counter,
4291 * it has to trigger a reset to recover from the error condition.
4292 * A “master PF” is the function who will have the privilege to
4293 * initiate the chimp reset. The master PF will be elected by the
4294 * firmware and will be notified through async message.
4296 static void bnxt_check_fw_health(void *arg)
4298 struct bnxt *bp = arg;
4299 struct bnxt_error_recovery_info *info = bp->recovery_info;
4300 uint32_t val = 0, wait_msec;
4302 if (!info || !bnxt_is_recovery_enabled(bp) ||
4303 is_bnxt_in_error(bp))
4306 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4307 if (val == info->last_heart_beat)
4310 info->last_heart_beat = val;
4312 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4313 if (val != info->last_reset_counter)
4316 info->last_reset_counter = val;
4318 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4319 bnxt_check_fw_health, (void *)bp);
4323 /* Stop DMA to/from device */
4324 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4325 bp->flags |= BNXT_FLAG_FW_RESET;
4327 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4329 if (bnxt_is_master_func(bp))
4330 wait_msec = info->master_func_wait_period;
4332 wait_msec = info->normal_func_wait_period;
4334 rte_eal_alarm_set(US_PER_MS * wait_msec,
4335 bnxt_fw_reset_cb, (void *)bp);
4338 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4340 uint32_t polling_freq;
4342 pthread_mutex_lock(&bp->health_check_lock);
4344 if (!bnxt_is_recovery_enabled(bp))
4347 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4350 polling_freq = bp->recovery_info->driver_polling_freq;
4352 rte_eal_alarm_set(US_PER_MS * polling_freq,
4353 bnxt_check_fw_health, (void *)bp);
4354 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4357 pthread_mutex_unlock(&bp->health_check_lock);
4360 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4362 if (!bnxt_is_recovery_enabled(bp))
4365 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4366 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4369 static bool bnxt_vf_pciid(uint16_t device_id)
4371 switch (device_id) {
4372 case BROADCOM_DEV_ID_57304_VF:
4373 case BROADCOM_DEV_ID_57406_VF:
4374 case BROADCOM_DEV_ID_5731X_VF:
4375 case BROADCOM_DEV_ID_5741X_VF:
4376 case BROADCOM_DEV_ID_57414_VF:
4377 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4378 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4379 case BROADCOM_DEV_ID_58802_VF:
4380 case BROADCOM_DEV_ID_57500_VF1:
4381 case BROADCOM_DEV_ID_57500_VF2:
4389 static bool bnxt_thor_device(uint16_t device_id)
4391 switch (device_id) {
4392 case BROADCOM_DEV_ID_57508:
4393 case BROADCOM_DEV_ID_57504:
4394 case BROADCOM_DEV_ID_57502:
4395 case BROADCOM_DEV_ID_57508_MF1:
4396 case BROADCOM_DEV_ID_57504_MF1:
4397 case BROADCOM_DEV_ID_57502_MF1:
4398 case BROADCOM_DEV_ID_57508_MF2:
4399 case BROADCOM_DEV_ID_57504_MF2:
4400 case BROADCOM_DEV_ID_57502_MF2:
4401 case BROADCOM_DEV_ID_57500_VF1:
4402 case BROADCOM_DEV_ID_57500_VF2:
4410 bool bnxt_stratus_device(struct bnxt *bp)
4412 uint16_t device_id = bp->pdev->id.device_id;
4414 switch (device_id) {
4415 case BROADCOM_DEV_ID_STRATUS_NIC:
4416 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4417 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4425 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4427 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4428 struct bnxt *bp = eth_dev->data->dev_private;
4430 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4431 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4432 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4433 if (!bp->bar0 || !bp->doorbell_base) {
4434 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4438 bp->eth_dev = eth_dev;
4444 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4445 struct bnxt_ctx_pg_info *ctx_pg,
4450 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4451 const struct rte_memzone *mz = NULL;
4452 char mz_name[RTE_MEMZONE_NAMESIZE];
4453 rte_iova_t mz_phys_addr;
4454 uint64_t valid_bits = 0;
4461 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4463 rmem->page_size = BNXT_PAGE_SIZE;
4464 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4465 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4466 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4468 valid_bits = PTU_PTE_VALID;
4470 if (rmem->nr_pages > 1) {
4471 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4472 "bnxt_ctx_pg_tbl%s_%x_%d",
4473 suffix, idx, bp->eth_dev->data->port_id);
4474 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4475 mz = rte_memzone_lookup(mz_name);
4477 mz = rte_memzone_reserve_aligned(mz_name,
4481 RTE_MEMZONE_SIZE_HINT_ONLY |
4482 RTE_MEMZONE_IOVA_CONTIG,
4488 memset(mz->addr, 0, mz->len);
4489 mz_phys_addr = mz->iova;
4491 rmem->pg_tbl = mz->addr;
4492 rmem->pg_tbl_map = mz_phys_addr;
4493 rmem->pg_tbl_mz = mz;
4496 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4497 suffix, idx, bp->eth_dev->data->port_id);
4498 mz = rte_memzone_lookup(mz_name);
4500 mz = rte_memzone_reserve_aligned(mz_name,
4504 RTE_MEMZONE_SIZE_HINT_ONLY |
4505 RTE_MEMZONE_IOVA_CONTIG,
4511 memset(mz->addr, 0, mz->len);
4512 mz_phys_addr = mz->iova;
4514 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4515 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4516 rmem->dma_arr[i] = mz_phys_addr + sz;
4518 if (rmem->nr_pages > 1) {
4519 if (i == rmem->nr_pages - 2 &&
4520 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4521 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4522 else if (i == rmem->nr_pages - 1 &&
4523 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4524 valid_bits |= PTU_PTE_LAST;
4526 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4532 if (rmem->vmem_size)
4533 rmem->vmem = (void **)mz->addr;
4534 rmem->dma_arr[0] = mz_phys_addr;
4538 static void bnxt_free_ctx_mem(struct bnxt *bp)
4542 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4545 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4546 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4547 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4548 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4549 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4550 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4551 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4552 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4553 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4554 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4555 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4557 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4558 if (bp->ctx->tqm_mem[i])
4559 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4566 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4568 #define min_t(type, x, y) ({ \
4569 type __min1 = (x); \
4570 type __min2 = (y); \
4571 __min1 < __min2 ? __min1 : __min2; })
4573 #define max_t(type, x, y) ({ \
4574 type __max1 = (x); \
4575 type __max2 = (y); \
4576 __max1 > __max2 ? __max1 : __max2; })
4578 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4580 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4582 struct bnxt_ctx_pg_info *ctx_pg;
4583 struct bnxt_ctx_mem_info *ctx;
4584 uint32_t mem_size, ena, entries;
4585 uint32_t entries_sp, min;
4588 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4590 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4594 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4597 ctx_pg = &ctx->qp_mem;
4598 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4599 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4600 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4604 ctx_pg = &ctx->srq_mem;
4605 ctx_pg->entries = ctx->srq_max_l2_entries;
4606 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4607 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4611 ctx_pg = &ctx->cq_mem;
4612 ctx_pg->entries = ctx->cq_max_l2_entries;
4613 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4614 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4618 ctx_pg = &ctx->vnic_mem;
4619 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4620 ctx->vnic_max_ring_table_entries;
4621 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4622 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4626 ctx_pg = &ctx->stat_mem;
4627 ctx_pg->entries = ctx->stat_max_entries;
4628 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4629 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4633 min = ctx->tqm_min_entries_per_ring;
4635 entries_sp = ctx->qp_max_l2_entries +
4636 ctx->vnic_max_vnic_entries +
4637 2 * ctx->qp_min_qp1_entries + min;
4638 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4640 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4641 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4642 entries = clamp_t(uint32_t, entries, min,
4643 ctx->tqm_max_entries_per_ring);
4644 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4645 ctx_pg = ctx->tqm_mem[i];
4646 ctx_pg->entries = i ? entries : entries_sp;
4647 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4648 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4651 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4654 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4655 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4658 "Failed to configure context mem: rc = %d\n", rc);
4660 ctx->flags |= BNXT_CTX_FLAG_INITED;
4665 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4667 struct rte_pci_device *pci_dev = bp->pdev;
4668 char mz_name[RTE_MEMZONE_NAMESIZE];
4669 const struct rte_memzone *mz = NULL;
4670 uint32_t total_alloc_len;
4671 rte_iova_t mz_phys_addr;
4673 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4676 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4677 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4678 pci_dev->addr.bus, pci_dev->addr.devid,
4679 pci_dev->addr.function, "rx_port_stats");
4680 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4681 mz = rte_memzone_lookup(mz_name);
4683 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4684 sizeof(struct rx_port_stats_ext) + 512);
4686 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4689 RTE_MEMZONE_SIZE_HINT_ONLY |
4690 RTE_MEMZONE_IOVA_CONTIG);
4694 memset(mz->addr, 0, mz->len);
4695 mz_phys_addr = mz->iova;
4697 bp->rx_mem_zone = (const void *)mz;
4698 bp->hw_rx_port_stats = mz->addr;
4699 bp->hw_rx_port_stats_map = mz_phys_addr;
4701 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4702 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4703 pci_dev->addr.bus, pci_dev->addr.devid,
4704 pci_dev->addr.function, "tx_port_stats");
4705 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4706 mz = rte_memzone_lookup(mz_name);
4708 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4709 sizeof(struct tx_port_stats_ext) + 512);
4711 mz = rte_memzone_reserve(mz_name,
4715 RTE_MEMZONE_SIZE_HINT_ONLY |
4716 RTE_MEMZONE_IOVA_CONTIG);
4720 memset(mz->addr, 0, mz->len);
4721 mz_phys_addr = mz->iova;
4723 bp->tx_mem_zone = (const void *)mz;
4724 bp->hw_tx_port_stats = mz->addr;
4725 bp->hw_tx_port_stats_map = mz_phys_addr;
4726 bp->flags |= BNXT_FLAG_PORT_STATS;
4728 /* Display extended statistics if FW supports it */
4729 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4730 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4731 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4734 bp->hw_rx_port_stats_ext = (void *)
4735 ((uint8_t *)bp->hw_rx_port_stats +
4736 sizeof(struct rx_port_stats));
4737 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4738 sizeof(struct rx_port_stats);
4739 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4741 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4742 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4743 bp->hw_tx_port_stats_ext = (void *)
4744 ((uint8_t *)bp->hw_tx_port_stats +
4745 sizeof(struct tx_port_stats));
4746 bp->hw_tx_port_stats_ext_map =
4747 bp->hw_tx_port_stats_map +
4748 sizeof(struct tx_port_stats);
4749 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4755 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4757 struct bnxt *bp = eth_dev->data->dev_private;
4760 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4761 RTE_ETHER_ADDR_LEN *
4764 if (eth_dev->data->mac_addrs == NULL) {
4765 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4769 if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4773 /* Generate a random MAC address, if none was assigned by PF */
4774 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4775 bnxt_eth_hw_addr_random(bp->mac_addr);
4777 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4778 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4779 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4781 rc = bnxt_hwrm_set_mac(bp);
4786 /* Copy the permanent MAC from the FUNC_QCAPS response */
4787 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4792 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4796 /* MAC is already configured in FW */
4797 if (BNXT_HAS_DFLT_MAC_SET(bp))
4800 /* Restore the old MAC configured */
4801 rc = bnxt_hwrm_set_mac(bp);
4803 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4808 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4813 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
4815 if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
4816 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
4817 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
4818 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
4819 BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
4820 BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
4824 bnxt_get_svif(uint16_t port_id, bool func_svif,
4825 enum bnxt_ulp_intf_type type)
4827 struct rte_eth_dev *eth_dev;
4830 eth_dev = &rte_eth_devices[port_id];
4831 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4832 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4836 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4839 eth_dev = vfr->parent_dev;
4842 bp = eth_dev->data->dev_private;
4844 return func_svif ? bp->func_svif : bp->port_svif;
4848 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
4850 struct rte_eth_dev *eth_dev;
4851 struct bnxt_vnic_info *vnic;
4854 eth_dev = &rte_eth_devices[port];
4855 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4856 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4860 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4861 return vfr->dflt_vnic_id;
4863 eth_dev = vfr->parent_dev;
4866 bp = eth_dev->data->dev_private;
4868 vnic = BNXT_GET_DEFAULT_VNIC(bp);
4870 return vnic->fw_vnic_id;
4874 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
4876 struct rte_eth_dev *eth_dev;
4879 eth_dev = &rte_eth_devices[port];
4880 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4881 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4885 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4888 eth_dev = vfr->parent_dev;
4891 bp = eth_dev->data->dev_private;
4896 enum bnxt_ulp_intf_type
4897 bnxt_get_interface_type(uint16_t port)
4899 struct rte_eth_dev *eth_dev;
4902 eth_dev = &rte_eth_devices[port];
4903 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
4904 return BNXT_ULP_INTF_TYPE_VF_REP;
4906 bp = eth_dev->data->dev_private;
4908 return BNXT_ULP_INTF_TYPE_PF;
4909 else if (BNXT_VF_IS_TRUSTED(bp))
4910 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
4911 else if (BNXT_VF(bp))
4912 return BNXT_ULP_INTF_TYPE_VF;
4914 return BNXT_ULP_INTF_TYPE_INVALID;
4918 bnxt_get_phy_port_id(uint16_t port_id)
4920 struct bnxt_representor *vfr;
4921 struct rte_eth_dev *eth_dev;
4924 eth_dev = &rte_eth_devices[port_id];
4925 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4926 vfr = eth_dev->data->dev_private;
4930 eth_dev = vfr->parent_dev;
4933 bp = eth_dev->data->dev_private;
4935 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
4939 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
4941 struct rte_eth_dev *eth_dev;
4944 eth_dev = &rte_eth_devices[port_id];
4945 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4946 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4950 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4951 return vfr->fw_fid - 1;
4953 eth_dev = vfr->parent_dev;
4956 bp = eth_dev->data->dev_private;
4958 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
4962 bnxt_get_vport(uint16_t port_id)
4964 return (1 << bnxt_get_phy_port_id(port_id));
4967 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
4969 struct bnxt_error_recovery_info *info = bp->recovery_info;
4972 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
4973 memset(info, 0, sizeof(*info));
4977 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4980 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4983 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4985 bp->recovery_info = info;
4988 static void bnxt_check_fw_status(struct bnxt *bp)
4992 if (!(bp->recovery_info &&
4993 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
4996 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
4997 if (fw_status != BNXT_FW_STATUS_HEALTHY)
4998 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5002 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5004 struct bnxt_error_recovery_info *info = bp->recovery_info;
5005 uint32_t status_loc;
5008 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5009 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5010 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5011 BNXT_GRCP_WINDOW_2_BASE +
5012 offsetof(struct hcomm_status,
5014 /* If the signature is absent, then FW does not support this feature */
5015 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5016 HCOMM_STATUS_SIGNATURE_VAL)
5020 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5024 bp->recovery_info = info;
5026 memset(info, 0, sizeof(*info));
5029 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5030 BNXT_GRCP_WINDOW_2_BASE +
5031 offsetof(struct hcomm_status,
5034 /* Only pre-map the FW health status GRC register */
5035 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5038 info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5039 info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5040 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5042 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5043 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5045 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5050 static int bnxt_init_fw(struct bnxt *bp)
5057 rc = bnxt_map_hcomm_fw_status_reg(bp);
5061 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5063 bnxt_check_fw_status(bp);
5067 rc = bnxt_hwrm_func_reset(bp);
5071 rc = bnxt_hwrm_vnic_qcaps(bp);
5075 rc = bnxt_hwrm_queue_qportcfg(bp);
5079 /* Get the MAX capabilities for this function.
5080 * This function also allocates context memory for TQM rings and
5081 * informs the firmware about this allocated backing store memory.
5083 rc = bnxt_hwrm_func_qcaps(bp);
5087 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5091 bnxt_hwrm_port_mac_qcfg(bp);
5093 bnxt_hwrm_parent_pf_qcfg(bp);
5095 bnxt_hwrm_port_phy_qcaps(bp);
5097 bnxt_alloc_error_recovery_info(bp);
5098 /* Get the adapter error recovery support info */
5099 rc = bnxt_hwrm_error_recovery_qcfg(bp);
5101 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5103 bnxt_hwrm_port_led_qcaps(bp);
5109 bnxt_init_locks(struct bnxt *bp)
5113 err = pthread_mutex_init(&bp->flow_lock, NULL);
5115 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5119 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5121 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5123 err = pthread_mutex_init(&bp->health_check_lock, NULL);
5125 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5129 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5133 rc = bnxt_init_fw(bp);
5137 if (!reconfig_dev) {
5138 rc = bnxt_setup_mac_addr(bp->eth_dev);
5142 rc = bnxt_restore_dflt_mac(bp);
5147 bnxt_config_vf_req_fwd(bp);
5149 rc = bnxt_hwrm_func_driver_register(bp);
5151 PMD_DRV_LOG(ERR, "Failed to register driver");
5156 if (bp->pdev->max_vfs) {
5157 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5159 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5163 rc = bnxt_hwrm_allocate_pf_only(bp);
5166 "Failed to allocate PF resources");
5172 rc = bnxt_alloc_mem(bp, reconfig_dev);
5176 rc = bnxt_setup_int(bp);
5180 rc = bnxt_request_int(bp);
5184 rc = bnxt_init_ctx_mem(bp);
5186 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5190 rc = bnxt_init_locks(bp);
5198 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5199 const char *value, void *opaque_arg)
5201 struct bnxt *bp = opaque_arg;
5202 unsigned long truflow;
5205 if (!value || !opaque_arg) {
5207 "Invalid parameter passed to truflow devargs.\n");
5211 truflow = strtoul(value, &end, 10);
5212 if (end == NULL || *end != '\0' ||
5213 (truflow == ULONG_MAX && errno == ERANGE)) {
5215 "Invalid parameter passed to truflow devargs.\n");
5219 if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5221 "Invalid value passed to truflow devargs.\n");
5226 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5227 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5229 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
5230 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
5237 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5238 const char *value, void *opaque_arg)
5240 struct bnxt *bp = opaque_arg;
5241 unsigned long flow_xstat;
5244 if (!value || !opaque_arg) {
5246 "Invalid parameter passed to flow_xstat devarg.\n");
5250 flow_xstat = strtoul(value, &end, 10);
5251 if (end == NULL || *end != '\0' ||
5252 (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5254 "Invalid parameter passed to flow_xstat devarg.\n");
5258 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5260 "Invalid value passed to flow_xstat devarg.\n");
5264 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5265 if (BNXT_FLOW_XSTATS_EN(bp))
5266 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5272 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5273 const char *value, void *opaque_arg)
5275 struct bnxt *bp = opaque_arg;
5276 unsigned long max_num_kflows;
5279 if (!value || !opaque_arg) {
5281 "Invalid parameter passed to max_num_kflows devarg.\n");
5285 max_num_kflows = strtoul(value, &end, 10);
5286 if (end == NULL || *end != '\0' ||
5287 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5289 "Invalid parameter passed to max_num_kflows devarg.\n");
5293 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5295 "Invalid value passed to max_num_kflows devarg.\n");
5299 bp->max_num_kflows = max_num_kflows;
5300 if (bp->max_num_kflows)
5301 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5308 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5309 const char *value, void *opaque_arg)
5311 struct bnxt_representor *vfr_bp = opaque_arg;
5312 unsigned long rep_is_pf;
5315 if (!value || !opaque_arg) {
5317 "Invalid parameter passed to rep_is_pf devargs.\n");
5321 rep_is_pf = strtoul(value, &end, 10);
5322 if (end == NULL || *end != '\0' ||
5323 (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5325 "Invalid parameter passed to rep_is_pf devargs.\n");
5329 if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5331 "Invalid value passed to rep_is_pf devargs.\n");
5335 vfr_bp->flags |= rep_is_pf;
5336 if (BNXT_REP_PF(vfr_bp))
5337 PMD_DRV_LOG(INFO, "PF representor\n");
5339 PMD_DRV_LOG(INFO, "VF representor\n");
5345 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5346 const char *value, void *opaque_arg)
5348 struct bnxt_representor *vfr_bp = opaque_arg;
5349 unsigned long rep_based_pf;
5352 if (!value || !opaque_arg) {
5354 "Invalid parameter passed to rep_based_pf "
5359 rep_based_pf = strtoul(value, &end, 10);
5360 if (end == NULL || *end != '\0' ||
5361 (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5363 "Invalid parameter passed to rep_based_pf "
5368 if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5370 "Invalid value passed to rep_based_pf devargs.\n");
5374 vfr_bp->rep_based_pf = rep_based_pf;
5375 vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
5377 PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5383 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5384 const char *value, void *opaque_arg)
5386 struct bnxt_representor *vfr_bp = opaque_arg;
5387 unsigned long rep_q_r2f;
5390 if (!value || !opaque_arg) {
5392 "Invalid parameter passed to rep_q_r2f "
5397 rep_q_r2f = strtoul(value, &end, 10);
5398 if (end == NULL || *end != '\0' ||
5399 (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5401 "Invalid parameter passed to rep_q_r2f "
5406 if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5408 "Invalid value passed to rep_q_r2f devargs.\n");
5412 vfr_bp->rep_q_r2f = rep_q_r2f;
5413 vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5414 PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5420 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5421 const char *value, void *opaque_arg)
5423 struct bnxt_representor *vfr_bp = opaque_arg;
5424 unsigned long rep_q_f2r;
5427 if (!value || !opaque_arg) {
5429 "Invalid parameter passed to rep_q_f2r "
5434 rep_q_f2r = strtoul(value, &end, 10);
5435 if (end == NULL || *end != '\0' ||
5436 (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5438 "Invalid parameter passed to rep_q_f2r "
5443 if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5445 "Invalid value passed to rep_q_f2r devargs.\n");
5449 vfr_bp->rep_q_f2r = rep_q_f2r;
5450 vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5451 PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5457 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5458 const char *value, void *opaque_arg)
5460 struct bnxt_representor *vfr_bp = opaque_arg;
5461 unsigned long rep_fc_r2f;
5464 if (!value || !opaque_arg) {
5466 "Invalid parameter passed to rep_fc_r2f "
5471 rep_fc_r2f = strtoul(value, &end, 10);
5472 if (end == NULL || *end != '\0' ||
5473 (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5475 "Invalid parameter passed to rep_fc_r2f "
5480 if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5482 "Invalid value passed to rep_fc_r2f devargs.\n");
5486 vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5487 vfr_bp->rep_fc_r2f = rep_fc_r2f;
5488 PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5494 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5495 const char *value, void *opaque_arg)
5497 struct bnxt_representor *vfr_bp = opaque_arg;
5498 unsigned long rep_fc_f2r;
5501 if (!value || !opaque_arg) {
5503 "Invalid parameter passed to rep_fc_f2r "
5508 rep_fc_f2r = strtoul(value, &end, 10);
5509 if (end == NULL || *end != '\0' ||
5510 (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5512 "Invalid parameter passed to rep_fc_f2r "
5517 if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5519 "Invalid value passed to rep_fc_f2r devargs.\n");
5523 vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5524 vfr_bp->rep_fc_f2r = rep_fc_f2r;
5525 PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5531 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5533 struct rte_kvargs *kvlist;
5535 if (devargs == NULL)
5538 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5543 * Handler for "truflow" devarg.
5544 * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1"
5546 rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5547 bnxt_parse_devarg_truflow, bp);
5550 * Handler for "flow_xstat" devarg.
5551 * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1"
5553 rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5554 bnxt_parse_devarg_flow_xstat, bp);
5557 * Handler for "max_num_kflows" devarg.
5558 * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32"
5560 rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5561 bnxt_parse_devarg_max_num_kflows, bp);
5563 rte_kvargs_free(kvlist);
5566 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5570 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5571 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5574 "Failed to alloc switch domain: %d\n", rc);
5577 "Switch domain allocated %d\n",
5578 bp->switch_domain_id);
5585 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5587 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5588 static int version_printed;
5592 if (version_printed++ == 0)
5593 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5595 eth_dev->dev_ops = &bnxt_dev_ops;
5596 eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5597 eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5598 eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5599 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5600 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5603 * For secondary processes, we don't initialise any further
5604 * as primary has already done this work.
5606 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5609 rte_eth_copy_pci_info(eth_dev, pci_dev);
5610 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
5612 bp = eth_dev->data->dev_private;
5614 /* Parse dev arguments passed on when starting the DPDK application. */
5615 bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5617 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5619 if (bnxt_vf_pciid(pci_dev->id.device_id))
5620 bp->flags |= BNXT_FLAG_VF;
5622 if (bnxt_thor_device(pci_dev->id.device_id))
5623 bp->flags |= BNXT_FLAG_THOR_CHIP;
5625 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5626 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5627 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5628 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5629 bp->flags |= BNXT_FLAG_STINGRAY;
5631 if (BNXT_TRUFLOW_EN(bp)) {
5632 /* extra mbuf field is required to store CFA code from mark */
5633 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5634 .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5635 .size = sizeof(bnxt_cfa_code_dynfield_t),
5636 .align = __alignof__(bnxt_cfa_code_dynfield_t),
5638 bnxt_cfa_code_dynfield_offset =
5639 rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5640 if (bnxt_cfa_code_dynfield_offset < 0) {
5642 "Failed to register mbuf field for TruFlow mark\n");
5647 rc = bnxt_init_board(eth_dev);
5650 "Failed to initialize board rc: %x\n", rc);
5654 rc = bnxt_alloc_pf_info(bp);
5658 rc = bnxt_alloc_link_info(bp);
5662 rc = bnxt_alloc_parent_info(bp);
5666 rc = bnxt_alloc_hwrm_resources(bp);
5669 "Failed to allocate hwrm resource rc: %x\n", rc);
5672 rc = bnxt_alloc_leds_info(bp);
5676 rc = bnxt_alloc_cos_queues(bp);
5680 rc = bnxt_init_resources(bp, false);
5684 rc = bnxt_alloc_stats_mem(bp);
5688 bnxt_alloc_switch_domain(bp);
5691 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5692 pci_dev->mem_resource[0].phys_addr,
5693 pci_dev->mem_resource[0].addr);
5698 bnxt_dev_uninit(eth_dev);
5703 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5712 ctx->dma = RTE_BAD_IOVA;
5713 ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5716 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5718 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5719 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5720 bp->flow_stat->rx_fc_out_tbl.ctx_id,
5721 bp->flow_stat->max_fc,
5724 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5725 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5726 bp->flow_stat->tx_fc_out_tbl.ctx_id,
5727 bp->flow_stat->max_fc,
5730 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5731 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5732 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5734 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5735 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5736 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5738 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5739 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5740 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5742 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5743 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5744 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5747 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5749 bnxt_unregister_fc_ctx_mem(bp);
5751 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5752 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5753 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5754 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5757 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5759 if (BNXT_FLOW_XSTATS_EN(bp))
5760 bnxt_uninit_fc_ctx_mem(bp);
5764 bnxt_free_error_recovery_info(struct bnxt *bp)
5766 rte_free(bp->recovery_info);
5767 bp->recovery_info = NULL;
5768 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5772 bnxt_uninit_locks(struct bnxt *bp)
5774 pthread_mutex_destroy(&bp->flow_lock);
5775 pthread_mutex_destroy(&bp->def_cp_lock);
5776 pthread_mutex_destroy(&bp->health_check_lock);
5778 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
5779 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
5784 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5789 bnxt_free_mem(bp, reconfig_dev);
5791 bnxt_hwrm_func_buf_unrgtr(bp);
5792 rte_free(bp->pf->vf_req_buf);
5794 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5795 bp->flags &= ~BNXT_FLAG_REGISTERED;
5796 bnxt_free_ctx_mem(bp);
5797 if (!reconfig_dev) {
5798 bnxt_free_hwrm_resources(bp);
5799 bnxt_free_error_recovery_info(bp);
5802 bnxt_uninit_ctx_mem(bp);
5804 bnxt_uninit_locks(bp);
5805 bnxt_free_flow_stats_info(bp);
5806 bnxt_free_rep_info(bp);
5807 rte_free(bp->ptp_cfg);
5813 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5815 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5818 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5820 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5821 bnxt_dev_close_op(eth_dev);
5826 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5828 struct bnxt *bp = eth_dev->data->dev_private;
5829 struct rte_eth_dev *vf_rep_eth_dev;
5835 for (i = 0; i < bp->num_reps; i++) {
5836 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5837 if (!vf_rep_eth_dev)
5839 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
5840 vf_rep_eth_dev->data->port_id);
5841 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
5843 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
5844 eth_dev->data->port_id);
5845 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5850 static void bnxt_free_rep_info(struct bnxt *bp)
5852 rte_free(bp->rep_info);
5853 bp->rep_info = NULL;
5854 rte_free(bp->cfa_code_map);
5855 bp->cfa_code_map = NULL;
5858 static int bnxt_init_rep_info(struct bnxt *bp)
5865 bp->rep_info = rte_zmalloc("bnxt_rep_info",
5866 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5868 if (!bp->rep_info) {
5869 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5872 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5873 sizeof(*bp->cfa_code_map) *
5874 BNXT_MAX_CFA_CODE, 0);
5875 if (!bp->cfa_code_map) {
5876 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5877 bnxt_free_rep_info(bp);
5881 for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5882 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5884 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5886 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5887 bnxt_free_rep_info(bp);
5891 rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
5893 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
5894 bnxt_free_rep_info(bp);
5901 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5902 struct rte_eth_devargs eth_da,
5903 struct rte_eth_dev *backing_eth_dev,
5904 const char *dev_args)
5906 struct rte_eth_dev *vf_rep_eth_dev;
5907 char name[RTE_ETH_NAME_MAX_LEN];
5908 struct bnxt *backing_bp;
5911 struct rte_kvargs *kvlist = NULL;
5913 num_rep = eth_da.nb_representor_ports;
5914 if (num_rep > BNXT_MAX_VF_REPS) {
5915 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5916 num_rep, BNXT_MAX_VF_REPS);
5920 if (num_rep >= RTE_MAX_ETHPORTS) {
5922 "nb_representor_ports = %d > %d MAX ETHPORTS\n",
5923 num_rep, RTE_MAX_ETHPORTS);
5927 backing_bp = backing_eth_dev->data->dev_private;
5929 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
5931 "Not a PF or trusted VF. No Representor support\n");
5932 /* Returning an error is not an option.
5933 * Applications are not handling this correctly
5938 if (bnxt_init_rep_info(backing_bp))
5941 for (i = 0; i < num_rep; i++) {
5942 struct bnxt_representor representor = {
5943 .vf_id = eth_da.representor_ports[i],
5944 .switch_domain_id = backing_bp->switch_domain_id,
5945 .parent_dev = backing_eth_dev
5948 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
5949 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
5950 representor.vf_id, BNXT_MAX_VF_REPS);
5954 /* representor port net_bdf_port */
5955 snprintf(name, sizeof(name), "net_%s_representor_%d",
5956 pci_dev->device.name, eth_da.representor_ports[i]);
5958 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
5961 * Handler for "rep_is_pf" devarg.
5962 * Invoked as for ex: "-w 000:00:0d.0,
5963 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5965 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
5966 bnxt_parse_devarg_rep_is_pf,
5967 (void *)&representor);
5973 * Handler for "rep_based_pf" devarg.
5974 * Invoked as for ex: "-w 000:00:0d.0,
5975 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5977 ret = rte_kvargs_process(kvlist,
5978 BNXT_DEVARG_REP_BASED_PF,
5979 bnxt_parse_devarg_rep_based_pf,
5980 (void *)&representor);
5986 * Handler for "rep_based_pf" devarg.
5987 * Invoked as for ex: "-w 000:00:0d.0,
5988 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5990 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
5991 bnxt_parse_devarg_rep_q_r2f,
5992 (void *)&representor);
5998 * Handler for "rep_based_pf" devarg.
5999 * Invoked as for ex: "-w 000:00:0d.0,
6000 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6002 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
6003 bnxt_parse_devarg_rep_q_f2r,
6004 (void *)&representor);
6010 * Handler for "rep_based_pf" devarg.
6011 * Invoked as for ex: "-w 000:00:0d.0,
6012 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6014 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
6015 bnxt_parse_devarg_rep_fc_r2f,
6016 (void *)&representor);
6022 * Handler for "rep_based_pf" devarg.
6023 * Invoked as for ex: "-w 000:00:0d.0,
6024 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6026 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
6027 bnxt_parse_devarg_rep_fc_f2r,
6028 (void *)&representor);
6035 ret = rte_eth_dev_create(&pci_dev->device, name,
6036 sizeof(struct bnxt_representor),
6038 bnxt_representor_init,
6041 PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6042 "representor %s.", name);
6046 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6047 if (!vf_rep_eth_dev) {
6048 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6049 " for VF-Rep: %s.", name);
6054 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6055 backing_eth_dev->data->port_id);
6056 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6058 backing_bp->num_reps++;
6062 rte_kvargs_free(kvlist);
6066 /* If num_rep > 1, then rollback already created
6067 * ports, since we'll be failing the probe anyway
6070 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6072 rte_kvargs_free(kvlist);
6077 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6078 struct rte_pci_device *pci_dev)
6080 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6081 struct rte_eth_dev *backing_eth_dev;
6085 if (pci_dev->device.devargs) {
6086 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6092 num_rep = eth_da.nb_representor_ports;
6093 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6096 /* We could come here after first level of probe is already invoked
6097 * as part of an application bringup(OVS-DPDK vswitchd), so first check
6098 * for already allocated eth_dev for the backing device (PF/Trusted VF)
6100 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6101 if (backing_eth_dev == NULL) {
6102 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6103 sizeof(struct bnxt),
6104 eth_dev_pci_specific_init, pci_dev,
6105 bnxt_dev_init, NULL);
6107 if (ret || !num_rep)
6110 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6112 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6113 backing_eth_dev->data->port_id);
6118 /* probe representor ports now */
6119 ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev,
6120 pci_dev->device.devargs->args);
6125 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6127 struct rte_eth_dev *eth_dev;
6129 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6131 return 0; /* Invoked typically only by OVS-DPDK, by the
6132 * time it comes here the eth_dev is already
6133 * deleted by rte_eth_dev_close(), so returning
6134 * +ve value will at least help in proper cleanup
6137 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6138 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6139 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6140 return rte_eth_dev_destroy(eth_dev,
6141 bnxt_representor_uninit);
6143 return rte_eth_dev_destroy(eth_dev,
6146 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6150 static struct rte_pci_driver bnxt_rte_pmd = {
6151 .id_table = bnxt_pci_id_map,
6152 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6153 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6156 .probe = bnxt_pci_probe,
6157 .remove = bnxt_pci_remove,
6161 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6163 if (strcmp(dev->device->driver->name, drv->driver.name))
6169 bool is_bnxt_supported(struct rte_eth_dev *dev)
6171 return is_device_supported(dev, &bnxt_rte_pmd);
6174 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
6175 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6176 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6177 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");