1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
20 #include "bnxt_ring.h"
23 #include "bnxt_stats.h"
26 #include "bnxt_vnic.h"
27 #include "hsi_struct_def_dpdk.h"
28 #include "bnxt_nvm_defs.h"
30 #define DRV_MODULE_NAME "bnxt"
31 static const char bnxt_version[] =
32 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
33 int bnxt_logtype_driver;
36 * The set of PCI devices this driver supports
38 static const struct rte_pci_id bnxt_pci_id_map[] = {
39 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
40 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
41 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
42 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
43 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
45 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
47 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
92 { .vendor_id = 0, /* sentinel */ },
95 #define BNXT_ETH_RSS_SUPPORT ( \
97 ETH_RSS_NONFRAG_IPV4_TCP | \
98 ETH_RSS_NONFRAG_IPV4_UDP | \
100 ETH_RSS_NONFRAG_IPV6_TCP | \
101 ETH_RSS_NONFRAG_IPV6_UDP)
103 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
104 DEV_TX_OFFLOAD_IPV4_CKSUM | \
105 DEV_TX_OFFLOAD_TCP_CKSUM | \
106 DEV_TX_OFFLOAD_UDP_CKSUM | \
107 DEV_TX_OFFLOAD_TCP_TSO | \
108 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
109 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
110 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
111 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
112 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
113 DEV_TX_OFFLOAD_QINQ_INSERT | \
114 DEV_TX_OFFLOAD_MULTI_SEGS)
116 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
117 DEV_RX_OFFLOAD_VLAN_STRIP | \
118 DEV_RX_OFFLOAD_IPV4_CKSUM | \
119 DEV_RX_OFFLOAD_UDP_CKSUM | \
120 DEV_RX_OFFLOAD_TCP_CKSUM | \
121 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
122 DEV_RX_OFFLOAD_JUMBO_FRAME | \
123 DEV_RX_OFFLOAD_KEEP_CRC | \
124 DEV_RX_OFFLOAD_VLAN_EXTEND | \
125 DEV_RX_OFFLOAD_TCP_LRO | \
126 DEV_RX_OFFLOAD_SCATTER | \
127 DEV_RX_OFFLOAD_RSS_HASH)
129 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
130 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
131 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
132 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
133 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
134 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
135 static int bnxt_restore_vlan_filters(struct bnxt *bp);
137 int is_bnxt_in_error(struct bnxt *bp)
139 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
141 if (bp->flags & BNXT_FLAG_FW_RESET)
147 /***********************/
150 * High level utility functions
153 uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
155 if (!BNXT_CHIP_THOR(bp))
158 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
159 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
160 BNXT_RSS_ENTRIES_PER_CTX_THOR;
163 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
165 if (!BNXT_CHIP_THOR(bp))
166 return HW_HASH_INDEX_SIZE;
168 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
171 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
173 bnxt_free_filter_mem(bp);
174 bnxt_free_vnic_attributes(bp);
175 bnxt_free_vnic_mem(bp);
177 /* tx/rx rings are configured as part of *_queue_setup callbacks.
178 * If the number of rings change across fw update,
179 * we don't have much choice except to warn the user.
183 bnxt_free_tx_rings(bp);
184 bnxt_free_rx_rings(bp);
186 bnxt_free_async_cp_ring(bp);
187 bnxt_free_rxtx_nq_ring(bp);
189 rte_free(bp->grp_info);
193 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
197 rc = bnxt_alloc_ring_grps(bp);
201 rc = bnxt_alloc_async_ring_struct(bp);
205 rc = bnxt_alloc_vnic_mem(bp);
209 rc = bnxt_alloc_vnic_attributes(bp);
213 rc = bnxt_alloc_filter_mem(bp);
217 rc = bnxt_alloc_async_cp_ring(bp);
221 rc = bnxt_alloc_rxtx_nq_ring(bp);
228 bnxt_free_mem(bp, reconfig);
232 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
234 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
235 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
236 uint64_t rx_offloads = dev_conf->rxmode.offloads;
237 struct bnxt_rx_queue *rxq;
241 rc = bnxt_vnic_grp_alloc(bp, vnic);
245 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
246 vnic_id, vnic, vnic->fw_grp_ids);
248 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
252 /* Alloc RSS context only if RSS mode is enabled */
253 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
254 int j, nr_ctxs = bnxt_rss_ctxts(bp);
257 for (j = 0; j < nr_ctxs; j++) {
258 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
264 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
268 vnic->num_lb_ctxts = nr_ctxs;
272 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
273 * setting is not available at this time, it will not be
274 * configured correctly in the CFA.
276 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
277 vnic->vlan_strip = true;
279 vnic->vlan_strip = false;
281 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
285 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
289 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
290 rxq = bp->eth_dev->data->rx_queues[j];
293 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
294 j, rxq->vnic, rxq->vnic->fw_grp_ids);
296 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
297 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
299 vnic->rx_queue_cnt++;
302 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
304 rc = bnxt_vnic_rss_configure(bp, vnic);
308 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
310 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
311 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
313 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
317 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
322 static int bnxt_init_chip(struct bnxt *bp)
324 struct rte_eth_link new;
325 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
326 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
327 uint32_t intr_vector = 0;
328 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
329 uint32_t vec = BNXT_MISC_VEC_ID;
333 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
334 bp->eth_dev->data->dev_conf.rxmode.offloads |=
335 DEV_RX_OFFLOAD_JUMBO_FRAME;
336 bp->flags |= BNXT_FLAG_JUMBO;
338 bp->eth_dev->data->dev_conf.rxmode.offloads &=
339 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
340 bp->flags &= ~BNXT_FLAG_JUMBO;
343 /* THOR does not support ring groups.
344 * But we will use the array to save RSS context IDs.
346 if (BNXT_CHIP_THOR(bp))
347 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
349 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
351 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
355 rc = bnxt_alloc_hwrm_rings(bp);
357 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
361 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
363 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
367 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
370 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
371 if (bp->rx_cos_queue[i].id != 0xff) {
372 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
376 "Num pools more than FW profile\n");
380 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
386 rc = bnxt_mq_rx_configure(bp);
388 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
392 /* VNIC configuration */
393 for (i = 0; i < bp->nr_vnics; i++) {
394 rc = bnxt_setup_one_vnic(bp, i);
399 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
402 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
406 /* check and configure queue intr-vector mapping */
407 if ((rte_intr_cap_multiple(intr_handle) ||
408 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
409 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
410 intr_vector = bp->eth_dev->data->nb_rx_queues;
411 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
412 if (intr_vector > bp->rx_cp_nr_rings) {
413 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
417 rc = rte_intr_efd_enable(intr_handle, intr_vector);
422 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
423 intr_handle->intr_vec =
424 rte_zmalloc("intr_vec",
425 bp->eth_dev->data->nb_rx_queues *
427 if (intr_handle->intr_vec == NULL) {
428 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
429 " intr_vec", bp->eth_dev->data->nb_rx_queues);
433 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
434 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
435 intr_handle->intr_vec, intr_handle->nb_efd,
436 intr_handle->max_intr);
437 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
439 intr_handle->intr_vec[queue_id] =
440 vec + BNXT_RX_VEC_START;
441 if (vec < base + intr_handle->nb_efd - 1)
446 /* enable uio/vfio intr/eventfd mapping */
447 rc = rte_intr_enable(intr_handle);
448 #ifndef RTE_EXEC_ENV_FREEBSD
449 /* In FreeBSD OS, nic_uio driver does not support interrupts */
454 rc = bnxt_get_hwrm_link_config(bp, &new);
456 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
460 if (!bp->link_info.link_up) {
461 rc = bnxt_set_hwrm_link_config(bp, true);
464 "HWRM link config failure rc: %x\n", rc);
468 bnxt_print_link_info(bp->eth_dev);
470 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
472 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
477 rte_free(intr_handle->intr_vec);
479 rte_intr_efd_disable(intr_handle);
481 /* Some of the error status returned by FW may not be from errno.h */
488 static int bnxt_shutdown_nic(struct bnxt *bp)
490 bnxt_free_all_hwrm_resources(bp);
491 bnxt_free_all_filters(bp);
492 bnxt_free_all_vnics(bp);
497 * Device configuration and status function
500 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
501 struct rte_eth_dev_info *dev_info)
503 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
504 struct bnxt *bp = eth_dev->data->dev_private;
505 uint16_t max_vnics, i, j, vpool, vrxq;
506 unsigned int max_rx_rings;
509 rc = is_bnxt_in_error(bp);
514 dev_info->max_mac_addrs = bp->max_l2_ctx;
515 dev_info->max_hash_mac_addrs = 0;
517 /* PF/VF specifics */
519 dev_info->max_vfs = pdev->max_vfs;
521 max_rx_rings = BNXT_MAX_RINGS(bp);
522 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
523 dev_info->max_rx_queues = max_rx_rings;
524 dev_info->max_tx_queues = max_rx_rings;
525 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
526 dev_info->hash_key_size = 40;
527 max_vnics = bp->max_vnics;
530 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
531 dev_info->max_mtu = BNXT_MAX_MTU;
533 /* Fast path specifics */
534 dev_info->min_rx_bufsize = 1;
535 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
537 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
538 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
539 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
540 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
541 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
544 dev_info->default_rxconf = (struct rte_eth_rxconf) {
550 .rx_free_thresh = 32,
551 /* If no descriptors available, pkts are dropped by default */
555 dev_info->default_txconf = (struct rte_eth_txconf) {
561 .tx_free_thresh = 32,
564 eth_dev->data->dev_conf.intr_conf.lsc = 1;
566 eth_dev->data->dev_conf.intr_conf.rxq = 1;
567 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
568 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
569 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
570 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
575 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
576 * need further investigation.
580 vpool = 64; /* ETH_64_POOLS */
581 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
582 for (i = 0; i < 4; vpool >>= 1, i++) {
583 if (max_vnics > vpool) {
584 for (j = 0; j < 5; vrxq >>= 1, j++) {
585 if (dev_info->max_rx_queues > vrxq) {
591 /* Not enough resources to support VMDq */
595 /* Not enough resources to support VMDq */
599 dev_info->max_vmdq_pools = vpool;
600 dev_info->vmdq_queue_num = vrxq;
602 dev_info->vmdq_pool_base = 0;
603 dev_info->vmdq_queue_base = 0;
608 /* Configure the device based on the configuration provided */
609 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
611 struct bnxt *bp = eth_dev->data->dev_private;
612 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
615 bp->rx_queues = (void *)eth_dev->data->rx_queues;
616 bp->tx_queues = (void *)eth_dev->data->tx_queues;
617 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
618 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
620 rc = is_bnxt_in_error(bp);
624 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
625 rc = bnxt_hwrm_check_vf_rings(bp);
627 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
631 /* If a resource has already been allocated - in this case
632 * it is the async completion ring, free it. Reallocate it after
633 * resource reservation. This will ensure the resource counts
634 * are calculated correctly.
637 pthread_mutex_lock(&bp->def_cp_lock);
639 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
640 bnxt_disable_int(bp);
641 bnxt_free_cp_ring(bp, bp->async_cp_ring);
644 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
646 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
647 pthread_mutex_unlock(&bp->def_cp_lock);
651 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
652 rc = bnxt_alloc_async_cp_ring(bp);
654 pthread_mutex_unlock(&bp->def_cp_lock);
660 pthread_mutex_unlock(&bp->def_cp_lock);
662 /* legacy driver needs to get updated values */
663 rc = bnxt_hwrm_func_qcaps(bp);
665 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
670 /* Inherit new configurations */
671 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
672 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
673 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
674 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
675 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
679 if (BNXT_HAS_RING_GRPS(bp) &&
680 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
683 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
684 bp->max_vnics < eth_dev->data->nb_rx_queues)
687 bp->rx_cp_nr_rings = bp->rx_nr_rings;
688 bp->tx_cp_nr_rings = bp->tx_nr_rings;
690 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
691 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
692 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
694 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
696 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
697 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
699 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
705 "Insufficient resources to support requested config\n");
707 "Num Queues Requested: Tx %d, Rx %d\n",
708 eth_dev->data->nb_tx_queues,
709 eth_dev->data->nb_rx_queues);
711 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
712 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
713 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
717 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
719 struct rte_eth_link *link = ð_dev->data->dev_link;
721 if (link->link_status)
722 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
723 eth_dev->data->port_id,
724 (uint32_t)link->link_speed,
725 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
726 ("full-duplex") : ("half-duplex\n"));
728 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
729 eth_dev->data->port_id);
733 * Determine whether the current configuration requires support for scattered
734 * receive; return 1 if scattered receive is required and 0 if not.
736 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
741 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
744 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
745 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
747 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
748 RTE_PKTMBUF_HEADROOM);
749 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
755 static eth_rx_burst_t
756 bnxt_receive_function(struct rte_eth_dev *eth_dev)
758 struct bnxt *bp = eth_dev->data->dev_private;
761 #ifndef RTE_LIBRTE_IEEE1588
763 * Vector mode receive can be enabled only if scatter rx is not
764 * in use and rx offloads are limited to VLAN stripping and
767 if (!eth_dev->data->scattered_rx &&
768 !(eth_dev->data->dev_conf.rxmode.offloads &
769 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
770 DEV_RX_OFFLOAD_KEEP_CRC |
771 DEV_RX_OFFLOAD_JUMBO_FRAME |
772 DEV_RX_OFFLOAD_IPV4_CKSUM |
773 DEV_RX_OFFLOAD_UDP_CKSUM |
774 DEV_RX_OFFLOAD_TCP_CKSUM |
775 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
776 DEV_RX_OFFLOAD_RSS_HASH |
777 DEV_RX_OFFLOAD_VLAN_FILTER))) {
778 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
779 eth_dev->data->port_id);
780 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
781 return bnxt_recv_pkts_vec;
783 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
784 eth_dev->data->port_id);
786 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
787 eth_dev->data->port_id,
788 eth_dev->data->scattered_rx,
789 eth_dev->data->dev_conf.rxmode.offloads);
792 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
793 return bnxt_recv_pkts;
796 static eth_tx_burst_t
797 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
800 #ifndef RTE_LIBRTE_IEEE1588
802 * Vector mode transmit can be enabled only if not using scatter rx
805 if (!eth_dev->data->scattered_rx &&
806 !eth_dev->data->dev_conf.txmode.offloads) {
807 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
808 eth_dev->data->port_id);
809 return bnxt_xmit_pkts_vec;
811 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
812 eth_dev->data->port_id);
814 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
815 eth_dev->data->port_id,
816 eth_dev->data->scattered_rx,
817 eth_dev->data->dev_conf.txmode.offloads);
820 return bnxt_xmit_pkts;
823 static int bnxt_handle_if_change_status(struct bnxt *bp)
827 /* Since fw has undergone a reset and lost all contexts,
828 * set fatal flag to not issue hwrm during cleanup
830 bp->flags |= BNXT_FLAG_FATAL_ERROR;
831 bnxt_uninit_resources(bp, true);
833 /* clear fatal flag so that re-init happens */
834 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
835 rc = bnxt_init_resources(bp, true);
837 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
842 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
844 struct bnxt *bp = eth_dev->data->dev_private;
845 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
849 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
850 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
854 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
856 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
857 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
860 rc = bnxt_hwrm_if_change(bp, 1);
862 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
863 rc = bnxt_handle_if_change_status(bp);
870 rc = bnxt_init_chip(bp);
874 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
876 bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
879 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
880 vlan_mask |= ETH_VLAN_FILTER_MASK;
881 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
882 vlan_mask |= ETH_VLAN_STRIP_MASK;
883 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
887 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
888 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
890 eth_dev->data->dev_started = 1;
891 pthread_mutex_lock(&bp->def_cp_lock);
892 bnxt_schedule_fw_health_check(bp);
893 pthread_mutex_unlock(&bp->def_cp_lock);
897 bnxt_hwrm_if_change(bp, 0);
898 bnxt_shutdown_nic(bp);
899 bnxt_free_tx_mbufs(bp);
900 bnxt_free_rx_mbufs(bp);
905 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
907 struct bnxt *bp = eth_dev->data->dev_private;
910 if (!bp->link_info.link_up)
911 rc = bnxt_set_hwrm_link_config(bp, true);
913 eth_dev->data->dev_link.link_status = 1;
915 bnxt_print_link_info(eth_dev);
919 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
921 struct bnxt *bp = eth_dev->data->dev_private;
923 eth_dev->data->dev_link.link_status = 0;
924 bnxt_set_hwrm_link_config(bp, false);
925 bp->link_info.link_up = 0;
930 /* Unload the driver, release resources */
931 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
933 struct bnxt *bp = eth_dev->data->dev_private;
934 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
935 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
937 eth_dev->data->dev_started = 0;
938 /* Prevent crashes when queues are still in use */
939 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
940 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
942 bnxt_disable_int(bp);
944 /* disable uio/vfio intr/eventfd mapping */
945 rte_intr_disable(intr_handle);
947 bnxt_cancel_fw_health_check(bp);
949 bnxt_dev_set_link_down_op(eth_dev);
951 /* Wait for link to be reset and the async notification to process.
952 * During reset recovery, there is no need to wait
954 if (!is_bnxt_in_error(bp))
955 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
957 /* Clean queue intr-vector mapping */
958 rte_intr_efd_disable(intr_handle);
959 if (intr_handle->intr_vec != NULL) {
960 rte_free(intr_handle->intr_vec);
961 intr_handle->intr_vec = NULL;
964 bnxt_hwrm_port_clr_stats(bp);
965 bnxt_free_tx_mbufs(bp);
966 bnxt_free_rx_mbufs(bp);
967 /* Process any remaining notifications in default completion queue */
968 bnxt_int_handler(eth_dev);
969 bnxt_shutdown_nic(bp);
970 bnxt_hwrm_if_change(bp, 0);
972 rte_free(bp->mark_table);
973 bp->mark_table = NULL;
975 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
980 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
982 struct bnxt *bp = eth_dev->data->dev_private;
984 if (bp->dev_stopped == 0)
985 bnxt_dev_stop_op(eth_dev);
987 bnxt_uninit_resources(bp, false);
989 eth_dev->dev_ops = NULL;
990 eth_dev->rx_pkt_burst = NULL;
991 eth_dev->tx_pkt_burst = NULL;
993 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
994 bp->tx_mem_zone = NULL;
995 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
996 bp->rx_mem_zone = NULL;
998 rte_free(bp->pf.vf_info);
999 bp->pf.vf_info = NULL;
1001 rte_free(bp->grp_info);
1002 bp->grp_info = NULL;
1005 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1008 struct bnxt *bp = eth_dev->data->dev_private;
1009 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1010 struct bnxt_vnic_info *vnic;
1011 struct bnxt_filter_info *filter, *temp_filter;
1014 if (is_bnxt_in_error(bp))
1018 * Loop through all VNICs from the specified filter flow pools to
1019 * remove the corresponding MAC addr filter
1021 for (i = 0; i < bp->nr_vnics; i++) {
1022 if (!(pool_mask & (1ULL << i)))
1025 vnic = &bp->vnic_info[i];
1026 filter = STAILQ_FIRST(&vnic->filter);
1028 temp_filter = STAILQ_NEXT(filter, next);
1029 if (filter->mac_index == index) {
1030 STAILQ_REMOVE(&vnic->filter, filter,
1031 bnxt_filter_info, next);
1032 bnxt_hwrm_clear_l2_filter(bp, filter);
1033 bnxt_free_filter(bp, filter);
1035 filter = temp_filter;
1040 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1041 struct rte_ether_addr *mac_addr, uint32_t index,
1044 struct bnxt_filter_info *filter;
1047 /* Attach requested MAC address to the new l2_filter */
1048 STAILQ_FOREACH(filter, &vnic->filter, next) {
1049 if (filter->mac_index == index) {
1051 "MAC addr already existed for pool %d\n",
1057 filter = bnxt_alloc_filter(bp);
1059 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1063 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1064 * if the MAC that's been programmed now is a different one, then,
1065 * copy that addr to filter->l2_addr
1068 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1069 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1071 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1073 filter->mac_index = index;
1074 if (filter->mac_index == 0)
1075 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1077 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1079 bnxt_free_filter(bp, filter);
1085 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1086 struct rte_ether_addr *mac_addr,
1087 uint32_t index, uint32_t pool)
1089 struct bnxt *bp = eth_dev->data->dev_private;
1090 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1093 rc = is_bnxt_in_error(bp);
1097 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1098 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1103 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1107 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1112 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1113 bool exp_link_status)
1116 struct bnxt *bp = eth_dev->data->dev_private;
1117 struct rte_eth_link new;
1118 int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1119 BNXT_LINK_DOWN_WAIT_CNT;
1121 rc = is_bnxt_in_error(bp);
1125 memset(&new, 0, sizeof(new));
1127 /* Retrieve link info from hardware */
1128 rc = bnxt_get_hwrm_link_config(bp, &new);
1130 new.link_speed = ETH_LINK_SPEED_100M;
1131 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1133 "Failed to retrieve link rc = 0x%x!\n", rc);
1137 if (!wait_to_complete || new.link_status == exp_link_status)
1140 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1144 /* Timed out or success */
1145 if (new.link_status != eth_dev->data->dev_link.link_status ||
1146 new.link_speed != eth_dev->data->dev_link.link_speed) {
1147 rte_eth_linkstatus_set(eth_dev, &new);
1149 _rte_eth_dev_callback_process(eth_dev,
1150 RTE_ETH_EVENT_INTR_LSC,
1153 bnxt_print_link_info(eth_dev);
1159 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1160 int wait_to_complete)
1162 return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1165 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1167 struct bnxt *bp = eth_dev->data->dev_private;
1168 struct bnxt_vnic_info *vnic;
1172 rc = is_bnxt_in_error(bp);
1176 /* Filter settings will get applied when port is started */
1177 if (bp->dev_stopped == 1)
1180 if (bp->vnic_info == NULL)
1183 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1185 old_flags = vnic->flags;
1186 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1187 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1189 vnic->flags = old_flags;
1194 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1196 struct bnxt *bp = eth_dev->data->dev_private;
1197 struct bnxt_vnic_info *vnic;
1201 rc = is_bnxt_in_error(bp);
1205 /* Filter settings will get applied when port is started */
1206 if (bp->dev_stopped == 1)
1209 if (bp->vnic_info == NULL)
1212 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1214 old_flags = vnic->flags;
1215 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1216 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1218 vnic->flags = old_flags;
1223 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1225 struct bnxt *bp = eth_dev->data->dev_private;
1226 struct bnxt_vnic_info *vnic;
1230 rc = is_bnxt_in_error(bp);
1234 /* Filter settings will get applied when port is started */
1235 if (bp->dev_stopped == 1)
1238 if (bp->vnic_info == NULL)
1241 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1243 old_flags = vnic->flags;
1244 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1245 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1247 vnic->flags = old_flags;
1252 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1254 struct bnxt *bp = eth_dev->data->dev_private;
1255 struct bnxt_vnic_info *vnic;
1259 rc = is_bnxt_in_error(bp);
1263 /* Filter settings will get applied when port is started */
1264 if (bp->dev_stopped == 1)
1267 if (bp->vnic_info == NULL)
1270 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1272 old_flags = vnic->flags;
1273 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1274 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1276 vnic->flags = old_flags;
1281 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1282 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1284 if (qid >= bp->rx_nr_rings)
1287 return bp->eth_dev->data->rx_queues[qid];
1290 /* Return rxq corresponding to a given rss table ring/group ID. */
1291 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1293 struct bnxt_rx_queue *rxq;
1296 if (!BNXT_HAS_RING_GRPS(bp)) {
1297 for (i = 0; i < bp->rx_nr_rings; i++) {
1298 rxq = bp->eth_dev->data->rx_queues[i];
1299 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1303 for (i = 0; i < bp->rx_nr_rings; i++) {
1304 if (bp->grp_info[i].fw_grp_id == fwr)
1309 return INVALID_HW_RING_ID;
1312 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1313 struct rte_eth_rss_reta_entry64 *reta_conf,
1316 struct bnxt *bp = eth_dev->data->dev_private;
1317 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1318 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1319 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1323 rc = is_bnxt_in_error(bp);
1327 if (!vnic->rss_table)
1330 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1333 if (reta_size != tbl_size) {
1334 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1335 "(%d) must equal the size supported by the hardware "
1336 "(%d)\n", reta_size, tbl_size);
1340 for (i = 0; i < reta_size; i++) {
1341 struct bnxt_rx_queue *rxq;
1343 idx = i / RTE_RETA_GROUP_SIZE;
1344 sft = i % RTE_RETA_GROUP_SIZE;
1346 if (!(reta_conf[idx].mask & (1ULL << sft)))
1349 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1351 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1355 if (BNXT_CHIP_THOR(bp)) {
1356 vnic->rss_table[i * 2] =
1357 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1358 vnic->rss_table[i * 2 + 1] =
1359 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1361 vnic->rss_table[i] =
1362 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1366 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1370 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1371 struct rte_eth_rss_reta_entry64 *reta_conf,
1374 struct bnxt *bp = eth_dev->data->dev_private;
1375 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1376 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1377 uint16_t idx, sft, i;
1380 rc = is_bnxt_in_error(bp);
1384 /* Retrieve from the default VNIC */
1387 if (!vnic->rss_table)
1390 if (reta_size != tbl_size) {
1391 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1392 "(%d) must equal the size supported by the hardware "
1393 "(%d)\n", reta_size, tbl_size);
1397 for (idx = 0, i = 0; i < reta_size; i++) {
1398 idx = i / RTE_RETA_GROUP_SIZE;
1399 sft = i % RTE_RETA_GROUP_SIZE;
1401 if (reta_conf[idx].mask & (1ULL << sft)) {
1404 if (BNXT_CHIP_THOR(bp))
1405 qid = bnxt_rss_to_qid(bp,
1406 vnic->rss_table[i * 2]);
1408 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1410 if (qid == INVALID_HW_RING_ID) {
1411 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1414 reta_conf[idx].reta[sft] = qid;
1421 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1422 struct rte_eth_rss_conf *rss_conf)
1424 struct bnxt *bp = eth_dev->data->dev_private;
1425 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1426 struct bnxt_vnic_info *vnic;
1429 rc = is_bnxt_in_error(bp);
1434 * If RSS enablement were different than dev_configure,
1435 * then return -EINVAL
1437 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1438 if (!rss_conf->rss_hf)
1439 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1441 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1445 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1446 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1448 /* Update the default RSS VNIC(s) */
1449 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1450 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1453 * If hashkey is not specified, use the previously configured
1456 if (!rss_conf->rss_key)
1459 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1461 "Invalid hashkey length, should be 16 bytes\n");
1464 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1467 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1471 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1472 struct rte_eth_rss_conf *rss_conf)
1474 struct bnxt *bp = eth_dev->data->dev_private;
1475 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1477 uint32_t hash_types;
1479 rc = is_bnxt_in_error(bp);
1483 /* RSS configuration is the same for all VNICs */
1484 if (vnic && vnic->rss_hash_key) {
1485 if (rss_conf->rss_key) {
1486 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1487 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1488 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1491 hash_types = vnic->hash_type;
1492 rss_conf->rss_hf = 0;
1493 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1494 rss_conf->rss_hf |= ETH_RSS_IPV4;
1495 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1497 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1498 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1500 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1502 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1503 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1505 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1507 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1508 rss_conf->rss_hf |= ETH_RSS_IPV6;
1509 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1511 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1512 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1514 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1516 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1517 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1519 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1523 "Unknwon RSS config from firmware (%08x), RSS disabled",
1528 rss_conf->rss_hf = 0;
1533 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1534 struct rte_eth_fc_conf *fc_conf)
1536 struct bnxt *bp = dev->data->dev_private;
1537 struct rte_eth_link link_info;
1540 rc = is_bnxt_in_error(bp);
1544 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1548 memset(fc_conf, 0, sizeof(*fc_conf));
1549 if (bp->link_info.auto_pause)
1550 fc_conf->autoneg = 1;
1551 switch (bp->link_info.pause) {
1553 fc_conf->mode = RTE_FC_NONE;
1555 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1556 fc_conf->mode = RTE_FC_TX_PAUSE;
1558 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1559 fc_conf->mode = RTE_FC_RX_PAUSE;
1561 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1562 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1563 fc_conf->mode = RTE_FC_FULL;
1569 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1570 struct rte_eth_fc_conf *fc_conf)
1572 struct bnxt *bp = dev->data->dev_private;
1575 rc = is_bnxt_in_error(bp);
1579 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1580 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1584 switch (fc_conf->mode) {
1586 bp->link_info.auto_pause = 0;
1587 bp->link_info.force_pause = 0;
1589 case RTE_FC_RX_PAUSE:
1590 if (fc_conf->autoneg) {
1591 bp->link_info.auto_pause =
1592 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1593 bp->link_info.force_pause = 0;
1595 bp->link_info.auto_pause = 0;
1596 bp->link_info.force_pause =
1597 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1600 case RTE_FC_TX_PAUSE:
1601 if (fc_conf->autoneg) {
1602 bp->link_info.auto_pause =
1603 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1604 bp->link_info.force_pause = 0;
1606 bp->link_info.auto_pause = 0;
1607 bp->link_info.force_pause =
1608 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1612 if (fc_conf->autoneg) {
1613 bp->link_info.auto_pause =
1614 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1615 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1616 bp->link_info.force_pause = 0;
1618 bp->link_info.auto_pause = 0;
1619 bp->link_info.force_pause =
1620 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1621 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1625 return bnxt_set_hwrm_link_config(bp, true);
1628 /* Add UDP tunneling port */
1630 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1631 struct rte_eth_udp_tunnel *udp_tunnel)
1633 struct bnxt *bp = eth_dev->data->dev_private;
1634 uint16_t tunnel_type = 0;
1637 rc = is_bnxt_in_error(bp);
1641 switch (udp_tunnel->prot_type) {
1642 case RTE_TUNNEL_TYPE_VXLAN:
1643 if (bp->vxlan_port_cnt) {
1644 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1645 udp_tunnel->udp_port);
1646 if (bp->vxlan_port != udp_tunnel->udp_port) {
1647 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1650 bp->vxlan_port_cnt++;
1654 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1655 bp->vxlan_port_cnt++;
1657 case RTE_TUNNEL_TYPE_GENEVE:
1658 if (bp->geneve_port_cnt) {
1659 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1660 udp_tunnel->udp_port);
1661 if (bp->geneve_port != udp_tunnel->udp_port) {
1662 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1665 bp->geneve_port_cnt++;
1669 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1670 bp->geneve_port_cnt++;
1673 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1676 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1682 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1683 struct rte_eth_udp_tunnel *udp_tunnel)
1685 struct bnxt *bp = eth_dev->data->dev_private;
1686 uint16_t tunnel_type = 0;
1690 rc = is_bnxt_in_error(bp);
1694 switch (udp_tunnel->prot_type) {
1695 case RTE_TUNNEL_TYPE_VXLAN:
1696 if (!bp->vxlan_port_cnt) {
1697 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1700 if (bp->vxlan_port != udp_tunnel->udp_port) {
1701 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1702 udp_tunnel->udp_port, bp->vxlan_port);
1705 if (--bp->vxlan_port_cnt)
1709 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1710 port = bp->vxlan_fw_dst_port_id;
1712 case RTE_TUNNEL_TYPE_GENEVE:
1713 if (!bp->geneve_port_cnt) {
1714 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1717 if (bp->geneve_port != udp_tunnel->udp_port) {
1718 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1719 udp_tunnel->udp_port, bp->geneve_port);
1722 if (--bp->geneve_port_cnt)
1726 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1727 port = bp->geneve_fw_dst_port_id;
1730 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1734 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1737 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1740 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1741 bp->geneve_port = 0;
1746 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1748 struct bnxt_filter_info *filter;
1749 struct bnxt_vnic_info *vnic;
1751 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1753 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1754 filter = STAILQ_FIRST(&vnic->filter);
1756 /* Search for this matching MAC+VLAN filter */
1757 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
1758 /* Delete the filter */
1759 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1762 STAILQ_REMOVE(&vnic->filter, filter,
1763 bnxt_filter_info, next);
1764 bnxt_free_filter(bp, filter);
1766 "Deleted vlan filter for %d\n",
1770 filter = STAILQ_NEXT(filter, next);
1775 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1777 struct bnxt_filter_info *filter;
1778 struct bnxt_vnic_info *vnic;
1780 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1781 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1782 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1784 /* Implementation notes on the use of VNIC in this command:
1786 * By default, these filters belong to default vnic for the function.
1787 * Once these filters are set up, only destination VNIC can be modified.
1788 * If the destination VNIC is not specified in this command,
1789 * then the HWRM shall only create an l2 context id.
1792 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1793 filter = STAILQ_FIRST(&vnic->filter);
1794 /* Check if the VLAN has already been added */
1796 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
1799 filter = STAILQ_NEXT(filter, next);
1802 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1803 * command to create MAC+VLAN filter with the right flags, enables set.
1805 filter = bnxt_alloc_filter(bp);
1808 "MAC/VLAN filter alloc failed\n");
1811 /* MAC + VLAN ID filter */
1812 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1813 * untagged packets are received
1815 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
1816 * packets and only the programmed vlan's packets are received
1818 filter->l2_ivlan = vlan_id;
1819 filter->l2_ivlan_mask = 0x0FFF;
1820 filter->enables |= en;
1821 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1823 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1825 /* Free the newly allocated filter as we were
1826 * not able to create the filter in hardware.
1828 bnxt_free_filter(bp, filter);
1832 filter->mac_index = 0;
1833 /* Add this new filter to the list */
1835 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1837 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1840 "Added Vlan filter for %d\n", vlan_id);
1844 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1845 uint16_t vlan_id, int on)
1847 struct bnxt *bp = eth_dev->data->dev_private;
1850 rc = is_bnxt_in_error(bp);
1854 /* These operations apply to ALL existing MAC/VLAN filters */
1856 return bnxt_add_vlan_filter(bp, vlan_id);
1858 return bnxt_del_vlan_filter(bp, vlan_id);
1861 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
1862 struct bnxt_vnic_info *vnic)
1864 struct bnxt_filter_info *filter;
1867 filter = STAILQ_FIRST(&vnic->filter);
1869 if (filter->mac_index == 0 &&
1870 !memcmp(filter->l2_addr, bp->mac_addr,
1871 RTE_ETHER_ADDR_LEN)) {
1872 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1874 STAILQ_REMOVE(&vnic->filter, filter,
1875 bnxt_filter_info, next);
1876 bnxt_free_filter(bp, filter);
1880 filter = STAILQ_NEXT(filter, next);
1886 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
1888 struct bnxt_vnic_info *vnic;
1892 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1893 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1894 /* Remove any VLAN filters programmed */
1895 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1896 bnxt_del_vlan_filter(bp, i);
1898 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1902 /* Default filter will allow packets that match the
1903 * dest mac. So, it has to be deleted, otherwise, we
1904 * will endup receiving vlan packets for which the
1905 * filter is not programmed, when hw-vlan-filter
1906 * configuration is ON
1908 bnxt_del_dflt_mac_filter(bp, vnic);
1909 /* This filter will allow only untagged packets */
1910 bnxt_add_vlan_filter(bp, 0);
1912 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1913 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1918 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
1920 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
1924 /* Destroy vnic filters and vnic */
1925 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
1926 DEV_RX_OFFLOAD_VLAN_FILTER) {
1927 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1928 bnxt_del_vlan_filter(bp, i);
1930 bnxt_del_dflt_mac_filter(bp, vnic);
1932 rc = bnxt_hwrm_vnic_free(bp, vnic);
1936 rte_free(vnic->fw_grp_ids);
1937 vnic->fw_grp_ids = NULL;
1943 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
1945 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1948 /* Destroy, recreate and reconfigure the default vnic */
1949 rc = bnxt_free_one_vnic(bp, 0);
1953 /* default vnic 0 */
1954 rc = bnxt_setup_one_vnic(bp, 0);
1958 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
1959 DEV_RX_OFFLOAD_VLAN_FILTER) {
1960 rc = bnxt_add_vlan_filter(bp, 0);
1961 bnxt_restore_vlan_filters(bp);
1963 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1966 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1970 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1971 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1977 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1979 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1980 struct bnxt *bp = dev->data->dev_private;
1983 rc = is_bnxt_in_error(bp);
1987 /* Filter settings will get applied when port is started */
1988 if (bp->dev_stopped == 1)
1991 if (mask & ETH_VLAN_FILTER_MASK) {
1992 /* Enable or disable VLAN filtering */
1993 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
1998 if (mask & ETH_VLAN_STRIP_MASK) {
1999 /* Enable or disable VLAN stripping */
2000 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2005 if (mask & ETH_VLAN_EXTEND_MASK) {
2006 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2007 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2009 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2016 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2019 struct bnxt *bp = dev->data->dev_private;
2020 int qinq = dev->data->dev_conf.rxmode.offloads &
2021 DEV_RX_OFFLOAD_VLAN_EXTEND;
2023 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2024 vlan_type != ETH_VLAN_TYPE_OUTER) {
2026 "Unsupported vlan type.");
2031 "QinQ not enabled. Needs to be ON as we can "
2032 "accelerate only outer vlan\n");
2036 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2038 case RTE_ETHER_TYPE_QINQ:
2040 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2042 case RTE_ETHER_TYPE_VLAN:
2044 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2048 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2052 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2056 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2059 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2062 bp->outer_tpid_bd |= tpid;
2063 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2064 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2066 "Can accelerate only outer vlan in QinQ\n");
2074 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2075 struct rte_ether_addr *addr)
2077 struct bnxt *bp = dev->data->dev_private;
2078 /* Default Filter is tied to VNIC 0 */
2079 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2082 rc = is_bnxt_in_error(bp);
2086 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2089 if (rte_is_zero_ether_addr(addr))
2092 /* Check if the requested MAC is already added */
2093 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2096 /* Destroy filter and re-create it */
2097 bnxt_del_dflt_mac_filter(bp, vnic);
2099 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2100 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2101 /* This filter will allow only untagged packets */
2102 rc = bnxt_add_vlan_filter(bp, 0);
2104 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2107 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2112 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2113 struct rte_ether_addr *mc_addr_set,
2114 uint32_t nb_mc_addr)
2116 struct bnxt *bp = eth_dev->data->dev_private;
2117 char *mc_addr_list = (char *)mc_addr_set;
2118 struct bnxt_vnic_info *vnic;
2119 uint32_t off = 0, i = 0;
2122 rc = is_bnxt_in_error(bp);
2126 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2128 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2129 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2133 /* TODO Check for Duplicate mcast addresses */
2134 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2135 for (i = 0; i < nb_mc_addr; i++) {
2136 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2137 RTE_ETHER_ADDR_LEN);
2138 off += RTE_ETHER_ADDR_LEN;
2141 vnic->mc_addr_cnt = i;
2142 if (vnic->mc_addr_cnt)
2143 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2145 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2148 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2152 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2154 struct bnxt *bp = dev->data->dev_private;
2155 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2156 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2157 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2160 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2161 fw_major, fw_minor, fw_updt);
2163 ret += 1; /* add the size of '\0' */
2164 if (fw_size < (uint32_t)ret)
2171 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2172 struct rte_eth_rxq_info *qinfo)
2174 struct bnxt *bp = dev->data->dev_private;
2175 struct bnxt_rx_queue *rxq;
2177 if (is_bnxt_in_error(bp))
2180 rxq = dev->data->rx_queues[queue_id];
2182 qinfo->mp = rxq->mb_pool;
2183 qinfo->scattered_rx = dev->data->scattered_rx;
2184 qinfo->nb_desc = rxq->nb_rx_desc;
2186 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2187 qinfo->conf.rx_drop_en = 0;
2188 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2192 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2193 struct rte_eth_txq_info *qinfo)
2195 struct bnxt *bp = dev->data->dev_private;
2196 struct bnxt_tx_queue *txq;
2198 if (is_bnxt_in_error(bp))
2201 txq = dev->data->tx_queues[queue_id];
2203 qinfo->nb_desc = txq->nb_tx_desc;
2205 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2206 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2207 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2209 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2210 qinfo->conf.tx_rs_thresh = 0;
2211 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2214 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2216 struct bnxt *bp = eth_dev->data->dev_private;
2217 uint32_t new_pkt_size;
2221 rc = is_bnxt_in_error(bp);
2225 /* Exit if receive queues are not configured yet */
2226 if (!eth_dev->data->nb_rx_queues)
2229 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2230 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2234 * If vector-mode tx/rx is active, disallow any MTU change that would
2235 * require scattered receive support.
2237 if (eth_dev->data->dev_started &&
2238 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2239 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2241 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2243 "MTU change would require scattered rx support. ");
2244 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2249 if (new_mtu > RTE_ETHER_MTU) {
2250 bp->flags |= BNXT_FLAG_JUMBO;
2251 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2252 DEV_RX_OFFLOAD_JUMBO_FRAME;
2254 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2255 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2256 bp->flags &= ~BNXT_FLAG_JUMBO;
2259 /* Is there a change in mtu setting? */
2260 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2263 for (i = 0; i < bp->nr_vnics; i++) {
2264 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2267 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2268 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2272 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2273 size -= RTE_PKTMBUF_HEADROOM;
2275 if (size < new_mtu) {
2276 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2283 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2285 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2291 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2293 struct bnxt *bp = dev->data->dev_private;
2294 uint16_t vlan = bp->vlan;
2297 rc = is_bnxt_in_error(bp);
2301 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2303 "PVID cannot be modified for this function\n");
2306 bp->vlan = on ? pvid : 0;
2308 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2315 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2317 struct bnxt *bp = dev->data->dev_private;
2320 rc = is_bnxt_in_error(bp);
2324 return bnxt_hwrm_port_led_cfg(bp, true);
2328 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2330 struct bnxt *bp = dev->data->dev_private;
2333 rc = is_bnxt_in_error(bp);
2337 return bnxt_hwrm_port_led_cfg(bp, false);
2341 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2343 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2344 uint32_t desc = 0, raw_cons = 0, cons;
2345 struct bnxt_cp_ring_info *cpr;
2346 struct bnxt_rx_queue *rxq;
2347 struct rx_pkt_cmpl *rxcmp;
2350 rc = is_bnxt_in_error(bp);
2354 rxq = dev->data->rx_queues[rx_queue_id];
2356 raw_cons = cpr->cp_raw_cons;
2359 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2360 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2361 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2363 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2375 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2377 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2378 struct bnxt_rx_ring_info *rxr;
2379 struct bnxt_cp_ring_info *cpr;
2380 struct bnxt_sw_rx_bd *rx_buf;
2381 struct rx_pkt_cmpl *rxcmp;
2382 uint32_t cons, cp_cons;
2388 rc = is_bnxt_in_error(rxq->bp);
2395 if (offset >= rxq->nb_rx_desc)
2398 cons = RING_CMP(cpr->cp_ring_struct, offset);
2399 cp_cons = cpr->cp_raw_cons;
2400 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2402 if (cons > cp_cons) {
2403 if (CMPL_VALID(rxcmp, cpr->valid))
2404 return RTE_ETH_RX_DESC_DONE;
2406 if (CMPL_VALID(rxcmp, !cpr->valid))
2407 return RTE_ETH_RX_DESC_DONE;
2409 rx_buf = &rxr->rx_buf_ring[cons];
2410 if (rx_buf->mbuf == NULL)
2411 return RTE_ETH_RX_DESC_UNAVAIL;
2414 return RTE_ETH_RX_DESC_AVAIL;
2418 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2420 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2421 struct bnxt_tx_ring_info *txr;
2422 struct bnxt_cp_ring_info *cpr;
2423 struct bnxt_sw_tx_bd *tx_buf;
2424 struct tx_pkt_cmpl *txcmp;
2425 uint32_t cons, cp_cons;
2431 rc = is_bnxt_in_error(txq->bp);
2438 if (offset >= txq->nb_tx_desc)
2441 cons = RING_CMP(cpr->cp_ring_struct, offset);
2442 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2443 cp_cons = cpr->cp_raw_cons;
2445 if (cons > cp_cons) {
2446 if (CMPL_VALID(txcmp, cpr->valid))
2447 return RTE_ETH_TX_DESC_UNAVAIL;
2449 if (CMPL_VALID(txcmp, !cpr->valid))
2450 return RTE_ETH_TX_DESC_UNAVAIL;
2452 tx_buf = &txr->tx_buf_ring[cons];
2453 if (tx_buf->mbuf == NULL)
2454 return RTE_ETH_TX_DESC_DONE;
2456 return RTE_ETH_TX_DESC_FULL;
2459 static struct bnxt_filter_info *
2460 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2461 struct rte_eth_ethertype_filter *efilter,
2462 struct bnxt_vnic_info *vnic0,
2463 struct bnxt_vnic_info *vnic,
2466 struct bnxt_filter_info *mfilter = NULL;
2470 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2471 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2472 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2473 " ethertype filter.", efilter->ether_type);
2477 if (efilter->queue >= bp->rx_nr_rings) {
2478 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2483 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2484 vnic = &bp->vnic_info[efilter->queue];
2486 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2491 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2492 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2493 if ((!memcmp(efilter->mac_addr.addr_bytes,
2494 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2496 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2497 mfilter->ethertype == efilter->ether_type)) {
2503 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2504 if ((!memcmp(efilter->mac_addr.addr_bytes,
2505 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2506 mfilter->ethertype == efilter->ether_type &&
2508 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2522 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2523 enum rte_filter_op filter_op,
2526 struct bnxt *bp = dev->data->dev_private;
2527 struct rte_eth_ethertype_filter *efilter =
2528 (struct rte_eth_ethertype_filter *)arg;
2529 struct bnxt_filter_info *bfilter, *filter1;
2530 struct bnxt_vnic_info *vnic, *vnic0;
2533 if (filter_op == RTE_ETH_FILTER_NOP)
2537 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2542 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2543 vnic = &bp->vnic_info[efilter->queue];
2545 switch (filter_op) {
2546 case RTE_ETH_FILTER_ADD:
2547 bnxt_match_and_validate_ether_filter(bp, efilter,
2552 bfilter = bnxt_get_unused_filter(bp);
2553 if (bfilter == NULL) {
2555 "Not enough resources for a new filter.\n");
2558 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2559 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2560 RTE_ETHER_ADDR_LEN);
2561 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2562 RTE_ETHER_ADDR_LEN);
2563 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2564 bfilter->ethertype = efilter->ether_type;
2565 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2567 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2568 if (filter1 == NULL) {
2573 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2574 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2576 bfilter->dst_id = vnic->fw_vnic_id;
2578 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2580 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2583 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2586 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2588 case RTE_ETH_FILTER_DELETE:
2589 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2591 if (ret == -EEXIST) {
2592 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2594 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2596 bnxt_free_filter(bp, filter1);
2597 } else if (ret == 0) {
2598 PMD_DRV_LOG(ERR, "No matching filter found\n");
2602 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2608 bnxt_free_filter(bp, bfilter);
2614 parse_ntuple_filter(struct bnxt *bp,
2615 struct rte_eth_ntuple_filter *nfilter,
2616 struct bnxt_filter_info *bfilter)
2620 if (nfilter->queue >= bp->rx_nr_rings) {
2621 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2625 switch (nfilter->dst_port_mask) {
2627 bfilter->dst_port_mask = -1;
2628 bfilter->dst_port = nfilter->dst_port;
2629 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2630 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2633 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2637 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2638 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2640 switch (nfilter->proto_mask) {
2642 if (nfilter->proto == 17) /* IPPROTO_UDP */
2643 bfilter->ip_protocol = 17;
2644 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2645 bfilter->ip_protocol = 6;
2648 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2651 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2655 switch (nfilter->dst_ip_mask) {
2657 bfilter->dst_ipaddr_mask[0] = -1;
2658 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2659 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2660 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2663 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2667 switch (nfilter->src_ip_mask) {
2669 bfilter->src_ipaddr_mask[0] = -1;
2670 bfilter->src_ipaddr[0] = nfilter->src_ip;
2671 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2672 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2675 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2679 switch (nfilter->src_port_mask) {
2681 bfilter->src_port_mask = -1;
2682 bfilter->src_port = nfilter->src_port;
2683 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2684 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2687 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2691 bfilter->enables = en;
2695 static struct bnxt_filter_info*
2696 bnxt_match_ntuple_filter(struct bnxt *bp,
2697 struct bnxt_filter_info *bfilter,
2698 struct bnxt_vnic_info **mvnic)
2700 struct bnxt_filter_info *mfilter = NULL;
2703 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2704 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2705 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2706 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2707 bfilter->src_ipaddr_mask[0] ==
2708 mfilter->src_ipaddr_mask[0] &&
2709 bfilter->src_port == mfilter->src_port &&
2710 bfilter->src_port_mask == mfilter->src_port_mask &&
2711 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2712 bfilter->dst_ipaddr_mask[0] ==
2713 mfilter->dst_ipaddr_mask[0] &&
2714 bfilter->dst_port == mfilter->dst_port &&
2715 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2716 bfilter->flags == mfilter->flags &&
2717 bfilter->enables == mfilter->enables) {
2728 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2729 struct rte_eth_ntuple_filter *nfilter,
2730 enum rte_filter_op filter_op)
2732 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2733 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2736 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2737 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2741 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2742 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2746 bfilter = bnxt_get_unused_filter(bp);
2747 if (bfilter == NULL) {
2749 "Not enough resources for a new filter.\n");
2752 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2756 vnic = &bp->vnic_info[nfilter->queue];
2757 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2758 filter1 = STAILQ_FIRST(&vnic0->filter);
2759 if (filter1 == NULL) {
2764 bfilter->dst_id = vnic->fw_vnic_id;
2765 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2767 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2768 bfilter->ethertype = 0x800;
2769 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2771 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2773 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2774 bfilter->dst_id == mfilter->dst_id) {
2775 PMD_DRV_LOG(ERR, "filter exists.\n");
2778 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2779 bfilter->dst_id != mfilter->dst_id) {
2780 mfilter->dst_id = vnic->fw_vnic_id;
2781 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2782 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2783 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2784 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2785 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2788 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2789 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2794 if (filter_op == RTE_ETH_FILTER_ADD) {
2795 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2796 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2799 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2801 if (mfilter == NULL) {
2802 /* This should not happen. But for Coverity! */
2806 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2808 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2809 bnxt_free_filter(bp, mfilter);
2810 bnxt_free_filter(bp, bfilter);
2815 bnxt_free_filter(bp, bfilter);
2820 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2821 enum rte_filter_op filter_op,
2824 struct bnxt *bp = dev->data->dev_private;
2827 if (filter_op == RTE_ETH_FILTER_NOP)
2831 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2836 switch (filter_op) {
2837 case RTE_ETH_FILTER_ADD:
2838 ret = bnxt_cfg_ntuple_filter(bp,
2839 (struct rte_eth_ntuple_filter *)arg,
2842 case RTE_ETH_FILTER_DELETE:
2843 ret = bnxt_cfg_ntuple_filter(bp,
2844 (struct rte_eth_ntuple_filter *)arg,
2848 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2856 bnxt_parse_fdir_filter(struct bnxt *bp,
2857 struct rte_eth_fdir_filter *fdir,
2858 struct bnxt_filter_info *filter)
2860 enum rte_fdir_mode fdir_mode =
2861 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2862 struct bnxt_vnic_info *vnic0, *vnic;
2863 struct bnxt_filter_info *filter1;
2867 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2870 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2871 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2873 switch (fdir->input.flow_type) {
2874 case RTE_ETH_FLOW_IPV4:
2875 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2877 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2878 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2879 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2880 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2881 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2882 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2883 filter->ip_addr_type =
2884 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2885 filter->src_ipaddr_mask[0] = 0xffffffff;
2886 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2887 filter->dst_ipaddr_mask[0] = 0xffffffff;
2888 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2889 filter->ethertype = 0x800;
2890 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2892 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2893 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2894 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2895 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2896 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2897 filter->dst_port_mask = 0xffff;
2898 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2899 filter->src_port_mask = 0xffff;
2900 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2901 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2902 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2903 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2904 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2905 filter->ip_protocol = 6;
2906 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2907 filter->ip_addr_type =
2908 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2909 filter->src_ipaddr_mask[0] = 0xffffffff;
2910 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2911 filter->dst_ipaddr_mask[0] = 0xffffffff;
2912 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2913 filter->ethertype = 0x800;
2914 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2916 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2917 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2918 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2919 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2920 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2921 filter->dst_port_mask = 0xffff;
2922 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2923 filter->src_port_mask = 0xffff;
2924 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2925 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2926 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2927 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2928 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2929 filter->ip_protocol = 17;
2930 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2931 filter->ip_addr_type =
2932 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2933 filter->src_ipaddr_mask[0] = 0xffffffff;
2934 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2935 filter->dst_ipaddr_mask[0] = 0xffffffff;
2936 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2937 filter->ethertype = 0x800;
2938 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2940 case RTE_ETH_FLOW_IPV6:
2941 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2943 filter->ip_addr_type =
2944 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2945 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2946 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2947 rte_memcpy(filter->src_ipaddr,
2948 fdir->input.flow.ipv6_flow.src_ip, 16);
2949 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2950 rte_memcpy(filter->dst_ipaddr,
2951 fdir->input.flow.ipv6_flow.dst_ip, 16);
2952 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2953 memset(filter->dst_ipaddr_mask, 0xff, 16);
2954 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2955 memset(filter->src_ipaddr_mask, 0xff, 16);
2956 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2957 filter->ethertype = 0x86dd;
2958 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2960 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2961 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2962 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2963 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2964 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2965 filter->dst_port_mask = 0xffff;
2966 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2967 filter->src_port_mask = 0xffff;
2968 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2969 filter->ip_addr_type =
2970 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2971 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2972 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2973 rte_memcpy(filter->src_ipaddr,
2974 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2975 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2976 rte_memcpy(filter->dst_ipaddr,
2977 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2978 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2979 memset(filter->dst_ipaddr_mask, 0xff, 16);
2980 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2981 memset(filter->src_ipaddr_mask, 0xff, 16);
2982 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2983 filter->ethertype = 0x86dd;
2984 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2986 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2987 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2988 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2989 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2990 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2991 filter->dst_port_mask = 0xffff;
2992 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2993 filter->src_port_mask = 0xffff;
2994 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2995 filter->ip_addr_type =
2996 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2997 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2998 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2999 rte_memcpy(filter->src_ipaddr,
3000 fdir->input.flow.udp6_flow.ip.src_ip, 16);
3001 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3002 rte_memcpy(filter->dst_ipaddr,
3003 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3004 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3005 memset(filter->dst_ipaddr_mask, 0xff, 16);
3006 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3007 memset(filter->src_ipaddr_mask, 0xff, 16);
3008 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3009 filter->ethertype = 0x86dd;
3010 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3012 case RTE_ETH_FLOW_L2_PAYLOAD:
3013 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3014 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3016 case RTE_ETH_FLOW_VXLAN:
3017 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3019 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3020 filter->tunnel_type =
3021 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3022 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3024 case RTE_ETH_FLOW_NVGRE:
3025 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3027 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3028 filter->tunnel_type =
3029 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3030 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3032 case RTE_ETH_FLOW_UNKNOWN:
3033 case RTE_ETH_FLOW_RAW:
3034 case RTE_ETH_FLOW_FRAG_IPV4:
3035 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3036 case RTE_ETH_FLOW_FRAG_IPV6:
3037 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3038 case RTE_ETH_FLOW_IPV6_EX:
3039 case RTE_ETH_FLOW_IPV6_TCP_EX:
3040 case RTE_ETH_FLOW_IPV6_UDP_EX:
3041 case RTE_ETH_FLOW_GENEVE:
3047 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3048 vnic = &bp->vnic_info[fdir->action.rx_queue];
3050 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3054 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3055 rte_memcpy(filter->dst_macaddr,
3056 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3057 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3060 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3061 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3062 filter1 = STAILQ_FIRST(&vnic0->filter);
3063 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3065 filter->dst_id = vnic->fw_vnic_id;
3066 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3067 if (filter->dst_macaddr[i] == 0x00)
3068 filter1 = STAILQ_FIRST(&vnic0->filter);
3070 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3073 if (filter1 == NULL)
3076 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3077 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3079 filter->enables = en;
3084 static struct bnxt_filter_info *
3085 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3086 struct bnxt_vnic_info **mvnic)
3088 struct bnxt_filter_info *mf = NULL;
3091 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3092 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3094 STAILQ_FOREACH(mf, &vnic->filter, next) {
3095 if (mf->filter_type == nf->filter_type &&
3096 mf->flags == nf->flags &&
3097 mf->src_port == nf->src_port &&
3098 mf->src_port_mask == nf->src_port_mask &&
3099 mf->dst_port == nf->dst_port &&
3100 mf->dst_port_mask == nf->dst_port_mask &&
3101 mf->ip_protocol == nf->ip_protocol &&
3102 mf->ip_addr_type == nf->ip_addr_type &&
3103 mf->ethertype == nf->ethertype &&
3104 mf->vni == nf->vni &&
3105 mf->tunnel_type == nf->tunnel_type &&
3106 mf->l2_ovlan == nf->l2_ovlan &&
3107 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3108 mf->l2_ivlan == nf->l2_ivlan &&
3109 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3110 !memcmp(mf->l2_addr, nf->l2_addr,
3111 RTE_ETHER_ADDR_LEN) &&
3112 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3113 RTE_ETHER_ADDR_LEN) &&
3114 !memcmp(mf->src_macaddr, nf->src_macaddr,
3115 RTE_ETHER_ADDR_LEN) &&
3116 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3117 RTE_ETHER_ADDR_LEN) &&
3118 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3119 sizeof(nf->src_ipaddr)) &&
3120 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3121 sizeof(nf->src_ipaddr_mask)) &&
3122 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3123 sizeof(nf->dst_ipaddr)) &&
3124 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3125 sizeof(nf->dst_ipaddr_mask))) {
3136 bnxt_fdir_filter(struct rte_eth_dev *dev,
3137 enum rte_filter_op filter_op,
3140 struct bnxt *bp = dev->data->dev_private;
3141 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
3142 struct bnxt_filter_info *filter, *match;
3143 struct bnxt_vnic_info *vnic, *mvnic;
3146 if (filter_op == RTE_ETH_FILTER_NOP)
3149 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3152 switch (filter_op) {
3153 case RTE_ETH_FILTER_ADD:
3154 case RTE_ETH_FILTER_DELETE:
3156 filter = bnxt_get_unused_filter(bp);
3157 if (filter == NULL) {
3159 "Not enough resources for a new flow.\n");
3163 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3166 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3168 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3169 vnic = &bp->vnic_info[0];
3171 vnic = &bp->vnic_info[fdir->action.rx_queue];
3173 match = bnxt_match_fdir(bp, filter, &mvnic);
3174 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3175 if (match->dst_id == vnic->fw_vnic_id) {
3176 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3180 match->dst_id = vnic->fw_vnic_id;
3181 ret = bnxt_hwrm_set_ntuple_filter(bp,
3184 STAILQ_REMOVE(&mvnic->filter, match,
3185 bnxt_filter_info, next);
3186 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3188 "Filter with matching pattern exist\n");
3190 "Updated it to new destination q\n");
3194 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3195 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3200 if (filter_op == RTE_ETH_FILTER_ADD) {
3201 ret = bnxt_hwrm_set_ntuple_filter(bp,
3206 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3208 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3209 STAILQ_REMOVE(&vnic->filter, match,
3210 bnxt_filter_info, next);
3211 bnxt_free_filter(bp, match);
3212 bnxt_free_filter(bp, filter);
3215 case RTE_ETH_FILTER_FLUSH:
3216 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3217 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3219 STAILQ_FOREACH(filter, &vnic->filter, next) {
3220 if (filter->filter_type ==
3221 HWRM_CFA_NTUPLE_FILTER) {
3223 bnxt_hwrm_clear_ntuple_filter(bp,
3225 STAILQ_REMOVE(&vnic->filter, filter,
3226 bnxt_filter_info, next);
3231 case RTE_ETH_FILTER_UPDATE:
3232 case RTE_ETH_FILTER_STATS:
3233 case RTE_ETH_FILTER_INFO:
3234 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3237 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3244 bnxt_free_filter(bp, filter);
3249 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3250 enum rte_filter_type filter_type,
3251 enum rte_filter_op filter_op, void *arg)
3255 ret = is_bnxt_in_error(dev->data->dev_private);
3259 switch (filter_type) {
3260 case RTE_ETH_FILTER_TUNNEL:
3262 "filter type: %d: To be implemented\n", filter_type);
3264 case RTE_ETH_FILTER_FDIR:
3265 ret = bnxt_fdir_filter(dev, filter_op, arg);
3267 case RTE_ETH_FILTER_NTUPLE:
3268 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3270 case RTE_ETH_FILTER_ETHERTYPE:
3271 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3273 case RTE_ETH_FILTER_GENERIC:
3274 if (filter_op != RTE_ETH_FILTER_GET)
3276 *(const void **)arg = &bnxt_flow_ops;
3280 "Filter type (%d) not supported", filter_type);
3287 static const uint32_t *
3288 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3290 static const uint32_t ptypes[] = {
3291 RTE_PTYPE_L2_ETHER_VLAN,
3292 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3293 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3297 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3298 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3299 RTE_PTYPE_INNER_L4_ICMP,
3300 RTE_PTYPE_INNER_L4_TCP,
3301 RTE_PTYPE_INNER_L4_UDP,
3305 if (!dev->rx_pkt_burst)
3311 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3314 uint32_t reg_base = *reg_arr & 0xfffff000;
3318 for (i = 0; i < count; i++) {
3319 if ((reg_arr[i] & 0xfffff000) != reg_base)
3322 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3323 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3327 static int bnxt_map_ptp_regs(struct bnxt *bp)
3329 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3333 reg_arr = ptp->rx_regs;
3334 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3338 reg_arr = ptp->tx_regs;
3339 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3343 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3344 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3346 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3347 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3352 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3354 rte_write32(0, (uint8_t *)bp->bar0 +
3355 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3356 rte_write32(0, (uint8_t *)bp->bar0 +
3357 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3360 static uint64_t bnxt_cc_read(struct bnxt *bp)
3364 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3365 BNXT_GRCPF_REG_SYNC_TIME));
3366 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3367 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3371 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3373 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3376 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3377 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3378 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3381 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3382 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3383 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3384 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3385 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3386 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3391 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3393 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3394 struct bnxt_pf_info *pf = &bp->pf;
3401 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3402 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3403 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3406 port_id = pf->port_id;
3407 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3408 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3410 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3411 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3412 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3413 /* bnxt_clr_rx_ts(bp); TBD */
3417 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3418 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3419 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3420 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3426 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3429 struct bnxt *bp = dev->data->dev_private;
3430 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3435 ns = rte_timespec_to_ns(ts);
3436 /* Set the timecounters to a new value. */
3443 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3445 struct bnxt *bp = dev->data->dev_private;
3446 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3447 uint64_t ns, systime_cycles = 0;
3453 if (BNXT_CHIP_THOR(bp))
3454 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3457 systime_cycles = bnxt_cc_read(bp);
3459 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3460 *ts = rte_ns_to_timespec(ns);
3465 bnxt_timesync_enable(struct rte_eth_dev *dev)
3467 struct bnxt *bp = dev->data->dev_private;
3468 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3476 ptp->tx_tstamp_en = 1;
3477 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3479 rc = bnxt_hwrm_ptp_cfg(bp);
3483 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3484 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3485 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3487 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3488 ptp->tc.cc_shift = shift;
3489 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3491 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3492 ptp->rx_tstamp_tc.cc_shift = shift;
3493 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3495 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3496 ptp->tx_tstamp_tc.cc_shift = shift;
3497 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3499 if (!BNXT_CHIP_THOR(bp))
3500 bnxt_map_ptp_regs(bp);
3506 bnxt_timesync_disable(struct rte_eth_dev *dev)
3508 struct bnxt *bp = dev->data->dev_private;
3509 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3515 ptp->tx_tstamp_en = 0;
3518 bnxt_hwrm_ptp_cfg(bp);
3520 if (!BNXT_CHIP_THOR(bp))
3521 bnxt_unmap_ptp_regs(bp);
3527 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3528 struct timespec *timestamp,
3529 uint32_t flags __rte_unused)
3531 struct bnxt *bp = dev->data->dev_private;
3532 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3533 uint64_t rx_tstamp_cycles = 0;
3539 if (BNXT_CHIP_THOR(bp))
3540 rx_tstamp_cycles = ptp->rx_timestamp;
3542 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3544 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3545 *timestamp = rte_ns_to_timespec(ns);
3550 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3551 struct timespec *timestamp)
3553 struct bnxt *bp = dev->data->dev_private;
3554 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3555 uint64_t tx_tstamp_cycles = 0;
3562 if (BNXT_CHIP_THOR(bp))
3563 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3566 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3568 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3569 *timestamp = rte_ns_to_timespec(ns);
3575 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3577 struct bnxt *bp = dev->data->dev_private;
3578 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3583 ptp->tc.nsec += delta;
3589 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3591 struct bnxt *bp = dev->data->dev_private;
3593 uint32_t dir_entries;
3594 uint32_t entry_length;
3596 rc = is_bnxt_in_error(bp);
3600 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3601 bp->pdev->addr.domain, bp->pdev->addr.bus,
3602 bp->pdev->addr.devid, bp->pdev->addr.function);
3604 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3608 return dir_entries * entry_length;
3612 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3613 struct rte_dev_eeprom_info *in_eeprom)
3615 struct bnxt *bp = dev->data->dev_private;
3620 rc = is_bnxt_in_error(bp);
3624 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3625 bp->pdev->addr.domain, bp->pdev->addr.bus,
3626 bp->pdev->addr.devid, bp->pdev->addr.function,
3627 in_eeprom->offset, in_eeprom->length);
3629 if (in_eeprom->offset == 0) /* special offset value to get directory */
3630 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3633 index = in_eeprom->offset >> 24;
3634 offset = in_eeprom->offset & 0xffffff;
3637 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3638 in_eeprom->length, in_eeprom->data);
3643 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3646 case BNX_DIR_TYPE_CHIMP_PATCH:
3647 case BNX_DIR_TYPE_BOOTCODE:
3648 case BNX_DIR_TYPE_BOOTCODE_2:
3649 case BNX_DIR_TYPE_APE_FW:
3650 case BNX_DIR_TYPE_APE_PATCH:
3651 case BNX_DIR_TYPE_KONG_FW:
3652 case BNX_DIR_TYPE_KONG_PATCH:
3653 case BNX_DIR_TYPE_BONO_FW:
3654 case BNX_DIR_TYPE_BONO_PATCH:
3662 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3665 case BNX_DIR_TYPE_AVS:
3666 case BNX_DIR_TYPE_EXP_ROM_MBA:
3667 case BNX_DIR_TYPE_PCIE:
3668 case BNX_DIR_TYPE_TSCF_UCODE:
3669 case BNX_DIR_TYPE_EXT_PHY:
3670 case BNX_DIR_TYPE_CCM:
3671 case BNX_DIR_TYPE_ISCSI_BOOT:
3672 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3673 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3681 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3683 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3684 bnxt_dir_type_is_other_exec_format(dir_type);
3688 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3689 struct rte_dev_eeprom_info *in_eeprom)
3691 struct bnxt *bp = dev->data->dev_private;
3692 uint8_t index, dir_op;
3693 uint16_t type, ext, ordinal, attr;
3696 rc = is_bnxt_in_error(bp);
3700 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3701 bp->pdev->addr.domain, bp->pdev->addr.bus,
3702 bp->pdev->addr.devid, bp->pdev->addr.function,
3703 in_eeprom->offset, in_eeprom->length);
3706 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3710 type = in_eeprom->magic >> 16;
3712 if (type == 0xffff) { /* special value for directory operations */
3713 index = in_eeprom->magic & 0xff;
3714 dir_op = in_eeprom->magic >> 8;
3718 case 0x0e: /* erase */
3719 if (in_eeprom->offset != ~in_eeprom->magic)
3721 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3727 /* Create or re-write an NVM item: */
3728 if (bnxt_dir_type_is_executable(type) == true)
3730 ext = in_eeprom->magic & 0xffff;
3731 ordinal = in_eeprom->offset >> 16;
3732 attr = in_eeprom->offset & 0xffff;
3734 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3735 in_eeprom->data, in_eeprom->length);
3742 static const struct eth_dev_ops bnxt_dev_ops = {
3743 .dev_infos_get = bnxt_dev_info_get_op,
3744 .dev_close = bnxt_dev_close_op,
3745 .dev_configure = bnxt_dev_configure_op,
3746 .dev_start = bnxt_dev_start_op,
3747 .dev_stop = bnxt_dev_stop_op,
3748 .dev_set_link_up = bnxt_dev_set_link_up_op,
3749 .dev_set_link_down = bnxt_dev_set_link_down_op,
3750 .stats_get = bnxt_stats_get_op,
3751 .stats_reset = bnxt_stats_reset_op,
3752 .rx_queue_setup = bnxt_rx_queue_setup_op,
3753 .rx_queue_release = bnxt_rx_queue_release_op,
3754 .tx_queue_setup = bnxt_tx_queue_setup_op,
3755 .tx_queue_release = bnxt_tx_queue_release_op,
3756 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3757 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3758 .reta_update = bnxt_reta_update_op,
3759 .reta_query = bnxt_reta_query_op,
3760 .rss_hash_update = bnxt_rss_hash_update_op,
3761 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3762 .link_update = bnxt_link_update_op,
3763 .promiscuous_enable = bnxt_promiscuous_enable_op,
3764 .promiscuous_disable = bnxt_promiscuous_disable_op,
3765 .allmulticast_enable = bnxt_allmulticast_enable_op,
3766 .allmulticast_disable = bnxt_allmulticast_disable_op,
3767 .mac_addr_add = bnxt_mac_addr_add_op,
3768 .mac_addr_remove = bnxt_mac_addr_remove_op,
3769 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3770 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3771 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3772 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3773 .vlan_filter_set = bnxt_vlan_filter_set_op,
3774 .vlan_offload_set = bnxt_vlan_offload_set_op,
3775 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3776 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3777 .mtu_set = bnxt_mtu_set_op,
3778 .mac_addr_set = bnxt_set_default_mac_addr_op,
3779 .xstats_get = bnxt_dev_xstats_get_op,
3780 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3781 .xstats_reset = bnxt_dev_xstats_reset_op,
3782 .fw_version_get = bnxt_fw_version_get,
3783 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3784 .rxq_info_get = bnxt_rxq_info_get_op,
3785 .txq_info_get = bnxt_txq_info_get_op,
3786 .dev_led_on = bnxt_dev_led_on_op,
3787 .dev_led_off = bnxt_dev_led_off_op,
3788 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3789 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3790 .rx_queue_count = bnxt_rx_queue_count_op,
3791 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3792 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3793 .rx_queue_start = bnxt_rx_queue_start,
3794 .rx_queue_stop = bnxt_rx_queue_stop,
3795 .tx_queue_start = bnxt_tx_queue_start,
3796 .tx_queue_stop = bnxt_tx_queue_stop,
3797 .filter_ctrl = bnxt_filter_ctrl_op,
3798 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3799 .get_eeprom_length = bnxt_get_eeprom_length_op,
3800 .get_eeprom = bnxt_get_eeprom_op,
3801 .set_eeprom = bnxt_set_eeprom_op,
3802 .timesync_enable = bnxt_timesync_enable,
3803 .timesync_disable = bnxt_timesync_disable,
3804 .timesync_read_time = bnxt_timesync_read_time,
3805 .timesync_write_time = bnxt_timesync_write_time,
3806 .timesync_adjust_time = bnxt_timesync_adjust_time,
3807 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3808 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3811 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3815 /* Only pre-map the reset GRC registers using window 3 */
3816 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3817 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3819 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3824 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3826 struct bnxt_error_recovery_info *info = bp->recovery_info;
3827 uint32_t reg_base = 0xffffffff;
3830 /* Only pre-map the monitoring GRC registers using window 2 */
3831 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3832 uint32_t reg = info->status_regs[i];
3834 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3837 if (reg_base == 0xffffffff)
3838 reg_base = reg & 0xfffff000;
3839 if ((reg & 0xfffff000) != reg_base)
3842 /* Use mask 0xffc as the Lower 2 bits indicates
3843 * address space location
3845 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3849 if (reg_base == 0xffffffff)
3852 rte_write32(reg_base, (uint8_t *)bp->bar0 +
3853 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3858 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3860 struct bnxt_error_recovery_info *info = bp->recovery_info;
3861 uint32_t delay = info->delay_after_reset[index];
3862 uint32_t val = info->reset_reg_val[index];
3863 uint32_t reg = info->reset_reg[index];
3864 uint32_t type, offset;
3866 type = BNXT_FW_STATUS_REG_TYPE(reg);
3867 offset = BNXT_FW_STATUS_REG_OFF(reg);
3870 case BNXT_FW_STATUS_REG_TYPE_CFG:
3871 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3873 case BNXT_FW_STATUS_REG_TYPE_GRC:
3874 offset = bnxt_map_reset_regs(bp, offset);
3875 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3877 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3878 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3881 /* wait on a specific interval of time until core reset is complete */
3883 rte_delay_ms(delay);
3886 static void bnxt_dev_cleanup(struct bnxt *bp)
3888 bnxt_set_hwrm_link_config(bp, false);
3889 bp->link_info.link_up = 0;
3890 if (bp->dev_stopped == 0)
3891 bnxt_dev_stop_op(bp->eth_dev);
3893 bnxt_uninit_resources(bp, true);
3896 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3898 struct rte_eth_dev *dev = bp->eth_dev;
3899 struct rte_vlan_filter_conf *vfc;
3903 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3904 vfc = &dev->data->vlan_filter_conf;
3905 vidx = vlan_id / 64;
3906 vbit = vlan_id % 64;
3908 /* Each bit corresponds to a VLAN id */
3909 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3910 rc = bnxt_add_vlan_filter(bp, vlan_id);
3919 static int bnxt_restore_mac_filters(struct bnxt *bp)
3921 struct rte_eth_dev *dev = bp->eth_dev;
3922 struct rte_eth_dev_info dev_info;
3923 struct rte_ether_addr *addr;
3929 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
3932 rc = bnxt_dev_info_get_op(dev, &dev_info);
3936 /* replay MAC address configuration */
3937 for (i = 1; i < dev_info.max_mac_addrs; i++) {
3938 addr = &dev->data->mac_addrs[i];
3940 /* skip zero address */
3941 if (rte_is_zero_ether_addr(addr))
3945 pool_mask = dev->data->mac_pool_sel[i];
3948 if (pool_mask & 1ULL) {
3949 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3955 } while (pool_mask);
3961 static int bnxt_restore_filters(struct bnxt *bp)
3963 struct rte_eth_dev *dev = bp->eth_dev;
3966 if (dev->data->all_multicast)
3967 ret = bnxt_allmulticast_enable_op(dev);
3968 if (dev->data->promiscuous)
3969 ret = bnxt_promiscuous_enable_op(dev);
3971 ret = bnxt_restore_mac_filters(bp);
3975 ret = bnxt_restore_vlan_filters(bp);
3976 /* TODO restore other filters as well */
3980 static void bnxt_dev_recover(void *arg)
3982 struct bnxt *bp = arg;
3983 int timeout = bp->fw_reset_max_msecs;
3986 /* Clear Error flag so that device re-init should happen */
3987 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3990 rc = bnxt_hwrm_ver_get(bp);
3993 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3994 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3995 } while (rc && timeout);
3998 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4002 rc = bnxt_init_resources(bp, true);
4005 "Failed to initialize resources after reset\n");
4008 /* clear reset flag as the device is initialized now */
4009 bp->flags &= ~BNXT_FLAG_FW_RESET;
4011 rc = bnxt_dev_start_op(bp->eth_dev);
4013 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4017 rc = bnxt_restore_filters(bp);
4021 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4024 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4025 bnxt_uninit_resources(bp, false);
4026 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4029 void bnxt_dev_reset_and_resume(void *arg)
4031 struct bnxt *bp = arg;
4034 bnxt_dev_cleanup(bp);
4036 bnxt_wait_for_device_shutdown(bp);
4038 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4039 bnxt_dev_recover, (void *)bp);
4041 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4044 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4046 struct bnxt_error_recovery_info *info = bp->recovery_info;
4047 uint32_t reg = info->status_regs[index];
4048 uint32_t type, offset, val = 0;
4050 type = BNXT_FW_STATUS_REG_TYPE(reg);
4051 offset = BNXT_FW_STATUS_REG_OFF(reg);
4054 case BNXT_FW_STATUS_REG_TYPE_CFG:
4055 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4057 case BNXT_FW_STATUS_REG_TYPE_GRC:
4058 offset = info->mapped_status_regs[index];
4060 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4061 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4069 static int bnxt_fw_reset_all(struct bnxt *bp)
4071 struct bnxt_error_recovery_info *info = bp->recovery_info;
4075 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4076 /* Reset through master function driver */
4077 for (i = 0; i < info->reg_array_cnt; i++)
4078 bnxt_write_fw_reset_reg(bp, i);
4079 /* Wait for time specified by FW after triggering reset */
4080 rte_delay_ms(info->master_func_wait_period_after_reset);
4081 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4082 /* Reset with the help of Kong processor */
4083 rc = bnxt_hwrm_fw_reset(bp);
4085 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4091 static void bnxt_fw_reset_cb(void *arg)
4093 struct bnxt *bp = arg;
4094 struct bnxt_error_recovery_info *info = bp->recovery_info;
4097 /* Only Master function can do FW reset */
4098 if (bnxt_is_master_func(bp) &&
4099 bnxt_is_recovery_enabled(bp)) {
4100 rc = bnxt_fw_reset_all(bp);
4102 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4107 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4108 * EXCEPTION_FATAL_ASYNC event to all the functions
4109 * (including MASTER FUNC). After receiving this Async, all the active
4110 * drivers should treat this case as FW initiated recovery
4112 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4113 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4114 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4116 /* To recover from error */
4117 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4122 /* Driver should poll FW heartbeat, reset_counter with the frequency
4123 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4124 * When the driver detects heartbeat stop or change in reset_counter,
4125 * it has to trigger a reset to recover from the error condition.
4126 * A “master PF” is the function who will have the privilege to
4127 * initiate the chimp reset. The master PF will be elected by the
4128 * firmware and will be notified through async message.
4130 static void bnxt_check_fw_health(void *arg)
4132 struct bnxt *bp = arg;
4133 struct bnxt_error_recovery_info *info = bp->recovery_info;
4134 uint32_t val = 0, wait_msec;
4136 if (!info || !bnxt_is_recovery_enabled(bp) ||
4137 is_bnxt_in_error(bp))
4140 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4141 if (val == info->last_heart_beat)
4144 info->last_heart_beat = val;
4146 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4147 if (val != info->last_reset_counter)
4150 info->last_reset_counter = val;
4152 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4153 bnxt_check_fw_health, (void *)bp);
4157 /* Stop DMA to/from device */
4158 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4159 bp->flags |= BNXT_FLAG_FW_RESET;
4161 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4163 if (bnxt_is_master_func(bp))
4164 wait_msec = info->master_func_wait_period;
4166 wait_msec = info->normal_func_wait_period;
4168 rte_eal_alarm_set(US_PER_MS * wait_msec,
4169 bnxt_fw_reset_cb, (void *)bp);
4172 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4174 uint32_t polling_freq;
4176 if (!bnxt_is_recovery_enabled(bp))
4179 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4182 polling_freq = bp->recovery_info->driver_polling_freq;
4184 rte_eal_alarm_set(US_PER_MS * polling_freq,
4185 bnxt_check_fw_health, (void *)bp);
4186 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4189 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4191 if (!bnxt_is_recovery_enabled(bp))
4194 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4195 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4198 static bool bnxt_vf_pciid(uint16_t device_id)
4200 switch (device_id) {
4201 case BROADCOM_DEV_ID_57304_VF:
4202 case BROADCOM_DEV_ID_57406_VF:
4203 case BROADCOM_DEV_ID_5731X_VF:
4204 case BROADCOM_DEV_ID_5741X_VF:
4205 case BROADCOM_DEV_ID_57414_VF:
4206 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4207 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4208 case BROADCOM_DEV_ID_58802_VF:
4209 case BROADCOM_DEV_ID_57500_VF1:
4210 case BROADCOM_DEV_ID_57500_VF2:
4218 static bool bnxt_thor_device(uint16_t device_id)
4220 switch (device_id) {
4221 case BROADCOM_DEV_ID_57508:
4222 case BROADCOM_DEV_ID_57504:
4223 case BROADCOM_DEV_ID_57502:
4224 case BROADCOM_DEV_ID_57508_MF1:
4225 case BROADCOM_DEV_ID_57504_MF1:
4226 case BROADCOM_DEV_ID_57502_MF1:
4227 case BROADCOM_DEV_ID_57508_MF2:
4228 case BROADCOM_DEV_ID_57504_MF2:
4229 case BROADCOM_DEV_ID_57502_MF2:
4230 case BROADCOM_DEV_ID_57500_VF1:
4231 case BROADCOM_DEV_ID_57500_VF2:
4239 bool bnxt_stratus_device(struct bnxt *bp)
4241 uint16_t device_id = bp->pdev->id.device_id;
4243 switch (device_id) {
4244 case BROADCOM_DEV_ID_STRATUS_NIC:
4245 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4246 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4254 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4256 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4257 struct bnxt *bp = eth_dev->data->dev_private;
4259 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4260 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4261 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4262 if (!bp->bar0 || !bp->doorbell_base) {
4263 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4267 bp->eth_dev = eth_dev;
4273 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4274 struct bnxt_ctx_pg_info *ctx_pg,
4279 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4280 const struct rte_memzone *mz = NULL;
4281 char mz_name[RTE_MEMZONE_NAMESIZE];
4282 rte_iova_t mz_phys_addr;
4283 uint64_t valid_bits = 0;
4290 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4292 rmem->page_size = BNXT_PAGE_SIZE;
4293 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4294 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4295 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4297 valid_bits = PTU_PTE_VALID;
4299 if (rmem->nr_pages > 1) {
4300 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4301 "bnxt_ctx_pg_tbl%s_%x_%d",
4302 suffix, idx, bp->eth_dev->data->port_id);
4303 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4304 mz = rte_memzone_lookup(mz_name);
4306 mz = rte_memzone_reserve_aligned(mz_name,
4310 RTE_MEMZONE_SIZE_HINT_ONLY |
4311 RTE_MEMZONE_IOVA_CONTIG,
4317 memset(mz->addr, 0, mz->len);
4318 mz_phys_addr = mz->iova;
4320 rmem->pg_tbl = mz->addr;
4321 rmem->pg_tbl_map = mz_phys_addr;
4322 rmem->pg_tbl_mz = mz;
4325 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4326 suffix, idx, bp->eth_dev->data->port_id);
4327 mz = rte_memzone_lookup(mz_name);
4329 mz = rte_memzone_reserve_aligned(mz_name,
4333 RTE_MEMZONE_SIZE_HINT_ONLY |
4334 RTE_MEMZONE_IOVA_CONTIG,
4340 memset(mz->addr, 0, mz->len);
4341 mz_phys_addr = mz->iova;
4343 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4344 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4345 rmem->dma_arr[i] = mz_phys_addr + sz;
4347 if (rmem->nr_pages > 1) {
4348 if (i == rmem->nr_pages - 2 &&
4349 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4350 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4351 else if (i == rmem->nr_pages - 1 &&
4352 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4353 valid_bits |= PTU_PTE_LAST;
4355 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4361 if (rmem->vmem_size)
4362 rmem->vmem = (void **)mz->addr;
4363 rmem->dma_arr[0] = mz_phys_addr;
4367 static void bnxt_free_ctx_mem(struct bnxt *bp)
4371 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4374 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4375 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4376 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4377 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4378 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4379 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4380 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4381 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4382 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4383 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4384 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4386 for (i = 0; i < BNXT_MAX_Q; i++) {
4387 if (bp->ctx->tqm_mem[i])
4388 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4395 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4397 #define min_t(type, x, y) ({ \
4398 type __min1 = (x); \
4399 type __min2 = (y); \
4400 __min1 < __min2 ? __min1 : __min2; })
4402 #define max_t(type, x, y) ({ \
4403 type __max1 = (x); \
4404 type __max2 = (y); \
4405 __max1 > __max2 ? __max1 : __max2; })
4407 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4409 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4411 struct bnxt_ctx_pg_info *ctx_pg;
4412 struct bnxt_ctx_mem_info *ctx;
4413 uint32_t mem_size, ena, entries;
4416 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4418 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4422 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4425 ctx_pg = &ctx->qp_mem;
4426 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4427 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4428 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4432 ctx_pg = &ctx->srq_mem;
4433 ctx_pg->entries = ctx->srq_max_l2_entries;
4434 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4435 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4439 ctx_pg = &ctx->cq_mem;
4440 ctx_pg->entries = ctx->cq_max_l2_entries;
4441 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4442 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4446 ctx_pg = &ctx->vnic_mem;
4447 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4448 ctx->vnic_max_ring_table_entries;
4449 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4450 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4454 ctx_pg = &ctx->stat_mem;
4455 ctx_pg->entries = ctx->stat_max_entries;
4456 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4457 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4461 entries = ctx->qp_max_l2_entries +
4462 ctx->vnic_max_vnic_entries +
4463 ctx->tqm_min_entries_per_ring;
4464 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4465 entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4466 ctx->tqm_max_entries_per_ring);
4467 for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4468 ctx_pg = ctx->tqm_mem[i];
4469 /* use min tqm entries for now. */
4470 ctx_pg->entries = entries;
4471 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4472 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4475 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4478 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4479 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4482 "Failed to configure context mem: rc = %d\n", rc);
4484 ctx->flags |= BNXT_CTX_FLAG_INITED;
4489 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4491 struct rte_pci_device *pci_dev = bp->pdev;
4492 char mz_name[RTE_MEMZONE_NAMESIZE];
4493 const struct rte_memzone *mz = NULL;
4494 uint32_t total_alloc_len;
4495 rte_iova_t mz_phys_addr;
4497 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4500 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4501 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4502 pci_dev->addr.bus, pci_dev->addr.devid,
4503 pci_dev->addr.function, "rx_port_stats");
4504 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4505 mz = rte_memzone_lookup(mz_name);
4507 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4508 sizeof(struct rx_port_stats_ext) + 512);
4510 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4513 RTE_MEMZONE_SIZE_HINT_ONLY |
4514 RTE_MEMZONE_IOVA_CONTIG);
4518 memset(mz->addr, 0, mz->len);
4519 mz_phys_addr = mz->iova;
4521 bp->rx_mem_zone = (const void *)mz;
4522 bp->hw_rx_port_stats = mz->addr;
4523 bp->hw_rx_port_stats_map = mz_phys_addr;
4525 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4526 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4527 pci_dev->addr.bus, pci_dev->addr.devid,
4528 pci_dev->addr.function, "tx_port_stats");
4529 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4530 mz = rte_memzone_lookup(mz_name);
4532 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4533 sizeof(struct tx_port_stats_ext) + 512);
4535 mz = rte_memzone_reserve(mz_name,
4539 RTE_MEMZONE_SIZE_HINT_ONLY |
4540 RTE_MEMZONE_IOVA_CONTIG);
4544 memset(mz->addr, 0, mz->len);
4545 mz_phys_addr = mz->iova;
4547 bp->tx_mem_zone = (const void *)mz;
4548 bp->hw_tx_port_stats = mz->addr;
4549 bp->hw_tx_port_stats_map = mz_phys_addr;
4550 bp->flags |= BNXT_FLAG_PORT_STATS;
4552 /* Display extended statistics if FW supports it */
4553 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4554 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4555 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4558 bp->hw_rx_port_stats_ext = (void *)
4559 ((uint8_t *)bp->hw_rx_port_stats +
4560 sizeof(struct rx_port_stats));
4561 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4562 sizeof(struct rx_port_stats);
4563 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4565 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4566 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4567 bp->hw_tx_port_stats_ext = (void *)
4568 ((uint8_t *)bp->hw_tx_port_stats +
4569 sizeof(struct tx_port_stats));
4570 bp->hw_tx_port_stats_ext_map =
4571 bp->hw_tx_port_stats_map +
4572 sizeof(struct tx_port_stats);
4573 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4579 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4581 struct bnxt *bp = eth_dev->data->dev_private;
4584 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4585 RTE_ETHER_ADDR_LEN *
4588 if (eth_dev->data->mac_addrs == NULL) {
4589 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4593 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4597 /* Generate a random MAC address, if none was assigned by PF */
4598 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4599 bnxt_eth_hw_addr_random(bp->mac_addr);
4601 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4602 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4603 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4605 rc = bnxt_hwrm_set_mac(bp);
4607 memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4608 RTE_ETHER_ADDR_LEN);
4612 /* Copy the permanent MAC from the FUNC_QCAPS response */
4613 memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4614 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4619 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4623 /* MAC is already configured in FW */
4624 if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4627 /* Restore the old MAC configured */
4628 rc = bnxt_hwrm_set_mac(bp);
4630 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4635 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4640 #define ALLOW_FUNC(x) \
4642 uint32_t arg = (x); \
4643 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4644 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4647 /* Forward all requests if firmware is new enough */
4648 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4649 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4650 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4651 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4653 PMD_DRV_LOG(WARNING,
4654 "Firmware too old for VF mailbox functionality\n");
4655 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4659 * The following are used for driver cleanup. If we disallow these,
4660 * VF drivers can't clean up cleanly.
4662 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4663 ALLOW_FUNC(HWRM_VNIC_FREE);
4664 ALLOW_FUNC(HWRM_RING_FREE);
4665 ALLOW_FUNC(HWRM_RING_GRP_FREE);
4666 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4667 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4668 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4669 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4670 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4673 static int bnxt_init_fw(struct bnxt *bp)
4680 rc = bnxt_hwrm_ver_get(bp);
4684 rc = bnxt_hwrm_func_reset(bp);
4688 rc = bnxt_hwrm_vnic_qcaps(bp);
4692 rc = bnxt_hwrm_queue_qportcfg(bp);
4696 /* Get the MAX capabilities for this function.
4697 * This function also allocates context memory for TQM rings and
4698 * informs the firmware about this allocated backing store memory.
4700 rc = bnxt_hwrm_func_qcaps(bp);
4704 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4708 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4712 /* Get the adapter error recovery support info */
4713 rc = bnxt_hwrm_error_recovery_qcfg(bp);
4715 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4717 bnxt_hwrm_port_led_qcaps(bp);
4723 bnxt_init_locks(struct bnxt *bp)
4727 err = pthread_mutex_init(&bp->flow_lock, NULL);
4729 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4733 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4735 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4739 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4743 rc = bnxt_init_fw(bp);
4747 if (!reconfig_dev) {
4748 rc = bnxt_setup_mac_addr(bp->eth_dev);
4752 rc = bnxt_restore_dflt_mac(bp);
4757 bnxt_config_vf_req_fwd(bp);
4759 rc = bnxt_hwrm_func_driver_register(bp);
4761 PMD_DRV_LOG(ERR, "Failed to register driver");
4766 if (bp->pdev->max_vfs) {
4767 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4769 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4773 rc = bnxt_hwrm_allocate_pf_only(bp);
4776 "Failed to allocate PF resources");
4782 rc = bnxt_alloc_mem(bp, reconfig_dev);
4786 rc = bnxt_setup_int(bp);
4790 rc = bnxt_request_int(bp);
4794 rc = bnxt_init_locks(bp);
4802 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4804 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4805 static int version_printed;
4809 if (version_printed++ == 0)
4810 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4812 eth_dev->dev_ops = &bnxt_dev_ops;
4813 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4814 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4817 * For secondary processes, we don't initialise any further
4818 * as primary has already done this work.
4820 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4823 rte_eth_copy_pci_info(eth_dev, pci_dev);
4825 bp = eth_dev->data->dev_private;
4827 bp->dev_stopped = 1;
4828 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
4830 if (bnxt_vf_pciid(pci_dev->id.device_id))
4831 bp->flags |= BNXT_FLAG_VF;
4833 if (bnxt_thor_device(pci_dev->id.device_id))
4834 bp->flags |= BNXT_FLAG_THOR_CHIP;
4836 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4837 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4838 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4839 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4840 bp->flags |= BNXT_FLAG_STINGRAY;
4842 rc = bnxt_init_board(eth_dev);
4845 "Failed to initialize board rc: %x\n", rc);
4849 rc = bnxt_alloc_hwrm_resources(bp);
4852 "Failed to allocate hwrm resource rc: %x\n", rc);
4855 rc = bnxt_init_resources(bp, false);
4859 rc = bnxt_alloc_stats_mem(bp);
4863 /* Pass the information to the rte_eth_dev_close() that it should also
4864 * release the private port resources.
4866 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
4869 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4870 pci_dev->mem_resource[0].phys_addr,
4871 pci_dev->mem_resource[0].addr);
4876 bnxt_dev_uninit(eth_dev);
4881 bnxt_uninit_locks(struct bnxt *bp)
4883 pthread_mutex_destroy(&bp->flow_lock);
4884 pthread_mutex_destroy(&bp->def_cp_lock);
4888 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4893 bnxt_free_mem(bp, reconfig_dev);
4894 bnxt_hwrm_func_buf_unrgtr(bp);
4895 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4896 bp->flags &= ~BNXT_FLAG_REGISTERED;
4897 bnxt_free_ctx_mem(bp);
4898 if (!reconfig_dev) {
4899 bnxt_free_hwrm_resources(bp);
4901 if (bp->recovery_info != NULL) {
4902 rte_free(bp->recovery_info);
4903 bp->recovery_info = NULL;
4907 bnxt_uninit_locks(bp);
4908 rte_free(bp->ptp_cfg);
4914 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4916 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4919 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4921 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
4922 bnxt_dev_close_op(eth_dev);
4927 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4928 struct rte_pci_device *pci_dev)
4930 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4934 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4936 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4937 return rte_eth_dev_pci_generic_remove(pci_dev,
4940 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4943 static struct rte_pci_driver bnxt_rte_pmd = {
4944 .id_table = bnxt_pci_id_map,
4945 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4946 .probe = bnxt_pci_probe,
4947 .remove = bnxt_pci_remove,
4951 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4953 if (strcmp(dev->device->driver->name, drv->driver.name))
4959 bool is_bnxt_supported(struct rte_eth_dev *dev)
4961 return is_device_supported(dev, &bnxt_rte_pmd);
4964 RTE_INIT(bnxt_init_log)
4966 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4967 if (bnxt_logtype_driver >= 0)
4968 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4971 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4972 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4973 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");