drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_irq.h"
  20 #include "bnxt_ring.h"
  21 #include "bnxt_rxq.h"
  22 #include "bnxt_rxr.h"
  23 #include "bnxt_stats.h"
  24 #include "bnxt_txq.h"
  25 #include "bnxt_txr.h"
  26 #include "bnxt_vnic.h"
  27 #include "hsi_struct_def_dpdk.h"
  28 #include "bnxt_nvm_defs.h"
  29
  30 #define DRV_MODULE_NAME         "bnxt"
  31 static const char bnxt_version[] =
  32         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  33 int bnxt_logtype_driver;
  34
  35 /*
  36  * The set of PCI devices this driver supports
  37  */
  38 static const struct rte_pci_id bnxt_pci_id_map[] = {
  39         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  40                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  41         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  42                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  43         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  45         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  92         { .vendor_id = 0, /* sentinel */ },
  93 };
  94
  95 #define BNXT_ETH_RSS_SUPPORT (  \
  96         ETH_RSS_IPV4 |          \
  97         ETH_RSS_NONFRAG_IPV4_TCP |      \
  98         ETH_RSS_NONFRAG_IPV4_UDP |      \
  99         ETH_RSS_IPV6 |          \
 100         ETH_RSS_NONFRAG_IPV6_TCP |      \
 101         ETH_RSS_NONFRAG_IPV6_UDP)
 102
 103 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 104                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 105                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 106                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 107                                      DEV_TX_OFFLOAD_TCP_TSO | \
 108                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 109                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 110                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 111                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 112                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 113                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 114                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 115
 116 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 117                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 118                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 119                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 120                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 121                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 122                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 123                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 124                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 125                                      DEV_RX_OFFLOAD_TCP_LRO | \
 126                                      DEV_RX_OFFLOAD_SCATTER)
 127
 128 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 129 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 130 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 131 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 132 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 133 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 134
 135 int is_bnxt_in_error(struct bnxt *bp)
 136 {
 137         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 138                 return -EIO;
 139         if (bp->flags & BNXT_FLAG_FW_RESET)
 140                 return -EBUSY;
 141
 142         return 0;
 143 }
 144
 145 /***********************/
 146
 147 /*
 148  * High level utility functions
 149  */
 150
 151 uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 152 {
 153         if (!BNXT_CHIP_THOR(bp))
 154                 return 1;
 155
 156         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 157                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 158                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 159 }
 160
 161 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 162 {
 163         if (!BNXT_CHIP_THOR(bp))
 164                 return HW_HASH_INDEX_SIZE;
 165
 166         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 167 }
 168
 169 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 170 {
 171         bnxt_free_filter_mem(bp);
 172         bnxt_free_vnic_attributes(bp);
 173         bnxt_free_vnic_mem(bp);
 174
 175         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 176          * If the number of rings change across fw update,
 177          * we don't have much choice except to warn the user.
 178          */
 179         if (!reconfig) {
 180                 bnxt_free_stats(bp);
 181                 bnxt_free_tx_rings(bp);
 182                 bnxt_free_rx_rings(bp);
 183         }
 184         bnxt_free_async_cp_ring(bp);
 185         bnxt_free_rxtx_nq_ring(bp);
 186
 187         rte_free(bp->grp_info);
 188         bp->grp_info = NULL;
 189 }
 190
 191 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 192 {
 193         int rc;
 194
 195         rc = bnxt_alloc_ring_grps(bp);
 196         if (rc)
 197                 goto alloc_mem_err;
 198
 199         rc = bnxt_alloc_async_ring_struct(bp);
 200         if (rc)
 201                 goto alloc_mem_err;
 202
 203         rc = bnxt_alloc_vnic_mem(bp);
 204         if (rc)
 205                 goto alloc_mem_err;
 206
 207         rc = bnxt_alloc_vnic_attributes(bp);
 208         if (rc)
 209                 goto alloc_mem_err;
 210
 211         rc = bnxt_alloc_filter_mem(bp);
 212         if (rc)
 213                 goto alloc_mem_err;
 214
 215         rc = bnxt_alloc_async_cp_ring(bp);
 216         if (rc)
 217                 goto alloc_mem_err;
 218
 219         rc = bnxt_alloc_rxtx_nq_ring(bp);
 220         if (rc)
 221                 goto alloc_mem_err;
 222
 223         return 0;
 224
 225 alloc_mem_err:
 226         bnxt_free_mem(bp, reconfig);
 227         return rc;
 228 }
 229
 230 static int bnxt_init_chip(struct bnxt *bp)
 231 {
 232         struct bnxt_rx_queue *rxq;
 233         struct rte_eth_link new;
 234         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 235         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 236         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 237         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 238         uint32_t intr_vector = 0;
 239         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 240         uint32_t vec = BNXT_MISC_VEC_ID;
 241         unsigned int i, j;
 242         int rc;
 243
 244         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 245                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 246                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 247                 bp->flags |= BNXT_FLAG_JUMBO;
 248         } else {
 249                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 250                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 251                 bp->flags &= ~BNXT_FLAG_JUMBO;
 252         }
 253
 254         /* THOR does not support ring groups.
 255          * But we will use the array to save RSS context IDs.
 256          */
 257         if (BNXT_CHIP_THOR(bp))
 258                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 259
 260         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 261         if (rc) {
 262                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 263                 goto err_out;
 264         }
 265
 266         rc = bnxt_alloc_hwrm_rings(bp);
 267         if (rc) {
 268                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 269                 goto err_out;
 270         }
 271
 272         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 273         if (rc) {
 274                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 275                 goto err_out;
 276         }
 277
 278         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 279                 goto skip_cosq_cfg;
 280
 281         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 282                 if (bp->rx_cos_queue[i].id != 0xff) {
 283                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 284
 285                         if (!vnic) {
 286                                 PMD_DRV_LOG(ERR,
 287                                             "Num pools more than FW profile\n");
 288                                 rc = -EINVAL;
 289                                 goto err_out;
 290                         }
 291                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 292                         bp->rx_cosq_cnt++;
 293                 }
 294         }
 295
 296 skip_cosq_cfg:
 297         rc = bnxt_mq_rx_configure(bp);
 298         if (rc) {
 299                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 300                 goto err_out;
 301         }
 302
 303         /* VNIC configuration */
 304         for (i = 0; i < bp->nr_vnics; i++) {
 305                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 306                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 307
 308                 rc = bnxt_vnic_grp_alloc(bp, vnic);
 309                 if (rc)
 310                         goto err_out;
 311
 312                 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 313                             i, vnic, vnic->fw_grp_ids);
 314
 315                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 316                 if (rc) {
 317                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 318                                 i, rc);
 319                         goto err_out;
 320                 }
 321
 322                 /* Alloc RSS context only if RSS mode is enabled */
 323                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 324                         int j, nr_ctxs = bnxt_rss_ctxts(bp);
 325
 326                         rc = 0;
 327                         for (j = 0; j < nr_ctxs; j++) {
 328                                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 329                                 if (rc)
 330                                         break;
 331                         }
 332                         if (rc) {
 333                                 PMD_DRV_LOG(ERR,
 334                                   "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 335                                   i, j, rc);
 336                                 goto err_out;
 337                         }
 338                         vnic->num_lb_ctxts = nr_ctxs;
 339                 }
 340
 341                 /*
 342                  * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 343                  * setting is not available at this time, it will not be
 344                  * configured correctly in the CFA.
 345                  */
 346                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 347                         vnic->vlan_strip = true;
 348                 else
 349                         vnic->vlan_strip = false;
 350
 351                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 352                 if (rc) {
 353                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 354                                 i, rc);
 355                         goto err_out;
 356                 }
 357
 358                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 359                 if (rc) {
 360                         PMD_DRV_LOG(ERR,
 361                                 "HWRM vnic %d filter failure rc: %x\n",
 362                                 i, rc);
 363                         goto err_out;
 364                 }
 365
 366                 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 367                         rxq = bp->eth_dev->data->rx_queues[j];
 368
 369                         PMD_DRV_LOG(DEBUG,
 370                                     "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 371                                     j, rxq->vnic, rxq->vnic->fw_grp_ids);
 372
 373                         if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 374                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 375                 }
 376
 377                 rc = bnxt_vnic_rss_configure(bp, vnic);
 378                 if (rc) {
 379                         PMD_DRV_LOG(ERR,
 380                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 381                         goto err_out;
 382                 }
 383
 384                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 385
 386                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 387                     DEV_RX_OFFLOAD_TCP_LRO)
 388                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 389                 else
 390                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 391         }
 392         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 393         if (rc) {
 394                 PMD_DRV_LOG(ERR,
 395                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 396                 goto err_out;
 397         }
 398
 399         /* check and configure queue intr-vector mapping */
 400         if ((rte_intr_cap_multiple(intr_handle) ||
 401              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 402             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 403                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 404                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 405                 if (intr_vector > bp->rx_cp_nr_rings) {
 406                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 407                                         bp->rx_cp_nr_rings);
 408                         return -ENOTSUP;
 409                 }
 410                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 411                 if (rc)
 412                         return rc;
 413         }
 414
 415         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 416                 intr_handle->intr_vec =
 417                         rte_zmalloc("intr_vec",
 418                                     bp->eth_dev->data->nb_rx_queues *
 419                                     sizeof(int), 0);
 420                 if (intr_handle->intr_vec == NULL) {
 421                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 422                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 423                         rc = -ENOMEM;
 424                         goto err_disable;
 425                 }
 426                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 427                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 428                          intr_handle->intr_vec, intr_handle->nb_efd,
 429                         intr_handle->max_intr);
 430                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 431                      queue_id++) {
 432                         intr_handle->intr_vec[queue_id] =
 433                                                         vec + BNXT_RX_VEC_START;
 434                         if (vec < base + intr_handle->nb_efd - 1)
 435                                 vec++;
 436                 }
 437         }
 438
 439         /* enable uio/vfio intr/eventfd mapping */
 440         rc = rte_intr_enable(intr_handle);
 441         if (rc)
 442                 goto err_free;
 443
 444         rc = bnxt_get_hwrm_link_config(bp, &new);
 445         if (rc) {
 446                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 447                 goto err_free;
 448         }
 449
 450         if (!bp->link_info.link_up) {
 451                 rc = bnxt_set_hwrm_link_config(bp, true);
 452                 if (rc) {
 453                         PMD_DRV_LOG(ERR,
 454                                 "HWRM link config failure rc: %x\n", rc);
 455                         goto err_free;
 456                 }
 457         }
 458         bnxt_print_link_info(bp->eth_dev);
 459
 460         return 0;
 461
 462 err_free:
 463         rte_free(intr_handle->intr_vec);
 464 err_disable:
 465         rte_intr_efd_disable(intr_handle);
 466 err_out:
 467         /* Some of the error status returned by FW may not be from errno.h */
 468         if (rc > 0)
 469                 rc = -EIO;
 470
 471         return rc;
 472 }
 473
 474 static int bnxt_shutdown_nic(struct bnxt *bp)
 475 {
 476         bnxt_free_all_hwrm_resources(bp);
 477         bnxt_free_all_filters(bp);
 478         bnxt_free_all_vnics(bp);
 479         return 0;
 480 }
 481
 482 static int bnxt_init_nic(struct bnxt *bp)
 483 {
 484         int rc;
 485
 486         if (BNXT_HAS_RING_GRPS(bp)) {
 487                 rc = bnxt_init_ring_grps(bp);
 488                 if (rc)
 489                         return rc;
 490         }
 491
 492         bnxt_init_vnics(bp);
 493         bnxt_init_filters(bp);
 494
 495         return 0;
 496 }
 497
 498 /*
 499  * Device configuration and status function
 500  */
 501
 502 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 503                                 struct rte_eth_dev_info *dev_info)
 504 {
 505         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 506         struct bnxt *bp = eth_dev->data->dev_private;
 507         uint16_t max_vnics, i, j, vpool, vrxq;
 508         unsigned int max_rx_rings;
 509         int rc;
 510
 511         rc = is_bnxt_in_error(bp);
 512         if (rc)
 513                 return rc;
 514
 515         /* MAC Specifics */
 516         dev_info->max_mac_addrs = bp->max_l2_ctx;
 517         dev_info->max_hash_mac_addrs = 0;
 518
 519         /* PF/VF specifics */
 520         if (BNXT_PF(bp))
 521                 dev_info->max_vfs = pdev->max_vfs;
 522
 523         max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
 524         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 525         dev_info->max_rx_queues = max_rx_rings;
 526         dev_info->max_tx_queues = max_rx_rings;
 527         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 528         dev_info->hash_key_size = 40;
 529         max_vnics = bp->max_vnics;
 530
 531         /* MTU specifics */
 532         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 533         dev_info->max_mtu = BNXT_MAX_MTU;
 534
 535         /* Fast path specifics */
 536         dev_info->min_rx_bufsize = 1;
 537         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 538
 539         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 540         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 541                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 542         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 543         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 544
 545         /* *INDENT-OFF* */
 546         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 547                 .rx_thresh = {
 548                         .pthresh = 8,
 549                         .hthresh = 8,
 550                         .wthresh = 0,
 551                 },
 552                 .rx_free_thresh = 32,
 553                 /* If no descriptors available, pkts are dropped by default */
 554                 .rx_drop_en = 1,
 555         };
 556
 557         dev_info->default_txconf = (struct rte_eth_txconf) {
 558                 .tx_thresh = {
 559                         .pthresh = 32,
 560                         .hthresh = 0,
 561                         .wthresh = 0,
 562                 },
 563                 .tx_free_thresh = 32,
 564                 .tx_rs_thresh = 32,
 565         };
 566         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 567
 568         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 569         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 570         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 571         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 572         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 573
 574         /* *INDENT-ON* */
 575
 576         /*
 577          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 578          *       need further investigation.
 579          */
 580
 581         /* VMDq resources */
 582         vpool = 64; /* ETH_64_POOLS */
 583         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 584         for (i = 0; i < 4; vpool >>= 1, i++) {
 585                 if (max_vnics > vpool) {
 586                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 587                                 if (dev_info->max_rx_queues > vrxq) {
 588                                         if (vpool > vrxq)
 589                                                 vpool = vrxq;
 590                                         goto found;
 591                                 }
 592                         }
 593                         /* Not enough resources to support VMDq */
 594                         break;
 595                 }
 596         }
 597         /* Not enough resources to support VMDq */
 598         vpool = 0;
 599         vrxq = 0;
 600 found:
 601         dev_info->max_vmdq_pools = vpool;
 602         dev_info->vmdq_queue_num = vrxq;
 603
 604         dev_info->vmdq_pool_base = 0;
 605         dev_info->vmdq_queue_base = 0;
 606
 607         return 0;
 608 }
 609
 610 /* Configure the device based on the configuration provided */
 611 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 612 {
 613         struct bnxt *bp = eth_dev->data->dev_private;
 614         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 615         int rc;
 616
 617         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 618         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 619         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 620         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 621
 622         rc = is_bnxt_in_error(bp);
 623         if (rc)
 624                 return rc;
 625
 626         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 627                 rc = bnxt_hwrm_check_vf_rings(bp);
 628                 if (rc) {
 629                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 630                         return -ENOSPC;
 631                 }
 632
 633                 /* If a resource has already been allocated - in this case
 634                  * it is the async completion ring, free it. Reallocate it after
 635                  * resource reservation. This will ensure the resource counts
 636                  * are calculated correctly.
 637                  */
 638
 639                 pthread_mutex_lock(&bp->def_cp_lock);
 640
 641                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 642                         bnxt_disable_int(bp);
 643                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 644                 }
 645
 646                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 647                 if (rc) {
 648                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 649                         pthread_mutex_unlock(&bp->def_cp_lock);
 650                         return -ENOSPC;
 651                 }
 652
 653                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 654                         rc = bnxt_alloc_async_cp_ring(bp);
 655                         if (rc) {
 656                                 pthread_mutex_unlock(&bp->def_cp_lock);
 657                                 return rc;
 658                         }
 659                         bnxt_enable_int(bp);
 660                 }
 661
 662                 pthread_mutex_unlock(&bp->def_cp_lock);
 663         } else {
 664                 /* legacy driver needs to get updated values */
 665                 rc = bnxt_hwrm_func_qcaps(bp);
 666                 if (rc) {
 667                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 668                         return rc;
 669                 }
 670         }
 671
 672         /* Inherit new configurations */
 673         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 674             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 675             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 676                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 677             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 678             bp->max_stat_ctx)
 679                 goto resource_error;
 680
 681         if (BNXT_HAS_RING_GRPS(bp) &&
 682             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 683                 goto resource_error;
 684
 685         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 686             bp->max_vnics < eth_dev->data->nb_rx_queues)
 687                 goto resource_error;
 688
 689         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 690         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 691
 692         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 693                 eth_dev->data->mtu =
 694                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 695                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 696                         BNXT_NUM_VLANS;
 697                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 698         }
 699         return 0;
 700
 701 resource_error:
 702         PMD_DRV_LOG(ERR,
 703                     "Insufficient resources to support requested config\n");
 704         PMD_DRV_LOG(ERR,
 705                     "Num Queues Requested: Tx %d, Rx %d\n",
 706                     eth_dev->data->nb_tx_queues,
 707                     eth_dev->data->nb_rx_queues);
 708         PMD_DRV_LOG(ERR,
 709                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 710                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 711                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 712         return -ENOSPC;
 713 }
 714
 715 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 716 {
 717         struct rte_eth_link *link = &eth_dev->data->dev_link;
 718
 719         if (link->link_status)
 720                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 721                         eth_dev->data->port_id,
 722                         (uint32_t)link->link_speed,
 723                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 724                         ("full-duplex") : ("half-duplex\n"));
 725         else
 726                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 727                         eth_dev->data->port_id);
 728 }
 729
 730 /*
 731  * Determine whether the current configuration requires support for scattered
 732  * receive; return 1 if scattered receive is required and 0 if not.
 733  */
 734 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 735 {
 736         uint16_t buf_size;
 737         int i;
 738
 739         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
 740                 return 1;
 741
 742         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 743                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 744
 745                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 746                                       RTE_PKTMBUF_HEADROOM);
 747                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 748                         return 1;
 749         }
 750         return 0;
 751 }
 752
 753 static eth_rx_burst_t
 754 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
 755 {
 756 #ifdef RTE_ARCH_X86
 757 #ifndef RTE_LIBRTE_IEEE1588
 758         /*
 759          * Vector mode receive can be enabled only if scatter rx is not
 760          * in use and rx offloads are limited to VLAN stripping and
 761          * CRC stripping.
 762          */
 763         if (!eth_dev->data->scattered_rx &&
 764             !(eth_dev->data->dev_conf.rxmode.offloads &
 765               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 766                 DEV_RX_OFFLOAD_KEEP_CRC |
 767                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 768                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 769                 DEV_RX_OFFLOAD_UDP_CKSUM |
 770                 DEV_RX_OFFLOAD_TCP_CKSUM |
 771                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 772                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 773                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 774                             eth_dev->data->port_id);
 775                 return bnxt_recv_pkts_vec;
 776         }
 777         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 778                     eth_dev->data->port_id);
 779         PMD_DRV_LOG(INFO,
 780                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 781                     eth_dev->data->port_id,
 782                     eth_dev->data->scattered_rx,
 783                     eth_dev->data->dev_conf.rxmode.offloads);
 784 #endif
 785 #endif
 786         return bnxt_recv_pkts;
 787 }
 788
 789 static eth_tx_burst_t
 790 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 791 {
 792 #ifdef RTE_ARCH_X86
 793 #ifndef RTE_LIBRTE_IEEE1588
 794         /*
 795          * Vector mode transmit can be enabled only if not using scatter rx
 796          * or tx offloads.
 797          */
 798         if (!eth_dev->data->scattered_rx &&
 799             !eth_dev->data->dev_conf.txmode.offloads) {
 800                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 801                             eth_dev->data->port_id);
 802                 return bnxt_xmit_pkts_vec;
 803         }
 804         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 805                     eth_dev->data->port_id);
 806         PMD_DRV_LOG(INFO,
 807                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 808                     eth_dev->data->port_id,
 809                     eth_dev->data->scattered_rx,
 810                     eth_dev->data->dev_conf.txmode.offloads);
 811 #endif
 812 #endif
 813         return bnxt_xmit_pkts;
 814 }
 815
 816 static int bnxt_handle_if_change_status(struct bnxt *bp)
 817 {
 818         int rc;
 819
 820         /* Since fw has undergone a reset and lost all contexts,
 821          * set fatal flag to not issue hwrm during cleanup
 822          */
 823         bp->flags |= BNXT_FLAG_FATAL_ERROR;
 824         bnxt_uninit_resources(bp, true);
 825
 826         /* clear fatal flag so that re-init happens */
 827         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
 828         rc = bnxt_init_resources(bp, true);
 829
 830         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
 831
 832         return rc;
 833 }
 834
 835 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 836 {
 837         struct bnxt *bp = eth_dev->data->dev_private;
 838         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 839         int vlan_mask = 0;
 840         int rc;
 841
 842         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
 843                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
 844                 return -EINVAL;
 845         }
 846
 847         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 848                 PMD_DRV_LOG(ERR,
 849                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 850                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 851         }
 852
 853         rc = bnxt_hwrm_if_change(bp, 1);
 854         if (!rc) {
 855                 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
 856                         rc = bnxt_handle_if_change_status(bp);
 857                         if (rc)
 858                                 return rc;
 859                 }
 860         }
 861         bnxt_enable_int(bp);
 862
 863         rc = bnxt_init_chip(bp);
 864         if (rc)
 865                 goto error;
 866
 867         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 868
 869         bnxt_link_update_op(eth_dev, 1);
 870
 871         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 872                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 873         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 874                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 875         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 876         if (rc)
 877                 goto error;
 878
 879         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 880         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 881
 882         bp->flags |= BNXT_FLAG_INIT_DONE;
 883         eth_dev->data->dev_started = 1;
 884         bp->dev_stopped = 0;
 885         pthread_mutex_lock(&bp->def_cp_lock);
 886         bnxt_schedule_fw_health_check(bp);
 887         pthread_mutex_unlock(&bp->def_cp_lock);
 888         return 0;
 889
 890 error:
 891         bnxt_hwrm_if_change(bp, 0);
 892         bnxt_shutdown_nic(bp);
 893         bnxt_free_tx_mbufs(bp);
 894         bnxt_free_rx_mbufs(bp);
 895         return rc;
 896 }
 897
 898 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 899 {
 900         struct bnxt *bp = eth_dev->data->dev_private;
 901         int rc = 0;
 902
 903         if (!bp->link_info.link_up)
 904                 rc = bnxt_set_hwrm_link_config(bp, true);
 905         if (!rc)
 906                 eth_dev->data->dev_link.link_status = 1;
 907
 908         bnxt_print_link_info(eth_dev);
 909         return rc;
 910 }
 911
 912 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 913 {
 914         struct bnxt *bp = eth_dev->data->dev_private;
 915
 916         eth_dev->data->dev_link.link_status = 0;
 917         bnxt_set_hwrm_link_config(bp, false);
 918         bp->link_info.link_up = 0;
 919
 920         return 0;
 921 }
 922
 923 /* Unload the driver, release resources */
 924 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 925 {
 926         struct bnxt *bp = eth_dev->data->dev_private;
 927         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 928         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 929
 930         eth_dev->data->dev_started = 0;
 931         /* Prevent crashes when queues are still in use */
 932         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
 933         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
 934
 935         bnxt_disable_int(bp);
 936
 937         /* disable uio/vfio intr/eventfd mapping */
 938         rte_intr_disable(intr_handle);
 939
 940         bnxt_cancel_fw_health_check(bp);
 941
 942         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 943         if (bp->eth_dev->data->dev_started) {
 944                 /* TBD: STOP HW queues DMA */
 945                 eth_dev->data->dev_link.link_status = 0;
 946         }
 947         bnxt_dev_set_link_down_op(eth_dev);
 948
 949         /* Wait for link to be reset and the async notification to process.
 950          * During reset recovery, there is no need to wait
 951          */
 952         if (!is_bnxt_in_error(bp))
 953                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL * 2);
 954
 955         /* Clean queue intr-vector mapping */
 956         rte_intr_efd_disable(intr_handle);
 957         if (intr_handle->intr_vec != NULL) {
 958                 rte_free(intr_handle->intr_vec);
 959                 intr_handle->intr_vec = NULL;
 960         }
 961
 962         bnxt_hwrm_port_clr_stats(bp);
 963         bnxt_free_tx_mbufs(bp);
 964         bnxt_free_rx_mbufs(bp);
 965         /* Process any remaining notifications in default completion queue */
 966         bnxt_int_handler(eth_dev);
 967         bnxt_shutdown_nic(bp);
 968         bnxt_hwrm_if_change(bp, 0);
 969         bp->dev_stopped = 1;
 970 }
 971
 972 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 973 {
 974         struct bnxt *bp = eth_dev->data->dev_private;
 975
 976         if (bp->dev_stopped == 0)
 977                 bnxt_dev_stop_op(eth_dev);
 978
 979         if (eth_dev->data->mac_addrs != NULL) {
 980                 rte_free(eth_dev->data->mac_addrs);
 981                 eth_dev->data->mac_addrs = NULL;
 982         }
 983         if (bp->grp_info != NULL) {
 984                 rte_free(bp->grp_info);
 985                 bp->grp_info = NULL;
 986         }
 987
 988         bnxt_dev_uninit(eth_dev);
 989 }
 990
 991 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 992                                     uint32_t index)
 993 {
 994         struct bnxt *bp = eth_dev->data->dev_private;
 995         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 996         struct bnxt_vnic_info *vnic;
 997         struct bnxt_filter_info *filter, *temp_filter;
 998         uint32_t i;
 999
1000         if (is_bnxt_in_error(bp))
1001                 return;
1002
1003         /*
1004          * Loop through all VNICs from the specified filter flow pools to
1005          * remove the corresponding MAC addr filter
1006          */
1007         for (i = 0; i < bp->nr_vnics; i++) {
1008                 if (!(pool_mask & (1ULL << i)))
1009                         continue;
1010
1011                 vnic = &bp->vnic_info[i];
1012                 filter = STAILQ_FIRST(&vnic->filter);
1013                 while (filter) {
1014                         temp_filter = STAILQ_NEXT(filter, next);
1015                         if (filter->mac_index == index) {
1016                                 STAILQ_REMOVE(&vnic->filter, filter,
1017                                                 bnxt_filter_info, next);
1018                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1019                                 filter->mac_index = INVALID_MAC_INDEX;
1020                                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1021                                 bnxt_free_filter(bp, filter);
1022                         }
1023                         filter = temp_filter;
1024                 }
1025         }
1026 }
1027
1028 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1029                                struct rte_ether_addr *mac_addr, uint32_t index,
1030                                uint32_t pool)
1031 {
1032         struct bnxt_filter_info *filter;
1033         int rc = 0;
1034
1035         /* Attach requested MAC address to the new l2_filter */
1036         STAILQ_FOREACH(filter, &vnic->filter, next) {
1037                 if (filter->mac_index == index) {
1038                         PMD_DRV_LOG(ERR,
1039                                     "MAC addr already existed for pool %d\n",
1040                                     pool);
1041                         return 0;
1042                 }
1043         }
1044
1045         filter = bnxt_alloc_filter(bp);
1046         if (!filter) {
1047                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1048                 return -ENODEV;
1049         }
1050
1051         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1052          * if the MAC that's been programmed now is a different one, then,
1053          * copy that addr to filter->l2_addr
1054          */
1055         if (mac_addr)
1056                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1057         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1058
1059         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1060         if (!rc) {
1061                 filter->mac_index = index;
1062                 if (filter->mac_index == 0)
1063                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1064                 else
1065                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1066         } else {
1067                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1068                 bnxt_free_filter(bp, filter);
1069         }
1070
1071         return rc;
1072 }
1073
1074 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1075                                 struct rte_ether_addr *mac_addr,
1076                                 uint32_t index, uint32_t pool)
1077 {
1078         struct bnxt *bp = eth_dev->data->dev_private;
1079         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1080         int rc = 0;
1081
1082         rc = is_bnxt_in_error(bp);
1083         if (rc)
1084                 return rc;
1085
1086         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1087                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1088                 return -ENOTSUP;
1089         }
1090
1091         if (!vnic) {
1092                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1093                 return -EINVAL;
1094         }
1095
1096         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1097
1098         return rc;
1099 }
1100
1101 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1102 {
1103         int rc = 0;
1104         struct bnxt *bp = eth_dev->data->dev_private;
1105         struct rte_eth_link new;
1106         unsigned int cnt = BNXT_LINK_WAIT_CNT;
1107
1108         rc = is_bnxt_in_error(bp);
1109         if (rc)
1110                 return rc;
1111
1112         memset(&new, 0, sizeof(new));
1113         do {
1114                 /* Retrieve link info from hardware */
1115                 rc = bnxt_get_hwrm_link_config(bp, &new);
1116                 if (rc) {
1117                         new.link_speed = ETH_LINK_SPEED_100M;
1118                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1119                         PMD_DRV_LOG(ERR,
1120                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1121                         goto out;
1122                 }
1123
1124                 if (!wait_to_complete || new.link_status)
1125                         break;
1126
1127                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1128         } while (cnt--);
1129
1130 out:
1131         /* Timed out or success */
1132         if (new.link_status != eth_dev->data->dev_link.link_status ||
1133         new.link_speed != eth_dev->data->dev_link.link_speed) {
1134                 rte_eth_linkstatus_set(eth_dev, &new);
1135
1136                 _rte_eth_dev_callback_process(eth_dev,
1137                                               RTE_ETH_EVENT_INTR_LSC,
1138                                               NULL);
1139
1140                 bnxt_print_link_info(eth_dev);
1141         }
1142
1143         return rc;
1144 }
1145
1146 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1147 {
1148         struct bnxt *bp = eth_dev->data->dev_private;
1149         struct bnxt_vnic_info *vnic;
1150         uint32_t old_flags;
1151         int rc;
1152
1153         rc = is_bnxt_in_error(bp);
1154         if (rc)
1155                 return rc;
1156
1157         if (bp->vnic_info == NULL)
1158                 return 0;
1159
1160         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1161
1162         old_flags = vnic->flags;
1163         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1164         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1165         if (rc != 0)
1166                 vnic->flags = old_flags;
1167
1168         return rc;
1169 }
1170
1171 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1172 {
1173         struct bnxt *bp = eth_dev->data->dev_private;
1174         struct bnxt_vnic_info *vnic;
1175         uint32_t old_flags;
1176         int rc;
1177
1178         rc = is_bnxt_in_error(bp);
1179         if (rc)
1180                 return rc;
1181
1182         if (bp->vnic_info == NULL)
1183                 return 0;
1184
1185         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1186
1187         old_flags = vnic->flags;
1188         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1189         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1190         if (rc != 0)
1191                 vnic->flags = old_flags;
1192
1193         return rc;
1194 }
1195
1196 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1197 {
1198         struct bnxt *bp = eth_dev->data->dev_private;
1199         struct bnxt_vnic_info *vnic;
1200         uint32_t old_flags;
1201         int rc;
1202
1203         rc = is_bnxt_in_error(bp);
1204         if (rc)
1205                 return rc;
1206
1207         if (bp->vnic_info == NULL)
1208                 return 0;
1209
1210         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1211
1212         old_flags = vnic->flags;
1213         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1214         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1215         if (rc != 0)
1216                 vnic->flags = old_flags;
1217
1218         return rc;
1219 }
1220
1221 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1222 {
1223         struct bnxt *bp = eth_dev->data->dev_private;
1224         struct bnxt_vnic_info *vnic;
1225         uint32_t old_flags;
1226         int rc;
1227
1228         rc = is_bnxt_in_error(bp);
1229         if (rc)
1230                 return rc;
1231
1232         if (bp->vnic_info == NULL)
1233                 return 0;
1234
1235         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1236
1237         old_flags = vnic->flags;
1238         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1239         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1240         if (rc != 0)
1241                 vnic->flags = old_flags;
1242
1243         return rc;
1244 }
1245
1246 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1247 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1248 {
1249         if (qid >= bp->rx_nr_rings)
1250                 return NULL;
1251
1252         return bp->eth_dev->data->rx_queues[qid];
1253 }
1254
1255 /* Return rxq corresponding to a given rss table ring/group ID. */
1256 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1257 {
1258         struct bnxt_rx_queue *rxq;
1259         unsigned int i;
1260
1261         if (!BNXT_HAS_RING_GRPS(bp)) {
1262                 for (i = 0; i < bp->rx_nr_rings; i++) {
1263                         rxq = bp->eth_dev->data->rx_queues[i];
1264                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1265                                 return rxq->index;
1266                 }
1267         } else {
1268                 for (i = 0; i < bp->rx_nr_rings; i++) {
1269                         if (bp->grp_info[i].fw_grp_id == fwr)
1270                                 return i;
1271                 }
1272         }
1273
1274         return INVALID_HW_RING_ID;
1275 }
1276
1277 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1278                             struct rte_eth_rss_reta_entry64 *reta_conf,
1279                             uint16_t reta_size)
1280 {
1281         struct bnxt *bp = eth_dev->data->dev_private;
1282         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1283         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1284         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1285         uint16_t idx, sft;
1286         int i, rc;
1287
1288         rc = is_bnxt_in_error(bp);
1289         if (rc)
1290                 return rc;
1291
1292         if (!vnic->rss_table)
1293                 return -EINVAL;
1294
1295         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1296                 return -EINVAL;
1297
1298         if (reta_size != tbl_size) {
1299                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1300                         "(%d) must equal the size supported by the hardware "
1301                         "(%d)\n", reta_size, tbl_size);
1302                 return -EINVAL;
1303         }
1304
1305         for (i = 0; i < reta_size; i++) {
1306                 struct bnxt_rx_queue *rxq;
1307
1308                 idx = i / RTE_RETA_GROUP_SIZE;
1309                 sft = i % RTE_RETA_GROUP_SIZE;
1310
1311                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1312                         continue;
1313
1314                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1315                 if (!rxq) {
1316                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1317                         return -EINVAL;
1318                 }
1319
1320                 if (BNXT_CHIP_THOR(bp)) {
1321                         vnic->rss_table[i * 2] =
1322                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1323                         vnic->rss_table[i * 2 + 1] =
1324                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1325                 } else {
1326                         vnic->rss_table[i] =
1327                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1328                 }
1329         }
1330
1331         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1332         return 0;
1333 }
1334
1335 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1336                               struct rte_eth_rss_reta_entry64 *reta_conf,
1337                               uint16_t reta_size)
1338 {
1339         struct bnxt *bp = eth_dev->data->dev_private;
1340         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1341         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1342         uint16_t idx, sft, i;
1343         int rc;
1344
1345         rc = is_bnxt_in_error(bp);
1346         if (rc)
1347                 return rc;
1348
1349         /* Retrieve from the default VNIC */
1350         if (!vnic)
1351                 return -EINVAL;
1352         if (!vnic->rss_table)
1353                 return -EINVAL;
1354
1355         if (reta_size != tbl_size) {
1356                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1357                         "(%d) must equal the size supported by the hardware "
1358                         "(%d)\n", reta_size, tbl_size);
1359                 return -EINVAL;
1360         }
1361
1362         for (idx = 0, i = 0; i < reta_size; i++) {
1363                 idx = i / RTE_RETA_GROUP_SIZE;
1364                 sft = i % RTE_RETA_GROUP_SIZE;
1365
1366                 if (reta_conf[idx].mask & (1ULL << sft)) {
1367                         uint16_t qid;
1368
1369                         if (BNXT_CHIP_THOR(bp))
1370                                 qid = bnxt_rss_to_qid(bp,
1371                                                       vnic->rss_table[i * 2]);
1372                         else
1373                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1374
1375                         if (qid == INVALID_HW_RING_ID) {
1376                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1377                                 return -EINVAL;
1378                         }
1379                         reta_conf[idx].reta[sft] = qid;
1380                 }
1381         }
1382
1383         return 0;
1384 }
1385
1386 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1387                                    struct rte_eth_rss_conf *rss_conf)
1388 {
1389         struct bnxt *bp = eth_dev->data->dev_private;
1390         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1391         struct bnxt_vnic_info *vnic;
1392         int rc;
1393
1394         rc = is_bnxt_in_error(bp);
1395         if (rc)
1396                 return rc;
1397
1398         /*
1399          * If RSS enablement were different than dev_configure,
1400          * then return -EINVAL
1401          */
1402         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1403                 if (!rss_conf->rss_hf)
1404                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1405         } else {
1406                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1407                         return -EINVAL;
1408         }
1409
1410         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1411         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1412
1413         /* Update the default RSS VNIC(s) */
1414         vnic = &bp->vnic_info[0];
1415         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1416
1417         /*
1418          * If hashkey is not specified, use the previously configured
1419          * hashkey
1420          */
1421         if (!rss_conf->rss_key)
1422                 goto rss_config;
1423
1424         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1425                 PMD_DRV_LOG(ERR,
1426                             "Invalid hashkey length, should be 16 bytes\n");
1427                 return -EINVAL;
1428         }
1429         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1430
1431 rss_config:
1432         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1433         return 0;
1434 }
1435
1436 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1437                                      struct rte_eth_rss_conf *rss_conf)
1438 {
1439         struct bnxt *bp = eth_dev->data->dev_private;
1440         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1441         int len, rc;
1442         uint32_t hash_types;
1443
1444         rc = is_bnxt_in_error(bp);
1445         if (rc)
1446                 return rc;
1447
1448         /* RSS configuration is the same for all VNICs */
1449         if (vnic && vnic->rss_hash_key) {
1450                 if (rss_conf->rss_key) {
1451                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1452                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1453                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1454                 }
1455
1456                 hash_types = vnic->hash_type;
1457                 rss_conf->rss_hf = 0;
1458                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1459                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1460                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1461                 }
1462                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1463                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1464                         hash_types &=
1465                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1466                 }
1467                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1468                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1469                         hash_types &=
1470                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1471                 }
1472                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1473                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1474                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1475                 }
1476                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1477                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1478                         hash_types &=
1479                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1480                 }
1481                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1482                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1483                         hash_types &=
1484                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1485                 }
1486                 if (hash_types) {
1487                         PMD_DRV_LOG(ERR,
1488                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1489                                 vnic->hash_type);
1490                         return -ENOTSUP;
1491                 }
1492         } else {
1493                 rss_conf->rss_hf = 0;
1494         }
1495         return 0;
1496 }
1497
1498 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1499                                struct rte_eth_fc_conf *fc_conf)
1500 {
1501         struct bnxt *bp = dev->data->dev_private;
1502         struct rte_eth_link link_info;
1503         int rc;
1504
1505         rc = is_bnxt_in_error(bp);
1506         if (rc)
1507                 return rc;
1508
1509         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1510         if (rc)
1511                 return rc;
1512
1513         memset(fc_conf, 0, sizeof(*fc_conf));
1514         if (bp->link_info.auto_pause)
1515                 fc_conf->autoneg = 1;
1516         switch (bp->link_info.pause) {
1517         case 0:
1518                 fc_conf->mode = RTE_FC_NONE;
1519                 break;
1520         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1521                 fc_conf->mode = RTE_FC_TX_PAUSE;
1522                 break;
1523         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1524                 fc_conf->mode = RTE_FC_RX_PAUSE;
1525                 break;
1526         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1527                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1528                 fc_conf->mode = RTE_FC_FULL;
1529                 break;
1530         }
1531         return 0;
1532 }
1533
1534 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1535                                struct rte_eth_fc_conf *fc_conf)
1536 {
1537         struct bnxt *bp = dev->data->dev_private;
1538         int rc;
1539
1540         rc = is_bnxt_in_error(bp);
1541         if (rc)
1542                 return rc;
1543
1544         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1545                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1546                 return -ENOTSUP;
1547         }
1548
1549         switch (fc_conf->mode) {
1550         case RTE_FC_NONE:
1551                 bp->link_info.auto_pause = 0;
1552                 bp->link_info.force_pause = 0;
1553                 break;
1554         case RTE_FC_RX_PAUSE:
1555                 if (fc_conf->autoneg) {
1556                         bp->link_info.auto_pause =
1557                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1558                         bp->link_info.force_pause = 0;
1559                 } else {
1560                         bp->link_info.auto_pause = 0;
1561                         bp->link_info.force_pause =
1562                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1563                 }
1564                 break;
1565         case RTE_FC_TX_PAUSE:
1566                 if (fc_conf->autoneg) {
1567                         bp->link_info.auto_pause =
1568                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1569                         bp->link_info.force_pause = 0;
1570                 } else {
1571                         bp->link_info.auto_pause = 0;
1572                         bp->link_info.force_pause =
1573                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1574                 }
1575                 break;
1576         case RTE_FC_FULL:
1577                 if (fc_conf->autoneg) {
1578                         bp->link_info.auto_pause =
1579                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1580                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1581                         bp->link_info.force_pause = 0;
1582                 } else {
1583                         bp->link_info.auto_pause = 0;
1584                         bp->link_info.force_pause =
1585                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1586                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1587                 }
1588                 break;
1589         }
1590         return bnxt_set_hwrm_link_config(bp, true);
1591 }
1592
1593 /* Add UDP tunneling port */
1594 static int
1595 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1596                          struct rte_eth_udp_tunnel *udp_tunnel)
1597 {
1598         struct bnxt *bp = eth_dev->data->dev_private;
1599         uint16_t tunnel_type = 0;
1600         int rc = 0;
1601
1602         rc = is_bnxt_in_error(bp);
1603         if (rc)
1604                 return rc;
1605
1606         switch (udp_tunnel->prot_type) {
1607         case RTE_TUNNEL_TYPE_VXLAN:
1608                 if (bp->vxlan_port_cnt) {
1609                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1610                                 udp_tunnel->udp_port);
1611                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1612                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1613                                 return -ENOSPC;
1614                         }
1615                         bp->vxlan_port_cnt++;
1616                         return 0;
1617                 }
1618                 tunnel_type =
1619                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1620                 bp->vxlan_port_cnt++;
1621                 break;
1622         case RTE_TUNNEL_TYPE_GENEVE:
1623                 if (bp->geneve_port_cnt) {
1624                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1625                                 udp_tunnel->udp_port);
1626                         if (bp->geneve_port != udp_tunnel->udp_port) {
1627                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1628                                 return -ENOSPC;
1629                         }
1630                         bp->geneve_port_cnt++;
1631                         return 0;
1632                 }
1633                 tunnel_type =
1634                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1635                 bp->geneve_port_cnt++;
1636                 break;
1637         default:
1638                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1639                 return -ENOTSUP;
1640         }
1641         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1642                                              tunnel_type);
1643         return rc;
1644 }
1645
1646 static int
1647 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1648                          struct rte_eth_udp_tunnel *udp_tunnel)
1649 {
1650         struct bnxt *bp = eth_dev->data->dev_private;
1651         uint16_t tunnel_type = 0;
1652         uint16_t port = 0;
1653         int rc = 0;
1654
1655         rc = is_bnxt_in_error(bp);
1656         if (rc)
1657                 return rc;
1658
1659         switch (udp_tunnel->prot_type) {
1660         case RTE_TUNNEL_TYPE_VXLAN:
1661                 if (!bp->vxlan_port_cnt) {
1662                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1663                         return -EINVAL;
1664                 }
1665                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1666                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1667                                 udp_tunnel->udp_port, bp->vxlan_port);
1668                         return -EINVAL;
1669                 }
1670                 if (--bp->vxlan_port_cnt)
1671                         return 0;
1672
1673                 tunnel_type =
1674                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1675                 port = bp->vxlan_fw_dst_port_id;
1676                 break;
1677         case RTE_TUNNEL_TYPE_GENEVE:
1678                 if (!bp->geneve_port_cnt) {
1679                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1680                         return -EINVAL;
1681                 }
1682                 if (bp->geneve_port != udp_tunnel->udp_port) {
1683                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1684                                 udp_tunnel->udp_port, bp->geneve_port);
1685                         return -EINVAL;
1686                 }
1687                 if (--bp->geneve_port_cnt)
1688                         return 0;
1689
1690                 tunnel_type =
1691                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1692                 port = bp->geneve_fw_dst_port_id;
1693                 break;
1694         default:
1695                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1696                 return -ENOTSUP;
1697         }
1698
1699         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1700         if (!rc) {
1701                 if (tunnel_type ==
1702                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1703                         bp->vxlan_port = 0;
1704                 if (tunnel_type ==
1705                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1706                         bp->geneve_port = 0;
1707         }
1708         return rc;
1709 }
1710
1711 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1712 {
1713         struct bnxt_filter_info *filter;
1714         struct bnxt_vnic_info *vnic;
1715         int rc = 0;
1716         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1717
1718         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1719         filter = STAILQ_FIRST(&vnic->filter);
1720         while (filter) {
1721                 /* Search for this matching MAC+VLAN filter */
1722                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
1723                         /* Delete the filter */
1724                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1725                         if (rc)
1726                                 return rc;
1727                         STAILQ_REMOVE(&vnic->filter, filter,
1728                                       bnxt_filter_info, next);
1729                         bnxt_free_filter(bp, filter);
1730                         PMD_DRV_LOG(INFO,
1731                                     "Deleted vlan filter for %d\n",
1732                                     vlan_id);
1733                         return 0;
1734                 }
1735                 filter = STAILQ_NEXT(filter, next);
1736         }
1737         return -ENOENT;
1738 }
1739
1740 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1741 {
1742         struct bnxt_filter_info *filter;
1743         struct bnxt_vnic_info *vnic;
1744         int rc = 0;
1745         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1746                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1747         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1748
1749         /* Implementation notes on the use of VNIC in this command:
1750          *
1751          * By default, these filters belong to default vnic for the function.
1752          * Once these filters are set up, only destination VNIC can be modified.
1753          * If the destination VNIC is not specified in this command,
1754          * then the HWRM shall only create an l2 context id.
1755          */
1756
1757         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1758         filter = STAILQ_FIRST(&vnic->filter);
1759         /* Check if the VLAN has already been added */
1760         while (filter) {
1761                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
1762                         return -EEXIST;
1763
1764                 filter = STAILQ_NEXT(filter, next);
1765         }
1766
1767         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1768          * command to create MAC+VLAN filter with the right flags, enables set.
1769          */
1770         filter = bnxt_alloc_filter(bp);
1771         if (!filter) {
1772                 PMD_DRV_LOG(ERR,
1773                             "MAC/VLAN filter alloc failed\n");
1774                 return -ENOMEM;
1775         }
1776         /* MAC + VLAN ID filter */
1777         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1778          * untagged packets are received
1779          *
1780          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
1781          * packets and only the programmed vlan's packets are received
1782          */
1783         filter->l2_ivlan = vlan_id;
1784         filter->l2_ivlan_mask = 0x0FFF;
1785         filter->enables |= en;
1786         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1787
1788         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1789         if (rc) {
1790                 /* Free the newly allocated filter as we were
1791                  * not able to create the filter in hardware.
1792                  */
1793                 filter->fw_l2_filter_id = UINT64_MAX;
1794                 bnxt_free_filter(bp, filter);
1795                 return rc;
1796         }
1797
1798         filter->mac_index = 0;
1799         /* Add this new filter to the list */
1800         if (vlan_id == 0)
1801                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1802         else
1803                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1804
1805         PMD_DRV_LOG(INFO,
1806                     "Added Vlan filter for %d\n", vlan_id);
1807         return rc;
1808 }
1809
1810 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1811                 uint16_t vlan_id, int on)
1812 {
1813         struct bnxt *bp = eth_dev->data->dev_private;
1814         int rc;
1815
1816         rc = is_bnxt_in_error(bp);
1817         if (rc)
1818                 return rc;
1819
1820         /* These operations apply to ALL existing MAC/VLAN filters */
1821         if (on)
1822                 return bnxt_add_vlan_filter(bp, vlan_id);
1823         else
1824                 return bnxt_del_vlan_filter(bp, vlan_id);
1825 }
1826
1827 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
1828                                     struct bnxt_vnic_info *vnic)
1829 {
1830         struct bnxt_filter_info *filter;
1831         int rc;
1832
1833         filter = STAILQ_FIRST(&vnic->filter);
1834         while (filter) {
1835                 if (filter->mac_index == 0 &&
1836                     !memcmp(filter->l2_addr, bp->mac_addr,
1837                             RTE_ETHER_ADDR_LEN)) {
1838                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1839                         if (!rc) {
1840                                 STAILQ_REMOVE(&vnic->filter, filter,
1841                                               bnxt_filter_info, next);
1842                                 bnxt_free_filter(bp, filter);
1843                                 filter->fw_l2_filter_id = UINT64_MAX;
1844                         }
1845                         return rc;
1846                 }
1847                 filter = STAILQ_NEXT(filter, next);
1848         }
1849         return 0;
1850 }
1851
1852 static int
1853 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1854 {
1855         struct bnxt *bp = dev->data->dev_private;
1856         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1857         struct bnxt_vnic_info *vnic;
1858         unsigned int i;
1859         int rc;
1860
1861         rc = is_bnxt_in_error(bp);
1862         if (rc)
1863                 return rc;
1864
1865         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1866         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1867                 /* Remove any VLAN filters programmed */
1868                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1869                         bnxt_del_vlan_filter(bp, i);
1870
1871                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1872                 if (rc)
1873                         return rc;
1874         } else {
1875                 /* Default filter will allow packets that match the
1876                  * dest mac. So, it has to be deleted, otherwise, we
1877                  * will endup receiving vlan packets for which the
1878                  * filter is not programmed, when hw-vlan-filter
1879                  * configuration is ON
1880                  */
1881                 bnxt_del_dflt_mac_filter(bp, vnic);
1882                 /* This filter will allow only untagged packets */
1883                 bnxt_add_vlan_filter(bp, 0);
1884         }
1885         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1886                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1887
1888         if (mask & ETH_VLAN_STRIP_MASK) {
1889                 /* Enable or disable VLAN stripping */
1890                 for (i = 0; i < bp->nr_vnics; i++) {
1891                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1892                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1893                                 vnic->vlan_strip = true;
1894                         else
1895                                 vnic->vlan_strip = false;
1896                         bnxt_hwrm_vnic_cfg(bp, vnic);
1897                 }
1898                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1899                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1900         }
1901
1902         if (mask & ETH_VLAN_EXTEND_MASK) {
1903                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1904                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
1905                 else
1906                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
1907         }
1908
1909         return 0;
1910 }
1911
1912 static int
1913 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
1914                       uint16_t tpid)
1915 {
1916         struct bnxt *bp = dev->data->dev_private;
1917         int qinq = dev->data->dev_conf.rxmode.offloads &
1918                    DEV_RX_OFFLOAD_VLAN_EXTEND;
1919
1920         if (vlan_type != ETH_VLAN_TYPE_INNER &&
1921             vlan_type != ETH_VLAN_TYPE_OUTER) {
1922                 PMD_DRV_LOG(ERR,
1923                             "Unsupported vlan type.");
1924                 return -EINVAL;
1925         }
1926         if (!qinq) {
1927                 PMD_DRV_LOG(ERR,
1928                             "QinQ not enabled. Needs to be ON as we can "
1929                             "accelerate only outer vlan\n");
1930                 return -EINVAL;
1931         }
1932
1933         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
1934                 switch (tpid) {
1935                 case RTE_ETHER_TYPE_QINQ:
1936                         bp->outer_tpid_bd =
1937                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
1938                                 break;
1939                 case RTE_ETHER_TYPE_VLAN:
1940                         bp->outer_tpid_bd =
1941                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
1942                                 break;
1943                 case 0x9100:
1944                         bp->outer_tpid_bd =
1945                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
1946                                 break;
1947                 case 0x9200:
1948                         bp->outer_tpid_bd =
1949                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
1950                                 break;
1951                 case 0x9300:
1952                         bp->outer_tpid_bd =
1953                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
1954                                 break;
1955                 default:
1956                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
1957                         return -EINVAL;
1958                 }
1959                 bp->outer_tpid_bd |= tpid;
1960                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
1961         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
1962                 PMD_DRV_LOG(ERR,
1963                             "Can accelerate only outer vlan in QinQ\n");
1964                 return -EINVAL;
1965         }
1966
1967         return 0;
1968 }
1969
1970 static int
1971 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1972                              struct rte_ether_addr *addr)
1973 {
1974         struct bnxt *bp = dev->data->dev_private;
1975         /* Default Filter is tied to VNIC 0 */
1976         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1977         struct bnxt_filter_info *filter;
1978         int rc;
1979
1980         rc = is_bnxt_in_error(bp);
1981         if (rc)
1982                 return rc;
1983
1984         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1985                 return -EPERM;
1986
1987         if (rte_is_zero_ether_addr(addr))
1988                 return -EINVAL;
1989
1990         STAILQ_FOREACH(filter, &vnic->filter, next) {
1991                 /* Default Filter is at Index 0 */
1992                 if (filter->mac_index != 0)
1993                         continue;
1994
1995                 memcpy(filter->l2_addr, addr, RTE_ETHER_ADDR_LEN);
1996                 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1997                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX |
1998                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1999                 filter->enables |=
2000                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
2001                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
2002
2003                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2004                 if (rc) {
2005                         memcpy(filter->l2_addr, bp->mac_addr,
2006                                RTE_ETHER_ADDR_LEN);
2007                         return rc;
2008                 }
2009
2010                 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2011                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2012                 return 0;
2013         }
2014
2015         return 0;
2016 }
2017
2018 static int
2019 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2020                           struct rte_ether_addr *mc_addr_set,
2021                           uint32_t nb_mc_addr)
2022 {
2023         struct bnxt *bp = eth_dev->data->dev_private;
2024         char *mc_addr_list = (char *)mc_addr_set;
2025         struct bnxt_vnic_info *vnic;
2026         uint32_t off = 0, i = 0;
2027         int rc;
2028
2029         rc = is_bnxt_in_error(bp);
2030         if (rc)
2031                 return rc;
2032
2033         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2034
2035         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2036                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2037                 goto allmulti;
2038         }
2039
2040         /* TODO Check for Duplicate mcast addresses */
2041         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2042         for (i = 0; i < nb_mc_addr; i++) {
2043                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2044                         RTE_ETHER_ADDR_LEN);
2045                 off += RTE_ETHER_ADDR_LEN;
2046         }
2047
2048         vnic->mc_addr_cnt = i;
2049         if (vnic->mc_addr_cnt)
2050                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2051         else
2052                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2053
2054 allmulti:
2055         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2056 }
2057
2058 static int
2059 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2060 {
2061         struct bnxt *bp = dev->data->dev_private;
2062         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2063         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2064         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2065         int ret;
2066
2067         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2068                         fw_major, fw_minor, fw_updt);
2069
2070         ret += 1; /* add the size of '\0' */
2071         if (fw_size < (uint32_t)ret)
2072                 return ret;
2073         else
2074                 return 0;
2075 }
2076
2077 static void
2078 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2079         struct rte_eth_rxq_info *qinfo)
2080 {
2081         struct bnxt_rx_queue *rxq;
2082
2083         rxq = dev->data->rx_queues[queue_id];
2084
2085         qinfo->mp = rxq->mb_pool;
2086         qinfo->scattered_rx = dev->data->scattered_rx;
2087         qinfo->nb_desc = rxq->nb_rx_desc;
2088
2089         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2090         qinfo->conf.rx_drop_en = 0;
2091         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2092 }
2093
2094 static void
2095 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2096         struct rte_eth_txq_info *qinfo)
2097 {
2098         struct bnxt_tx_queue *txq;
2099
2100         txq = dev->data->tx_queues[queue_id];
2101
2102         qinfo->nb_desc = txq->nb_tx_desc;
2103
2104         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2105         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2106         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2107
2108         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2109         qinfo->conf.tx_rs_thresh = 0;
2110         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2111 }
2112
2113 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2114 {
2115         struct bnxt *bp = eth_dev->data->dev_private;
2116         uint32_t new_pkt_size;
2117         uint32_t rc = 0;
2118         uint32_t i;
2119
2120         rc = is_bnxt_in_error(bp);
2121         if (rc)
2122                 return rc;
2123
2124         /* Exit if receive queues are not configured yet */
2125         if (!eth_dev->data->nb_rx_queues)
2126                 return rc;
2127
2128         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2129                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2130
2131 #ifdef RTE_ARCH_X86
2132         /*
2133          * If vector-mode tx/rx is active, disallow any MTU change that would
2134          * require scattered receive support.
2135          */
2136         if (eth_dev->data->dev_started &&
2137             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2138              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2139             (new_pkt_size >
2140              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2141                 PMD_DRV_LOG(ERR,
2142                             "MTU change would require scattered rx support. ");
2143                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2144                 return -EINVAL;
2145         }
2146 #endif
2147
2148         if (new_mtu > RTE_ETHER_MTU) {
2149                 bp->flags |= BNXT_FLAG_JUMBO;
2150                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2151                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2152         } else {
2153                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2154                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2155                 bp->flags &= ~BNXT_FLAG_JUMBO;
2156         }
2157
2158         /* Is there a change in mtu setting? */
2159         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2160                 return rc;
2161
2162         for (i = 0; i < bp->nr_vnics; i++) {
2163                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2164                 uint16_t size = 0;
2165
2166                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2167                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2168                 if (rc)
2169                         break;
2170
2171                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2172                 size -= RTE_PKTMBUF_HEADROOM;
2173
2174                 if (size < new_mtu) {
2175                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2176                         if (rc)
2177                                 return rc;
2178                 }
2179         }
2180
2181         if (!rc)
2182                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2183
2184         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2185
2186         return rc;
2187 }
2188
2189 static int
2190 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2191 {
2192         struct bnxt *bp = dev->data->dev_private;
2193         uint16_t vlan = bp->vlan;
2194         int rc;
2195
2196         rc = is_bnxt_in_error(bp);
2197         if (rc)
2198                 return rc;
2199
2200         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2201                 PMD_DRV_LOG(ERR,
2202                         "PVID cannot be modified for this function\n");
2203                 return -ENOTSUP;
2204         }
2205         bp->vlan = on ? pvid : 0;
2206
2207         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2208         if (rc)
2209                 bp->vlan = vlan;
2210         return rc;
2211 }
2212
2213 static int
2214 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2215 {
2216         struct bnxt *bp = dev->data->dev_private;
2217         int rc;
2218
2219         rc = is_bnxt_in_error(bp);
2220         if (rc)
2221                 return rc;
2222
2223         return bnxt_hwrm_port_led_cfg(bp, true);
2224 }
2225
2226 static int
2227 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2228 {
2229         struct bnxt *bp = dev->data->dev_private;
2230         int rc;
2231
2232         rc = is_bnxt_in_error(bp);
2233         if (rc)
2234                 return rc;
2235
2236         return bnxt_hwrm_port_led_cfg(bp, false);
2237 }
2238
2239 static uint32_t
2240 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2241 {
2242         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2243         uint32_t desc = 0, raw_cons = 0, cons;
2244         struct bnxt_cp_ring_info *cpr;
2245         struct bnxt_rx_queue *rxq;
2246         struct rx_pkt_cmpl *rxcmp;
2247         int rc;
2248
2249         rc = is_bnxt_in_error(bp);
2250         if (rc)
2251                 return rc;
2252
2253         rxq = dev->data->rx_queues[rx_queue_id];
2254         cpr = rxq->cp_ring;
2255         raw_cons = cpr->cp_raw_cons;
2256
2257         while (1) {
2258                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2259                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2260                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2261
2262                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2263                         break;
2264                 } else {
2265                         raw_cons++;
2266                         desc++;
2267                 }
2268         }
2269
2270         return desc;
2271 }
2272
2273 static int
2274 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2275 {
2276         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2277         struct bnxt_rx_ring_info *rxr;
2278         struct bnxt_cp_ring_info *cpr;
2279         struct bnxt_sw_rx_bd *rx_buf;
2280         struct rx_pkt_cmpl *rxcmp;
2281         uint32_t cons, cp_cons;
2282         int rc;
2283
2284         if (!rxq)
2285                 return -EINVAL;
2286
2287         rc = is_bnxt_in_error(rxq->bp);
2288         if (rc)
2289                 return rc;
2290
2291         cpr = rxq->cp_ring;
2292         rxr = rxq->rx_ring;
2293
2294         if (offset >= rxq->nb_rx_desc)
2295                 return -EINVAL;
2296
2297         cons = RING_CMP(cpr->cp_ring_struct, offset);
2298         cp_cons = cpr->cp_raw_cons;
2299         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2300
2301         if (cons > cp_cons) {
2302                 if (CMPL_VALID(rxcmp, cpr->valid))
2303                         return RTE_ETH_RX_DESC_DONE;
2304         } else {
2305                 if (CMPL_VALID(rxcmp, !cpr->valid))
2306                         return RTE_ETH_RX_DESC_DONE;
2307         }
2308         rx_buf = &rxr->rx_buf_ring[cons];
2309         if (rx_buf->mbuf == NULL)
2310                 return RTE_ETH_RX_DESC_UNAVAIL;
2311
2312
2313         return RTE_ETH_RX_DESC_AVAIL;
2314 }
2315
2316 static int
2317 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2318 {
2319         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2320         struct bnxt_tx_ring_info *txr;
2321         struct bnxt_cp_ring_info *cpr;
2322         struct bnxt_sw_tx_bd *tx_buf;
2323         struct tx_pkt_cmpl *txcmp;
2324         uint32_t cons, cp_cons;
2325         int rc;
2326
2327         if (!txq)
2328                 return -EINVAL;
2329
2330         rc = is_bnxt_in_error(txq->bp);
2331         if (rc)
2332                 return rc;
2333
2334         cpr = txq->cp_ring;
2335         txr = txq->tx_ring;
2336
2337         if (offset >= txq->nb_tx_desc)
2338                 return -EINVAL;
2339
2340         cons = RING_CMP(cpr->cp_ring_struct, offset);
2341         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2342         cp_cons = cpr->cp_raw_cons;
2343
2344         if (cons > cp_cons) {
2345                 if (CMPL_VALID(txcmp, cpr->valid))
2346                         return RTE_ETH_TX_DESC_UNAVAIL;
2347         } else {
2348                 if (CMPL_VALID(txcmp, !cpr->valid))
2349                         return RTE_ETH_TX_DESC_UNAVAIL;
2350         }
2351         tx_buf = &txr->tx_buf_ring[cons];
2352         if (tx_buf->mbuf == NULL)
2353                 return RTE_ETH_TX_DESC_DONE;
2354
2355         return RTE_ETH_TX_DESC_FULL;
2356 }
2357
2358 static struct bnxt_filter_info *
2359 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2360                                 struct rte_eth_ethertype_filter *efilter,
2361                                 struct bnxt_vnic_info *vnic0,
2362                                 struct bnxt_vnic_info *vnic,
2363                                 int *ret)
2364 {
2365         struct bnxt_filter_info *mfilter = NULL;
2366         int match = 0;
2367         *ret = 0;
2368
2369         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2370                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2371                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2372                         " ethertype filter.", efilter->ether_type);
2373                 *ret = -EINVAL;
2374                 goto exit;
2375         }
2376         if (efilter->queue >= bp->rx_nr_rings) {
2377                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2378                 *ret = -EINVAL;
2379                 goto exit;
2380         }
2381
2382         vnic0 = &bp->vnic_info[0];
2383         vnic = &bp->vnic_info[efilter->queue];
2384         if (vnic == NULL) {
2385                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2386                 *ret = -EINVAL;
2387                 goto exit;
2388         }
2389
2390         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2391                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2392                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2393                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2394                              mfilter->flags ==
2395                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2396                              mfilter->ethertype == efilter->ether_type)) {
2397                                 match = 1;
2398                                 break;
2399                         }
2400                 }
2401         } else {
2402                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2403                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2404                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2405                              mfilter->ethertype == efilter->ether_type &&
2406                              mfilter->flags ==
2407                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2408                                 match = 1;
2409                                 break;
2410                         }
2411         }
2412
2413         if (match)
2414                 *ret = -EEXIST;
2415
2416 exit:
2417         return mfilter;
2418 }
2419
2420 static int
2421 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2422                         enum rte_filter_op filter_op,
2423                         void *arg)
2424 {
2425         struct bnxt *bp = dev->data->dev_private;
2426         struct rte_eth_ethertype_filter *efilter =
2427                         (struct rte_eth_ethertype_filter *)arg;
2428         struct bnxt_filter_info *bfilter, *filter1;
2429         struct bnxt_vnic_info *vnic, *vnic0;
2430         int ret;
2431
2432         if (filter_op == RTE_ETH_FILTER_NOP)
2433                 return 0;
2434
2435         if (arg == NULL) {
2436                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2437                             filter_op);
2438                 return -EINVAL;
2439         }
2440
2441         vnic0 = &bp->vnic_info[0];
2442         vnic = &bp->vnic_info[efilter->queue];
2443
2444         switch (filter_op) {
2445         case RTE_ETH_FILTER_ADD:
2446                 bnxt_match_and_validate_ether_filter(bp, efilter,
2447                                                         vnic0, vnic, &ret);
2448                 if (ret < 0)
2449                         return ret;
2450
2451                 bfilter = bnxt_get_unused_filter(bp);
2452                 if (bfilter == NULL) {
2453                         PMD_DRV_LOG(ERR,
2454                                 "Not enough resources for a new filter.\n");
2455                         return -ENOMEM;
2456                 }
2457                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2458                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2459                        RTE_ETHER_ADDR_LEN);
2460                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2461                        RTE_ETHER_ADDR_LEN);
2462                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2463                 bfilter->ethertype = efilter->ether_type;
2464                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2465
2466                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2467                 if (filter1 == NULL) {
2468                         ret = -EINVAL;
2469                         goto cleanup;
2470                 }
2471                 bfilter->enables |=
2472                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2473                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2474
2475                 bfilter->dst_id = vnic->fw_vnic_id;
2476
2477                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2478                         bfilter->flags =
2479                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2480                 }
2481
2482                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2483                 if (ret)
2484                         goto cleanup;
2485                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2486                 break;
2487         case RTE_ETH_FILTER_DELETE:
2488                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2489                                                         vnic0, vnic, &ret);
2490                 if (ret == -EEXIST) {
2491                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2492
2493                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2494                                       next);
2495                         bnxt_free_filter(bp, filter1);
2496                 } else if (ret == 0) {
2497                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2498                 }
2499                 break;
2500         default:
2501                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2502                 ret = -EINVAL;
2503                 goto error;
2504         }
2505         return ret;
2506 cleanup:
2507         bnxt_free_filter(bp, bfilter);
2508 error:
2509         return ret;
2510 }
2511
2512 static inline int
2513 parse_ntuple_filter(struct bnxt *bp,
2514                     struct rte_eth_ntuple_filter *nfilter,
2515                     struct bnxt_filter_info *bfilter)
2516 {
2517         uint32_t en = 0;
2518
2519         if (nfilter->queue >= bp->rx_nr_rings) {
2520                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2521                 return -EINVAL;
2522         }
2523
2524         switch (nfilter->dst_port_mask) {
2525         case UINT16_MAX:
2526                 bfilter->dst_port_mask = -1;
2527                 bfilter->dst_port = nfilter->dst_port;
2528                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2529                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2530                 break;
2531         default:
2532                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2533                 return -EINVAL;
2534         }
2535
2536         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2537         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2538
2539         switch (nfilter->proto_mask) {
2540         case UINT8_MAX:
2541                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2542                         bfilter->ip_protocol = 17;
2543                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2544                         bfilter->ip_protocol = 6;
2545                 else
2546                         return -EINVAL;
2547                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2548                 break;
2549         default:
2550                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2551                 return -EINVAL;
2552         }
2553
2554         switch (nfilter->dst_ip_mask) {
2555         case UINT32_MAX:
2556                 bfilter->dst_ipaddr_mask[0] = -1;
2557                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2558                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2559                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2560                 break;
2561         default:
2562                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2563                 return -EINVAL;
2564         }
2565
2566         switch (nfilter->src_ip_mask) {
2567         case UINT32_MAX:
2568                 bfilter->src_ipaddr_mask[0] = -1;
2569                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2570                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2571                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2572                 break;
2573         default:
2574                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2575                 return -EINVAL;
2576         }
2577
2578         switch (nfilter->src_port_mask) {
2579         case UINT16_MAX:
2580                 bfilter->src_port_mask = -1;
2581                 bfilter->src_port = nfilter->src_port;
2582                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2583                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2584                 break;
2585         default:
2586                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2587                 return -EINVAL;
2588         }
2589
2590         bfilter->enables = en;
2591         return 0;
2592 }
2593
2594 static struct bnxt_filter_info*
2595 bnxt_match_ntuple_filter(struct bnxt *bp,
2596                          struct bnxt_filter_info *bfilter,
2597                          struct bnxt_vnic_info **mvnic)
2598 {
2599         struct bnxt_filter_info *mfilter = NULL;
2600         int i;
2601
2602         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2603                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2604                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2605                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2606                             bfilter->src_ipaddr_mask[0] ==
2607                             mfilter->src_ipaddr_mask[0] &&
2608                             bfilter->src_port == mfilter->src_port &&
2609                             bfilter->src_port_mask == mfilter->src_port_mask &&
2610                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2611                             bfilter->dst_ipaddr_mask[0] ==
2612                             mfilter->dst_ipaddr_mask[0] &&
2613                             bfilter->dst_port == mfilter->dst_port &&
2614                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2615                             bfilter->flags == mfilter->flags &&
2616                             bfilter->enables == mfilter->enables) {
2617                                 if (mvnic)
2618                                         *mvnic = vnic;
2619                                 return mfilter;
2620                         }
2621                 }
2622         }
2623         return NULL;
2624 }
2625
2626 static int
2627 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2628                        struct rte_eth_ntuple_filter *nfilter,
2629                        enum rte_filter_op filter_op)
2630 {
2631         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2632         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2633         int ret;
2634
2635         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2636                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2637                 return -EINVAL;
2638         }
2639
2640         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2641                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2642                 return -EINVAL;
2643         }
2644
2645         bfilter = bnxt_get_unused_filter(bp);
2646         if (bfilter == NULL) {
2647                 PMD_DRV_LOG(ERR,
2648                         "Not enough resources for a new filter.\n");
2649                 return -ENOMEM;
2650         }
2651         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2652         if (ret < 0)
2653                 goto free_filter;
2654
2655         vnic = &bp->vnic_info[nfilter->queue];
2656         vnic0 = &bp->vnic_info[0];
2657         filter1 = STAILQ_FIRST(&vnic0->filter);
2658         if (filter1 == NULL) {
2659                 ret = -EINVAL;
2660                 goto free_filter;
2661         }
2662
2663         bfilter->dst_id = vnic->fw_vnic_id;
2664         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2665         bfilter->enables |=
2666                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2667         bfilter->ethertype = 0x800;
2668         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2669
2670         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2671
2672         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2673             bfilter->dst_id == mfilter->dst_id) {
2674                 PMD_DRV_LOG(ERR, "filter exists.\n");
2675                 ret = -EEXIST;
2676                 goto free_filter;
2677         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2678                    bfilter->dst_id != mfilter->dst_id) {
2679                 mfilter->dst_id = vnic->fw_vnic_id;
2680                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2681                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2682                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2683                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2684                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2685                 goto free_filter;
2686         }
2687         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2688                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2689                 ret = -ENOENT;
2690                 goto free_filter;
2691         }
2692
2693         if (filter_op == RTE_ETH_FILTER_ADD) {
2694                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2695                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2696                 if (ret)
2697                         goto free_filter;
2698                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2699         } else {
2700                 if (mfilter == NULL) {
2701                         /* This should not happen. But for Coverity! */
2702                         ret = -ENOENT;
2703                         goto free_filter;
2704                 }
2705                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2706
2707                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2708                 bnxt_free_filter(bp, mfilter);
2709                 mfilter->fw_l2_filter_id = -1;
2710                 bnxt_free_filter(bp, bfilter);
2711                 bfilter->fw_l2_filter_id = -1;
2712         }
2713
2714         return 0;
2715 free_filter:
2716         bfilter->fw_l2_filter_id = -1;
2717         bnxt_free_filter(bp, bfilter);
2718         return ret;
2719 }
2720
2721 static int
2722 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2723                         enum rte_filter_op filter_op,
2724                         void *arg)
2725 {
2726         struct bnxt *bp = dev->data->dev_private;
2727         int ret;
2728
2729         if (filter_op == RTE_ETH_FILTER_NOP)
2730                 return 0;
2731
2732         if (arg == NULL) {
2733                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2734                             filter_op);
2735                 return -EINVAL;
2736         }
2737
2738         switch (filter_op) {
2739         case RTE_ETH_FILTER_ADD:
2740                 ret = bnxt_cfg_ntuple_filter(bp,
2741                         (struct rte_eth_ntuple_filter *)arg,
2742                         filter_op);
2743                 break;
2744         case RTE_ETH_FILTER_DELETE:
2745                 ret = bnxt_cfg_ntuple_filter(bp,
2746                         (struct rte_eth_ntuple_filter *)arg,
2747                         filter_op);
2748                 break;
2749         default:
2750                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2751                 ret = -EINVAL;
2752                 break;
2753         }
2754         return ret;
2755 }
2756
2757 static int
2758 bnxt_parse_fdir_filter(struct bnxt *bp,
2759                        struct rte_eth_fdir_filter *fdir,
2760                        struct bnxt_filter_info *filter)
2761 {
2762         enum rte_fdir_mode fdir_mode =
2763                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2764         struct bnxt_vnic_info *vnic0, *vnic;
2765         struct bnxt_filter_info *filter1;
2766         uint32_t en = 0;
2767         int i;
2768
2769         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2770                 return -EINVAL;
2771
2772         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2773         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2774
2775         switch (fdir->input.flow_type) {
2776         case RTE_ETH_FLOW_IPV4:
2777         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2778                 /* FALLTHROUGH */
2779                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2780                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2781                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2782                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2783                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2784                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2785                 filter->ip_addr_type =
2786                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2787                 filter->src_ipaddr_mask[0] = 0xffffffff;
2788                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2789                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2790                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2791                 filter->ethertype = 0x800;
2792                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2793                 break;
2794         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2795                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2796                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2797                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2798                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2799                 filter->dst_port_mask = 0xffff;
2800                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2801                 filter->src_port_mask = 0xffff;
2802                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2803                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2804                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2805                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2806                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2807                 filter->ip_protocol = 6;
2808                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2809                 filter->ip_addr_type =
2810                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2811                 filter->src_ipaddr_mask[0] = 0xffffffff;
2812                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2813                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2814                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2815                 filter->ethertype = 0x800;
2816                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2817                 break;
2818         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2819                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2820                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2821                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2822                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2823                 filter->dst_port_mask = 0xffff;
2824                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2825                 filter->src_port_mask = 0xffff;
2826                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2827                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2828                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2829                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2830                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2831                 filter->ip_protocol = 17;
2832                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2833                 filter->ip_addr_type =
2834                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2835                 filter->src_ipaddr_mask[0] = 0xffffffff;
2836                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2837                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2838                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2839                 filter->ethertype = 0x800;
2840                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2841                 break;
2842         case RTE_ETH_FLOW_IPV6:
2843         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2844                 /* FALLTHROUGH */
2845                 filter->ip_addr_type =
2846                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2847                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2848                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2849                 rte_memcpy(filter->src_ipaddr,
2850                            fdir->input.flow.ipv6_flow.src_ip, 16);
2851                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2852                 rte_memcpy(filter->dst_ipaddr,
2853                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2854                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2855                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2856                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2857                 memset(filter->src_ipaddr_mask, 0xff, 16);
2858                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2859                 filter->ethertype = 0x86dd;
2860                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2861                 break;
2862         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2863                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2864                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2865                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2866                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2867                 filter->dst_port_mask = 0xffff;
2868                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2869                 filter->src_port_mask = 0xffff;
2870                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2871                 filter->ip_addr_type =
2872                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2873                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2874                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2875                 rte_memcpy(filter->src_ipaddr,
2876                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2877                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2878                 rte_memcpy(filter->dst_ipaddr,
2879                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2880                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2881                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2882                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2883                 memset(filter->src_ipaddr_mask, 0xff, 16);
2884                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2885                 filter->ethertype = 0x86dd;
2886                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2887                 break;
2888         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2889                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2890                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2891                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2892                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2893                 filter->dst_port_mask = 0xffff;
2894                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2895                 filter->src_port_mask = 0xffff;
2896                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2897                 filter->ip_addr_type =
2898                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2899                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2900                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2901                 rte_memcpy(filter->src_ipaddr,
2902                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2903                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2904                 rte_memcpy(filter->dst_ipaddr,
2905                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2906                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2907                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2908                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2909                 memset(filter->src_ipaddr_mask, 0xff, 16);
2910                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2911                 filter->ethertype = 0x86dd;
2912                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2913                 break;
2914         case RTE_ETH_FLOW_L2_PAYLOAD:
2915                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2916                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2917                 break;
2918         case RTE_ETH_FLOW_VXLAN:
2919                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2920                         return -EINVAL;
2921                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2922                 filter->tunnel_type =
2923                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2924                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2925                 break;
2926         case RTE_ETH_FLOW_NVGRE:
2927                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2928                         return -EINVAL;
2929                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2930                 filter->tunnel_type =
2931                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2932                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2933                 break;
2934         case RTE_ETH_FLOW_UNKNOWN:
2935         case RTE_ETH_FLOW_RAW:
2936         case RTE_ETH_FLOW_FRAG_IPV4:
2937         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2938         case RTE_ETH_FLOW_FRAG_IPV6:
2939         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2940         case RTE_ETH_FLOW_IPV6_EX:
2941         case RTE_ETH_FLOW_IPV6_TCP_EX:
2942         case RTE_ETH_FLOW_IPV6_UDP_EX:
2943         case RTE_ETH_FLOW_GENEVE:
2944                 /* FALLTHROUGH */
2945         default:
2946                 return -EINVAL;
2947         }
2948
2949         vnic0 = &bp->vnic_info[0];
2950         vnic = &bp->vnic_info[fdir->action.rx_queue];
2951         if (vnic == NULL) {
2952                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2953                 return -EINVAL;
2954         }
2955
2956         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2957                 rte_memcpy(filter->dst_macaddr,
2958                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2959                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2960         }
2961
2962         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2963                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2964                 filter1 = STAILQ_FIRST(&vnic0->filter);
2965                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2966         } else {
2967                 filter->dst_id = vnic->fw_vnic_id;
2968                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2969                         if (filter->dst_macaddr[i] == 0x00)
2970                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2971                         else
2972                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2973         }
2974
2975         if (filter1 == NULL)
2976                 return -EINVAL;
2977
2978         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2979         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2980
2981         filter->enables = en;
2982
2983         return 0;
2984 }
2985
2986 static struct bnxt_filter_info *
2987 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2988                 struct bnxt_vnic_info **mvnic)
2989 {
2990         struct bnxt_filter_info *mf = NULL;
2991         int i;
2992
2993         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2994                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2995
2996                 STAILQ_FOREACH(mf, &vnic->filter, next) {
2997                         if (mf->filter_type == nf->filter_type &&
2998                             mf->flags == nf->flags &&
2999                             mf->src_port == nf->src_port &&
3000                             mf->src_port_mask == nf->src_port_mask &&
3001                             mf->dst_port == nf->dst_port &&
3002                             mf->dst_port_mask == nf->dst_port_mask &&
3003                             mf->ip_protocol == nf->ip_protocol &&
3004                             mf->ip_addr_type == nf->ip_addr_type &&
3005                             mf->ethertype == nf->ethertype &&
3006                             mf->vni == nf->vni &&
3007                             mf->tunnel_type == nf->tunnel_type &&
3008                             mf->l2_ovlan == nf->l2_ovlan &&
3009                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3010                             mf->l2_ivlan == nf->l2_ivlan &&
3011                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3012                             !memcmp(mf->l2_addr, nf->l2_addr,
3013                                     RTE_ETHER_ADDR_LEN) &&
3014                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3015                                     RTE_ETHER_ADDR_LEN) &&
3016                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3017                                     RTE_ETHER_ADDR_LEN) &&
3018                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3019                                     RTE_ETHER_ADDR_LEN) &&
3020                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3021                                     sizeof(nf->src_ipaddr)) &&
3022                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3023                                     sizeof(nf->src_ipaddr_mask)) &&
3024                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3025                                     sizeof(nf->dst_ipaddr)) &&
3026                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3027                                     sizeof(nf->dst_ipaddr_mask))) {
3028                                 if (mvnic)
3029                                         *mvnic = vnic;
3030                                 return mf;
3031                         }
3032                 }
3033         }
3034         return NULL;
3035 }
3036
3037 static int
3038 bnxt_fdir_filter(struct rte_eth_dev *dev,
3039                  enum rte_filter_op filter_op,
3040                  void *arg)
3041 {
3042         struct bnxt *bp = dev->data->dev_private;
3043         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3044         struct bnxt_filter_info *filter, *match;
3045         struct bnxt_vnic_info *vnic, *mvnic;
3046         int ret = 0, i;
3047
3048         if (filter_op == RTE_ETH_FILTER_NOP)
3049                 return 0;
3050
3051         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3052                 return -EINVAL;
3053
3054         switch (filter_op) {
3055         case RTE_ETH_FILTER_ADD:
3056         case RTE_ETH_FILTER_DELETE:
3057                 /* FALLTHROUGH */
3058                 filter = bnxt_get_unused_filter(bp);
3059                 if (filter == NULL) {
3060                         PMD_DRV_LOG(ERR,
3061                                 "Not enough resources for a new flow.\n");
3062                         return -ENOMEM;
3063                 }
3064
3065                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3066                 if (ret != 0)
3067                         goto free_filter;
3068                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3069
3070                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3071                         vnic = &bp->vnic_info[0];
3072                 else
3073                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3074
3075                 match = bnxt_match_fdir(bp, filter, &mvnic);
3076                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3077                         if (match->dst_id == vnic->fw_vnic_id) {
3078                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3079                                 ret = -EEXIST;
3080                                 goto free_filter;
3081                         } else {
3082                                 match->dst_id = vnic->fw_vnic_id;
3083                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3084                                                                   match->dst_id,
3085                                                                   match);
3086                                 STAILQ_REMOVE(&mvnic->filter, match,
3087                                               bnxt_filter_info, next);
3088                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3089                                 PMD_DRV_LOG(ERR,
3090                                         "Filter with matching pattern exist\n");
3091                                 PMD_DRV_LOG(ERR,
3092                                         "Updated it to new destination q\n");
3093                                 goto free_filter;
3094                         }
3095                 }
3096                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3097                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3098                         ret = -ENOENT;
3099                         goto free_filter;
3100                 }
3101
3102                 if (filter_op == RTE_ETH_FILTER_ADD) {
3103                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3104                                                           filter->dst_id,
3105                                                           filter);
3106                         if (ret)
3107                                 goto free_filter;
3108                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3109                 } else {
3110                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3111                         STAILQ_REMOVE(&vnic->filter, match,
3112                                       bnxt_filter_info, next);
3113                         bnxt_free_filter(bp, match);
3114                         filter->fw_l2_filter_id = -1;
3115                         bnxt_free_filter(bp, filter);
3116                 }
3117                 break;
3118         case RTE_ETH_FILTER_FLUSH:
3119                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3120                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3121
3122                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3123                                 if (filter->filter_type ==
3124                                     HWRM_CFA_NTUPLE_FILTER) {
3125                                         ret =
3126                                         bnxt_hwrm_clear_ntuple_filter(bp,
3127                                                                       filter);
3128                                         STAILQ_REMOVE(&vnic->filter, filter,
3129                                                       bnxt_filter_info, next);
3130                                 }
3131                         }
3132                 }
3133                 return ret;
3134         case RTE_ETH_FILTER_UPDATE:
3135         case RTE_ETH_FILTER_STATS:
3136         case RTE_ETH_FILTER_INFO:
3137                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3138                 break;
3139         default:
3140                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3141                 ret = -EINVAL;
3142                 break;
3143         }
3144         return ret;
3145
3146 free_filter:
3147         filter->fw_l2_filter_id = -1;
3148         bnxt_free_filter(bp, filter);
3149         return ret;
3150 }
3151
3152 static int
3153 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
3154                     enum rte_filter_type filter_type,
3155                     enum rte_filter_op filter_op, void *arg)
3156 {
3157         int ret = 0;
3158
3159         ret = is_bnxt_in_error(dev->data->dev_private);
3160         if (ret)
3161                 return ret;
3162
3163         switch (filter_type) {
3164         case RTE_ETH_FILTER_TUNNEL:
3165                 PMD_DRV_LOG(ERR,
3166                         "filter type: %d: To be implemented\n", filter_type);
3167                 break;
3168         case RTE_ETH_FILTER_FDIR:
3169                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3170                 break;
3171         case RTE_ETH_FILTER_NTUPLE:
3172                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3173                 break;
3174         case RTE_ETH_FILTER_ETHERTYPE:
3175                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3176                 break;
3177         case RTE_ETH_FILTER_GENERIC:
3178                 if (filter_op != RTE_ETH_FILTER_GET)
3179                         return -EINVAL;
3180                 *(const void **)arg = &bnxt_flow_ops;
3181                 break;
3182         default:
3183                 PMD_DRV_LOG(ERR,
3184                         "Filter type (%d) not supported", filter_type);
3185                 ret = -EINVAL;
3186                 break;
3187         }
3188         return ret;
3189 }
3190
3191 static const uint32_t *
3192 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3193 {
3194         static const uint32_t ptypes[] = {
3195                 RTE_PTYPE_L2_ETHER_VLAN,
3196                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3197                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3198                 RTE_PTYPE_L4_ICMP,
3199                 RTE_PTYPE_L4_TCP,
3200                 RTE_PTYPE_L4_UDP,
3201                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3202                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3203                 RTE_PTYPE_INNER_L4_ICMP,
3204                 RTE_PTYPE_INNER_L4_TCP,
3205                 RTE_PTYPE_INNER_L4_UDP,
3206                 RTE_PTYPE_UNKNOWN
3207         };
3208
3209         if (!dev->rx_pkt_burst)
3210                 return NULL;
3211
3212         return ptypes;
3213 }
3214
3215 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3216                          int reg_win)
3217 {
3218         uint32_t reg_base = *reg_arr & 0xfffff000;
3219         uint32_t win_off;
3220         int i;
3221
3222         for (i = 0; i < count; i++) {
3223                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3224                         return -ERANGE;
3225         }
3226         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3227         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3228         return 0;
3229 }
3230
3231 static int bnxt_map_ptp_regs(struct bnxt *bp)
3232 {
3233         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3234         uint32_t *reg_arr;
3235         int rc, i;
3236
3237         reg_arr = ptp->rx_regs;
3238         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3239         if (rc)
3240                 return rc;
3241
3242         reg_arr = ptp->tx_regs;
3243         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3244         if (rc)
3245                 return rc;
3246
3247         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3248                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3249
3250         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3251                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3252
3253         return 0;
3254 }
3255
3256 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3257 {
3258         rte_write32(0, (uint8_t *)bp->bar0 +
3259                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3260         rte_write32(0, (uint8_t *)bp->bar0 +
3261                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3262 }
3263
3264 static uint64_t bnxt_cc_read(struct bnxt *bp)
3265 {
3266         uint64_t ns;
3267
3268         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3269                               BNXT_GRCPF_REG_SYNC_TIME));
3270         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3271                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3272         return ns;
3273 }
3274
3275 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3276 {
3277         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3278         uint32_t fifo;
3279
3280         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3281                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3282         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3283                 return -EAGAIN;
3284
3285         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3286                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3287         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3288                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3289         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3290                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3291
3292         return 0;
3293 }
3294
3295 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3296 {
3297         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3298         struct bnxt_pf_info *pf = &bp->pf;
3299         uint16_t port_id;
3300         uint32_t fifo;
3301
3302         if (!ptp)
3303                 return -ENODEV;
3304
3305         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3306                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3307         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3308                 return -EAGAIN;
3309
3310         port_id = pf->port_id;
3311         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3312                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3313
3314         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3315                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3316         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3317 /*              bnxt_clr_rx_ts(bp);       TBD  */
3318                 return -EBUSY;
3319         }
3320
3321         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3322                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3323         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3324                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3325
3326         return 0;
3327 }
3328
3329 static int
3330 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3331 {
3332         uint64_t ns;
3333         struct bnxt *bp = dev->data->dev_private;
3334         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3335
3336         if (!ptp)
3337                 return 0;
3338
3339         ns = rte_timespec_to_ns(ts);
3340         /* Set the timecounters to a new value. */
3341         ptp->tc.nsec = ns;
3342
3343         return 0;
3344 }
3345
3346 static int
3347 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3348 {
3349         struct bnxt *bp = dev->data->dev_private;
3350         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3351         uint64_t ns, systime_cycles = 0;
3352         int rc = 0;
3353
3354         if (!ptp)
3355                 return 0;
3356
3357         if (BNXT_CHIP_THOR(bp))
3358                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3359                                              &systime_cycles);
3360         else
3361                 systime_cycles = bnxt_cc_read(bp);
3362
3363         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3364         *ts = rte_ns_to_timespec(ns);
3365
3366         return rc;
3367 }
3368 static int
3369 bnxt_timesync_enable(struct rte_eth_dev *dev)
3370 {
3371         struct bnxt *bp = dev->data->dev_private;
3372         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3373         uint32_t shift = 0;
3374         int rc;
3375
3376         if (!ptp)
3377                 return 0;
3378
3379         ptp->rx_filter = 1;
3380         ptp->tx_tstamp_en = 1;
3381         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3382
3383         rc = bnxt_hwrm_ptp_cfg(bp);
3384         if (rc)
3385                 return rc;
3386
3387         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3388         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3389         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3390
3391         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3392         ptp->tc.cc_shift = shift;
3393         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3394
3395         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3396         ptp->rx_tstamp_tc.cc_shift = shift;
3397         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3398
3399         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3400         ptp->tx_tstamp_tc.cc_shift = shift;
3401         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3402
3403         if (!BNXT_CHIP_THOR(bp))
3404                 bnxt_map_ptp_regs(bp);
3405
3406         return 0;
3407 }
3408
3409 static int
3410 bnxt_timesync_disable(struct rte_eth_dev *dev)
3411 {
3412         struct bnxt *bp = dev->data->dev_private;
3413         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3414
3415         if (!ptp)
3416                 return 0;
3417
3418         ptp->rx_filter = 0;
3419         ptp->tx_tstamp_en = 0;
3420         ptp->rxctl = 0;
3421
3422         bnxt_hwrm_ptp_cfg(bp);
3423
3424         if (!BNXT_CHIP_THOR(bp))
3425                 bnxt_unmap_ptp_regs(bp);
3426
3427         return 0;
3428 }
3429
3430 static int
3431 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3432                                  struct timespec *timestamp,
3433                                  uint32_t flags __rte_unused)
3434 {
3435         struct bnxt *bp = dev->data->dev_private;
3436         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3437         uint64_t rx_tstamp_cycles = 0;
3438         uint64_t ns;
3439
3440         if (!ptp)
3441                 return 0;
3442
3443         if (BNXT_CHIP_THOR(bp))
3444                 rx_tstamp_cycles = ptp->rx_timestamp;
3445         else
3446                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3447
3448         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3449         *timestamp = rte_ns_to_timespec(ns);
3450         return  0;
3451 }
3452
3453 static int
3454 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3455                                  struct timespec *timestamp)
3456 {
3457         struct bnxt *bp = dev->data->dev_private;
3458         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3459         uint64_t tx_tstamp_cycles = 0;
3460         uint64_t ns;
3461         int rc = 0;
3462
3463         if (!ptp)
3464                 return 0;
3465
3466         if (BNXT_CHIP_THOR(bp))
3467                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3468                                              &tx_tstamp_cycles);
3469         else
3470                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3471
3472         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3473         *timestamp = rte_ns_to_timespec(ns);
3474
3475         return rc;
3476 }
3477
3478 static int
3479 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3480 {
3481         struct bnxt *bp = dev->data->dev_private;
3482         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3483
3484         if (!ptp)
3485                 return 0;
3486
3487         ptp->tc.nsec += delta;
3488
3489         return 0;
3490 }
3491
3492 static int
3493 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3494 {
3495         struct bnxt *bp = dev->data->dev_private;
3496         int rc;
3497         uint32_t dir_entries;
3498         uint32_t entry_length;
3499
3500         rc = is_bnxt_in_error(bp);
3501         if (rc)
3502                 return rc;
3503
3504         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3505                 bp->pdev->addr.domain, bp->pdev->addr.bus,
3506                 bp->pdev->addr.devid, bp->pdev->addr.function);
3507
3508         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3509         if (rc != 0)
3510                 return rc;
3511
3512         return dir_entries * entry_length;
3513 }
3514
3515 static int
3516 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3517                 struct rte_dev_eeprom_info *in_eeprom)
3518 {
3519         struct bnxt *bp = dev->data->dev_private;
3520         uint32_t index;
3521         uint32_t offset;
3522         int rc;
3523
3524         rc = is_bnxt_in_error(bp);
3525         if (rc)
3526                 return rc;
3527
3528         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3529                 "len = %d\n", bp->pdev->addr.domain,
3530                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3531                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3532
3533         if (in_eeprom->offset == 0) /* special offset value to get directory */
3534                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3535                                                 in_eeprom->data);
3536
3537         index = in_eeprom->offset >> 24;
3538         offset = in_eeprom->offset & 0xffffff;
3539
3540         if (index != 0)
3541                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3542                                            in_eeprom->length, in_eeprom->data);
3543
3544         return 0;
3545 }
3546
3547 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3548 {
3549         switch (dir_type) {
3550         case BNX_DIR_TYPE_CHIMP_PATCH:
3551         case BNX_DIR_TYPE_BOOTCODE:
3552         case BNX_DIR_TYPE_BOOTCODE_2:
3553         case BNX_DIR_TYPE_APE_FW:
3554         case BNX_DIR_TYPE_APE_PATCH:
3555         case BNX_DIR_TYPE_KONG_FW:
3556         case BNX_DIR_TYPE_KONG_PATCH:
3557         case BNX_DIR_TYPE_BONO_FW:
3558         case BNX_DIR_TYPE_BONO_PATCH:
3559                 /* FALLTHROUGH */
3560                 return true;
3561         }
3562
3563         return false;
3564 }
3565
3566 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3567 {
3568         switch (dir_type) {
3569         case BNX_DIR_TYPE_AVS:
3570         case BNX_DIR_TYPE_EXP_ROM_MBA:
3571         case BNX_DIR_TYPE_PCIE:
3572         case BNX_DIR_TYPE_TSCF_UCODE:
3573         case BNX_DIR_TYPE_EXT_PHY:
3574         case BNX_DIR_TYPE_CCM:
3575         case BNX_DIR_TYPE_ISCSI_BOOT:
3576         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3577         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3578                 /* FALLTHROUGH */
3579                 return true;
3580         }
3581
3582         return false;
3583 }
3584
3585 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3586 {
3587         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3588                 bnxt_dir_type_is_other_exec_format(dir_type);
3589 }
3590
3591 static int
3592 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3593                 struct rte_dev_eeprom_info *in_eeprom)
3594 {
3595         struct bnxt *bp = dev->data->dev_private;
3596         uint8_t index, dir_op;
3597         uint16_t type, ext, ordinal, attr;
3598         int rc;
3599
3600         rc = is_bnxt_in_error(bp);
3601         if (rc)
3602                 return rc;
3603
3604         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3605                 "len = %d\n", bp->pdev->addr.domain,
3606                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3607                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3608
3609         if (!BNXT_PF(bp)) {
3610                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3611                 return -EINVAL;
3612         }
3613
3614         type = in_eeprom->magic >> 16;
3615
3616         if (type == 0xffff) { /* special value for directory operations */
3617                 index = in_eeprom->magic & 0xff;
3618                 dir_op = in_eeprom->magic >> 8;
3619                 if (index == 0)
3620                         return -EINVAL;
3621                 switch (dir_op) {
3622                 case 0x0e: /* erase */
3623                         if (in_eeprom->offset != ~in_eeprom->magic)
3624                                 return -EINVAL;
3625                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3626                 default:
3627                         return -EINVAL;
3628                 }
3629         }
3630
3631         /* Create or re-write an NVM item: */
3632         if (bnxt_dir_type_is_executable(type) == true)
3633                 return -EOPNOTSUPP;
3634         ext = in_eeprom->magic & 0xffff;
3635         ordinal = in_eeprom->offset >> 16;
3636         attr = in_eeprom->offset & 0xffff;
3637
3638         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3639                                      in_eeprom->data, in_eeprom->length);
3640 }
3641
3642 /*
3643  * Initialization
3644  */
3645
3646 static const struct eth_dev_ops bnxt_dev_ops = {
3647         .dev_infos_get = bnxt_dev_info_get_op,
3648         .dev_close = bnxt_dev_close_op,
3649         .dev_configure = bnxt_dev_configure_op,
3650         .dev_start = bnxt_dev_start_op,
3651         .dev_stop = bnxt_dev_stop_op,
3652         .dev_set_link_up = bnxt_dev_set_link_up_op,
3653         .dev_set_link_down = bnxt_dev_set_link_down_op,
3654         .stats_get = bnxt_stats_get_op,
3655         .stats_reset = bnxt_stats_reset_op,
3656         .rx_queue_setup = bnxt_rx_queue_setup_op,
3657         .rx_queue_release = bnxt_rx_queue_release_op,
3658         .tx_queue_setup = bnxt_tx_queue_setup_op,
3659         .tx_queue_release = bnxt_tx_queue_release_op,
3660         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3661         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3662         .reta_update = bnxt_reta_update_op,
3663         .reta_query = bnxt_reta_query_op,
3664         .rss_hash_update = bnxt_rss_hash_update_op,
3665         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3666         .link_update = bnxt_link_update_op,
3667         .promiscuous_enable = bnxt_promiscuous_enable_op,
3668         .promiscuous_disable = bnxt_promiscuous_disable_op,
3669         .allmulticast_enable = bnxt_allmulticast_enable_op,
3670         .allmulticast_disable = bnxt_allmulticast_disable_op,
3671         .mac_addr_add = bnxt_mac_addr_add_op,
3672         .mac_addr_remove = bnxt_mac_addr_remove_op,
3673         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3674         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3675         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3676         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3677         .vlan_filter_set = bnxt_vlan_filter_set_op,
3678         .vlan_offload_set = bnxt_vlan_offload_set_op,
3679         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3680         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3681         .mtu_set = bnxt_mtu_set_op,
3682         .mac_addr_set = bnxt_set_default_mac_addr_op,
3683         .xstats_get = bnxt_dev_xstats_get_op,
3684         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3685         .xstats_reset = bnxt_dev_xstats_reset_op,
3686         .fw_version_get = bnxt_fw_version_get,
3687         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3688         .rxq_info_get = bnxt_rxq_info_get_op,
3689         .txq_info_get = bnxt_txq_info_get_op,
3690         .dev_led_on = bnxt_dev_led_on_op,
3691         .dev_led_off = bnxt_dev_led_off_op,
3692         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3693         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3694         .rx_queue_count = bnxt_rx_queue_count_op,
3695         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3696         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3697         .rx_queue_start = bnxt_rx_queue_start,
3698         .rx_queue_stop = bnxt_rx_queue_stop,
3699         .tx_queue_start = bnxt_tx_queue_start,
3700         .tx_queue_stop = bnxt_tx_queue_stop,
3701         .filter_ctrl = bnxt_filter_ctrl_op,
3702         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3703         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3704         .get_eeprom           = bnxt_get_eeprom_op,
3705         .set_eeprom           = bnxt_set_eeprom_op,
3706         .timesync_enable      = bnxt_timesync_enable,
3707         .timesync_disable     = bnxt_timesync_disable,
3708         .timesync_read_time   = bnxt_timesync_read_time,
3709         .timesync_write_time   = bnxt_timesync_write_time,
3710         .timesync_adjust_time = bnxt_timesync_adjust_time,
3711         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3712         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3713 };
3714
3715 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3716 {
3717         uint32_t offset;
3718
3719         /* Only pre-map the reset GRC registers using window 3 */
3720         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3721                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3722
3723         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3724
3725         return offset;
3726 }
3727
3728 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3729 {
3730         struct bnxt_error_recovery_info *info = bp->recovery_info;
3731         uint32_t reg_base = 0xffffffff;
3732         int i;
3733
3734         /* Only pre-map the monitoring GRC registers using window 2 */
3735         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3736                 uint32_t reg = info->status_regs[i];
3737
3738                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3739                         continue;
3740
3741                 if (reg_base == 0xffffffff)
3742                         reg_base = reg & 0xfffff000;
3743                 if ((reg & 0xfffff000) != reg_base)
3744                         return -ERANGE;
3745
3746                 /* Use mask 0xffc as the Lower 2 bits indicates
3747                  * address space location
3748                  */
3749                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3750                                                 (reg & 0xffc);
3751         }
3752
3753         if (reg_base == 0xffffffff)
3754                 return 0;
3755
3756         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3757                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3758
3759         return 0;
3760 }
3761
3762 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3763 {
3764         struct bnxt_error_recovery_info *info = bp->recovery_info;
3765         uint32_t delay = info->delay_after_reset[index];
3766         uint32_t val = info->reset_reg_val[index];
3767         uint32_t reg = info->reset_reg[index];
3768         uint32_t type, offset;
3769
3770         type = BNXT_FW_STATUS_REG_TYPE(reg);
3771         offset = BNXT_FW_STATUS_REG_OFF(reg);
3772
3773         switch (type) {
3774         case BNXT_FW_STATUS_REG_TYPE_CFG:
3775                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3776                 break;
3777         case BNXT_FW_STATUS_REG_TYPE_GRC:
3778                 offset = bnxt_map_reset_regs(bp, offset);
3779                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3780                 break;
3781         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3782                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3783                 break;
3784         }
3785         /* wait on a specific interval of time until core reset is complete */
3786         if (delay)
3787                 rte_delay_ms(delay);
3788 }
3789
3790 static void bnxt_dev_cleanup(struct bnxt *bp)
3791 {
3792         bnxt_set_hwrm_link_config(bp, false);
3793         bp->link_info.link_up = 0;
3794         if (bp->dev_stopped == 0)
3795                 bnxt_dev_stop_op(bp->eth_dev);
3796
3797         bnxt_uninit_resources(bp, true);
3798 }
3799
3800 static int bnxt_restore_filters(struct bnxt *bp)
3801 {
3802         struct rte_eth_dev *dev = bp->eth_dev;
3803         int ret = 0;
3804
3805         if (dev->data->all_multicast)
3806                 ret = bnxt_allmulticast_enable_op(dev);
3807         if (dev->data->promiscuous)
3808                 ret = bnxt_promiscuous_enable_op(dev);
3809
3810         /* TODO restore other filters as well */
3811         return ret;
3812 }
3813
3814 static void bnxt_dev_recover(void *arg)
3815 {
3816         struct bnxt *bp = arg;
3817         int timeout = bp->fw_reset_max_msecs;
3818         int rc = 0;
3819
3820         /* Clear Error flag so that device re-init should happen */
3821         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3822
3823         do {
3824                 rc = bnxt_hwrm_ver_get(bp);
3825                 if (rc == 0)
3826                         break;
3827                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3828                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3829         } while (rc && timeout);
3830
3831         if (rc) {
3832                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3833                 goto err;
3834         }
3835
3836         rc = bnxt_init_resources(bp, true);
3837         if (rc) {
3838                 PMD_DRV_LOG(ERR,
3839                             "Failed to initialize resources after reset\n");
3840                 goto err;
3841         }
3842         /* clear reset flag as the device is initialized now */
3843         bp->flags &= ~BNXT_FLAG_FW_RESET;
3844
3845         rc = bnxt_dev_start_op(bp->eth_dev);
3846         if (rc) {
3847                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3848                 goto err;
3849         }
3850
3851         rc = bnxt_restore_filters(bp);
3852         if (rc)
3853                 goto err;
3854
3855         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3856         return;
3857 err:
3858         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3859         bnxt_uninit_resources(bp, false);
3860         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3861 }
3862
3863 void bnxt_dev_reset_and_resume(void *arg)
3864 {
3865         struct bnxt *bp = arg;
3866         int rc;
3867
3868         bnxt_dev_cleanup(bp);
3869
3870         bnxt_wait_for_device_shutdown(bp);
3871
3872         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3873                                bnxt_dev_recover, (void *)bp);
3874         if (rc)
3875                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3876 }
3877
3878 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3879 {
3880         struct bnxt_error_recovery_info *info = bp->recovery_info;
3881         uint32_t reg = info->status_regs[index];
3882         uint32_t type, offset, val = 0;
3883
3884         type = BNXT_FW_STATUS_REG_TYPE(reg);
3885         offset = BNXT_FW_STATUS_REG_OFF(reg);
3886
3887         switch (type) {
3888         case BNXT_FW_STATUS_REG_TYPE_CFG:
3889                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3890                 break;
3891         case BNXT_FW_STATUS_REG_TYPE_GRC:
3892                 offset = info->mapped_status_regs[index];
3893                 /* FALLTHROUGH */
3894         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3895                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3896                                        offset));
3897                 break;
3898         }
3899
3900         return val;
3901 }
3902
3903 static int bnxt_fw_reset_all(struct bnxt *bp)
3904 {
3905         struct bnxt_error_recovery_info *info = bp->recovery_info;
3906         uint32_t i;
3907         int rc = 0;
3908
3909         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3910                 /* Reset through master function driver */
3911                 for (i = 0; i < info->reg_array_cnt; i++)
3912                         bnxt_write_fw_reset_reg(bp, i);
3913                 /* Wait for time specified by FW after triggering reset */
3914                 rte_delay_ms(info->master_func_wait_period_after_reset);
3915         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3916                 /* Reset with the help of Kong processor */
3917                 rc = bnxt_hwrm_fw_reset(bp);
3918                 if (rc)
3919                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3920         }
3921
3922         return rc;
3923 }
3924
3925 static void bnxt_fw_reset_cb(void *arg)
3926 {
3927         struct bnxt *bp = arg;
3928         struct bnxt_error_recovery_info *info = bp->recovery_info;
3929         int rc = 0;
3930
3931         /* Only Master function can do FW reset */
3932         if (bnxt_is_master_func(bp) &&
3933             bnxt_is_recovery_enabled(bp)) {
3934                 rc = bnxt_fw_reset_all(bp);
3935                 if (rc) {
3936                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3937                         return;
3938                 }
3939         }
3940
3941         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3942          * EXCEPTION_FATAL_ASYNC event to all the functions
3943          * (including MASTER FUNC). After receiving this Async, all the active
3944          * drivers should treat this case as FW initiated recovery
3945          */
3946         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3947                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3948                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3949
3950                 /* To recover from error */
3951                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3952                                   (void *)bp);
3953         }
3954 }
3955
3956 /* Driver should poll FW heartbeat, reset_counter with the frequency
3957  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3958  * When the driver detects heartbeat stop or change in reset_counter,
3959  * it has to trigger a reset to recover from the error condition.
3960  * A “master PF” is the function who will have the privilege to
3961  * initiate the chimp reset. The master PF will be elected by the
3962  * firmware and will be notified through async message.
3963  */
3964 static void bnxt_check_fw_health(void *arg)
3965 {
3966         struct bnxt *bp = arg;
3967         struct bnxt_error_recovery_info *info = bp->recovery_info;
3968         uint32_t val = 0, wait_msec;
3969
3970         if (!info || !bnxt_is_recovery_enabled(bp) ||
3971             is_bnxt_in_error(bp))
3972                 return;
3973
3974         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3975         if (val == info->last_heart_beat)
3976                 goto reset;
3977
3978         info->last_heart_beat = val;
3979
3980         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3981         if (val != info->last_reset_counter)
3982                 goto reset;
3983
3984         info->last_reset_counter = val;
3985
3986         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3987                           bnxt_check_fw_health, (void *)bp);
3988
3989         return;
3990 reset:
3991         /* Stop DMA to/from device */
3992         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3993         bp->flags |= BNXT_FLAG_FW_RESET;
3994
3995         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
3996
3997         if (bnxt_is_master_func(bp))
3998                 wait_msec = info->master_func_wait_period;
3999         else
4000                 wait_msec = info->normal_func_wait_period;
4001
4002         rte_eal_alarm_set(US_PER_MS * wait_msec,
4003                           bnxt_fw_reset_cb, (void *)bp);
4004 }
4005
4006 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4007 {
4008         uint32_t polling_freq;
4009
4010         if (!bnxt_is_recovery_enabled(bp))
4011                 return;
4012
4013         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4014                 return;
4015
4016         polling_freq = bp->recovery_info->driver_polling_freq;
4017
4018         rte_eal_alarm_set(US_PER_MS * polling_freq,
4019                           bnxt_check_fw_health, (void *)bp);
4020         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4021 }
4022
4023 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4024 {
4025         if (!bnxt_is_recovery_enabled(bp))
4026                 return;
4027
4028         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4029         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4030 }
4031
4032 static bool bnxt_vf_pciid(uint16_t id)
4033 {
4034         if (id == BROADCOM_DEV_ID_57304_VF ||
4035             id == BROADCOM_DEV_ID_57406_VF ||
4036             id == BROADCOM_DEV_ID_5731X_VF ||
4037             id == BROADCOM_DEV_ID_5741X_VF ||
4038             id == BROADCOM_DEV_ID_57414_VF ||
4039             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
4040             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
4041             id == BROADCOM_DEV_ID_58802_VF ||
4042             id == BROADCOM_DEV_ID_57500_VF1 ||
4043             id == BROADCOM_DEV_ID_57500_VF2)
4044                 return true;
4045         return false;
4046 }
4047
4048 static bool bnxt_thor_device(uint16_t id)
4049 {
4050         if (id == BROADCOM_DEV_ID_57508 ||
4051             id == BROADCOM_DEV_ID_57504 ||
4052             id == BROADCOM_DEV_ID_57502 ||
4053             id == BROADCOM_DEV_ID_57508_MF1 ||
4054             id == BROADCOM_DEV_ID_57504_MF1 ||
4055             id == BROADCOM_DEV_ID_57502_MF1 ||
4056             id == BROADCOM_DEV_ID_57508_MF2 ||
4057             id == BROADCOM_DEV_ID_57504_MF2 ||
4058             id == BROADCOM_DEV_ID_57502_MF2 ||
4059             id == BROADCOM_DEV_ID_57500_VF1 ||
4060             id == BROADCOM_DEV_ID_57500_VF2)
4061                 return true;
4062
4063         return false;
4064 }
4065
4066 bool bnxt_stratus_device(struct bnxt *bp)
4067 {
4068         uint16_t id = bp->pdev->id.device_id;
4069
4070         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
4071             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
4072             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
4073                 return true;
4074         return false;
4075 }
4076
4077 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4078 {
4079         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4080         struct bnxt *bp = eth_dev->data->dev_private;
4081
4082         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4083         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4084         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4085         if (!bp->bar0 || !bp->doorbell_base) {
4086                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4087                 return -ENODEV;
4088         }
4089
4090         bp->eth_dev = eth_dev;
4091         bp->pdev = pci_dev;
4092
4093         return 0;
4094 }
4095
4096 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
4097                                   struct bnxt_ctx_pg_info *ctx_pg,
4098                                   uint32_t mem_size,
4099                                   const char *suffix,
4100                                   uint16_t idx)
4101 {
4102         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4103         const struct rte_memzone *mz = NULL;
4104         char mz_name[RTE_MEMZONE_NAMESIZE];
4105         rte_iova_t mz_phys_addr;
4106         uint64_t valid_bits = 0;
4107         uint32_t sz;
4108         int i;
4109
4110         if (!mem_size)
4111                 return 0;
4112
4113         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4114                          BNXT_PAGE_SIZE;
4115         rmem->page_size = BNXT_PAGE_SIZE;
4116         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4117         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4118         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4119
4120         valid_bits = PTU_PTE_VALID;
4121
4122         if (rmem->nr_pages > 1) {
4123                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4124                          "bnxt_ctx_pg_tbl%s_%x_%d",
4125                          suffix, idx, bp->eth_dev->data->port_id);
4126                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4127                 mz = rte_memzone_lookup(mz_name);
4128                 if (!mz) {
4129                         mz = rte_memzone_reserve_aligned(mz_name,
4130                                                 rmem->nr_pages * 8,
4131                                                 SOCKET_ID_ANY,
4132                                                 RTE_MEMZONE_2MB |
4133                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4134                                                 RTE_MEMZONE_IOVA_CONTIG,
4135                                                 BNXT_PAGE_SIZE);
4136                         if (mz == NULL)
4137                                 return -ENOMEM;
4138                 }
4139
4140                 memset(mz->addr, 0, mz->len);
4141                 mz_phys_addr = mz->iova;
4142                 if ((unsigned long)mz->addr == mz_phys_addr) {
4143                         PMD_DRV_LOG(DEBUG,
4144                                     "physical address same as virtual\n");
4145                         PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4146                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
4147                         if (mz_phys_addr == RTE_BAD_IOVA) {
4148                                 PMD_DRV_LOG(ERR,
4149                                         "unable to map addr to phys memory\n");
4150                                 return -ENOMEM;
4151                         }
4152                 }
4153                 rte_mem_lock_page(((char *)mz->addr));
4154
4155                 rmem->pg_tbl = mz->addr;
4156                 rmem->pg_tbl_map = mz_phys_addr;
4157                 rmem->pg_tbl_mz = mz;
4158         }
4159
4160         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4161                  suffix, idx, bp->eth_dev->data->port_id);
4162         mz = rte_memzone_lookup(mz_name);
4163         if (!mz) {
4164                 mz = rte_memzone_reserve_aligned(mz_name,
4165                                                  mem_size,
4166                                                  SOCKET_ID_ANY,
4167                                                  RTE_MEMZONE_1GB |
4168                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4169                                                  RTE_MEMZONE_IOVA_CONTIG,
4170                                                  BNXT_PAGE_SIZE);
4171                 if (mz == NULL)
4172                         return -ENOMEM;
4173         }
4174
4175         memset(mz->addr, 0, mz->len);
4176         mz_phys_addr = mz->iova;
4177         if ((unsigned long)mz->addr == mz_phys_addr) {
4178                 PMD_DRV_LOG(DEBUG,
4179                             "Memzone physical address same as virtual.\n");
4180                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4181                 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
4182                         rte_mem_lock_page(((char *)mz->addr) + sz);
4183                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4184                 if (mz_phys_addr == RTE_BAD_IOVA) {
4185                         PMD_DRV_LOG(ERR,
4186                                     "unable to map addr to phys memory\n");
4187                         return -ENOMEM;
4188                 }
4189         }
4190
4191         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4192                 rte_mem_lock_page(((char *)mz->addr) + sz);
4193                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4194                 rmem->dma_arr[i] = mz_phys_addr + sz;
4195
4196                 if (rmem->nr_pages > 1) {
4197                         if (i == rmem->nr_pages - 2 &&
4198                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4199                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4200                         else if (i == rmem->nr_pages - 1 &&
4201                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4202                                 valid_bits |= PTU_PTE_LAST;
4203
4204                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4205                                                            valid_bits);
4206                 }
4207         }
4208
4209         rmem->mz = mz;
4210         if (rmem->vmem_size)
4211                 rmem->vmem = (void **)mz->addr;
4212         rmem->dma_arr[0] = mz_phys_addr;
4213         return 0;
4214 }
4215
4216 static void bnxt_free_ctx_mem(struct bnxt *bp)
4217 {
4218         int i;
4219
4220         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4221                 return;
4222
4223         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4224         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4225         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4226         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4227         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4228         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4229         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4230         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4231         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4232         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4233         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4234
4235         for (i = 0; i < BNXT_MAX_Q; i++) {
4236                 if (bp->ctx->tqm_mem[i])
4237                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4238         }
4239
4240         rte_free(bp->ctx);
4241         bp->ctx = NULL;
4242 }
4243
4244 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4245
4246 #define min_t(type, x, y) ({                    \
4247         type __min1 = (x);                      \
4248         type __min2 = (y);                      \
4249         __min1 < __min2 ? __min1 : __min2; })
4250
4251 #define max_t(type, x, y) ({                    \
4252         type __max1 = (x);                      \
4253         type __max2 = (y);                      \
4254         __max1 > __max2 ? __max1 : __max2; })
4255
4256 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4257
4258 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4259 {
4260         struct bnxt_ctx_pg_info *ctx_pg;
4261         struct bnxt_ctx_mem_info *ctx;
4262         uint32_t mem_size, ena, entries;
4263         int i, rc;
4264
4265         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4266         if (rc) {
4267                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4268                 return rc;
4269         }
4270         ctx = bp->ctx;
4271         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4272                 return 0;
4273
4274         ctx_pg = &ctx->qp_mem;
4275         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4276         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4277         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4278         if (rc)
4279                 return rc;
4280
4281         ctx_pg = &ctx->srq_mem;
4282         ctx_pg->entries = ctx->srq_max_l2_entries;
4283         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4284         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4285         if (rc)
4286                 return rc;
4287
4288         ctx_pg = &ctx->cq_mem;
4289         ctx_pg->entries = ctx->cq_max_l2_entries;
4290         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4291         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4292         if (rc)
4293                 return rc;
4294
4295         ctx_pg = &ctx->vnic_mem;
4296         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4297                 ctx->vnic_max_ring_table_entries;
4298         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4299         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4300         if (rc)
4301                 return rc;
4302
4303         ctx_pg = &ctx->stat_mem;
4304         ctx_pg->entries = ctx->stat_max_entries;
4305         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4306         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4307         if (rc)
4308                 return rc;
4309
4310         entries = ctx->qp_max_l2_entries +
4311                   ctx->vnic_max_vnic_entries +
4312                   ctx->tqm_min_entries_per_ring;
4313         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4314         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4315                           ctx->tqm_max_entries_per_ring);
4316         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4317                 ctx_pg = ctx->tqm_mem[i];
4318                 /* use min tqm entries for now. */
4319                 ctx_pg->entries = entries;
4320                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4321                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4322                 if (rc)
4323                         return rc;
4324                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4325         }
4326
4327         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4328         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4329         if (rc)
4330                 PMD_DRV_LOG(ERR,
4331                             "Failed to configure context mem: rc = %d\n", rc);
4332         else
4333                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4334
4335         return rc;
4336 }
4337
4338 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4339 {
4340         struct rte_pci_device *pci_dev = bp->pdev;
4341         char mz_name[RTE_MEMZONE_NAMESIZE];
4342         const struct rte_memzone *mz = NULL;
4343         uint32_t total_alloc_len;
4344         rte_iova_t mz_phys_addr;
4345
4346         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4347                 return 0;
4348
4349         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4350                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4351                  pci_dev->addr.bus, pci_dev->addr.devid,
4352                  pci_dev->addr.function, "rx_port_stats");
4353         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4354         mz = rte_memzone_lookup(mz_name);
4355         total_alloc_len =
4356                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4357                                        sizeof(struct rx_port_stats_ext) + 512);
4358         if (!mz) {
4359                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4360                                          SOCKET_ID_ANY,
4361                                          RTE_MEMZONE_2MB |
4362                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4363                                          RTE_MEMZONE_IOVA_CONTIG);
4364                 if (mz == NULL)
4365                         return -ENOMEM;
4366         }
4367         memset(mz->addr, 0, mz->len);
4368         mz_phys_addr = mz->iova;
4369         if ((unsigned long)mz->addr == mz_phys_addr) {
4370                 PMD_DRV_LOG(DEBUG,
4371                             "Memzone physical address same as virtual.\n");
4372                 PMD_DRV_LOG(DEBUG,
4373                             "Using rte_mem_virt2iova()\n");
4374                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4375                 if (mz_phys_addr == RTE_BAD_IOVA) {
4376                         PMD_DRV_LOG(ERR,
4377                                     "Can't map address to physical memory\n");
4378                         return -ENOMEM;
4379                 }
4380         }
4381
4382         bp->rx_mem_zone = (const void *)mz;
4383         bp->hw_rx_port_stats = mz->addr;
4384         bp->hw_rx_port_stats_map = mz_phys_addr;
4385
4386         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4387                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4388                  pci_dev->addr.bus, pci_dev->addr.devid,
4389                  pci_dev->addr.function, "tx_port_stats");
4390         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4391         mz = rte_memzone_lookup(mz_name);
4392         total_alloc_len =
4393                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4394                                        sizeof(struct tx_port_stats_ext) + 512);
4395         if (!mz) {
4396                 mz = rte_memzone_reserve(mz_name,
4397                                          total_alloc_len,
4398                                          SOCKET_ID_ANY,
4399                                          RTE_MEMZONE_2MB |
4400                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4401                                          RTE_MEMZONE_IOVA_CONTIG);
4402                 if (mz == NULL)
4403                         return -ENOMEM;
4404         }
4405         memset(mz->addr, 0, mz->len);
4406         mz_phys_addr = mz->iova;
4407         if ((unsigned long)mz->addr == mz_phys_addr) {
4408                 PMD_DRV_LOG(DEBUG,
4409                             "Memzone physical address same as virtual\n");
4410                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4411                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4412                 if (mz_phys_addr == RTE_BAD_IOVA) {
4413                         PMD_DRV_LOG(ERR,
4414                                     "Can't map address to physical memory\n");
4415                         return -ENOMEM;
4416                 }
4417         }
4418
4419         bp->tx_mem_zone = (const void *)mz;
4420         bp->hw_tx_port_stats = mz->addr;
4421         bp->hw_tx_port_stats_map = mz_phys_addr;
4422         bp->flags |= BNXT_FLAG_PORT_STATS;
4423
4424         /* Display extended statistics if FW supports it */
4425         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4426             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4427             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4428                 return 0;
4429
4430         bp->hw_rx_port_stats_ext = (void *)
4431                 ((uint8_t *)bp->hw_rx_port_stats +
4432                  sizeof(struct rx_port_stats));
4433         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4434                 sizeof(struct rx_port_stats);
4435         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4436
4437         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4438             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4439                 bp->hw_tx_port_stats_ext = (void *)
4440                         ((uint8_t *)bp->hw_tx_port_stats +
4441                          sizeof(struct tx_port_stats));
4442                 bp->hw_tx_port_stats_ext_map =
4443                         bp->hw_tx_port_stats_map +
4444                         sizeof(struct tx_port_stats);
4445                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4446         }
4447
4448         return 0;
4449 }
4450
4451 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4452 {
4453         struct bnxt *bp = eth_dev->data->dev_private;
4454         int rc = 0;
4455
4456         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4457                                                RTE_ETHER_ADDR_LEN *
4458                                                bp->max_l2_ctx,
4459                                                0);
4460         if (eth_dev->data->mac_addrs == NULL) {
4461                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4462                 return -ENOMEM;
4463         }
4464
4465         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4466                 if (BNXT_PF(bp))
4467                         return -EINVAL;
4468
4469                 /* Generate a random MAC address, if none was assigned by PF */
4470                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4471                 bnxt_eth_hw_addr_random(bp->mac_addr);
4472                 PMD_DRV_LOG(INFO,
4473                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4474                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4475                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4476
4477                 rc = bnxt_hwrm_set_mac(bp);
4478                 if (!rc)
4479                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4480                                RTE_ETHER_ADDR_LEN);
4481                 return rc;
4482         }
4483
4484         /* Copy the permanent MAC from the FUNC_QCAPS response */
4485         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4486         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4487
4488         return rc;
4489 }
4490
4491 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4492 {
4493         int rc = 0;
4494
4495         /* MAC is already configured in FW */
4496         if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4497                 return 0;
4498
4499         /* Restore the old MAC configured */
4500         rc = bnxt_hwrm_set_mac(bp);
4501         if (rc)
4502                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4503
4504         return rc;
4505 }
4506
4507 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4508 {
4509         if (!BNXT_PF(bp))
4510                 return;
4511
4512 #define ALLOW_FUNC(x)   \
4513         { \
4514                 uint32_t arg = (x); \
4515                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4516                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4517         }
4518
4519         /* Forward all requests if firmware is new enough */
4520         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4521              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4522             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4523                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4524         } else {
4525                 PMD_DRV_LOG(WARNING,
4526                             "Firmware too old for VF mailbox functionality\n");
4527                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4528         }
4529
4530         /*
4531          * The following are used for driver cleanup. If we disallow these,
4532          * VF drivers can't clean up cleanly.
4533          */
4534         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4535         ALLOW_FUNC(HWRM_VNIC_FREE);
4536         ALLOW_FUNC(HWRM_RING_FREE);
4537         ALLOW_FUNC(HWRM_RING_GRP_FREE);
4538         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4539         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4540         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4541         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4542         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4543 }
4544
4545 static int bnxt_init_fw(struct bnxt *bp)
4546 {
4547         uint16_t mtu;
4548         int rc = 0;
4549
4550         rc = bnxt_hwrm_ver_get(bp);
4551         if (rc)
4552                 return rc;
4553
4554         rc = bnxt_hwrm_func_reset(bp);
4555         if (rc)
4556                 return -EIO;
4557
4558         rc = bnxt_hwrm_vnic_qcaps(bp);
4559         if (rc)
4560                 return rc;
4561
4562         rc = bnxt_hwrm_queue_qportcfg(bp);
4563         if (rc)
4564                 return rc;
4565
4566         /* Get the MAX capabilities for this function.
4567          * This function also allocates context memory for TQM rings and
4568          * informs the firmware about this allocated backing store memory.
4569          */
4570         rc = bnxt_hwrm_func_qcaps(bp);
4571         if (rc)
4572                 return rc;
4573
4574         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4575         if (rc)
4576                 return rc;
4577
4578         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4579         if (rc)
4580                 return rc;
4581
4582         /* Get the adapter error recovery support info */
4583         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4584         if (rc)
4585                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
4586
4587         if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
4588             mtu != bp->eth_dev->data->mtu)
4589                 bp->eth_dev->data->mtu = mtu;
4590
4591         bnxt_hwrm_port_led_qcaps(bp);
4592
4593         return 0;
4594 }
4595
4596 static int
4597 bnxt_init_locks(struct bnxt *bp)
4598 {
4599         int err;
4600
4601         err = pthread_mutex_init(&bp->flow_lock, NULL);
4602         if (err) {
4603                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4604                 return err;
4605         }
4606
4607         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4608         if (err)
4609                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4610         return err;
4611 }
4612
4613 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4614 {
4615         int rc;
4616
4617         rc = bnxt_init_fw(bp);
4618         if (rc)
4619                 return rc;
4620
4621         if (!reconfig_dev) {
4622                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4623                 if (rc)
4624                         return rc;
4625         } else {
4626                 rc = bnxt_restore_dflt_mac(bp);
4627                 if (rc)
4628                         return rc;
4629         }
4630
4631         bnxt_config_vf_req_fwd(bp);
4632
4633         rc = bnxt_hwrm_func_driver_register(bp);
4634         if (rc) {
4635                 PMD_DRV_LOG(ERR, "Failed to register driver");
4636                 return -EBUSY;
4637         }
4638
4639         if (BNXT_PF(bp)) {
4640                 if (bp->pdev->max_vfs) {
4641                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4642                         if (rc) {
4643                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4644                                 return rc;
4645                         }
4646                 } else {
4647                         rc = bnxt_hwrm_allocate_pf_only(bp);
4648                         if (rc) {
4649                                 PMD_DRV_LOG(ERR,
4650                                             "Failed to allocate PF resources");
4651                                 return rc;
4652                         }
4653                 }
4654         }
4655
4656         rc = bnxt_alloc_mem(bp, reconfig_dev);
4657         if (rc)
4658                 return rc;
4659
4660         rc = bnxt_setup_int(bp);
4661         if (rc)
4662                 return rc;
4663
4664         bnxt_init_nic(bp);
4665
4666         rc = bnxt_request_int(bp);
4667         if (rc)
4668                 return rc;
4669
4670         rc = bnxt_init_locks(bp);
4671         if (rc)
4672                 return rc;
4673
4674         return 0;
4675 }
4676
4677 static int
4678 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4679 {
4680         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4681         static int version_printed;
4682         struct bnxt *bp;
4683         int rc;
4684
4685         if (version_printed++ == 0)
4686                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4687
4688         eth_dev->dev_ops = &bnxt_dev_ops;
4689         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4690         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4691
4692         /*
4693          * For secondary processes, we don't initialise any further
4694          * as primary has already done this work.
4695          */
4696         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4697                 return 0;
4698
4699         rte_eth_copy_pci_info(eth_dev, pci_dev);
4700
4701         bp = eth_dev->data->dev_private;
4702
4703         bp->dev_stopped = 1;
4704
4705         if (bnxt_vf_pciid(pci_dev->id.device_id))
4706                 bp->flags |= BNXT_FLAG_VF;
4707
4708         if (bnxt_thor_device(pci_dev->id.device_id))
4709                 bp->flags |= BNXT_FLAG_THOR_CHIP;
4710
4711         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4712             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4713             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4714             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4715                 bp->flags |= BNXT_FLAG_STINGRAY;
4716
4717         rc = bnxt_init_board(eth_dev);
4718         if (rc) {
4719                 PMD_DRV_LOG(ERR,
4720                             "Failed to initialize board rc: %x\n", rc);
4721                 return rc;
4722         }
4723
4724         rc = bnxt_alloc_hwrm_resources(bp);
4725         if (rc) {
4726                 PMD_DRV_LOG(ERR,
4727                             "Failed to allocate hwrm resource rc: %x\n", rc);
4728                 goto error_free;
4729         }
4730         rc = bnxt_init_resources(bp, false);
4731         if (rc)
4732                 goto error_free;
4733
4734         rc = bnxt_alloc_stats_mem(bp);
4735         if (rc)
4736                 goto error_free;
4737
4738         PMD_DRV_LOG(INFO,
4739                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4740                     pci_dev->mem_resource[0].phys_addr,
4741                     pci_dev->mem_resource[0].addr);
4742
4743         return 0;
4744
4745 error_free:
4746         bnxt_dev_uninit(eth_dev);
4747         return rc;
4748 }
4749
4750 static void
4751 bnxt_uninit_locks(struct bnxt *bp)
4752 {
4753         pthread_mutex_destroy(&bp->flow_lock);
4754         pthread_mutex_destroy(&bp->def_cp_lock);
4755 }
4756
4757 static int
4758 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4759 {
4760         int rc;
4761
4762         bnxt_free_int(bp);
4763         bnxt_free_mem(bp, reconfig_dev);
4764         bnxt_hwrm_func_buf_unrgtr(bp);
4765         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4766         bp->flags &= ~BNXT_FLAG_REGISTERED;
4767         bnxt_free_ctx_mem(bp);
4768         if (!reconfig_dev) {
4769                 bnxt_free_hwrm_resources(bp);
4770
4771                 if (bp->recovery_info != NULL) {
4772                         rte_free(bp->recovery_info);
4773                         bp->recovery_info = NULL;
4774                 }
4775         }
4776
4777         bnxt_uninit_locks(bp);
4778         rte_free(bp->ptp_cfg);
4779         bp->ptp_cfg = NULL;
4780         return rc;
4781 }
4782
4783 static int
4784 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4785 {
4786         struct bnxt *bp = eth_dev->data->dev_private;
4787         int rc;
4788
4789         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4790                 return -EPERM;
4791
4792         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4793
4794         rc = bnxt_uninit_resources(bp, false);
4795
4796         if (bp->tx_mem_zone) {
4797                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4798                 bp->tx_mem_zone = NULL;
4799         }
4800
4801         if (bp->rx_mem_zone) {
4802                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4803                 bp->rx_mem_zone = NULL;
4804         }
4805
4806         if (bp->dev_stopped == 0)
4807                 bnxt_dev_close_op(eth_dev);
4808         if (bp->pf.vf_info)
4809                 rte_free(bp->pf.vf_info);
4810         eth_dev->dev_ops = NULL;
4811         eth_dev->rx_pkt_burst = NULL;
4812         eth_dev->tx_pkt_burst = NULL;
4813
4814         return rc;
4815 }
4816
4817 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4818         struct rte_pci_device *pci_dev)
4819 {
4820         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4821                 bnxt_dev_init);
4822 }
4823
4824 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4825 {
4826         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4827                 return rte_eth_dev_pci_generic_remove(pci_dev,
4828                                 bnxt_dev_uninit);
4829         else
4830                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4831 }
4832
4833 static struct rte_pci_driver bnxt_rte_pmd = {
4834         .id_table = bnxt_pci_id_map,
4835         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4836         .probe = bnxt_pci_probe,
4837         .remove = bnxt_pci_remove,
4838 };
4839
4840 static bool
4841 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4842 {
4843         if (strcmp(dev->device->driver->name, drv->driver.name))
4844                 return false;
4845
4846         return true;
4847 }
4848
4849 bool is_bnxt_supported(struct rte_eth_dev *dev)
4850 {
4851         return is_device_supported(dev, &bnxt_rte_pmd);
4852 }
4853
4854 RTE_INIT(bnxt_init_log)
4855 {
4856         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4857         if (bnxt_logtype_driver >= 0)
4858                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4859 }
4860
4861 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4862 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4863 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");