drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16
  17 #include "bnxt.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_rxq.h"
  23 #include "bnxt_rxr.h"
  24 #include "bnxt_stats.h"
  25 #include "bnxt_txq.h"
  26 #include "bnxt_txr.h"
  27 #include "bnxt_vnic.h"
  28 #include "hsi_struct_def_dpdk.h"
  29 #include "bnxt_nvm_defs.h"
  30
  31 #define DRV_MODULE_NAME         "bnxt"
  32 static const char bnxt_version[] =
  33         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  34 int bnxt_logtype_driver;
  35
  36 /*
  37  * The set of PCI devices this driver supports
  38  */
  39 static const struct rte_pci_id bnxt_pci_id_map[] = {
  40         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  41                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  42         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  43                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  45         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  93         { .vendor_id = 0, /* sentinel */ },
  94 };
  95
  96 #define BNXT_ETH_RSS_SUPPORT (  \
  97         ETH_RSS_IPV4 |          \
  98         ETH_RSS_NONFRAG_IPV4_TCP |      \
  99         ETH_RSS_NONFRAG_IPV4_UDP |      \
 100         ETH_RSS_IPV6 |          \
 101         ETH_RSS_NONFRAG_IPV6_TCP |      \
 102         ETH_RSS_NONFRAG_IPV6_UDP)
 103
 104 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 105                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 106                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 107                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 108                                      DEV_TX_OFFLOAD_TCP_TSO | \
 109                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 110                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 111                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 112                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 113                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 114                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 115                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 116
 117 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 118                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 119                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 120                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 121                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 122                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 123                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 124                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 125                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 126                                      DEV_RX_OFFLOAD_TCP_LRO | \
 127                                      DEV_RX_OFFLOAD_SCATTER | \
 128                                      DEV_RX_OFFLOAD_RSS_HASH)
 129
 130 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
 131 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
 132 static const char *const bnxt_dev_args[] = {
 133         BNXT_DEVARG_TRUFLOW,
 134         BNXT_DEVARG_FLOW_XSTAT,
 135         NULL
 136 };
 137
 138 /*
 139  * truflow == false to disable the feature
 140  * truflow == true to enable the feature
 141  */
 142 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 143
 144 /*
 145  * flow_xstat == false to disable the feature
 146  * flow_xstat == true to enable the feature
 147  */
 148 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 149
 150 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 151 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 152 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 153 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 154 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 155 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 156 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 157 static void bnxt_dev_recover(void *arg);
 158 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 159
 160 int is_bnxt_in_error(struct bnxt *bp)
 161 {
 162         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 163                 return -EIO;
 164         if (bp->flags & BNXT_FLAG_FW_RESET)
 165                 return -EBUSY;
 166
 167         return 0;
 168 }
 169
 170 /***********************/
 171
 172 /*
 173  * High level utility functions
 174  */
 175
 176 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 177 {
 178         if (!BNXT_CHIP_THOR(bp))
 179                 return 1;
 180
 181         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 182                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 183                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 184 }
 185
 186 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 187 {
 188         if (!BNXT_CHIP_THOR(bp))
 189                 return HW_HASH_INDEX_SIZE;
 190
 191         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 192 }
 193
 194 static void bnxt_free_link_info(struct bnxt *bp)
 195 {
 196         rte_free(bp->link_info);
 197 }
 198
 199 static void bnxt_free_leds_info(struct bnxt *bp)
 200 {
 201         rte_free(bp->leds);
 202         bp->leds = NULL;
 203 }
 204
 205 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 206 {
 207         rte_free(bp->flow_stat);
 208         bp->flow_stat = NULL;
 209 }
 210
 211 static void bnxt_free_cos_queues(struct bnxt *bp)
 212 {
 213         rte_free(bp->rx_cos_queue);
 214         rte_free(bp->tx_cos_queue);
 215 }
 216
 217 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 218 {
 219         bnxt_free_flow_stats_info(bp);
 220
 221         bnxt_free_filter_mem(bp);
 222         bnxt_free_vnic_attributes(bp);
 223         bnxt_free_vnic_mem(bp);
 224
 225         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 226          * If the number of rings change across fw update,
 227          * we don't have much choice except to warn the user.
 228          */
 229         if (!reconfig) {
 230                 bnxt_free_stats(bp);
 231                 bnxt_free_tx_rings(bp);
 232                 bnxt_free_rx_rings(bp);
 233         }
 234         bnxt_free_async_cp_ring(bp);
 235         bnxt_free_rxtx_nq_ring(bp);
 236
 237         rte_free(bp->grp_info);
 238         bp->grp_info = NULL;
 239 }
 240
 241 static int bnxt_alloc_link_info(struct bnxt *bp)
 242 {
 243         bp->link_info =
 244                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 245         if (bp->link_info == NULL)
 246                 return -ENOMEM;
 247
 248         return 0;
 249 }
 250
 251 static int bnxt_alloc_leds_info(struct bnxt *bp)
 252 {
 253         bp->leds = rte_zmalloc("bnxt_leds",
 254                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 255                                0);
 256         if (bp->leds == NULL)
 257                 return -ENOMEM;
 258
 259         return 0;
 260 }
 261
 262 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 263 {
 264         bp->rx_cos_queue =
 265                 rte_zmalloc("bnxt_rx_cosq",
 266                             BNXT_COS_QUEUE_COUNT *
 267                             sizeof(struct bnxt_cos_queue_info),
 268                             0);
 269         if (bp->rx_cos_queue == NULL)
 270                 return -ENOMEM;
 271
 272         bp->tx_cos_queue =
 273                 rte_zmalloc("bnxt_tx_cosq",
 274                             BNXT_COS_QUEUE_COUNT *
 275                             sizeof(struct bnxt_cos_queue_info),
 276                             0);
 277         if (bp->tx_cos_queue == NULL)
 278                 return -ENOMEM;
 279
 280         return 0;
 281 }
 282
 283 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 284 {
 285         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 286                                     sizeof(struct bnxt_flow_stat_info), 0);
 287         if (bp->flow_stat == NULL)
 288                 return -ENOMEM;
 289
 290         return 0;
 291 }
 292
 293 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 294 {
 295         int rc;
 296
 297         rc = bnxt_alloc_ring_grps(bp);
 298         if (rc)
 299                 goto alloc_mem_err;
 300
 301         rc = bnxt_alloc_async_ring_struct(bp);
 302         if (rc)
 303                 goto alloc_mem_err;
 304
 305         rc = bnxt_alloc_vnic_mem(bp);
 306         if (rc)
 307                 goto alloc_mem_err;
 308
 309         rc = bnxt_alloc_vnic_attributes(bp);
 310         if (rc)
 311                 goto alloc_mem_err;
 312
 313         rc = bnxt_alloc_filter_mem(bp);
 314         if (rc)
 315                 goto alloc_mem_err;
 316
 317         rc = bnxt_alloc_async_cp_ring(bp);
 318         if (rc)
 319                 goto alloc_mem_err;
 320
 321         rc = bnxt_alloc_rxtx_nq_ring(bp);
 322         if (rc)
 323                 goto alloc_mem_err;
 324
 325         if (BNXT_FLOW_XSTATS_EN(bp)) {
 326                 rc = bnxt_alloc_flow_stats_info(bp);
 327                 if (rc)
 328                         goto alloc_mem_err;
 329         }
 330
 331         return 0;
 332
 333 alloc_mem_err:
 334         bnxt_free_mem(bp, reconfig);
 335         return rc;
 336 }
 337
 338 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 339 {
 340         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 341         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 342         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 343         struct bnxt_rx_queue *rxq;
 344         unsigned int j;
 345         int rc;
 346
 347         rc = bnxt_vnic_grp_alloc(bp, vnic);
 348         if (rc)
 349                 goto err_out;
 350
 351         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 352                     vnic_id, vnic, vnic->fw_grp_ids);
 353
 354         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 355         if (rc)
 356                 goto err_out;
 357
 358         /* Alloc RSS context only if RSS mode is enabled */
 359         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 360                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 361
 362                 rc = 0;
 363                 for (j = 0; j < nr_ctxs; j++) {
 364                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 365                         if (rc)
 366                                 break;
 367                 }
 368                 if (rc) {
 369                         PMD_DRV_LOG(ERR,
 370                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 371                                     vnic_id, j, rc);
 372                         goto err_out;
 373                 }
 374                 vnic->num_lb_ctxts = nr_ctxs;
 375         }
 376
 377         /*
 378          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 379          * setting is not available at this time, it will not be
 380          * configured correctly in the CFA.
 381          */
 382         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 383                 vnic->vlan_strip = true;
 384         else
 385                 vnic->vlan_strip = false;
 386
 387         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 388         if (rc)
 389                 goto err_out;
 390
 391         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 392         if (rc)
 393                 goto err_out;
 394
 395         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 396                 rxq = bp->eth_dev->data->rx_queues[j];
 397
 398                 PMD_DRV_LOG(DEBUG,
 399                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 400                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 401
 402                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 403                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 404                 else
 405                         vnic->rx_queue_cnt++;
 406         }
 407
 408         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 409
 410         rc = bnxt_vnic_rss_configure(bp, vnic);
 411         if (rc)
 412                 goto err_out;
 413
 414         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 415
 416         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 417                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 418         else
 419                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 420
 421         return 0;
 422 err_out:
 423         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 424                     vnic_id, rc);
 425         return rc;
 426 }
 427
 428 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 429 {
 430         int rc = 0;
 431
 432         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 433                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 434         if (rc)
 435                 return rc;
 436
 437         PMD_DRV_LOG(DEBUG,
 438                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 439                     " rx_fc_in_tbl.ctx_id = %d\n",
 440                     bp->flow_stat->rx_fc_in_tbl.va,
 441                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 442                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 443
 444         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 445                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 446         if (rc)
 447                 return rc;
 448
 449         PMD_DRV_LOG(DEBUG,
 450                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 451                     " rx_fc_out_tbl.ctx_id = %d\n",
 452                     bp->flow_stat->rx_fc_out_tbl.va,
 453                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 454                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 455
 456         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 457                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 458         if (rc)
 459                 return rc;
 460
 461         PMD_DRV_LOG(DEBUG,
 462                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 463                     " tx_fc_in_tbl.ctx_id = %d\n",
 464                     bp->flow_stat->tx_fc_in_tbl.va,
 465                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 466                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 467
 468         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 469                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 470         if (rc)
 471                 return rc;
 472
 473         PMD_DRV_LOG(DEBUG,
 474                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 475                     " tx_fc_out_tbl.ctx_id = %d\n",
 476                     bp->flow_stat->tx_fc_out_tbl.va,
 477                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 478                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 479
 480         memset(bp->flow_stat->rx_fc_out_tbl.va,
 481                0,
 482                bp->flow_stat->rx_fc_out_tbl.size);
 483         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 484                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 485                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 486                                        bp->flow_stat->max_fc,
 487                                        true);
 488         if (rc)
 489                 return rc;
 490
 491         memset(bp->flow_stat->tx_fc_out_tbl.va,
 492                0,
 493                bp->flow_stat->tx_fc_out_tbl.size);
 494         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 495                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 496                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 497                                        bp->flow_stat->max_fc,
 498                                        true);
 499
 500         return rc;
 501 }
 502
 503 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 504                                   struct bnxt_ctx_mem_buf_info *ctx)
 505 {
 506         if (!ctx)
 507                 return -EINVAL;
 508
 509         ctx->va = rte_zmalloc(type, size, 0);
 510         if (ctx->va == NULL)
 511                 return -ENOMEM;
 512         rte_mem_lock_page(ctx->va);
 513         ctx->size = size;
 514         ctx->dma = rte_mem_virt2iova(ctx->va);
 515         if (ctx->dma == RTE_BAD_IOVA)
 516                 return -ENOMEM;
 517
 518         return 0;
 519 }
 520
 521 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 522 {
 523         struct rte_pci_device *pdev = bp->pdev;
 524         char type[RTE_MEMZONE_NAMESIZE];
 525         uint16_t max_fc;
 526         int rc = 0;
 527
 528         max_fc = bp->flow_stat->max_fc;
 529
 530         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 531                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 532         /* 4 bytes for each counter-id */
 533         rc = bnxt_alloc_ctx_mem_buf(type,
 534                                     max_fc * 4,
 535                                     &bp->flow_stat->rx_fc_in_tbl);
 536         if (rc)
 537                 return rc;
 538
 539         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 540                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 541         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 542         rc = bnxt_alloc_ctx_mem_buf(type,
 543                                     max_fc * 16,
 544                                     &bp->flow_stat->rx_fc_out_tbl);
 545         if (rc)
 546                 return rc;
 547
 548         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 549                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 550         /* 4 bytes for each counter-id */
 551         rc = bnxt_alloc_ctx_mem_buf(type,
 552                                     max_fc * 4,
 553                                     &bp->flow_stat->tx_fc_in_tbl);
 554         if (rc)
 555                 return rc;
 556
 557         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 558                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 559         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 560         rc = bnxt_alloc_ctx_mem_buf(type,
 561                                     max_fc * 16,
 562                                     &bp->flow_stat->tx_fc_out_tbl);
 563         if (rc)
 564                 return rc;
 565
 566         rc = bnxt_register_fc_ctx_mem(bp);
 567
 568         return rc;
 569 }
 570
 571 static int bnxt_init_ctx_mem(struct bnxt *bp)
 572 {
 573         int rc = 0;
 574
 575         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 576             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 577             !BNXT_FLOW_XSTATS_EN(bp))
 578                 return 0;
 579
 580         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 581         if (rc)
 582                 return rc;
 583
 584         rc = bnxt_init_fc_ctx_mem(bp);
 585
 586         return rc;
 587 }
 588
 589 static int bnxt_init_chip(struct bnxt *bp)
 590 {
 591         struct rte_eth_link new;
 592         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 593         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 594         uint32_t intr_vector = 0;
 595         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 596         uint32_t vec = BNXT_MISC_VEC_ID;
 597         unsigned int i, j;
 598         int rc;
 599
 600         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 601                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 602                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 603                 bp->flags |= BNXT_FLAG_JUMBO;
 604         } else {
 605                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 606                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 607                 bp->flags &= ~BNXT_FLAG_JUMBO;
 608         }
 609
 610         /* THOR does not support ring groups.
 611          * But we will use the array to save RSS context IDs.
 612          */
 613         if (BNXT_CHIP_THOR(bp))
 614                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 615
 616         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 617         if (rc) {
 618                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 619                 goto err_out;
 620         }
 621
 622         rc = bnxt_alloc_hwrm_rings(bp);
 623         if (rc) {
 624                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 625                 goto err_out;
 626         }
 627
 628         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 629         if (rc) {
 630                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 631                 goto err_out;
 632         }
 633
 634         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 635                 goto skip_cosq_cfg;
 636
 637         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 638                 if (bp->rx_cos_queue[i].id != 0xff) {
 639                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 640
 641                         if (!vnic) {
 642                                 PMD_DRV_LOG(ERR,
 643                                             "Num pools more than FW profile\n");
 644                                 rc = -EINVAL;
 645                                 goto err_out;
 646                         }
 647                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 648                         bp->rx_cosq_cnt++;
 649                 }
 650         }
 651
 652 skip_cosq_cfg:
 653         rc = bnxt_mq_rx_configure(bp);
 654         if (rc) {
 655                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 656                 goto err_out;
 657         }
 658
 659         /* VNIC configuration */
 660         for (i = 0; i < bp->nr_vnics; i++) {
 661                 rc = bnxt_setup_one_vnic(bp, i);
 662                 if (rc)
 663                         goto err_out;
 664         }
 665
 666         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 667         if (rc) {
 668                 PMD_DRV_LOG(ERR,
 669                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 670                 goto err_out;
 671         }
 672
 673         /* check and configure queue intr-vector mapping */
 674         if ((rte_intr_cap_multiple(intr_handle) ||
 675              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 676             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 677                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 678                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 679                 if (intr_vector > bp->rx_cp_nr_rings) {
 680                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 681                                         bp->rx_cp_nr_rings);
 682                         return -ENOTSUP;
 683                 }
 684                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 685                 if (rc)
 686                         return rc;
 687         }
 688
 689         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 690                 intr_handle->intr_vec =
 691                         rte_zmalloc("intr_vec",
 692                                     bp->eth_dev->data->nb_rx_queues *
 693                                     sizeof(int), 0);
 694                 if (intr_handle->intr_vec == NULL) {
 695                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 696                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 697                         rc = -ENOMEM;
 698                         goto err_disable;
 699                 }
 700                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 701                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 702                          intr_handle->intr_vec, intr_handle->nb_efd,
 703                         intr_handle->max_intr);
 704                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 705                      queue_id++) {
 706                         intr_handle->intr_vec[queue_id] =
 707                                                         vec + BNXT_RX_VEC_START;
 708                         if (vec < base + intr_handle->nb_efd - 1)
 709                                 vec++;
 710                 }
 711         }
 712
 713         /* enable uio/vfio intr/eventfd mapping */
 714         rc = rte_intr_enable(intr_handle);
 715 #ifndef RTE_EXEC_ENV_FREEBSD
 716         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 717         if (rc)
 718                 goto err_free;
 719 #endif
 720
 721         rc = bnxt_get_hwrm_link_config(bp, &new);
 722         if (rc) {
 723                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 724                 goto err_free;
 725         }
 726
 727         if (!bp->link_info->link_up) {
 728                 rc = bnxt_set_hwrm_link_config(bp, true);
 729                 if (rc) {
 730                         PMD_DRV_LOG(ERR,
 731                                 "HWRM link config failure rc: %x\n", rc);
 732                         goto err_free;
 733                 }
 734         }
 735         bnxt_print_link_info(bp->eth_dev);
 736
 737         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 738         if (!bp->mark_table)
 739                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 740
 741         return 0;
 742
 743 err_free:
 744         rte_free(intr_handle->intr_vec);
 745 err_disable:
 746         rte_intr_efd_disable(intr_handle);
 747 err_out:
 748         /* Some of the error status returned by FW may not be from errno.h */
 749         if (rc > 0)
 750                 rc = -EIO;
 751
 752         return rc;
 753 }
 754
 755 static int bnxt_shutdown_nic(struct bnxt *bp)
 756 {
 757         bnxt_free_all_hwrm_resources(bp);
 758         bnxt_free_all_filters(bp);
 759         bnxt_free_all_vnics(bp);
 760         return 0;
 761 }
 762
 763 /*
 764  * Device configuration and status function
 765  */
 766
 767 static uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 768 {
 769         uint32_t link_speed = bp->link_info->support_speeds;
 770         uint32_t speed_capa = 0;
 771
 772         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 773                 speed_capa |= ETH_LINK_SPEED_100M;
 774         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 775                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 776         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 777                 speed_capa |= ETH_LINK_SPEED_1G;
 778         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 779                 speed_capa |= ETH_LINK_SPEED_2_5G;
 780         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 781                 speed_capa |= ETH_LINK_SPEED_10G;
 782         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 783                 speed_capa |= ETH_LINK_SPEED_20G;
 784         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 785                 speed_capa |= ETH_LINK_SPEED_25G;
 786         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 787                 speed_capa |= ETH_LINK_SPEED_40G;
 788         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 789                 speed_capa |= ETH_LINK_SPEED_50G;
 790         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 791                 speed_capa |= ETH_LINK_SPEED_100G;
 792         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB)
 793                 speed_capa |= ETH_LINK_SPEED_200G;
 794
 795         if (bp->link_info->auto_mode ==
 796             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 797                 speed_capa |= ETH_LINK_SPEED_FIXED;
 798         else
 799                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 800
 801         return speed_capa;
 802 }
 803
 804 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 805                                 struct rte_eth_dev_info *dev_info)
 806 {
 807         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 808         struct bnxt *bp = eth_dev->data->dev_private;
 809         uint16_t max_vnics, i, j, vpool, vrxq;
 810         unsigned int max_rx_rings;
 811         int rc;
 812
 813         rc = is_bnxt_in_error(bp);
 814         if (rc)
 815                 return rc;
 816
 817         /* MAC Specifics */
 818         dev_info->max_mac_addrs = bp->max_l2_ctx;
 819         dev_info->max_hash_mac_addrs = 0;
 820
 821         /* PF/VF specifics */
 822         if (BNXT_PF(bp))
 823                 dev_info->max_vfs = pdev->max_vfs;
 824
 825         max_rx_rings = BNXT_MAX_RINGS(bp);
 826         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 827         dev_info->max_rx_queues = max_rx_rings;
 828         dev_info->max_tx_queues = max_rx_rings;
 829         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 830         dev_info->hash_key_size = 40;
 831         max_vnics = bp->max_vnics;
 832
 833         /* MTU specifics */
 834         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 835         dev_info->max_mtu = BNXT_MAX_MTU;
 836
 837         /* Fast path specifics */
 838         dev_info->min_rx_bufsize = 1;
 839         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 840
 841         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 842         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 843                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 844         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 845         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 846
 847         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 848
 849         /* *INDENT-OFF* */
 850         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 851                 .rx_thresh = {
 852                         .pthresh = 8,
 853                         .hthresh = 8,
 854                         .wthresh = 0,
 855                 },
 856                 .rx_free_thresh = 32,
 857                 /* If no descriptors available, pkts are dropped by default */
 858                 .rx_drop_en = 1,
 859         };
 860
 861         dev_info->default_txconf = (struct rte_eth_txconf) {
 862                 .tx_thresh = {
 863                         .pthresh = 32,
 864                         .hthresh = 0,
 865                         .wthresh = 0,
 866                 },
 867                 .tx_free_thresh = 32,
 868                 .tx_rs_thresh = 32,
 869         };
 870         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 871
 872         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 873         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 874         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 875         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 876         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 877
 878         /* *INDENT-ON* */
 879
 880         /*
 881          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 882          *       need further investigation.
 883          */
 884
 885         /* VMDq resources */
 886         vpool = 64; /* ETH_64_POOLS */
 887         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 888         for (i = 0; i < 4; vpool >>= 1, i++) {
 889                 if (max_vnics > vpool) {
 890                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 891                                 if (dev_info->max_rx_queues > vrxq) {
 892                                         if (vpool > vrxq)
 893                                                 vpool = vrxq;
 894                                         goto found;
 895                                 }
 896                         }
 897                         /* Not enough resources to support VMDq */
 898                         break;
 899                 }
 900         }
 901         /* Not enough resources to support VMDq */
 902         vpool = 0;
 903         vrxq = 0;
 904 found:
 905         dev_info->max_vmdq_pools = vpool;
 906         dev_info->vmdq_queue_num = vrxq;
 907
 908         dev_info->vmdq_pool_base = 0;
 909         dev_info->vmdq_queue_base = 0;
 910
 911         return 0;
 912 }
 913
 914 /* Configure the device based on the configuration provided */
 915 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 916 {
 917         struct bnxt *bp = eth_dev->data->dev_private;
 918         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 919         int rc;
 920
 921         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 922         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 923         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 924         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 925
 926         rc = is_bnxt_in_error(bp);
 927         if (rc)
 928                 return rc;
 929
 930         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 931                 rc = bnxt_hwrm_check_vf_rings(bp);
 932                 if (rc) {
 933                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 934                         return -ENOSPC;
 935                 }
 936
 937                 /* If a resource has already been allocated - in this case
 938                  * it is the async completion ring, free it. Reallocate it after
 939                  * resource reservation. This will ensure the resource counts
 940                  * are calculated correctly.
 941                  */
 942
 943                 pthread_mutex_lock(&bp->def_cp_lock);
 944
 945                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 946                         bnxt_disable_int(bp);
 947                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 948                 }
 949
 950                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 951                 if (rc) {
 952                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 953                         pthread_mutex_unlock(&bp->def_cp_lock);
 954                         return -ENOSPC;
 955                 }
 956
 957                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 958                         rc = bnxt_alloc_async_cp_ring(bp);
 959                         if (rc) {
 960                                 pthread_mutex_unlock(&bp->def_cp_lock);
 961                                 return rc;
 962                         }
 963                         bnxt_enable_int(bp);
 964                 }
 965
 966                 pthread_mutex_unlock(&bp->def_cp_lock);
 967         } else {
 968                 /* legacy driver needs to get updated values */
 969                 rc = bnxt_hwrm_func_qcaps(bp);
 970                 if (rc) {
 971                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 972                         return rc;
 973                 }
 974         }
 975
 976         /* Inherit new configurations */
 977         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 978             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 979             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 980                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 981             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 982             bp->max_stat_ctx)
 983                 goto resource_error;
 984
 985         if (BNXT_HAS_RING_GRPS(bp) &&
 986             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 987                 goto resource_error;
 988
 989         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 990             bp->max_vnics < eth_dev->data->nb_rx_queues)
 991                 goto resource_error;
 992
 993         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 994         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 995
 996         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
 997                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 998         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
 999
1000         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1001                 eth_dev->data->mtu =
1002                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1003                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1004                         BNXT_NUM_VLANS;
1005                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1006         }
1007         return 0;
1008
1009 resource_error:
1010         PMD_DRV_LOG(ERR,
1011                     "Insufficient resources to support requested config\n");
1012         PMD_DRV_LOG(ERR,
1013                     "Num Queues Requested: Tx %d, Rx %d\n",
1014                     eth_dev->data->nb_tx_queues,
1015                     eth_dev->data->nb_rx_queues);
1016         PMD_DRV_LOG(ERR,
1017                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1018                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1019                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1020         return -ENOSPC;
1021 }
1022
1023 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1024 {
1025         struct rte_eth_link *link = &eth_dev->data->dev_link;
1026
1027         if (link->link_status)
1028                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1029                         eth_dev->data->port_id,
1030                         (uint32_t)link->link_speed,
1031                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1032                         ("full-duplex") : ("half-duplex\n"));
1033         else
1034                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1035                         eth_dev->data->port_id);
1036 }
1037
1038 /*
1039  * Determine whether the current configuration requires support for scattered
1040  * receive; return 1 if scattered receive is required and 0 if not.
1041  */
1042 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1043 {
1044         uint16_t buf_size;
1045         int i;
1046
1047         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1048                 return 1;
1049
1050         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1051                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1052
1053                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1054                                       RTE_PKTMBUF_HEADROOM);
1055                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1056                         return 1;
1057         }
1058         return 0;
1059 }
1060
1061 static eth_rx_burst_t
1062 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1063 {
1064         struct bnxt *bp = eth_dev->data->dev_private;
1065
1066 #ifdef RTE_ARCH_X86
1067 #ifndef RTE_LIBRTE_IEEE1588
1068         /*
1069          * Vector mode receive can be enabled only if scatter rx is not
1070          * in use and rx offloads are limited to VLAN stripping and
1071          * CRC stripping.
1072          */
1073         if (!eth_dev->data->scattered_rx &&
1074             !(eth_dev->data->dev_conf.rxmode.offloads &
1075               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1076                 DEV_RX_OFFLOAD_KEEP_CRC |
1077                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1078                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1079                 DEV_RX_OFFLOAD_UDP_CKSUM |
1080                 DEV_RX_OFFLOAD_TCP_CKSUM |
1081                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1082                 DEV_RX_OFFLOAD_RSS_HASH |
1083                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1084             !bp->truflow) {
1085                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1086                             eth_dev->data->port_id);
1087                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1088                 return bnxt_recv_pkts_vec;
1089         }
1090         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1091                     eth_dev->data->port_id);
1092         PMD_DRV_LOG(INFO,
1093                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1094                     eth_dev->data->port_id,
1095                     eth_dev->data->scattered_rx,
1096                     eth_dev->data->dev_conf.rxmode.offloads);
1097 #endif
1098 #endif
1099         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1100         return bnxt_recv_pkts;
1101 }
1102
1103 static eth_tx_burst_t
1104 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1105 {
1106 #ifdef RTE_ARCH_X86
1107 #ifndef RTE_LIBRTE_IEEE1588
1108         /*
1109          * Vector mode transmit can be enabled only if not using scatter rx
1110          * or tx offloads.
1111          */
1112         if (!eth_dev->data->scattered_rx &&
1113             !eth_dev->data->dev_conf.txmode.offloads) {
1114                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1115                             eth_dev->data->port_id);
1116                 return bnxt_xmit_pkts_vec;
1117         }
1118         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1119                     eth_dev->data->port_id);
1120         PMD_DRV_LOG(INFO,
1121                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1122                     eth_dev->data->port_id,
1123                     eth_dev->data->scattered_rx,
1124                     eth_dev->data->dev_conf.txmode.offloads);
1125 #endif
1126 #endif
1127         return bnxt_xmit_pkts;
1128 }
1129
1130 static int bnxt_handle_if_change_status(struct bnxt *bp)
1131 {
1132         int rc;
1133
1134         /* Since fw has undergone a reset and lost all contexts,
1135          * set fatal flag to not issue hwrm during cleanup
1136          */
1137         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1138         bnxt_uninit_resources(bp, true);
1139
1140         /* clear fatal flag so that re-init happens */
1141         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1142         rc = bnxt_init_resources(bp, true);
1143
1144         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1145
1146         return rc;
1147 }
1148
1149 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1150 {
1151         struct bnxt *bp = eth_dev->data->dev_private;
1152         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1153         int vlan_mask = 0;
1154         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1155
1156         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1157                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1158                 return -EINVAL;
1159         }
1160
1161         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1162                 PMD_DRV_LOG(ERR,
1163                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1164                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1165         }
1166
1167         do {
1168                 rc = bnxt_hwrm_if_change(bp, true);
1169                 if (rc == 0 || rc != -EAGAIN)
1170                         break;
1171
1172                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1173         } while (retry_cnt--);
1174
1175         if (rc)
1176                 return rc;
1177
1178         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1179                 rc = bnxt_handle_if_change_status(bp);
1180                 if (rc)
1181                         return rc;
1182         }
1183
1184         bnxt_enable_int(bp);
1185
1186         rc = bnxt_init_chip(bp);
1187         if (rc)
1188                 goto error;
1189
1190         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1191         eth_dev->data->dev_started = 1;
1192
1193         bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1194
1195         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1196                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1197         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1198                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1199         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1200         if (rc)
1201                 goto error;
1202
1203         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1204         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1205
1206         pthread_mutex_lock(&bp->def_cp_lock);
1207         bnxt_schedule_fw_health_check(bp);
1208         pthread_mutex_unlock(&bp->def_cp_lock);
1209
1210         if (bp->truflow)
1211                 bnxt_ulp_init(bp);
1212
1213         return 0;
1214
1215 error:
1216         bnxt_shutdown_nic(bp);
1217         bnxt_free_tx_mbufs(bp);
1218         bnxt_free_rx_mbufs(bp);
1219         bnxt_hwrm_if_change(bp, false);
1220         eth_dev->data->dev_started = 0;
1221         return rc;
1222 }
1223
1224 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1225 {
1226         struct bnxt *bp = eth_dev->data->dev_private;
1227         int rc = 0;
1228
1229         if (!bp->link_info->link_up)
1230                 rc = bnxt_set_hwrm_link_config(bp, true);
1231         if (!rc)
1232                 eth_dev->data->dev_link.link_status = 1;
1233
1234         bnxt_print_link_info(eth_dev);
1235         return rc;
1236 }
1237
1238 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1239 {
1240         struct bnxt *bp = eth_dev->data->dev_private;
1241
1242         eth_dev->data->dev_link.link_status = 0;
1243         bnxt_set_hwrm_link_config(bp, false);
1244         bp->link_info->link_up = 0;
1245
1246         return 0;
1247 }
1248
1249 /* Unload the driver, release resources */
1250 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1251 {
1252         struct bnxt *bp = eth_dev->data->dev_private;
1253         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1254         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1255
1256         if (bp->truflow)
1257                 bnxt_ulp_deinit(bp);
1258
1259         eth_dev->data->dev_started = 0;
1260         /* Prevent crashes when queues are still in use */
1261         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1262         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1263
1264         bnxt_disable_int(bp);
1265
1266         /* disable uio/vfio intr/eventfd mapping */
1267         rte_intr_disable(intr_handle);
1268
1269         bnxt_cancel_fw_health_check(bp);
1270
1271         bnxt_dev_set_link_down_op(eth_dev);
1272
1273         /* Wait for link to be reset and the async notification to process.
1274          * During reset recovery, there is no need to wait and
1275          * VF/NPAR functions do not have privilege to change PHY config.
1276          */
1277         if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1278                 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1279
1280         /* Clean queue intr-vector mapping */
1281         rte_intr_efd_disable(intr_handle);
1282         if (intr_handle->intr_vec != NULL) {
1283                 rte_free(intr_handle->intr_vec);
1284                 intr_handle->intr_vec = NULL;
1285         }
1286
1287         bnxt_hwrm_port_clr_stats(bp);
1288         bnxt_free_tx_mbufs(bp);
1289         bnxt_free_rx_mbufs(bp);
1290         /* Process any remaining notifications in default completion queue */
1291         bnxt_int_handler(eth_dev);
1292         bnxt_shutdown_nic(bp);
1293         bnxt_hwrm_if_change(bp, false);
1294
1295         rte_free(bp->mark_table);
1296         bp->mark_table = NULL;
1297
1298         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1299         bp->rx_cosq_cnt = 0;
1300         /* All filters are deleted on a port stop. */
1301         if (BNXT_FLOW_XSTATS_EN(bp))
1302                 bp->flow_stat->flow_count = 0;
1303 }
1304
1305 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1306 {
1307         struct bnxt *bp = eth_dev->data->dev_private;
1308
1309         /* cancel the recovery handler before remove dev */
1310         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1311         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1312         bnxt_cancel_fc_thread(bp);
1313
1314         if (eth_dev->data->dev_started)
1315                 bnxt_dev_stop_op(eth_dev);
1316
1317         bnxt_uninit_resources(bp, false);
1318
1319         bnxt_free_leds_info(bp);
1320         bnxt_free_cos_queues(bp);
1321         bnxt_free_link_info(bp);
1322
1323         eth_dev->dev_ops = NULL;
1324         eth_dev->rx_pkt_burst = NULL;
1325         eth_dev->tx_pkt_burst = NULL;
1326
1327         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1328         bp->tx_mem_zone = NULL;
1329         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1330         bp->rx_mem_zone = NULL;
1331
1332         rte_free(bp->pf.vf_info);
1333         bp->pf.vf_info = NULL;
1334
1335         rte_free(bp->grp_info);
1336         bp->grp_info = NULL;
1337 }
1338
1339 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1340                                     uint32_t index)
1341 {
1342         struct bnxt *bp = eth_dev->data->dev_private;
1343         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1344         struct bnxt_vnic_info *vnic;
1345         struct bnxt_filter_info *filter, *temp_filter;
1346         uint32_t i;
1347
1348         if (is_bnxt_in_error(bp))
1349                 return;
1350
1351         /*
1352          * Loop through all VNICs from the specified filter flow pools to
1353          * remove the corresponding MAC addr filter
1354          */
1355         for (i = 0; i < bp->nr_vnics; i++) {
1356                 if (!(pool_mask & (1ULL << i)))
1357                         continue;
1358
1359                 vnic = &bp->vnic_info[i];
1360                 filter = STAILQ_FIRST(&vnic->filter);
1361                 while (filter) {
1362                         temp_filter = STAILQ_NEXT(filter, next);
1363                         if (filter->mac_index == index) {
1364                                 STAILQ_REMOVE(&vnic->filter, filter,
1365                                                 bnxt_filter_info, next);
1366                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1367                                 bnxt_free_filter(bp, filter);
1368                         }
1369                         filter = temp_filter;
1370                 }
1371         }
1372 }
1373
1374 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1375                                struct rte_ether_addr *mac_addr, uint32_t index,
1376                                uint32_t pool)
1377 {
1378         struct bnxt_filter_info *filter;
1379         int rc = 0;
1380
1381         /* Attach requested MAC address to the new l2_filter */
1382         STAILQ_FOREACH(filter, &vnic->filter, next) {
1383                 if (filter->mac_index == index) {
1384                         PMD_DRV_LOG(DEBUG,
1385                                     "MAC addr already existed for pool %d\n",
1386                                     pool);
1387                         return 0;
1388                 }
1389         }
1390
1391         filter = bnxt_alloc_filter(bp);
1392         if (!filter) {
1393                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1394                 return -ENODEV;
1395         }
1396
1397         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1398          * if the MAC that's been programmed now is a different one, then,
1399          * copy that addr to filter->l2_addr
1400          */
1401         if (mac_addr)
1402                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1403         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1404
1405         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1406         if (!rc) {
1407                 filter->mac_index = index;
1408                 if (filter->mac_index == 0)
1409                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1410                 else
1411                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1412         } else {
1413                 bnxt_free_filter(bp, filter);
1414         }
1415
1416         return rc;
1417 }
1418
1419 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1420                                 struct rte_ether_addr *mac_addr,
1421                                 uint32_t index, uint32_t pool)
1422 {
1423         struct bnxt *bp = eth_dev->data->dev_private;
1424         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1425         int rc = 0;
1426
1427         rc = is_bnxt_in_error(bp);
1428         if (rc)
1429                 return rc;
1430
1431         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1432                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1433                 return -ENOTSUP;
1434         }
1435
1436         if (!vnic) {
1437                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1438                 return -EINVAL;
1439         }
1440
1441         /* Filter settings will get applied when port is started */
1442         if (!eth_dev->data->dev_started)
1443                 return 0;
1444
1445         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1446
1447         return rc;
1448 }
1449
1450 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1451                      bool exp_link_status)
1452 {
1453         int rc = 0;
1454         struct bnxt *bp = eth_dev->data->dev_private;
1455         struct rte_eth_link new;
1456         int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1457                   BNXT_LINK_DOWN_WAIT_CNT;
1458
1459         rc = is_bnxt_in_error(bp);
1460         if (rc)
1461                 return rc;
1462
1463         memset(&new, 0, sizeof(new));
1464         do {
1465                 /* Retrieve link info from hardware */
1466                 rc = bnxt_get_hwrm_link_config(bp, &new);
1467                 if (rc) {
1468                         new.link_speed = ETH_LINK_SPEED_100M;
1469                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1470                         PMD_DRV_LOG(ERR,
1471                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1472                         goto out;
1473                 }
1474
1475                 if (!wait_to_complete || new.link_status == exp_link_status)
1476                         break;
1477
1478                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1479         } while (cnt--);
1480
1481 out:
1482         /* Timed out or success */
1483         if (new.link_status != eth_dev->data->dev_link.link_status ||
1484         new.link_speed != eth_dev->data->dev_link.link_speed) {
1485                 rte_eth_linkstatus_set(eth_dev, &new);
1486
1487                 _rte_eth_dev_callback_process(eth_dev,
1488                                               RTE_ETH_EVENT_INTR_LSC,
1489                                               NULL);
1490
1491                 bnxt_print_link_info(eth_dev);
1492         }
1493
1494         return rc;
1495 }
1496
1497 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1498                                int wait_to_complete)
1499 {
1500         return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1501 }
1502
1503 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1504 {
1505         struct bnxt *bp = eth_dev->data->dev_private;
1506         struct bnxt_vnic_info *vnic;
1507         uint32_t old_flags;
1508         int rc;
1509
1510         rc = is_bnxt_in_error(bp);
1511         if (rc)
1512                 return rc;
1513
1514         /* Filter settings will get applied when port is started */
1515         if (!eth_dev->data->dev_started)
1516                 return 0;
1517
1518         if (bp->vnic_info == NULL)
1519                 return 0;
1520
1521         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1522
1523         old_flags = vnic->flags;
1524         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1525         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1526         if (rc != 0)
1527                 vnic->flags = old_flags;
1528
1529         return rc;
1530 }
1531
1532 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1533 {
1534         struct bnxt *bp = eth_dev->data->dev_private;
1535         struct bnxt_vnic_info *vnic;
1536         uint32_t old_flags;
1537         int rc;
1538
1539         rc = is_bnxt_in_error(bp);
1540         if (rc)
1541                 return rc;
1542
1543         /* Filter settings will get applied when port is started */
1544         if (!eth_dev->data->dev_started)
1545                 return 0;
1546
1547         if (bp->vnic_info == NULL)
1548                 return 0;
1549
1550         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1551
1552         old_flags = vnic->flags;
1553         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1554         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1555         if (rc != 0)
1556                 vnic->flags = old_flags;
1557
1558         return rc;
1559 }
1560
1561 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1562 {
1563         struct bnxt *bp = eth_dev->data->dev_private;
1564         struct bnxt_vnic_info *vnic;
1565         uint32_t old_flags;
1566         int rc;
1567
1568         rc = is_bnxt_in_error(bp);
1569         if (rc)
1570                 return rc;
1571
1572         /* Filter settings will get applied when port is started */
1573         if (!eth_dev->data->dev_started)
1574                 return 0;
1575
1576         if (bp->vnic_info == NULL)
1577                 return 0;
1578
1579         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1580
1581         old_flags = vnic->flags;
1582         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1583         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1584         if (rc != 0)
1585                 vnic->flags = old_flags;
1586
1587         return rc;
1588 }
1589
1590 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1591 {
1592         struct bnxt *bp = eth_dev->data->dev_private;
1593         struct bnxt_vnic_info *vnic;
1594         uint32_t old_flags;
1595         int rc;
1596
1597         rc = is_bnxt_in_error(bp);
1598         if (rc)
1599                 return rc;
1600
1601         /* Filter settings will get applied when port is started */
1602         if (!eth_dev->data->dev_started)
1603                 return 0;
1604
1605         if (bp->vnic_info == NULL)
1606                 return 0;
1607
1608         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1609
1610         old_flags = vnic->flags;
1611         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1612         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1613         if (rc != 0)
1614                 vnic->flags = old_flags;
1615
1616         return rc;
1617 }
1618
1619 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1620 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1621 {
1622         if (qid >= bp->rx_nr_rings)
1623                 return NULL;
1624
1625         return bp->eth_dev->data->rx_queues[qid];
1626 }
1627
1628 /* Return rxq corresponding to a given rss table ring/group ID. */
1629 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1630 {
1631         struct bnxt_rx_queue *rxq;
1632         unsigned int i;
1633
1634         if (!BNXT_HAS_RING_GRPS(bp)) {
1635                 for (i = 0; i < bp->rx_nr_rings; i++) {
1636                         rxq = bp->eth_dev->data->rx_queues[i];
1637                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1638                                 return rxq->index;
1639                 }
1640         } else {
1641                 for (i = 0; i < bp->rx_nr_rings; i++) {
1642                         if (bp->grp_info[i].fw_grp_id == fwr)
1643                                 return i;
1644                 }
1645         }
1646
1647         return INVALID_HW_RING_ID;
1648 }
1649
1650 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1651                             struct rte_eth_rss_reta_entry64 *reta_conf,
1652                             uint16_t reta_size)
1653 {
1654         struct bnxt *bp = eth_dev->data->dev_private;
1655         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1656         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1657         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1658         uint16_t idx, sft;
1659         int i, rc;
1660
1661         rc = is_bnxt_in_error(bp);
1662         if (rc)
1663                 return rc;
1664
1665         if (!vnic->rss_table)
1666                 return -EINVAL;
1667
1668         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1669                 return -EINVAL;
1670
1671         if (reta_size != tbl_size) {
1672                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1673                         "(%d) must equal the size supported by the hardware "
1674                         "(%d)\n", reta_size, tbl_size);
1675                 return -EINVAL;
1676         }
1677
1678         for (i = 0; i < reta_size; i++) {
1679                 struct bnxt_rx_queue *rxq;
1680
1681                 idx = i / RTE_RETA_GROUP_SIZE;
1682                 sft = i % RTE_RETA_GROUP_SIZE;
1683
1684                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1685                         continue;
1686
1687                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1688                 if (!rxq) {
1689                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1690                         return -EINVAL;
1691                 }
1692
1693                 if (BNXT_CHIP_THOR(bp)) {
1694                         vnic->rss_table[i * 2] =
1695                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1696                         vnic->rss_table[i * 2 + 1] =
1697                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1698                 } else {
1699                         vnic->rss_table[i] =
1700                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1701                 }
1702         }
1703
1704         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1705         return 0;
1706 }
1707
1708 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1709                               struct rte_eth_rss_reta_entry64 *reta_conf,
1710                               uint16_t reta_size)
1711 {
1712         struct bnxt *bp = eth_dev->data->dev_private;
1713         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1714         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1715         uint16_t idx, sft, i;
1716         int rc;
1717
1718         rc = is_bnxt_in_error(bp);
1719         if (rc)
1720                 return rc;
1721
1722         /* Retrieve from the default VNIC */
1723         if (!vnic)
1724                 return -EINVAL;
1725         if (!vnic->rss_table)
1726                 return -EINVAL;
1727
1728         if (reta_size != tbl_size) {
1729                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1730                         "(%d) must equal the size supported by the hardware "
1731                         "(%d)\n", reta_size, tbl_size);
1732                 return -EINVAL;
1733         }
1734
1735         for (idx = 0, i = 0; i < reta_size; i++) {
1736                 idx = i / RTE_RETA_GROUP_SIZE;
1737                 sft = i % RTE_RETA_GROUP_SIZE;
1738
1739                 if (reta_conf[idx].mask & (1ULL << sft)) {
1740                         uint16_t qid;
1741
1742                         if (BNXT_CHIP_THOR(bp))
1743                                 qid = bnxt_rss_to_qid(bp,
1744                                                       vnic->rss_table[i * 2]);
1745                         else
1746                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1747
1748                         if (qid == INVALID_HW_RING_ID) {
1749                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1750                                 return -EINVAL;
1751                         }
1752                         reta_conf[idx].reta[sft] = qid;
1753                 }
1754         }
1755
1756         return 0;
1757 }
1758
1759 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1760                                    struct rte_eth_rss_conf *rss_conf)
1761 {
1762         struct bnxt *bp = eth_dev->data->dev_private;
1763         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1764         struct bnxt_vnic_info *vnic;
1765         int rc;
1766
1767         rc = is_bnxt_in_error(bp);
1768         if (rc)
1769                 return rc;
1770
1771         /*
1772          * If RSS enablement were different than dev_configure,
1773          * then return -EINVAL
1774          */
1775         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1776                 if (!rss_conf->rss_hf)
1777                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1778         } else {
1779                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1780                         return -EINVAL;
1781         }
1782
1783         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1784         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1785
1786         /* Update the default RSS VNIC(s) */
1787         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1788         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1789
1790         /*
1791          * If hashkey is not specified, use the previously configured
1792          * hashkey
1793          */
1794         if (!rss_conf->rss_key)
1795                 goto rss_config;
1796
1797         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1798                 PMD_DRV_LOG(ERR,
1799                             "Invalid hashkey length, should be 16 bytes\n");
1800                 return -EINVAL;
1801         }
1802         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1803
1804 rss_config:
1805         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1806         return 0;
1807 }
1808
1809 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1810                                      struct rte_eth_rss_conf *rss_conf)
1811 {
1812         struct bnxt *bp = eth_dev->data->dev_private;
1813         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1814         int len, rc;
1815         uint32_t hash_types;
1816
1817         rc = is_bnxt_in_error(bp);
1818         if (rc)
1819                 return rc;
1820
1821         /* RSS configuration is the same for all VNICs */
1822         if (vnic && vnic->rss_hash_key) {
1823                 if (rss_conf->rss_key) {
1824                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1825                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1826                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1827                 }
1828
1829                 hash_types = vnic->hash_type;
1830                 rss_conf->rss_hf = 0;
1831                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1832                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1833                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1834                 }
1835                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1836                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1837                         hash_types &=
1838                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1839                 }
1840                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1841                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1842                         hash_types &=
1843                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1844                 }
1845                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1846                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1847                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1848                 }
1849                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1850                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1851                         hash_types &=
1852                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1853                 }
1854                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1855                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1856                         hash_types &=
1857                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1858                 }
1859                 if (hash_types) {
1860                         PMD_DRV_LOG(ERR,
1861                                 "Unknown RSS config from firmware (%08x), RSS disabled",
1862                                 vnic->hash_type);
1863                         return -ENOTSUP;
1864                 }
1865         } else {
1866                 rss_conf->rss_hf = 0;
1867         }
1868         return 0;
1869 }
1870
1871 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1872                                struct rte_eth_fc_conf *fc_conf)
1873 {
1874         struct bnxt *bp = dev->data->dev_private;
1875         struct rte_eth_link link_info;
1876         int rc;
1877
1878         rc = is_bnxt_in_error(bp);
1879         if (rc)
1880                 return rc;
1881
1882         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1883         if (rc)
1884                 return rc;
1885
1886         memset(fc_conf, 0, sizeof(*fc_conf));
1887         if (bp->link_info->auto_pause)
1888                 fc_conf->autoneg = 1;
1889         switch (bp->link_info->pause) {
1890         case 0:
1891                 fc_conf->mode = RTE_FC_NONE;
1892                 break;
1893         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1894                 fc_conf->mode = RTE_FC_TX_PAUSE;
1895                 break;
1896         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1897                 fc_conf->mode = RTE_FC_RX_PAUSE;
1898                 break;
1899         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1900                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1901                 fc_conf->mode = RTE_FC_FULL;
1902                 break;
1903         }
1904         return 0;
1905 }
1906
1907 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1908                                struct rte_eth_fc_conf *fc_conf)
1909 {
1910         struct bnxt *bp = dev->data->dev_private;
1911         int rc;
1912
1913         rc = is_bnxt_in_error(bp);
1914         if (rc)
1915                 return rc;
1916
1917         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1918                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1919                 return -ENOTSUP;
1920         }
1921
1922         switch (fc_conf->mode) {
1923         case RTE_FC_NONE:
1924                 bp->link_info->auto_pause = 0;
1925                 bp->link_info->force_pause = 0;
1926                 break;
1927         case RTE_FC_RX_PAUSE:
1928                 if (fc_conf->autoneg) {
1929                         bp->link_info->auto_pause =
1930                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1931                         bp->link_info->force_pause = 0;
1932                 } else {
1933                         bp->link_info->auto_pause = 0;
1934                         bp->link_info->force_pause =
1935                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1936                 }
1937                 break;
1938         case RTE_FC_TX_PAUSE:
1939                 if (fc_conf->autoneg) {
1940                         bp->link_info->auto_pause =
1941                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1942                         bp->link_info->force_pause = 0;
1943                 } else {
1944                         bp->link_info->auto_pause = 0;
1945                         bp->link_info->force_pause =
1946                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1947                 }
1948                 break;
1949         case RTE_FC_FULL:
1950                 if (fc_conf->autoneg) {
1951                         bp->link_info->auto_pause =
1952                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1953                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1954                         bp->link_info->force_pause = 0;
1955                 } else {
1956                         bp->link_info->auto_pause = 0;
1957                         bp->link_info->force_pause =
1958                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1959                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1960                 }
1961                 break;
1962         }
1963         return bnxt_set_hwrm_link_config(bp, true);
1964 }
1965
1966 /* Add UDP tunneling port */
1967 static int
1968 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1969                          struct rte_eth_udp_tunnel *udp_tunnel)
1970 {
1971         struct bnxt *bp = eth_dev->data->dev_private;
1972         uint16_t tunnel_type = 0;
1973         int rc = 0;
1974
1975         rc = is_bnxt_in_error(bp);
1976         if (rc)
1977                 return rc;
1978
1979         switch (udp_tunnel->prot_type) {
1980         case RTE_TUNNEL_TYPE_VXLAN:
1981                 if (bp->vxlan_port_cnt) {
1982                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1983                                 udp_tunnel->udp_port);
1984                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1985                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1986                                 return -ENOSPC;
1987                         }
1988                         bp->vxlan_port_cnt++;
1989                         return 0;
1990                 }
1991                 tunnel_type =
1992                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1993                 bp->vxlan_port_cnt++;
1994                 break;
1995         case RTE_TUNNEL_TYPE_GENEVE:
1996                 if (bp->geneve_port_cnt) {
1997                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1998                                 udp_tunnel->udp_port);
1999                         if (bp->geneve_port != udp_tunnel->udp_port) {
2000                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2001                                 return -ENOSPC;
2002                         }
2003                         bp->geneve_port_cnt++;
2004                         return 0;
2005                 }
2006                 tunnel_type =
2007                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2008                 bp->geneve_port_cnt++;
2009                 break;
2010         default:
2011                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2012                 return -ENOTSUP;
2013         }
2014         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2015                                              tunnel_type);
2016         return rc;
2017 }
2018
2019 static int
2020 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2021                          struct rte_eth_udp_tunnel *udp_tunnel)
2022 {
2023         struct bnxt *bp = eth_dev->data->dev_private;
2024         uint16_t tunnel_type = 0;
2025         uint16_t port = 0;
2026         int rc = 0;
2027
2028         rc = is_bnxt_in_error(bp);
2029         if (rc)
2030                 return rc;
2031
2032         switch (udp_tunnel->prot_type) {
2033         case RTE_TUNNEL_TYPE_VXLAN:
2034                 if (!bp->vxlan_port_cnt) {
2035                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2036                         return -EINVAL;
2037                 }
2038                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2039                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2040                                 udp_tunnel->udp_port, bp->vxlan_port);
2041                         return -EINVAL;
2042                 }
2043                 if (--bp->vxlan_port_cnt)
2044                         return 0;
2045
2046                 tunnel_type =
2047                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2048                 port = bp->vxlan_fw_dst_port_id;
2049                 break;
2050         case RTE_TUNNEL_TYPE_GENEVE:
2051                 if (!bp->geneve_port_cnt) {
2052                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2053                         return -EINVAL;
2054                 }
2055                 if (bp->geneve_port != udp_tunnel->udp_port) {
2056                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2057                                 udp_tunnel->udp_port, bp->geneve_port);
2058                         return -EINVAL;
2059                 }
2060                 if (--bp->geneve_port_cnt)
2061                         return 0;
2062
2063                 tunnel_type =
2064                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2065                 port = bp->geneve_fw_dst_port_id;
2066                 break;
2067         default:
2068                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2069                 return -ENOTSUP;
2070         }
2071
2072         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2073         if (!rc) {
2074                 if (tunnel_type ==
2075                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
2076                         bp->vxlan_port = 0;
2077                 if (tunnel_type ==
2078                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
2079                         bp->geneve_port = 0;
2080         }
2081         return rc;
2082 }
2083
2084 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2085 {
2086         struct bnxt_filter_info *filter;
2087         struct bnxt_vnic_info *vnic;
2088         int rc = 0;
2089         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2090
2091         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2092         filter = STAILQ_FIRST(&vnic->filter);
2093         while (filter) {
2094                 /* Search for this matching MAC+VLAN filter */
2095                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2096                         /* Delete the filter */
2097                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2098                         if (rc)
2099                                 return rc;
2100                         STAILQ_REMOVE(&vnic->filter, filter,
2101                                       bnxt_filter_info, next);
2102                         bnxt_free_filter(bp, filter);
2103                         PMD_DRV_LOG(INFO,
2104                                     "Deleted vlan filter for %d\n",
2105                                     vlan_id);
2106                         return 0;
2107                 }
2108                 filter = STAILQ_NEXT(filter, next);
2109         }
2110         return -ENOENT;
2111 }
2112
2113 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2114 {
2115         struct bnxt_filter_info *filter;
2116         struct bnxt_vnic_info *vnic;
2117         int rc = 0;
2118         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2119                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2120         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2121
2122         /* Implementation notes on the use of VNIC in this command:
2123          *
2124          * By default, these filters belong to default vnic for the function.
2125          * Once these filters are set up, only destination VNIC can be modified.
2126          * If the destination VNIC is not specified in this command,
2127          * then the HWRM shall only create an l2 context id.
2128          */
2129
2130         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2131         filter = STAILQ_FIRST(&vnic->filter);
2132         /* Check if the VLAN has already been added */
2133         while (filter) {
2134                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2135                         return -EEXIST;
2136
2137                 filter = STAILQ_NEXT(filter, next);
2138         }
2139
2140         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2141          * command to create MAC+VLAN filter with the right flags, enables set.
2142          */
2143         filter = bnxt_alloc_filter(bp);
2144         if (!filter) {
2145                 PMD_DRV_LOG(ERR,
2146                             "MAC/VLAN filter alloc failed\n");
2147                 return -ENOMEM;
2148         }
2149         /* MAC + VLAN ID filter */
2150         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2151          * untagged packets are received
2152          *
2153          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2154          * packets and only the programmed vlan's packets are received
2155          */
2156         filter->l2_ivlan = vlan_id;
2157         filter->l2_ivlan_mask = 0x0FFF;
2158         filter->enables |= en;
2159         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2160
2161         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2162         if (rc) {
2163                 /* Free the newly allocated filter as we were
2164                  * not able to create the filter in hardware.
2165                  */
2166                 bnxt_free_filter(bp, filter);
2167                 return rc;
2168         }
2169
2170         filter->mac_index = 0;
2171         /* Add this new filter to the list */
2172         if (vlan_id == 0)
2173                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2174         else
2175                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2176
2177         PMD_DRV_LOG(INFO,
2178                     "Added Vlan filter for %d\n", vlan_id);
2179         return rc;
2180 }
2181
2182 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2183                 uint16_t vlan_id, int on)
2184 {
2185         struct bnxt *bp = eth_dev->data->dev_private;
2186         int rc;
2187
2188         rc = is_bnxt_in_error(bp);
2189         if (rc)
2190                 return rc;
2191
2192         if (!eth_dev->data->dev_started) {
2193                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2194                 return -EINVAL;
2195         }
2196
2197         /* These operations apply to ALL existing MAC/VLAN filters */
2198         if (on)
2199                 return bnxt_add_vlan_filter(bp, vlan_id);
2200         else
2201                 return bnxt_del_vlan_filter(bp, vlan_id);
2202 }
2203
2204 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2205                                     struct bnxt_vnic_info *vnic)
2206 {
2207         struct bnxt_filter_info *filter;
2208         int rc;
2209
2210         filter = STAILQ_FIRST(&vnic->filter);
2211         while (filter) {
2212                 if (filter->mac_index == 0 &&
2213                     !memcmp(filter->l2_addr, bp->mac_addr,
2214                             RTE_ETHER_ADDR_LEN)) {
2215                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2216                         if (!rc) {
2217                                 STAILQ_REMOVE(&vnic->filter, filter,
2218                                               bnxt_filter_info, next);
2219                                 bnxt_free_filter(bp, filter);
2220                         }
2221                         return rc;
2222                 }
2223                 filter = STAILQ_NEXT(filter, next);
2224         }
2225         return 0;
2226 }
2227
2228 static int
2229 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2230 {
2231         struct bnxt_vnic_info *vnic;
2232         unsigned int i;
2233         int rc;
2234
2235         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2236         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2237                 /* Remove any VLAN filters programmed */
2238                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2239                         bnxt_del_vlan_filter(bp, i);
2240
2241                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2242                 if (rc)
2243                         return rc;
2244         } else {
2245                 /* Default filter will allow packets that match the
2246                  * dest mac. So, it has to be deleted, otherwise, we
2247                  * will endup receiving vlan packets for which the
2248                  * filter is not programmed, when hw-vlan-filter
2249                  * configuration is ON
2250                  */
2251                 bnxt_del_dflt_mac_filter(bp, vnic);
2252                 /* This filter will allow only untagged packets */
2253                 bnxt_add_vlan_filter(bp, 0);
2254         }
2255         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2256                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2257
2258         return 0;
2259 }
2260
2261 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2262 {
2263         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2264         unsigned int i;
2265         int rc;
2266
2267         /* Destroy vnic filters and vnic */
2268         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2269             DEV_RX_OFFLOAD_VLAN_FILTER) {
2270                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2271                         bnxt_del_vlan_filter(bp, i);
2272         }
2273         bnxt_del_dflt_mac_filter(bp, vnic);
2274
2275         rc = bnxt_hwrm_vnic_free(bp, vnic);
2276         if (rc)
2277                 return rc;
2278
2279         rte_free(vnic->fw_grp_ids);
2280         vnic->fw_grp_ids = NULL;
2281
2282         vnic->rx_queue_cnt = 0;
2283
2284         return 0;
2285 }
2286
2287 static int
2288 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2289 {
2290         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2291         int rc;
2292
2293         /* Destroy, recreate and reconfigure the default vnic */
2294         rc = bnxt_free_one_vnic(bp, 0);
2295         if (rc)
2296                 return rc;
2297
2298         /* default vnic 0 */
2299         rc = bnxt_setup_one_vnic(bp, 0);
2300         if (rc)
2301                 return rc;
2302
2303         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2304             DEV_RX_OFFLOAD_VLAN_FILTER) {
2305                 rc = bnxt_add_vlan_filter(bp, 0);
2306                 if (rc)
2307                         return rc;
2308                 rc = bnxt_restore_vlan_filters(bp);
2309                 if (rc)
2310                         return rc;
2311         } else {
2312                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2313                 if (rc)
2314                         return rc;
2315         }
2316
2317         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2318         if (rc)
2319                 return rc;
2320
2321         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2322                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2323
2324         return rc;
2325 }
2326
2327 static int
2328 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2329 {
2330         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2331         struct bnxt *bp = dev->data->dev_private;
2332         int rc;
2333
2334         rc = is_bnxt_in_error(bp);
2335         if (rc)
2336                 return rc;
2337
2338         /* Filter settings will get applied when port is started */
2339         if (!dev->data->dev_started)
2340                 return 0;
2341
2342         if (mask & ETH_VLAN_FILTER_MASK) {
2343                 /* Enable or disable VLAN filtering */
2344                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2345                 if (rc)
2346                         return rc;
2347         }
2348
2349         if (mask & ETH_VLAN_STRIP_MASK) {
2350                 /* Enable or disable VLAN stripping */
2351                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2352                 if (rc)
2353                         return rc;
2354         }
2355
2356         if (mask & ETH_VLAN_EXTEND_MASK) {
2357                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2358                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2359                 else
2360                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2361         }
2362
2363         return 0;
2364 }
2365
2366 static int
2367 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2368                       uint16_t tpid)
2369 {
2370         struct bnxt *bp = dev->data->dev_private;
2371         int qinq = dev->data->dev_conf.rxmode.offloads &
2372                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2373
2374         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2375             vlan_type != ETH_VLAN_TYPE_OUTER) {
2376                 PMD_DRV_LOG(ERR,
2377                             "Unsupported vlan type.");
2378                 return -EINVAL;
2379         }
2380         if (!qinq) {
2381                 PMD_DRV_LOG(ERR,
2382                             "QinQ not enabled. Needs to be ON as we can "
2383                             "accelerate only outer vlan\n");
2384                 return -EINVAL;
2385         }
2386
2387         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2388                 switch (tpid) {
2389                 case RTE_ETHER_TYPE_QINQ:
2390                         bp->outer_tpid_bd =
2391                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2392                                 break;
2393                 case RTE_ETHER_TYPE_VLAN:
2394                         bp->outer_tpid_bd =
2395                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2396                                 break;
2397                 case 0x9100:
2398                         bp->outer_tpid_bd =
2399                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2400                                 break;
2401                 case 0x9200:
2402                         bp->outer_tpid_bd =
2403                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2404                                 break;
2405                 case 0x9300:
2406                         bp->outer_tpid_bd =
2407                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2408                                 break;
2409                 default:
2410                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2411                         return -EINVAL;
2412                 }
2413                 bp->outer_tpid_bd |= tpid;
2414                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2415         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2416                 PMD_DRV_LOG(ERR,
2417                             "Can accelerate only outer vlan in QinQ\n");
2418                 return -EINVAL;
2419         }
2420
2421         return 0;
2422 }
2423
2424 static int
2425 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2426                              struct rte_ether_addr *addr)
2427 {
2428         struct bnxt *bp = dev->data->dev_private;
2429         /* Default Filter is tied to VNIC 0 */
2430         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2431         int rc;
2432
2433         rc = is_bnxt_in_error(bp);
2434         if (rc)
2435                 return rc;
2436
2437         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2438                 return -EPERM;
2439
2440         if (rte_is_zero_ether_addr(addr))
2441                 return -EINVAL;
2442
2443         /* Filter settings will get applied when port is started */
2444         if (!dev->data->dev_started)
2445                 return 0;
2446
2447         /* Check if the requested MAC is already added */
2448         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2449                 return 0;
2450
2451         /* Destroy filter and re-create it */
2452         bnxt_del_dflt_mac_filter(bp, vnic);
2453
2454         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2455         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2456                 /* This filter will allow only untagged packets */
2457                 rc = bnxt_add_vlan_filter(bp, 0);
2458         } else {
2459                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2460         }
2461
2462         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2463         return rc;
2464 }
2465
2466 static int
2467 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2468                           struct rte_ether_addr *mc_addr_set,
2469                           uint32_t nb_mc_addr)
2470 {
2471         struct bnxt *bp = eth_dev->data->dev_private;
2472         char *mc_addr_list = (char *)mc_addr_set;
2473         struct bnxt_vnic_info *vnic;
2474         uint32_t off = 0, i = 0;
2475         int rc;
2476
2477         rc = is_bnxt_in_error(bp);
2478         if (rc)
2479                 return rc;
2480
2481         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2482
2483         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2484                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2485                 goto allmulti;
2486         }
2487
2488         /* TODO Check for Duplicate mcast addresses */
2489         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2490         for (i = 0; i < nb_mc_addr; i++) {
2491                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2492                         RTE_ETHER_ADDR_LEN);
2493                 off += RTE_ETHER_ADDR_LEN;
2494         }
2495
2496         vnic->mc_addr_cnt = i;
2497         if (vnic->mc_addr_cnt)
2498                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2499         else
2500                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2501
2502 allmulti:
2503         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2504 }
2505
2506 static int
2507 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2508 {
2509         struct bnxt *bp = dev->data->dev_private;
2510         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2511         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2512         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2513         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2514         int ret;
2515
2516         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2517                         fw_major, fw_minor, fw_updt, fw_rsvd);
2518
2519         ret += 1; /* add the size of '\0' */
2520         if (fw_size < (uint32_t)ret)
2521                 return ret;
2522         else
2523                 return 0;
2524 }
2525
2526 static void
2527 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2528         struct rte_eth_rxq_info *qinfo)
2529 {
2530         struct bnxt *bp = dev->data->dev_private;
2531         struct bnxt_rx_queue *rxq;
2532
2533         if (is_bnxt_in_error(bp))
2534                 return;
2535
2536         rxq = dev->data->rx_queues[queue_id];
2537
2538         qinfo->mp = rxq->mb_pool;
2539         qinfo->scattered_rx = dev->data->scattered_rx;
2540         qinfo->nb_desc = rxq->nb_rx_desc;
2541
2542         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2543         qinfo->conf.rx_drop_en = 0;
2544         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2545 }
2546
2547 static void
2548 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2549         struct rte_eth_txq_info *qinfo)
2550 {
2551         struct bnxt *bp = dev->data->dev_private;
2552         struct bnxt_tx_queue *txq;
2553
2554         if (is_bnxt_in_error(bp))
2555                 return;
2556
2557         txq = dev->data->tx_queues[queue_id];
2558
2559         qinfo->nb_desc = txq->nb_tx_desc;
2560
2561         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2562         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2563         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2564
2565         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2566         qinfo->conf.tx_rs_thresh = 0;
2567         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2568 }
2569
2570 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2571 {
2572         struct bnxt *bp = eth_dev->data->dev_private;
2573         uint32_t new_pkt_size;
2574         uint32_t rc = 0;
2575         uint32_t i;
2576
2577         rc = is_bnxt_in_error(bp);
2578         if (rc)
2579                 return rc;
2580
2581         /* Exit if receive queues are not configured yet */
2582         if (!eth_dev->data->nb_rx_queues)
2583                 return rc;
2584
2585         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2586                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2587
2588 #ifdef RTE_ARCH_X86
2589         /*
2590          * If vector-mode tx/rx is active, disallow any MTU change that would
2591          * require scattered receive support.
2592          */
2593         if (eth_dev->data->dev_started &&
2594             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2595              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2596             (new_pkt_size >
2597              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2598                 PMD_DRV_LOG(ERR,
2599                             "MTU change would require scattered rx support. ");
2600                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2601                 return -EINVAL;
2602         }
2603 #endif
2604
2605         if (new_mtu > RTE_ETHER_MTU) {
2606                 bp->flags |= BNXT_FLAG_JUMBO;
2607                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2608                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2609         } else {
2610                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2611                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2612                 bp->flags &= ~BNXT_FLAG_JUMBO;
2613         }
2614
2615         /* Is there a change in mtu setting? */
2616         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2617                 return rc;
2618
2619         for (i = 0; i < bp->nr_vnics; i++) {
2620                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2621                 uint16_t size = 0;
2622
2623                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2624                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2625                 if (rc)
2626                         break;
2627
2628                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2629                 size -= RTE_PKTMBUF_HEADROOM;
2630
2631                 if (size < new_mtu) {
2632                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2633                         if (rc)
2634                                 return rc;
2635                 }
2636         }
2637
2638         if (!rc)
2639                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2640
2641         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2642
2643         return rc;
2644 }
2645
2646 static int
2647 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2648 {
2649         struct bnxt *bp = dev->data->dev_private;
2650         uint16_t vlan = bp->vlan;
2651         int rc;
2652
2653         rc = is_bnxt_in_error(bp);
2654         if (rc)
2655                 return rc;
2656
2657         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2658                 PMD_DRV_LOG(ERR,
2659                         "PVID cannot be modified for this function\n");
2660                 return -ENOTSUP;
2661         }
2662         bp->vlan = on ? pvid : 0;
2663
2664         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2665         if (rc)
2666                 bp->vlan = vlan;
2667         return rc;
2668 }
2669
2670 static int
2671 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2672 {
2673         struct bnxt *bp = dev->data->dev_private;
2674         int rc;
2675
2676         rc = is_bnxt_in_error(bp);
2677         if (rc)
2678                 return rc;
2679
2680         return bnxt_hwrm_port_led_cfg(bp, true);
2681 }
2682
2683 static int
2684 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2685 {
2686         struct bnxt *bp = dev->data->dev_private;
2687         int rc;
2688
2689         rc = is_bnxt_in_error(bp);
2690         if (rc)
2691                 return rc;
2692
2693         return bnxt_hwrm_port_led_cfg(bp, false);
2694 }
2695
2696 static uint32_t
2697 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2698 {
2699         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2700         uint32_t desc = 0, raw_cons = 0, cons;
2701         struct bnxt_cp_ring_info *cpr;
2702         struct bnxt_rx_queue *rxq;
2703         struct rx_pkt_cmpl *rxcmp;
2704         int rc;
2705
2706         rc = is_bnxt_in_error(bp);
2707         if (rc)
2708                 return rc;
2709
2710         rxq = dev->data->rx_queues[rx_queue_id];
2711         cpr = rxq->cp_ring;
2712         raw_cons = cpr->cp_raw_cons;
2713
2714         while (1) {
2715                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2716                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2717                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2718
2719                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2720                         break;
2721                 } else {
2722                         raw_cons++;
2723                         desc++;
2724                 }
2725         }
2726
2727         return desc;
2728 }
2729
2730 static int
2731 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2732 {
2733         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2734         struct bnxt_rx_ring_info *rxr;
2735         struct bnxt_cp_ring_info *cpr;
2736         struct bnxt_sw_rx_bd *rx_buf;
2737         struct rx_pkt_cmpl *rxcmp;
2738         uint32_t cons, cp_cons;
2739         int rc;
2740
2741         if (!rxq)
2742                 return -EINVAL;
2743
2744         rc = is_bnxt_in_error(rxq->bp);
2745         if (rc)
2746                 return rc;
2747
2748         cpr = rxq->cp_ring;
2749         rxr = rxq->rx_ring;
2750
2751         if (offset >= rxq->nb_rx_desc)
2752                 return -EINVAL;
2753
2754         cons = RING_CMP(cpr->cp_ring_struct, offset);
2755         cp_cons = cpr->cp_raw_cons;
2756         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2757
2758         if (cons > cp_cons) {
2759                 if (CMPL_VALID(rxcmp, cpr->valid))
2760                         return RTE_ETH_RX_DESC_DONE;
2761         } else {
2762                 if (CMPL_VALID(rxcmp, !cpr->valid))
2763                         return RTE_ETH_RX_DESC_DONE;
2764         }
2765         rx_buf = &rxr->rx_buf_ring[cons];
2766         if (rx_buf->mbuf == NULL)
2767                 return RTE_ETH_RX_DESC_UNAVAIL;
2768
2769
2770         return RTE_ETH_RX_DESC_AVAIL;
2771 }
2772
2773 static int
2774 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2775 {
2776         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2777         struct bnxt_tx_ring_info *txr;
2778         struct bnxt_cp_ring_info *cpr;
2779         struct bnxt_sw_tx_bd *tx_buf;
2780         struct tx_pkt_cmpl *txcmp;
2781         uint32_t cons, cp_cons;
2782         int rc;
2783
2784         if (!txq)
2785                 return -EINVAL;
2786
2787         rc = is_bnxt_in_error(txq->bp);
2788         if (rc)
2789                 return rc;
2790
2791         cpr = txq->cp_ring;
2792         txr = txq->tx_ring;
2793
2794         if (offset >= txq->nb_tx_desc)
2795                 return -EINVAL;
2796
2797         cons = RING_CMP(cpr->cp_ring_struct, offset);
2798         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2799         cp_cons = cpr->cp_raw_cons;
2800
2801         if (cons > cp_cons) {
2802                 if (CMPL_VALID(txcmp, cpr->valid))
2803                         return RTE_ETH_TX_DESC_UNAVAIL;
2804         } else {
2805                 if (CMPL_VALID(txcmp, !cpr->valid))
2806                         return RTE_ETH_TX_DESC_UNAVAIL;
2807         }
2808         tx_buf = &txr->tx_buf_ring[cons];
2809         if (tx_buf->mbuf == NULL)
2810                 return RTE_ETH_TX_DESC_DONE;
2811
2812         return RTE_ETH_TX_DESC_FULL;
2813 }
2814
2815 static struct bnxt_filter_info *
2816 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2817                                 struct rte_eth_ethertype_filter *efilter,
2818                                 struct bnxt_vnic_info *vnic0,
2819                                 struct bnxt_vnic_info *vnic,
2820                                 int *ret)
2821 {
2822         struct bnxt_filter_info *mfilter = NULL;
2823         int match = 0;
2824         *ret = 0;
2825
2826         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2827                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2828                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2829                         " ethertype filter.", efilter->ether_type);
2830                 *ret = -EINVAL;
2831                 goto exit;
2832         }
2833         if (efilter->queue >= bp->rx_nr_rings) {
2834                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2835                 *ret = -EINVAL;
2836                 goto exit;
2837         }
2838
2839         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2840         vnic = &bp->vnic_info[efilter->queue];
2841         if (vnic == NULL) {
2842                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2843                 *ret = -EINVAL;
2844                 goto exit;
2845         }
2846
2847         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2848                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2849                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2850                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2851                              mfilter->flags ==
2852                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2853                              mfilter->ethertype == efilter->ether_type)) {
2854                                 match = 1;
2855                                 break;
2856                         }
2857                 }
2858         } else {
2859                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2860                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2861                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2862                              mfilter->ethertype == efilter->ether_type &&
2863                              mfilter->flags ==
2864                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2865                                 match = 1;
2866                                 break;
2867                         }
2868         }
2869
2870         if (match)
2871                 *ret = -EEXIST;
2872
2873 exit:
2874         return mfilter;
2875 }
2876
2877 static int
2878 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2879                         enum rte_filter_op filter_op,
2880                         void *arg)
2881 {
2882         struct bnxt *bp = dev->data->dev_private;
2883         struct rte_eth_ethertype_filter *efilter =
2884                         (struct rte_eth_ethertype_filter *)arg;
2885         struct bnxt_filter_info *bfilter, *filter1;
2886         struct bnxt_vnic_info *vnic, *vnic0;
2887         int ret;
2888
2889         if (filter_op == RTE_ETH_FILTER_NOP)
2890                 return 0;
2891
2892         if (arg == NULL) {
2893                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2894                             filter_op);
2895                 return -EINVAL;
2896         }
2897
2898         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2899         vnic = &bp->vnic_info[efilter->queue];
2900
2901         switch (filter_op) {
2902         case RTE_ETH_FILTER_ADD:
2903                 bnxt_match_and_validate_ether_filter(bp, efilter,
2904                                                         vnic0, vnic, &ret);
2905                 if (ret < 0)
2906                         return ret;
2907
2908                 bfilter = bnxt_get_unused_filter(bp);
2909                 if (bfilter == NULL) {
2910                         PMD_DRV_LOG(ERR,
2911                                 "Not enough resources for a new filter.\n");
2912                         return -ENOMEM;
2913                 }
2914                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2915                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2916                        RTE_ETHER_ADDR_LEN);
2917                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2918                        RTE_ETHER_ADDR_LEN);
2919                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2920                 bfilter->ethertype = efilter->ether_type;
2921                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2922
2923                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2924                 if (filter1 == NULL) {
2925                         ret = -EINVAL;
2926                         goto cleanup;
2927                 }
2928                 bfilter->enables |=
2929                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2930                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2931
2932                 bfilter->dst_id = vnic->fw_vnic_id;
2933
2934                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2935                         bfilter->flags =
2936                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2937                 }
2938
2939                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2940                 if (ret)
2941                         goto cleanup;
2942                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2943                 break;
2944         case RTE_ETH_FILTER_DELETE:
2945                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2946                                                         vnic0, vnic, &ret);
2947                 if (ret == -EEXIST) {
2948                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2949
2950                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2951                                       next);
2952                         bnxt_free_filter(bp, filter1);
2953                 } else if (ret == 0) {
2954                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2955                 }
2956                 break;
2957         default:
2958                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2959                 ret = -EINVAL;
2960                 goto error;
2961         }
2962         return ret;
2963 cleanup:
2964         bnxt_free_filter(bp, bfilter);
2965 error:
2966         return ret;
2967 }
2968
2969 static inline int
2970 parse_ntuple_filter(struct bnxt *bp,
2971                     struct rte_eth_ntuple_filter *nfilter,
2972                     struct bnxt_filter_info *bfilter)
2973 {
2974         uint32_t en = 0;
2975
2976         if (nfilter->queue >= bp->rx_nr_rings) {
2977                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2978                 return -EINVAL;
2979         }
2980
2981         switch (nfilter->dst_port_mask) {
2982         case UINT16_MAX:
2983                 bfilter->dst_port_mask = -1;
2984                 bfilter->dst_port = nfilter->dst_port;
2985                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2986                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2987                 break;
2988         default:
2989                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2990                 return -EINVAL;
2991         }
2992
2993         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2994         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2995
2996         switch (nfilter->proto_mask) {
2997         case UINT8_MAX:
2998                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2999                         bfilter->ip_protocol = 17;
3000                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
3001                         bfilter->ip_protocol = 6;
3002                 else
3003                         return -EINVAL;
3004                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3005                 break;
3006         default:
3007                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3008                 return -EINVAL;
3009         }
3010
3011         switch (nfilter->dst_ip_mask) {
3012         case UINT32_MAX:
3013                 bfilter->dst_ipaddr_mask[0] = -1;
3014                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
3015                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
3016                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3017                 break;
3018         default:
3019                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3020                 return -EINVAL;
3021         }
3022
3023         switch (nfilter->src_ip_mask) {
3024         case UINT32_MAX:
3025                 bfilter->src_ipaddr_mask[0] = -1;
3026                 bfilter->src_ipaddr[0] = nfilter->src_ip;
3027                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
3028                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3029                 break;
3030         default:
3031                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3032                 return -EINVAL;
3033         }
3034
3035         switch (nfilter->src_port_mask) {
3036         case UINT16_MAX:
3037                 bfilter->src_port_mask = -1;
3038                 bfilter->src_port = nfilter->src_port;
3039                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
3040                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3041                 break;
3042         default:
3043                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3044                 return -EINVAL;
3045         }
3046
3047         bfilter->enables = en;
3048         return 0;
3049 }
3050
3051 static struct bnxt_filter_info*
3052 bnxt_match_ntuple_filter(struct bnxt *bp,
3053                          struct bnxt_filter_info *bfilter,
3054                          struct bnxt_vnic_info **mvnic)
3055 {
3056         struct bnxt_filter_info *mfilter = NULL;
3057         int i;
3058
3059         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3060                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3061                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
3062                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
3063                             bfilter->src_ipaddr_mask[0] ==
3064                             mfilter->src_ipaddr_mask[0] &&
3065                             bfilter->src_port == mfilter->src_port &&
3066                             bfilter->src_port_mask == mfilter->src_port_mask &&
3067                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
3068                             bfilter->dst_ipaddr_mask[0] ==
3069                             mfilter->dst_ipaddr_mask[0] &&
3070                             bfilter->dst_port == mfilter->dst_port &&
3071                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
3072                             bfilter->flags == mfilter->flags &&
3073                             bfilter->enables == mfilter->enables) {
3074                                 if (mvnic)
3075                                         *mvnic = vnic;
3076                                 return mfilter;
3077                         }
3078                 }
3079         }
3080         return NULL;
3081 }
3082
3083 static int
3084 bnxt_cfg_ntuple_filter(struct bnxt *bp,
3085                        struct rte_eth_ntuple_filter *nfilter,
3086                        enum rte_filter_op filter_op)
3087 {
3088         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
3089         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
3090         int ret;
3091
3092         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
3093                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3094                 return -EINVAL;
3095         }
3096
3097         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
3098                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
3099                 return -EINVAL;
3100         }
3101
3102         bfilter = bnxt_get_unused_filter(bp);
3103         if (bfilter == NULL) {
3104                 PMD_DRV_LOG(ERR,
3105                         "Not enough resources for a new filter.\n");
3106                 return -ENOMEM;
3107         }
3108         ret = parse_ntuple_filter(bp, nfilter, bfilter);
3109         if (ret < 0)
3110                 goto free_filter;
3111
3112         vnic = &bp->vnic_info[nfilter->queue];
3113         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3114         filter1 = STAILQ_FIRST(&vnic0->filter);
3115         if (filter1 == NULL) {
3116                 ret = -EINVAL;
3117                 goto free_filter;
3118         }
3119
3120         bfilter->dst_id = vnic->fw_vnic_id;
3121         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3122         bfilter->enables |=
3123                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3124         bfilter->ethertype = 0x800;
3125         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3126
3127         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3128
3129         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3130             bfilter->dst_id == mfilter->dst_id) {
3131                 PMD_DRV_LOG(ERR, "filter exists.\n");
3132                 ret = -EEXIST;
3133                 goto free_filter;
3134         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3135                    bfilter->dst_id != mfilter->dst_id) {
3136                 mfilter->dst_id = vnic->fw_vnic_id;
3137                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3138                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3139                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3140                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3141                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3142                 goto free_filter;
3143         }
3144         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3145                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3146                 ret = -ENOENT;
3147                 goto free_filter;
3148         }
3149
3150         if (filter_op == RTE_ETH_FILTER_ADD) {
3151                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3152                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3153                 if (ret)
3154                         goto free_filter;
3155                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3156         } else {
3157                 if (mfilter == NULL) {
3158                         /* This should not happen. But for Coverity! */
3159                         ret = -ENOENT;
3160                         goto free_filter;
3161                 }
3162                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3163
3164                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3165                 bnxt_free_filter(bp, mfilter);
3166                 bnxt_free_filter(bp, bfilter);
3167         }
3168
3169         return 0;
3170 free_filter:
3171         bnxt_free_filter(bp, bfilter);
3172         return ret;
3173 }
3174
3175 static int
3176 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3177                         enum rte_filter_op filter_op,
3178                         void *arg)
3179 {
3180         struct bnxt *bp = dev->data->dev_private;
3181         int ret;
3182
3183         if (filter_op == RTE_ETH_FILTER_NOP)
3184                 return 0;
3185
3186         if (arg == NULL) {
3187                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3188                             filter_op);
3189                 return -EINVAL;
3190         }
3191
3192         switch (filter_op) {
3193         case RTE_ETH_FILTER_ADD:
3194                 ret = bnxt_cfg_ntuple_filter(bp,
3195                         (struct rte_eth_ntuple_filter *)arg,
3196                         filter_op);
3197                 break;
3198         case RTE_ETH_FILTER_DELETE:
3199                 ret = bnxt_cfg_ntuple_filter(bp,
3200                         (struct rte_eth_ntuple_filter *)arg,
3201                         filter_op);
3202                 break;
3203         default:
3204                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3205                 ret = -EINVAL;
3206                 break;
3207         }
3208         return ret;
3209 }
3210
3211 static int
3212 bnxt_parse_fdir_filter(struct bnxt *bp,
3213                        struct rte_eth_fdir_filter *fdir,
3214                        struct bnxt_filter_info *filter)
3215 {
3216         enum rte_fdir_mode fdir_mode =
3217                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3218         struct bnxt_vnic_info *vnic0, *vnic;
3219         struct bnxt_filter_info *filter1;
3220         uint32_t en = 0;
3221         int i;
3222
3223         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3224                 return -EINVAL;
3225
3226         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3227         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3228
3229         switch (fdir->input.flow_type) {
3230         case RTE_ETH_FLOW_IPV4:
3231         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3232                 /* FALLTHROUGH */
3233                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3234                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3235                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3236                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3237                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3238                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3239                 filter->ip_addr_type =
3240                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3241                 filter->src_ipaddr_mask[0] = 0xffffffff;
3242                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3243                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3244                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3245                 filter->ethertype = 0x800;
3246                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3247                 break;
3248         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3249                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3250                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3251                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3252                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3253                 filter->dst_port_mask = 0xffff;
3254                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3255                 filter->src_port_mask = 0xffff;
3256                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3257                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3258                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3259                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3260                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3261                 filter->ip_protocol = 6;
3262                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3263                 filter->ip_addr_type =
3264                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3265                 filter->src_ipaddr_mask[0] = 0xffffffff;
3266                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3267                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3268                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3269                 filter->ethertype = 0x800;
3270                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3271                 break;
3272         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3273                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3274                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3275                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3276                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3277                 filter->dst_port_mask = 0xffff;
3278                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3279                 filter->src_port_mask = 0xffff;
3280                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3281                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3282                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3283                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3284                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3285                 filter->ip_protocol = 17;
3286                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3287                 filter->ip_addr_type =
3288                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3289                 filter->src_ipaddr_mask[0] = 0xffffffff;
3290                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3291                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3292                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3293                 filter->ethertype = 0x800;
3294                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3295                 break;
3296         case RTE_ETH_FLOW_IPV6:
3297         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3298                 /* FALLTHROUGH */
3299                 filter->ip_addr_type =
3300                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3301                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3302                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3303                 rte_memcpy(filter->src_ipaddr,
3304                            fdir->input.flow.ipv6_flow.src_ip, 16);
3305                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3306                 rte_memcpy(filter->dst_ipaddr,
3307                            fdir->input.flow.ipv6_flow.dst_ip, 16);
3308                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3309                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3310                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3311                 memset(filter->src_ipaddr_mask, 0xff, 16);
3312                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3313                 filter->ethertype = 0x86dd;
3314                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3315                 break;
3316         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3317                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3318                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3319                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3320                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3321                 filter->dst_port_mask = 0xffff;
3322                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3323                 filter->src_port_mask = 0xffff;
3324                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3325                 filter->ip_addr_type =
3326                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3327                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3328                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3329                 rte_memcpy(filter->src_ipaddr,
3330                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3331                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3332                 rte_memcpy(filter->dst_ipaddr,
3333                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3334                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3335                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3336                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3337                 memset(filter->src_ipaddr_mask, 0xff, 16);
3338                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3339                 filter->ethertype = 0x86dd;
3340                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3341                 break;
3342         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3343                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3344                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3345                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3346                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3347                 filter->dst_port_mask = 0xffff;
3348                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3349                 filter->src_port_mask = 0xffff;
3350                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3351                 filter->ip_addr_type =
3352                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3353                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3354                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3355                 rte_memcpy(filter->src_ipaddr,
3356                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3357                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3358                 rte_memcpy(filter->dst_ipaddr,
3359                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3360                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3361                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3362                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3363                 memset(filter->src_ipaddr_mask, 0xff, 16);
3364                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3365                 filter->ethertype = 0x86dd;
3366                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3367                 break;
3368         case RTE_ETH_FLOW_L2_PAYLOAD:
3369                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3370                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3371                 break;
3372         case RTE_ETH_FLOW_VXLAN:
3373                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3374                         return -EINVAL;
3375                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3376                 filter->tunnel_type =
3377                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3378                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3379                 break;
3380         case RTE_ETH_FLOW_NVGRE:
3381                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3382                         return -EINVAL;
3383                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3384                 filter->tunnel_type =
3385                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3386                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3387                 break;
3388         case RTE_ETH_FLOW_UNKNOWN:
3389         case RTE_ETH_FLOW_RAW:
3390         case RTE_ETH_FLOW_FRAG_IPV4:
3391         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3392         case RTE_ETH_FLOW_FRAG_IPV6:
3393         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3394         case RTE_ETH_FLOW_IPV6_EX:
3395         case RTE_ETH_FLOW_IPV6_TCP_EX:
3396         case RTE_ETH_FLOW_IPV6_UDP_EX:
3397         case RTE_ETH_FLOW_GENEVE:
3398                 /* FALLTHROUGH */
3399         default:
3400                 return -EINVAL;
3401         }
3402
3403         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3404         vnic = &bp->vnic_info[fdir->action.rx_queue];
3405         if (vnic == NULL) {
3406                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3407                 return -EINVAL;
3408         }
3409
3410         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3411                 rte_memcpy(filter->dst_macaddr,
3412                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3413                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3414         }
3415
3416         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3417                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3418                 filter1 = STAILQ_FIRST(&vnic0->filter);
3419                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3420         } else {
3421                 filter->dst_id = vnic->fw_vnic_id;
3422                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3423                         if (filter->dst_macaddr[i] == 0x00)
3424                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3425                         else
3426                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3427         }
3428
3429         if (filter1 == NULL)
3430                 return -EINVAL;
3431
3432         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3433         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3434
3435         filter->enables = en;
3436
3437         return 0;
3438 }
3439
3440 static struct bnxt_filter_info *
3441 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3442                 struct bnxt_vnic_info **mvnic)
3443 {
3444         struct bnxt_filter_info *mf = NULL;
3445         int i;
3446
3447         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3448                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3449
3450                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3451                         if (mf->filter_type == nf->filter_type &&
3452                             mf->flags == nf->flags &&
3453                             mf->src_port == nf->src_port &&
3454                             mf->src_port_mask == nf->src_port_mask &&
3455                             mf->dst_port == nf->dst_port &&
3456                             mf->dst_port_mask == nf->dst_port_mask &&
3457                             mf->ip_protocol == nf->ip_protocol &&
3458                             mf->ip_addr_type == nf->ip_addr_type &&
3459                             mf->ethertype == nf->ethertype &&
3460                             mf->vni == nf->vni &&
3461                             mf->tunnel_type == nf->tunnel_type &&
3462                             mf->l2_ovlan == nf->l2_ovlan &&
3463                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3464                             mf->l2_ivlan == nf->l2_ivlan &&
3465                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3466                             !memcmp(mf->l2_addr, nf->l2_addr,
3467                                     RTE_ETHER_ADDR_LEN) &&
3468                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3469                                     RTE_ETHER_ADDR_LEN) &&
3470                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3471                                     RTE_ETHER_ADDR_LEN) &&
3472                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3473                                     RTE_ETHER_ADDR_LEN) &&
3474                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3475                                     sizeof(nf->src_ipaddr)) &&
3476                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3477                                     sizeof(nf->src_ipaddr_mask)) &&
3478                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3479                                     sizeof(nf->dst_ipaddr)) &&
3480                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3481                                     sizeof(nf->dst_ipaddr_mask))) {
3482                                 if (mvnic)
3483                                         *mvnic = vnic;
3484                                 return mf;
3485                         }
3486                 }
3487         }
3488         return NULL;
3489 }
3490
3491 static int
3492 bnxt_fdir_filter(struct rte_eth_dev *dev,
3493                  enum rte_filter_op filter_op,
3494                  void *arg)
3495 {
3496         struct bnxt *bp = dev->data->dev_private;
3497         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3498         struct bnxt_filter_info *filter, *match;
3499         struct bnxt_vnic_info *vnic, *mvnic;
3500         int ret = 0, i;
3501
3502         if (filter_op == RTE_ETH_FILTER_NOP)
3503                 return 0;
3504
3505         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3506                 return -EINVAL;
3507
3508         switch (filter_op) {
3509         case RTE_ETH_FILTER_ADD:
3510         case RTE_ETH_FILTER_DELETE:
3511                 /* FALLTHROUGH */
3512                 filter = bnxt_get_unused_filter(bp);
3513                 if (filter == NULL) {
3514                         PMD_DRV_LOG(ERR,
3515                                 "Not enough resources for a new flow.\n");
3516                         return -ENOMEM;
3517                 }
3518
3519                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3520                 if (ret != 0)
3521                         goto free_filter;
3522                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3523
3524                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3525                         vnic = &bp->vnic_info[0];
3526                 else
3527                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3528
3529                 match = bnxt_match_fdir(bp, filter, &mvnic);
3530                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3531                         if (match->dst_id == vnic->fw_vnic_id) {
3532                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3533                                 ret = -EEXIST;
3534                                 goto free_filter;
3535                         } else {
3536                                 match->dst_id = vnic->fw_vnic_id;
3537                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3538                                                                   match->dst_id,
3539                                                                   match);
3540                                 STAILQ_REMOVE(&mvnic->filter, match,
3541                                               bnxt_filter_info, next);
3542                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3543                                 PMD_DRV_LOG(ERR,
3544                                         "Filter with matching pattern exist\n");
3545                                 PMD_DRV_LOG(ERR,
3546                                         "Updated it to new destination q\n");
3547                                 goto free_filter;
3548                         }
3549                 }
3550                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3551                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3552                         ret = -ENOENT;
3553                         goto free_filter;
3554                 }
3555
3556                 if (filter_op == RTE_ETH_FILTER_ADD) {
3557                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3558                                                           filter->dst_id,
3559                                                           filter);
3560                         if (ret)
3561                                 goto free_filter;
3562                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3563                 } else {
3564                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3565                         STAILQ_REMOVE(&vnic->filter, match,
3566                                       bnxt_filter_info, next);
3567                         bnxt_free_filter(bp, match);
3568                         bnxt_free_filter(bp, filter);
3569                 }
3570                 break;
3571         case RTE_ETH_FILTER_FLUSH:
3572                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3573                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3574
3575                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3576                                 if (filter->filter_type ==
3577                                     HWRM_CFA_NTUPLE_FILTER) {
3578                                         ret =
3579                                         bnxt_hwrm_clear_ntuple_filter(bp,
3580                                                                       filter);
3581                                         STAILQ_REMOVE(&vnic->filter, filter,
3582                                                       bnxt_filter_info, next);
3583                                 }
3584                         }
3585                 }
3586                 return ret;
3587         case RTE_ETH_FILTER_UPDATE:
3588         case RTE_ETH_FILTER_STATS:
3589         case RTE_ETH_FILTER_INFO:
3590                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3591                 break;
3592         default:
3593                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3594                 ret = -EINVAL;
3595                 break;
3596         }
3597         return ret;
3598
3599 free_filter:
3600         bnxt_free_filter(bp, filter);
3601         return ret;
3602 }
3603
3604 static int
3605 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3606                     enum rte_filter_type filter_type,
3607                     enum rte_filter_op filter_op, void *arg)
3608 {
3609         struct bnxt *bp = dev->data->dev_private;
3610         int ret = 0;
3611
3612         ret = is_bnxt_in_error(dev->data->dev_private);
3613         if (ret)
3614                 return ret;
3615
3616         switch (filter_type) {
3617         case RTE_ETH_FILTER_TUNNEL:
3618                 PMD_DRV_LOG(ERR,
3619                         "filter type: %d: To be implemented\n", filter_type);
3620                 break;
3621         case RTE_ETH_FILTER_FDIR:
3622                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3623                 break;
3624         case RTE_ETH_FILTER_NTUPLE:
3625                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3626                 break;
3627         case RTE_ETH_FILTER_ETHERTYPE:
3628                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3629                 break;
3630         case RTE_ETH_FILTER_GENERIC:
3631                 if (filter_op != RTE_ETH_FILTER_GET)
3632                         return -EINVAL;
3633                 if (bp->truflow)
3634                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3635                 else
3636                         *(const void **)arg = &bnxt_flow_ops;
3637                 break;
3638         default:
3639                 PMD_DRV_LOG(ERR,
3640                         "Filter type (%d) not supported", filter_type);
3641                 ret = -EINVAL;
3642                 break;
3643         }
3644         return ret;
3645 }
3646
3647 static const uint32_t *
3648 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3649 {
3650         static const uint32_t ptypes[] = {
3651                 RTE_PTYPE_L2_ETHER_VLAN,
3652                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3653                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3654                 RTE_PTYPE_L4_ICMP,
3655                 RTE_PTYPE_L4_TCP,
3656                 RTE_PTYPE_L4_UDP,
3657                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3658                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3659                 RTE_PTYPE_INNER_L4_ICMP,
3660                 RTE_PTYPE_INNER_L4_TCP,
3661                 RTE_PTYPE_INNER_L4_UDP,
3662                 RTE_PTYPE_UNKNOWN
3663         };
3664
3665         if (!dev->rx_pkt_burst)
3666                 return NULL;
3667
3668         return ptypes;
3669 }
3670
3671 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3672                          int reg_win)
3673 {
3674         uint32_t reg_base = *reg_arr & 0xfffff000;
3675         uint32_t win_off;
3676         int i;
3677
3678         for (i = 0; i < count; i++) {
3679                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3680                         return -ERANGE;
3681         }
3682         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3683         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3684         return 0;
3685 }
3686
3687 static int bnxt_map_ptp_regs(struct bnxt *bp)
3688 {
3689         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3690         uint32_t *reg_arr;
3691         int rc, i;
3692
3693         reg_arr = ptp->rx_regs;
3694         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3695         if (rc)
3696                 return rc;
3697
3698         reg_arr = ptp->tx_regs;
3699         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3700         if (rc)
3701                 return rc;
3702
3703         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3704                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3705
3706         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3707                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3708
3709         return 0;
3710 }
3711
3712 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3713 {
3714         rte_write32(0, (uint8_t *)bp->bar0 +
3715                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3716         rte_write32(0, (uint8_t *)bp->bar0 +
3717                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3718 }
3719
3720 static uint64_t bnxt_cc_read(struct bnxt *bp)
3721 {
3722         uint64_t ns;
3723
3724         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3725                               BNXT_GRCPF_REG_SYNC_TIME));
3726         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3727                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3728         return ns;
3729 }
3730
3731 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3732 {
3733         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3734         uint32_t fifo;
3735
3736         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3737                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3738         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3739                 return -EAGAIN;
3740
3741         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3742                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3743         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3744                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3745         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3746                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3747
3748         return 0;
3749 }
3750
3751 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3752 {
3753         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3754         struct bnxt_pf_info *pf = &bp->pf;
3755         uint16_t port_id;
3756         uint32_t fifo;
3757
3758         if (!ptp)
3759                 return -ENODEV;
3760
3761         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3762                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3763         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3764                 return -EAGAIN;
3765
3766         port_id = pf->port_id;
3767         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3768                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3769
3770         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3771                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3772         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3773 /*              bnxt_clr_rx_ts(bp);       TBD  */
3774                 return -EBUSY;
3775         }
3776
3777         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3778                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3779         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3780                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3781
3782         return 0;
3783 }
3784
3785 static int
3786 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3787 {
3788         uint64_t ns;
3789         struct bnxt *bp = dev->data->dev_private;
3790         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3791
3792         if (!ptp)
3793                 return 0;
3794
3795         ns = rte_timespec_to_ns(ts);
3796         /* Set the timecounters to a new value. */
3797         ptp->tc.nsec = ns;
3798
3799         return 0;
3800 }
3801
3802 static int
3803 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3804 {
3805         struct bnxt *bp = dev->data->dev_private;
3806         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3807         uint64_t ns, systime_cycles = 0;
3808         int rc = 0;
3809
3810         if (!ptp)
3811                 return 0;
3812
3813         if (BNXT_CHIP_THOR(bp))
3814                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3815                                              &systime_cycles);
3816         else
3817                 systime_cycles = bnxt_cc_read(bp);
3818
3819         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3820         *ts = rte_ns_to_timespec(ns);
3821
3822         return rc;
3823 }
3824 static int
3825 bnxt_timesync_enable(struct rte_eth_dev *dev)
3826 {
3827         struct bnxt *bp = dev->data->dev_private;
3828         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3829         uint32_t shift = 0;
3830         int rc;
3831
3832         if (!ptp)
3833                 return 0;
3834
3835         ptp->rx_filter = 1;
3836         ptp->tx_tstamp_en = 1;
3837         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3838
3839         rc = bnxt_hwrm_ptp_cfg(bp);
3840         if (rc)
3841                 return rc;
3842
3843         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3844         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3845         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3846
3847         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3848         ptp->tc.cc_shift = shift;
3849         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3850
3851         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3852         ptp->rx_tstamp_tc.cc_shift = shift;
3853         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3854
3855         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3856         ptp->tx_tstamp_tc.cc_shift = shift;
3857         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3858
3859         if (!BNXT_CHIP_THOR(bp))
3860                 bnxt_map_ptp_regs(bp);
3861
3862         return 0;
3863 }
3864
3865 static int
3866 bnxt_timesync_disable(struct rte_eth_dev *dev)
3867 {
3868         struct bnxt *bp = dev->data->dev_private;
3869         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3870
3871         if (!ptp)
3872                 return 0;
3873
3874         ptp->rx_filter = 0;
3875         ptp->tx_tstamp_en = 0;
3876         ptp->rxctl = 0;
3877
3878         bnxt_hwrm_ptp_cfg(bp);
3879
3880         if (!BNXT_CHIP_THOR(bp))
3881                 bnxt_unmap_ptp_regs(bp);
3882
3883         return 0;
3884 }
3885
3886 static int
3887 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3888                                  struct timespec *timestamp,
3889                                  uint32_t flags __rte_unused)
3890 {
3891         struct bnxt *bp = dev->data->dev_private;
3892         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3893         uint64_t rx_tstamp_cycles = 0;
3894         uint64_t ns;
3895
3896         if (!ptp)
3897                 return 0;
3898
3899         if (BNXT_CHIP_THOR(bp))
3900                 rx_tstamp_cycles = ptp->rx_timestamp;
3901         else
3902                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3903
3904         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3905         *timestamp = rte_ns_to_timespec(ns);
3906         return  0;
3907 }
3908
3909 static int
3910 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3911                                  struct timespec *timestamp)
3912 {
3913         struct bnxt *bp = dev->data->dev_private;
3914         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3915         uint64_t tx_tstamp_cycles = 0;
3916         uint64_t ns;
3917         int rc = 0;
3918
3919         if (!ptp)
3920                 return 0;
3921
3922         if (BNXT_CHIP_THOR(bp))
3923                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3924                                              &tx_tstamp_cycles);
3925         else
3926                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3927
3928         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3929         *timestamp = rte_ns_to_timespec(ns);
3930
3931         return rc;
3932 }
3933
3934 static int
3935 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3936 {
3937         struct bnxt *bp = dev->data->dev_private;
3938         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3939
3940         if (!ptp)
3941                 return 0;
3942
3943         ptp->tc.nsec += delta;
3944
3945         return 0;
3946 }
3947
3948 static int
3949 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3950 {
3951         struct bnxt *bp = dev->data->dev_private;
3952         int rc;
3953         uint32_t dir_entries;
3954         uint32_t entry_length;
3955
3956         rc = is_bnxt_in_error(bp);
3957         if (rc)
3958                 return rc;
3959
3960         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3961                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3962                     bp->pdev->addr.devid, bp->pdev->addr.function);
3963
3964         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3965         if (rc != 0)
3966                 return rc;
3967
3968         return dir_entries * entry_length;
3969 }
3970
3971 static int
3972 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3973                 struct rte_dev_eeprom_info *in_eeprom)
3974 {
3975         struct bnxt *bp = dev->data->dev_private;
3976         uint32_t index;
3977         uint32_t offset;
3978         int rc;
3979
3980         rc = is_bnxt_in_error(bp);
3981         if (rc)
3982                 return rc;
3983
3984         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3985                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3986                     bp->pdev->addr.devid, bp->pdev->addr.function,
3987                     in_eeprom->offset, in_eeprom->length);
3988
3989         if (in_eeprom->offset == 0) /* special offset value to get directory */
3990                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3991                                                 in_eeprom->data);
3992
3993         index = in_eeprom->offset >> 24;
3994         offset = in_eeprom->offset & 0xffffff;
3995
3996         if (index != 0)
3997                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3998                                            in_eeprom->length, in_eeprom->data);
3999
4000         return 0;
4001 }
4002
4003 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
4004 {
4005         switch (dir_type) {
4006         case BNX_DIR_TYPE_CHIMP_PATCH:
4007         case BNX_DIR_TYPE_BOOTCODE:
4008         case BNX_DIR_TYPE_BOOTCODE_2:
4009         case BNX_DIR_TYPE_APE_FW:
4010         case BNX_DIR_TYPE_APE_PATCH:
4011         case BNX_DIR_TYPE_KONG_FW:
4012         case BNX_DIR_TYPE_KONG_PATCH:
4013         case BNX_DIR_TYPE_BONO_FW:
4014         case BNX_DIR_TYPE_BONO_PATCH:
4015                 /* FALLTHROUGH */
4016                 return true;
4017         }
4018
4019         return false;
4020 }
4021
4022 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
4023 {
4024         switch (dir_type) {
4025         case BNX_DIR_TYPE_AVS:
4026         case BNX_DIR_TYPE_EXP_ROM_MBA:
4027         case BNX_DIR_TYPE_PCIE:
4028         case BNX_DIR_TYPE_TSCF_UCODE:
4029         case BNX_DIR_TYPE_EXT_PHY:
4030         case BNX_DIR_TYPE_CCM:
4031         case BNX_DIR_TYPE_ISCSI_BOOT:
4032         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
4033         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
4034                 /* FALLTHROUGH */
4035                 return true;
4036         }
4037
4038         return false;
4039 }
4040
4041 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
4042 {
4043         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
4044                 bnxt_dir_type_is_other_exec_format(dir_type);
4045 }
4046
4047 static int
4048 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
4049                 struct rte_dev_eeprom_info *in_eeprom)
4050 {
4051         struct bnxt *bp = dev->data->dev_private;
4052         uint8_t index, dir_op;
4053         uint16_t type, ext, ordinal, attr;
4054         int rc;
4055
4056         rc = is_bnxt_in_error(bp);
4057         if (rc)
4058                 return rc;
4059
4060         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4061                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4062                     bp->pdev->addr.devid, bp->pdev->addr.function,
4063                     in_eeprom->offset, in_eeprom->length);
4064
4065         if (!BNXT_PF(bp)) {
4066                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
4067                 return -EINVAL;
4068         }
4069
4070         type = in_eeprom->magic >> 16;
4071
4072         if (type == 0xffff) { /* special value for directory operations */
4073                 index = in_eeprom->magic & 0xff;
4074                 dir_op = in_eeprom->magic >> 8;
4075                 if (index == 0)
4076                         return -EINVAL;
4077                 switch (dir_op) {
4078                 case 0x0e: /* erase */
4079                         if (in_eeprom->offset != ~in_eeprom->magic)
4080                                 return -EINVAL;
4081                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
4082                 default:
4083                         return -EINVAL;
4084                 }
4085         }
4086
4087         /* Create or re-write an NVM item: */
4088         if (bnxt_dir_type_is_executable(type) == true)
4089                 return -EOPNOTSUPP;
4090         ext = in_eeprom->magic & 0xffff;
4091         ordinal = in_eeprom->offset >> 16;
4092         attr = in_eeprom->offset & 0xffff;
4093
4094         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
4095                                      in_eeprom->data, in_eeprom->length);
4096 }
4097
4098 /*
4099  * Initialization
4100  */
4101
4102 static const struct eth_dev_ops bnxt_dev_ops = {
4103         .dev_infos_get = bnxt_dev_info_get_op,
4104         .dev_close = bnxt_dev_close_op,
4105         .dev_configure = bnxt_dev_configure_op,
4106         .dev_start = bnxt_dev_start_op,
4107         .dev_stop = bnxt_dev_stop_op,
4108         .dev_set_link_up = bnxt_dev_set_link_up_op,
4109         .dev_set_link_down = bnxt_dev_set_link_down_op,
4110         .stats_get = bnxt_stats_get_op,
4111         .stats_reset = bnxt_stats_reset_op,
4112         .rx_queue_setup = bnxt_rx_queue_setup_op,
4113         .rx_queue_release = bnxt_rx_queue_release_op,
4114         .tx_queue_setup = bnxt_tx_queue_setup_op,
4115         .tx_queue_release = bnxt_tx_queue_release_op,
4116         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4117         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4118         .reta_update = bnxt_reta_update_op,
4119         .reta_query = bnxt_reta_query_op,
4120         .rss_hash_update = bnxt_rss_hash_update_op,
4121         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4122         .link_update = bnxt_link_update_op,
4123         .promiscuous_enable = bnxt_promiscuous_enable_op,
4124         .promiscuous_disable = bnxt_promiscuous_disable_op,
4125         .allmulticast_enable = bnxt_allmulticast_enable_op,
4126         .allmulticast_disable = bnxt_allmulticast_disable_op,
4127         .mac_addr_add = bnxt_mac_addr_add_op,
4128         .mac_addr_remove = bnxt_mac_addr_remove_op,
4129         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4130         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4131         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4132         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4133         .vlan_filter_set = bnxt_vlan_filter_set_op,
4134         .vlan_offload_set = bnxt_vlan_offload_set_op,
4135         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4136         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4137         .mtu_set = bnxt_mtu_set_op,
4138         .mac_addr_set = bnxt_set_default_mac_addr_op,
4139         .xstats_get = bnxt_dev_xstats_get_op,
4140         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4141         .xstats_reset = bnxt_dev_xstats_reset_op,
4142         .fw_version_get = bnxt_fw_version_get,
4143         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4144         .rxq_info_get = bnxt_rxq_info_get_op,
4145         .txq_info_get = bnxt_txq_info_get_op,
4146         .dev_led_on = bnxt_dev_led_on_op,
4147         .dev_led_off = bnxt_dev_led_off_op,
4148         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4149         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4150         .rx_queue_count = bnxt_rx_queue_count_op,
4151         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
4152         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
4153         .rx_queue_start = bnxt_rx_queue_start,
4154         .rx_queue_stop = bnxt_rx_queue_stop,
4155         .tx_queue_start = bnxt_tx_queue_start,
4156         .tx_queue_stop = bnxt_tx_queue_stop,
4157         .filter_ctrl = bnxt_filter_ctrl_op,
4158         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4159         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4160         .get_eeprom           = bnxt_get_eeprom_op,
4161         .set_eeprom           = bnxt_set_eeprom_op,
4162         .timesync_enable      = bnxt_timesync_enable,
4163         .timesync_disable     = bnxt_timesync_disable,
4164         .timesync_read_time   = bnxt_timesync_read_time,
4165         .timesync_write_time   = bnxt_timesync_write_time,
4166         .timesync_adjust_time = bnxt_timesync_adjust_time,
4167         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4168         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4169 };
4170
4171 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4172 {
4173         uint32_t offset;
4174
4175         /* Only pre-map the reset GRC registers using window 3 */
4176         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4177                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4178
4179         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4180
4181         return offset;
4182 }
4183
4184 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4185 {
4186         struct bnxt_error_recovery_info *info = bp->recovery_info;
4187         uint32_t reg_base = 0xffffffff;
4188         int i;
4189
4190         /* Only pre-map the monitoring GRC registers using window 2 */
4191         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4192                 uint32_t reg = info->status_regs[i];
4193
4194                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4195                         continue;
4196
4197                 if (reg_base == 0xffffffff)
4198                         reg_base = reg & 0xfffff000;
4199                 if ((reg & 0xfffff000) != reg_base)
4200                         return -ERANGE;
4201
4202                 /* Use mask 0xffc as the Lower 2 bits indicates
4203                  * address space location
4204                  */
4205                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4206                                                 (reg & 0xffc);
4207         }
4208
4209         if (reg_base == 0xffffffff)
4210                 return 0;
4211
4212         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4213                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4214
4215         return 0;
4216 }
4217
4218 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4219 {
4220         struct bnxt_error_recovery_info *info = bp->recovery_info;
4221         uint32_t delay = info->delay_after_reset[index];
4222         uint32_t val = info->reset_reg_val[index];
4223         uint32_t reg = info->reset_reg[index];
4224         uint32_t type, offset;
4225
4226         type = BNXT_FW_STATUS_REG_TYPE(reg);
4227         offset = BNXT_FW_STATUS_REG_OFF(reg);
4228
4229         switch (type) {
4230         case BNXT_FW_STATUS_REG_TYPE_CFG:
4231                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4232                 break;
4233         case BNXT_FW_STATUS_REG_TYPE_GRC:
4234                 offset = bnxt_map_reset_regs(bp, offset);
4235                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4236                 break;
4237         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4238                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4239                 break;
4240         }
4241         /* wait on a specific interval of time until core reset is complete */
4242         if (delay)
4243                 rte_delay_ms(delay);
4244 }
4245
4246 static void bnxt_dev_cleanup(struct bnxt *bp)
4247 {
4248         bnxt_set_hwrm_link_config(bp, false);
4249         bp->link_info->link_up = 0;
4250         if (bp->eth_dev->data->dev_started)
4251                 bnxt_dev_stop_op(bp->eth_dev);
4252
4253         bnxt_uninit_resources(bp, true);
4254 }
4255
4256 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4257 {
4258         struct rte_eth_dev *dev = bp->eth_dev;
4259         struct rte_vlan_filter_conf *vfc;
4260         int vidx, vbit, rc;
4261         uint16_t vlan_id;
4262
4263         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4264                 vfc = &dev->data->vlan_filter_conf;
4265                 vidx = vlan_id / 64;
4266                 vbit = vlan_id % 64;
4267
4268                 /* Each bit corresponds to a VLAN id */
4269                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4270                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4271                         if (rc)
4272                                 return rc;
4273                 }
4274         }
4275
4276         return 0;
4277 }
4278
4279 static int bnxt_restore_mac_filters(struct bnxt *bp)
4280 {
4281         struct rte_eth_dev *dev = bp->eth_dev;
4282         struct rte_eth_dev_info dev_info;
4283         struct rte_ether_addr *addr;
4284         uint64_t pool_mask;
4285         uint32_t pool = 0;
4286         uint16_t i;
4287         int rc;
4288
4289         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
4290                 return 0;
4291
4292         rc = bnxt_dev_info_get_op(dev, &dev_info);
4293         if (rc)
4294                 return rc;
4295
4296         /* replay MAC address configuration */
4297         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4298                 addr = &dev->data->mac_addrs[i];
4299
4300                 /* skip zero address */
4301                 if (rte_is_zero_ether_addr(addr))
4302                         continue;
4303
4304                 pool = 0;
4305                 pool_mask = dev->data->mac_pool_sel[i];
4306
4307                 do {
4308                         if (pool_mask & 1ULL) {
4309                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4310                                 if (rc)
4311                                         return rc;
4312                         }
4313                         pool_mask >>= 1;
4314                         pool++;
4315                 } while (pool_mask);
4316         }
4317
4318         return 0;
4319 }
4320
4321 static int bnxt_restore_filters(struct bnxt *bp)
4322 {
4323         struct rte_eth_dev *dev = bp->eth_dev;
4324         int ret = 0;
4325
4326         if (dev->data->all_multicast) {
4327                 ret = bnxt_allmulticast_enable_op(dev);
4328                 if (ret)
4329                         return ret;
4330         }
4331         if (dev->data->promiscuous) {
4332                 ret = bnxt_promiscuous_enable_op(dev);
4333                 if (ret)
4334                         return ret;
4335         }
4336
4337         ret = bnxt_restore_mac_filters(bp);
4338         if (ret)
4339                 return ret;
4340
4341         ret = bnxt_restore_vlan_filters(bp);
4342         /* TODO restore other filters as well */
4343         return ret;
4344 }
4345
4346 static void bnxt_dev_recover(void *arg)
4347 {
4348         struct bnxt *bp = arg;
4349         int timeout = bp->fw_reset_max_msecs;
4350         int rc = 0;
4351
4352         /* Clear Error flag so that device re-init should happen */
4353         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4354
4355         do {
4356                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4357                 if (rc == 0)
4358                         break;
4359                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4360                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4361         } while (rc && timeout);
4362
4363         if (rc) {
4364                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4365                 goto err;
4366         }
4367
4368         rc = bnxt_init_resources(bp, true);
4369         if (rc) {
4370                 PMD_DRV_LOG(ERR,
4371                             "Failed to initialize resources after reset\n");
4372                 goto err;
4373         }
4374         /* clear reset flag as the device is initialized now */
4375         bp->flags &= ~BNXT_FLAG_FW_RESET;
4376
4377         rc = bnxt_dev_start_op(bp->eth_dev);
4378         if (rc) {
4379                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4380                 goto err_start;
4381         }
4382
4383         rc = bnxt_restore_filters(bp);
4384         if (rc)
4385                 goto err_start;
4386
4387         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4388         return;
4389 err_start:
4390         bnxt_dev_stop_op(bp->eth_dev);
4391 err:
4392         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4393         bnxt_uninit_resources(bp, false);
4394         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4395 }
4396
4397 void bnxt_dev_reset_and_resume(void *arg)
4398 {
4399         struct bnxt *bp = arg;
4400         int rc;
4401
4402         bnxt_dev_cleanup(bp);
4403
4404         bnxt_wait_for_device_shutdown(bp);
4405
4406         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4407                                bnxt_dev_recover, (void *)bp);
4408         if (rc)
4409                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4410 }
4411
4412 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4413 {
4414         struct bnxt_error_recovery_info *info = bp->recovery_info;
4415         uint32_t reg = info->status_regs[index];
4416         uint32_t type, offset, val = 0;
4417
4418         type = BNXT_FW_STATUS_REG_TYPE(reg);
4419         offset = BNXT_FW_STATUS_REG_OFF(reg);
4420
4421         switch (type) {
4422         case BNXT_FW_STATUS_REG_TYPE_CFG:
4423                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4424                 break;
4425         case BNXT_FW_STATUS_REG_TYPE_GRC:
4426                 offset = info->mapped_status_regs[index];
4427                 /* FALLTHROUGH */
4428         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4429                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4430                                        offset));
4431                 break;
4432         }
4433
4434         return val;
4435 }
4436
4437 static int bnxt_fw_reset_all(struct bnxt *bp)
4438 {
4439         struct bnxt_error_recovery_info *info = bp->recovery_info;
4440         uint32_t i;
4441         int rc = 0;
4442
4443         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4444                 /* Reset through master function driver */
4445                 for (i = 0; i < info->reg_array_cnt; i++)
4446                         bnxt_write_fw_reset_reg(bp, i);
4447                 /* Wait for time specified by FW after triggering reset */
4448                 rte_delay_ms(info->master_func_wait_period_after_reset);
4449         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4450                 /* Reset with the help of Kong processor */
4451                 rc = bnxt_hwrm_fw_reset(bp);
4452                 if (rc)
4453                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4454         }
4455
4456         return rc;
4457 }
4458
4459 static void bnxt_fw_reset_cb(void *arg)
4460 {
4461         struct bnxt *bp = arg;
4462         struct bnxt_error_recovery_info *info = bp->recovery_info;
4463         int rc = 0;
4464
4465         /* Only Master function can do FW reset */
4466         if (bnxt_is_master_func(bp) &&
4467             bnxt_is_recovery_enabled(bp)) {
4468                 rc = bnxt_fw_reset_all(bp);
4469                 if (rc) {
4470                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4471                         return;
4472                 }
4473         }
4474
4475         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4476          * EXCEPTION_FATAL_ASYNC event to all the functions
4477          * (including MASTER FUNC). After receiving this Async, all the active
4478          * drivers should treat this case as FW initiated recovery
4479          */
4480         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4481                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4482                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4483
4484                 /* To recover from error */
4485                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4486                                   (void *)bp);
4487         }
4488 }
4489
4490 /* Driver should poll FW heartbeat, reset_counter with the frequency
4491  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4492  * When the driver detects heartbeat stop or change in reset_counter,
4493  * it has to trigger a reset to recover from the error condition.
4494  * A “master PF” is the function who will have the privilege to
4495  * initiate the chimp reset. The master PF will be elected by the
4496  * firmware and will be notified through async message.
4497  */
4498 static void bnxt_check_fw_health(void *arg)
4499 {
4500         struct bnxt *bp = arg;
4501         struct bnxt_error_recovery_info *info = bp->recovery_info;
4502         uint32_t val = 0, wait_msec;
4503
4504         if (!info || !bnxt_is_recovery_enabled(bp) ||
4505             is_bnxt_in_error(bp))
4506                 return;
4507
4508         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4509         if (val == info->last_heart_beat)
4510                 goto reset;
4511
4512         info->last_heart_beat = val;
4513
4514         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4515         if (val != info->last_reset_counter)
4516                 goto reset;
4517
4518         info->last_reset_counter = val;
4519
4520         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4521                           bnxt_check_fw_health, (void *)bp);
4522
4523         return;
4524 reset:
4525         /* Stop DMA to/from device */
4526         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4527         bp->flags |= BNXT_FLAG_FW_RESET;
4528
4529         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4530
4531         if (bnxt_is_master_func(bp))
4532                 wait_msec = info->master_func_wait_period;
4533         else
4534                 wait_msec = info->normal_func_wait_period;
4535
4536         rte_eal_alarm_set(US_PER_MS * wait_msec,
4537                           bnxt_fw_reset_cb, (void *)bp);
4538 }
4539
4540 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4541 {
4542         uint32_t polling_freq;
4543
4544         if (!bnxt_is_recovery_enabled(bp))
4545                 return;
4546
4547         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4548                 return;
4549
4550         polling_freq = bp->recovery_info->driver_polling_freq;
4551
4552         rte_eal_alarm_set(US_PER_MS * polling_freq,
4553                           bnxt_check_fw_health, (void *)bp);
4554         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4555 }
4556
4557 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4558 {
4559         if (!bnxt_is_recovery_enabled(bp))
4560                 return;
4561
4562         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4563         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4564 }
4565
4566 static bool bnxt_vf_pciid(uint16_t device_id)
4567 {
4568         switch (device_id) {
4569         case BROADCOM_DEV_ID_57304_VF:
4570         case BROADCOM_DEV_ID_57406_VF:
4571         case BROADCOM_DEV_ID_5731X_VF:
4572         case BROADCOM_DEV_ID_5741X_VF:
4573         case BROADCOM_DEV_ID_57414_VF:
4574         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4575         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4576         case BROADCOM_DEV_ID_58802_VF:
4577         case BROADCOM_DEV_ID_57500_VF1:
4578         case BROADCOM_DEV_ID_57500_VF2:
4579                 /* FALLTHROUGH */
4580                 return true;
4581         default:
4582                 return false;
4583         }
4584 }
4585
4586 static bool bnxt_thor_device(uint16_t device_id)
4587 {
4588         switch (device_id) {
4589         case BROADCOM_DEV_ID_57508:
4590         case BROADCOM_DEV_ID_57504:
4591         case BROADCOM_DEV_ID_57502:
4592         case BROADCOM_DEV_ID_57508_MF1:
4593         case BROADCOM_DEV_ID_57504_MF1:
4594         case BROADCOM_DEV_ID_57502_MF1:
4595         case BROADCOM_DEV_ID_57508_MF2:
4596         case BROADCOM_DEV_ID_57504_MF2:
4597         case BROADCOM_DEV_ID_57502_MF2:
4598         case BROADCOM_DEV_ID_57500_VF1:
4599         case BROADCOM_DEV_ID_57500_VF2:
4600                 /* FALLTHROUGH */
4601                 return true;
4602         default:
4603                 return false;
4604         }
4605 }
4606
4607 bool bnxt_stratus_device(struct bnxt *bp)
4608 {
4609         uint16_t device_id = bp->pdev->id.device_id;
4610
4611         switch (device_id) {
4612         case BROADCOM_DEV_ID_STRATUS_NIC:
4613         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4614         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4615                 /* FALLTHROUGH */
4616                 return true;
4617         default:
4618                 return false;
4619         }
4620 }
4621
4622 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4623 {
4624         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4625         struct bnxt *bp = eth_dev->data->dev_private;
4626
4627         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4628         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4629         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4630         if (!bp->bar0 || !bp->doorbell_base) {
4631                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4632                 return -ENODEV;
4633         }
4634
4635         bp->eth_dev = eth_dev;
4636         bp->pdev = pci_dev;
4637
4638         return 0;
4639 }
4640
4641 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4642                                   struct bnxt_ctx_pg_info *ctx_pg,
4643                                   uint32_t mem_size,
4644                                   const char *suffix,
4645                                   uint16_t idx)
4646 {
4647         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4648         const struct rte_memzone *mz = NULL;
4649         char mz_name[RTE_MEMZONE_NAMESIZE];
4650         rte_iova_t mz_phys_addr;
4651         uint64_t valid_bits = 0;
4652         uint32_t sz;
4653         int i;
4654
4655         if (!mem_size)
4656                 return 0;
4657
4658         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4659                          BNXT_PAGE_SIZE;
4660         rmem->page_size = BNXT_PAGE_SIZE;
4661         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4662         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4663         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4664
4665         valid_bits = PTU_PTE_VALID;
4666
4667         if (rmem->nr_pages > 1) {
4668                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4669                          "bnxt_ctx_pg_tbl%s_%x_%d",
4670                          suffix, idx, bp->eth_dev->data->port_id);
4671                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4672                 mz = rte_memzone_lookup(mz_name);
4673                 if (!mz) {
4674                         mz = rte_memzone_reserve_aligned(mz_name,
4675                                                 rmem->nr_pages * 8,
4676                                                 SOCKET_ID_ANY,
4677                                                 RTE_MEMZONE_2MB |
4678                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4679                                                 RTE_MEMZONE_IOVA_CONTIG,
4680                                                 BNXT_PAGE_SIZE);
4681                         if (mz == NULL)
4682                                 return -ENOMEM;
4683                 }
4684
4685                 memset(mz->addr, 0, mz->len);
4686                 mz_phys_addr = mz->iova;
4687
4688                 rmem->pg_tbl = mz->addr;
4689                 rmem->pg_tbl_map = mz_phys_addr;
4690                 rmem->pg_tbl_mz = mz;
4691         }
4692
4693         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4694                  suffix, idx, bp->eth_dev->data->port_id);
4695         mz = rte_memzone_lookup(mz_name);
4696         if (!mz) {
4697                 mz = rte_memzone_reserve_aligned(mz_name,
4698                                                  mem_size,
4699                                                  SOCKET_ID_ANY,
4700                                                  RTE_MEMZONE_1GB |
4701                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4702                                                  RTE_MEMZONE_IOVA_CONTIG,
4703                                                  BNXT_PAGE_SIZE);
4704                 if (mz == NULL)
4705                         return -ENOMEM;
4706         }
4707
4708         memset(mz->addr, 0, mz->len);
4709         mz_phys_addr = mz->iova;
4710
4711         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4712                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4713                 rmem->dma_arr[i] = mz_phys_addr + sz;
4714
4715                 if (rmem->nr_pages > 1) {
4716                         if (i == rmem->nr_pages - 2 &&
4717                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4718                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4719                         else if (i == rmem->nr_pages - 1 &&
4720                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4721                                 valid_bits |= PTU_PTE_LAST;
4722
4723                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4724                                                            valid_bits);
4725                 }
4726         }
4727
4728         rmem->mz = mz;
4729         if (rmem->vmem_size)
4730                 rmem->vmem = (void **)mz->addr;
4731         rmem->dma_arr[0] = mz_phys_addr;
4732         return 0;
4733 }
4734
4735 static void bnxt_free_ctx_mem(struct bnxt *bp)
4736 {
4737         int i;
4738
4739         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4740                 return;
4741
4742         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4743         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4744         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4745         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4746         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4747         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4748         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4749         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4750         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4751         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4752         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4753
4754         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4755                 if (bp->ctx->tqm_mem[i])
4756                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4757         }
4758
4759         rte_free(bp->ctx);
4760         bp->ctx = NULL;
4761 }
4762
4763 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4764
4765 #define min_t(type, x, y) ({                    \
4766         type __min1 = (x);                      \
4767         type __min2 = (y);                      \
4768         __min1 < __min2 ? __min1 : __min2; })
4769
4770 #define max_t(type, x, y) ({                    \
4771         type __max1 = (x);                      \
4772         type __max2 = (y);                      \
4773         __max1 > __max2 ? __max1 : __max2; })
4774
4775 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4776
4777 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4778 {
4779         struct bnxt_ctx_pg_info *ctx_pg;
4780         struct bnxt_ctx_mem_info *ctx;
4781         uint32_t mem_size, ena, entries;
4782         uint32_t entries_sp, min;
4783         int i, rc;
4784
4785         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4786         if (rc) {
4787                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4788                 return rc;
4789         }
4790         ctx = bp->ctx;
4791         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4792                 return 0;
4793
4794         ctx_pg = &ctx->qp_mem;
4795         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4796         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4797         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4798         if (rc)
4799                 return rc;
4800
4801         ctx_pg = &ctx->srq_mem;
4802         ctx_pg->entries = ctx->srq_max_l2_entries;
4803         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4804         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4805         if (rc)
4806                 return rc;
4807
4808         ctx_pg = &ctx->cq_mem;
4809         ctx_pg->entries = ctx->cq_max_l2_entries;
4810         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4811         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4812         if (rc)
4813                 return rc;
4814
4815         ctx_pg = &ctx->vnic_mem;
4816         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4817                 ctx->vnic_max_ring_table_entries;
4818         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4819         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4820         if (rc)
4821                 return rc;
4822
4823         ctx_pg = &ctx->stat_mem;
4824         ctx_pg->entries = ctx->stat_max_entries;
4825         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4826         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4827         if (rc)
4828                 return rc;
4829
4830         min = ctx->tqm_min_entries_per_ring;
4831
4832         entries_sp = ctx->qp_max_l2_entries +
4833                      ctx->vnic_max_vnic_entries +
4834                      2 * ctx->qp_min_qp1_entries + min;
4835         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4836
4837         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4838         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4839         entries = clamp_t(uint32_t, entries, min,
4840                           ctx->tqm_max_entries_per_ring);
4841         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4842                 ctx_pg = ctx->tqm_mem[i];
4843                 ctx_pg->entries = i ? entries : entries_sp;
4844                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4845                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4846                 if (rc)
4847                         return rc;
4848                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4849         }
4850
4851         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4852         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4853         if (rc)
4854                 PMD_DRV_LOG(ERR,
4855                             "Failed to configure context mem: rc = %d\n", rc);
4856         else
4857                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4858
4859         return rc;
4860 }
4861
4862 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4863 {
4864         struct rte_pci_device *pci_dev = bp->pdev;
4865         char mz_name[RTE_MEMZONE_NAMESIZE];
4866         const struct rte_memzone *mz = NULL;
4867         uint32_t total_alloc_len;
4868         rte_iova_t mz_phys_addr;
4869
4870         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4871                 return 0;
4872
4873         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4874                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4875                  pci_dev->addr.bus, pci_dev->addr.devid,
4876                  pci_dev->addr.function, "rx_port_stats");
4877         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4878         mz = rte_memzone_lookup(mz_name);
4879         total_alloc_len =
4880                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4881                                        sizeof(struct rx_port_stats_ext) + 512);
4882         if (!mz) {
4883                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4884                                          SOCKET_ID_ANY,
4885                                          RTE_MEMZONE_2MB |
4886                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4887                                          RTE_MEMZONE_IOVA_CONTIG);
4888                 if (mz == NULL)
4889                         return -ENOMEM;
4890         }
4891         memset(mz->addr, 0, mz->len);
4892         mz_phys_addr = mz->iova;
4893
4894         bp->rx_mem_zone = (const void *)mz;
4895         bp->hw_rx_port_stats = mz->addr;
4896         bp->hw_rx_port_stats_map = mz_phys_addr;
4897
4898         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4899                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4900                  pci_dev->addr.bus, pci_dev->addr.devid,
4901                  pci_dev->addr.function, "tx_port_stats");
4902         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4903         mz = rte_memzone_lookup(mz_name);
4904         total_alloc_len =
4905                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4906                                        sizeof(struct tx_port_stats_ext) + 512);
4907         if (!mz) {
4908                 mz = rte_memzone_reserve(mz_name,
4909                                          total_alloc_len,
4910                                          SOCKET_ID_ANY,
4911                                          RTE_MEMZONE_2MB |
4912                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4913                                          RTE_MEMZONE_IOVA_CONTIG);
4914                 if (mz == NULL)
4915                         return -ENOMEM;
4916         }
4917         memset(mz->addr, 0, mz->len);
4918         mz_phys_addr = mz->iova;
4919
4920         bp->tx_mem_zone = (const void *)mz;
4921         bp->hw_tx_port_stats = mz->addr;
4922         bp->hw_tx_port_stats_map = mz_phys_addr;
4923         bp->flags |= BNXT_FLAG_PORT_STATS;
4924
4925         /* Display extended statistics if FW supports it */
4926         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4927             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4928             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4929                 return 0;
4930
4931         bp->hw_rx_port_stats_ext = (void *)
4932                 ((uint8_t *)bp->hw_rx_port_stats +
4933                  sizeof(struct rx_port_stats));
4934         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4935                 sizeof(struct rx_port_stats);
4936         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4937
4938         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4939             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4940                 bp->hw_tx_port_stats_ext = (void *)
4941                         ((uint8_t *)bp->hw_tx_port_stats +
4942                          sizeof(struct tx_port_stats));
4943                 bp->hw_tx_port_stats_ext_map =
4944                         bp->hw_tx_port_stats_map +
4945                         sizeof(struct tx_port_stats);
4946                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4947         }
4948
4949         return 0;
4950 }
4951
4952 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4953 {
4954         struct bnxt *bp = eth_dev->data->dev_private;
4955         int rc = 0;
4956
4957         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4958                                                RTE_ETHER_ADDR_LEN *
4959                                                bp->max_l2_ctx,
4960                                                0);
4961         if (eth_dev->data->mac_addrs == NULL) {
4962                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4963                 return -ENOMEM;
4964         }
4965
4966         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4967                 if (BNXT_PF(bp))
4968                         return -EINVAL;
4969
4970                 /* Generate a random MAC address, if none was assigned by PF */
4971                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4972                 bnxt_eth_hw_addr_random(bp->mac_addr);
4973                 PMD_DRV_LOG(INFO,
4974                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4975                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4976                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4977
4978                 rc = bnxt_hwrm_set_mac(bp);
4979                 if (!rc)
4980                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4981                                RTE_ETHER_ADDR_LEN);
4982                 return rc;
4983         }
4984
4985         /* Copy the permanent MAC from the FUNC_QCAPS response */
4986         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4987         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4988
4989         return rc;
4990 }
4991
4992 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4993 {
4994         int rc = 0;
4995
4996         /* MAC is already configured in FW */
4997         if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4998                 return 0;
4999
5000         /* Restore the old MAC configured */
5001         rc = bnxt_hwrm_set_mac(bp);
5002         if (rc)
5003                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5004
5005         return rc;
5006 }
5007
5008 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5009 {
5010         if (!BNXT_PF(bp))
5011                 return;
5012
5013 #define ALLOW_FUNC(x)   \
5014         { \
5015                 uint32_t arg = (x); \
5016                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
5017                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
5018         }
5019
5020         /* Forward all requests if firmware is new enough */
5021         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
5022              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
5023             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
5024                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
5025         } else {
5026                 PMD_DRV_LOG(WARNING,
5027                             "Firmware too old for VF mailbox functionality\n");
5028                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
5029         }
5030
5031         /*
5032          * The following are used for driver cleanup. If we disallow these,
5033          * VF drivers can't clean up cleanly.
5034          */
5035         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
5036         ALLOW_FUNC(HWRM_VNIC_FREE);
5037         ALLOW_FUNC(HWRM_RING_FREE);
5038         ALLOW_FUNC(HWRM_RING_GRP_FREE);
5039         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
5040         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
5041         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
5042         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
5043         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
5044 }
5045
5046 uint16_t
5047 bnxt_get_svif(uint16_t port_id, bool func_svif)
5048 {
5049         struct rte_eth_dev *eth_dev;
5050         struct bnxt *bp;
5051
5052         eth_dev = &rte_eth_devices[port_id];
5053         bp = eth_dev->data->dev_private;
5054
5055         return func_svif ? bp->func_svif : bp->port_svif;
5056 }
5057
5058 uint16_t
5059 bnxt_get_vnic_id(uint16_t port)
5060 {
5061         struct rte_eth_dev *eth_dev;
5062         struct bnxt_vnic_info *vnic;
5063         struct bnxt *bp;
5064
5065         eth_dev = &rte_eth_devices[port];
5066         bp = eth_dev->data->dev_private;
5067
5068         vnic = BNXT_GET_DEFAULT_VNIC(bp);
5069
5070         return vnic->fw_vnic_id;
5071 }
5072
5073 uint16_t
5074 bnxt_get_fw_func_id(uint16_t port)
5075 {
5076         struct rte_eth_dev *eth_dev;
5077         struct bnxt *bp;
5078
5079         eth_dev = &rte_eth_devices[port];
5080         bp = eth_dev->data->dev_private;
5081
5082         return bp->fw_fid;
5083 }
5084
5085 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5086 {
5087         struct bnxt_error_recovery_info *info = bp->recovery_info;
5088
5089         if (info) {
5090                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5091                         memset(info, 0, sizeof(*info));
5092                 return;
5093         }
5094
5095         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5096                 return;
5097
5098         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5099                            sizeof(*info), 0);
5100         if (!info)
5101                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5102
5103         bp->recovery_info = info;
5104 }
5105
5106 static void bnxt_check_fw_status(struct bnxt *bp)
5107 {
5108         uint32_t fw_status;
5109
5110         if (!(bp->recovery_info &&
5111               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5112                 return;
5113
5114         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5115         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5116                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5117                             fw_status);
5118 }
5119
5120 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5121 {
5122         struct bnxt_error_recovery_info *info = bp->recovery_info;
5123         uint32_t status_loc;
5124         uint32_t sig_ver;
5125
5126         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5127                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5128         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5129                                    BNXT_GRCP_WINDOW_2_BASE +
5130                                    offsetof(struct hcomm_status,
5131                                             sig_ver)));
5132         /* If the signature is absent, then FW does not support this feature */
5133         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5134             HCOMM_STATUS_SIGNATURE_VAL)
5135                 return 0;
5136
5137         if (!info) {
5138                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5139                                    sizeof(*info), 0);
5140                 if (!info)
5141                         return -ENOMEM;
5142                 bp->recovery_info = info;
5143         } else {
5144                 memset(info, 0, sizeof(*info));
5145         }
5146
5147         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5148                                       BNXT_GRCP_WINDOW_2_BASE +
5149                                       offsetof(struct hcomm_status,
5150                                                fw_status_loc)));
5151
5152         /* Only pre-map the FW health status GRC register */
5153         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5154                 return 0;
5155
5156         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5157         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5158                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5159
5160         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5161                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5162
5163         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5164
5165         return 0;
5166 }
5167
5168 static int bnxt_init_fw(struct bnxt *bp)
5169 {
5170         uint16_t mtu;
5171         int rc = 0;
5172
5173         bp->fw_cap = 0;
5174
5175         rc = bnxt_map_hcomm_fw_status_reg(bp);
5176         if (rc)
5177                 return rc;
5178
5179         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5180         if (rc) {
5181                 bnxt_check_fw_status(bp);
5182                 return rc;
5183         }
5184
5185         rc = bnxt_hwrm_func_reset(bp);
5186         if (rc)
5187                 return -EIO;
5188
5189         rc = bnxt_hwrm_vnic_qcaps(bp);
5190         if (rc)
5191                 return rc;
5192
5193         rc = bnxt_hwrm_queue_qportcfg(bp);
5194         if (rc)
5195                 return rc;
5196
5197         /* Get the MAX capabilities for this function.
5198          * This function also allocates context memory for TQM rings and
5199          * informs the firmware about this allocated backing store memory.
5200          */
5201         rc = bnxt_hwrm_func_qcaps(bp);
5202         if (rc)
5203                 return rc;
5204
5205         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5206         if (rc)
5207                 return rc;
5208
5209         bnxt_hwrm_port_mac_qcfg(bp);
5210
5211         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5212         if (rc)
5213                 return rc;
5214
5215         bnxt_alloc_error_recovery_info(bp);
5216         /* Get the adapter error recovery support info */
5217         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5218         if (rc)
5219                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5220
5221         bnxt_hwrm_port_led_qcaps(bp);
5222
5223         return 0;
5224 }
5225
5226 static int
5227 bnxt_init_locks(struct bnxt *bp)
5228 {
5229         int err;
5230
5231         err = pthread_mutex_init(&bp->flow_lock, NULL);
5232         if (err) {
5233                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5234                 return err;
5235         }
5236
5237         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5238         if (err)
5239                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5240         return err;
5241 }
5242
5243 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5244 {
5245         int rc;
5246
5247         rc = bnxt_init_fw(bp);
5248         if (rc)
5249                 return rc;
5250
5251         if (!reconfig_dev) {
5252                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5253                 if (rc)
5254                         return rc;
5255         } else {
5256                 rc = bnxt_restore_dflt_mac(bp);
5257                 if (rc)
5258                         return rc;
5259         }
5260
5261         bnxt_config_vf_req_fwd(bp);
5262
5263         rc = bnxt_hwrm_func_driver_register(bp);
5264         if (rc) {
5265                 PMD_DRV_LOG(ERR, "Failed to register driver");
5266                 return -EBUSY;
5267         }
5268
5269         if (BNXT_PF(bp)) {
5270                 if (bp->pdev->max_vfs) {
5271                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5272                         if (rc) {
5273                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5274                                 return rc;
5275                         }
5276                 } else {
5277                         rc = bnxt_hwrm_allocate_pf_only(bp);
5278                         if (rc) {
5279                                 PMD_DRV_LOG(ERR,
5280                                             "Failed to allocate PF resources");
5281                                 return rc;
5282                         }
5283                 }
5284         }
5285
5286         rc = bnxt_alloc_mem(bp, reconfig_dev);
5287         if (rc)
5288                 return rc;
5289
5290         rc = bnxt_setup_int(bp);
5291         if (rc)
5292                 return rc;
5293
5294         rc = bnxt_request_int(bp);
5295         if (rc)
5296                 return rc;
5297
5298         rc = bnxt_init_ctx_mem(bp);
5299         if (rc) {
5300                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5301                 return rc;
5302         }
5303
5304         rc = bnxt_init_locks(bp);
5305         if (rc)
5306                 return rc;
5307
5308         return 0;
5309 }
5310
5311 static int
5312 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5313                           const char *value, void *opaque_arg)
5314 {
5315         struct bnxt *bp = opaque_arg;
5316         unsigned long truflow;
5317         char *end = NULL;
5318
5319         if (!value || !opaque_arg) {
5320                 PMD_DRV_LOG(ERR,
5321                             "Invalid parameter passed to truflow devargs.\n");
5322                 return -EINVAL;
5323         }
5324
5325         truflow = strtoul(value, &end, 10);
5326         if (end == NULL || *end != '\0' ||
5327             (truflow == ULONG_MAX && errno == ERANGE)) {
5328                 PMD_DRV_LOG(ERR,
5329                             "Invalid parameter passed to truflow devargs.\n");
5330                 return -EINVAL;
5331         }
5332
5333         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5334                 PMD_DRV_LOG(ERR,
5335                             "Invalid value passed to truflow devargs.\n");
5336                 return -EINVAL;
5337         }
5338
5339         bp->truflow = truflow;
5340         if (bp->truflow)
5341                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5342
5343         return 0;
5344 }
5345
5346 static int
5347 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5348                              const char *value, void *opaque_arg)
5349 {
5350         struct bnxt *bp = opaque_arg;
5351         unsigned long flow_xstat;
5352         char *end = NULL;
5353
5354         if (!value || !opaque_arg) {
5355                 PMD_DRV_LOG(ERR,
5356                             "Invalid parameter passed to flow_xstat devarg.\n");
5357                 return -EINVAL;
5358         }
5359
5360         flow_xstat = strtoul(value, &end, 10);
5361         if (end == NULL || *end != '\0' ||
5362             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5363                 PMD_DRV_LOG(ERR,
5364                             "Invalid parameter passed to flow_xstat devarg.\n");
5365                 return -EINVAL;
5366         }
5367
5368         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5369                 PMD_DRV_LOG(ERR,
5370                             "Invalid value passed to flow_xstat devarg.\n");
5371                 return -EINVAL;
5372         }
5373
5374         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5375         if (BNXT_FLOW_XSTATS_EN(bp))
5376                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5377
5378         return 0;
5379 }
5380
5381 static void
5382 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5383 {
5384         struct rte_kvargs *kvlist;
5385
5386         if (devargs == NULL)
5387                 return;
5388
5389         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5390         if (kvlist == NULL)
5391                 return;
5392
5393         /*
5394          * Handler for "truflow" devarg.
5395          * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1”
5396          */
5397         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5398                            bnxt_parse_devarg_truflow, bp);
5399
5400         /*
5401          * Handler for "flow_xstat" devarg.
5402          * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1”
5403          */
5404         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5405                            bnxt_parse_devarg_flow_xstat, bp);
5406
5407         rte_kvargs_free(kvlist);
5408 }
5409
5410 static int
5411 bnxt_dev_init(struct rte_eth_dev *eth_dev)
5412 {
5413         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5414         static int version_printed;
5415         struct bnxt *bp;
5416         int rc;
5417
5418         if (version_printed++ == 0)
5419                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5420
5421         eth_dev->dev_ops = &bnxt_dev_ops;
5422         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5423         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5424
5425         /*
5426          * For secondary processes, we don't initialise any further
5427          * as primary has already done this work.
5428          */
5429         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5430                 return 0;
5431
5432         rte_eth_copy_pci_info(eth_dev, pci_dev);
5433
5434         bp = eth_dev->data->dev_private;
5435
5436         /* Parse dev arguments passed on when starting the DPDK application. */
5437         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5438
5439         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5440
5441         if (bnxt_vf_pciid(pci_dev->id.device_id))
5442                 bp->flags |= BNXT_FLAG_VF;
5443
5444         if (bnxt_thor_device(pci_dev->id.device_id))
5445                 bp->flags |= BNXT_FLAG_THOR_CHIP;
5446
5447         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5448             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5449             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5450             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5451                 bp->flags |= BNXT_FLAG_STINGRAY;
5452
5453         rc = bnxt_init_board(eth_dev);
5454         if (rc) {
5455                 PMD_DRV_LOG(ERR,
5456                             "Failed to initialize board rc: %x\n", rc);
5457                 return rc;
5458         }
5459
5460         rc = bnxt_alloc_link_info(bp);
5461         if (rc)
5462                 goto error_free;
5463
5464         rc = bnxt_alloc_hwrm_resources(bp);
5465         if (rc) {
5466                 PMD_DRV_LOG(ERR,
5467                             "Failed to allocate hwrm resource rc: %x\n", rc);
5468                 goto error_free;
5469         }
5470         rc = bnxt_alloc_leds_info(bp);
5471         if (rc)
5472                 goto error_free;
5473
5474         rc = bnxt_alloc_cos_queues(bp);
5475         if (rc)
5476                 goto error_free;
5477
5478         rc = bnxt_init_resources(bp, false);
5479         if (rc)
5480                 goto error_free;
5481
5482         rc = bnxt_alloc_stats_mem(bp);
5483         if (rc)
5484                 goto error_free;
5485
5486         /* Pass the information to the rte_eth_dev_close() that it should also
5487          * release the private port resources.
5488          */
5489         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5490
5491         PMD_DRV_LOG(INFO,
5492                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5493                     pci_dev->mem_resource[0].phys_addr,
5494                     pci_dev->mem_resource[0].addr);
5495
5496         return 0;
5497
5498 error_free:
5499         bnxt_dev_uninit(eth_dev);
5500         return rc;
5501 }
5502
5503
5504 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5505 {
5506         if (!ctx)
5507                 return;
5508
5509         if (ctx->va)
5510                 rte_free(ctx->va);
5511
5512         ctx->va = NULL;
5513         ctx->dma = RTE_BAD_IOVA;
5514         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5515 }
5516
5517 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5518 {
5519         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5520                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5521                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
5522                                   bp->flow_stat->max_fc,
5523                                   false);
5524
5525         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5526                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5527                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
5528                                   bp->flow_stat->max_fc,
5529                                   false);
5530
5531         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5532                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5533         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5534
5535         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5536                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5537         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5538
5539         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5540                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5541         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5542
5543         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5544                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5545         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5546 }
5547
5548 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5549 {
5550         bnxt_unregister_fc_ctx_mem(bp);
5551
5552         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5553         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5554         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5555         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5556 }
5557
5558 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5559 {
5560         if (BNXT_FLOW_XSTATS_EN(bp))
5561                 bnxt_uninit_fc_ctx_mem(bp);
5562 }
5563
5564 static void
5565 bnxt_free_error_recovery_info(struct bnxt *bp)
5566 {
5567         rte_free(bp->recovery_info);
5568         bp->recovery_info = NULL;
5569         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5570 }
5571
5572 static void
5573 bnxt_uninit_locks(struct bnxt *bp)
5574 {
5575         pthread_mutex_destroy(&bp->flow_lock);
5576         pthread_mutex_destroy(&bp->def_cp_lock);
5577 }
5578
5579 static int
5580 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5581 {
5582         int rc;
5583
5584         bnxt_free_int(bp);
5585         bnxt_free_mem(bp, reconfig_dev);
5586         bnxt_hwrm_func_buf_unrgtr(bp);
5587         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5588         bp->flags &= ~BNXT_FLAG_REGISTERED;
5589         bnxt_free_ctx_mem(bp);
5590         if (!reconfig_dev) {
5591                 bnxt_free_hwrm_resources(bp);
5592                 bnxt_free_error_recovery_info(bp);
5593         }
5594
5595         bnxt_uninit_ctx_mem(bp);
5596
5597         bnxt_uninit_locks(bp);
5598         rte_free(bp->ptp_cfg);
5599         bp->ptp_cfg = NULL;
5600         return rc;
5601 }
5602
5603 static int
5604 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5605 {
5606         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5607                 return -EPERM;
5608
5609         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5610
5611         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5612                 bnxt_dev_close_op(eth_dev);
5613
5614         return 0;
5615 }
5616
5617 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5618         struct rte_pci_device *pci_dev)
5619 {
5620         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
5621                 bnxt_dev_init);
5622 }
5623
5624 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5625 {
5626         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
5627                 return rte_eth_dev_pci_generic_remove(pci_dev,
5628                                 bnxt_dev_uninit);
5629         else
5630                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5631 }
5632
5633 static struct rte_pci_driver bnxt_rte_pmd = {
5634         .id_table = bnxt_pci_id_map,
5635         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5636         .probe = bnxt_pci_probe,
5637         .remove = bnxt_pci_remove,
5638 };
5639
5640 static bool
5641 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5642 {
5643         if (strcmp(dev->device->driver->name, drv->driver.name))
5644                 return false;
5645
5646         return true;
5647 }
5648
5649 bool is_bnxt_supported(struct rte_eth_dev *dev)
5650 {
5651         return is_device_supported(dev, &bnxt_rte_pmd);
5652 }
5653
5654 RTE_INIT(bnxt_init_log)
5655 {
5656         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
5657         if (bnxt_logtype_driver >= 0)
5658                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
5659 }
5660
5661 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5662 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5663 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");