drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_irq.h"
  20 #include "bnxt_ring.h"
  21 #include "bnxt_rxq.h"
  22 #include "bnxt_rxr.h"
  23 #include "bnxt_stats.h"
  24 #include "bnxt_txq.h"
  25 #include "bnxt_txr.h"
  26 #include "bnxt_vnic.h"
  27 #include "hsi_struct_def_dpdk.h"
  28 #include "bnxt_nvm_defs.h"
  29
  30 #define DRV_MODULE_NAME         "bnxt"
  31 static const char bnxt_version[] =
  32         "Broadcom Cumulus driver " DRV_MODULE_NAME "\n";
  33 int bnxt_logtype_driver;
  34
  35 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  36
  37 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  39 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
  40 #define BROADCOM_DEV_ID_57414_VF 0x16c1
  41 #define BROADCOM_DEV_ID_57301 0x16c8
  42 #define BROADCOM_DEV_ID_57302 0x16c9
  43 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  44 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  45 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  46 #define BROADCOM_DEV_ID_NS2 0x16cd
  47 #define BROADCOM_DEV_ID_57311 0x16ce
  48 #define BROADCOM_DEV_ID_57312 0x16cf
  49 #define BROADCOM_DEV_ID_57402 0x16d0
  50 #define BROADCOM_DEV_ID_57404 0x16d1
  51 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  52 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  53 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  54 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  55 #define BROADCOM_DEV_ID_57412 0x16d6
  56 #define BROADCOM_DEV_ID_57414 0x16d7
  57 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  58 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  59 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  60 #define BROADCOM_DEV_ID_57412_MF 0x16de
  61 #define BROADCOM_DEV_ID_57314 0x16df
  62 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  63 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  64 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  65 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  66 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  67 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  68 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  69 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  70 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  71 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  72 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  73 #define BROADCOM_DEV_ID_58802 0xd802
  74 #define BROADCOM_DEV_ID_58804 0xd804
  75 #define BROADCOM_DEV_ID_58808 0x16f0
  76
  77 static const struct rte_pci_id bnxt_pci_id_map[] = {
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  79                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  81                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
 119         { .vendor_id = 0, /* sentinel */ },
 120 };
 121
 122 #define BNXT_ETH_RSS_SUPPORT (  \
 123         ETH_RSS_IPV4 |          \
 124         ETH_RSS_NONFRAG_IPV4_TCP |      \
 125         ETH_RSS_NONFRAG_IPV4_UDP |      \
 126         ETH_RSS_IPV6 |          \
 127         ETH_RSS_NONFRAG_IPV6_TCP |      \
 128         ETH_RSS_NONFRAG_IPV6_UDP)
 129
 130 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 131                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 132                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 133                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 134                                      DEV_TX_OFFLOAD_TCP_TSO | \
 135                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 136                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 137                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 138                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 139                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 140                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 141
 142 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 143                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 144                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 145                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 146                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 147                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 148                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 149                                      DEV_RX_OFFLOAD_CRC_STRIP | \
 150                                      DEV_RX_OFFLOAD_TCP_LRO)
 151
 152 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 153 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 154
 155 /***********************/
 156
 157 /*
 158  * High level utility functions
 159  */
 160
 161 static void bnxt_free_mem(struct bnxt *bp)
 162 {
 163         bnxt_free_filter_mem(bp);
 164         bnxt_free_vnic_attributes(bp);
 165         bnxt_free_vnic_mem(bp);
 166
 167         bnxt_free_stats(bp);
 168         bnxt_free_tx_rings(bp);
 169         bnxt_free_rx_rings(bp);
 170         bnxt_free_def_cp_ring(bp);
 171 }
 172
 173 static int bnxt_alloc_mem(struct bnxt *bp)
 174 {
 175         int rc;
 176
 177         /* Default completion ring */
 178         rc = bnxt_init_def_ring_struct(bp, SOCKET_ID_ANY);
 179         if (rc)
 180                 goto alloc_mem_err;
 181
 182         rc = bnxt_alloc_rings(bp, 0, NULL, NULL,
 183                               bp->def_cp_ring, "def_cp");
 184         if (rc)
 185                 goto alloc_mem_err;
 186
 187         rc = bnxt_alloc_vnic_mem(bp);
 188         if (rc)
 189                 goto alloc_mem_err;
 190
 191         rc = bnxt_alloc_vnic_attributes(bp);
 192         if (rc)
 193                 goto alloc_mem_err;
 194
 195         rc = bnxt_alloc_filter_mem(bp);
 196         if (rc)
 197                 goto alloc_mem_err;
 198
 199         return 0;
 200
 201 alloc_mem_err:
 202         bnxt_free_mem(bp);
 203         return rc;
 204 }
 205
 206 static int bnxt_init_chip(struct bnxt *bp)
 207 {
 208         unsigned int i;
 209         struct rte_eth_link new;
 210         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 211         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 212         uint32_t intr_vector = 0;
 213         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 214         uint32_t vec = BNXT_MISC_VEC_ID;
 215         int rc;
 216
 217         /* disable uio/vfio intr/eventfd mapping */
 218         rte_intr_disable(intr_handle);
 219
 220         if (bp->eth_dev->data->mtu > ETHER_MTU) {
 221                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 222                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 223                 bp->flags |= BNXT_FLAG_JUMBO;
 224         } else {
 225                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 226                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 227                 bp->flags &= ~BNXT_FLAG_JUMBO;
 228         }
 229
 230         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 231         if (rc) {
 232                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 233                 goto err_out;
 234         }
 235
 236         rc = bnxt_alloc_hwrm_rings(bp);
 237         if (rc) {
 238                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 239                 goto err_out;
 240         }
 241
 242         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 243         if (rc) {
 244                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 245                 goto err_out;
 246         }
 247
 248         rc = bnxt_mq_rx_configure(bp);
 249         if (rc) {
 250                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 251                 goto err_out;
 252         }
 253
 254         /* VNIC configuration */
 255         for (i = 0; i < bp->nr_vnics; i++) {
 256                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 257
 258                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 259                 if (rc) {
 260                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 261                                 i, rc);
 262                         goto err_out;
 263                 }
 264
 265                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
 266                 if (rc) {
 267                         PMD_DRV_LOG(ERR,
 268                                 "HWRM vnic %d ctx alloc failure rc: %x\n",
 269                                 i, rc);
 270                         goto err_out;
 271                 }
 272
 273                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 274                 if (rc) {
 275                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 276                                 i, rc);
 277                         goto err_out;
 278                 }
 279
 280                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 281                 if (rc) {
 282                         PMD_DRV_LOG(ERR,
 283                                 "HWRM vnic %d filter failure rc: %x\n",
 284                                 i, rc);
 285                         goto err_out;
 286                 }
 287
 288                 rc = bnxt_vnic_rss_configure(bp, vnic);
 289                 if (rc) {
 290                         PMD_DRV_LOG(ERR,
 291                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 292                         goto err_out;
 293                 }
 294
 295                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 296
 297                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 298                     DEV_RX_OFFLOAD_TCP_LRO)
 299                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 300                 else
 301                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 302         }
 303         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 304         if (rc) {
 305                 PMD_DRV_LOG(ERR,
 306                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 307                 goto err_out;
 308         }
 309
 310         /* check and configure queue intr-vector mapping */
 311         if ((rte_intr_cap_multiple(intr_handle) ||
 312              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 313             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 314                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 315                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 316                 if (intr_vector > bp->rx_cp_nr_rings) {
 317                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 318                                         bp->rx_cp_nr_rings);
 319                         return -ENOTSUP;
 320                 }
 321                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 322                         return -1;
 323         }
 324
 325         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 326                 intr_handle->intr_vec =
 327                         rte_zmalloc("intr_vec",
 328                                     bp->eth_dev->data->nb_rx_queues *
 329                                     sizeof(int), 0);
 330                 if (intr_handle->intr_vec == NULL) {
 331                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 332                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 333                         return -ENOMEM;
 334                 }
 335                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 336                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 337                          intr_handle->intr_vec, intr_handle->nb_efd,
 338                         intr_handle->max_intr);
 339         }
 340
 341         for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 342              queue_id++) {
 343                 intr_handle->intr_vec[queue_id] = vec;
 344                 if (vec < base + intr_handle->nb_efd - 1)
 345                         vec++;
 346         }
 347
 348         /* enable uio/vfio intr/eventfd mapping */
 349         rte_intr_enable(intr_handle);
 350
 351         rc = bnxt_get_hwrm_link_config(bp, &new);
 352         if (rc) {
 353                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 354                 goto err_out;
 355         }
 356
 357         if (!bp->link_info.link_up) {
 358                 rc = bnxt_set_hwrm_link_config(bp, true);
 359                 if (rc) {
 360                         PMD_DRV_LOG(ERR,
 361                                 "HWRM link config failure rc: %x\n", rc);
 362                         goto err_out;
 363                 }
 364         }
 365         bnxt_print_link_info(bp->eth_dev);
 366
 367         return 0;
 368
 369 err_out:
 370         bnxt_free_all_hwrm_resources(bp);
 371
 372         /* Some of the error status returned by FW may not be from errno.h */
 373         if (rc > 0)
 374                 rc = -EIO;
 375
 376         return rc;
 377 }
 378
 379 static int bnxt_shutdown_nic(struct bnxt *bp)
 380 {
 381         bnxt_free_all_hwrm_resources(bp);
 382         bnxt_free_all_filters(bp);
 383         bnxt_free_all_vnics(bp);
 384         return 0;
 385 }
 386
 387 static int bnxt_init_nic(struct bnxt *bp)
 388 {
 389         int rc;
 390
 391         rc = bnxt_init_ring_grps(bp);
 392         if (rc)
 393                 return rc;
 394
 395         bnxt_init_vnics(bp);
 396         bnxt_init_filters(bp);
 397
 398         return 0;
 399 }
 400
 401 /*
 402  * Device configuration and status function
 403  */
 404
 405 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 406                                   struct rte_eth_dev_info *dev_info)
 407 {
 408         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 409         uint16_t max_vnics, i, j, vpool, vrxq;
 410         unsigned int max_rx_rings;
 411
 412         /* MAC Specifics */
 413         dev_info->max_mac_addrs = bp->max_l2_ctx;
 414         dev_info->max_hash_mac_addrs = 0;
 415
 416         /* PF/VF specifics */
 417         if (BNXT_PF(bp))
 418                 dev_info->max_vfs = bp->pdev->max_vfs;
 419         max_rx_rings = RTE_MIN(bp->max_vnics, RTE_MIN(bp->max_l2_ctx,
 420                                                 RTE_MIN(bp->max_rsscos_ctx,
 421                                                 bp->max_stat_ctx)));
 422         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 423         dev_info->max_rx_queues = max_rx_rings;
 424         dev_info->max_tx_queues = max_rx_rings;
 425         dev_info->reta_size = bp->max_rsscos_ctx;
 426         dev_info->hash_key_size = 40;
 427         max_vnics = bp->max_vnics;
 428
 429         /* Fast path specifics */
 430         dev_info->min_rx_bufsize = 1;
 431         dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
 432                                   + VLAN_TAG_SIZE;
 433
 434         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 435         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 436                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 437         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 438         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 439
 440         /* *INDENT-OFF* */
 441         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 442                 .rx_thresh = {
 443                         .pthresh = 8,
 444                         .hthresh = 8,
 445                         .wthresh = 0,
 446                 },
 447                 .rx_free_thresh = 32,
 448                 /* If no descriptors available, pkts are dropped by default */
 449                 .rx_drop_en = 1,
 450         };
 451
 452         dev_info->default_txconf = (struct rte_eth_txconf) {
 453                 .tx_thresh = {
 454                         .pthresh = 32,
 455                         .hthresh = 0,
 456                         .wthresh = 0,
 457                 },
 458                 .tx_free_thresh = 32,
 459                 .tx_rs_thresh = 32,
 460         };
 461         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 462
 463         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 464
 465         /* *INDENT-ON* */
 466
 467         /*
 468          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 469          *       need further investigation.
 470          */
 471
 472         /* VMDq resources */
 473         vpool = 64; /* ETH_64_POOLS */
 474         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 475         for (i = 0; i < 4; vpool >>= 1, i++) {
 476                 if (max_vnics > vpool) {
 477                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 478                                 if (dev_info->max_rx_queues > vrxq) {
 479                                         if (vpool > vrxq)
 480                                                 vpool = vrxq;
 481                                         goto found;
 482                                 }
 483                         }
 484                         /* Not enough resources to support VMDq */
 485                         break;
 486                 }
 487         }
 488         /* Not enough resources to support VMDq */
 489         vpool = 0;
 490         vrxq = 0;
 491 found:
 492         dev_info->max_vmdq_pools = vpool;
 493         dev_info->vmdq_queue_num = vrxq;
 494
 495         dev_info->vmdq_pool_base = 0;
 496         dev_info->vmdq_queue_base = 0;
 497 }
 498
 499 /* Configure the device based on the configuration provided */
 500 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 501 {
 502         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 503         uint64_t tx_offloads = eth_dev->data->dev_conf.txmode.offloads;
 504         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 505
 506         if (tx_offloads != (tx_offloads & BNXT_DEV_TX_OFFLOAD_SUPPORT)) {
 507                 PMD_DRV_LOG
 508                         (ERR,
 509                          "Tx offloads requested 0x%" PRIx64 " supported 0x%x\n",
 510                          tx_offloads, BNXT_DEV_TX_OFFLOAD_SUPPORT);
 511                 return -ENOTSUP;
 512         }
 513
 514         if (rx_offloads != (rx_offloads & BNXT_DEV_RX_OFFLOAD_SUPPORT)) {
 515                 PMD_DRV_LOG
 516                         (ERR,
 517                          "Rx offloads requested 0x%" PRIx64 " supported 0x%x\n",
 518                             rx_offloads, BNXT_DEV_RX_OFFLOAD_SUPPORT);
 519                 return -ENOTSUP;
 520         }
 521
 522         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 523         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 524
 525         /* Inherit new configurations */
 526         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 527             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 528             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues + 1 >
 529             bp->max_cp_rings ||
 530             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 531             bp->max_stat_ctx ||
 532             (uint32_t)(eth_dev->data->nb_rx_queues + 1) > bp->max_ring_grps) {
 533                 PMD_DRV_LOG(ERR,
 534                         "Insufficient resources to support requested config\n");
 535                 PMD_DRV_LOG(ERR,
 536                         "Num Queues Requested: Tx %d, Rx %d\n",
 537                         eth_dev->data->nb_tx_queues,
 538                         eth_dev->data->nb_rx_queues);
 539                 PMD_DRV_LOG(ERR,
 540                         "Res available: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d\n",
 541                         bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 542                         bp->max_stat_ctx, bp->max_ring_grps);
 543                 return -ENOSPC;
 544         }
 545
 546         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 547         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 548         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 549         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 550
 551         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
 552                 eth_dev->data->mtu =
 553                                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 554                                 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE;
 555         return 0;
 556 }
 557
 558 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 559 {
 560         struct rte_eth_link *link = &eth_dev->data->dev_link;
 561
 562         if (link->link_status)
 563                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 564                         eth_dev->data->port_id,
 565                         (uint32_t)link->link_speed,
 566                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 567                         ("full-duplex") : ("half-duplex\n"));
 568         else
 569                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 570                         eth_dev->data->port_id);
 571 }
 572
 573 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
 574 {
 575         bnxt_print_link_info(eth_dev);
 576         return 0;
 577 }
 578
 579 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 580 {
 581         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 582         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 583         int vlan_mask = 0;
 584         int rc;
 585
 586         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 587                 PMD_DRV_LOG(ERR,
 588                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 589                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 590         }
 591         bp->dev_stopped = 0;
 592
 593         rc = bnxt_init_chip(bp);
 594         if (rc)
 595                 goto error;
 596
 597         bnxt_link_update_op(eth_dev, 1);
 598
 599         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 600                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 601         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 602                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 603         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 604         if (rc)
 605                 goto error;
 606
 607         bp->flags |= BNXT_FLAG_INIT_DONE;
 608         return 0;
 609
 610 error:
 611         bnxt_shutdown_nic(bp);
 612         bnxt_free_tx_mbufs(bp);
 613         bnxt_free_rx_mbufs(bp);
 614         return rc;
 615 }
 616
 617 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 618 {
 619         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 620         int rc = 0;
 621
 622         if (!bp->link_info.link_up)
 623                 rc = bnxt_set_hwrm_link_config(bp, true);
 624         if (!rc)
 625                 eth_dev->data->dev_link.link_status = 1;
 626
 627         bnxt_print_link_info(eth_dev);
 628         return 0;
 629 }
 630
 631 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 632 {
 633         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 634
 635         eth_dev->data->dev_link.link_status = 0;
 636         bnxt_set_hwrm_link_config(bp, false);
 637         bp->link_info.link_up = 0;
 638
 639         return 0;
 640 }
 641
 642 /* Unload the driver, release resources */
 643 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 644 {
 645         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 646
 647         if (bp->eth_dev->data->dev_started) {
 648                 /* TBD: STOP HW queues DMA */
 649                 eth_dev->data->dev_link.link_status = 0;
 650         }
 651         bnxt_set_hwrm_link_config(bp, false);
 652         bnxt_hwrm_port_clr_stats(bp);
 653         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 654         bnxt_shutdown_nic(bp);
 655         bp->dev_stopped = 1;
 656 }
 657
 658 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 659 {
 660         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 661
 662         if (bp->dev_stopped == 0)
 663                 bnxt_dev_stop_op(eth_dev);
 664
 665         bnxt_free_tx_mbufs(bp);
 666         bnxt_free_rx_mbufs(bp);
 667         bnxt_free_mem(bp);
 668         if (eth_dev->data->mac_addrs != NULL) {
 669                 rte_free(eth_dev->data->mac_addrs);
 670                 eth_dev->data->mac_addrs = NULL;
 671         }
 672         if (bp->grp_info != NULL) {
 673                 rte_free(bp->grp_info);
 674                 bp->grp_info = NULL;
 675         }
 676 }
 677
 678 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 679                                     uint32_t index)
 680 {
 681         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 682         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 683         struct bnxt_vnic_info *vnic;
 684         struct bnxt_filter_info *filter, *temp_filter;
 685         uint32_t pool = RTE_MIN(MAX_FF_POOLS, ETH_64_POOLS);
 686         uint32_t i;
 687
 688         /*
 689          * Loop through all VNICs from the specified filter flow pools to
 690          * remove the corresponding MAC addr filter
 691          */
 692         for (i = 0; i < pool; i++) {
 693                 if (!(pool_mask & (1ULL << i)))
 694                         continue;
 695
 696                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
 697                         filter = STAILQ_FIRST(&vnic->filter);
 698                         while (filter) {
 699                                 temp_filter = STAILQ_NEXT(filter, next);
 700                                 if (filter->mac_index == index) {
 701                                         STAILQ_REMOVE(&vnic->filter, filter,
 702                                                       bnxt_filter_info, next);
 703                                         bnxt_hwrm_clear_l2_filter(bp, filter);
 704                                         filter->mac_index = INVALID_MAC_INDEX;
 705                                         memset(&filter->l2_addr, 0,
 706                                                ETHER_ADDR_LEN);
 707                                         STAILQ_INSERT_TAIL(
 708                                                         &bp->free_filter_list,
 709                                                         filter, next);
 710                                 }
 711                                 filter = temp_filter;
 712                         }
 713                 }
 714         }
 715 }
 716
 717 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
 718                                 struct ether_addr *mac_addr,
 719                                 uint32_t index, uint32_t pool)
 720 {
 721         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 722         struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]);
 723         struct bnxt_filter_info *filter;
 724
 725         if (BNXT_VF(bp)) {
 726                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
 727                 return -ENOTSUP;
 728         }
 729
 730         if (!vnic) {
 731                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
 732                 return -EINVAL;
 733         }
 734         /* Attach requested MAC address to the new l2_filter */
 735         STAILQ_FOREACH(filter, &vnic->filter, next) {
 736                 if (filter->mac_index == index) {
 737                         PMD_DRV_LOG(ERR,
 738                                 "MAC addr already existed for pool %d\n", pool);
 739                         return 0;
 740                 }
 741         }
 742         filter = bnxt_alloc_filter(bp);
 743         if (!filter) {
 744                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
 745                 return -ENODEV;
 746         }
 747         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
 748         filter->mac_index = index;
 749         memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
 750         return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
 751 }
 752
 753 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
 754 {
 755         int rc = 0;
 756         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 757         struct rte_eth_link new;
 758         unsigned int cnt = BNXT_LINK_WAIT_CNT;
 759
 760         memset(&new, 0, sizeof(new));
 761         do {
 762                 /* Retrieve link info from hardware */
 763                 rc = bnxt_get_hwrm_link_config(bp, &new);
 764                 if (rc) {
 765                         new.link_speed = ETH_LINK_SPEED_100M;
 766                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
 767                         PMD_DRV_LOG(ERR,
 768                                 "Failed to retrieve link rc = 0x%x!\n", rc);
 769                         goto out;
 770                 }
 771                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
 772
 773                 if (!wait_to_complete)
 774                         break;
 775         } while (!new.link_status && cnt--);
 776
 777 out:
 778         /* Timed out or success */
 779         if (new.link_status != eth_dev->data->dev_link.link_status ||
 780         new.link_speed != eth_dev->data->dev_link.link_speed) {
 781                 memcpy(&eth_dev->data->dev_link, &new,
 782                         sizeof(struct rte_eth_link));
 783                 bnxt_print_link_info(eth_dev);
 784         }
 785
 786         return rc;
 787 }
 788
 789 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
 790 {
 791         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 792         struct bnxt_vnic_info *vnic;
 793
 794         if (bp->vnic_info == NULL)
 795                 return;
 796
 797         vnic = &bp->vnic_info[0];
 798
 799         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
 800         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 801 }
 802
 803 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
 804 {
 805         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 806         struct bnxt_vnic_info *vnic;
 807
 808         if (bp->vnic_info == NULL)
 809                 return;
 810
 811         vnic = &bp->vnic_info[0];
 812
 813         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
 814         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 815 }
 816
 817 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
 818 {
 819         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 820         struct bnxt_vnic_info *vnic;
 821
 822         if (bp->vnic_info == NULL)
 823                 return;
 824
 825         vnic = &bp->vnic_info[0];
 826
 827         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
 828         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 829 }
 830
 831 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
 832 {
 833         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 834         struct bnxt_vnic_info *vnic;
 835
 836         if (bp->vnic_info == NULL)
 837                 return;
 838
 839         vnic = &bp->vnic_info[0];
 840
 841         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
 842         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 843 }
 844
 845 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
 846                             struct rte_eth_rss_reta_entry64 *reta_conf,
 847                             uint16_t reta_size)
 848 {
 849         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 850         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 851         struct bnxt_vnic_info *vnic;
 852         int i;
 853
 854         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
 855                 return -EINVAL;
 856
 857         if (reta_size != HW_HASH_INDEX_SIZE) {
 858                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
 859                         "(%d) must equal the size supported by the hardware "
 860                         "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
 861                 return -EINVAL;
 862         }
 863         /* Update the RSS VNIC(s) */
 864         for (i = 0; i < MAX_FF_POOLS; i++) {
 865                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
 866                         memcpy(vnic->rss_table, reta_conf, reta_size);
 867
 868                         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
 869                 }
 870         }
 871         return 0;
 872 }
 873
 874 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
 875                               struct rte_eth_rss_reta_entry64 *reta_conf,
 876                               uint16_t reta_size)
 877 {
 878         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 879         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
 880         struct rte_intr_handle *intr_handle
 881                 = &bp->pdev->intr_handle;
 882
 883         /* Retrieve from the default VNIC */
 884         if (!vnic)
 885                 return -EINVAL;
 886         if (!vnic->rss_table)
 887                 return -EINVAL;
 888
 889         if (reta_size != HW_HASH_INDEX_SIZE) {
 890                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
 891                         "(%d) must equal the size supported by the hardware "
 892                         "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
 893                 return -EINVAL;
 894         }
 895         /* EW - need to revisit here copying from uint64_t to uint16_t */
 896         memcpy(reta_conf, vnic->rss_table, reta_size);
 897
 898         if (rte_intr_allow_others(intr_handle)) {
 899                 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
 900                         bnxt_dev_lsc_intr_setup(eth_dev);
 901         }
 902
 903         return 0;
 904 }
 905
 906 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
 907                                    struct rte_eth_rss_conf *rss_conf)
 908 {
 909         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 910         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 911         struct bnxt_vnic_info *vnic;
 912         uint16_t hash_type = 0;
 913         int i;
 914
 915         /*
 916          * If RSS enablement were different than dev_configure,
 917          * then return -EINVAL
 918          */
 919         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
 920                 if (!rss_conf->rss_hf)
 921                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
 922         } else {
 923                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
 924                         return -EINVAL;
 925         }
 926
 927         bp->flags |= BNXT_FLAG_UPDATE_HASH;
 928         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
 929
 930         if (rss_conf->rss_hf & ETH_RSS_IPV4)
 931                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
 932         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
 933                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
 934         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
 935                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
 936         if (rss_conf->rss_hf & ETH_RSS_IPV6)
 937                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
 938         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
 939                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
 940         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
 941                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
 942
 943         /* Update the RSS VNIC(s) */
 944         for (i = 0; i < MAX_FF_POOLS; i++) {
 945                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
 946                         vnic->hash_type = hash_type;
 947
 948                         /*
 949                          * Use the supplied key if the key length is
 950                          * acceptable and the rss_key is not NULL
 951                          */
 952                         if (rss_conf->rss_key &&
 953                             rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
 954                                 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
 955                                        rss_conf->rss_key_len);
 956
 957                         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
 958                 }
 959         }
 960         return 0;
 961 }
 962
 963 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
 964                                      struct rte_eth_rss_conf *rss_conf)
 965 {
 966         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 967         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
 968         int len;
 969         uint32_t hash_types;
 970
 971         /* RSS configuration is the same for all VNICs */
 972         if (vnic && vnic->rss_hash_key) {
 973                 if (rss_conf->rss_key) {
 974                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
 975                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
 976                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
 977                 }
 978
 979                 hash_types = vnic->hash_type;
 980                 rss_conf->rss_hf = 0;
 981                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
 982                         rss_conf->rss_hf |= ETH_RSS_IPV4;
 983                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
 984                 }
 985                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
 986                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
 987                         hash_types &=
 988                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
 989                 }
 990                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
 991                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
 992                         hash_types &=
 993                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
 994                 }
 995                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
 996                         rss_conf->rss_hf |= ETH_RSS_IPV6;
 997                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
 998                 }
 999                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1000                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1001                         hash_types &=
1002                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1003                 }
1004                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1005                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1006                         hash_types &=
1007                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1008                 }
1009                 if (hash_types) {
1010                         PMD_DRV_LOG(ERR,
1011                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1012                                 vnic->hash_type);
1013                         return -ENOTSUP;
1014                 }
1015         } else {
1016                 rss_conf->rss_hf = 0;
1017         }
1018         return 0;
1019 }
1020
1021 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1022                                struct rte_eth_fc_conf *fc_conf)
1023 {
1024         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1025         struct rte_eth_link link_info;
1026         int rc;
1027
1028         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1029         if (rc)
1030                 return rc;
1031
1032         memset(fc_conf, 0, sizeof(*fc_conf));
1033         if (bp->link_info.auto_pause)
1034                 fc_conf->autoneg = 1;
1035         switch (bp->link_info.pause) {
1036         case 0:
1037                 fc_conf->mode = RTE_FC_NONE;
1038                 break;
1039         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1040                 fc_conf->mode = RTE_FC_TX_PAUSE;
1041                 break;
1042         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1043                 fc_conf->mode = RTE_FC_RX_PAUSE;
1044                 break;
1045         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1046                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1047                 fc_conf->mode = RTE_FC_FULL;
1048                 break;
1049         }
1050         return 0;
1051 }
1052
1053 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1054                                struct rte_eth_fc_conf *fc_conf)
1055 {
1056         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1057
1058         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1059                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1060                 return -ENOTSUP;
1061         }
1062
1063         switch (fc_conf->mode) {
1064         case RTE_FC_NONE:
1065                 bp->link_info.auto_pause = 0;
1066                 bp->link_info.force_pause = 0;
1067                 break;
1068         case RTE_FC_RX_PAUSE:
1069                 if (fc_conf->autoneg) {
1070                         bp->link_info.auto_pause =
1071                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1072                         bp->link_info.force_pause = 0;
1073                 } else {
1074                         bp->link_info.auto_pause = 0;
1075                         bp->link_info.force_pause =
1076                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1077                 }
1078                 break;
1079         case RTE_FC_TX_PAUSE:
1080                 if (fc_conf->autoneg) {
1081                         bp->link_info.auto_pause =
1082                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1083                         bp->link_info.force_pause = 0;
1084                 } else {
1085                         bp->link_info.auto_pause = 0;
1086                         bp->link_info.force_pause =
1087                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1088                 }
1089                 break;
1090         case RTE_FC_FULL:
1091                 if (fc_conf->autoneg) {
1092                         bp->link_info.auto_pause =
1093                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1094                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1095                         bp->link_info.force_pause = 0;
1096                 } else {
1097                         bp->link_info.auto_pause = 0;
1098                         bp->link_info.force_pause =
1099                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1100                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1101                 }
1102                 break;
1103         }
1104         return bnxt_set_hwrm_link_config(bp, true);
1105 }
1106
1107 /* Add UDP tunneling port */
1108 static int
1109 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1110                          struct rte_eth_udp_tunnel *udp_tunnel)
1111 {
1112         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1113         uint16_t tunnel_type = 0;
1114         int rc = 0;
1115
1116         switch (udp_tunnel->prot_type) {
1117         case RTE_TUNNEL_TYPE_VXLAN:
1118                 if (bp->vxlan_port_cnt) {
1119                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1120                                 udp_tunnel->udp_port);
1121                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1122                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1123                                 return -ENOSPC;
1124                         }
1125                         bp->vxlan_port_cnt++;
1126                         return 0;
1127                 }
1128                 tunnel_type =
1129                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1130                 bp->vxlan_port_cnt++;
1131                 break;
1132         case RTE_TUNNEL_TYPE_GENEVE:
1133                 if (bp->geneve_port_cnt) {
1134                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1135                                 udp_tunnel->udp_port);
1136                         if (bp->geneve_port != udp_tunnel->udp_port) {
1137                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1138                                 return -ENOSPC;
1139                         }
1140                         bp->geneve_port_cnt++;
1141                         return 0;
1142                 }
1143                 tunnel_type =
1144                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1145                 bp->geneve_port_cnt++;
1146                 break;
1147         default:
1148                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1149                 return -ENOTSUP;
1150         }
1151         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1152                                              tunnel_type);
1153         return rc;
1154 }
1155
1156 static int
1157 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1158                          struct rte_eth_udp_tunnel *udp_tunnel)
1159 {
1160         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1161         uint16_t tunnel_type = 0;
1162         uint16_t port = 0;
1163         int rc = 0;
1164
1165         switch (udp_tunnel->prot_type) {
1166         case RTE_TUNNEL_TYPE_VXLAN:
1167                 if (!bp->vxlan_port_cnt) {
1168                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1169                         return -EINVAL;
1170                 }
1171                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1172                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1173                                 udp_tunnel->udp_port, bp->vxlan_port);
1174                         return -EINVAL;
1175                 }
1176                 if (--bp->vxlan_port_cnt)
1177                         return 0;
1178
1179                 tunnel_type =
1180                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1181                 port = bp->vxlan_fw_dst_port_id;
1182                 break;
1183         case RTE_TUNNEL_TYPE_GENEVE:
1184                 if (!bp->geneve_port_cnt) {
1185                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1186                         return -EINVAL;
1187                 }
1188                 if (bp->geneve_port != udp_tunnel->udp_port) {
1189                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1190                                 udp_tunnel->udp_port, bp->geneve_port);
1191                         return -EINVAL;
1192                 }
1193                 if (--bp->geneve_port_cnt)
1194                         return 0;
1195
1196                 tunnel_type =
1197                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1198                 port = bp->geneve_fw_dst_port_id;
1199                 break;
1200         default:
1201                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1202                 return -ENOTSUP;
1203         }
1204
1205         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1206         if (!rc) {
1207                 if (tunnel_type ==
1208                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1209                         bp->vxlan_port = 0;
1210                 if (tunnel_type ==
1211                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1212                         bp->geneve_port = 0;
1213         }
1214         return rc;
1215 }
1216
1217 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1218 {
1219         struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1220         struct bnxt_vnic_info *vnic;
1221         unsigned int i;
1222         int rc = 0;
1223         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1224
1225         /* Cycle through all VNICs */
1226         for (i = 0; i < bp->nr_vnics; i++) {
1227                 /*
1228                  * For each VNIC and each associated filter(s)
1229                  * if VLAN exists && VLAN matches vlan_id
1230                  *      remove the MAC+VLAN filter
1231                  *      add a new MAC only filter
1232                  * else
1233                  *      VLAN filter doesn't exist, just skip and continue
1234                  */
1235                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1236                         filter = STAILQ_FIRST(&vnic->filter);
1237                         while (filter) {
1238                                 temp_filter = STAILQ_NEXT(filter, next);
1239
1240                                 if (filter->enables & chk &&
1241                                     filter->l2_ovlan == vlan_id) {
1242                                         /* Must delete the filter */
1243                                         STAILQ_REMOVE(&vnic->filter, filter,
1244                                                       bnxt_filter_info, next);
1245                                         bnxt_hwrm_clear_l2_filter(bp, filter);
1246                                         STAILQ_INSERT_TAIL(
1247                                                         &bp->free_filter_list,
1248                                                         filter, next);
1249
1250                                         /*
1251                                          * Need to examine to see if the MAC
1252                                          * filter already existed or not before
1253                                          * allocating a new one
1254                                          */
1255
1256                                         new_filter = bnxt_alloc_filter(bp);
1257                                         if (!new_filter) {
1258                                                 PMD_DRV_LOG(ERR,
1259                                                         "MAC/VLAN filter alloc failed\n");
1260                                                 rc = -ENOMEM;
1261                                                 goto exit;
1262                                         }
1263                                         STAILQ_INSERT_TAIL(&vnic->filter,
1264                                                            new_filter, next);
1265                                         /* Inherit MAC from previous filter */
1266                                         new_filter->mac_index =
1267                                                         filter->mac_index;
1268                                         memcpy(new_filter->l2_addr,
1269                                                filter->l2_addr, ETHER_ADDR_LEN);
1270                                         /* MAC only filter */
1271                                         rc = bnxt_hwrm_set_l2_filter(bp,
1272                                                         vnic->fw_vnic_id,
1273                                                         new_filter);
1274                                         if (rc)
1275                                                 goto exit;
1276                                         PMD_DRV_LOG(INFO,
1277                                                 "Del Vlan filter for %d\n",
1278                                                 vlan_id);
1279                                 }
1280                                 filter = temp_filter;
1281                         }
1282                 }
1283         }
1284 exit:
1285         return rc;
1286 }
1287
1288 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1289 {
1290         struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1291         struct bnxt_vnic_info *vnic;
1292         unsigned int i;
1293         int rc = 0;
1294         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN |
1295                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK;
1296         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1297
1298         /* Cycle through all VNICs */
1299         for (i = 0; i < bp->nr_vnics; i++) {
1300                 /*
1301                  * For each VNIC and each associated filter(s)
1302                  * if VLAN exists:
1303                  *   if VLAN matches vlan_id
1304                  *      VLAN filter already exists, just skip and continue
1305                  *   else
1306                  *      add a new MAC+VLAN filter
1307                  * else
1308                  *   Remove the old MAC only filter
1309                  *    Add a new MAC+VLAN filter
1310                  */
1311                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1312                         filter = STAILQ_FIRST(&vnic->filter);
1313                         while (filter) {
1314                                 temp_filter = STAILQ_NEXT(filter, next);
1315
1316                                 if (filter->enables & chk) {
1317                                         if (filter->l2_ovlan == vlan_id)
1318                                                 goto cont;
1319                                 } else {
1320                                         /* Must delete the MAC filter */
1321                                         STAILQ_REMOVE(&vnic->filter, filter,
1322                                                       bnxt_filter_info, next);
1323                                         bnxt_hwrm_clear_l2_filter(bp, filter);
1324                                         filter->l2_ovlan = 0;
1325                                         STAILQ_INSERT_TAIL(
1326                                                         &bp->free_filter_list,
1327                                                         filter, next);
1328                                 }
1329                                 new_filter = bnxt_alloc_filter(bp);
1330                                 if (!new_filter) {
1331                                         PMD_DRV_LOG(ERR,
1332                                                 "MAC/VLAN filter alloc failed\n");
1333                                         rc = -ENOMEM;
1334                                         goto exit;
1335                                 }
1336                                 STAILQ_INSERT_TAIL(&vnic->filter, new_filter,
1337                                                    next);
1338                                 /* Inherit MAC from the previous filter */
1339                                 new_filter->mac_index = filter->mac_index;
1340                                 memcpy(new_filter->l2_addr, filter->l2_addr,
1341                                        ETHER_ADDR_LEN);
1342                                 /* MAC + VLAN ID filter */
1343                                 new_filter->l2_ovlan = vlan_id;
1344                                 new_filter->l2_ovlan_mask = 0xF000;
1345                                 new_filter->enables |= en;
1346                                 rc = bnxt_hwrm_set_l2_filter(bp,
1347                                                              vnic->fw_vnic_id,
1348                                                              new_filter);
1349                                 if (rc)
1350                                         goto exit;
1351                                 PMD_DRV_LOG(INFO,
1352                                         "Added Vlan filter for %d\n", vlan_id);
1353 cont:
1354                                 filter = temp_filter;
1355                         }
1356                 }
1357         }
1358 exit:
1359         return rc;
1360 }
1361
1362 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1363                                    uint16_t vlan_id, int on)
1364 {
1365         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1366
1367         /* These operations apply to ALL existing MAC/VLAN filters */
1368         if (on)
1369                 return bnxt_add_vlan_filter(bp, vlan_id);
1370         else
1371                 return bnxt_del_vlan_filter(bp, vlan_id);
1372 }
1373
1374 static int
1375 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1376 {
1377         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1378         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1379         unsigned int i;
1380
1381         if (mask & ETH_VLAN_FILTER_MASK) {
1382                 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1383                         /* Remove any VLAN filters programmed */
1384                         for (i = 0; i < 4095; i++)
1385                                 bnxt_del_vlan_filter(bp, i);
1386                 }
1387                 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1388                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1389         }
1390
1391         if (mask & ETH_VLAN_STRIP_MASK) {
1392                 /* Enable or disable VLAN stripping */
1393                 for (i = 0; i < bp->nr_vnics; i++) {
1394                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1395                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1396                                 vnic->vlan_strip = true;
1397                         else
1398                                 vnic->vlan_strip = false;
1399                         bnxt_hwrm_vnic_cfg(bp, vnic);
1400                 }
1401                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1402                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1403         }
1404
1405         if (mask & ETH_VLAN_EXTEND_MASK)
1406                 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1407
1408         return 0;
1409 }
1410
1411 static int
1412 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, struct ether_addr *addr)
1413 {
1414         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1415         /* Default Filter is tied to VNIC 0 */
1416         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1417         struct bnxt_filter_info *filter;
1418         int rc;
1419
1420         if (BNXT_VF(bp))
1421                 return -EPERM;
1422
1423         memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1424
1425         STAILQ_FOREACH(filter, &vnic->filter, next) {
1426                 /* Default Filter is at Index 0 */
1427                 if (filter->mac_index != 0)
1428                         continue;
1429                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1430                 if (rc)
1431                         return rc;
1432                 memcpy(filter->l2_addr, bp->mac_addr, ETHER_ADDR_LEN);
1433                 memset(filter->l2_addr_mask, 0xff, ETHER_ADDR_LEN);
1434                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1435                 filter->enables |=
1436                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1437                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1438                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1439                 if (rc)
1440                         return rc;
1441                 filter->mac_index = 0;
1442                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1443         }
1444
1445         return 0;
1446 }
1447
1448 static int
1449 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1450                           struct ether_addr *mc_addr_set,
1451                           uint32_t nb_mc_addr)
1452 {
1453         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1454         char *mc_addr_list = (char *)mc_addr_set;
1455         struct bnxt_vnic_info *vnic;
1456         uint32_t off = 0, i = 0;
1457
1458         vnic = &bp->vnic_info[0];
1459
1460         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1461                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1462                 goto allmulti;
1463         }
1464
1465         /* TODO Check for Duplicate mcast addresses */
1466         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1467         for (i = 0; i < nb_mc_addr; i++) {
1468                 memcpy(vnic->mc_list + off, &mc_addr_list[i], ETHER_ADDR_LEN);
1469                 off += ETHER_ADDR_LEN;
1470         }
1471
1472         vnic->mc_addr_cnt = i;
1473
1474 allmulti:
1475         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1476 }
1477
1478 static int
1479 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1480 {
1481         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1482         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1483         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1484         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1485         int ret;
1486
1487         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1488                         fw_major, fw_minor, fw_updt);
1489
1490         ret += 1; /* add the size of '\0' */
1491         if (fw_size < (uint32_t)ret)
1492                 return ret;
1493         else
1494                 return 0;
1495 }
1496
1497 static void
1498 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1499         struct rte_eth_rxq_info *qinfo)
1500 {
1501         struct bnxt_rx_queue *rxq;
1502
1503         rxq = dev->data->rx_queues[queue_id];
1504
1505         qinfo->mp = rxq->mb_pool;
1506         qinfo->scattered_rx = dev->data->scattered_rx;
1507         qinfo->nb_desc = rxq->nb_rx_desc;
1508
1509         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1510         qinfo->conf.rx_drop_en = 0;
1511         qinfo->conf.rx_deferred_start = 0;
1512 }
1513
1514 static void
1515 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1516         struct rte_eth_txq_info *qinfo)
1517 {
1518         struct bnxt_tx_queue *txq;
1519
1520         txq = dev->data->tx_queues[queue_id];
1521
1522         qinfo->nb_desc = txq->nb_tx_desc;
1523
1524         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1525         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1526         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1527
1528         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1529         qinfo->conf.tx_rs_thresh = 0;
1530         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1531 }
1532
1533 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1534 {
1535         struct bnxt *bp = eth_dev->data->dev_private;
1536         struct rte_eth_dev_info dev_info;
1537         uint32_t max_dev_mtu;
1538         uint32_t rc = 0;
1539         uint32_t i;
1540
1541         bnxt_dev_info_get_op(eth_dev, &dev_info);
1542         max_dev_mtu = dev_info.max_rx_pktlen -
1543                       ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE * 2;
1544
1545         if (new_mtu < ETHER_MIN_MTU || new_mtu > max_dev_mtu) {
1546                 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1547                         ETHER_MIN_MTU, max_dev_mtu);
1548                 return -EINVAL;
1549         }
1550
1551
1552         if (new_mtu > ETHER_MTU) {
1553                 bp->flags |= BNXT_FLAG_JUMBO;
1554                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1555                         DEV_RX_OFFLOAD_JUMBO_FRAME;
1556         } else {
1557                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1558                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1559                 bp->flags &= ~BNXT_FLAG_JUMBO;
1560         }
1561
1562         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len =
1563                 new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1564
1565         eth_dev->data->mtu = new_mtu;
1566         PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1567
1568         for (i = 0; i < bp->nr_vnics; i++) {
1569                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1570
1571                 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1572                                         ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1573                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1574                 if (rc)
1575                         break;
1576
1577                 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1578                 if (rc)
1579                         return rc;
1580         }
1581
1582         return rc;
1583 }
1584
1585 static int
1586 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1587 {
1588         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1589         uint16_t vlan = bp->vlan;
1590         int rc;
1591
1592         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1593                 PMD_DRV_LOG(ERR,
1594                         "PVID cannot be modified for this function\n");
1595                 return -ENOTSUP;
1596         }
1597         bp->vlan = on ? pvid : 0;
1598
1599         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1600         if (rc)
1601                 bp->vlan = vlan;
1602         return rc;
1603 }
1604
1605 static int
1606 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1607 {
1608         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1609
1610         return bnxt_hwrm_port_led_cfg(bp, true);
1611 }
1612
1613 static int
1614 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1615 {
1616         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1617
1618         return bnxt_hwrm_port_led_cfg(bp, false);
1619 }
1620
1621 static uint32_t
1622 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1623 {
1624         uint32_t desc = 0, raw_cons = 0, cons;
1625         struct bnxt_cp_ring_info *cpr;
1626         struct bnxt_rx_queue *rxq;
1627         struct rx_pkt_cmpl *rxcmp;
1628         uint16_t cmp_type;
1629         uint8_t cmp = 1;
1630         bool valid;
1631
1632         rxq = dev->data->rx_queues[rx_queue_id];
1633         cpr = rxq->cp_ring;
1634         valid = cpr->valid;
1635
1636         while (raw_cons < rxq->nb_rx_desc) {
1637                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1638                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1639
1640                 if (!CMPL_VALID(rxcmp, valid))
1641                         goto nothing_to_do;
1642                 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1643                 cmp_type = CMP_TYPE(rxcmp);
1644                 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1645                         cmp = (rte_le_to_cpu_32(
1646                                         ((struct rx_tpa_end_cmpl *)
1647                                          (rxcmp))->agg_bufs_v1) &
1648                                RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1649                                 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1650                         desc++;
1651                 } else if (cmp_type == 0x11) {
1652                         desc++;
1653                         cmp = (rxcmp->agg_bufs_v1 &
1654                                    RX_PKT_CMPL_AGG_BUFS_MASK) >>
1655                                 RX_PKT_CMPL_AGG_BUFS_SFT;
1656                 } else {
1657                         cmp = 1;
1658                 }
1659 nothing_to_do:
1660                 raw_cons += cmp ? cmp : 2;
1661         }
1662
1663         return desc;
1664 }
1665
1666 static int
1667 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1668 {
1669         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1670         struct bnxt_rx_ring_info *rxr;
1671         struct bnxt_cp_ring_info *cpr;
1672         struct bnxt_sw_rx_bd *rx_buf;
1673         struct rx_pkt_cmpl *rxcmp;
1674         uint32_t cons, cp_cons;
1675
1676         if (!rxq)
1677                 return -EINVAL;
1678
1679         cpr = rxq->cp_ring;
1680         rxr = rxq->rx_ring;
1681
1682         if (offset >= rxq->nb_rx_desc)
1683                 return -EINVAL;
1684
1685         cons = RING_CMP(cpr->cp_ring_struct, offset);
1686         cp_cons = cpr->cp_raw_cons;
1687         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1688
1689         if (cons > cp_cons) {
1690                 if (CMPL_VALID(rxcmp, cpr->valid))
1691                         return RTE_ETH_RX_DESC_DONE;
1692         } else {
1693                 if (CMPL_VALID(rxcmp, !cpr->valid))
1694                         return RTE_ETH_RX_DESC_DONE;
1695         }
1696         rx_buf = &rxr->rx_buf_ring[cons];
1697         if (rx_buf->mbuf == NULL)
1698                 return RTE_ETH_RX_DESC_UNAVAIL;
1699
1700
1701         return RTE_ETH_RX_DESC_AVAIL;
1702 }
1703
1704 static int
1705 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1706 {
1707         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1708         struct bnxt_tx_ring_info *txr;
1709         struct bnxt_cp_ring_info *cpr;
1710         struct bnxt_sw_tx_bd *tx_buf;
1711         struct tx_pkt_cmpl *txcmp;
1712         uint32_t cons, cp_cons;
1713
1714         if (!txq)
1715                 return -EINVAL;
1716
1717         cpr = txq->cp_ring;
1718         txr = txq->tx_ring;
1719
1720         if (offset >= txq->nb_tx_desc)
1721                 return -EINVAL;
1722
1723         cons = RING_CMP(cpr->cp_ring_struct, offset);
1724         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1725         cp_cons = cpr->cp_raw_cons;
1726
1727         if (cons > cp_cons) {
1728                 if (CMPL_VALID(txcmp, cpr->valid))
1729                         return RTE_ETH_TX_DESC_UNAVAIL;
1730         } else {
1731                 if (CMPL_VALID(txcmp, !cpr->valid))
1732                         return RTE_ETH_TX_DESC_UNAVAIL;
1733         }
1734         tx_buf = &txr->tx_buf_ring[cons];
1735         if (tx_buf->mbuf == NULL)
1736                 return RTE_ETH_TX_DESC_DONE;
1737
1738         return RTE_ETH_TX_DESC_FULL;
1739 }
1740
1741 static struct bnxt_filter_info *
1742 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
1743                                 struct rte_eth_ethertype_filter *efilter,
1744                                 struct bnxt_vnic_info *vnic0,
1745                                 struct bnxt_vnic_info *vnic,
1746                                 int *ret)
1747 {
1748         struct bnxt_filter_info *mfilter = NULL;
1749         int match = 0;
1750         *ret = 0;
1751
1752         if (efilter->ether_type == ETHER_TYPE_IPv4 ||
1753                 efilter->ether_type == ETHER_TYPE_IPv6) {
1754                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
1755                         " ethertype filter.", efilter->ether_type);
1756                 *ret = -EINVAL;
1757                 goto exit;
1758         }
1759         if (efilter->queue >= bp->rx_nr_rings) {
1760                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1761                 *ret = -EINVAL;
1762                 goto exit;
1763         }
1764
1765         vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1766         vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1767         if (vnic == NULL) {
1768                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1769                 *ret = -EINVAL;
1770                 goto exit;
1771         }
1772
1773         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1774                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
1775                         if ((!memcmp(efilter->mac_addr.addr_bytes,
1776                                      mfilter->l2_addr, ETHER_ADDR_LEN) &&
1777                              mfilter->flags ==
1778                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
1779                              mfilter->ethertype == efilter->ether_type)) {
1780                                 match = 1;
1781                                 break;
1782                         }
1783                 }
1784         } else {
1785                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
1786                         if ((!memcmp(efilter->mac_addr.addr_bytes,
1787                                      mfilter->l2_addr, ETHER_ADDR_LEN) &&
1788                              mfilter->ethertype == efilter->ether_type &&
1789                              mfilter->flags ==
1790                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
1791                                 match = 1;
1792                                 break;
1793                         }
1794         }
1795
1796         if (match)
1797                 *ret = -EEXIST;
1798
1799 exit:
1800         return mfilter;
1801 }
1802
1803 static int
1804 bnxt_ethertype_filter(struct rte_eth_dev *dev,
1805                         enum rte_filter_op filter_op,
1806                         void *arg)
1807 {
1808         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1809         struct rte_eth_ethertype_filter *efilter =
1810                         (struct rte_eth_ethertype_filter *)arg;
1811         struct bnxt_filter_info *bfilter, *filter1;
1812         struct bnxt_vnic_info *vnic, *vnic0;
1813         int ret;
1814
1815         if (filter_op == RTE_ETH_FILTER_NOP)
1816                 return 0;
1817
1818         if (arg == NULL) {
1819                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
1820                             filter_op);
1821                 return -EINVAL;
1822         }
1823
1824         vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1825         vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1826
1827         switch (filter_op) {
1828         case RTE_ETH_FILTER_ADD:
1829                 bnxt_match_and_validate_ether_filter(bp, efilter,
1830                                                         vnic0, vnic, &ret);
1831                 if (ret < 0)
1832                         return ret;
1833
1834                 bfilter = bnxt_get_unused_filter(bp);
1835                 if (bfilter == NULL) {
1836                         PMD_DRV_LOG(ERR,
1837                                 "Not enough resources for a new filter.\n");
1838                         return -ENOMEM;
1839                 }
1840                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
1841                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
1842                        ETHER_ADDR_LEN);
1843                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
1844                        ETHER_ADDR_LEN);
1845                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
1846                 bfilter->ethertype = efilter->ether_type;
1847                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
1848
1849                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
1850                 if (filter1 == NULL) {
1851                         ret = -1;
1852                         goto cleanup;
1853                 }
1854                 bfilter->enables |=
1855                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
1856                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
1857
1858                 bfilter->dst_id = vnic->fw_vnic_id;
1859
1860                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1861                         bfilter->flags =
1862                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
1863                 }
1864
1865                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
1866                 if (ret)
1867                         goto cleanup;
1868                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
1869                 break;
1870         case RTE_ETH_FILTER_DELETE:
1871                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
1872                                                         vnic0, vnic, &ret);
1873                 if (ret == -EEXIST) {
1874                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
1875
1876                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
1877                                       next);
1878                         bnxt_free_filter(bp, filter1);
1879                 } else if (ret == 0) {
1880                         PMD_DRV_LOG(ERR, "No matching filter found\n");
1881                 }
1882                 break;
1883         default:
1884                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
1885                 ret = -EINVAL;
1886                 goto error;
1887         }
1888         return ret;
1889 cleanup:
1890         bnxt_free_filter(bp, bfilter);
1891 error:
1892         return ret;
1893 }
1894
1895 static inline int
1896 parse_ntuple_filter(struct bnxt *bp,
1897                     struct rte_eth_ntuple_filter *nfilter,
1898                     struct bnxt_filter_info *bfilter)
1899 {
1900         uint32_t en = 0;
1901
1902         if (nfilter->queue >= bp->rx_nr_rings) {
1903                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
1904                 return -EINVAL;
1905         }
1906
1907         switch (nfilter->dst_port_mask) {
1908         case UINT16_MAX:
1909                 bfilter->dst_port_mask = -1;
1910                 bfilter->dst_port = nfilter->dst_port;
1911                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
1912                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
1913                 break;
1914         default:
1915                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
1916                 return -EINVAL;
1917         }
1918
1919         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
1920         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1921
1922         switch (nfilter->proto_mask) {
1923         case UINT8_MAX:
1924                 if (nfilter->proto == 17) /* IPPROTO_UDP */
1925                         bfilter->ip_protocol = 17;
1926                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
1927                         bfilter->ip_protocol = 6;
1928                 else
1929                         return -EINVAL;
1930                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1931                 break;
1932         default:
1933                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
1934                 return -EINVAL;
1935         }
1936
1937         switch (nfilter->dst_ip_mask) {
1938         case UINT32_MAX:
1939                 bfilter->dst_ipaddr_mask[0] = -1;
1940                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
1941                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
1942                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
1943                 break;
1944         default:
1945                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
1946                 return -EINVAL;
1947         }
1948
1949         switch (nfilter->src_ip_mask) {
1950         case UINT32_MAX:
1951                 bfilter->src_ipaddr_mask[0] = -1;
1952                 bfilter->src_ipaddr[0] = nfilter->src_ip;
1953                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
1954                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
1955                 break;
1956         default:
1957                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
1958                 return -EINVAL;
1959         }
1960
1961         switch (nfilter->src_port_mask) {
1962         case UINT16_MAX:
1963                 bfilter->src_port_mask = -1;
1964                 bfilter->src_port = nfilter->src_port;
1965                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
1966                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
1967                 break;
1968         default:
1969                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
1970                 return -EINVAL;
1971         }
1972
1973         //TODO Priority
1974         //nfilter->priority = (uint8_t)filter->priority;
1975
1976         bfilter->enables = en;
1977         return 0;
1978 }
1979
1980 static struct bnxt_filter_info*
1981 bnxt_match_ntuple_filter(struct bnxt *bp,
1982                          struct bnxt_filter_info *bfilter,
1983                          struct bnxt_vnic_info **mvnic)
1984 {
1985         struct bnxt_filter_info *mfilter = NULL;
1986         int i;
1987
1988         for (i = bp->nr_vnics - 1; i >= 0; i--) {
1989                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1990                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
1991                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
1992                             bfilter->src_ipaddr_mask[0] ==
1993                             mfilter->src_ipaddr_mask[0] &&
1994                             bfilter->src_port == mfilter->src_port &&
1995                             bfilter->src_port_mask == mfilter->src_port_mask &&
1996                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
1997                             bfilter->dst_ipaddr_mask[0] ==
1998                             mfilter->dst_ipaddr_mask[0] &&
1999                             bfilter->dst_port == mfilter->dst_port &&
2000                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2001                             bfilter->flags == mfilter->flags &&
2002                             bfilter->enables == mfilter->enables) {
2003                                 if (mvnic)
2004                                         *mvnic = vnic;
2005                                 return mfilter;
2006                         }
2007                 }
2008         }
2009         return NULL;
2010 }
2011
2012 static int
2013 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2014                        struct rte_eth_ntuple_filter *nfilter,
2015                        enum rte_filter_op filter_op)
2016 {
2017         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2018         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2019         int ret;
2020
2021         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2022                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2023                 return -EINVAL;
2024         }
2025
2026         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2027                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2028                 return -EINVAL;
2029         }
2030
2031         bfilter = bnxt_get_unused_filter(bp);
2032         if (bfilter == NULL) {
2033                 PMD_DRV_LOG(ERR,
2034                         "Not enough resources for a new filter.\n");
2035                 return -ENOMEM;
2036         }
2037         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2038         if (ret < 0)
2039                 goto free_filter;
2040
2041         vnic = STAILQ_FIRST(&bp->ff_pool[nfilter->queue]);
2042         vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
2043         filter1 = STAILQ_FIRST(&vnic0->filter);
2044         if (filter1 == NULL) {
2045                 ret = -1;
2046                 goto free_filter;
2047         }
2048
2049         bfilter->dst_id = vnic->fw_vnic_id;
2050         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2051         bfilter->enables |=
2052                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2053         bfilter->ethertype = 0x800;
2054         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2055
2056         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2057
2058         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2059             bfilter->dst_id == mfilter->dst_id) {
2060                 PMD_DRV_LOG(ERR, "filter exists.\n");
2061                 ret = -EEXIST;
2062                 goto free_filter;
2063         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2064                    bfilter->dst_id != mfilter->dst_id) {
2065                 mfilter->dst_id = vnic->fw_vnic_id;
2066                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2067                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2068                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2069                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2070                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2071                 goto free_filter;
2072         }
2073         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2074                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2075                 ret = -ENOENT;
2076                 goto free_filter;
2077         }
2078
2079         if (filter_op == RTE_ETH_FILTER_ADD) {
2080                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2081                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2082                 if (ret)
2083                         goto free_filter;
2084                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2085         } else {
2086                 if (mfilter == NULL) {
2087                         /* This should not happen. But for Coverity! */
2088                         ret = -ENOENT;
2089                         goto free_filter;
2090                 }
2091                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2092
2093                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2094                 bnxt_free_filter(bp, mfilter);
2095                 mfilter->fw_l2_filter_id = -1;
2096                 bnxt_free_filter(bp, bfilter);
2097                 bfilter->fw_l2_filter_id = -1;
2098         }
2099
2100         return 0;
2101 free_filter:
2102         bfilter->fw_l2_filter_id = -1;
2103         bnxt_free_filter(bp, bfilter);
2104         return ret;
2105 }
2106
2107 static int
2108 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2109                         enum rte_filter_op filter_op,
2110                         void *arg)
2111 {
2112         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2113         int ret;
2114
2115         if (filter_op == RTE_ETH_FILTER_NOP)
2116                 return 0;
2117
2118         if (arg == NULL) {
2119                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2120                             filter_op);
2121                 return -EINVAL;
2122         }
2123
2124         switch (filter_op) {
2125         case RTE_ETH_FILTER_ADD:
2126                 ret = bnxt_cfg_ntuple_filter(bp,
2127                         (struct rte_eth_ntuple_filter *)arg,
2128                         filter_op);
2129                 break;
2130         case RTE_ETH_FILTER_DELETE:
2131                 ret = bnxt_cfg_ntuple_filter(bp,
2132                         (struct rte_eth_ntuple_filter *)arg,
2133                         filter_op);
2134                 break;
2135         default:
2136                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2137                 ret = -EINVAL;
2138                 break;
2139         }
2140         return ret;
2141 }
2142
2143 static int
2144 bnxt_parse_fdir_filter(struct bnxt *bp,
2145                        struct rte_eth_fdir_filter *fdir,
2146                        struct bnxt_filter_info *filter)
2147 {
2148         enum rte_fdir_mode fdir_mode =
2149                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2150         struct bnxt_vnic_info *vnic0, *vnic;
2151         struct bnxt_filter_info *filter1;
2152         uint32_t en = 0;
2153         int i;
2154
2155         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2156                 return -EINVAL;
2157
2158         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2159         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2160
2161         switch (fdir->input.flow_type) {
2162         case RTE_ETH_FLOW_IPV4:
2163         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2164                 /* FALLTHROUGH */
2165                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2166                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2167                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2168                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2169                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2170                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2171                 filter->ip_addr_type =
2172                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2173                 filter->src_ipaddr_mask[0] = 0xffffffff;
2174                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2175                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2176                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2177                 filter->ethertype = 0x800;
2178                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2179                 break;
2180         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2181                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2182                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2183                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2184                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2185                 filter->dst_port_mask = 0xffff;
2186                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2187                 filter->src_port_mask = 0xffff;
2188                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2189                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2190                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2191                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2192                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2193                 filter->ip_protocol = 6;
2194                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2195                 filter->ip_addr_type =
2196                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2197                 filter->src_ipaddr_mask[0] = 0xffffffff;
2198                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2199                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2200                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2201                 filter->ethertype = 0x800;
2202                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2203                 break;
2204         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2205                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2206                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2207                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2208                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2209                 filter->dst_port_mask = 0xffff;
2210                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2211                 filter->src_port_mask = 0xffff;
2212                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2213                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2214                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2215                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2216                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2217                 filter->ip_protocol = 17;
2218                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2219                 filter->ip_addr_type =
2220                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2221                 filter->src_ipaddr_mask[0] = 0xffffffff;
2222                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2223                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2224                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2225                 filter->ethertype = 0x800;
2226                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2227                 break;
2228         case RTE_ETH_FLOW_IPV6:
2229         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2230                 /* FALLTHROUGH */
2231                 filter->ip_addr_type =
2232                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2233                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2234                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2235                 rte_memcpy(filter->src_ipaddr,
2236                            fdir->input.flow.ipv6_flow.src_ip, 16);
2237                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2238                 rte_memcpy(filter->dst_ipaddr,
2239                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2240                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2241                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2242                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2243                 memset(filter->src_ipaddr_mask, 0xff, 16);
2244                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2245                 filter->ethertype = 0x86dd;
2246                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2247                 break;
2248         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2249                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2250                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2251                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2252                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2253                 filter->dst_port_mask = 0xffff;
2254                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2255                 filter->src_port_mask = 0xffff;
2256                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2257                 filter->ip_addr_type =
2258                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2259                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2260                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2261                 rte_memcpy(filter->src_ipaddr,
2262                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2263                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2264                 rte_memcpy(filter->dst_ipaddr,
2265                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2266                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2267                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2268                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2269                 memset(filter->src_ipaddr_mask, 0xff, 16);
2270                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2271                 filter->ethertype = 0x86dd;
2272                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2273                 break;
2274         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2275                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2276                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2277                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2278                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2279                 filter->dst_port_mask = 0xffff;
2280                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2281                 filter->src_port_mask = 0xffff;
2282                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2283                 filter->ip_addr_type =
2284                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2285                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2286                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2287                 rte_memcpy(filter->src_ipaddr,
2288                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2289                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2290                 rte_memcpy(filter->dst_ipaddr,
2291                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2292                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2293                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2294                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2295                 memset(filter->src_ipaddr_mask, 0xff, 16);
2296                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2297                 filter->ethertype = 0x86dd;
2298                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2299                 break;
2300         case RTE_ETH_FLOW_L2_PAYLOAD:
2301                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2302                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2303                 break;
2304         case RTE_ETH_FLOW_VXLAN:
2305                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2306                         return -EINVAL;
2307                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2308                 filter->tunnel_type =
2309                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2310                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2311                 break;
2312         case RTE_ETH_FLOW_NVGRE:
2313                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2314                         return -EINVAL;
2315                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2316                 filter->tunnel_type =
2317                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2318                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2319                 break;
2320         case RTE_ETH_FLOW_UNKNOWN:
2321         case RTE_ETH_FLOW_RAW:
2322         case RTE_ETH_FLOW_FRAG_IPV4:
2323         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2324         case RTE_ETH_FLOW_FRAG_IPV6:
2325         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2326         case RTE_ETH_FLOW_IPV6_EX:
2327         case RTE_ETH_FLOW_IPV6_TCP_EX:
2328         case RTE_ETH_FLOW_IPV6_UDP_EX:
2329         case RTE_ETH_FLOW_GENEVE:
2330                 /* FALLTHROUGH */
2331         default:
2332                 return -EINVAL;
2333         }
2334
2335         vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
2336         vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]);
2337         if (vnic == NULL) {
2338                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2339                 return -EINVAL;
2340         }
2341
2342
2343         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2344                 rte_memcpy(filter->dst_macaddr,
2345                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2346                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2347         }
2348
2349         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2350                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2351                 filter1 = STAILQ_FIRST(&vnic0->filter);
2352                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2353         } else {
2354                 filter->dst_id = vnic->fw_vnic_id;
2355                 for (i = 0; i < ETHER_ADDR_LEN; i++)
2356                         if (filter->dst_macaddr[i] == 0x00)
2357                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2358                         else
2359                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2360         }
2361
2362         if (filter1 == NULL)
2363                 return -EINVAL;
2364
2365         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2366         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2367
2368         filter->enables = en;
2369
2370         return 0;
2371 }
2372
2373 static struct bnxt_filter_info *
2374 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2375                 struct bnxt_vnic_info **mvnic)
2376 {
2377         struct bnxt_filter_info *mf = NULL;
2378         int i;
2379
2380         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2381                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2382
2383                 STAILQ_FOREACH(mf, &vnic->filter, next) {
2384                         if (mf->filter_type == nf->filter_type &&
2385                             mf->flags == nf->flags &&
2386                             mf->src_port == nf->src_port &&
2387                             mf->src_port_mask == nf->src_port_mask &&
2388                             mf->dst_port == nf->dst_port &&
2389                             mf->dst_port_mask == nf->dst_port_mask &&
2390                             mf->ip_protocol == nf->ip_protocol &&
2391                             mf->ip_addr_type == nf->ip_addr_type &&
2392                             mf->ethertype == nf->ethertype &&
2393                             mf->vni == nf->vni &&
2394                             mf->tunnel_type == nf->tunnel_type &&
2395                             mf->l2_ovlan == nf->l2_ovlan &&
2396                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2397                             mf->l2_ivlan == nf->l2_ivlan &&
2398                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2399                             !memcmp(mf->l2_addr, nf->l2_addr, ETHER_ADDR_LEN) &&
2400                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2401                                     ETHER_ADDR_LEN) &&
2402                             !memcmp(mf->src_macaddr, nf->src_macaddr,
2403                                     ETHER_ADDR_LEN) &&
2404                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2405                                     ETHER_ADDR_LEN) &&
2406                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2407                                     sizeof(nf->src_ipaddr)) &&
2408                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2409                                     sizeof(nf->src_ipaddr_mask)) &&
2410                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2411                                     sizeof(nf->dst_ipaddr)) &&
2412                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2413                                     sizeof(nf->dst_ipaddr_mask))) {
2414                                 if (mvnic)
2415                                         *mvnic = vnic;
2416                                 return mf;
2417                         }
2418                 }
2419         }
2420         return NULL;
2421 }
2422
2423 static int
2424 bnxt_fdir_filter(struct rte_eth_dev *dev,
2425                  enum rte_filter_op filter_op,
2426                  void *arg)
2427 {
2428         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2429         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
2430         struct bnxt_filter_info *filter, *match;
2431         struct bnxt_vnic_info *vnic, *mvnic;
2432         int ret = 0, i;
2433
2434         if (filter_op == RTE_ETH_FILTER_NOP)
2435                 return 0;
2436
2437         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2438                 return -EINVAL;
2439
2440         switch (filter_op) {
2441         case RTE_ETH_FILTER_ADD:
2442         case RTE_ETH_FILTER_DELETE:
2443                 filter = bnxt_get_unused_filter(bp);
2444                 if (filter == NULL) {
2445                         PMD_DRV_LOG(ERR,
2446                                 "Not enough resources for a new flow.\n");
2447                         return -ENOMEM;
2448                 }
2449
2450                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2451                 if (ret != 0)
2452                         goto free_filter;
2453                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2454
2455                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2456                         vnic = STAILQ_FIRST(&bp->ff_pool[0]);
2457                 else
2458                         vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]);
2459
2460                 match = bnxt_match_fdir(bp, filter, &mvnic);
2461                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2462                         if (match->dst_id == vnic->fw_vnic_id) {
2463                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2464                                 ret = -EEXIST;
2465                                 goto free_filter;
2466                         } else {
2467                                 match->dst_id = vnic->fw_vnic_id;
2468                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
2469                                                                   match->dst_id,
2470                                                                   match);
2471                                 STAILQ_REMOVE(&mvnic->filter, match,
2472                                               bnxt_filter_info, next);
2473                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2474                                 PMD_DRV_LOG(ERR,
2475                                         "Filter with matching pattern exist\n");
2476                                 PMD_DRV_LOG(ERR,
2477                                         "Updated it to new destination q\n");
2478                                 goto free_filter;
2479                         }
2480                 }
2481                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2482                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2483                         ret = -ENOENT;
2484                         goto free_filter;
2485                 }
2486
2487                 if (filter_op == RTE_ETH_FILTER_ADD) {
2488                         ret = bnxt_hwrm_set_ntuple_filter(bp,
2489                                                           filter->dst_id,
2490                                                           filter);
2491                         if (ret)
2492                                 goto free_filter;
2493                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2494                 } else {
2495                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2496                         STAILQ_REMOVE(&vnic->filter, match,
2497                                       bnxt_filter_info, next);
2498                         bnxt_free_filter(bp, match);
2499                         filter->fw_l2_filter_id = -1;
2500                         bnxt_free_filter(bp, filter);
2501                 }
2502                 break;
2503         case RTE_ETH_FILTER_FLUSH:
2504                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2505                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2506
2507                         STAILQ_FOREACH(filter, &vnic->filter, next) {
2508                                 if (filter->filter_type ==
2509                                     HWRM_CFA_NTUPLE_FILTER) {
2510                                         ret =
2511                                         bnxt_hwrm_clear_ntuple_filter(bp,
2512                                                                       filter);
2513                                         STAILQ_REMOVE(&vnic->filter, filter,
2514                                                       bnxt_filter_info, next);
2515                                 }
2516                         }
2517                 }
2518                 return ret;
2519         case RTE_ETH_FILTER_UPDATE:
2520         case RTE_ETH_FILTER_STATS:
2521         case RTE_ETH_FILTER_INFO:
2522                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2523                 break;
2524         default:
2525                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2526                 ret = -EINVAL;
2527                 break;
2528         }
2529         return ret;
2530
2531 free_filter:
2532         filter->fw_l2_filter_id = -1;
2533         bnxt_free_filter(bp, filter);
2534         return ret;
2535 }
2536
2537 static int
2538 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2539                     enum rte_filter_type filter_type,
2540                     enum rte_filter_op filter_op, void *arg)
2541 {
2542         int ret = 0;
2543
2544         switch (filter_type) {
2545         case RTE_ETH_FILTER_TUNNEL:
2546                 PMD_DRV_LOG(ERR,
2547                         "filter type: %d: To be implemented\n", filter_type);
2548                 break;
2549         case RTE_ETH_FILTER_FDIR:
2550                 ret = bnxt_fdir_filter(dev, filter_op, arg);
2551                 break;
2552         case RTE_ETH_FILTER_NTUPLE:
2553                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2554                 break;
2555         case RTE_ETH_FILTER_ETHERTYPE:
2556                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2557                 break;
2558         case RTE_ETH_FILTER_GENERIC:
2559                 if (filter_op != RTE_ETH_FILTER_GET)
2560                         return -EINVAL;
2561                 *(const void **)arg = &bnxt_flow_ops;
2562                 break;
2563         default:
2564                 PMD_DRV_LOG(ERR,
2565                         "Filter type (%d) not supported", filter_type);
2566                 ret = -EINVAL;
2567                 break;
2568         }
2569         return ret;
2570 }
2571
2572 static const uint32_t *
2573 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2574 {
2575         static const uint32_t ptypes[] = {
2576                 RTE_PTYPE_L2_ETHER_VLAN,
2577                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2578                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2579                 RTE_PTYPE_L4_ICMP,
2580                 RTE_PTYPE_L4_TCP,
2581                 RTE_PTYPE_L4_UDP,
2582                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2583                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2584                 RTE_PTYPE_INNER_L4_ICMP,
2585                 RTE_PTYPE_INNER_L4_TCP,
2586                 RTE_PTYPE_INNER_L4_UDP,
2587                 RTE_PTYPE_UNKNOWN
2588         };
2589
2590         if (dev->rx_pkt_burst == bnxt_recv_pkts)
2591                 return ptypes;
2592         return NULL;
2593 }
2594
2595 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2596                          int reg_win)
2597 {
2598         uint32_t reg_base = *reg_arr & 0xfffff000;
2599         uint32_t win_off;
2600         int i;
2601
2602         for (i = 0; i < count; i++) {
2603                 if ((reg_arr[i] & 0xfffff000) != reg_base)
2604                         return -ERANGE;
2605         }
2606         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2607         rte_cpu_to_le_32(rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off));
2608         return 0;
2609 }
2610
2611 static int bnxt_map_ptp_regs(struct bnxt *bp)
2612 {
2613         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2614         uint32_t *reg_arr;
2615         int rc, i;
2616
2617         reg_arr = ptp->rx_regs;
2618         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2619         if (rc)
2620                 return rc;
2621
2622         reg_arr = ptp->tx_regs;
2623         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2624         if (rc)
2625                 return rc;
2626
2627         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2628                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2629
2630         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2631                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2632
2633         return 0;
2634 }
2635
2636 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2637 {
2638         rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +
2639                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16));
2640         rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +
2641                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20));
2642 }
2643
2644 static uint64_t bnxt_cc_read(struct bnxt *bp)
2645 {
2646         uint64_t ns;
2647
2648         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2649                               BNXT_GRCPF_REG_SYNC_TIME));
2650         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2651                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2652         return ns;
2653 }
2654
2655 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2656 {
2657         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2658         uint32_t fifo;
2659
2660         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2661                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2662         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2663                 return -EAGAIN;
2664
2665         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2666                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2667         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2668                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2669         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2670                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2671
2672         return 0;
2673 }
2674
2675 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2676 {
2677         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2678         struct bnxt_pf_info *pf = &bp->pf;
2679         uint16_t port_id;
2680         uint32_t fifo;
2681
2682         if (!ptp)
2683                 return -ENODEV;
2684
2685         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2686                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2687         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2688                 return -EAGAIN;
2689
2690         port_id = pf->port_id;
2691         rte_cpu_to_le_32(rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2692                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]));
2693
2694         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2695                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2696         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
2697 /*              bnxt_clr_rx_ts(bp);       TBD  */
2698                 return -EBUSY;
2699         }
2700
2701         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2702                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
2703         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2704                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
2705
2706         return 0;
2707 }
2708
2709 static int
2710 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
2711 {
2712         uint64_t ns;
2713         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2714         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2715
2716         if (!ptp)
2717                 return 0;
2718
2719         ns = rte_timespec_to_ns(ts);
2720         /* Set the timecounters to a new value. */
2721         ptp->tc.nsec = ns;
2722
2723         return 0;
2724 }
2725
2726 static int
2727 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
2728 {
2729         uint64_t ns, systime_cycles;
2730         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2731         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2732
2733         if (!ptp)
2734                 return 0;
2735
2736         systime_cycles = bnxt_cc_read(bp);
2737         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
2738         *ts = rte_ns_to_timespec(ns);
2739
2740         return 0;
2741 }
2742 static int
2743 bnxt_timesync_enable(struct rte_eth_dev *dev)
2744 {
2745         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2746         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2747         uint32_t shift = 0;
2748
2749         if (!ptp)
2750                 return 0;
2751
2752         ptp->rx_filter = 1;
2753         ptp->tx_tstamp_en = 1;
2754         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
2755
2756         if (!bnxt_hwrm_ptp_cfg(bp))
2757                 bnxt_map_ptp_regs(bp);
2758
2759         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
2760         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2761         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2762
2763         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2764         ptp->tc.cc_shift = shift;
2765         ptp->tc.nsec_mask = (1ULL << shift) - 1;
2766
2767         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2768         ptp->rx_tstamp_tc.cc_shift = shift;
2769         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2770
2771         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2772         ptp->tx_tstamp_tc.cc_shift = shift;
2773         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2774
2775         return 0;
2776 }
2777
2778 static int
2779 bnxt_timesync_disable(struct rte_eth_dev *dev)
2780 {
2781         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2782         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2783
2784         if (!ptp)
2785                 return 0;
2786
2787         ptp->rx_filter = 0;
2788         ptp->tx_tstamp_en = 0;
2789         ptp->rxctl = 0;
2790
2791         bnxt_hwrm_ptp_cfg(bp);
2792
2793         bnxt_unmap_ptp_regs(bp);
2794
2795         return 0;
2796 }
2797
2798 static int
2799 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
2800                                  struct timespec *timestamp,
2801                                  uint32_t flags __rte_unused)
2802 {
2803         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2804         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2805         uint64_t rx_tstamp_cycles = 0;
2806         uint64_t ns;
2807
2808         if (!ptp)
2809                 return 0;
2810
2811         bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
2812         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
2813         *timestamp = rte_ns_to_timespec(ns);
2814         return  0;
2815 }
2816
2817 static int
2818 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
2819                                  struct timespec *timestamp)
2820 {
2821         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2822         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2823         uint64_t tx_tstamp_cycles = 0;
2824         uint64_t ns;
2825
2826         if (!ptp)
2827                 return 0;
2828
2829         bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
2830         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
2831         *timestamp = rte_ns_to_timespec(ns);
2832
2833         return 0;
2834 }
2835
2836 static int
2837 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
2838 {
2839         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2840         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2841
2842         if (!ptp)
2843                 return 0;
2844
2845         ptp->tc.nsec += delta;
2846
2847         return 0;
2848 }
2849
2850 static int
2851 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
2852 {
2853         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2854         int rc;
2855         uint32_t dir_entries;
2856         uint32_t entry_length;
2857
2858         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
2859                 bp->pdev->addr.domain, bp->pdev->addr.bus,
2860                 bp->pdev->addr.devid, bp->pdev->addr.function);
2861
2862         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
2863         if (rc != 0)
2864                 return rc;
2865
2866         return dir_entries * entry_length;
2867 }
2868
2869 static int
2870 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
2871                 struct rte_dev_eeprom_info *in_eeprom)
2872 {
2873         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2874         uint32_t index;
2875         uint32_t offset;
2876
2877         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
2878                 "len = %d\n", bp->pdev->addr.domain,
2879                 bp->pdev->addr.bus, bp->pdev->addr.devid,
2880                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2881
2882         if (in_eeprom->offset == 0) /* special offset value to get directory */
2883                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
2884                                                 in_eeprom->data);
2885
2886         index = in_eeprom->offset >> 24;
2887         offset = in_eeprom->offset & 0xffffff;
2888
2889         if (index != 0)
2890                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
2891                                            in_eeprom->length, in_eeprom->data);
2892
2893         return 0;
2894 }
2895
2896 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
2897 {
2898         switch (dir_type) {
2899         case BNX_DIR_TYPE_CHIMP_PATCH:
2900         case BNX_DIR_TYPE_BOOTCODE:
2901         case BNX_DIR_TYPE_BOOTCODE_2:
2902         case BNX_DIR_TYPE_APE_FW:
2903         case BNX_DIR_TYPE_APE_PATCH:
2904         case BNX_DIR_TYPE_KONG_FW:
2905         case BNX_DIR_TYPE_KONG_PATCH:
2906         case BNX_DIR_TYPE_BONO_FW:
2907         case BNX_DIR_TYPE_BONO_PATCH:
2908                 return true;
2909         }
2910
2911         return false;
2912 }
2913
2914 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
2915 {
2916         switch (dir_type) {
2917         case BNX_DIR_TYPE_AVS:
2918         case BNX_DIR_TYPE_EXP_ROM_MBA:
2919         case BNX_DIR_TYPE_PCIE:
2920         case BNX_DIR_TYPE_TSCF_UCODE:
2921         case BNX_DIR_TYPE_EXT_PHY:
2922         case BNX_DIR_TYPE_CCM:
2923         case BNX_DIR_TYPE_ISCSI_BOOT:
2924         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
2925         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
2926                 return true;
2927         }
2928
2929         return false;
2930 }
2931
2932 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
2933 {
2934         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
2935                 bnxt_dir_type_is_other_exec_format(dir_type);
2936 }
2937
2938 static int
2939 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
2940                 struct rte_dev_eeprom_info *in_eeprom)
2941 {
2942         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2943         uint8_t index, dir_op;
2944         uint16_t type, ext, ordinal, attr;
2945
2946         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
2947                 "len = %d\n", bp->pdev->addr.domain,
2948                 bp->pdev->addr.bus, bp->pdev->addr.devid,
2949                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2950
2951         if (!BNXT_PF(bp)) {
2952                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
2953                 return -EINVAL;
2954         }
2955
2956         type = in_eeprom->magic >> 16;
2957
2958         if (type == 0xffff) { /* special value for directory operations */
2959                 index = in_eeprom->magic & 0xff;
2960                 dir_op = in_eeprom->magic >> 8;
2961                 if (index == 0)
2962                         return -EINVAL;
2963                 switch (dir_op) {
2964                 case 0x0e: /* erase */
2965                         if (in_eeprom->offset != ~in_eeprom->magic)
2966                                 return -EINVAL;
2967                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
2968                 default:
2969                         return -EINVAL;
2970                 }
2971         }
2972
2973         /* Create or re-write an NVM item: */
2974         if (bnxt_dir_type_is_executable(type) == true)
2975                 return -EOPNOTSUPP;
2976         ext = in_eeprom->magic & 0xffff;
2977         ordinal = in_eeprom->offset >> 16;
2978         attr = in_eeprom->offset & 0xffff;
2979
2980         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
2981                                      in_eeprom->data, in_eeprom->length);
2982         return 0;
2983 }
2984
2985 /*
2986  * Initialization
2987  */
2988
2989 static const struct eth_dev_ops bnxt_dev_ops = {
2990         .dev_infos_get = bnxt_dev_info_get_op,
2991         .dev_close = bnxt_dev_close_op,
2992         .dev_configure = bnxt_dev_configure_op,
2993         .dev_start = bnxt_dev_start_op,
2994         .dev_stop = bnxt_dev_stop_op,
2995         .dev_set_link_up = bnxt_dev_set_link_up_op,
2996         .dev_set_link_down = bnxt_dev_set_link_down_op,
2997         .stats_get = bnxt_stats_get_op,
2998         .stats_reset = bnxt_stats_reset_op,
2999         .rx_queue_setup = bnxt_rx_queue_setup_op,
3000         .rx_queue_release = bnxt_rx_queue_release_op,
3001         .tx_queue_setup = bnxt_tx_queue_setup_op,
3002         .tx_queue_release = bnxt_tx_queue_release_op,
3003         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3004         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3005         .reta_update = bnxt_reta_update_op,
3006         .reta_query = bnxt_reta_query_op,
3007         .rss_hash_update = bnxt_rss_hash_update_op,
3008         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3009         .link_update = bnxt_link_update_op,
3010         .promiscuous_enable = bnxt_promiscuous_enable_op,
3011         .promiscuous_disable = bnxt_promiscuous_disable_op,
3012         .allmulticast_enable = bnxt_allmulticast_enable_op,
3013         .allmulticast_disable = bnxt_allmulticast_disable_op,
3014         .mac_addr_add = bnxt_mac_addr_add_op,
3015         .mac_addr_remove = bnxt_mac_addr_remove_op,
3016         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3017         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3018         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3019         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3020         .vlan_filter_set = bnxt_vlan_filter_set_op,
3021         .vlan_offload_set = bnxt_vlan_offload_set_op,
3022         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3023         .mtu_set = bnxt_mtu_set_op,
3024         .mac_addr_set = bnxt_set_default_mac_addr_op,
3025         .xstats_get = bnxt_dev_xstats_get_op,
3026         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3027         .xstats_reset = bnxt_dev_xstats_reset_op,
3028         .fw_version_get = bnxt_fw_version_get,
3029         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3030         .rxq_info_get = bnxt_rxq_info_get_op,
3031         .txq_info_get = bnxt_txq_info_get_op,
3032         .dev_led_on = bnxt_dev_led_on_op,
3033         .dev_led_off = bnxt_dev_led_off_op,
3034         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3035         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3036         .rx_queue_count = bnxt_rx_queue_count_op,
3037         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3038         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3039         .rx_queue_start = bnxt_rx_queue_start,
3040         .rx_queue_stop = bnxt_rx_queue_stop,
3041         .tx_queue_start = bnxt_tx_queue_start,
3042         .tx_queue_stop = bnxt_tx_queue_stop,
3043         .filter_ctrl = bnxt_filter_ctrl_op,
3044         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3045         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3046         .get_eeprom           = bnxt_get_eeprom_op,
3047         .set_eeprom           = bnxt_set_eeprom_op,
3048         .timesync_enable      = bnxt_timesync_enable,
3049         .timesync_disable     = bnxt_timesync_disable,
3050         .timesync_read_time   = bnxt_timesync_read_time,
3051         .timesync_write_time   = bnxt_timesync_write_time,
3052         .timesync_adjust_time = bnxt_timesync_adjust_time,
3053         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3054         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3055 };
3056
3057 static bool bnxt_vf_pciid(uint16_t id)
3058 {
3059         if (id == BROADCOM_DEV_ID_57304_VF ||
3060             id == BROADCOM_DEV_ID_57406_VF ||
3061             id == BROADCOM_DEV_ID_5731X_VF ||
3062             id == BROADCOM_DEV_ID_5741X_VF ||
3063             id == BROADCOM_DEV_ID_57414_VF ||
3064             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3065             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3066                 return true;
3067         return false;
3068 }
3069
3070 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3071 {
3072         struct bnxt *bp = eth_dev->data->dev_private;
3073         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3074         int rc;
3075
3076         /* enable device (incl. PCI PM wakeup), and bus-mastering */
3077         if (!pci_dev->mem_resource[0].addr) {
3078                 PMD_DRV_LOG(ERR,
3079                         "Cannot find PCI device base address, aborting\n");
3080                 rc = -ENODEV;
3081                 goto init_err_disable;
3082         }
3083
3084         bp->eth_dev = eth_dev;
3085         bp->pdev = pci_dev;
3086
3087         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3088         if (!bp->bar0) {
3089                 PMD_DRV_LOG(ERR, "Cannot map device registers, aborting\n");
3090                 rc = -ENOMEM;
3091                 goto init_err_release;
3092         }
3093
3094         if (!pci_dev->mem_resource[2].addr) {
3095                 PMD_DRV_LOG(ERR,
3096                             "Cannot find PCI device BAR 2 address, aborting\n");
3097                 rc = -ENODEV;
3098                 goto init_err_release;
3099         } else {
3100                 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3101         }
3102
3103         return 0;
3104
3105 init_err_release:
3106         if (bp->bar0)
3107                 bp->bar0 = NULL;
3108         if (bp->doorbell_base)
3109                 bp->doorbell_base = NULL;
3110
3111 init_err_disable:
3112
3113         return rc;
3114 }
3115
3116 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
3117
3118 #define ALLOW_FUNC(x)   \
3119         { \
3120                 typeof(x) arg = (x); \
3121                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3122                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3123         }
3124 static int
3125 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3126 {
3127         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3128         char mz_name[RTE_MEMZONE_NAMESIZE];
3129         const struct rte_memzone *mz = NULL;
3130         static int version_printed;
3131         uint32_t total_alloc_len;
3132         rte_iova_t mz_phys_addr;
3133         struct bnxt *bp;
3134         int rc;
3135
3136         if (version_printed++ == 0)
3137                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
3138
3139         rte_eth_copy_pci_info(eth_dev, pci_dev);
3140
3141         bp = eth_dev->data->dev_private;
3142
3143         bp->dev_stopped = 1;
3144
3145         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3146                 goto skip_init;
3147
3148         if (bnxt_vf_pciid(pci_dev->id.device_id))
3149                 bp->flags |= BNXT_FLAG_VF;
3150
3151         rc = bnxt_init_board(eth_dev);
3152         if (rc) {
3153                 PMD_DRV_LOG(ERR,
3154                         "Board initialization failed rc: %x\n", rc);
3155                 goto error;
3156         }
3157 skip_init:
3158         eth_dev->dev_ops = &bnxt_dev_ops;
3159         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3160                 return 0;
3161         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3162         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3163
3164         if (BNXT_PF(bp) && pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) {
3165                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3166                          "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3167                          pci_dev->addr.bus, pci_dev->addr.devid,
3168                          pci_dev->addr.function, "rx_port_stats");
3169                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3170                 mz = rte_memzone_lookup(mz_name);
3171                 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3172                                 sizeof(struct rx_port_stats) + 512);
3173                 if (!mz) {
3174                         mz = rte_memzone_reserve(mz_name, total_alloc_len,
3175                                         SOCKET_ID_ANY,
3176                                         RTE_MEMZONE_2MB |
3177                                         RTE_MEMZONE_SIZE_HINT_ONLY |
3178                                         RTE_MEMZONE_IOVA_CONTIG);
3179                         if (mz == NULL)
3180                                 return -ENOMEM;
3181                 }
3182                 memset(mz->addr, 0, mz->len);
3183                 mz_phys_addr = mz->iova;
3184                 if ((unsigned long)mz->addr == mz_phys_addr) {
3185                         PMD_DRV_LOG(WARNING,
3186                                 "Memzone physical address same as virtual.\n");
3187                         PMD_DRV_LOG(WARNING,
3188                                 "Using rte_mem_virt2iova()\n");
3189                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3190                         if (mz_phys_addr == 0) {
3191                                 PMD_DRV_LOG(ERR,
3192                                 "unable to map address to physical memory\n");
3193                                 return -ENOMEM;
3194                         }
3195                 }
3196
3197                 bp->rx_mem_zone = (const void *)mz;
3198                 bp->hw_rx_port_stats = mz->addr;
3199                 bp->hw_rx_port_stats_map = mz_phys_addr;
3200
3201                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3202                          "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3203                          pci_dev->addr.bus, pci_dev->addr.devid,
3204                          pci_dev->addr.function, "tx_port_stats");
3205                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3206                 mz = rte_memzone_lookup(mz_name);
3207                 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3208                                 sizeof(struct tx_port_stats) + 512);
3209                 if (!mz) {
3210                         mz = rte_memzone_reserve(mz_name,
3211                                         total_alloc_len,
3212                                         SOCKET_ID_ANY,
3213                                         RTE_MEMZONE_2MB |
3214                                         RTE_MEMZONE_SIZE_HINT_ONLY |
3215                                         RTE_MEMZONE_IOVA_CONTIG);
3216                         if (mz == NULL)
3217                                 return -ENOMEM;
3218                 }
3219                 memset(mz->addr, 0, mz->len);
3220                 mz_phys_addr = mz->iova;
3221                 if ((unsigned long)mz->addr == mz_phys_addr) {
3222                         PMD_DRV_LOG(WARNING,
3223                                 "Memzone physical address same as virtual.\n");
3224                         PMD_DRV_LOG(WARNING,
3225                                 "Using rte_mem_virt2iova()\n");
3226                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3227                         if (mz_phys_addr == 0) {
3228                                 PMD_DRV_LOG(ERR,
3229                                 "unable to map address to physical memory\n");
3230                                 return -ENOMEM;
3231                         }
3232                 }
3233
3234                 bp->tx_mem_zone = (const void *)mz;
3235                 bp->hw_tx_port_stats = mz->addr;
3236                 bp->hw_tx_port_stats_map = mz_phys_addr;
3237
3238                 bp->flags |= BNXT_FLAG_PORT_STATS;
3239         }
3240
3241         rc = bnxt_alloc_hwrm_resources(bp);
3242         if (rc) {
3243                 PMD_DRV_LOG(ERR,
3244                         "hwrm resource allocation failure rc: %x\n", rc);
3245                 goto error_free;
3246         }
3247         rc = bnxt_hwrm_ver_get(bp);
3248         if (rc)
3249                 goto error_free;
3250         rc = bnxt_hwrm_queue_qportcfg(bp);
3251         if (rc) {
3252                 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n");
3253                 goto error_free;
3254         }
3255
3256         rc = bnxt_hwrm_func_qcfg(bp);
3257         if (rc) {
3258                 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n");
3259                 goto error_free;
3260         }
3261
3262         /* Get the MAX capabilities for this function */
3263         rc = bnxt_hwrm_func_qcaps(bp);
3264         if (rc) {
3265                 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc);
3266                 goto error_free;
3267         }
3268         if (bp->max_tx_rings == 0) {
3269                 PMD_DRV_LOG(ERR, "No TX rings available!\n");
3270                 rc = -EBUSY;
3271                 goto error_free;
3272         }
3273         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3274                                         ETHER_ADDR_LEN * bp->max_l2_ctx, 0);
3275         if (eth_dev->data->mac_addrs == NULL) {
3276                 PMD_DRV_LOG(ERR,
3277                         "Failed to alloc %u bytes needed to store MAC addr tbl",
3278                         ETHER_ADDR_LEN * bp->max_l2_ctx);
3279                 rc = -ENOMEM;
3280                 goto error_free;
3281         }
3282
3283         if (check_zero_bytes(bp->dflt_mac_addr, ETHER_ADDR_LEN)) {
3284                 PMD_DRV_LOG(ERR,
3285                             "Invalid MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
3286                             bp->dflt_mac_addr[0], bp->dflt_mac_addr[1],
3287                             bp->dflt_mac_addr[2], bp->dflt_mac_addr[3],
3288                             bp->dflt_mac_addr[4], bp->dflt_mac_addr[5]);
3289                 rc = -EINVAL;
3290                 goto error_free;
3291         }
3292         /* Copy the permanent MAC from the qcap response address now. */
3293         memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr));
3294         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
3295
3296         if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3297                 /* 1 ring is for default completion ring */
3298                 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
3299                 rc = -ENOSPC;
3300                 goto error_free;
3301         }
3302
3303         bp->grp_info = rte_zmalloc("bnxt_grp_info",
3304                                 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
3305         if (!bp->grp_info) {
3306                 PMD_DRV_LOG(ERR,
3307                         "Failed to alloc %zu bytes to store group info table\n",
3308                         sizeof(*bp->grp_info) * bp->max_ring_grps);
3309                 rc = -ENOMEM;
3310                 goto error_free;
3311         }
3312
3313         /* Forward all requests if firmware is new enough */
3314         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3315             (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3316             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3317                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3318         } else {
3319                 PMD_DRV_LOG(WARNING,
3320                         "Firmware too old for VF mailbox functionality\n");
3321                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3322         }
3323
3324         /*
3325          * The following are used for driver cleanup.  If we disallow these,
3326          * VF drivers can't clean up cleanly.
3327          */
3328         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3329         ALLOW_FUNC(HWRM_VNIC_FREE);
3330         ALLOW_FUNC(HWRM_RING_FREE);
3331         ALLOW_FUNC(HWRM_RING_GRP_FREE);
3332         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3333         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3334         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3335         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3336         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3337         rc = bnxt_hwrm_func_driver_register(bp);
3338         if (rc) {
3339                 PMD_DRV_LOG(ERR,
3340                         "Failed to register driver");
3341                 rc = -EBUSY;
3342                 goto error_free;
3343         }
3344
3345         PMD_DRV_LOG(INFO,
3346                 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3347                 pci_dev->mem_resource[0].phys_addr,
3348                 pci_dev->mem_resource[0].addr);
3349
3350         rc = bnxt_hwrm_func_reset(bp);
3351         if (rc) {
3352                 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc);
3353                 rc = -EIO;
3354                 goto error_free;
3355         }
3356
3357         if (BNXT_PF(bp)) {
3358                 //if (bp->pf.active_vfs) {
3359                         // TODO: Deallocate VF resources?
3360                 //}
3361                 if (bp->pdev->max_vfs) {
3362                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
3363                         if (rc) {
3364                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
3365                                 goto error_free;
3366                         }
3367                 } else {
3368                         rc = bnxt_hwrm_allocate_pf_only(bp);
3369                         if (rc) {
3370                                 PMD_DRV_LOG(ERR,
3371                                         "Failed to allocate PF resources\n");
3372                                 goto error_free;
3373                         }
3374                 }
3375         }
3376
3377         bnxt_hwrm_port_led_qcaps(bp);
3378
3379         rc = bnxt_setup_int(bp);
3380         if (rc)
3381                 goto error_free;
3382
3383         rc = bnxt_alloc_mem(bp);
3384         if (rc)
3385                 goto error_free_int;
3386
3387         rc = bnxt_request_int(bp);
3388         if (rc)
3389                 goto error_free_int;
3390
3391         rc = bnxt_alloc_def_cp_ring(bp);
3392         if (rc)
3393                 goto error_free_int;
3394
3395         bnxt_enable_int(bp);
3396         bnxt_init_nic(bp);
3397
3398         return 0;
3399
3400 error_free_int:
3401         bnxt_disable_int(bp);
3402         bnxt_free_def_cp_ring(bp);
3403         bnxt_hwrm_func_buf_unrgtr(bp);
3404         bnxt_free_int(bp);
3405         bnxt_free_mem(bp);
3406 error_free:
3407         bnxt_dev_uninit(eth_dev);
3408 error:
3409         return rc;
3410 }
3411
3412 static int
3413 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) {
3414         struct bnxt *bp = eth_dev->data->dev_private;
3415         int rc;
3416
3417         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3418                 return -EPERM;
3419
3420         bnxt_disable_int(bp);
3421         bnxt_free_int(bp);
3422         bnxt_free_mem(bp);
3423         if (eth_dev->data->mac_addrs != NULL) {
3424                 rte_free(eth_dev->data->mac_addrs);
3425                 eth_dev->data->mac_addrs = NULL;
3426         }
3427         if (bp->grp_info != NULL) {
3428                 rte_free(bp->grp_info);
3429                 bp->grp_info = NULL;
3430         }
3431         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
3432         bnxt_free_hwrm_resources(bp);
3433         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
3434         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
3435         if (bp->dev_stopped == 0)
3436                 bnxt_dev_close_op(eth_dev);
3437         if (bp->pf.vf_info)
3438                 rte_free(bp->pf.vf_info);
3439         eth_dev->dev_ops = NULL;
3440         eth_dev->rx_pkt_burst = NULL;
3441         eth_dev->tx_pkt_burst = NULL;
3442
3443         return rc;
3444 }
3445
3446 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3447         struct rte_pci_device *pci_dev)
3448 {
3449         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
3450                 bnxt_dev_init);
3451 }
3452
3453 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
3454 {
3455         return rte_eth_dev_pci_generic_remove(pci_dev, bnxt_dev_uninit);
3456 }
3457
3458 static struct rte_pci_driver bnxt_rte_pmd = {
3459         .id_table = bnxt_pci_id_map,
3460         .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
3461                 RTE_PCI_DRV_INTR_LSC,
3462         .probe = bnxt_pci_probe,
3463         .remove = bnxt_pci_remove,
3464 };
3465
3466 static bool
3467 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
3468 {
3469         if (strcmp(dev->device->driver->name, drv->driver.name))
3470                 return false;
3471
3472         return true;
3473 }
3474
3475 bool is_bnxt_supported(struct rte_eth_dev *dev)
3476 {
3477         return is_device_supported(dev, &bnxt_rte_pmd);
3478 }
3479
3480 RTE_INIT(bnxt_init_log);
3481 static void
3482 bnxt_init_log(void)
3483 {
3484         bnxt_logtype_driver = rte_log_register("pmd.bnxt.driver");
3485         if (bnxt_logtype_driver >= 0)
3486                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_INFO);
3487 }
3488
3489 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
3490 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
3491 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");