1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
15 #include <rte_kvargs.h>
18 #include "bnxt_filter.h"
19 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_stats.h"
27 #include "bnxt_vnic.h"
28 #include "hsi_struct_def_dpdk.h"
29 #include "bnxt_nvm_defs.h"
31 #define DRV_MODULE_NAME "bnxt"
32 static const char bnxt_version[] =
33 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
34 int bnxt_logtype_driver;
37 * The set of PCI devices this driver supports
39 static const struct rte_pci_id bnxt_pci_id_map[] = {
40 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
41 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
42 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
43 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
45 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
47 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
93 { .vendor_id = 0, /* sentinel */ },
96 #define BNXT_ETH_RSS_SUPPORT ( \
98 ETH_RSS_NONFRAG_IPV4_TCP | \
99 ETH_RSS_NONFRAG_IPV4_UDP | \
101 ETH_RSS_NONFRAG_IPV6_TCP | \
102 ETH_RSS_NONFRAG_IPV6_UDP)
104 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
105 DEV_TX_OFFLOAD_IPV4_CKSUM | \
106 DEV_TX_OFFLOAD_TCP_CKSUM | \
107 DEV_TX_OFFLOAD_UDP_CKSUM | \
108 DEV_TX_OFFLOAD_TCP_TSO | \
109 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
110 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
111 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
112 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
113 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
114 DEV_TX_OFFLOAD_QINQ_INSERT | \
115 DEV_TX_OFFLOAD_MULTI_SEGS)
117 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
118 DEV_RX_OFFLOAD_VLAN_STRIP | \
119 DEV_RX_OFFLOAD_IPV4_CKSUM | \
120 DEV_RX_OFFLOAD_UDP_CKSUM | \
121 DEV_RX_OFFLOAD_TCP_CKSUM | \
122 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
123 DEV_RX_OFFLOAD_JUMBO_FRAME | \
124 DEV_RX_OFFLOAD_KEEP_CRC | \
125 DEV_RX_OFFLOAD_VLAN_EXTEND | \
126 DEV_RX_OFFLOAD_TCP_LRO | \
127 DEV_RX_OFFLOAD_SCATTER | \
128 DEV_RX_OFFLOAD_RSS_HASH)
130 #define BNXT_DEVARG_TRUFLOW "host-based-truflow"
131 static const char *const bnxt_dev_args[] = {
137 * truflow == false to disable the feature
138 * truflow == true to enable the feature
140 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1)
142 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
143 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
144 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
145 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
146 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
147 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
148 static int bnxt_restore_vlan_filters(struct bnxt *bp);
149 static void bnxt_dev_recover(void *arg);
151 int is_bnxt_in_error(struct bnxt *bp)
153 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
155 if (bp->flags & BNXT_FLAG_FW_RESET)
161 /***********************/
164 * High level utility functions
167 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
169 if (!BNXT_CHIP_THOR(bp))
172 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
173 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
174 BNXT_RSS_ENTRIES_PER_CTX_THOR;
177 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
179 if (!BNXT_CHIP_THOR(bp))
180 return HW_HASH_INDEX_SIZE;
182 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
185 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
187 bnxt_free_filter_mem(bp);
188 bnxt_free_vnic_attributes(bp);
189 bnxt_free_vnic_mem(bp);
191 /* tx/rx rings are configured as part of *_queue_setup callbacks.
192 * If the number of rings change across fw update,
193 * we don't have much choice except to warn the user.
197 bnxt_free_tx_rings(bp);
198 bnxt_free_rx_rings(bp);
200 bnxt_free_async_cp_ring(bp);
201 bnxt_free_rxtx_nq_ring(bp);
203 rte_free(bp->grp_info);
207 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
211 rc = bnxt_alloc_ring_grps(bp);
215 rc = bnxt_alloc_async_ring_struct(bp);
219 rc = bnxt_alloc_vnic_mem(bp);
223 rc = bnxt_alloc_vnic_attributes(bp);
227 rc = bnxt_alloc_filter_mem(bp);
231 rc = bnxt_alloc_async_cp_ring(bp);
235 rc = bnxt_alloc_rxtx_nq_ring(bp);
242 bnxt_free_mem(bp, reconfig);
246 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
248 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
249 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
250 uint64_t rx_offloads = dev_conf->rxmode.offloads;
251 struct bnxt_rx_queue *rxq;
255 rc = bnxt_vnic_grp_alloc(bp, vnic);
259 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
260 vnic_id, vnic, vnic->fw_grp_ids);
262 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
266 /* Alloc RSS context only if RSS mode is enabled */
267 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
268 int j, nr_ctxs = bnxt_rss_ctxts(bp);
271 for (j = 0; j < nr_ctxs; j++) {
272 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
278 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
282 vnic->num_lb_ctxts = nr_ctxs;
286 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
287 * setting is not available at this time, it will not be
288 * configured correctly in the CFA.
290 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
291 vnic->vlan_strip = true;
293 vnic->vlan_strip = false;
295 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
299 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
303 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
304 rxq = bp->eth_dev->data->rx_queues[j];
307 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
308 j, rxq->vnic, rxq->vnic->fw_grp_ids);
310 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
311 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
313 vnic->rx_queue_cnt++;
316 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
318 rc = bnxt_vnic_rss_configure(bp, vnic);
322 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
324 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
325 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
327 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
331 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
336 static int bnxt_init_chip(struct bnxt *bp)
338 struct rte_eth_link new;
339 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
340 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
341 uint32_t intr_vector = 0;
342 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
343 uint32_t vec = BNXT_MISC_VEC_ID;
347 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
348 bp->eth_dev->data->dev_conf.rxmode.offloads |=
349 DEV_RX_OFFLOAD_JUMBO_FRAME;
350 bp->flags |= BNXT_FLAG_JUMBO;
352 bp->eth_dev->data->dev_conf.rxmode.offloads &=
353 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
354 bp->flags &= ~BNXT_FLAG_JUMBO;
357 /* THOR does not support ring groups.
358 * But we will use the array to save RSS context IDs.
360 if (BNXT_CHIP_THOR(bp))
361 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
363 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
365 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
369 rc = bnxt_alloc_hwrm_rings(bp);
371 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
375 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
377 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
381 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
384 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
385 if (bp->rx_cos_queue[i].id != 0xff) {
386 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
390 "Num pools more than FW profile\n");
394 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
400 rc = bnxt_mq_rx_configure(bp);
402 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
406 /* VNIC configuration */
407 for (i = 0; i < bp->nr_vnics; i++) {
408 rc = bnxt_setup_one_vnic(bp, i);
413 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
416 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
420 /* check and configure queue intr-vector mapping */
421 if ((rte_intr_cap_multiple(intr_handle) ||
422 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
423 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
424 intr_vector = bp->eth_dev->data->nb_rx_queues;
425 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
426 if (intr_vector > bp->rx_cp_nr_rings) {
427 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
431 rc = rte_intr_efd_enable(intr_handle, intr_vector);
436 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
437 intr_handle->intr_vec =
438 rte_zmalloc("intr_vec",
439 bp->eth_dev->data->nb_rx_queues *
441 if (intr_handle->intr_vec == NULL) {
442 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
443 " intr_vec", bp->eth_dev->data->nb_rx_queues);
447 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
448 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
449 intr_handle->intr_vec, intr_handle->nb_efd,
450 intr_handle->max_intr);
451 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
453 intr_handle->intr_vec[queue_id] =
454 vec + BNXT_RX_VEC_START;
455 if (vec < base + intr_handle->nb_efd - 1)
460 /* enable uio/vfio intr/eventfd mapping */
461 rc = rte_intr_enable(intr_handle);
462 #ifndef RTE_EXEC_ENV_FREEBSD
463 /* In FreeBSD OS, nic_uio driver does not support interrupts */
468 rc = bnxt_get_hwrm_link_config(bp, &new);
470 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
474 if (!bp->link_info.link_up) {
475 rc = bnxt_set_hwrm_link_config(bp, true);
478 "HWRM link config failure rc: %x\n", rc);
482 bnxt_print_link_info(bp->eth_dev);
484 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
486 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
491 rte_free(intr_handle->intr_vec);
493 rte_intr_efd_disable(intr_handle);
495 /* Some of the error status returned by FW may not be from errno.h */
502 static int bnxt_shutdown_nic(struct bnxt *bp)
504 bnxt_free_all_hwrm_resources(bp);
505 bnxt_free_all_filters(bp);
506 bnxt_free_all_vnics(bp);
511 * Device configuration and status function
514 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
515 struct rte_eth_dev_info *dev_info)
517 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
518 struct bnxt *bp = eth_dev->data->dev_private;
519 uint16_t max_vnics, i, j, vpool, vrxq;
520 unsigned int max_rx_rings;
523 rc = is_bnxt_in_error(bp);
528 dev_info->max_mac_addrs = bp->max_l2_ctx;
529 dev_info->max_hash_mac_addrs = 0;
531 /* PF/VF specifics */
533 dev_info->max_vfs = pdev->max_vfs;
535 max_rx_rings = BNXT_MAX_RINGS(bp);
536 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
537 dev_info->max_rx_queues = max_rx_rings;
538 dev_info->max_tx_queues = max_rx_rings;
539 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
540 dev_info->hash_key_size = 40;
541 max_vnics = bp->max_vnics;
544 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
545 dev_info->max_mtu = BNXT_MAX_MTU;
547 /* Fast path specifics */
548 dev_info->min_rx_bufsize = 1;
549 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
551 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
552 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
553 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
554 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
555 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
558 dev_info->default_rxconf = (struct rte_eth_rxconf) {
564 .rx_free_thresh = 32,
565 /* If no descriptors available, pkts are dropped by default */
569 dev_info->default_txconf = (struct rte_eth_txconf) {
575 .tx_free_thresh = 32,
578 eth_dev->data->dev_conf.intr_conf.lsc = 1;
580 eth_dev->data->dev_conf.intr_conf.rxq = 1;
581 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
582 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
583 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
584 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
589 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
590 * need further investigation.
594 vpool = 64; /* ETH_64_POOLS */
595 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
596 for (i = 0; i < 4; vpool >>= 1, i++) {
597 if (max_vnics > vpool) {
598 for (j = 0; j < 5; vrxq >>= 1, j++) {
599 if (dev_info->max_rx_queues > vrxq) {
605 /* Not enough resources to support VMDq */
609 /* Not enough resources to support VMDq */
613 dev_info->max_vmdq_pools = vpool;
614 dev_info->vmdq_queue_num = vrxq;
616 dev_info->vmdq_pool_base = 0;
617 dev_info->vmdq_queue_base = 0;
622 /* Configure the device based on the configuration provided */
623 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
625 struct bnxt *bp = eth_dev->data->dev_private;
626 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
629 bp->rx_queues = (void *)eth_dev->data->rx_queues;
630 bp->tx_queues = (void *)eth_dev->data->tx_queues;
631 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
632 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
634 rc = is_bnxt_in_error(bp);
638 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
639 rc = bnxt_hwrm_check_vf_rings(bp);
641 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
645 /* If a resource has already been allocated - in this case
646 * it is the async completion ring, free it. Reallocate it after
647 * resource reservation. This will ensure the resource counts
648 * are calculated correctly.
651 pthread_mutex_lock(&bp->def_cp_lock);
653 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
654 bnxt_disable_int(bp);
655 bnxt_free_cp_ring(bp, bp->async_cp_ring);
658 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
660 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
661 pthread_mutex_unlock(&bp->def_cp_lock);
665 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
666 rc = bnxt_alloc_async_cp_ring(bp);
668 pthread_mutex_unlock(&bp->def_cp_lock);
674 pthread_mutex_unlock(&bp->def_cp_lock);
676 /* legacy driver needs to get updated values */
677 rc = bnxt_hwrm_func_qcaps(bp);
679 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
684 /* Inherit new configurations */
685 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
686 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
687 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
688 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
689 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
693 if (BNXT_HAS_RING_GRPS(bp) &&
694 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
697 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
698 bp->max_vnics < eth_dev->data->nb_rx_queues)
701 bp->rx_cp_nr_rings = bp->rx_nr_rings;
702 bp->tx_cp_nr_rings = bp->tx_nr_rings;
704 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
705 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
706 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
708 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
710 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
711 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
713 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
719 "Insufficient resources to support requested config\n");
721 "Num Queues Requested: Tx %d, Rx %d\n",
722 eth_dev->data->nb_tx_queues,
723 eth_dev->data->nb_rx_queues);
725 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
726 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
727 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
731 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
733 struct rte_eth_link *link = ð_dev->data->dev_link;
735 if (link->link_status)
736 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
737 eth_dev->data->port_id,
738 (uint32_t)link->link_speed,
739 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
740 ("full-duplex") : ("half-duplex\n"));
742 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
743 eth_dev->data->port_id);
747 * Determine whether the current configuration requires support for scattered
748 * receive; return 1 if scattered receive is required and 0 if not.
750 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
755 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
758 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
759 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
761 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
762 RTE_PKTMBUF_HEADROOM);
763 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
769 static eth_rx_burst_t
770 bnxt_receive_function(struct rte_eth_dev *eth_dev)
772 struct bnxt *bp = eth_dev->data->dev_private;
775 #ifndef RTE_LIBRTE_IEEE1588
777 * Vector mode receive can be enabled only if scatter rx is not
778 * in use and rx offloads are limited to VLAN stripping and
781 if (!eth_dev->data->scattered_rx &&
782 !(eth_dev->data->dev_conf.rxmode.offloads &
783 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
784 DEV_RX_OFFLOAD_KEEP_CRC |
785 DEV_RX_OFFLOAD_JUMBO_FRAME |
786 DEV_RX_OFFLOAD_IPV4_CKSUM |
787 DEV_RX_OFFLOAD_UDP_CKSUM |
788 DEV_RX_OFFLOAD_TCP_CKSUM |
789 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
790 DEV_RX_OFFLOAD_RSS_HASH |
791 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
793 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
794 eth_dev->data->port_id);
795 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
796 return bnxt_recv_pkts_vec;
798 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
799 eth_dev->data->port_id);
801 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
802 eth_dev->data->port_id,
803 eth_dev->data->scattered_rx,
804 eth_dev->data->dev_conf.rxmode.offloads);
807 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
808 return bnxt_recv_pkts;
811 static eth_tx_burst_t
812 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
815 #ifndef RTE_LIBRTE_IEEE1588
817 * Vector mode transmit can be enabled only if not using scatter rx
820 if (!eth_dev->data->scattered_rx &&
821 !eth_dev->data->dev_conf.txmode.offloads) {
822 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
823 eth_dev->data->port_id);
824 return bnxt_xmit_pkts_vec;
826 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
827 eth_dev->data->port_id);
829 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
830 eth_dev->data->port_id,
831 eth_dev->data->scattered_rx,
832 eth_dev->data->dev_conf.txmode.offloads);
835 return bnxt_xmit_pkts;
838 static int bnxt_handle_if_change_status(struct bnxt *bp)
842 /* Since fw has undergone a reset and lost all contexts,
843 * set fatal flag to not issue hwrm during cleanup
845 bp->flags |= BNXT_FLAG_FATAL_ERROR;
846 bnxt_uninit_resources(bp, true);
848 /* clear fatal flag so that re-init happens */
849 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
850 rc = bnxt_init_resources(bp, true);
852 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
857 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
859 struct bnxt *bp = eth_dev->data->dev_private;
860 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
864 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
865 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
869 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
871 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
872 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
875 rc = bnxt_hwrm_if_change(bp, 1);
877 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
878 rc = bnxt_handle_if_change_status(bp);
885 rc = bnxt_init_chip(bp);
889 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
890 eth_dev->data->dev_started = 1;
892 bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
894 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
895 vlan_mask |= ETH_VLAN_FILTER_MASK;
896 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
897 vlan_mask |= ETH_VLAN_STRIP_MASK;
898 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
902 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
903 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
905 pthread_mutex_lock(&bp->def_cp_lock);
906 bnxt_schedule_fw_health_check(bp);
907 pthread_mutex_unlock(&bp->def_cp_lock);
915 bnxt_hwrm_if_change(bp, 0);
916 bnxt_shutdown_nic(bp);
917 bnxt_free_tx_mbufs(bp);
918 bnxt_free_rx_mbufs(bp);
919 eth_dev->data->dev_started = 0;
923 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
925 struct bnxt *bp = eth_dev->data->dev_private;
928 if (!bp->link_info.link_up)
929 rc = bnxt_set_hwrm_link_config(bp, true);
931 eth_dev->data->dev_link.link_status = 1;
933 bnxt_print_link_info(eth_dev);
937 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
939 struct bnxt *bp = eth_dev->data->dev_private;
941 eth_dev->data->dev_link.link_status = 0;
942 bnxt_set_hwrm_link_config(bp, false);
943 bp->link_info.link_up = 0;
948 /* Unload the driver, release resources */
949 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
951 struct bnxt *bp = eth_dev->data->dev_private;
952 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
953 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
958 eth_dev->data->dev_started = 0;
959 /* Prevent crashes when queues are still in use */
960 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
961 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
963 bnxt_disable_int(bp);
965 /* disable uio/vfio intr/eventfd mapping */
966 rte_intr_disable(intr_handle);
968 bnxt_cancel_fw_health_check(bp);
970 bnxt_dev_set_link_down_op(eth_dev);
972 /* Wait for link to be reset and the async notification to process.
973 * During reset recovery, there is no need to wait and
974 * VF/NPAR functions do not have privilege to change PHY config.
976 if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
977 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
979 /* Clean queue intr-vector mapping */
980 rte_intr_efd_disable(intr_handle);
981 if (intr_handle->intr_vec != NULL) {
982 rte_free(intr_handle->intr_vec);
983 intr_handle->intr_vec = NULL;
986 bnxt_hwrm_port_clr_stats(bp);
987 bnxt_free_tx_mbufs(bp);
988 bnxt_free_rx_mbufs(bp);
989 /* Process any remaining notifications in default completion queue */
990 bnxt_int_handler(eth_dev);
991 bnxt_shutdown_nic(bp);
992 bnxt_hwrm_if_change(bp, 0);
994 rte_free(bp->mark_table);
995 bp->mark_table = NULL;
997 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1001 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1003 struct bnxt *bp = eth_dev->data->dev_private;
1005 /* cancel the recovery handler before remove dev */
1006 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1007 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1009 if (eth_dev->data->dev_started)
1010 bnxt_dev_stop_op(eth_dev);
1012 bnxt_uninit_resources(bp, false);
1014 eth_dev->dev_ops = NULL;
1015 eth_dev->rx_pkt_burst = NULL;
1016 eth_dev->tx_pkt_burst = NULL;
1018 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1019 bp->tx_mem_zone = NULL;
1020 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1021 bp->rx_mem_zone = NULL;
1023 rte_free(bp->pf.vf_info);
1024 bp->pf.vf_info = NULL;
1026 rte_free(bp->grp_info);
1027 bp->grp_info = NULL;
1030 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1033 struct bnxt *bp = eth_dev->data->dev_private;
1034 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1035 struct bnxt_vnic_info *vnic;
1036 struct bnxt_filter_info *filter, *temp_filter;
1039 if (is_bnxt_in_error(bp))
1043 * Loop through all VNICs from the specified filter flow pools to
1044 * remove the corresponding MAC addr filter
1046 for (i = 0; i < bp->nr_vnics; i++) {
1047 if (!(pool_mask & (1ULL << i)))
1050 vnic = &bp->vnic_info[i];
1051 filter = STAILQ_FIRST(&vnic->filter);
1053 temp_filter = STAILQ_NEXT(filter, next);
1054 if (filter->mac_index == index) {
1055 STAILQ_REMOVE(&vnic->filter, filter,
1056 bnxt_filter_info, next);
1057 bnxt_hwrm_clear_l2_filter(bp, filter);
1058 bnxt_free_filter(bp, filter);
1060 filter = temp_filter;
1065 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1066 struct rte_ether_addr *mac_addr, uint32_t index,
1069 struct bnxt_filter_info *filter;
1072 /* Attach requested MAC address to the new l2_filter */
1073 STAILQ_FOREACH(filter, &vnic->filter, next) {
1074 if (filter->mac_index == index) {
1076 "MAC addr already existed for pool %d\n",
1082 filter = bnxt_alloc_filter(bp);
1084 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1088 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1089 * if the MAC that's been programmed now is a different one, then,
1090 * copy that addr to filter->l2_addr
1093 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1094 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1096 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1098 filter->mac_index = index;
1099 if (filter->mac_index == 0)
1100 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1102 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1104 bnxt_free_filter(bp, filter);
1110 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1111 struct rte_ether_addr *mac_addr,
1112 uint32_t index, uint32_t pool)
1114 struct bnxt *bp = eth_dev->data->dev_private;
1115 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1118 rc = is_bnxt_in_error(bp);
1122 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1123 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1128 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1132 /* Filter settings will get applied when port is started */
1133 if (!eth_dev->data->dev_started)
1136 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1141 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1142 bool exp_link_status)
1145 struct bnxt *bp = eth_dev->data->dev_private;
1146 struct rte_eth_link new;
1147 int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1148 BNXT_LINK_DOWN_WAIT_CNT;
1150 rc = is_bnxt_in_error(bp);
1154 memset(&new, 0, sizeof(new));
1156 /* Retrieve link info from hardware */
1157 rc = bnxt_get_hwrm_link_config(bp, &new);
1159 new.link_speed = ETH_LINK_SPEED_100M;
1160 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1162 "Failed to retrieve link rc = 0x%x!\n", rc);
1166 if (!wait_to_complete || new.link_status == exp_link_status)
1169 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1173 /* Timed out or success */
1174 if (new.link_status != eth_dev->data->dev_link.link_status ||
1175 new.link_speed != eth_dev->data->dev_link.link_speed) {
1176 rte_eth_linkstatus_set(eth_dev, &new);
1178 _rte_eth_dev_callback_process(eth_dev,
1179 RTE_ETH_EVENT_INTR_LSC,
1182 bnxt_print_link_info(eth_dev);
1188 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1189 int wait_to_complete)
1191 return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1194 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1196 struct bnxt *bp = eth_dev->data->dev_private;
1197 struct bnxt_vnic_info *vnic;
1201 rc = is_bnxt_in_error(bp);
1205 /* Filter settings will get applied when port is started */
1206 if (!eth_dev->data->dev_started)
1209 if (bp->vnic_info == NULL)
1212 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1214 old_flags = vnic->flags;
1215 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1216 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1218 vnic->flags = old_flags;
1223 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1225 struct bnxt *bp = eth_dev->data->dev_private;
1226 struct bnxt_vnic_info *vnic;
1230 rc = is_bnxt_in_error(bp);
1234 /* Filter settings will get applied when port is started */
1235 if (!eth_dev->data->dev_started)
1238 if (bp->vnic_info == NULL)
1241 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1243 old_flags = vnic->flags;
1244 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1245 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1247 vnic->flags = old_flags;
1252 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1254 struct bnxt *bp = eth_dev->data->dev_private;
1255 struct bnxt_vnic_info *vnic;
1259 rc = is_bnxt_in_error(bp);
1263 /* Filter settings will get applied when port is started */
1264 if (!eth_dev->data->dev_started)
1267 if (bp->vnic_info == NULL)
1270 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1272 old_flags = vnic->flags;
1273 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1274 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1276 vnic->flags = old_flags;
1281 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1283 struct bnxt *bp = eth_dev->data->dev_private;
1284 struct bnxt_vnic_info *vnic;
1288 rc = is_bnxt_in_error(bp);
1292 /* Filter settings will get applied when port is started */
1293 if (!eth_dev->data->dev_started)
1296 if (bp->vnic_info == NULL)
1299 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1301 old_flags = vnic->flags;
1302 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1303 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1305 vnic->flags = old_flags;
1310 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1311 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1313 if (qid >= bp->rx_nr_rings)
1316 return bp->eth_dev->data->rx_queues[qid];
1319 /* Return rxq corresponding to a given rss table ring/group ID. */
1320 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1322 struct bnxt_rx_queue *rxq;
1325 if (!BNXT_HAS_RING_GRPS(bp)) {
1326 for (i = 0; i < bp->rx_nr_rings; i++) {
1327 rxq = bp->eth_dev->data->rx_queues[i];
1328 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1332 for (i = 0; i < bp->rx_nr_rings; i++) {
1333 if (bp->grp_info[i].fw_grp_id == fwr)
1338 return INVALID_HW_RING_ID;
1341 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1342 struct rte_eth_rss_reta_entry64 *reta_conf,
1345 struct bnxt *bp = eth_dev->data->dev_private;
1346 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1347 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1348 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1352 rc = is_bnxt_in_error(bp);
1356 if (!vnic->rss_table)
1359 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1362 if (reta_size != tbl_size) {
1363 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1364 "(%d) must equal the size supported by the hardware "
1365 "(%d)\n", reta_size, tbl_size);
1369 for (i = 0; i < reta_size; i++) {
1370 struct bnxt_rx_queue *rxq;
1372 idx = i / RTE_RETA_GROUP_SIZE;
1373 sft = i % RTE_RETA_GROUP_SIZE;
1375 if (!(reta_conf[idx].mask & (1ULL << sft)))
1378 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1380 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1384 if (BNXT_CHIP_THOR(bp)) {
1385 vnic->rss_table[i * 2] =
1386 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1387 vnic->rss_table[i * 2 + 1] =
1388 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1390 vnic->rss_table[i] =
1391 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1395 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1399 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1400 struct rte_eth_rss_reta_entry64 *reta_conf,
1403 struct bnxt *bp = eth_dev->data->dev_private;
1404 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1405 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1406 uint16_t idx, sft, i;
1409 rc = is_bnxt_in_error(bp);
1413 /* Retrieve from the default VNIC */
1416 if (!vnic->rss_table)
1419 if (reta_size != tbl_size) {
1420 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1421 "(%d) must equal the size supported by the hardware "
1422 "(%d)\n", reta_size, tbl_size);
1426 for (idx = 0, i = 0; i < reta_size; i++) {
1427 idx = i / RTE_RETA_GROUP_SIZE;
1428 sft = i % RTE_RETA_GROUP_SIZE;
1430 if (reta_conf[idx].mask & (1ULL << sft)) {
1433 if (BNXT_CHIP_THOR(bp))
1434 qid = bnxt_rss_to_qid(bp,
1435 vnic->rss_table[i * 2]);
1437 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1439 if (qid == INVALID_HW_RING_ID) {
1440 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1443 reta_conf[idx].reta[sft] = qid;
1450 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1451 struct rte_eth_rss_conf *rss_conf)
1453 struct bnxt *bp = eth_dev->data->dev_private;
1454 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1455 struct bnxt_vnic_info *vnic;
1458 rc = is_bnxt_in_error(bp);
1463 * If RSS enablement were different than dev_configure,
1464 * then return -EINVAL
1466 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1467 if (!rss_conf->rss_hf)
1468 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1470 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1474 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1475 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1477 /* Update the default RSS VNIC(s) */
1478 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1479 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1482 * If hashkey is not specified, use the previously configured
1485 if (!rss_conf->rss_key)
1488 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1490 "Invalid hashkey length, should be 16 bytes\n");
1493 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1496 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1500 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1501 struct rte_eth_rss_conf *rss_conf)
1503 struct bnxt *bp = eth_dev->data->dev_private;
1504 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1506 uint32_t hash_types;
1508 rc = is_bnxt_in_error(bp);
1512 /* RSS configuration is the same for all VNICs */
1513 if (vnic && vnic->rss_hash_key) {
1514 if (rss_conf->rss_key) {
1515 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1516 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1517 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1520 hash_types = vnic->hash_type;
1521 rss_conf->rss_hf = 0;
1522 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1523 rss_conf->rss_hf |= ETH_RSS_IPV4;
1524 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1526 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1527 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1529 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1531 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1532 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1534 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1536 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1537 rss_conf->rss_hf |= ETH_RSS_IPV6;
1538 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1540 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1541 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1543 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1545 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1546 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1548 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1552 "Unknwon RSS config from firmware (%08x), RSS disabled",
1557 rss_conf->rss_hf = 0;
1562 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1563 struct rte_eth_fc_conf *fc_conf)
1565 struct bnxt *bp = dev->data->dev_private;
1566 struct rte_eth_link link_info;
1569 rc = is_bnxt_in_error(bp);
1573 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1577 memset(fc_conf, 0, sizeof(*fc_conf));
1578 if (bp->link_info.auto_pause)
1579 fc_conf->autoneg = 1;
1580 switch (bp->link_info.pause) {
1582 fc_conf->mode = RTE_FC_NONE;
1584 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1585 fc_conf->mode = RTE_FC_TX_PAUSE;
1587 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1588 fc_conf->mode = RTE_FC_RX_PAUSE;
1590 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1591 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1592 fc_conf->mode = RTE_FC_FULL;
1598 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1599 struct rte_eth_fc_conf *fc_conf)
1601 struct bnxt *bp = dev->data->dev_private;
1604 rc = is_bnxt_in_error(bp);
1608 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1609 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1613 switch (fc_conf->mode) {
1615 bp->link_info.auto_pause = 0;
1616 bp->link_info.force_pause = 0;
1618 case RTE_FC_RX_PAUSE:
1619 if (fc_conf->autoneg) {
1620 bp->link_info.auto_pause =
1621 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1622 bp->link_info.force_pause = 0;
1624 bp->link_info.auto_pause = 0;
1625 bp->link_info.force_pause =
1626 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1629 case RTE_FC_TX_PAUSE:
1630 if (fc_conf->autoneg) {
1631 bp->link_info.auto_pause =
1632 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1633 bp->link_info.force_pause = 0;
1635 bp->link_info.auto_pause = 0;
1636 bp->link_info.force_pause =
1637 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1641 if (fc_conf->autoneg) {
1642 bp->link_info.auto_pause =
1643 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1644 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1645 bp->link_info.force_pause = 0;
1647 bp->link_info.auto_pause = 0;
1648 bp->link_info.force_pause =
1649 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1650 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1654 return bnxt_set_hwrm_link_config(bp, true);
1657 /* Add UDP tunneling port */
1659 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1660 struct rte_eth_udp_tunnel *udp_tunnel)
1662 struct bnxt *bp = eth_dev->data->dev_private;
1663 uint16_t tunnel_type = 0;
1666 rc = is_bnxt_in_error(bp);
1670 switch (udp_tunnel->prot_type) {
1671 case RTE_TUNNEL_TYPE_VXLAN:
1672 if (bp->vxlan_port_cnt) {
1673 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1674 udp_tunnel->udp_port);
1675 if (bp->vxlan_port != udp_tunnel->udp_port) {
1676 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1679 bp->vxlan_port_cnt++;
1683 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1684 bp->vxlan_port_cnt++;
1686 case RTE_TUNNEL_TYPE_GENEVE:
1687 if (bp->geneve_port_cnt) {
1688 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1689 udp_tunnel->udp_port);
1690 if (bp->geneve_port != udp_tunnel->udp_port) {
1691 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1694 bp->geneve_port_cnt++;
1698 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1699 bp->geneve_port_cnt++;
1702 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1705 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1711 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1712 struct rte_eth_udp_tunnel *udp_tunnel)
1714 struct bnxt *bp = eth_dev->data->dev_private;
1715 uint16_t tunnel_type = 0;
1719 rc = is_bnxt_in_error(bp);
1723 switch (udp_tunnel->prot_type) {
1724 case RTE_TUNNEL_TYPE_VXLAN:
1725 if (!bp->vxlan_port_cnt) {
1726 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1729 if (bp->vxlan_port != udp_tunnel->udp_port) {
1730 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1731 udp_tunnel->udp_port, bp->vxlan_port);
1734 if (--bp->vxlan_port_cnt)
1738 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1739 port = bp->vxlan_fw_dst_port_id;
1741 case RTE_TUNNEL_TYPE_GENEVE:
1742 if (!bp->geneve_port_cnt) {
1743 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1746 if (bp->geneve_port != udp_tunnel->udp_port) {
1747 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1748 udp_tunnel->udp_port, bp->geneve_port);
1751 if (--bp->geneve_port_cnt)
1755 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1756 port = bp->geneve_fw_dst_port_id;
1759 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1763 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1766 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1769 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1770 bp->geneve_port = 0;
1775 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1777 struct bnxt_filter_info *filter;
1778 struct bnxt_vnic_info *vnic;
1780 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1782 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1783 filter = STAILQ_FIRST(&vnic->filter);
1785 /* Search for this matching MAC+VLAN filter */
1786 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
1787 /* Delete the filter */
1788 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1791 STAILQ_REMOVE(&vnic->filter, filter,
1792 bnxt_filter_info, next);
1793 bnxt_free_filter(bp, filter);
1795 "Deleted vlan filter for %d\n",
1799 filter = STAILQ_NEXT(filter, next);
1804 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1806 struct bnxt_filter_info *filter;
1807 struct bnxt_vnic_info *vnic;
1809 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1810 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1811 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1813 /* Implementation notes on the use of VNIC in this command:
1815 * By default, these filters belong to default vnic for the function.
1816 * Once these filters are set up, only destination VNIC can be modified.
1817 * If the destination VNIC is not specified in this command,
1818 * then the HWRM shall only create an l2 context id.
1821 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1822 filter = STAILQ_FIRST(&vnic->filter);
1823 /* Check if the VLAN has already been added */
1825 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
1828 filter = STAILQ_NEXT(filter, next);
1831 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1832 * command to create MAC+VLAN filter with the right flags, enables set.
1834 filter = bnxt_alloc_filter(bp);
1837 "MAC/VLAN filter alloc failed\n");
1840 /* MAC + VLAN ID filter */
1841 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1842 * untagged packets are received
1844 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
1845 * packets and only the programmed vlan's packets are received
1847 filter->l2_ivlan = vlan_id;
1848 filter->l2_ivlan_mask = 0x0FFF;
1849 filter->enables |= en;
1850 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1852 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1854 /* Free the newly allocated filter as we were
1855 * not able to create the filter in hardware.
1857 bnxt_free_filter(bp, filter);
1861 filter->mac_index = 0;
1862 /* Add this new filter to the list */
1864 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1866 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1869 "Added Vlan filter for %d\n", vlan_id);
1873 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1874 uint16_t vlan_id, int on)
1876 struct bnxt *bp = eth_dev->data->dev_private;
1879 rc = is_bnxt_in_error(bp);
1883 /* These operations apply to ALL existing MAC/VLAN filters */
1885 return bnxt_add_vlan_filter(bp, vlan_id);
1887 return bnxt_del_vlan_filter(bp, vlan_id);
1890 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
1891 struct bnxt_vnic_info *vnic)
1893 struct bnxt_filter_info *filter;
1896 filter = STAILQ_FIRST(&vnic->filter);
1898 if (filter->mac_index == 0 &&
1899 !memcmp(filter->l2_addr, bp->mac_addr,
1900 RTE_ETHER_ADDR_LEN)) {
1901 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1903 STAILQ_REMOVE(&vnic->filter, filter,
1904 bnxt_filter_info, next);
1905 bnxt_free_filter(bp, filter);
1909 filter = STAILQ_NEXT(filter, next);
1915 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
1917 struct bnxt_vnic_info *vnic;
1921 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1922 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1923 /* Remove any VLAN filters programmed */
1924 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1925 bnxt_del_vlan_filter(bp, i);
1927 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1931 /* Default filter will allow packets that match the
1932 * dest mac. So, it has to be deleted, otherwise, we
1933 * will endup receiving vlan packets for which the
1934 * filter is not programmed, when hw-vlan-filter
1935 * configuration is ON
1937 bnxt_del_dflt_mac_filter(bp, vnic);
1938 /* This filter will allow only untagged packets */
1939 bnxt_add_vlan_filter(bp, 0);
1941 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1942 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1947 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
1949 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
1953 /* Destroy vnic filters and vnic */
1954 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
1955 DEV_RX_OFFLOAD_VLAN_FILTER) {
1956 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1957 bnxt_del_vlan_filter(bp, i);
1959 bnxt_del_dflt_mac_filter(bp, vnic);
1961 rc = bnxt_hwrm_vnic_free(bp, vnic);
1965 rte_free(vnic->fw_grp_ids);
1966 vnic->fw_grp_ids = NULL;
1972 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
1974 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1977 /* Destroy, recreate and reconfigure the default vnic */
1978 rc = bnxt_free_one_vnic(bp, 0);
1982 /* default vnic 0 */
1983 rc = bnxt_setup_one_vnic(bp, 0);
1987 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
1988 DEV_RX_OFFLOAD_VLAN_FILTER) {
1989 rc = bnxt_add_vlan_filter(bp, 0);
1992 rc = bnxt_restore_vlan_filters(bp);
1996 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2001 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2005 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2006 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2012 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2014 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2015 struct bnxt *bp = dev->data->dev_private;
2018 rc = is_bnxt_in_error(bp);
2022 /* Filter settings will get applied when port is started */
2023 if (!dev->data->dev_started)
2026 if (mask & ETH_VLAN_FILTER_MASK) {
2027 /* Enable or disable VLAN filtering */
2028 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2033 if (mask & ETH_VLAN_STRIP_MASK) {
2034 /* Enable or disable VLAN stripping */
2035 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2040 if (mask & ETH_VLAN_EXTEND_MASK) {
2041 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2042 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2044 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2051 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2054 struct bnxt *bp = dev->data->dev_private;
2055 int qinq = dev->data->dev_conf.rxmode.offloads &
2056 DEV_RX_OFFLOAD_VLAN_EXTEND;
2058 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2059 vlan_type != ETH_VLAN_TYPE_OUTER) {
2061 "Unsupported vlan type.");
2066 "QinQ not enabled. Needs to be ON as we can "
2067 "accelerate only outer vlan\n");
2071 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2073 case RTE_ETHER_TYPE_QINQ:
2075 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2077 case RTE_ETHER_TYPE_VLAN:
2079 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2083 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2087 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2091 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2094 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2097 bp->outer_tpid_bd |= tpid;
2098 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2099 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2101 "Can accelerate only outer vlan in QinQ\n");
2109 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2110 struct rte_ether_addr *addr)
2112 struct bnxt *bp = dev->data->dev_private;
2113 /* Default Filter is tied to VNIC 0 */
2114 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2117 rc = is_bnxt_in_error(bp);
2121 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2124 if (rte_is_zero_ether_addr(addr))
2127 /* Filter settings will get applied when port is started */
2128 if (!dev->data->dev_started)
2131 /* Check if the requested MAC is already added */
2132 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2135 /* Destroy filter and re-create it */
2136 bnxt_del_dflt_mac_filter(bp, vnic);
2138 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2139 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2140 /* This filter will allow only untagged packets */
2141 rc = bnxt_add_vlan_filter(bp, 0);
2143 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2146 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2151 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2152 struct rte_ether_addr *mc_addr_set,
2153 uint32_t nb_mc_addr)
2155 struct bnxt *bp = eth_dev->data->dev_private;
2156 char *mc_addr_list = (char *)mc_addr_set;
2157 struct bnxt_vnic_info *vnic;
2158 uint32_t off = 0, i = 0;
2161 rc = is_bnxt_in_error(bp);
2165 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2167 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2168 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2172 /* TODO Check for Duplicate mcast addresses */
2173 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2174 for (i = 0; i < nb_mc_addr; i++) {
2175 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2176 RTE_ETHER_ADDR_LEN);
2177 off += RTE_ETHER_ADDR_LEN;
2180 vnic->mc_addr_cnt = i;
2181 if (vnic->mc_addr_cnt)
2182 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2184 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2187 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2191 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2193 struct bnxt *bp = dev->data->dev_private;
2194 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2195 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2196 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2199 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2200 fw_major, fw_minor, fw_updt);
2202 ret += 1; /* add the size of '\0' */
2203 if (fw_size < (uint32_t)ret)
2210 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2211 struct rte_eth_rxq_info *qinfo)
2213 struct bnxt *bp = dev->data->dev_private;
2214 struct bnxt_rx_queue *rxq;
2216 if (is_bnxt_in_error(bp))
2219 rxq = dev->data->rx_queues[queue_id];
2221 qinfo->mp = rxq->mb_pool;
2222 qinfo->scattered_rx = dev->data->scattered_rx;
2223 qinfo->nb_desc = rxq->nb_rx_desc;
2225 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2226 qinfo->conf.rx_drop_en = 0;
2227 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2231 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2232 struct rte_eth_txq_info *qinfo)
2234 struct bnxt *bp = dev->data->dev_private;
2235 struct bnxt_tx_queue *txq;
2237 if (is_bnxt_in_error(bp))
2240 txq = dev->data->tx_queues[queue_id];
2242 qinfo->nb_desc = txq->nb_tx_desc;
2244 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2245 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2246 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2248 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2249 qinfo->conf.tx_rs_thresh = 0;
2250 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2253 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2255 struct bnxt *bp = eth_dev->data->dev_private;
2256 uint32_t new_pkt_size;
2260 rc = is_bnxt_in_error(bp);
2264 /* Exit if receive queues are not configured yet */
2265 if (!eth_dev->data->nb_rx_queues)
2268 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2269 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2273 * If vector-mode tx/rx is active, disallow any MTU change that would
2274 * require scattered receive support.
2276 if (eth_dev->data->dev_started &&
2277 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2278 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2280 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2282 "MTU change would require scattered rx support. ");
2283 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2288 if (new_mtu > RTE_ETHER_MTU) {
2289 bp->flags |= BNXT_FLAG_JUMBO;
2290 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2291 DEV_RX_OFFLOAD_JUMBO_FRAME;
2293 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2294 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2295 bp->flags &= ~BNXT_FLAG_JUMBO;
2298 /* Is there a change in mtu setting? */
2299 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2302 for (i = 0; i < bp->nr_vnics; i++) {
2303 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2306 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2307 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2311 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2312 size -= RTE_PKTMBUF_HEADROOM;
2314 if (size < new_mtu) {
2315 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2322 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2324 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2330 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2332 struct bnxt *bp = dev->data->dev_private;
2333 uint16_t vlan = bp->vlan;
2336 rc = is_bnxt_in_error(bp);
2340 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2342 "PVID cannot be modified for this function\n");
2345 bp->vlan = on ? pvid : 0;
2347 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2354 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2356 struct bnxt *bp = dev->data->dev_private;
2359 rc = is_bnxt_in_error(bp);
2363 return bnxt_hwrm_port_led_cfg(bp, true);
2367 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2369 struct bnxt *bp = dev->data->dev_private;
2372 rc = is_bnxt_in_error(bp);
2376 return bnxt_hwrm_port_led_cfg(bp, false);
2380 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2382 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2383 uint32_t desc = 0, raw_cons = 0, cons;
2384 struct bnxt_cp_ring_info *cpr;
2385 struct bnxt_rx_queue *rxq;
2386 struct rx_pkt_cmpl *rxcmp;
2389 rc = is_bnxt_in_error(bp);
2393 rxq = dev->data->rx_queues[rx_queue_id];
2395 raw_cons = cpr->cp_raw_cons;
2398 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2399 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2400 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2402 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2414 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2416 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2417 struct bnxt_rx_ring_info *rxr;
2418 struct bnxt_cp_ring_info *cpr;
2419 struct bnxt_sw_rx_bd *rx_buf;
2420 struct rx_pkt_cmpl *rxcmp;
2421 uint32_t cons, cp_cons;
2427 rc = is_bnxt_in_error(rxq->bp);
2434 if (offset >= rxq->nb_rx_desc)
2437 cons = RING_CMP(cpr->cp_ring_struct, offset);
2438 cp_cons = cpr->cp_raw_cons;
2439 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2441 if (cons > cp_cons) {
2442 if (CMPL_VALID(rxcmp, cpr->valid))
2443 return RTE_ETH_RX_DESC_DONE;
2445 if (CMPL_VALID(rxcmp, !cpr->valid))
2446 return RTE_ETH_RX_DESC_DONE;
2448 rx_buf = &rxr->rx_buf_ring[cons];
2449 if (rx_buf->mbuf == NULL)
2450 return RTE_ETH_RX_DESC_UNAVAIL;
2453 return RTE_ETH_RX_DESC_AVAIL;
2457 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2459 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2460 struct bnxt_tx_ring_info *txr;
2461 struct bnxt_cp_ring_info *cpr;
2462 struct bnxt_sw_tx_bd *tx_buf;
2463 struct tx_pkt_cmpl *txcmp;
2464 uint32_t cons, cp_cons;
2470 rc = is_bnxt_in_error(txq->bp);
2477 if (offset >= txq->nb_tx_desc)
2480 cons = RING_CMP(cpr->cp_ring_struct, offset);
2481 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2482 cp_cons = cpr->cp_raw_cons;
2484 if (cons > cp_cons) {
2485 if (CMPL_VALID(txcmp, cpr->valid))
2486 return RTE_ETH_TX_DESC_UNAVAIL;
2488 if (CMPL_VALID(txcmp, !cpr->valid))
2489 return RTE_ETH_TX_DESC_UNAVAIL;
2491 tx_buf = &txr->tx_buf_ring[cons];
2492 if (tx_buf->mbuf == NULL)
2493 return RTE_ETH_TX_DESC_DONE;
2495 return RTE_ETH_TX_DESC_FULL;
2498 static struct bnxt_filter_info *
2499 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2500 struct rte_eth_ethertype_filter *efilter,
2501 struct bnxt_vnic_info *vnic0,
2502 struct bnxt_vnic_info *vnic,
2505 struct bnxt_filter_info *mfilter = NULL;
2509 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2510 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2511 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2512 " ethertype filter.", efilter->ether_type);
2516 if (efilter->queue >= bp->rx_nr_rings) {
2517 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2522 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2523 vnic = &bp->vnic_info[efilter->queue];
2525 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2530 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2531 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2532 if ((!memcmp(efilter->mac_addr.addr_bytes,
2533 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2535 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2536 mfilter->ethertype == efilter->ether_type)) {
2542 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2543 if ((!memcmp(efilter->mac_addr.addr_bytes,
2544 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2545 mfilter->ethertype == efilter->ether_type &&
2547 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2561 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2562 enum rte_filter_op filter_op,
2565 struct bnxt *bp = dev->data->dev_private;
2566 struct rte_eth_ethertype_filter *efilter =
2567 (struct rte_eth_ethertype_filter *)arg;
2568 struct bnxt_filter_info *bfilter, *filter1;
2569 struct bnxt_vnic_info *vnic, *vnic0;
2572 if (filter_op == RTE_ETH_FILTER_NOP)
2576 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2581 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2582 vnic = &bp->vnic_info[efilter->queue];
2584 switch (filter_op) {
2585 case RTE_ETH_FILTER_ADD:
2586 bnxt_match_and_validate_ether_filter(bp, efilter,
2591 bfilter = bnxt_get_unused_filter(bp);
2592 if (bfilter == NULL) {
2594 "Not enough resources for a new filter.\n");
2597 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2598 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2599 RTE_ETHER_ADDR_LEN);
2600 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2601 RTE_ETHER_ADDR_LEN);
2602 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2603 bfilter->ethertype = efilter->ether_type;
2604 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2606 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2607 if (filter1 == NULL) {
2612 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2613 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2615 bfilter->dst_id = vnic->fw_vnic_id;
2617 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2619 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2622 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2625 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2627 case RTE_ETH_FILTER_DELETE:
2628 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2630 if (ret == -EEXIST) {
2631 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2633 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2635 bnxt_free_filter(bp, filter1);
2636 } else if (ret == 0) {
2637 PMD_DRV_LOG(ERR, "No matching filter found\n");
2641 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2647 bnxt_free_filter(bp, bfilter);
2653 parse_ntuple_filter(struct bnxt *bp,
2654 struct rte_eth_ntuple_filter *nfilter,
2655 struct bnxt_filter_info *bfilter)
2659 if (nfilter->queue >= bp->rx_nr_rings) {
2660 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2664 switch (nfilter->dst_port_mask) {
2666 bfilter->dst_port_mask = -1;
2667 bfilter->dst_port = nfilter->dst_port;
2668 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2669 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2672 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2676 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2677 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2679 switch (nfilter->proto_mask) {
2681 if (nfilter->proto == 17) /* IPPROTO_UDP */
2682 bfilter->ip_protocol = 17;
2683 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2684 bfilter->ip_protocol = 6;
2687 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2690 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2694 switch (nfilter->dst_ip_mask) {
2696 bfilter->dst_ipaddr_mask[0] = -1;
2697 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2698 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2699 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2702 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2706 switch (nfilter->src_ip_mask) {
2708 bfilter->src_ipaddr_mask[0] = -1;
2709 bfilter->src_ipaddr[0] = nfilter->src_ip;
2710 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2711 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2714 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2718 switch (nfilter->src_port_mask) {
2720 bfilter->src_port_mask = -1;
2721 bfilter->src_port = nfilter->src_port;
2722 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2723 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2726 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2730 bfilter->enables = en;
2734 static struct bnxt_filter_info*
2735 bnxt_match_ntuple_filter(struct bnxt *bp,
2736 struct bnxt_filter_info *bfilter,
2737 struct bnxt_vnic_info **mvnic)
2739 struct bnxt_filter_info *mfilter = NULL;
2742 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2743 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2744 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2745 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2746 bfilter->src_ipaddr_mask[0] ==
2747 mfilter->src_ipaddr_mask[0] &&
2748 bfilter->src_port == mfilter->src_port &&
2749 bfilter->src_port_mask == mfilter->src_port_mask &&
2750 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2751 bfilter->dst_ipaddr_mask[0] ==
2752 mfilter->dst_ipaddr_mask[0] &&
2753 bfilter->dst_port == mfilter->dst_port &&
2754 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2755 bfilter->flags == mfilter->flags &&
2756 bfilter->enables == mfilter->enables) {
2767 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2768 struct rte_eth_ntuple_filter *nfilter,
2769 enum rte_filter_op filter_op)
2771 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2772 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2775 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2776 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2780 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2781 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2785 bfilter = bnxt_get_unused_filter(bp);
2786 if (bfilter == NULL) {
2788 "Not enough resources for a new filter.\n");
2791 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2795 vnic = &bp->vnic_info[nfilter->queue];
2796 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2797 filter1 = STAILQ_FIRST(&vnic0->filter);
2798 if (filter1 == NULL) {
2803 bfilter->dst_id = vnic->fw_vnic_id;
2804 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2806 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2807 bfilter->ethertype = 0x800;
2808 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2810 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2812 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2813 bfilter->dst_id == mfilter->dst_id) {
2814 PMD_DRV_LOG(ERR, "filter exists.\n");
2817 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2818 bfilter->dst_id != mfilter->dst_id) {
2819 mfilter->dst_id = vnic->fw_vnic_id;
2820 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2821 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2822 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2823 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2824 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2827 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2828 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2833 if (filter_op == RTE_ETH_FILTER_ADD) {
2834 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2835 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2838 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2840 if (mfilter == NULL) {
2841 /* This should not happen. But for Coverity! */
2845 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2847 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2848 bnxt_free_filter(bp, mfilter);
2849 bnxt_free_filter(bp, bfilter);
2854 bnxt_free_filter(bp, bfilter);
2859 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2860 enum rte_filter_op filter_op,
2863 struct bnxt *bp = dev->data->dev_private;
2866 if (filter_op == RTE_ETH_FILTER_NOP)
2870 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2875 switch (filter_op) {
2876 case RTE_ETH_FILTER_ADD:
2877 ret = bnxt_cfg_ntuple_filter(bp,
2878 (struct rte_eth_ntuple_filter *)arg,
2881 case RTE_ETH_FILTER_DELETE:
2882 ret = bnxt_cfg_ntuple_filter(bp,
2883 (struct rte_eth_ntuple_filter *)arg,
2887 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2895 bnxt_parse_fdir_filter(struct bnxt *bp,
2896 struct rte_eth_fdir_filter *fdir,
2897 struct bnxt_filter_info *filter)
2899 enum rte_fdir_mode fdir_mode =
2900 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2901 struct bnxt_vnic_info *vnic0, *vnic;
2902 struct bnxt_filter_info *filter1;
2906 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2909 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2910 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2912 switch (fdir->input.flow_type) {
2913 case RTE_ETH_FLOW_IPV4:
2914 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2916 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2917 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2918 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2919 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2920 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2921 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2922 filter->ip_addr_type =
2923 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2924 filter->src_ipaddr_mask[0] = 0xffffffff;
2925 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2926 filter->dst_ipaddr_mask[0] = 0xffffffff;
2927 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2928 filter->ethertype = 0x800;
2929 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2931 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2932 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2933 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2934 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2935 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2936 filter->dst_port_mask = 0xffff;
2937 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2938 filter->src_port_mask = 0xffff;
2939 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2940 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2941 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2942 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2943 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2944 filter->ip_protocol = 6;
2945 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2946 filter->ip_addr_type =
2947 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2948 filter->src_ipaddr_mask[0] = 0xffffffff;
2949 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2950 filter->dst_ipaddr_mask[0] = 0xffffffff;
2951 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2952 filter->ethertype = 0x800;
2953 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2955 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2956 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2957 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2958 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2959 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2960 filter->dst_port_mask = 0xffff;
2961 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2962 filter->src_port_mask = 0xffff;
2963 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2964 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2965 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2966 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2967 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2968 filter->ip_protocol = 17;
2969 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2970 filter->ip_addr_type =
2971 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2972 filter->src_ipaddr_mask[0] = 0xffffffff;
2973 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2974 filter->dst_ipaddr_mask[0] = 0xffffffff;
2975 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2976 filter->ethertype = 0x800;
2977 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2979 case RTE_ETH_FLOW_IPV6:
2980 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2982 filter->ip_addr_type =
2983 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2984 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2985 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2986 rte_memcpy(filter->src_ipaddr,
2987 fdir->input.flow.ipv6_flow.src_ip, 16);
2988 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2989 rte_memcpy(filter->dst_ipaddr,
2990 fdir->input.flow.ipv6_flow.dst_ip, 16);
2991 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2992 memset(filter->dst_ipaddr_mask, 0xff, 16);
2993 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2994 memset(filter->src_ipaddr_mask, 0xff, 16);
2995 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2996 filter->ethertype = 0x86dd;
2997 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2999 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3000 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3001 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3002 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3003 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3004 filter->dst_port_mask = 0xffff;
3005 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3006 filter->src_port_mask = 0xffff;
3007 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3008 filter->ip_addr_type =
3009 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3010 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3011 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3012 rte_memcpy(filter->src_ipaddr,
3013 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3014 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3015 rte_memcpy(filter->dst_ipaddr,
3016 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3017 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3018 memset(filter->dst_ipaddr_mask, 0xff, 16);
3019 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3020 memset(filter->src_ipaddr_mask, 0xff, 16);
3021 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3022 filter->ethertype = 0x86dd;
3023 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3025 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3026 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3027 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3028 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3029 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3030 filter->dst_port_mask = 0xffff;
3031 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3032 filter->src_port_mask = 0xffff;
3033 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3034 filter->ip_addr_type =
3035 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3036 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3037 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3038 rte_memcpy(filter->src_ipaddr,
3039 fdir->input.flow.udp6_flow.ip.src_ip, 16);
3040 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3041 rte_memcpy(filter->dst_ipaddr,
3042 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3043 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3044 memset(filter->dst_ipaddr_mask, 0xff, 16);
3045 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3046 memset(filter->src_ipaddr_mask, 0xff, 16);
3047 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3048 filter->ethertype = 0x86dd;
3049 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3051 case RTE_ETH_FLOW_L2_PAYLOAD:
3052 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3053 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3055 case RTE_ETH_FLOW_VXLAN:
3056 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3058 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3059 filter->tunnel_type =
3060 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3061 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3063 case RTE_ETH_FLOW_NVGRE:
3064 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3066 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3067 filter->tunnel_type =
3068 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3069 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3071 case RTE_ETH_FLOW_UNKNOWN:
3072 case RTE_ETH_FLOW_RAW:
3073 case RTE_ETH_FLOW_FRAG_IPV4:
3074 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3075 case RTE_ETH_FLOW_FRAG_IPV6:
3076 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3077 case RTE_ETH_FLOW_IPV6_EX:
3078 case RTE_ETH_FLOW_IPV6_TCP_EX:
3079 case RTE_ETH_FLOW_IPV6_UDP_EX:
3080 case RTE_ETH_FLOW_GENEVE:
3086 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3087 vnic = &bp->vnic_info[fdir->action.rx_queue];
3089 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3093 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3094 rte_memcpy(filter->dst_macaddr,
3095 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3096 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3099 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3100 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3101 filter1 = STAILQ_FIRST(&vnic0->filter);
3102 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3104 filter->dst_id = vnic->fw_vnic_id;
3105 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3106 if (filter->dst_macaddr[i] == 0x00)
3107 filter1 = STAILQ_FIRST(&vnic0->filter);
3109 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3112 if (filter1 == NULL)
3115 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3116 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3118 filter->enables = en;
3123 static struct bnxt_filter_info *
3124 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3125 struct bnxt_vnic_info **mvnic)
3127 struct bnxt_filter_info *mf = NULL;
3130 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3131 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3133 STAILQ_FOREACH(mf, &vnic->filter, next) {
3134 if (mf->filter_type == nf->filter_type &&
3135 mf->flags == nf->flags &&
3136 mf->src_port == nf->src_port &&
3137 mf->src_port_mask == nf->src_port_mask &&
3138 mf->dst_port == nf->dst_port &&
3139 mf->dst_port_mask == nf->dst_port_mask &&
3140 mf->ip_protocol == nf->ip_protocol &&
3141 mf->ip_addr_type == nf->ip_addr_type &&
3142 mf->ethertype == nf->ethertype &&
3143 mf->vni == nf->vni &&
3144 mf->tunnel_type == nf->tunnel_type &&
3145 mf->l2_ovlan == nf->l2_ovlan &&
3146 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3147 mf->l2_ivlan == nf->l2_ivlan &&
3148 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3149 !memcmp(mf->l2_addr, nf->l2_addr,
3150 RTE_ETHER_ADDR_LEN) &&
3151 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3152 RTE_ETHER_ADDR_LEN) &&
3153 !memcmp(mf->src_macaddr, nf->src_macaddr,
3154 RTE_ETHER_ADDR_LEN) &&
3155 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3156 RTE_ETHER_ADDR_LEN) &&
3157 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3158 sizeof(nf->src_ipaddr)) &&
3159 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3160 sizeof(nf->src_ipaddr_mask)) &&
3161 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3162 sizeof(nf->dst_ipaddr)) &&
3163 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3164 sizeof(nf->dst_ipaddr_mask))) {
3175 bnxt_fdir_filter(struct rte_eth_dev *dev,
3176 enum rte_filter_op filter_op,
3179 struct bnxt *bp = dev->data->dev_private;
3180 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
3181 struct bnxt_filter_info *filter, *match;
3182 struct bnxt_vnic_info *vnic, *mvnic;
3185 if (filter_op == RTE_ETH_FILTER_NOP)
3188 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3191 switch (filter_op) {
3192 case RTE_ETH_FILTER_ADD:
3193 case RTE_ETH_FILTER_DELETE:
3195 filter = bnxt_get_unused_filter(bp);
3196 if (filter == NULL) {
3198 "Not enough resources for a new flow.\n");
3202 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3205 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3207 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3208 vnic = &bp->vnic_info[0];
3210 vnic = &bp->vnic_info[fdir->action.rx_queue];
3212 match = bnxt_match_fdir(bp, filter, &mvnic);
3213 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3214 if (match->dst_id == vnic->fw_vnic_id) {
3215 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3219 match->dst_id = vnic->fw_vnic_id;
3220 ret = bnxt_hwrm_set_ntuple_filter(bp,
3223 STAILQ_REMOVE(&mvnic->filter, match,
3224 bnxt_filter_info, next);
3225 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3227 "Filter with matching pattern exist\n");
3229 "Updated it to new destination q\n");
3233 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3234 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3239 if (filter_op == RTE_ETH_FILTER_ADD) {
3240 ret = bnxt_hwrm_set_ntuple_filter(bp,
3245 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3247 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3248 STAILQ_REMOVE(&vnic->filter, match,
3249 bnxt_filter_info, next);
3250 bnxt_free_filter(bp, match);
3251 bnxt_free_filter(bp, filter);
3254 case RTE_ETH_FILTER_FLUSH:
3255 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3256 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3258 STAILQ_FOREACH(filter, &vnic->filter, next) {
3259 if (filter->filter_type ==
3260 HWRM_CFA_NTUPLE_FILTER) {
3262 bnxt_hwrm_clear_ntuple_filter(bp,
3264 STAILQ_REMOVE(&vnic->filter, filter,
3265 bnxt_filter_info, next);
3270 case RTE_ETH_FILTER_UPDATE:
3271 case RTE_ETH_FILTER_STATS:
3272 case RTE_ETH_FILTER_INFO:
3273 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3276 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3283 bnxt_free_filter(bp, filter);
3288 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3289 enum rte_filter_type filter_type,
3290 enum rte_filter_op filter_op, void *arg)
3292 struct bnxt *bp = dev->data->dev_private;
3295 ret = is_bnxt_in_error(dev->data->dev_private);
3299 switch (filter_type) {
3300 case RTE_ETH_FILTER_TUNNEL:
3302 "filter type: %d: To be implemented\n", filter_type);
3304 case RTE_ETH_FILTER_FDIR:
3305 ret = bnxt_fdir_filter(dev, filter_op, arg);
3307 case RTE_ETH_FILTER_NTUPLE:
3308 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3310 case RTE_ETH_FILTER_ETHERTYPE:
3311 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3313 case RTE_ETH_FILTER_GENERIC:
3314 if (filter_op != RTE_ETH_FILTER_GET)
3317 *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3319 *(const void **)arg = &bnxt_flow_ops;
3323 "Filter type (%d) not supported", filter_type);
3330 static const uint32_t *
3331 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3333 static const uint32_t ptypes[] = {
3334 RTE_PTYPE_L2_ETHER_VLAN,
3335 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3336 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3340 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3341 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3342 RTE_PTYPE_INNER_L4_ICMP,
3343 RTE_PTYPE_INNER_L4_TCP,
3344 RTE_PTYPE_INNER_L4_UDP,
3348 if (!dev->rx_pkt_burst)
3354 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3357 uint32_t reg_base = *reg_arr & 0xfffff000;
3361 for (i = 0; i < count; i++) {
3362 if ((reg_arr[i] & 0xfffff000) != reg_base)
3365 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3366 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3370 static int bnxt_map_ptp_regs(struct bnxt *bp)
3372 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3376 reg_arr = ptp->rx_regs;
3377 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3381 reg_arr = ptp->tx_regs;
3382 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3386 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3387 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3389 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3390 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3395 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3397 rte_write32(0, (uint8_t *)bp->bar0 +
3398 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3399 rte_write32(0, (uint8_t *)bp->bar0 +
3400 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3403 static uint64_t bnxt_cc_read(struct bnxt *bp)
3407 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3408 BNXT_GRCPF_REG_SYNC_TIME));
3409 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3410 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3414 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3416 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3419 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3420 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3421 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3424 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3425 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3426 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3427 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3428 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3429 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3434 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3436 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3437 struct bnxt_pf_info *pf = &bp->pf;
3444 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3445 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3446 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3449 port_id = pf->port_id;
3450 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3451 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3453 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3454 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3455 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3456 /* bnxt_clr_rx_ts(bp); TBD */
3460 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3461 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3462 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3463 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3469 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3472 struct bnxt *bp = dev->data->dev_private;
3473 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3478 ns = rte_timespec_to_ns(ts);
3479 /* Set the timecounters to a new value. */
3486 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3488 struct bnxt *bp = dev->data->dev_private;
3489 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3490 uint64_t ns, systime_cycles = 0;
3496 if (BNXT_CHIP_THOR(bp))
3497 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3500 systime_cycles = bnxt_cc_read(bp);
3502 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3503 *ts = rte_ns_to_timespec(ns);
3508 bnxt_timesync_enable(struct rte_eth_dev *dev)
3510 struct bnxt *bp = dev->data->dev_private;
3511 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3519 ptp->tx_tstamp_en = 1;
3520 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3522 rc = bnxt_hwrm_ptp_cfg(bp);
3526 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3527 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3528 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3530 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3531 ptp->tc.cc_shift = shift;
3532 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3534 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3535 ptp->rx_tstamp_tc.cc_shift = shift;
3536 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3538 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3539 ptp->tx_tstamp_tc.cc_shift = shift;
3540 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3542 if (!BNXT_CHIP_THOR(bp))
3543 bnxt_map_ptp_regs(bp);
3549 bnxt_timesync_disable(struct rte_eth_dev *dev)
3551 struct bnxt *bp = dev->data->dev_private;
3552 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3558 ptp->tx_tstamp_en = 0;
3561 bnxt_hwrm_ptp_cfg(bp);
3563 if (!BNXT_CHIP_THOR(bp))
3564 bnxt_unmap_ptp_regs(bp);
3570 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3571 struct timespec *timestamp,
3572 uint32_t flags __rte_unused)
3574 struct bnxt *bp = dev->data->dev_private;
3575 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3576 uint64_t rx_tstamp_cycles = 0;
3582 if (BNXT_CHIP_THOR(bp))
3583 rx_tstamp_cycles = ptp->rx_timestamp;
3585 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3587 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3588 *timestamp = rte_ns_to_timespec(ns);
3593 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3594 struct timespec *timestamp)
3596 struct bnxt *bp = dev->data->dev_private;
3597 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3598 uint64_t tx_tstamp_cycles = 0;
3605 if (BNXT_CHIP_THOR(bp))
3606 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3609 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3611 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3612 *timestamp = rte_ns_to_timespec(ns);
3618 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3620 struct bnxt *bp = dev->data->dev_private;
3621 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3626 ptp->tc.nsec += delta;
3632 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3634 struct bnxt *bp = dev->data->dev_private;
3636 uint32_t dir_entries;
3637 uint32_t entry_length;
3639 rc = is_bnxt_in_error(bp);
3643 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3644 bp->pdev->addr.domain, bp->pdev->addr.bus,
3645 bp->pdev->addr.devid, bp->pdev->addr.function);
3647 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3651 return dir_entries * entry_length;
3655 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3656 struct rte_dev_eeprom_info *in_eeprom)
3658 struct bnxt *bp = dev->data->dev_private;
3663 rc = is_bnxt_in_error(bp);
3667 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3668 bp->pdev->addr.domain, bp->pdev->addr.bus,
3669 bp->pdev->addr.devid, bp->pdev->addr.function,
3670 in_eeprom->offset, in_eeprom->length);
3672 if (in_eeprom->offset == 0) /* special offset value to get directory */
3673 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3676 index = in_eeprom->offset >> 24;
3677 offset = in_eeprom->offset & 0xffffff;
3680 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3681 in_eeprom->length, in_eeprom->data);
3686 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3689 case BNX_DIR_TYPE_CHIMP_PATCH:
3690 case BNX_DIR_TYPE_BOOTCODE:
3691 case BNX_DIR_TYPE_BOOTCODE_2:
3692 case BNX_DIR_TYPE_APE_FW:
3693 case BNX_DIR_TYPE_APE_PATCH:
3694 case BNX_DIR_TYPE_KONG_FW:
3695 case BNX_DIR_TYPE_KONG_PATCH:
3696 case BNX_DIR_TYPE_BONO_FW:
3697 case BNX_DIR_TYPE_BONO_PATCH:
3705 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3708 case BNX_DIR_TYPE_AVS:
3709 case BNX_DIR_TYPE_EXP_ROM_MBA:
3710 case BNX_DIR_TYPE_PCIE:
3711 case BNX_DIR_TYPE_TSCF_UCODE:
3712 case BNX_DIR_TYPE_EXT_PHY:
3713 case BNX_DIR_TYPE_CCM:
3714 case BNX_DIR_TYPE_ISCSI_BOOT:
3715 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3716 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3724 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3726 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3727 bnxt_dir_type_is_other_exec_format(dir_type);
3731 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3732 struct rte_dev_eeprom_info *in_eeprom)
3734 struct bnxt *bp = dev->data->dev_private;
3735 uint8_t index, dir_op;
3736 uint16_t type, ext, ordinal, attr;
3739 rc = is_bnxt_in_error(bp);
3743 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3744 bp->pdev->addr.domain, bp->pdev->addr.bus,
3745 bp->pdev->addr.devid, bp->pdev->addr.function,
3746 in_eeprom->offset, in_eeprom->length);
3749 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3753 type = in_eeprom->magic >> 16;
3755 if (type == 0xffff) { /* special value for directory operations */
3756 index = in_eeprom->magic & 0xff;
3757 dir_op = in_eeprom->magic >> 8;
3761 case 0x0e: /* erase */
3762 if (in_eeprom->offset != ~in_eeprom->magic)
3764 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3770 /* Create or re-write an NVM item: */
3771 if (bnxt_dir_type_is_executable(type) == true)
3773 ext = in_eeprom->magic & 0xffff;
3774 ordinal = in_eeprom->offset >> 16;
3775 attr = in_eeprom->offset & 0xffff;
3777 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3778 in_eeprom->data, in_eeprom->length);
3785 static const struct eth_dev_ops bnxt_dev_ops = {
3786 .dev_infos_get = bnxt_dev_info_get_op,
3787 .dev_close = bnxt_dev_close_op,
3788 .dev_configure = bnxt_dev_configure_op,
3789 .dev_start = bnxt_dev_start_op,
3790 .dev_stop = bnxt_dev_stop_op,
3791 .dev_set_link_up = bnxt_dev_set_link_up_op,
3792 .dev_set_link_down = bnxt_dev_set_link_down_op,
3793 .stats_get = bnxt_stats_get_op,
3794 .stats_reset = bnxt_stats_reset_op,
3795 .rx_queue_setup = bnxt_rx_queue_setup_op,
3796 .rx_queue_release = bnxt_rx_queue_release_op,
3797 .tx_queue_setup = bnxt_tx_queue_setup_op,
3798 .tx_queue_release = bnxt_tx_queue_release_op,
3799 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3800 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3801 .reta_update = bnxt_reta_update_op,
3802 .reta_query = bnxt_reta_query_op,
3803 .rss_hash_update = bnxt_rss_hash_update_op,
3804 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3805 .link_update = bnxt_link_update_op,
3806 .promiscuous_enable = bnxt_promiscuous_enable_op,
3807 .promiscuous_disable = bnxt_promiscuous_disable_op,
3808 .allmulticast_enable = bnxt_allmulticast_enable_op,
3809 .allmulticast_disable = bnxt_allmulticast_disable_op,
3810 .mac_addr_add = bnxt_mac_addr_add_op,
3811 .mac_addr_remove = bnxt_mac_addr_remove_op,
3812 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3813 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3814 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3815 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3816 .vlan_filter_set = bnxt_vlan_filter_set_op,
3817 .vlan_offload_set = bnxt_vlan_offload_set_op,
3818 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3819 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3820 .mtu_set = bnxt_mtu_set_op,
3821 .mac_addr_set = bnxt_set_default_mac_addr_op,
3822 .xstats_get = bnxt_dev_xstats_get_op,
3823 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3824 .xstats_reset = bnxt_dev_xstats_reset_op,
3825 .fw_version_get = bnxt_fw_version_get,
3826 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3827 .rxq_info_get = bnxt_rxq_info_get_op,
3828 .txq_info_get = bnxt_txq_info_get_op,
3829 .dev_led_on = bnxt_dev_led_on_op,
3830 .dev_led_off = bnxt_dev_led_off_op,
3831 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3832 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3833 .rx_queue_count = bnxt_rx_queue_count_op,
3834 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3835 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3836 .rx_queue_start = bnxt_rx_queue_start,
3837 .rx_queue_stop = bnxt_rx_queue_stop,
3838 .tx_queue_start = bnxt_tx_queue_start,
3839 .tx_queue_stop = bnxt_tx_queue_stop,
3840 .filter_ctrl = bnxt_filter_ctrl_op,
3841 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3842 .get_eeprom_length = bnxt_get_eeprom_length_op,
3843 .get_eeprom = bnxt_get_eeprom_op,
3844 .set_eeprom = bnxt_set_eeprom_op,
3845 .timesync_enable = bnxt_timesync_enable,
3846 .timesync_disable = bnxt_timesync_disable,
3847 .timesync_read_time = bnxt_timesync_read_time,
3848 .timesync_write_time = bnxt_timesync_write_time,
3849 .timesync_adjust_time = bnxt_timesync_adjust_time,
3850 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3851 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3854 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3858 /* Only pre-map the reset GRC registers using window 3 */
3859 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3860 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3862 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3867 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3869 struct bnxt_error_recovery_info *info = bp->recovery_info;
3870 uint32_t reg_base = 0xffffffff;
3873 /* Only pre-map the monitoring GRC registers using window 2 */
3874 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3875 uint32_t reg = info->status_regs[i];
3877 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3880 if (reg_base == 0xffffffff)
3881 reg_base = reg & 0xfffff000;
3882 if ((reg & 0xfffff000) != reg_base)
3885 /* Use mask 0xffc as the Lower 2 bits indicates
3886 * address space location
3888 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3892 if (reg_base == 0xffffffff)
3895 rte_write32(reg_base, (uint8_t *)bp->bar0 +
3896 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3901 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3903 struct bnxt_error_recovery_info *info = bp->recovery_info;
3904 uint32_t delay = info->delay_after_reset[index];
3905 uint32_t val = info->reset_reg_val[index];
3906 uint32_t reg = info->reset_reg[index];
3907 uint32_t type, offset;
3909 type = BNXT_FW_STATUS_REG_TYPE(reg);
3910 offset = BNXT_FW_STATUS_REG_OFF(reg);
3913 case BNXT_FW_STATUS_REG_TYPE_CFG:
3914 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3916 case BNXT_FW_STATUS_REG_TYPE_GRC:
3917 offset = bnxt_map_reset_regs(bp, offset);
3918 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3920 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3921 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3924 /* wait on a specific interval of time until core reset is complete */
3926 rte_delay_ms(delay);
3929 static void bnxt_dev_cleanup(struct bnxt *bp)
3931 bnxt_set_hwrm_link_config(bp, false);
3932 bp->link_info.link_up = 0;
3933 if (bp->eth_dev->data->dev_started)
3934 bnxt_dev_stop_op(bp->eth_dev);
3936 bnxt_uninit_resources(bp, true);
3939 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3941 struct rte_eth_dev *dev = bp->eth_dev;
3942 struct rte_vlan_filter_conf *vfc;
3946 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3947 vfc = &dev->data->vlan_filter_conf;
3948 vidx = vlan_id / 64;
3949 vbit = vlan_id % 64;
3951 /* Each bit corresponds to a VLAN id */
3952 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3953 rc = bnxt_add_vlan_filter(bp, vlan_id);
3962 static int bnxt_restore_mac_filters(struct bnxt *bp)
3964 struct rte_eth_dev *dev = bp->eth_dev;
3965 struct rte_eth_dev_info dev_info;
3966 struct rte_ether_addr *addr;
3972 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
3975 rc = bnxt_dev_info_get_op(dev, &dev_info);
3979 /* replay MAC address configuration */
3980 for (i = 1; i < dev_info.max_mac_addrs; i++) {
3981 addr = &dev->data->mac_addrs[i];
3983 /* skip zero address */
3984 if (rte_is_zero_ether_addr(addr))
3988 pool_mask = dev->data->mac_pool_sel[i];
3991 if (pool_mask & 1ULL) {
3992 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3998 } while (pool_mask);
4004 static int bnxt_restore_filters(struct bnxt *bp)
4006 struct rte_eth_dev *dev = bp->eth_dev;
4009 if (dev->data->all_multicast) {
4010 ret = bnxt_allmulticast_enable_op(dev);
4014 if (dev->data->promiscuous) {
4015 ret = bnxt_promiscuous_enable_op(dev);
4020 ret = bnxt_restore_mac_filters(bp);
4024 ret = bnxt_restore_vlan_filters(bp);
4025 /* TODO restore other filters as well */
4029 static void bnxt_dev_recover(void *arg)
4031 struct bnxt *bp = arg;
4032 int timeout = bp->fw_reset_max_msecs;
4035 /* Clear Error flag so that device re-init should happen */
4036 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4039 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4042 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4043 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4044 } while (rc && timeout);
4047 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4051 rc = bnxt_init_resources(bp, true);
4054 "Failed to initialize resources after reset\n");
4057 /* clear reset flag as the device is initialized now */
4058 bp->flags &= ~BNXT_FLAG_FW_RESET;
4060 rc = bnxt_dev_start_op(bp->eth_dev);
4062 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4066 rc = bnxt_restore_filters(bp);
4070 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4073 bnxt_dev_stop_op(bp->eth_dev);
4075 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4076 bnxt_uninit_resources(bp, false);
4077 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4080 void bnxt_dev_reset_and_resume(void *arg)
4082 struct bnxt *bp = arg;
4085 bnxt_dev_cleanup(bp);
4087 bnxt_wait_for_device_shutdown(bp);
4089 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4090 bnxt_dev_recover, (void *)bp);
4092 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4095 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4097 struct bnxt_error_recovery_info *info = bp->recovery_info;
4098 uint32_t reg = info->status_regs[index];
4099 uint32_t type, offset, val = 0;
4101 type = BNXT_FW_STATUS_REG_TYPE(reg);
4102 offset = BNXT_FW_STATUS_REG_OFF(reg);
4105 case BNXT_FW_STATUS_REG_TYPE_CFG:
4106 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4108 case BNXT_FW_STATUS_REG_TYPE_GRC:
4109 offset = info->mapped_status_regs[index];
4111 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4112 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4120 static int bnxt_fw_reset_all(struct bnxt *bp)
4122 struct bnxt_error_recovery_info *info = bp->recovery_info;
4126 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4127 /* Reset through master function driver */
4128 for (i = 0; i < info->reg_array_cnt; i++)
4129 bnxt_write_fw_reset_reg(bp, i);
4130 /* Wait for time specified by FW after triggering reset */
4131 rte_delay_ms(info->master_func_wait_period_after_reset);
4132 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4133 /* Reset with the help of Kong processor */
4134 rc = bnxt_hwrm_fw_reset(bp);
4136 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4142 static void bnxt_fw_reset_cb(void *arg)
4144 struct bnxt *bp = arg;
4145 struct bnxt_error_recovery_info *info = bp->recovery_info;
4148 /* Only Master function can do FW reset */
4149 if (bnxt_is_master_func(bp) &&
4150 bnxt_is_recovery_enabled(bp)) {
4151 rc = bnxt_fw_reset_all(bp);
4153 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4158 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4159 * EXCEPTION_FATAL_ASYNC event to all the functions
4160 * (including MASTER FUNC). After receiving this Async, all the active
4161 * drivers should treat this case as FW initiated recovery
4163 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4164 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4165 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4167 /* To recover from error */
4168 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4173 /* Driver should poll FW heartbeat, reset_counter with the frequency
4174 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4175 * When the driver detects heartbeat stop or change in reset_counter,
4176 * it has to trigger a reset to recover from the error condition.
4177 * A “master PF” is the function who will have the privilege to
4178 * initiate the chimp reset. The master PF will be elected by the
4179 * firmware and will be notified through async message.
4181 static void bnxt_check_fw_health(void *arg)
4183 struct bnxt *bp = arg;
4184 struct bnxt_error_recovery_info *info = bp->recovery_info;
4185 uint32_t val = 0, wait_msec;
4187 if (!info || !bnxt_is_recovery_enabled(bp) ||
4188 is_bnxt_in_error(bp))
4191 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4192 if (val == info->last_heart_beat)
4195 info->last_heart_beat = val;
4197 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4198 if (val != info->last_reset_counter)
4201 info->last_reset_counter = val;
4203 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4204 bnxt_check_fw_health, (void *)bp);
4208 /* Stop DMA to/from device */
4209 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4210 bp->flags |= BNXT_FLAG_FW_RESET;
4212 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4214 if (bnxt_is_master_func(bp))
4215 wait_msec = info->master_func_wait_period;
4217 wait_msec = info->normal_func_wait_period;
4219 rte_eal_alarm_set(US_PER_MS * wait_msec,
4220 bnxt_fw_reset_cb, (void *)bp);
4223 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4225 uint32_t polling_freq;
4227 if (!bnxt_is_recovery_enabled(bp))
4230 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4233 polling_freq = bp->recovery_info->driver_polling_freq;
4235 rte_eal_alarm_set(US_PER_MS * polling_freq,
4236 bnxt_check_fw_health, (void *)bp);
4237 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4240 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4242 if (!bnxt_is_recovery_enabled(bp))
4245 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4246 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4249 static bool bnxt_vf_pciid(uint16_t device_id)
4251 switch (device_id) {
4252 case BROADCOM_DEV_ID_57304_VF:
4253 case BROADCOM_DEV_ID_57406_VF:
4254 case BROADCOM_DEV_ID_5731X_VF:
4255 case BROADCOM_DEV_ID_5741X_VF:
4256 case BROADCOM_DEV_ID_57414_VF:
4257 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4258 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4259 case BROADCOM_DEV_ID_58802_VF:
4260 case BROADCOM_DEV_ID_57500_VF1:
4261 case BROADCOM_DEV_ID_57500_VF2:
4269 static bool bnxt_thor_device(uint16_t device_id)
4271 switch (device_id) {
4272 case BROADCOM_DEV_ID_57508:
4273 case BROADCOM_DEV_ID_57504:
4274 case BROADCOM_DEV_ID_57502:
4275 case BROADCOM_DEV_ID_57508_MF1:
4276 case BROADCOM_DEV_ID_57504_MF1:
4277 case BROADCOM_DEV_ID_57502_MF1:
4278 case BROADCOM_DEV_ID_57508_MF2:
4279 case BROADCOM_DEV_ID_57504_MF2:
4280 case BROADCOM_DEV_ID_57502_MF2:
4281 case BROADCOM_DEV_ID_57500_VF1:
4282 case BROADCOM_DEV_ID_57500_VF2:
4290 bool bnxt_stratus_device(struct bnxt *bp)
4292 uint16_t device_id = bp->pdev->id.device_id;
4294 switch (device_id) {
4295 case BROADCOM_DEV_ID_STRATUS_NIC:
4296 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4297 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4305 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4307 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4308 struct bnxt *bp = eth_dev->data->dev_private;
4310 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4311 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4312 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4313 if (!bp->bar0 || !bp->doorbell_base) {
4314 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4318 bp->eth_dev = eth_dev;
4324 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4325 struct bnxt_ctx_pg_info *ctx_pg,
4330 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4331 const struct rte_memzone *mz = NULL;
4332 char mz_name[RTE_MEMZONE_NAMESIZE];
4333 rte_iova_t mz_phys_addr;
4334 uint64_t valid_bits = 0;
4341 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4343 rmem->page_size = BNXT_PAGE_SIZE;
4344 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4345 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4346 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4348 valid_bits = PTU_PTE_VALID;
4350 if (rmem->nr_pages > 1) {
4351 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4352 "bnxt_ctx_pg_tbl%s_%x_%d",
4353 suffix, idx, bp->eth_dev->data->port_id);
4354 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4355 mz = rte_memzone_lookup(mz_name);
4357 mz = rte_memzone_reserve_aligned(mz_name,
4361 RTE_MEMZONE_SIZE_HINT_ONLY |
4362 RTE_MEMZONE_IOVA_CONTIG,
4368 memset(mz->addr, 0, mz->len);
4369 mz_phys_addr = mz->iova;
4371 rmem->pg_tbl = mz->addr;
4372 rmem->pg_tbl_map = mz_phys_addr;
4373 rmem->pg_tbl_mz = mz;
4376 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4377 suffix, idx, bp->eth_dev->data->port_id);
4378 mz = rte_memzone_lookup(mz_name);
4380 mz = rte_memzone_reserve_aligned(mz_name,
4384 RTE_MEMZONE_SIZE_HINT_ONLY |
4385 RTE_MEMZONE_IOVA_CONTIG,
4391 memset(mz->addr, 0, mz->len);
4392 mz_phys_addr = mz->iova;
4394 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4395 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4396 rmem->dma_arr[i] = mz_phys_addr + sz;
4398 if (rmem->nr_pages > 1) {
4399 if (i == rmem->nr_pages - 2 &&
4400 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4401 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4402 else if (i == rmem->nr_pages - 1 &&
4403 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4404 valid_bits |= PTU_PTE_LAST;
4406 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4412 if (rmem->vmem_size)
4413 rmem->vmem = (void **)mz->addr;
4414 rmem->dma_arr[0] = mz_phys_addr;
4418 static void bnxt_free_ctx_mem(struct bnxt *bp)
4422 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4425 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4426 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4427 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4428 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4429 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4430 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4431 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4432 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4433 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4434 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4435 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4437 for (i = 0; i < BNXT_MAX_Q; i++) {
4438 if (bp->ctx->tqm_mem[i])
4439 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4446 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4448 #define min_t(type, x, y) ({ \
4449 type __min1 = (x); \
4450 type __min2 = (y); \
4451 __min1 < __min2 ? __min1 : __min2; })
4453 #define max_t(type, x, y) ({ \
4454 type __max1 = (x); \
4455 type __max2 = (y); \
4456 __max1 > __max2 ? __max1 : __max2; })
4458 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4460 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4462 struct bnxt_ctx_pg_info *ctx_pg;
4463 struct bnxt_ctx_mem_info *ctx;
4464 uint32_t mem_size, ena, entries;
4467 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4469 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4473 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4476 ctx_pg = &ctx->qp_mem;
4477 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4478 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4479 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4483 ctx_pg = &ctx->srq_mem;
4484 ctx_pg->entries = ctx->srq_max_l2_entries;
4485 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4486 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4490 ctx_pg = &ctx->cq_mem;
4491 ctx_pg->entries = ctx->cq_max_l2_entries;
4492 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4493 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4497 ctx_pg = &ctx->vnic_mem;
4498 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4499 ctx->vnic_max_ring_table_entries;
4500 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4501 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4505 ctx_pg = &ctx->stat_mem;
4506 ctx_pg->entries = ctx->stat_max_entries;
4507 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4508 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4512 entries = ctx->qp_max_l2_entries +
4513 ctx->vnic_max_vnic_entries +
4514 ctx->tqm_min_entries_per_ring;
4515 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4516 entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4517 ctx->tqm_max_entries_per_ring);
4518 for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4519 ctx_pg = ctx->tqm_mem[i];
4520 /* use min tqm entries for now. */
4521 ctx_pg->entries = entries;
4522 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4523 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4526 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4529 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4530 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4533 "Failed to configure context mem: rc = %d\n", rc);
4535 ctx->flags |= BNXT_CTX_FLAG_INITED;
4540 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4542 struct rte_pci_device *pci_dev = bp->pdev;
4543 char mz_name[RTE_MEMZONE_NAMESIZE];
4544 const struct rte_memzone *mz = NULL;
4545 uint32_t total_alloc_len;
4546 rte_iova_t mz_phys_addr;
4548 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4551 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4552 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4553 pci_dev->addr.bus, pci_dev->addr.devid,
4554 pci_dev->addr.function, "rx_port_stats");
4555 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4556 mz = rte_memzone_lookup(mz_name);
4558 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4559 sizeof(struct rx_port_stats_ext) + 512);
4561 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4564 RTE_MEMZONE_SIZE_HINT_ONLY |
4565 RTE_MEMZONE_IOVA_CONTIG);
4569 memset(mz->addr, 0, mz->len);
4570 mz_phys_addr = mz->iova;
4572 bp->rx_mem_zone = (const void *)mz;
4573 bp->hw_rx_port_stats = mz->addr;
4574 bp->hw_rx_port_stats_map = mz_phys_addr;
4576 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4577 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4578 pci_dev->addr.bus, pci_dev->addr.devid,
4579 pci_dev->addr.function, "tx_port_stats");
4580 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4581 mz = rte_memzone_lookup(mz_name);
4583 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4584 sizeof(struct tx_port_stats_ext) + 512);
4586 mz = rte_memzone_reserve(mz_name,
4590 RTE_MEMZONE_SIZE_HINT_ONLY |
4591 RTE_MEMZONE_IOVA_CONTIG);
4595 memset(mz->addr, 0, mz->len);
4596 mz_phys_addr = mz->iova;
4598 bp->tx_mem_zone = (const void *)mz;
4599 bp->hw_tx_port_stats = mz->addr;
4600 bp->hw_tx_port_stats_map = mz_phys_addr;
4601 bp->flags |= BNXT_FLAG_PORT_STATS;
4603 /* Display extended statistics if FW supports it */
4604 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4605 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4606 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4609 bp->hw_rx_port_stats_ext = (void *)
4610 ((uint8_t *)bp->hw_rx_port_stats +
4611 sizeof(struct rx_port_stats));
4612 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4613 sizeof(struct rx_port_stats);
4614 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4616 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4617 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4618 bp->hw_tx_port_stats_ext = (void *)
4619 ((uint8_t *)bp->hw_tx_port_stats +
4620 sizeof(struct tx_port_stats));
4621 bp->hw_tx_port_stats_ext_map =
4622 bp->hw_tx_port_stats_map +
4623 sizeof(struct tx_port_stats);
4624 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4630 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4632 struct bnxt *bp = eth_dev->data->dev_private;
4635 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4636 RTE_ETHER_ADDR_LEN *
4639 if (eth_dev->data->mac_addrs == NULL) {
4640 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4644 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4648 /* Generate a random MAC address, if none was assigned by PF */
4649 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4650 bnxt_eth_hw_addr_random(bp->mac_addr);
4652 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4653 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4654 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4656 rc = bnxt_hwrm_set_mac(bp);
4658 memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4659 RTE_ETHER_ADDR_LEN);
4663 /* Copy the permanent MAC from the FUNC_QCAPS response */
4664 memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4665 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4670 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4674 /* MAC is already configured in FW */
4675 if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4678 /* Restore the old MAC configured */
4679 rc = bnxt_hwrm_set_mac(bp);
4681 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4686 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4691 #define ALLOW_FUNC(x) \
4693 uint32_t arg = (x); \
4694 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4695 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4698 /* Forward all requests if firmware is new enough */
4699 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4700 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4701 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4702 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4704 PMD_DRV_LOG(WARNING,
4705 "Firmware too old for VF mailbox functionality\n");
4706 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4710 * The following are used for driver cleanup. If we disallow these,
4711 * VF drivers can't clean up cleanly.
4713 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4714 ALLOW_FUNC(HWRM_VNIC_FREE);
4715 ALLOW_FUNC(HWRM_RING_FREE);
4716 ALLOW_FUNC(HWRM_RING_GRP_FREE);
4717 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4718 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4719 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4720 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4721 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4725 bnxt_get_svif(uint16_t port_id, bool func_svif)
4727 struct rte_eth_dev *eth_dev;
4730 eth_dev = &rte_eth_devices[port_id];
4731 bp = eth_dev->data->dev_private;
4733 return func_svif ? bp->func_svif : bp->port_svif;
4737 bnxt_get_vnic_id(uint16_t port)
4739 struct rte_eth_dev *eth_dev;
4740 struct bnxt_vnic_info *vnic;
4743 eth_dev = &rte_eth_devices[port];
4744 bp = eth_dev->data->dev_private;
4746 vnic = BNXT_GET_DEFAULT_VNIC(bp);
4748 return vnic->fw_vnic_id;
4751 static int bnxt_init_fw(struct bnxt *bp)
4758 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
4762 rc = bnxt_hwrm_func_reset(bp);
4766 rc = bnxt_hwrm_vnic_qcaps(bp);
4770 rc = bnxt_hwrm_queue_qportcfg(bp);
4774 /* Get the MAX capabilities for this function.
4775 * This function also allocates context memory for TQM rings and
4776 * informs the firmware about this allocated backing store memory.
4778 rc = bnxt_hwrm_func_qcaps(bp);
4782 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4786 bnxt_hwrm_port_mac_qcfg(bp);
4788 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4792 /* Get the adapter error recovery support info */
4793 rc = bnxt_hwrm_error_recovery_qcfg(bp);
4795 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4797 bnxt_hwrm_port_led_qcaps(bp);
4803 bnxt_init_locks(struct bnxt *bp)
4807 err = pthread_mutex_init(&bp->flow_lock, NULL);
4809 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4813 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4815 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4819 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4823 rc = bnxt_init_fw(bp);
4827 if (!reconfig_dev) {
4828 rc = bnxt_setup_mac_addr(bp->eth_dev);
4832 rc = bnxt_restore_dflt_mac(bp);
4837 bnxt_config_vf_req_fwd(bp);
4839 rc = bnxt_hwrm_func_driver_register(bp);
4841 PMD_DRV_LOG(ERR, "Failed to register driver");
4846 if (bp->pdev->max_vfs) {
4847 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4849 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4853 rc = bnxt_hwrm_allocate_pf_only(bp);
4856 "Failed to allocate PF resources");
4862 rc = bnxt_alloc_mem(bp, reconfig_dev);
4866 rc = bnxt_setup_int(bp);
4870 rc = bnxt_request_int(bp);
4874 rc = bnxt_init_locks(bp);
4882 bnxt_parse_devarg_truflow(__rte_unused const char *key,
4883 const char *value, void *opaque_arg)
4885 struct bnxt *bp = opaque_arg;
4886 unsigned long truflow;
4889 if (!value || !opaque_arg) {
4891 "Invalid parameter passed to truflow devargs.\n");
4895 truflow = strtoul(value, &end, 10);
4896 if (end == NULL || *end != '\0' ||
4897 (truflow == ULONG_MAX && errno == ERANGE)) {
4899 "Invalid parameter passed to truflow devargs.\n");
4903 if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
4905 "Invalid value passed to truflow devargs.\n");
4909 bp->truflow = truflow;
4911 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
4917 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
4919 struct rte_kvargs *kvlist;
4921 if (devargs == NULL)
4924 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
4929 * Handler for "truflow" devarg.
4930 * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1”
4932 rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
4933 bnxt_parse_devarg_truflow, bp);
4935 rte_kvargs_free(kvlist);
4939 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4941 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4942 static int version_printed;
4946 if (version_printed++ == 0)
4947 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4949 eth_dev->dev_ops = &bnxt_dev_ops;
4950 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4951 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4954 * For secondary processes, we don't initialise any further
4955 * as primary has already done this work.
4957 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4960 rte_eth_copy_pci_info(eth_dev, pci_dev);
4962 bp = eth_dev->data->dev_private;
4964 /* Parse dev arguments passed on when starting the DPDK application. */
4965 bnxt_parse_dev_args(bp, pci_dev->device.devargs);
4967 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
4969 if (bnxt_vf_pciid(pci_dev->id.device_id))
4970 bp->flags |= BNXT_FLAG_VF;
4972 if (bnxt_thor_device(pci_dev->id.device_id))
4973 bp->flags |= BNXT_FLAG_THOR_CHIP;
4975 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4976 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4977 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4978 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4979 bp->flags |= BNXT_FLAG_STINGRAY;
4981 rc = bnxt_init_board(eth_dev);
4984 "Failed to initialize board rc: %x\n", rc);
4988 rc = bnxt_alloc_hwrm_resources(bp);
4991 "Failed to allocate hwrm resource rc: %x\n", rc);
4994 rc = bnxt_init_resources(bp, false);
4998 rc = bnxt_alloc_stats_mem(bp);
5002 /* Pass the information to the rte_eth_dev_close() that it should also
5003 * release the private port resources.
5005 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5008 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5009 pci_dev->mem_resource[0].phys_addr,
5010 pci_dev->mem_resource[0].addr);
5015 bnxt_dev_uninit(eth_dev);
5020 bnxt_uninit_locks(struct bnxt *bp)
5022 pthread_mutex_destroy(&bp->flow_lock);
5023 pthread_mutex_destroy(&bp->def_cp_lock);
5027 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5032 bnxt_free_mem(bp, reconfig_dev);
5033 bnxt_hwrm_func_buf_unrgtr(bp);
5034 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5035 bp->flags &= ~BNXT_FLAG_REGISTERED;
5036 bnxt_free_ctx_mem(bp);
5037 if (!reconfig_dev) {
5038 bnxt_free_hwrm_resources(bp);
5040 if (bp->recovery_info != NULL) {
5041 rte_free(bp->recovery_info);
5042 bp->recovery_info = NULL;
5046 bnxt_uninit_locks(bp);
5047 rte_free(bp->ptp_cfg);
5053 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5055 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5058 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5060 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5061 bnxt_dev_close_op(eth_dev);
5066 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5067 struct rte_pci_device *pci_dev)
5069 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
5073 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5075 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
5076 return rte_eth_dev_pci_generic_remove(pci_dev,
5079 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5082 static struct rte_pci_driver bnxt_rte_pmd = {
5083 .id_table = bnxt_pci_id_map,
5084 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5085 .probe = bnxt_pci_probe,
5086 .remove = bnxt_pci_remove,
5090 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5092 if (strcmp(dev->device->driver->name, drv->driver.name))
5098 bool is_bnxt_supported(struct rte_eth_dev *dev)
5100 return is_device_supported(dev, &bnxt_rte_pmd);
5103 RTE_INIT(bnxt_init_log)
5105 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
5106 if (bnxt_logtype_driver >= 0)
5107 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
5110 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5111 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5112 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");