4 * Copyright(c) Broadcom Limited.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Broadcom Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 #include <rte_ethdev.h>
39 #include <rte_ethdev_pci.h>
40 #include <rte_malloc.h>
41 #include <rte_cycles.h>
45 #include "bnxt_filter.h"
46 #include "bnxt_hwrm.h"
48 #include "bnxt_ring.h"
51 #include "bnxt_stats.h"
54 #include "bnxt_vnic.h"
55 #include "hsi_struct_def_dpdk.h"
57 #define DRV_MODULE_NAME "bnxt"
58 static const char bnxt_version[] =
59 "Broadcom Cumulus driver " DRV_MODULE_NAME "\n";
61 #define PCI_VENDOR_ID_BROADCOM 0x14E4
63 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
64 #define BROADCOM_DEV_ID_57414_VF 0x16c1
65 #define BROADCOM_DEV_ID_57301 0x16c8
66 #define BROADCOM_DEV_ID_57302 0x16c9
67 #define BROADCOM_DEV_ID_57304_PF 0x16ca
68 #define BROADCOM_DEV_ID_57304_VF 0x16cb
69 #define BROADCOM_DEV_ID_57417_MF 0x16cc
70 #define BROADCOM_DEV_ID_NS2 0x16cd
71 #define BROADCOM_DEV_ID_57311 0x16ce
72 #define BROADCOM_DEV_ID_57312 0x16cf
73 #define BROADCOM_DEV_ID_57402 0x16d0
74 #define BROADCOM_DEV_ID_57404 0x16d1
75 #define BROADCOM_DEV_ID_57406_PF 0x16d2
76 #define BROADCOM_DEV_ID_57406_VF 0x16d3
77 #define BROADCOM_DEV_ID_57402_MF 0x16d4
78 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
79 #define BROADCOM_DEV_ID_57412 0x16d6
80 #define BROADCOM_DEV_ID_57414 0x16d7
81 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
82 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
83 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
84 #define BROADCOM_DEV_ID_57412_MF 0x16de
85 #define BROADCOM_DEV_ID_57314 0x16df
86 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
87 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
88 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
89 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
90 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
91 #define BROADCOM_DEV_ID_57404_MF 0x16e7
92 #define BROADCOM_DEV_ID_57406_MF 0x16e8
93 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
94 #define BROADCOM_DEV_ID_57407_MF 0x16ea
95 #define BROADCOM_DEV_ID_57414_MF 0x16ec
96 #define BROADCOM_DEV_ID_57416_MF 0x16ee
98 static const struct rte_pci_id bnxt_pci_id_map[] = {
99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
122 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
123 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
124 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
125 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
126 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
127 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
128 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
129 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
130 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
131 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
132 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
133 { .vendor_id = 0, /* sentinel */ },
136 #define BNXT_ETH_RSS_SUPPORT ( \
138 ETH_RSS_NONFRAG_IPV4_TCP | \
139 ETH_RSS_NONFRAG_IPV4_UDP | \
141 ETH_RSS_NONFRAG_IPV6_TCP | \
142 ETH_RSS_NONFRAG_IPV6_UDP)
144 /***********************/
147 * High level utility functions
150 static void bnxt_free_mem(struct bnxt *bp)
152 bnxt_free_filter_mem(bp);
153 bnxt_free_vnic_attributes(bp);
154 bnxt_free_vnic_mem(bp);
157 bnxt_free_tx_rings(bp);
158 bnxt_free_rx_rings(bp);
159 bnxt_free_def_cp_ring(bp);
162 static int bnxt_alloc_mem(struct bnxt *bp)
166 /* Default completion ring */
167 rc = bnxt_init_def_ring_struct(bp, SOCKET_ID_ANY);
171 rc = bnxt_alloc_rings(bp, 0, NULL, NULL,
172 bp->def_cp_ring, "def_cp");
176 rc = bnxt_alloc_vnic_mem(bp);
180 rc = bnxt_alloc_vnic_attributes(bp);
184 rc = bnxt_alloc_filter_mem(bp);
195 static int bnxt_init_chip(struct bnxt *bp)
197 unsigned int i, rss_idx, fw_idx;
198 struct rte_eth_link new;
201 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
203 RTE_LOG(ERR, PMD, "HWRM stat ctx alloc failure rc: %x\n", rc);
207 rc = bnxt_alloc_hwrm_rings(bp);
209 RTE_LOG(ERR, PMD, "HWRM ring alloc failure rc: %x\n", rc);
213 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
215 RTE_LOG(ERR, PMD, "HWRM ring grp alloc failure: %x\n", rc);
219 rc = bnxt_mq_rx_configure(bp);
221 RTE_LOG(ERR, PMD, "MQ mode configure failure rc: %x\n", rc);
225 /* VNIC configuration */
226 for (i = 0; i < bp->nr_vnics; i++) {
227 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
229 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
231 RTE_LOG(ERR, PMD, "HWRM vnic %d alloc failure rc: %x\n",
236 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
239 "HWRM vnic %d ctx alloc failure rc: %x\n",
244 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
246 RTE_LOG(ERR, PMD, "HWRM vnic %d cfg failure rc: %x\n",
251 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
254 "HWRM vnic %d filter failure rc: %x\n",
258 if (vnic->rss_table && vnic->hash_type) {
260 * Fill the RSS hash & redirection table with
261 * ring group ids for all VNICs
263 for (rss_idx = 0, fw_idx = 0;
264 rss_idx < HW_HASH_INDEX_SIZE;
265 rss_idx++, fw_idx++) {
266 if (vnic->fw_grp_ids[fw_idx] ==
269 vnic->rss_table[rss_idx] =
270 vnic->fw_grp_ids[fw_idx];
272 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
275 "HWRM vnic %d set RSS failure rc: %x\n",
281 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0]);
284 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
288 rc = bnxt_get_hwrm_link_config(bp, &new);
290 RTE_LOG(ERR, PMD, "HWRM Get link config failure rc: %x\n", rc);
294 if (!bp->link_info.link_up) {
295 rc = bnxt_set_hwrm_link_config(bp, true);
298 "HWRM link config failure rc: %x\n", rc);
306 bnxt_free_all_hwrm_resources(bp);
311 static int bnxt_shutdown_nic(struct bnxt *bp)
313 bnxt_free_all_hwrm_resources(bp);
314 bnxt_free_all_filters(bp);
315 bnxt_free_all_vnics(bp);
319 static int bnxt_init_nic(struct bnxt *bp)
323 bnxt_init_ring_grps(bp);
325 bnxt_init_filters(bp);
327 rc = bnxt_init_chip(bp);
335 * Device configuration and status function
338 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
339 struct rte_eth_dev_info *dev_info)
341 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
342 uint16_t max_vnics, i, j, vpool, vrxq;
344 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
347 dev_info->max_mac_addrs = MAX_NUM_MAC_ADDR;
348 dev_info->max_hash_mac_addrs = 0;
350 /* PF/VF specifics */
352 dev_info->max_vfs = bp->pdev->max_vfs;
353 dev_info->max_rx_queues = bp->max_rx_rings;
354 dev_info->max_tx_queues = bp->max_tx_rings;
355 dev_info->reta_size = bp->max_rsscos_ctx;
356 max_vnics = bp->max_vnics;
358 /* Fast path specifics */
359 dev_info->min_rx_bufsize = 1;
360 dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
362 dev_info->rx_offload_capa = 0;
363 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM |
364 DEV_TX_OFFLOAD_TCP_CKSUM |
365 DEV_TX_OFFLOAD_UDP_CKSUM |
366 DEV_TX_OFFLOAD_TCP_TSO |
367 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
368 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
369 DEV_TX_OFFLOAD_GRE_TNL_TSO |
370 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
371 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
374 dev_info->default_rxconf = (struct rte_eth_rxconf) {
380 .rx_free_thresh = 32,
384 dev_info->default_txconf = (struct rte_eth_txconf) {
390 .tx_free_thresh = 32,
392 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
393 ETH_TXQ_FLAGS_NOOFFLOADS,
395 eth_dev->data->dev_conf.intr_conf.lsc = 1;
400 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
401 * need further investigation.
405 vpool = 64; /* ETH_64_POOLS */
406 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
407 for (i = 0; i < 4; vpool >>= 1, i++) {
408 if (max_vnics > vpool) {
409 for (j = 0; j < 5; vrxq >>= 1, j++) {
410 if (dev_info->max_rx_queues > vrxq) {
416 /* Not enough resources to support VMDq */
420 /* Not enough resources to support VMDq */
424 dev_info->max_vmdq_pools = vpool;
425 dev_info->vmdq_queue_num = vrxq;
427 dev_info->vmdq_pool_base = 0;
428 dev_info->vmdq_queue_base = 0;
431 /* Configure the device based on the configuration provided */
432 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
434 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
436 bp->rx_queues = (void *)eth_dev->data->rx_queues;
437 bp->tx_queues = (void *)eth_dev->data->tx_queues;
439 /* Inherit new configurations */
440 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
441 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
442 bp->rx_cp_nr_rings = bp->rx_nr_rings;
443 bp->tx_cp_nr_rings = bp->tx_nr_rings;
445 if (eth_dev->data->dev_conf.rxmode.jumbo_frame)
447 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
448 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE;
453 rte_bnxt_atomic_write_link_status(struct rte_eth_dev *eth_dev,
454 struct rte_eth_link *link)
456 struct rte_eth_link *dst = ð_dev->data->dev_link;
457 struct rte_eth_link *src = link;
459 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
460 *(uint64_t *)src) == 0)
466 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
468 struct rte_eth_link *link = ð_dev->data->dev_link;
470 if (link->link_status)
471 RTE_LOG(INFO, PMD, "Port %d Link Up - speed %u Mbps - %s\n",
472 (uint8_t)(eth_dev->data->port_id),
473 (uint32_t)link->link_speed,
474 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
475 ("full-duplex") : ("half-duplex\n"));
477 RTE_LOG(INFO, PMD, "Port %d Link Down\n",
478 (uint8_t)(eth_dev->data->port_id));
481 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
483 bnxt_print_link_info(eth_dev);
487 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
489 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
494 rc = bnxt_init_nic(bp);
498 bnxt_link_update_op(eth_dev, 0);
502 bnxt_shutdown_nic(bp);
503 bnxt_free_tx_mbufs(bp);
504 bnxt_free_rx_mbufs(bp);
508 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
510 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
512 eth_dev->data->dev_link.link_status = 1;
513 bnxt_set_hwrm_link_config(bp, true);
517 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
519 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
521 eth_dev->data->dev_link.link_status = 0;
522 bnxt_set_hwrm_link_config(bp, false);
526 /* Unload the driver, release resources */
527 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
529 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
531 if (bp->eth_dev->data->dev_started) {
532 /* TBD: STOP HW queues DMA */
533 eth_dev->data->dev_link.link_status = 0;
535 bnxt_set_hwrm_link_config(bp, false);
536 bnxt_hwrm_port_clr_stats(bp);
537 bnxt_shutdown_nic(bp);
541 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
543 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
545 if (bp->dev_stopped == 0)
546 bnxt_dev_stop_op(eth_dev);
548 bnxt_free_tx_mbufs(bp);
549 bnxt_free_rx_mbufs(bp);
551 if (eth_dev->data->mac_addrs != NULL) {
552 rte_free(eth_dev->data->mac_addrs);
553 eth_dev->data->mac_addrs = NULL;
555 if (bp->grp_info != NULL) {
556 rte_free(bp->grp_info);
561 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
564 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
565 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
566 struct bnxt_vnic_info *vnic;
567 struct bnxt_filter_info *filter, *temp_filter;
571 * Loop through all VNICs from the specified filter flow pools to
572 * remove the corresponding MAC addr filter
574 for (i = 0; i < MAX_FF_POOLS; i++) {
575 if (!(pool_mask & (1ULL << i)))
578 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
579 filter = STAILQ_FIRST(&vnic->filter);
581 temp_filter = STAILQ_NEXT(filter, next);
582 if (filter->mac_index == index) {
583 STAILQ_REMOVE(&vnic->filter, filter,
584 bnxt_filter_info, next);
585 bnxt_hwrm_clear_filter(bp, filter);
586 filter->mac_index = INVALID_MAC_INDEX;
587 memset(&filter->l2_addr, 0,
590 &bp->free_filter_list,
593 filter = temp_filter;
599 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
600 struct ether_addr *mac_addr,
601 uint32_t index, uint32_t pool)
603 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
604 struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]);
605 struct bnxt_filter_info *filter;
608 RTE_LOG(ERR, PMD, "Cannot add MAC address to a VF interface\n");
613 RTE_LOG(ERR, PMD, "VNIC not found for pool %d!\n", pool);
616 /* Attach requested MAC address to the new l2_filter */
617 STAILQ_FOREACH(filter, &vnic->filter, next) {
618 if (filter->mac_index == index) {
620 "MAC addr already existed for pool %d\n", pool);
624 filter = bnxt_alloc_filter(bp);
626 RTE_LOG(ERR, PMD, "L2 filter alloc failed\n");
629 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
630 filter->mac_index = index;
631 memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
632 return bnxt_hwrm_set_filter(bp, vnic, filter);
635 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
638 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
639 struct rte_eth_link new;
640 unsigned int cnt = BNXT_LINK_WAIT_CNT;
642 memset(&new, 0, sizeof(new));
644 /* Retrieve link info from hardware */
645 rc = bnxt_get_hwrm_link_config(bp, &new);
647 new.link_speed = ETH_LINK_SPEED_100M;
648 new.link_duplex = ETH_LINK_FULL_DUPLEX;
650 "Failed to retrieve link rc = 0x%x!\n", rc);
653 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
655 if (!wait_to_complete)
657 } while (!new.link_status && cnt--);
660 /* Timed out or success */
661 if (new.link_status != eth_dev->data->dev_link.link_status ||
662 new.link_speed != eth_dev->data->dev_link.link_speed) {
663 rte_bnxt_atomic_write_link_status(eth_dev, &new);
664 bnxt_print_link_info(eth_dev);
670 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
672 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
673 struct bnxt_vnic_info *vnic;
675 if (bp->vnic_info == NULL)
678 vnic = &bp->vnic_info[0];
680 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
681 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
684 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
686 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
687 struct bnxt_vnic_info *vnic;
689 if (bp->vnic_info == NULL)
692 vnic = &bp->vnic_info[0];
694 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
695 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
698 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
700 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
701 struct bnxt_vnic_info *vnic;
703 if (bp->vnic_info == NULL)
706 vnic = &bp->vnic_info[0];
708 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
709 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
712 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
714 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
715 struct bnxt_vnic_info *vnic;
717 if (bp->vnic_info == NULL)
720 vnic = &bp->vnic_info[0];
722 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
723 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
726 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
727 struct rte_eth_rss_reta_entry64 *reta_conf,
730 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
731 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
732 struct bnxt_vnic_info *vnic;
735 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
738 if (reta_size != HW_HASH_INDEX_SIZE) {
739 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
740 "(%d) must equal the size supported by the hardware "
741 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
744 /* Update the RSS VNIC(s) */
745 for (i = 0; i < MAX_FF_POOLS; i++) {
746 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
747 memcpy(vnic->rss_table, reta_conf, reta_size);
749 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
755 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
756 struct rte_eth_rss_reta_entry64 *reta_conf,
759 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
760 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
761 struct rte_intr_handle *intr_handle
762 = &bp->pdev->intr_handle;
764 /* Retrieve from the default VNIC */
767 if (!vnic->rss_table)
770 if (reta_size != HW_HASH_INDEX_SIZE) {
771 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
772 "(%d) must equal the size supported by the hardware "
773 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
776 /* EW - need to revisit here copying from u64 to u16 */
777 memcpy(reta_conf, vnic->rss_table, reta_size);
779 if (rte_intr_allow_others(intr_handle)) {
780 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
781 bnxt_dev_lsc_intr_setup(eth_dev);
787 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
788 struct rte_eth_rss_conf *rss_conf)
790 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
791 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
792 struct bnxt_vnic_info *vnic;
793 uint16_t hash_type = 0;
797 * If RSS enablement were different than dev_configure,
798 * then return -EINVAL
800 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
801 if (!rss_conf->rss_hf)
804 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
807 if (rss_conf->rss_hf & ETH_RSS_IPV4)
808 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
809 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
810 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
811 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
812 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
813 if (rss_conf->rss_hf & ETH_RSS_IPV6)
814 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
815 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
816 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
817 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
818 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
820 /* Update the RSS VNIC(s) */
821 for (i = 0; i < MAX_FF_POOLS; i++) {
822 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
823 vnic->hash_type = hash_type;
826 * Use the supplied key if the key length is
827 * acceptable and the rss_key is not NULL
829 if (rss_conf->rss_key &&
830 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
831 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
832 rss_conf->rss_key_len);
834 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
840 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
841 struct rte_eth_rss_conf *rss_conf)
843 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
844 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
848 /* RSS configuration is the same for all VNICs */
849 if (vnic && vnic->rss_hash_key) {
850 if (rss_conf->rss_key) {
851 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
852 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
853 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
856 hash_types = vnic->hash_type;
857 rss_conf->rss_hf = 0;
858 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
859 rss_conf->rss_hf |= ETH_RSS_IPV4;
860 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
862 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
863 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
865 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
867 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
868 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
870 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
872 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
873 rss_conf->rss_hf |= ETH_RSS_IPV6;
874 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
876 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
877 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
879 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
881 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
882 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
884 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
888 "Unknwon RSS config from firmware (%08x), RSS disabled",
893 rss_conf->rss_hf = 0;
898 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
899 struct rte_eth_fc_conf *fc_conf)
901 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
902 struct rte_eth_link link_info;
905 rc = bnxt_get_hwrm_link_config(bp, &link_info);
909 memset(fc_conf, 0, sizeof(*fc_conf));
910 if (bp->link_info.auto_pause)
911 fc_conf->autoneg = 1;
912 switch (bp->link_info.pause) {
914 fc_conf->mode = RTE_FC_NONE;
916 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
917 fc_conf->mode = RTE_FC_TX_PAUSE;
919 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
920 fc_conf->mode = RTE_FC_RX_PAUSE;
922 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
923 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
924 fc_conf->mode = RTE_FC_FULL;
930 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
931 struct rte_eth_fc_conf *fc_conf)
933 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
935 if (BNXT_NPAR_PF(bp) || BNXT_VF(bp)) {
936 RTE_LOG(ERR, PMD, "Flow Control Settings cannot be modified\n");
940 switch (fc_conf->mode) {
942 bp->link_info.auto_pause = 0;
943 bp->link_info.force_pause = 0;
945 case RTE_FC_RX_PAUSE:
946 if (fc_conf->autoneg) {
947 bp->link_info.auto_pause =
948 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
949 bp->link_info.force_pause = 0;
951 bp->link_info.auto_pause = 0;
952 bp->link_info.force_pause =
953 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
956 case RTE_FC_TX_PAUSE:
957 if (fc_conf->autoneg) {
958 bp->link_info.auto_pause =
959 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
960 bp->link_info.force_pause = 0;
962 bp->link_info.auto_pause = 0;
963 bp->link_info.force_pause =
964 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
968 if (fc_conf->autoneg) {
969 bp->link_info.auto_pause =
970 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
971 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
972 bp->link_info.force_pause = 0;
974 bp->link_info.auto_pause = 0;
975 bp->link_info.force_pause =
976 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
977 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
981 return bnxt_set_hwrm_link_config(bp, true);
984 /* Add UDP tunneling port */
986 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
987 struct rte_eth_udp_tunnel *udp_tunnel)
989 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
990 uint16_t tunnel_type = 0;
993 switch (udp_tunnel->prot_type) {
994 case RTE_TUNNEL_TYPE_VXLAN:
995 if (bp->vxlan_port_cnt) {
996 RTE_LOG(ERR, PMD, "Tunnel Port %d already programmed\n",
997 udp_tunnel->udp_port);
998 if (bp->vxlan_port != udp_tunnel->udp_port) {
999 RTE_LOG(ERR, PMD, "Only one port allowed\n");
1002 bp->vxlan_port_cnt++;
1006 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1007 bp->vxlan_port_cnt++;
1009 case RTE_TUNNEL_TYPE_GENEVE:
1010 if (bp->geneve_port_cnt) {
1011 RTE_LOG(ERR, PMD, "Tunnel Port %d already programmed\n",
1012 udp_tunnel->udp_port);
1013 if (bp->geneve_port != udp_tunnel->udp_port) {
1014 RTE_LOG(ERR, PMD, "Only one port allowed\n");
1017 bp->geneve_port_cnt++;
1021 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1022 bp->geneve_port_cnt++;
1025 RTE_LOG(ERR, PMD, "Tunnel type is not supported\n");
1028 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1034 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1035 struct rte_eth_udp_tunnel *udp_tunnel)
1037 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1038 uint16_t tunnel_type = 0;
1042 switch (udp_tunnel->prot_type) {
1043 case RTE_TUNNEL_TYPE_VXLAN:
1044 if (!bp->vxlan_port_cnt) {
1045 RTE_LOG(ERR, PMD, "No Tunnel port configured yet\n");
1048 if (bp->vxlan_port != udp_tunnel->udp_port) {
1049 RTE_LOG(ERR, PMD, "Req Port: %d. Configured port: %d\n",
1050 udp_tunnel->udp_port, bp->vxlan_port);
1053 if (--bp->vxlan_port_cnt)
1057 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1058 port = bp->vxlan_fw_dst_port_id;
1060 case RTE_TUNNEL_TYPE_GENEVE:
1061 if (!bp->geneve_port_cnt) {
1062 RTE_LOG(ERR, PMD, "No Tunnel port configured yet\n");
1065 if (bp->geneve_port != udp_tunnel->udp_port) {
1066 RTE_LOG(ERR, PMD, "Req Port: %d. Configured port: %d\n",
1067 udp_tunnel->udp_port, bp->geneve_port);
1070 if (--bp->geneve_port_cnt)
1074 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1075 port = bp->geneve_fw_dst_port_id;
1078 RTE_LOG(ERR, PMD, "Tunnel type is not supported\n");
1082 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1085 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1088 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1089 bp->geneve_port = 0;
1098 static const struct eth_dev_ops bnxt_dev_ops = {
1099 .dev_infos_get = bnxt_dev_info_get_op,
1100 .dev_close = bnxt_dev_close_op,
1101 .dev_configure = bnxt_dev_configure_op,
1102 .dev_start = bnxt_dev_start_op,
1103 .dev_stop = bnxt_dev_stop_op,
1104 .dev_set_link_up = bnxt_dev_set_link_up_op,
1105 .dev_set_link_down = bnxt_dev_set_link_down_op,
1106 .stats_get = bnxt_stats_get_op,
1107 .stats_reset = bnxt_stats_reset_op,
1108 .rx_queue_setup = bnxt_rx_queue_setup_op,
1109 .rx_queue_release = bnxt_rx_queue_release_op,
1110 .tx_queue_setup = bnxt_tx_queue_setup_op,
1111 .tx_queue_release = bnxt_tx_queue_release_op,
1112 .reta_update = bnxt_reta_update_op,
1113 .reta_query = bnxt_reta_query_op,
1114 .rss_hash_update = bnxt_rss_hash_update_op,
1115 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
1116 .link_update = bnxt_link_update_op,
1117 .promiscuous_enable = bnxt_promiscuous_enable_op,
1118 .promiscuous_disable = bnxt_promiscuous_disable_op,
1119 .allmulticast_enable = bnxt_allmulticast_enable_op,
1120 .allmulticast_disable = bnxt_allmulticast_disable_op,
1121 .mac_addr_add = bnxt_mac_addr_add_op,
1122 .mac_addr_remove = bnxt_mac_addr_remove_op,
1123 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
1124 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
1125 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
1126 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
1127 .xstats_get = bnxt_dev_xstats_get_op,
1128 .xstats_get_names = bnxt_dev_xstats_get_names_op,
1129 .xstats_reset = bnxt_dev_xstats_reset_op,
1132 static bool bnxt_vf_pciid(uint16_t id)
1134 if (id == BROADCOM_DEV_ID_57304_VF ||
1135 id == BROADCOM_DEV_ID_57406_VF ||
1136 id == BROADCOM_DEV_ID_5731X_VF ||
1137 id == BROADCOM_DEV_ID_5741X_VF ||
1138 id == BROADCOM_DEV_ID_57414_VF)
1143 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
1145 struct bnxt *bp = eth_dev->data->dev_private;
1146 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1149 /* enable device (incl. PCI PM wakeup), and bus-mastering */
1150 if (!pci_dev->mem_resource[0].addr) {
1152 "Cannot find PCI device base address, aborting\n");
1154 goto init_err_disable;
1157 bp->eth_dev = eth_dev;
1160 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
1162 RTE_LOG(ERR, PMD, "Cannot map device registers, aborting\n");
1164 goto init_err_release;
1177 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
1179 #define ALLOW_FUNC(x) \
1181 typeof(x) arg = (x); \
1182 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
1183 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
1186 bnxt_dev_init(struct rte_eth_dev *eth_dev)
1188 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1189 char mz_name[RTE_MEMZONE_NAMESIZE];
1190 const struct rte_memzone *mz = NULL;
1191 static int version_printed;
1192 uint32_t total_alloc_len;
1193 phys_addr_t mz_phys_addr;
1197 if (version_printed++ == 0)
1198 RTE_LOG(INFO, PMD, "%s\n", bnxt_version);
1200 rte_eth_copy_pci_info(eth_dev, pci_dev);
1201 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1203 bp = eth_dev->data->dev_private;
1204 bp->dev_stopped = 1;
1206 if (bnxt_vf_pciid(pci_dev->id.device_id))
1207 bp->flags |= BNXT_FLAG_VF;
1209 rc = bnxt_init_board(eth_dev);
1212 "Board initialization failed rc: %x\n", rc);
1215 eth_dev->dev_ops = &bnxt_dev_ops;
1216 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
1217 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
1219 if (BNXT_PF(bp) && pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) {
1220 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
1221 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
1222 pci_dev->addr.bus, pci_dev->addr.devid,
1223 pci_dev->addr.function, "rx_port_stats");
1224 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
1225 mz = rte_memzone_lookup(mz_name);
1226 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
1227 sizeof(struct rx_port_stats) + 512);
1229 mz = rte_memzone_reserve(mz_name, total_alloc_len,
1232 RTE_MEMZONE_SIZE_HINT_ONLY);
1236 memset(mz->addr, 0, mz->len);
1237 mz_phys_addr = mz->phys_addr;
1238 if ((unsigned long)mz->addr == mz_phys_addr) {
1239 RTE_LOG(WARNING, PMD,
1240 "Memzone physical address same as virtual.\n");
1241 RTE_LOG(WARNING, PMD,
1242 "Using rte_mem_virt2phy()\n");
1243 mz_phys_addr = rte_mem_virt2phy(mz->addr);
1244 if (mz_phys_addr == 0) {
1246 "unable to map address to physical memory\n");
1251 bp->rx_mem_zone = (const void *)mz;
1252 bp->hw_rx_port_stats = mz->addr;
1253 bp->hw_rx_port_stats_map = mz_phys_addr;
1255 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
1256 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
1257 pci_dev->addr.bus, pci_dev->addr.devid,
1258 pci_dev->addr.function, "tx_port_stats");
1259 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
1260 mz = rte_memzone_lookup(mz_name);
1261 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
1262 sizeof(struct tx_port_stats) + 512);
1264 mz = rte_memzone_reserve(mz_name, total_alloc_len,
1267 RTE_MEMZONE_SIZE_HINT_ONLY);
1271 memset(mz->addr, 0, mz->len);
1272 mz_phys_addr = mz->phys_addr;
1273 if ((unsigned long)mz->addr == mz_phys_addr) {
1274 RTE_LOG(WARNING, PMD,
1275 "Memzone physical address same as virtual.\n");
1276 RTE_LOG(WARNING, PMD,
1277 "Using rte_mem_virt2phy()\n");
1278 mz_phys_addr = rte_mem_virt2phy(mz->addr);
1279 if (mz_phys_addr == 0) {
1281 "unable to map address to physical memory\n");
1286 bp->tx_mem_zone = (const void *)mz;
1287 bp->hw_tx_port_stats = mz->addr;
1288 bp->hw_tx_port_stats_map = mz_phys_addr;
1290 bp->flags |= BNXT_FLAG_PORT_STATS;
1293 rc = bnxt_alloc_hwrm_resources(bp);
1296 "hwrm resource allocation failure rc: %x\n", rc);
1299 rc = bnxt_hwrm_ver_get(bp);
1302 bnxt_hwrm_queue_qportcfg(bp);
1304 bnxt_hwrm_func_qcfg(bp);
1306 /* Get the MAX capabilities for this function */
1307 rc = bnxt_hwrm_func_qcaps(bp);
1309 RTE_LOG(ERR, PMD, "hwrm query capability failure rc: %x\n", rc);
1312 if (bp->max_tx_rings == 0) {
1313 RTE_LOG(ERR, PMD, "No TX rings available!\n");
1317 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
1318 ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR, 0);
1319 if (eth_dev->data->mac_addrs == NULL) {
1321 "Failed to alloc %u bytes needed to store MAC addr tbl",
1322 ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR);
1326 /* Copy the permanent MAC from the qcap response address now. */
1327 memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr));
1328 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
1329 bp->grp_info = rte_zmalloc("bnxt_grp_info",
1330 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
1331 if (!bp->grp_info) {
1333 "Failed to alloc %zu bytes needed to store group info table\n",
1334 sizeof(*bp->grp_info) * bp->max_ring_grps);
1339 /* Forward all requests if firmware is new enough */
1340 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
1341 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
1342 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
1343 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
1345 RTE_LOG(WARNING, PMD,
1346 "Firmware too old for VF mailbox functionality\n");
1347 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
1351 * The following are used for driver cleanup. If we disallow these,
1352 * VF drivers can't clean up cleanly.
1354 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
1355 ALLOW_FUNC(HWRM_VNIC_FREE);
1356 ALLOW_FUNC(HWRM_RING_FREE);
1357 ALLOW_FUNC(HWRM_RING_GRP_FREE);
1358 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
1359 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
1360 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
1361 rc = bnxt_hwrm_func_driver_register(bp);
1364 "Failed to register driver");
1370 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
1371 pci_dev->mem_resource[0].phys_addr,
1372 pci_dev->mem_resource[0].addr);
1374 rc = bnxt_hwrm_func_reset(bp);
1376 RTE_LOG(ERR, PMD, "hwrm chip reset failure rc: %x\n", rc);
1382 //if (bp->pf.active_vfs) {
1383 // TODO: Deallocate VF resources?
1385 if (bp->pdev->max_vfs) {
1386 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
1388 RTE_LOG(ERR, PMD, "Failed to allocate VFs\n");
1392 rc = bnxt_hwrm_allocate_pf_only(bp);
1395 "Failed to allocate PF resources\n");
1401 rc = bnxt_setup_int(bp);
1405 rc = bnxt_alloc_mem(bp);
1407 goto error_free_int;
1409 rc = bnxt_request_int(bp);
1411 goto error_free_int;
1413 rc = bnxt_alloc_def_cp_ring(bp);
1415 goto error_free_int;
1417 bnxt_enable_int(bp);
1422 bnxt_disable_int(bp);
1423 bnxt_free_def_cp_ring(bp);
1424 bnxt_hwrm_func_buf_unrgtr(bp);
1428 bnxt_dev_uninit(eth_dev);
1434 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) {
1435 struct bnxt *bp = eth_dev->data->dev_private;
1438 bnxt_disable_int(bp);
1441 if (eth_dev->data->mac_addrs != NULL) {
1442 rte_free(eth_dev->data->mac_addrs);
1443 eth_dev->data->mac_addrs = NULL;
1445 if (bp->grp_info != NULL) {
1446 rte_free(bp->grp_info);
1447 bp->grp_info = NULL;
1449 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
1450 bnxt_free_hwrm_resources(bp);
1451 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1452 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1453 if (bp->dev_stopped == 0)
1454 bnxt_dev_close_op(eth_dev);
1456 rte_free(bp->pf.vf_info);
1457 eth_dev->dev_ops = NULL;
1458 eth_dev->rx_pkt_burst = NULL;
1459 eth_dev->tx_pkt_burst = NULL;
1464 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg)
1466 struct rte_pmd_bnxt_mb_event_param cb_param;
1468 cb_param.retval = RTE_PMD_BNXT_MB_EVENT_PROCEED;
1469 cb_param.vf_id = vf_id;
1472 _rte_eth_dev_callback_process(bp->eth_dev, RTE_ETH_EVENT_VF_MBOX,
1475 /* Default to approve */
1476 if (cb_param.retval == RTE_PMD_BNXT_MB_EVENT_PROCEED)
1477 cb_param.retval = RTE_PMD_BNXT_MB_EVENT_NOOP_ACK;
1479 return cb_param.retval == RTE_PMD_BNXT_MB_EVENT_NOOP_ACK ? true : false;
1482 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1483 struct rte_pci_device *pci_dev)
1485 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
1489 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
1491 return rte_eth_dev_pci_generic_remove(pci_dev, bnxt_dev_uninit);
1494 static struct rte_pci_driver bnxt_rte_pmd = {
1495 .id_table = bnxt_pci_id_map,
1496 .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
1497 RTE_PCI_DRV_INTR_LSC,
1498 .probe = bnxt_pci_probe,
1499 .remove = bnxt_pci_remove,
1502 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
1503 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
1504 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");