1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2021 Broadcom
10 #include <ethdev_driver.h>
11 #include <ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
15 #include <rte_kvargs.h>
19 #include "bnxt_filter.h"
20 #include "bnxt_hwrm.h"
22 #include "bnxt_reps.h"
23 #include "bnxt_ring.h"
26 #include "bnxt_stats.h"
29 #include "bnxt_vnic.h"
30 #include "hsi_struct_def_dpdk.h"
31 #include "bnxt_nvm_defs.h"
32 #include "bnxt_tf_common.h"
33 #include "ulp_flow_db.h"
34 #include "rte_pmd_bnxt.h"
36 #define DRV_MODULE_NAME "bnxt"
37 static const char bnxt_version[] =
38 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
41 * The set of PCI devices this driver supports
43 static const struct rte_pci_id bnxt_pci_id_map[] = {
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
45 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
47 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
87 { .vendor_id = 0, /* sentinel */ },
90 #define BNXT_DEVARG_ACCUM_STATS "accum-stats"
91 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat"
92 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows"
93 #define BNXT_DEVARG_REPRESENTOR "representor"
94 #define BNXT_DEVARG_REP_BASED_PF "rep-based-pf"
95 #define BNXT_DEVARG_REP_IS_PF "rep-is-pf"
96 #define BNXT_DEVARG_REP_Q_R2F "rep-q-r2f"
97 #define BNXT_DEVARG_REP_Q_F2R "rep-q-f2r"
98 #define BNXT_DEVARG_REP_FC_R2F "rep-fc-r2f"
99 #define BNXT_DEVARG_REP_FC_F2R "rep-fc-f2r"
100 #define BNXT_DEVARG_APP_ID "app-id"
102 static const char *const bnxt_dev_args[] = {
103 BNXT_DEVARG_REPRESENTOR,
104 BNXT_DEVARG_ACCUM_STATS,
105 BNXT_DEVARG_FLOW_XSTAT,
106 BNXT_DEVARG_MAX_NUM_KFLOWS,
107 BNXT_DEVARG_REP_BASED_PF,
108 BNXT_DEVARG_REP_IS_PF,
109 BNXT_DEVARG_REP_Q_R2F,
110 BNXT_DEVARG_REP_Q_F2R,
111 BNXT_DEVARG_REP_FC_R2F,
112 BNXT_DEVARG_REP_FC_F2R,
118 * accum-stats == false to disable flow counter accumulation
119 * accum-stats == true to enable flow counter accumulation
121 #define BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats) ((accum_stats) > 1)
124 * app-id = an non-negative 8-bit number
126 #define BNXT_DEVARG_APP_ID_INVALID(val) ((val) > 255)
129 * flow_xstat == false to disable the feature
130 * flow_xstat == true to enable the feature
132 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1)
135 * rep_is_pf == false to indicate VF representor
136 * rep_is_pf == true to indicate PF representor
138 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf) ((rep_is_pf) > 1)
141 * rep_based_pf == Physical index of the PF
143 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf) ((rep_based_pf) > 15)
145 * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
147 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f) ((rep_q_r2f) > 3)
150 * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
152 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r) ((rep_q_f2r) > 3)
155 * rep_fc_r2f == Flow control for the representor to endpoint direction
157 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f) ((rep_fc_r2f) > 1)
160 * rep_fc_f2r == Flow control for the endpoint to representor direction
162 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r) ((rep_fc_f2r) > 1)
164 int bnxt_cfa_code_dynfield_offset = -1;
167 * max_num_kflows must be >= 32
168 * and must be a power-of-2 supported value
169 * return: 1 -> invalid
172 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
174 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
179 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
180 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
181 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
182 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
183 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
184 static int bnxt_restore_vlan_filters(struct bnxt *bp);
185 static void bnxt_dev_recover(void *arg);
186 static void bnxt_free_error_recovery_info(struct bnxt *bp);
187 static void bnxt_free_rep_info(struct bnxt *bp);
189 int is_bnxt_in_error(struct bnxt *bp)
191 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
193 if (bp->flags & BNXT_FLAG_FW_RESET)
199 /***********************/
202 * High level utility functions
205 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
207 unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
208 BNXT_RSS_TBL_SIZE_P5);
210 if (!BNXT_CHIP_P5(bp))
213 return RTE_ALIGN_MUL_CEIL(num_rss_rings,
214 BNXT_RSS_ENTRIES_PER_CTX_P5) /
215 BNXT_RSS_ENTRIES_PER_CTX_P5;
218 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
220 if (!BNXT_CHIP_P5(bp))
221 return HW_HASH_INDEX_SIZE;
223 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
226 static void bnxt_free_parent_info(struct bnxt *bp)
228 rte_free(bp->parent);
232 static void bnxt_free_pf_info(struct bnxt *bp)
238 static void bnxt_free_link_info(struct bnxt *bp)
240 rte_free(bp->link_info);
241 bp->link_info = NULL;
244 static void bnxt_free_leds_info(struct bnxt *bp)
253 static void bnxt_free_flow_stats_info(struct bnxt *bp)
255 rte_free(bp->flow_stat);
256 bp->flow_stat = NULL;
259 static void bnxt_free_cos_queues(struct bnxt *bp)
261 rte_free(bp->rx_cos_queue);
262 bp->rx_cos_queue = NULL;
263 rte_free(bp->tx_cos_queue);
264 bp->tx_cos_queue = NULL;
267 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
269 bnxt_free_filter_mem(bp);
270 bnxt_free_vnic_attributes(bp);
271 bnxt_free_vnic_mem(bp);
273 /* tx/rx rings are configured as part of *_queue_setup callbacks.
274 * If the number of rings change across fw update,
275 * we don't have much choice except to warn the user.
279 bnxt_free_tx_rings(bp);
280 bnxt_free_rx_rings(bp);
282 bnxt_free_async_cp_ring(bp);
283 bnxt_free_rxtx_nq_ring(bp);
285 rte_free(bp->grp_info);
289 static int bnxt_alloc_parent_info(struct bnxt *bp)
291 bp->parent = rte_zmalloc("bnxt_parent_info",
292 sizeof(struct bnxt_parent_info), 0);
293 if (bp->parent == NULL)
299 static int bnxt_alloc_pf_info(struct bnxt *bp)
301 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
308 static int bnxt_alloc_link_info(struct bnxt *bp)
311 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
312 if (bp->link_info == NULL)
318 static int bnxt_alloc_leds_info(struct bnxt *bp)
323 bp->leds = rte_zmalloc("bnxt_leds",
324 BNXT_MAX_LED * sizeof(struct bnxt_led_info),
326 if (bp->leds == NULL)
332 static int bnxt_alloc_cos_queues(struct bnxt *bp)
335 rte_zmalloc("bnxt_rx_cosq",
336 BNXT_COS_QUEUE_COUNT *
337 sizeof(struct bnxt_cos_queue_info),
339 if (bp->rx_cos_queue == NULL)
343 rte_zmalloc("bnxt_tx_cosq",
344 BNXT_COS_QUEUE_COUNT *
345 sizeof(struct bnxt_cos_queue_info),
347 if (bp->tx_cos_queue == NULL)
353 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
355 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
356 sizeof(struct bnxt_flow_stat_info), 0);
357 if (bp->flow_stat == NULL)
363 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
367 rc = bnxt_alloc_ring_grps(bp);
371 rc = bnxt_alloc_async_ring_struct(bp);
375 rc = bnxt_alloc_vnic_mem(bp);
379 rc = bnxt_alloc_vnic_attributes(bp);
383 rc = bnxt_alloc_filter_mem(bp);
387 rc = bnxt_alloc_async_cp_ring(bp);
391 rc = bnxt_alloc_rxtx_nq_ring(bp);
395 if (BNXT_FLOW_XSTATS_EN(bp)) {
396 rc = bnxt_alloc_flow_stats_info(bp);
404 bnxt_free_mem(bp, reconfig);
408 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
410 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
411 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
412 uint64_t rx_offloads = dev_conf->rxmode.offloads;
413 struct bnxt_rx_queue *rxq;
417 rc = bnxt_vnic_grp_alloc(bp, vnic);
421 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
422 vnic_id, vnic, vnic->fw_grp_ids);
424 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
428 /* Alloc RSS context only if RSS mode is enabled */
429 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
430 int j, nr_ctxs = bnxt_rss_ctxts(bp);
432 /* RSS table size in Thor is 512.
433 * Cap max Rx rings to same value
435 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
436 PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
437 bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
442 for (j = 0; j < nr_ctxs; j++) {
443 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
449 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
453 vnic->num_lb_ctxts = nr_ctxs;
457 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
458 * setting is not available at this time, it will not be
459 * configured correctly in the CFA.
461 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
462 vnic->vlan_strip = true;
464 vnic->vlan_strip = false;
466 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
470 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
474 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
475 rxq = bp->eth_dev->data->rx_queues[j];
478 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
479 j, rxq->vnic, rxq->vnic->fw_grp_ids);
481 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
482 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
484 vnic->rx_queue_cnt++;
487 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
489 rc = bnxt_vnic_rss_configure(bp, vnic);
493 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
495 rc = bnxt_hwrm_vnic_tpa_cfg(bp, vnic,
496 (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) ?
503 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
508 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
512 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
513 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
518 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
519 " rx_fc_in_tbl.ctx_id = %d\n",
520 bp->flow_stat->rx_fc_in_tbl.va,
521 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
522 bp->flow_stat->rx_fc_in_tbl.ctx_id);
524 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
525 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
530 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
531 " rx_fc_out_tbl.ctx_id = %d\n",
532 bp->flow_stat->rx_fc_out_tbl.va,
533 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
534 bp->flow_stat->rx_fc_out_tbl.ctx_id);
536 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
537 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
542 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
543 " tx_fc_in_tbl.ctx_id = %d\n",
544 bp->flow_stat->tx_fc_in_tbl.va,
545 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
546 bp->flow_stat->tx_fc_in_tbl.ctx_id);
548 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
549 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
554 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
555 " tx_fc_out_tbl.ctx_id = %d\n",
556 bp->flow_stat->tx_fc_out_tbl.va,
557 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
558 bp->flow_stat->tx_fc_out_tbl.ctx_id);
560 memset(bp->flow_stat->rx_fc_out_tbl.va,
562 bp->flow_stat->rx_fc_out_tbl.size);
563 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
564 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
565 bp->flow_stat->rx_fc_out_tbl.ctx_id,
566 bp->flow_stat->max_fc,
571 memset(bp->flow_stat->tx_fc_out_tbl.va,
573 bp->flow_stat->tx_fc_out_tbl.size);
574 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
575 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
576 bp->flow_stat->tx_fc_out_tbl.ctx_id,
577 bp->flow_stat->max_fc,
583 static int bnxt_alloc_ctx_mem_buf(struct bnxt *bp, char *type, size_t size,
584 struct bnxt_ctx_mem_buf_info *ctx)
589 ctx->va = rte_zmalloc_socket(type, size, 0,
590 bp->eth_dev->device->numa_node);
593 rte_mem_lock_page(ctx->va);
595 ctx->dma = rte_mem_virt2iova(ctx->va);
596 if (ctx->dma == RTE_BAD_IOVA)
602 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
604 struct rte_pci_device *pdev = bp->pdev;
605 char type[RTE_MEMZONE_NAMESIZE];
609 max_fc = bp->flow_stat->max_fc;
611 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
612 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
613 /* 4 bytes for each counter-id */
614 rc = bnxt_alloc_ctx_mem_buf(bp, type,
616 &bp->flow_stat->rx_fc_in_tbl);
620 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
621 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
622 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
623 rc = bnxt_alloc_ctx_mem_buf(bp, type,
625 &bp->flow_stat->rx_fc_out_tbl);
629 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
630 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
631 /* 4 bytes for each counter-id */
632 rc = bnxt_alloc_ctx_mem_buf(bp, type,
634 &bp->flow_stat->tx_fc_in_tbl);
638 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
639 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
640 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
641 rc = bnxt_alloc_ctx_mem_buf(bp, type,
643 &bp->flow_stat->tx_fc_out_tbl);
647 rc = bnxt_register_fc_ctx_mem(bp);
652 static int bnxt_init_ctx_mem(struct bnxt *bp)
656 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
657 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
658 !BNXT_FLOW_XSTATS_EN(bp))
661 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
665 rc = bnxt_init_fc_ctx_mem(bp);
670 static int bnxt_update_phy_setting(struct bnxt *bp)
672 struct rte_eth_link new;
675 rc = bnxt_get_hwrm_link_config(bp, &new);
677 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
682 * On BCM957508-N2100 adapters, FW will not allow any user other
683 * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
684 * always returns link up. Force phy update always in that case.
686 if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
687 rc = bnxt_set_hwrm_link_config(bp, true);
689 PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
697 static void bnxt_free_prev_ring_stats(struct bnxt *bp)
699 rte_free(bp->prev_rx_ring_stats);
700 rte_free(bp->prev_tx_ring_stats);
702 bp->prev_rx_ring_stats = NULL;
703 bp->prev_tx_ring_stats = NULL;
706 static int bnxt_alloc_prev_ring_stats(struct bnxt *bp)
708 bp->prev_rx_ring_stats = rte_zmalloc("bnxt_prev_rx_ring_stats",
709 sizeof(struct bnxt_ring_stats) *
712 if (bp->prev_rx_ring_stats == NULL)
715 bp->prev_tx_ring_stats = rte_zmalloc("bnxt_prev_tx_ring_stats",
716 sizeof(struct bnxt_ring_stats) *
719 if (bp->prev_tx_ring_stats == NULL)
725 bnxt_free_prev_ring_stats(bp);
729 static int bnxt_start_nic(struct bnxt *bp)
731 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
732 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
733 uint32_t intr_vector = 0;
734 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
735 uint32_t vec = BNXT_MISC_VEC_ID;
739 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
740 bp->eth_dev->data->dev_conf.rxmode.offloads |=
741 DEV_RX_OFFLOAD_JUMBO_FRAME;
742 bp->flags |= BNXT_FLAG_JUMBO;
744 bp->eth_dev->data->dev_conf.rxmode.offloads &=
745 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
746 bp->flags &= ~BNXT_FLAG_JUMBO;
749 /* THOR does not support ring groups.
750 * But we will use the array to save RSS context IDs.
752 if (BNXT_CHIP_P5(bp))
753 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
755 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
757 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
761 rc = bnxt_alloc_hwrm_rings(bp);
763 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
767 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
769 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
773 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
776 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
777 if (bp->rx_cos_queue[i].id != 0xff) {
778 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
782 "Num pools more than FW profile\n");
786 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
792 rc = bnxt_mq_rx_configure(bp);
794 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
799 rc = bnxt_setup_one_vnic(bp, 0);
802 /* VNIC configuration */
803 if (BNXT_RFS_NEEDS_VNIC(bp)) {
804 for (i = 1; i < bp->nr_vnics; i++) {
805 rc = bnxt_setup_one_vnic(bp, i);
811 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
814 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
818 /* check and configure queue intr-vector mapping */
819 if ((rte_intr_cap_multiple(intr_handle) ||
820 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
821 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
822 intr_vector = bp->eth_dev->data->nb_rx_queues;
823 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
824 if (intr_vector > bp->rx_cp_nr_rings) {
825 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
829 rc = rte_intr_efd_enable(intr_handle, intr_vector);
834 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
835 intr_handle->intr_vec =
836 rte_zmalloc("intr_vec",
837 bp->eth_dev->data->nb_rx_queues *
839 if (intr_handle->intr_vec == NULL) {
840 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
841 " intr_vec", bp->eth_dev->data->nb_rx_queues);
845 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
846 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
847 intr_handle->intr_vec, intr_handle->nb_efd,
848 intr_handle->max_intr);
849 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
851 intr_handle->intr_vec[queue_id] =
852 vec + BNXT_RX_VEC_START;
853 if (vec < base + intr_handle->nb_efd - 1)
858 /* enable uio/vfio intr/eventfd mapping */
859 rc = rte_intr_enable(intr_handle);
860 #ifndef RTE_EXEC_ENV_FREEBSD
861 /* In FreeBSD OS, nic_uio driver does not support interrupts */
866 rc = bnxt_update_phy_setting(bp);
870 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
872 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
877 /* Some of the error status returned by FW may not be from errno.h */
884 static int bnxt_shutdown_nic(struct bnxt *bp)
886 bnxt_free_all_hwrm_resources(bp);
887 bnxt_free_all_filters(bp);
888 bnxt_free_all_vnics(bp);
893 * Device configuration and status function
896 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
898 uint32_t link_speed = 0;
899 uint32_t speed_capa = 0;
901 if (bp->link_info == NULL)
904 link_speed = bp->link_info->support_speeds;
906 /* If PAM4 is configured, use PAM4 supported speed */
907 if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
908 link_speed = bp->link_info->support_pam4_speeds;
910 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
911 speed_capa |= ETH_LINK_SPEED_100M;
912 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
913 speed_capa |= ETH_LINK_SPEED_100M_HD;
914 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
915 speed_capa |= ETH_LINK_SPEED_1G;
916 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
917 speed_capa |= ETH_LINK_SPEED_2_5G;
918 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
919 speed_capa |= ETH_LINK_SPEED_10G;
920 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
921 speed_capa |= ETH_LINK_SPEED_20G;
922 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
923 speed_capa |= ETH_LINK_SPEED_25G;
924 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
925 speed_capa |= ETH_LINK_SPEED_40G;
926 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
927 speed_capa |= ETH_LINK_SPEED_50G;
928 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
929 speed_capa |= ETH_LINK_SPEED_100G;
930 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
931 speed_capa |= ETH_LINK_SPEED_50G;
932 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
933 speed_capa |= ETH_LINK_SPEED_100G;
934 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
935 speed_capa |= ETH_LINK_SPEED_200G;
937 if (bp->link_info->auto_mode ==
938 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
939 speed_capa |= ETH_LINK_SPEED_FIXED;
944 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
945 struct rte_eth_dev_info *dev_info)
947 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
948 struct bnxt *bp = eth_dev->data->dev_private;
949 uint16_t max_vnics, i, j, vpool, vrxq;
950 unsigned int max_rx_rings;
953 rc = is_bnxt_in_error(bp);
958 dev_info->max_mac_addrs = bp->max_l2_ctx;
959 dev_info->max_hash_mac_addrs = 0;
961 /* PF/VF specifics */
963 dev_info->max_vfs = pdev->max_vfs;
965 max_rx_rings = bnxt_max_rings(bp);
966 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
967 dev_info->max_rx_queues = max_rx_rings;
968 dev_info->max_tx_queues = max_rx_rings;
969 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
970 dev_info->hash_key_size = HW_HASH_KEY_SIZE;
971 max_vnics = bp->max_vnics;
974 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
975 dev_info->max_mtu = BNXT_MAX_MTU;
977 /* Fast path specifics */
978 dev_info->min_rx_bufsize = 1;
979 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
981 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
982 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
983 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
984 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_VLAN_RX_STRIP)
985 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_VLAN_STRIP;
986 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
987 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
988 dev_info->tx_queue_offload_capa;
989 if (bp->fw_cap & BNXT_FW_CAP_VLAN_TX_INSERT)
990 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_VLAN_INSERT;
991 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
993 dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
994 dev_info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
995 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
997 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1003 .rx_free_thresh = 32,
1004 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
1007 dev_info->default_txconf = (struct rte_eth_txconf) {
1013 .tx_free_thresh = 32,
1016 eth_dev->data->dev_conf.intr_conf.lsc = 1;
1018 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
1019 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
1020 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
1021 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
1023 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
1024 dev_info->switch_info.name = eth_dev->device->name;
1025 dev_info->switch_info.domain_id = bp->switch_domain_id;
1026 dev_info->switch_info.port_id =
1027 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
1028 BNXT_SWITCH_PORT_ID_TRUSTED_VF;
1032 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
1033 * need further investigation.
1036 /* VMDq resources */
1037 vpool = 64; /* ETH_64_POOLS */
1038 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
1039 for (i = 0; i < 4; vpool >>= 1, i++) {
1040 if (max_vnics > vpool) {
1041 for (j = 0; j < 5; vrxq >>= 1, j++) {
1042 if (dev_info->max_rx_queues > vrxq) {
1048 /* Not enough resources to support VMDq */
1052 /* Not enough resources to support VMDq */
1056 dev_info->max_vmdq_pools = vpool;
1057 dev_info->vmdq_queue_num = vrxq;
1059 dev_info->vmdq_pool_base = 0;
1060 dev_info->vmdq_queue_base = 0;
1065 /* Configure the device based on the configuration provided */
1066 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1068 struct bnxt *bp = eth_dev->data->dev_private;
1069 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1072 bp->rx_queues = (void *)eth_dev->data->rx_queues;
1073 bp->tx_queues = (void *)eth_dev->data->tx_queues;
1074 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1075 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1077 rc = is_bnxt_in_error(bp);
1081 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1082 rc = bnxt_hwrm_check_vf_rings(bp);
1084 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1088 /* If a resource has already been allocated - in this case
1089 * it is the async completion ring, free it. Reallocate it after
1090 * resource reservation. This will ensure the resource counts
1091 * are calculated correctly.
1094 pthread_mutex_lock(&bp->def_cp_lock);
1096 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1097 bnxt_disable_int(bp);
1098 bnxt_free_cp_ring(bp, bp->async_cp_ring);
1101 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1103 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1104 pthread_mutex_unlock(&bp->def_cp_lock);
1108 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1109 rc = bnxt_alloc_async_cp_ring(bp);
1111 pthread_mutex_unlock(&bp->def_cp_lock);
1114 bnxt_enable_int(bp);
1117 pthread_mutex_unlock(&bp->def_cp_lock);
1120 /* Inherit new configurations */
1121 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1122 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1123 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1124 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1125 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1127 goto resource_error;
1129 if (BNXT_HAS_RING_GRPS(bp) &&
1130 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1131 goto resource_error;
1133 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1134 bp->max_vnics < eth_dev->data->nb_rx_queues)
1135 goto resource_error;
1137 bp->rx_cp_nr_rings = bp->rx_nr_rings;
1138 bp->tx_cp_nr_rings = bp->tx_nr_rings;
1140 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1141 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1142 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1144 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1145 eth_dev->data->mtu =
1146 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1147 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1149 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1155 "Insufficient resources to support requested config\n");
1157 "Num Queues Requested: Tx %d, Rx %d\n",
1158 eth_dev->data->nb_tx_queues,
1159 eth_dev->data->nb_rx_queues);
1161 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1162 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1163 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1167 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1169 struct rte_eth_link *link = ð_dev->data->dev_link;
1171 if (link->link_status)
1172 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1173 eth_dev->data->port_id,
1174 (uint32_t)link->link_speed,
1175 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1176 ("full-duplex") : ("half-duplex\n"));
1178 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1179 eth_dev->data->port_id);
1183 * Determine whether the current configuration requires support for scattered
1184 * receive; return 1 if scattered receive is required and 0 if not.
1186 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1191 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1194 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO)
1197 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1198 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1200 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1201 RTE_PKTMBUF_HEADROOM);
1202 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1208 static eth_rx_burst_t
1209 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1211 struct bnxt *bp = eth_dev->data->dev_private;
1213 /* Disable vector mode RX for Stingray2 for now */
1214 if (BNXT_CHIP_SR2(bp)) {
1215 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1216 return bnxt_recv_pkts;
1219 #if (defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)) && \
1220 !defined(RTE_LIBRTE_IEEE1588)
1222 /* Vector mode receive cannot be enabled if scattered rx is in use. */
1223 if (eth_dev->data->scattered_rx)
1227 * Vector mode receive cannot be enabled if Truflow is enabled or if
1228 * asynchronous completions and receive completions can be placed in
1229 * the same completion ring.
1231 if (BNXT_TRUFLOW_EN(bp) || !BNXT_NUM_ASYNC_CPR(bp))
1235 * Vector mode receive cannot be enabled if any receive offloads outside
1236 * a limited subset have been enabled.
1238 if (eth_dev->data->dev_conf.rxmode.offloads &
1239 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1240 DEV_RX_OFFLOAD_KEEP_CRC |
1241 DEV_RX_OFFLOAD_JUMBO_FRAME |
1242 DEV_RX_OFFLOAD_IPV4_CKSUM |
1243 DEV_RX_OFFLOAD_UDP_CKSUM |
1244 DEV_RX_OFFLOAD_TCP_CKSUM |
1245 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1246 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1247 DEV_RX_OFFLOAD_RSS_HASH |
1248 DEV_RX_OFFLOAD_VLAN_FILTER))
1251 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1252 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1253 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1255 "Using AVX2 vector mode receive for port %d\n",
1256 eth_dev->data->port_id);
1257 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1258 return bnxt_recv_pkts_vec_avx2;
1261 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1263 "Using SSE vector mode receive for port %d\n",
1264 eth_dev->data->port_id);
1265 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1266 return bnxt_recv_pkts_vec;
1270 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1271 eth_dev->data->port_id);
1273 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1274 eth_dev->data->port_id,
1275 eth_dev->data->scattered_rx,
1276 eth_dev->data->dev_conf.rxmode.offloads);
1278 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1279 return bnxt_recv_pkts;
1282 static eth_tx_burst_t
1283 bnxt_transmit_function(struct rte_eth_dev *eth_dev)
1285 struct bnxt *bp = eth_dev->data->dev_private;
1287 /* Disable vector mode TX for Stingray2 for now */
1288 if (BNXT_CHIP_SR2(bp))
1289 return bnxt_xmit_pkts;
1291 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) && \
1292 !defined(RTE_LIBRTE_IEEE1588)
1293 uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1296 * Vector mode transmit can be enabled only if not using scatter rx
1299 if (eth_dev->data->scattered_rx ||
1300 (offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) ||
1301 BNXT_TRUFLOW_EN(bp))
1304 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1305 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1306 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1308 "Using AVX2 vector mode transmit for port %d\n",
1309 eth_dev->data->port_id);
1310 return bnxt_xmit_pkts_vec_avx2;
1313 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1315 "Using SSE vector mode transmit for port %d\n",
1316 eth_dev->data->port_id);
1317 return bnxt_xmit_pkts_vec;
1321 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1322 eth_dev->data->port_id);
1324 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1325 eth_dev->data->port_id,
1326 eth_dev->data->scattered_rx,
1329 return bnxt_xmit_pkts;
1332 static int bnxt_handle_if_change_status(struct bnxt *bp)
1336 /* Since fw has undergone a reset and lost all contexts,
1337 * set fatal flag to not issue hwrm during cleanup
1339 bp->flags |= BNXT_FLAG_FATAL_ERROR;
1340 bnxt_uninit_resources(bp, true);
1342 /* clear fatal flag so that re-init happens */
1343 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1344 rc = bnxt_init_resources(bp, true);
1346 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1351 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1353 struct bnxt *bp = eth_dev->data->dev_private;
1356 if (!BNXT_SINGLE_PF(bp))
1359 if (!bp->link_info->link_up)
1360 rc = bnxt_set_hwrm_link_config(bp, true);
1362 eth_dev->data->dev_link.link_status = 1;
1364 bnxt_print_link_info(eth_dev);
1368 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1370 struct bnxt *bp = eth_dev->data->dev_private;
1372 if (!BNXT_SINGLE_PF(bp))
1375 eth_dev->data->dev_link.link_status = 0;
1376 bnxt_set_hwrm_link_config(bp, false);
1377 bp->link_info->link_up = 0;
1382 static void bnxt_free_switch_domain(struct bnxt *bp)
1386 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)))
1389 rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1391 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1392 bp->switch_domain_id, rc);
1395 static void bnxt_ptp_get_current_time(void *arg)
1397 struct bnxt *bp = arg;
1398 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1401 rc = is_bnxt_in_error(bp);
1408 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1409 &ptp->current_time);
1411 rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1413 PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n");
1414 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1418 static int bnxt_schedule_ptp_alarm(struct bnxt *bp)
1420 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1423 if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED)
1426 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1427 &ptp->current_time);
1429 rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1433 static void bnxt_cancel_ptp_alarm(struct bnxt *bp)
1435 if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) {
1436 rte_eal_alarm_cancel(bnxt_ptp_get_current_time, (void *)bp);
1437 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1441 static void bnxt_ptp_stop(struct bnxt *bp)
1443 bnxt_cancel_ptp_alarm(bp);
1444 bp->flags2 &= ~BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1447 static int bnxt_ptp_start(struct bnxt *bp)
1451 rc = bnxt_schedule_ptp_alarm(bp);
1453 PMD_DRV_LOG(ERR, "Failed to schedule PTP alarm\n");
1455 bp->flags2 |= BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1456 bp->flags2 |= BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1462 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev)
1464 struct bnxt *bp = eth_dev->data->dev_private;
1465 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1466 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1467 struct rte_eth_link link;
1470 eth_dev->data->dev_started = 0;
1471 eth_dev->data->scattered_rx = 0;
1473 /* Prevent crashes when queues are still in use */
1474 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1475 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1477 bnxt_disable_int(bp);
1479 /* disable uio/vfio intr/eventfd mapping */
1480 rte_intr_disable(intr_handle);
1482 /* Stop the child representors for this device */
1483 ret = bnxt_rep_stop_all(bp);
1487 /* delete the bnxt ULP port details */
1488 bnxt_ulp_port_deinit(bp);
1490 bnxt_cancel_fw_health_check(bp);
1492 if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1493 bnxt_cancel_ptp_alarm(bp);
1495 /* Do not bring link down during reset recovery */
1496 if (!is_bnxt_in_error(bp)) {
1497 bnxt_dev_set_link_down_op(eth_dev);
1498 /* Wait for link to be reset */
1499 if (BNXT_SINGLE_PF(bp))
1501 /* clear the recorded link status */
1502 memset(&link, 0, sizeof(link));
1503 rte_eth_linkstatus_set(eth_dev, &link);
1506 /* Clean queue intr-vector mapping */
1507 rte_intr_efd_disable(intr_handle);
1508 if (intr_handle->intr_vec != NULL) {
1509 rte_free(intr_handle->intr_vec);
1510 intr_handle->intr_vec = NULL;
1513 bnxt_hwrm_port_clr_stats(bp);
1514 bnxt_free_tx_mbufs(bp);
1515 bnxt_free_rx_mbufs(bp);
1516 /* Process any remaining notifications in default completion queue */
1517 bnxt_int_handler(eth_dev);
1518 bnxt_shutdown_nic(bp);
1519 bnxt_hwrm_if_change(bp, false);
1521 bnxt_free_prev_ring_stats(bp);
1522 rte_free(bp->mark_table);
1523 bp->mark_table = NULL;
1525 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1526 bp->rx_cosq_cnt = 0;
1527 /* All filters are deleted on a port stop. */
1528 if (BNXT_FLOW_XSTATS_EN(bp))
1529 bp->flow_stat->flow_count = 0;
1534 /* Unload the driver, release resources */
1535 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1537 struct bnxt *bp = eth_dev->data->dev_private;
1539 pthread_mutex_lock(&bp->err_recovery_lock);
1540 if (bp->flags & BNXT_FLAG_FW_RESET) {
1542 "Adapter recovering from error..Please retry\n");
1543 pthread_mutex_unlock(&bp->err_recovery_lock);
1546 pthread_mutex_unlock(&bp->err_recovery_lock);
1548 return bnxt_dev_stop(eth_dev);
1551 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1553 struct bnxt *bp = eth_dev->data->dev_private;
1554 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1556 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1558 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1559 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1563 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1565 "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1566 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1569 rc = bnxt_hwrm_if_change(bp, true);
1570 if (rc == 0 || rc != -EAGAIN)
1573 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1574 } while (retry_cnt--);
1579 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1580 rc = bnxt_handle_if_change_status(bp);
1585 bnxt_enable_int(bp);
1587 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1589 rc = bnxt_start_nic(bp);
1593 rc = bnxt_alloc_prev_ring_stats(bp);
1597 eth_dev->data->dev_started = 1;
1599 bnxt_link_update_op(eth_dev, 1);
1601 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1602 vlan_mask |= ETH_VLAN_FILTER_MASK;
1603 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1604 vlan_mask |= ETH_VLAN_STRIP_MASK;
1605 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1609 /* Initialize bnxt ULP port details */
1610 rc = bnxt_ulp_port_init(bp);
1614 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1615 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1617 bnxt_schedule_fw_health_check(bp);
1619 if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1620 bnxt_schedule_ptp_alarm(bp);
1625 bnxt_dev_stop(eth_dev);
1630 bnxt_uninit_locks(struct bnxt *bp)
1632 pthread_mutex_destroy(&bp->flow_lock);
1633 pthread_mutex_destroy(&bp->def_cp_lock);
1634 pthread_mutex_destroy(&bp->health_check_lock);
1635 pthread_mutex_destroy(&bp->err_recovery_lock);
1637 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
1638 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
1642 static void bnxt_drv_uninit(struct bnxt *bp)
1644 bnxt_free_leds_info(bp);
1645 bnxt_free_cos_queues(bp);
1646 bnxt_free_link_info(bp);
1647 bnxt_free_parent_info(bp);
1648 bnxt_uninit_locks(bp);
1650 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1651 bp->tx_mem_zone = NULL;
1652 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1653 bp->rx_mem_zone = NULL;
1655 bnxt_free_vf_info(bp);
1656 bnxt_free_pf_info(bp);
1658 rte_free(bp->grp_info);
1659 bp->grp_info = NULL;
1662 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1664 struct bnxt *bp = eth_dev->data->dev_private;
1667 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1670 pthread_mutex_lock(&bp->err_recovery_lock);
1671 if (bp->flags & BNXT_FLAG_FW_RESET) {
1673 "Adapter recovering from error...Please retry\n");
1674 pthread_mutex_unlock(&bp->err_recovery_lock);
1677 pthread_mutex_unlock(&bp->err_recovery_lock);
1679 /* cancel the recovery handler before remove dev */
1680 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1681 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1682 bnxt_cancel_fc_thread(bp);
1684 if (eth_dev->data->dev_started)
1685 ret = bnxt_dev_stop(eth_dev);
1687 bnxt_uninit_resources(bp, false);
1689 bnxt_drv_uninit(bp);
1694 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1697 struct bnxt *bp = eth_dev->data->dev_private;
1698 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1699 struct bnxt_vnic_info *vnic;
1700 struct bnxt_filter_info *filter, *temp_filter;
1703 if (is_bnxt_in_error(bp))
1707 * Loop through all VNICs from the specified filter flow pools to
1708 * remove the corresponding MAC addr filter
1710 for (i = 0; i < bp->nr_vnics; i++) {
1711 if (!(pool_mask & (1ULL << i)))
1714 vnic = &bp->vnic_info[i];
1715 filter = STAILQ_FIRST(&vnic->filter);
1717 temp_filter = STAILQ_NEXT(filter, next);
1718 if (filter->mac_index == index) {
1719 STAILQ_REMOVE(&vnic->filter, filter,
1720 bnxt_filter_info, next);
1721 bnxt_hwrm_clear_l2_filter(bp, filter);
1722 bnxt_free_filter(bp, filter);
1724 filter = temp_filter;
1729 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1730 struct rte_ether_addr *mac_addr, uint32_t index,
1733 struct bnxt_filter_info *filter;
1736 /* Attach requested MAC address to the new l2_filter */
1737 STAILQ_FOREACH(filter, &vnic->filter, next) {
1738 if (filter->mac_index == index) {
1740 "MAC addr already existed for pool %d\n",
1746 filter = bnxt_alloc_filter(bp);
1748 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1752 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1753 * if the MAC that's been programmed now is a different one, then,
1754 * copy that addr to filter->l2_addr
1757 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1758 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1760 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1762 filter->mac_index = index;
1763 if (filter->mac_index == 0)
1764 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1766 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1768 bnxt_free_filter(bp, filter);
1774 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1775 struct rte_ether_addr *mac_addr,
1776 uint32_t index, uint32_t pool)
1778 struct bnxt *bp = eth_dev->data->dev_private;
1779 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1782 rc = is_bnxt_in_error(bp);
1786 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1787 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1792 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1796 /* Filter settings will get applied when port is started */
1797 if (!eth_dev->data->dev_started)
1800 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1805 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1808 struct bnxt *bp = eth_dev->data->dev_private;
1809 struct rte_eth_link new;
1810 int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1811 BNXT_MIN_LINK_WAIT_CNT;
1813 rc = is_bnxt_in_error(bp);
1817 memset(&new, 0, sizeof(new));
1819 if (bp->link_info == NULL)
1823 /* Retrieve link info from hardware */
1824 rc = bnxt_get_hwrm_link_config(bp, &new);
1826 new.link_speed = ETH_LINK_SPEED_100M;
1827 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1829 "Failed to retrieve link rc = 0x%x!\n", rc);
1833 if (!wait_to_complete || new.link_status)
1836 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1839 /* Only single function PF can bring phy down.
1840 * When port is stopped, report link down for VF/MH/NPAR functions.
1842 if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1843 memset(&new, 0, sizeof(new));
1846 /* Timed out or success */
1847 if (new.link_status != eth_dev->data->dev_link.link_status ||
1848 new.link_speed != eth_dev->data->dev_link.link_speed) {
1849 rte_eth_linkstatus_set(eth_dev, &new);
1850 bnxt_print_link_info(eth_dev);
1856 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1858 struct bnxt *bp = eth_dev->data->dev_private;
1859 struct bnxt_vnic_info *vnic;
1863 rc = is_bnxt_in_error(bp);
1867 /* Filter settings will get applied when port is started */
1868 if (!eth_dev->data->dev_started)
1871 if (bp->vnic_info == NULL)
1874 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1876 old_flags = vnic->flags;
1877 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1878 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1880 vnic->flags = old_flags;
1885 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1887 struct bnxt *bp = eth_dev->data->dev_private;
1888 struct bnxt_vnic_info *vnic;
1892 rc = is_bnxt_in_error(bp);
1896 /* Filter settings will get applied when port is started */
1897 if (!eth_dev->data->dev_started)
1900 if (bp->vnic_info == NULL)
1903 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1905 old_flags = vnic->flags;
1906 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1907 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1909 vnic->flags = old_flags;
1914 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1916 struct bnxt *bp = eth_dev->data->dev_private;
1917 struct bnxt_vnic_info *vnic;
1921 rc = is_bnxt_in_error(bp);
1925 /* Filter settings will get applied when port is started */
1926 if (!eth_dev->data->dev_started)
1929 if (bp->vnic_info == NULL)
1932 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1934 old_flags = vnic->flags;
1935 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1936 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1938 vnic->flags = old_flags;
1943 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1945 struct bnxt *bp = eth_dev->data->dev_private;
1946 struct bnxt_vnic_info *vnic;
1950 rc = is_bnxt_in_error(bp);
1954 /* Filter settings will get applied when port is started */
1955 if (!eth_dev->data->dev_started)
1958 if (bp->vnic_info == NULL)
1961 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1963 old_flags = vnic->flags;
1964 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1965 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1967 vnic->flags = old_flags;
1972 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1973 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1975 if (qid >= bp->rx_nr_rings)
1978 return bp->eth_dev->data->rx_queues[qid];
1981 /* Return rxq corresponding to a given rss table ring/group ID. */
1982 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1984 struct bnxt_rx_queue *rxq;
1987 if (!BNXT_HAS_RING_GRPS(bp)) {
1988 for (i = 0; i < bp->rx_nr_rings; i++) {
1989 rxq = bp->eth_dev->data->rx_queues[i];
1990 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1994 for (i = 0; i < bp->rx_nr_rings; i++) {
1995 if (bp->grp_info[i].fw_grp_id == fwr)
2000 return INVALID_HW_RING_ID;
2003 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
2004 struct rte_eth_rss_reta_entry64 *reta_conf,
2007 struct bnxt *bp = eth_dev->data->dev_private;
2008 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2009 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2010 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
2014 rc = is_bnxt_in_error(bp);
2018 if (!vnic->rss_table)
2021 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
2024 if (reta_size != tbl_size) {
2025 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2026 "(%d) must equal the size supported by the hardware "
2027 "(%d)\n", reta_size, tbl_size);
2031 for (i = 0; i < reta_size; i++) {
2032 struct bnxt_rx_queue *rxq;
2034 idx = i / RTE_RETA_GROUP_SIZE;
2035 sft = i % RTE_RETA_GROUP_SIZE;
2037 if (!(reta_conf[idx].mask & (1ULL << sft)))
2040 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
2042 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
2046 if (BNXT_CHIP_P5(bp)) {
2047 vnic->rss_table[i * 2] =
2048 rxq->rx_ring->rx_ring_struct->fw_ring_id;
2049 vnic->rss_table[i * 2 + 1] =
2050 rxq->cp_ring->cp_ring_struct->fw_ring_id;
2052 vnic->rss_table[i] =
2053 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
2057 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2061 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
2062 struct rte_eth_rss_reta_entry64 *reta_conf,
2065 struct bnxt *bp = eth_dev->data->dev_private;
2066 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2067 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
2068 uint16_t idx, sft, i;
2071 rc = is_bnxt_in_error(bp);
2077 if (!vnic->rss_table)
2080 if (reta_size != tbl_size) {
2081 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2082 "(%d) must equal the size supported by the hardware "
2083 "(%d)\n", reta_size, tbl_size);
2087 for (idx = 0, i = 0; i < reta_size; i++) {
2088 idx = i / RTE_RETA_GROUP_SIZE;
2089 sft = i % RTE_RETA_GROUP_SIZE;
2091 if (reta_conf[idx].mask & (1ULL << sft)) {
2094 if (BNXT_CHIP_P5(bp))
2095 qid = bnxt_rss_to_qid(bp,
2096 vnic->rss_table[i * 2]);
2098 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
2100 if (qid == INVALID_HW_RING_ID) {
2101 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
2104 reta_conf[idx].reta[sft] = qid;
2111 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
2112 struct rte_eth_rss_conf *rss_conf)
2114 struct bnxt *bp = eth_dev->data->dev_private;
2115 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2116 struct bnxt_vnic_info *vnic;
2119 rc = is_bnxt_in_error(bp);
2124 * If RSS enablement were different than dev_configure,
2125 * then return -EINVAL
2127 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
2128 if (!rss_conf->rss_hf)
2129 PMD_DRV_LOG(ERR, "Hash type NONE\n");
2131 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
2135 bp->flags |= BNXT_FLAG_UPDATE_HASH;
2136 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf,
2140 /* Update the default RSS VNIC(s) */
2141 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2142 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
2144 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
2145 ETH_RSS_LEVEL(rss_conf->rss_hf));
2148 * If hashkey is not specified, use the previously configured
2151 if (!rss_conf->rss_key)
2154 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
2156 "Invalid hashkey length, should be %d bytes\n",
2160 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
2163 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2167 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
2168 struct rte_eth_rss_conf *rss_conf)
2170 struct bnxt *bp = eth_dev->data->dev_private;
2171 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2173 uint32_t hash_types;
2175 rc = is_bnxt_in_error(bp);
2179 /* RSS configuration is the same for all VNICs */
2180 if (vnic && vnic->rss_hash_key) {
2181 if (rss_conf->rss_key) {
2182 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
2183 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
2184 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
2187 hash_types = vnic->hash_type;
2188 rss_conf->rss_hf = 0;
2189 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
2190 rss_conf->rss_hf |= ETH_RSS_IPV4;
2191 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
2193 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
2194 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2196 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
2198 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
2199 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2201 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
2203 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
2204 rss_conf->rss_hf |= ETH_RSS_IPV6;
2205 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
2207 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
2208 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2210 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
2212 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
2213 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2215 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2219 bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2223 "Unknown RSS config from firmware (%08x), RSS disabled",
2228 rss_conf->rss_hf = 0;
2233 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2234 struct rte_eth_fc_conf *fc_conf)
2236 struct bnxt *bp = dev->data->dev_private;
2237 struct rte_eth_link link_info;
2240 rc = is_bnxt_in_error(bp);
2244 rc = bnxt_get_hwrm_link_config(bp, &link_info);
2248 memset(fc_conf, 0, sizeof(*fc_conf));
2249 if (bp->link_info->auto_pause)
2250 fc_conf->autoneg = 1;
2251 switch (bp->link_info->pause) {
2253 fc_conf->mode = RTE_FC_NONE;
2255 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2256 fc_conf->mode = RTE_FC_TX_PAUSE;
2258 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2259 fc_conf->mode = RTE_FC_RX_PAUSE;
2261 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2262 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2263 fc_conf->mode = RTE_FC_FULL;
2269 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2270 struct rte_eth_fc_conf *fc_conf)
2272 struct bnxt *bp = dev->data->dev_private;
2275 rc = is_bnxt_in_error(bp);
2279 if (!BNXT_SINGLE_PF(bp)) {
2281 "Flow Control Settings cannot be modified on VF or on shared PF\n");
2285 switch (fc_conf->mode) {
2287 bp->link_info->auto_pause = 0;
2288 bp->link_info->force_pause = 0;
2290 case RTE_FC_RX_PAUSE:
2291 if (fc_conf->autoneg) {
2292 bp->link_info->auto_pause =
2293 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2294 bp->link_info->force_pause = 0;
2296 bp->link_info->auto_pause = 0;
2297 bp->link_info->force_pause =
2298 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2301 case RTE_FC_TX_PAUSE:
2302 if (fc_conf->autoneg) {
2303 bp->link_info->auto_pause =
2304 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2305 bp->link_info->force_pause = 0;
2307 bp->link_info->auto_pause = 0;
2308 bp->link_info->force_pause =
2309 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2313 if (fc_conf->autoneg) {
2314 bp->link_info->auto_pause =
2315 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2316 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2317 bp->link_info->force_pause = 0;
2319 bp->link_info->auto_pause = 0;
2320 bp->link_info->force_pause =
2321 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2322 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2326 return bnxt_set_hwrm_link_config(bp, true);
2329 /* Add UDP tunneling port */
2331 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2332 struct rte_eth_udp_tunnel *udp_tunnel)
2334 struct bnxt *bp = eth_dev->data->dev_private;
2335 uint16_t tunnel_type = 0;
2338 rc = is_bnxt_in_error(bp);
2342 switch (udp_tunnel->prot_type) {
2343 case RTE_TUNNEL_TYPE_VXLAN:
2344 if (bp->vxlan_port_cnt) {
2345 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2346 udp_tunnel->udp_port);
2347 if (bp->vxlan_port != udp_tunnel->udp_port) {
2348 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2351 bp->vxlan_port_cnt++;
2355 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2356 bp->vxlan_port_cnt++;
2358 case RTE_TUNNEL_TYPE_GENEVE:
2359 if (bp->geneve_port_cnt) {
2360 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2361 udp_tunnel->udp_port);
2362 if (bp->geneve_port != udp_tunnel->udp_port) {
2363 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2366 bp->geneve_port_cnt++;
2370 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2371 bp->geneve_port_cnt++;
2374 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2377 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2383 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2384 struct rte_eth_udp_tunnel *udp_tunnel)
2386 struct bnxt *bp = eth_dev->data->dev_private;
2387 uint16_t tunnel_type = 0;
2391 rc = is_bnxt_in_error(bp);
2395 switch (udp_tunnel->prot_type) {
2396 case RTE_TUNNEL_TYPE_VXLAN:
2397 if (!bp->vxlan_port_cnt) {
2398 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2401 if (bp->vxlan_port != udp_tunnel->udp_port) {
2402 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2403 udp_tunnel->udp_port, bp->vxlan_port);
2406 if (--bp->vxlan_port_cnt)
2410 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2411 port = bp->vxlan_fw_dst_port_id;
2413 case RTE_TUNNEL_TYPE_GENEVE:
2414 if (!bp->geneve_port_cnt) {
2415 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2418 if (bp->geneve_port != udp_tunnel->udp_port) {
2419 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2420 udp_tunnel->udp_port, bp->geneve_port);
2423 if (--bp->geneve_port_cnt)
2427 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2428 port = bp->geneve_fw_dst_port_id;
2431 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2435 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2439 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2441 struct bnxt_filter_info *filter;
2442 struct bnxt_vnic_info *vnic;
2444 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2446 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2447 filter = STAILQ_FIRST(&vnic->filter);
2449 /* Search for this matching MAC+VLAN filter */
2450 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2451 /* Delete the filter */
2452 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2455 STAILQ_REMOVE(&vnic->filter, filter,
2456 bnxt_filter_info, next);
2457 bnxt_free_filter(bp, filter);
2459 "Deleted vlan filter for %d\n",
2463 filter = STAILQ_NEXT(filter, next);
2468 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2470 struct bnxt_filter_info *filter;
2471 struct bnxt_vnic_info *vnic;
2473 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2474 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2475 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2477 /* Implementation notes on the use of VNIC in this command:
2479 * By default, these filters belong to default vnic for the function.
2480 * Once these filters are set up, only destination VNIC can be modified.
2481 * If the destination VNIC is not specified in this command,
2482 * then the HWRM shall only create an l2 context id.
2485 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2486 filter = STAILQ_FIRST(&vnic->filter);
2487 /* Check if the VLAN has already been added */
2489 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2492 filter = STAILQ_NEXT(filter, next);
2495 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2496 * command to create MAC+VLAN filter with the right flags, enables set.
2498 filter = bnxt_alloc_filter(bp);
2501 "MAC/VLAN filter alloc failed\n");
2504 /* MAC + VLAN ID filter */
2505 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2506 * untagged packets are received
2508 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2509 * packets and only the programmed vlan's packets are received
2511 filter->l2_ivlan = vlan_id;
2512 filter->l2_ivlan_mask = 0x0FFF;
2513 filter->enables |= en;
2514 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2516 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2518 /* Free the newly allocated filter as we were
2519 * not able to create the filter in hardware.
2521 bnxt_free_filter(bp, filter);
2525 filter->mac_index = 0;
2526 /* Add this new filter to the list */
2528 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2530 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2533 "Added Vlan filter for %d\n", vlan_id);
2537 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2538 uint16_t vlan_id, int on)
2540 struct bnxt *bp = eth_dev->data->dev_private;
2543 rc = is_bnxt_in_error(bp);
2547 if (!eth_dev->data->dev_started) {
2548 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2552 /* These operations apply to ALL existing MAC/VLAN filters */
2554 return bnxt_add_vlan_filter(bp, vlan_id);
2556 return bnxt_del_vlan_filter(bp, vlan_id);
2559 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2560 struct bnxt_vnic_info *vnic)
2562 struct bnxt_filter_info *filter;
2565 filter = STAILQ_FIRST(&vnic->filter);
2567 if (filter->mac_index == 0 &&
2568 !memcmp(filter->l2_addr, bp->mac_addr,
2569 RTE_ETHER_ADDR_LEN)) {
2570 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2572 STAILQ_REMOVE(&vnic->filter, filter,
2573 bnxt_filter_info, next);
2574 bnxt_free_filter(bp, filter);
2578 filter = STAILQ_NEXT(filter, next);
2584 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2586 struct bnxt_vnic_info *vnic;
2590 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2591 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2592 /* Remove any VLAN filters programmed */
2593 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2594 bnxt_del_vlan_filter(bp, i);
2596 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2600 /* Default filter will allow packets that match the
2601 * dest mac. So, it has to be deleted, otherwise, we
2602 * will endup receiving vlan packets for which the
2603 * filter is not programmed, when hw-vlan-filter
2604 * configuration is ON
2606 bnxt_del_dflt_mac_filter(bp, vnic);
2607 /* This filter will allow only untagged packets */
2608 bnxt_add_vlan_filter(bp, 0);
2610 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2611 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2616 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2618 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2622 /* Destroy vnic filters and vnic */
2623 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2624 DEV_RX_OFFLOAD_VLAN_FILTER) {
2625 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2626 bnxt_del_vlan_filter(bp, i);
2628 bnxt_del_dflt_mac_filter(bp, vnic);
2630 rc = bnxt_hwrm_vnic_ctx_free(bp, vnic);
2634 rc = bnxt_hwrm_vnic_free(bp, vnic);
2638 rte_free(vnic->fw_grp_ids);
2639 vnic->fw_grp_ids = NULL;
2641 vnic->rx_queue_cnt = 0;
2647 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2649 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2652 /* Destroy, recreate and reconfigure the default vnic */
2653 rc = bnxt_free_one_vnic(bp, 0);
2657 /* default vnic 0 */
2658 rc = bnxt_setup_one_vnic(bp, 0);
2662 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2663 DEV_RX_OFFLOAD_VLAN_FILTER) {
2664 rc = bnxt_add_vlan_filter(bp, 0);
2667 rc = bnxt_restore_vlan_filters(bp);
2671 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2676 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2680 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2681 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2687 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2689 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2690 struct bnxt *bp = dev->data->dev_private;
2693 rc = is_bnxt_in_error(bp);
2697 /* Filter settings will get applied when port is started */
2698 if (!dev->data->dev_started)
2701 if (mask & ETH_VLAN_FILTER_MASK) {
2702 /* Enable or disable VLAN filtering */
2703 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2708 if (mask & ETH_VLAN_STRIP_MASK) {
2709 /* Enable or disable VLAN stripping */
2710 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2715 if (mask & ETH_VLAN_EXTEND_MASK) {
2716 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2717 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2719 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2726 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2729 struct bnxt *bp = dev->data->dev_private;
2730 int qinq = dev->data->dev_conf.rxmode.offloads &
2731 DEV_RX_OFFLOAD_VLAN_EXTEND;
2733 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2734 vlan_type != ETH_VLAN_TYPE_OUTER) {
2736 "Unsupported vlan type.");
2741 "QinQ not enabled. Needs to be ON as we can "
2742 "accelerate only outer vlan\n");
2746 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2748 case RTE_ETHER_TYPE_QINQ:
2750 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2752 case RTE_ETHER_TYPE_VLAN:
2754 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2756 case RTE_ETHER_TYPE_QINQ1:
2758 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2760 case RTE_ETHER_TYPE_QINQ2:
2762 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2764 case RTE_ETHER_TYPE_QINQ3:
2766 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2769 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2772 bp->outer_tpid_bd |= tpid;
2773 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2774 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2776 "Can accelerate only outer vlan in QinQ\n");
2784 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2785 struct rte_ether_addr *addr)
2787 struct bnxt *bp = dev->data->dev_private;
2788 /* Default Filter is tied to VNIC 0 */
2789 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2792 rc = is_bnxt_in_error(bp);
2796 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2799 if (rte_is_zero_ether_addr(addr))
2802 /* Filter settings will get applied when port is started */
2803 if (!dev->data->dev_started)
2806 /* Check if the requested MAC is already added */
2807 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2810 /* Destroy filter and re-create it */
2811 bnxt_del_dflt_mac_filter(bp, vnic);
2813 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2814 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2815 /* This filter will allow only untagged packets */
2816 rc = bnxt_add_vlan_filter(bp, 0);
2818 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2821 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2826 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2827 struct rte_ether_addr *mc_addr_set,
2828 uint32_t nb_mc_addr)
2830 struct bnxt *bp = eth_dev->data->dev_private;
2831 char *mc_addr_list = (char *)mc_addr_set;
2832 struct bnxt_vnic_info *vnic;
2833 uint32_t off = 0, i = 0;
2836 rc = is_bnxt_in_error(bp);
2840 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2842 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2843 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2847 /* TODO Check for Duplicate mcast addresses */
2848 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2849 for (i = 0; i < nb_mc_addr; i++) {
2850 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2851 RTE_ETHER_ADDR_LEN);
2852 off += RTE_ETHER_ADDR_LEN;
2855 vnic->mc_addr_cnt = i;
2856 if (vnic->mc_addr_cnt)
2857 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2859 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2862 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2866 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2868 struct bnxt *bp = dev->data->dev_private;
2869 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2870 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2871 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2872 uint8_t fw_rsvd = bp->fw_ver & 0xff;
2875 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2876 fw_major, fw_minor, fw_updt, fw_rsvd);
2880 ret += 1; /* add the size of '\0' */
2881 if (fw_size < (size_t)ret)
2888 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2889 struct rte_eth_rxq_info *qinfo)
2891 struct bnxt *bp = dev->data->dev_private;
2892 struct bnxt_rx_queue *rxq;
2894 if (is_bnxt_in_error(bp))
2897 rxq = dev->data->rx_queues[queue_id];
2899 qinfo->mp = rxq->mb_pool;
2900 qinfo->scattered_rx = dev->data->scattered_rx;
2901 qinfo->nb_desc = rxq->nb_rx_desc;
2903 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2904 qinfo->conf.rx_drop_en = rxq->drop_en;
2905 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2906 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2910 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2911 struct rte_eth_txq_info *qinfo)
2913 struct bnxt *bp = dev->data->dev_private;
2914 struct bnxt_tx_queue *txq;
2916 if (is_bnxt_in_error(bp))
2919 txq = dev->data->tx_queues[queue_id];
2921 qinfo->nb_desc = txq->nb_tx_desc;
2923 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2924 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2925 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2927 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2928 qinfo->conf.tx_rs_thresh = 0;
2929 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2930 qinfo->conf.offloads = txq->offloads;
2933 static const struct {
2934 eth_rx_burst_t pkt_burst;
2936 } bnxt_rx_burst_info[] = {
2937 {bnxt_recv_pkts, "Scalar"},
2938 #if defined(RTE_ARCH_X86)
2939 {bnxt_recv_pkts_vec, "Vector SSE"},
2941 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2942 {bnxt_recv_pkts_vec_avx2, "Vector AVX2"},
2944 #if defined(RTE_ARCH_ARM64)
2945 {bnxt_recv_pkts_vec, "Vector Neon"},
2950 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2951 struct rte_eth_burst_mode *mode)
2953 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2956 for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2957 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2958 snprintf(mode->info, sizeof(mode->info), "%s",
2959 bnxt_rx_burst_info[i].info);
2967 static const struct {
2968 eth_tx_burst_t pkt_burst;
2970 } bnxt_tx_burst_info[] = {
2971 {bnxt_xmit_pkts, "Scalar"},
2972 #if defined(RTE_ARCH_X86)
2973 {bnxt_xmit_pkts_vec, "Vector SSE"},
2975 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2976 {bnxt_xmit_pkts_vec_avx2, "Vector AVX2"},
2978 #if defined(RTE_ARCH_ARM64)
2979 {bnxt_xmit_pkts_vec, "Vector Neon"},
2984 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2985 struct rte_eth_burst_mode *mode)
2987 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2990 for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2991 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2992 snprintf(mode->info, sizeof(mode->info), "%s",
2993 bnxt_tx_burst_info[i].info);
3001 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
3003 struct bnxt *bp = eth_dev->data->dev_private;
3004 uint32_t new_pkt_size;
3008 rc = is_bnxt_in_error(bp);
3012 /* Exit if receive queues are not configured yet */
3013 if (!eth_dev->data->nb_rx_queues)
3016 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
3017 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
3020 * Disallow any MTU change that would require scattered receive support
3021 * if it is not already enabled.
3023 if (eth_dev->data->dev_started &&
3024 !eth_dev->data->scattered_rx &&
3026 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
3028 "MTU change would require scattered rx support. ");
3029 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
3033 if (new_mtu > RTE_ETHER_MTU) {
3034 bp->flags |= BNXT_FLAG_JUMBO;
3035 bp->eth_dev->data->dev_conf.rxmode.offloads |=
3036 DEV_RX_OFFLOAD_JUMBO_FRAME;
3038 bp->eth_dev->data->dev_conf.rxmode.offloads &=
3039 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3040 bp->flags &= ~BNXT_FLAG_JUMBO;
3043 /* Is there a change in mtu setting? */
3044 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
3047 for (i = 0; i < bp->nr_vnics; i++) {
3048 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3051 vnic->mru = BNXT_VNIC_MRU(new_mtu);
3052 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
3056 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
3057 size -= RTE_PKTMBUF_HEADROOM;
3059 if (size < new_mtu) {
3060 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
3067 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
3069 if (bnxt_hwrm_config_host_mtu(bp))
3070 PMD_DRV_LOG(WARNING, "Failed to configure host MTU\n");
3072 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
3078 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
3080 struct bnxt *bp = dev->data->dev_private;
3081 uint16_t vlan = bp->vlan;
3084 rc = is_bnxt_in_error(bp);
3088 if (!BNXT_SINGLE_PF(bp)) {
3089 PMD_DRV_LOG(ERR, "PVID cannot be modified on VF or on shared PF\n");
3092 bp->vlan = on ? pvid : 0;
3094 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
3101 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
3103 struct bnxt *bp = dev->data->dev_private;
3106 rc = is_bnxt_in_error(bp);
3110 return bnxt_hwrm_port_led_cfg(bp, true);
3114 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
3116 struct bnxt *bp = dev->data->dev_private;
3119 rc = is_bnxt_in_error(bp);
3123 return bnxt_hwrm_port_led_cfg(bp, false);
3127 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3129 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
3130 struct bnxt_cp_ring_info *cpr;
3131 uint32_t desc = 0, raw_cons, cp_ring_size;
3132 struct bnxt_rx_queue *rxq;
3133 struct rx_pkt_cmpl *rxcmp;
3136 rc = is_bnxt_in_error(bp);
3140 rxq = dev->data->rx_queues[rx_queue_id];
3142 raw_cons = cpr->cp_raw_cons;
3143 cp_ring_size = cpr->cp_ring_struct->ring_size;
3146 uint32_t agg_cnt, cons, cmpl_type;
3148 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3149 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3151 if (!bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size))
3154 cmpl_type = CMP_TYPE(rxcmp);
3156 switch (cmpl_type) {
3157 case CMPL_BASE_TYPE_RX_L2:
3158 case CMPL_BASE_TYPE_RX_L2_V2:
3159 agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3160 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3164 case CMPL_BASE_TYPE_RX_TPA_END:
3165 if (BNXT_CHIP_P5(rxq->bp)) {
3166 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3168 p5_tpa_end = (void *)rxcmp;
3169 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3171 struct rx_tpa_end_cmpl *tpa_end;
3173 tpa_end = (void *)rxcmp;
3174 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3177 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3182 raw_cons += CMP_LEN(cmpl_type);
3190 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
3192 struct bnxt_rx_queue *rxq = rx_queue;
3193 struct bnxt_cp_ring_info *cpr;
3194 struct bnxt_rx_ring_info *rxr;
3195 uint32_t desc, raw_cons, cp_ring_size;
3196 struct bnxt *bp = rxq->bp;
3197 struct rx_pkt_cmpl *rxcmp;
3200 rc = is_bnxt_in_error(bp);
3204 if (offset >= rxq->nb_rx_desc)
3209 cp_ring_size = cpr->cp_ring_struct->ring_size;
3212 * For the vector receive case, the completion at the requested
3213 * offset can be indexed directly.
3215 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
3216 if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) {
3217 struct rx_pkt_cmpl *rxcmp;
3220 /* Check status of completion descriptor. */
3221 raw_cons = cpr->cp_raw_cons +
3222 offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2);
3223 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3224 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3226 if (bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size))
3227 return RTE_ETH_RX_DESC_DONE;
3229 /* Check whether rx desc has an mbuf attached. */
3230 cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2);
3231 if (cons >= rxq->rxrearm_start &&
3232 cons < rxq->rxrearm_start + rxq->rxrearm_nb) {
3233 return RTE_ETH_RX_DESC_UNAVAIL;
3236 return RTE_ETH_RX_DESC_AVAIL;
3241 * For the non-vector receive case, scan the completion ring to
3242 * locate the completion descriptor for the requested offset.
3244 raw_cons = cpr->cp_raw_cons;
3247 uint32_t agg_cnt, cons, cmpl_type;
3249 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3250 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3252 if (!bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size))
3255 cmpl_type = CMP_TYPE(rxcmp);
3257 switch (cmpl_type) {
3258 case CMPL_BASE_TYPE_RX_L2:
3259 case CMPL_BASE_TYPE_RX_L2_V2:
3260 if (desc == offset) {
3261 cons = rxcmp->opaque;
3262 if (rxr->rx_buf_ring[cons])
3263 return RTE_ETH_RX_DESC_DONE;
3265 return RTE_ETH_RX_DESC_UNAVAIL;
3267 agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3268 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3272 case CMPL_BASE_TYPE_RX_TPA_END:
3274 return RTE_ETH_RX_DESC_DONE;
3276 if (BNXT_CHIP_P5(rxq->bp)) {
3277 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3279 p5_tpa_end = (void *)rxcmp;
3280 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3282 struct rx_tpa_end_cmpl *tpa_end;
3284 tpa_end = (void *)rxcmp;
3285 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3288 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3293 raw_cons += CMP_LEN(cmpl_type);
3297 return RTE_ETH_RX_DESC_AVAIL;
3301 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
3303 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
3304 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
3305 uint32_t ring_mask, raw_cons, nb_tx_pkts = 0;
3306 struct cmpl_base *cp_desc_ring;
3309 rc = is_bnxt_in_error(txq->bp);
3313 if (offset >= txq->nb_tx_desc)
3316 /* Return "desc done" if descriptor is available for use. */
3317 if (bnxt_tx_bds_in_hw(txq) <= offset)
3318 return RTE_ETH_TX_DESC_DONE;
3320 raw_cons = cpr->cp_raw_cons;
3321 cp_desc_ring = cpr->cp_desc_ring;
3322 ring_mask = cpr->cp_ring_struct->ring_mask;
3324 /* Check to see if hw has posted a completion for the descriptor. */
3326 struct tx_cmpl *txcmp;
3329 cons = RING_CMPL(ring_mask, raw_cons);
3330 txcmp = (struct tx_cmpl *)&cp_desc_ring[cons];
3332 if (!bnxt_cpr_cmp_valid(txcmp, raw_cons, ring_mask + 1))
3335 if (CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2)
3336 nb_tx_pkts += rte_le_to_cpu_32(txcmp->opaque);
3338 if (nb_tx_pkts > offset)
3339 return RTE_ETH_TX_DESC_DONE;
3341 raw_cons = NEXT_RAW_CMP(raw_cons);
3344 /* Descriptor is pending transmit, not yet completed by hardware. */
3345 return RTE_ETH_TX_DESC_FULL;
3349 bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
3350 const struct rte_flow_ops **ops)
3352 struct bnxt *bp = dev->data->dev_private;
3358 if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3359 struct bnxt_representor *vfr = dev->data->dev_private;
3360 bp = vfr->parent_dev->data->dev_private;
3361 /* parent is deleted while children are still valid */
3363 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error\n",
3364 dev->data->port_id);
3369 ret = is_bnxt_in_error(bp);
3373 /* PMD supports thread-safe flow operations. rte_flow API
3374 * functions can avoid mutex for multi-thread safety.
3376 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3378 if (BNXT_TRUFLOW_EN(bp))
3379 *ops = &bnxt_ulp_rte_flow_ops;
3381 *ops = &bnxt_flow_ops;
3386 static const uint32_t *
3387 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3389 static const uint32_t ptypes[] = {
3390 RTE_PTYPE_L2_ETHER_VLAN,
3391 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3392 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3396 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3397 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3398 RTE_PTYPE_INNER_L4_ICMP,
3399 RTE_PTYPE_INNER_L4_TCP,
3400 RTE_PTYPE_INNER_L4_UDP,
3404 if (!dev->rx_pkt_burst)
3410 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3413 uint32_t reg_base = *reg_arr & 0xfffff000;
3417 for (i = 0; i < count; i++) {
3418 if ((reg_arr[i] & 0xfffff000) != reg_base)
3421 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3422 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3426 static int bnxt_map_ptp_regs(struct bnxt *bp)
3428 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3432 reg_arr = ptp->rx_regs;
3433 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3437 reg_arr = ptp->tx_regs;
3438 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3442 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3443 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3445 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3446 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3451 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3453 rte_write32(0, (uint8_t *)bp->bar0 +
3454 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3455 rte_write32(0, (uint8_t *)bp->bar0 +
3456 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3459 static uint64_t bnxt_cc_read(struct bnxt *bp)
3463 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3464 BNXT_GRCPF_REG_SYNC_TIME));
3465 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3466 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3470 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3472 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3475 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3476 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3477 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3480 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3481 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3482 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3483 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3484 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3485 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3486 rte_read32((uint8_t *)bp->bar0 + ptp->tx_mapped_regs[BNXT_PTP_TX_SEQ]);
3491 static int bnxt_clr_rx_ts(struct bnxt *bp, uint64_t *last_ts)
3493 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3494 struct bnxt_pf_info *pf = bp->pf;
3499 if (!ptp || (bp->flags & BNXT_FLAG_CHIP_P5))
3502 port_id = pf->port_id;
3503 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3504 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3505 while ((fifo & BNXT_PTP_RX_FIFO_PENDING) && (i < BNXT_PTP_RX_PND_CNT)) {
3506 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3507 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3508 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3509 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3510 *last_ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3511 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3512 *last_ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3513 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3517 if (i >= BNXT_PTP_RX_PND_CNT)
3523 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3525 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3526 struct bnxt_pf_info *pf = bp->pf;
3530 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3531 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3532 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3535 port_id = pf->port_id;
3536 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3537 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3539 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3540 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3541 if (fifo & BNXT_PTP_RX_FIFO_PENDING)
3542 return bnxt_clr_rx_ts(bp, ts);
3544 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3545 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3546 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3547 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3553 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3556 struct bnxt *bp = dev->data->dev_private;
3557 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3562 ns = rte_timespec_to_ns(ts);
3563 /* Set the timecounters to a new value. */
3565 ptp->tx_tstamp_tc.nsec = ns;
3566 ptp->rx_tstamp_tc.nsec = ns;
3572 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3574 struct bnxt *bp = dev->data->dev_private;
3575 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3576 uint64_t ns, systime_cycles = 0;
3582 if (BNXT_CHIP_P5(bp))
3583 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3586 systime_cycles = bnxt_cc_read(bp);
3588 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3589 *ts = rte_ns_to_timespec(ns);
3594 bnxt_timesync_enable(struct rte_eth_dev *dev)
3596 struct bnxt *bp = dev->data->dev_private;
3597 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3605 ptp->tx_tstamp_en = 1;
3606 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3608 rc = bnxt_hwrm_ptp_cfg(bp);
3612 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3613 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3614 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3616 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3617 ptp->tc.cc_shift = shift;
3618 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3620 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3621 ptp->rx_tstamp_tc.cc_shift = shift;
3622 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3624 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3625 ptp->tx_tstamp_tc.cc_shift = shift;
3626 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3628 if (!BNXT_CHIP_P5(bp))
3629 bnxt_map_ptp_regs(bp);
3631 rc = bnxt_ptp_start(bp);
3637 bnxt_timesync_disable(struct rte_eth_dev *dev)
3639 struct bnxt *bp = dev->data->dev_private;
3640 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3646 ptp->tx_tstamp_en = 0;
3649 bnxt_hwrm_ptp_cfg(bp);
3651 if (!BNXT_CHIP_P5(bp))
3652 bnxt_unmap_ptp_regs(bp);
3660 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3661 struct timespec *timestamp,
3662 uint32_t flags __rte_unused)
3664 struct bnxt *bp = dev->data->dev_private;
3665 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3666 uint64_t rx_tstamp_cycles = 0;
3672 if (BNXT_CHIP_P5(bp))
3673 rx_tstamp_cycles = ptp->rx_timestamp;
3675 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3677 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3678 *timestamp = rte_ns_to_timespec(ns);
3683 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3684 struct timespec *timestamp)
3686 struct bnxt *bp = dev->data->dev_private;
3687 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3688 uint64_t tx_tstamp_cycles = 0;
3695 if (BNXT_CHIP_P5(bp))
3696 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3699 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3701 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3702 *timestamp = rte_ns_to_timespec(ns);
3708 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3710 struct bnxt *bp = dev->data->dev_private;
3711 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3716 ptp->tc.nsec += delta;
3717 ptp->tx_tstamp_tc.nsec += delta;
3718 ptp->rx_tstamp_tc.nsec += delta;
3724 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3726 struct bnxt *bp = dev->data->dev_private;
3728 uint32_t dir_entries;
3729 uint32_t entry_length;
3731 rc = is_bnxt_in_error(bp);
3735 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3736 bp->pdev->addr.domain, bp->pdev->addr.bus,
3737 bp->pdev->addr.devid, bp->pdev->addr.function);
3739 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3743 return dir_entries * entry_length;
3747 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3748 struct rte_dev_eeprom_info *in_eeprom)
3750 struct bnxt *bp = dev->data->dev_private;
3755 rc = is_bnxt_in_error(bp);
3759 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3760 bp->pdev->addr.domain, bp->pdev->addr.bus,
3761 bp->pdev->addr.devid, bp->pdev->addr.function,
3762 in_eeprom->offset, in_eeprom->length);
3764 if (in_eeprom->offset == 0) /* special offset value to get directory */
3765 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3768 index = in_eeprom->offset >> 24;
3769 offset = in_eeprom->offset & 0xffffff;
3772 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3773 in_eeprom->length, in_eeprom->data);
3778 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3781 case BNX_DIR_TYPE_CHIMP_PATCH:
3782 case BNX_DIR_TYPE_BOOTCODE:
3783 case BNX_DIR_TYPE_BOOTCODE_2:
3784 case BNX_DIR_TYPE_APE_FW:
3785 case BNX_DIR_TYPE_APE_PATCH:
3786 case BNX_DIR_TYPE_KONG_FW:
3787 case BNX_DIR_TYPE_KONG_PATCH:
3788 case BNX_DIR_TYPE_BONO_FW:
3789 case BNX_DIR_TYPE_BONO_PATCH:
3797 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3800 case BNX_DIR_TYPE_AVS:
3801 case BNX_DIR_TYPE_EXP_ROM_MBA:
3802 case BNX_DIR_TYPE_PCIE:
3803 case BNX_DIR_TYPE_TSCF_UCODE:
3804 case BNX_DIR_TYPE_EXT_PHY:
3805 case BNX_DIR_TYPE_CCM:
3806 case BNX_DIR_TYPE_ISCSI_BOOT:
3807 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3808 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3816 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3818 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3819 bnxt_dir_type_is_other_exec_format(dir_type);
3823 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3824 struct rte_dev_eeprom_info *in_eeprom)
3826 struct bnxt *bp = dev->data->dev_private;
3827 uint8_t index, dir_op;
3828 uint16_t type, ext, ordinal, attr;
3831 rc = is_bnxt_in_error(bp);
3835 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3836 bp->pdev->addr.domain, bp->pdev->addr.bus,
3837 bp->pdev->addr.devid, bp->pdev->addr.function,
3838 in_eeprom->offset, in_eeprom->length);
3841 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3845 type = in_eeprom->magic >> 16;
3847 if (type == 0xffff) { /* special value for directory operations */
3848 index = in_eeprom->magic & 0xff;
3849 dir_op = in_eeprom->magic >> 8;
3853 case 0x0e: /* erase */
3854 if (in_eeprom->offset != ~in_eeprom->magic)
3856 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3862 /* Create or re-write an NVM item: */
3863 if (bnxt_dir_type_is_executable(type) == true)
3865 ext = in_eeprom->magic & 0xffff;
3866 ordinal = in_eeprom->offset >> 16;
3867 attr = in_eeprom->offset & 0xffff;
3869 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3870 in_eeprom->data, in_eeprom->length);
3873 static int bnxt_get_module_info(struct rte_eth_dev *dev,
3874 struct rte_eth_dev_module_info *modinfo)
3876 uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1];
3877 struct bnxt *bp = dev->data->dev_private;
3880 /* No point in going further if phy status indicates
3881 * module is not inserted or if it is powered down or
3882 * if it is of type 10GBase-T
3884 if (bp->link_info->module_status >
3885 HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG) {
3886 PMD_DRV_LOG(NOTICE, "Port %u : Module is not inserted or is powered down\n",
3887 dev->data->port_id);
3891 /* This feature is not supported in older firmware versions */
3892 if (bp->hwrm_spec_code < 0x10202) {
3893 PMD_DRV_LOG(NOTICE, "Port %u : Feature is not supported in older firmware\n",
3894 dev->data->port_id);
3898 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
3899 SFF_DIAG_SUPPORT_OFFSET + 1,
3905 switch (module_info[0]) {
3906 case SFF_MODULE_ID_SFP:
3907 modinfo->type = RTE_ETH_MODULE_SFF_8472;
3908 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
3909 if (module_info[SFF_DIAG_SUPPORT_OFFSET] == 0)
3910 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN;
3912 case SFF_MODULE_ID_QSFP:
3913 case SFF_MODULE_ID_QSFP_PLUS:
3914 modinfo->type = RTE_ETH_MODULE_SFF_8436;
3915 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN;
3917 case SFF_MODULE_ID_QSFP28:
3918 modinfo->type = RTE_ETH_MODULE_SFF_8636;
3919 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
3920 if (module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK)
3921 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_LEN;
3924 PMD_DRV_LOG(NOTICE, "Port %u : Unsupported module\n", dev->data->port_id);
3928 PMD_DRV_LOG(INFO, "Port %u : modinfo->type = %d modinfo->eeprom_len = %d\n",
3929 dev->data->port_id, modinfo->type, modinfo->eeprom_len);
3934 static int bnxt_get_module_eeprom(struct rte_eth_dev *dev,
3935 struct rte_dev_eeprom_info *info)
3937 uint8_t pg_addr[5] = { I2C_DEV_ADDR_A0, I2C_DEV_ADDR_A0 };
3938 uint32_t offset = info->offset, length = info->length;
3939 uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1];
3940 struct bnxt *bp = dev->data->dev_private;
3941 uint8_t *data = info->data;
3942 uint8_t page = offset >> 7;
3943 uint8_t max_pages = 2;
3947 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
3948 SFF_DIAG_SUPPORT_OFFSET + 1,
3953 switch (module_info[0]) {
3954 case SFF_MODULE_ID_SFP:
3955 module_info[SFF_DIAG_SUPPORT_OFFSET] = 0;
3956 if (module_info[SFF_DIAG_SUPPORT_OFFSET]) {
3957 pg_addr[2] = I2C_DEV_ADDR_A2;
3958 pg_addr[3] = I2C_DEV_ADDR_A2;
3962 case SFF_MODULE_ID_QSFP28:
3963 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0,
3964 SFF8636_OPT_PAGES_OFFSET,
3969 if (opt_pages & SFF8636_PAGE1_MASK) {
3970 pg_addr[2] = I2C_DEV_ADDR_A0;
3973 if (opt_pages & SFF8636_PAGE2_MASK) {
3974 pg_addr[3] = I2C_DEV_ADDR_A0;
3977 if (~module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK) {
3978 pg_addr[4] = I2C_DEV_ADDR_A0;
3986 memset(data, 0, length);
3989 while (length && page < max_pages) {
3990 uint8_t raw_page = page ? page - 1 : 0;
3993 if (pg_addr[page] == I2C_DEV_ADDR_A2)
3997 chunk = RTE_MIN(length, 256 - offset);
3999 if (pg_addr[page]) {
4000 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, pg_addr[page],
4010 page += 1 + (chunk > 128);
4013 return length ? -EINVAL : 0;
4020 static const struct eth_dev_ops bnxt_dev_ops = {
4021 .dev_infos_get = bnxt_dev_info_get_op,
4022 .dev_close = bnxt_dev_close_op,
4023 .dev_configure = bnxt_dev_configure_op,
4024 .dev_start = bnxt_dev_start_op,
4025 .dev_stop = bnxt_dev_stop_op,
4026 .dev_set_link_up = bnxt_dev_set_link_up_op,
4027 .dev_set_link_down = bnxt_dev_set_link_down_op,
4028 .stats_get = bnxt_stats_get_op,
4029 .stats_reset = bnxt_stats_reset_op,
4030 .rx_queue_setup = bnxt_rx_queue_setup_op,
4031 .rx_queue_release = bnxt_rx_queue_release_op,
4032 .tx_queue_setup = bnxt_tx_queue_setup_op,
4033 .tx_queue_release = bnxt_tx_queue_release_op,
4034 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4035 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4036 .reta_update = bnxt_reta_update_op,
4037 .reta_query = bnxt_reta_query_op,
4038 .rss_hash_update = bnxt_rss_hash_update_op,
4039 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4040 .link_update = bnxt_link_update_op,
4041 .promiscuous_enable = bnxt_promiscuous_enable_op,
4042 .promiscuous_disable = bnxt_promiscuous_disable_op,
4043 .allmulticast_enable = bnxt_allmulticast_enable_op,
4044 .allmulticast_disable = bnxt_allmulticast_disable_op,
4045 .mac_addr_add = bnxt_mac_addr_add_op,
4046 .mac_addr_remove = bnxt_mac_addr_remove_op,
4047 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4048 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4049 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
4050 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
4051 .vlan_filter_set = bnxt_vlan_filter_set_op,
4052 .vlan_offload_set = bnxt_vlan_offload_set_op,
4053 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4054 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4055 .mtu_set = bnxt_mtu_set_op,
4056 .mac_addr_set = bnxt_set_default_mac_addr_op,
4057 .xstats_get = bnxt_dev_xstats_get_op,
4058 .xstats_get_names = bnxt_dev_xstats_get_names_op,
4059 .xstats_reset = bnxt_dev_xstats_reset_op,
4060 .fw_version_get = bnxt_fw_version_get,
4061 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4062 .rxq_info_get = bnxt_rxq_info_get_op,
4063 .txq_info_get = bnxt_txq_info_get_op,
4064 .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4065 .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4066 .dev_led_on = bnxt_dev_led_on_op,
4067 .dev_led_off = bnxt_dev_led_off_op,
4068 .rx_queue_start = bnxt_rx_queue_start,
4069 .rx_queue_stop = bnxt_rx_queue_stop,
4070 .tx_queue_start = bnxt_tx_queue_start,
4071 .tx_queue_stop = bnxt_tx_queue_stop,
4072 .flow_ops_get = bnxt_flow_ops_get_op,
4073 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4074 .get_eeprom_length = bnxt_get_eeprom_length_op,
4075 .get_eeprom = bnxt_get_eeprom_op,
4076 .set_eeprom = bnxt_set_eeprom_op,
4077 .get_module_info = bnxt_get_module_info,
4078 .get_module_eeprom = bnxt_get_module_eeprom,
4079 .timesync_enable = bnxt_timesync_enable,
4080 .timesync_disable = bnxt_timesync_disable,
4081 .timesync_read_time = bnxt_timesync_read_time,
4082 .timesync_write_time = bnxt_timesync_write_time,
4083 .timesync_adjust_time = bnxt_timesync_adjust_time,
4084 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4085 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4088 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4092 /* Only pre-map the reset GRC registers using window 3 */
4093 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4094 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4096 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4101 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4103 struct bnxt_error_recovery_info *info = bp->recovery_info;
4104 uint32_t reg_base = 0xffffffff;
4107 /* Only pre-map the monitoring GRC registers using window 2 */
4108 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4109 uint32_t reg = info->status_regs[i];
4111 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4114 if (reg_base == 0xffffffff)
4115 reg_base = reg & 0xfffff000;
4116 if ((reg & 0xfffff000) != reg_base)
4119 /* Use mask 0xffc as the Lower 2 bits indicates
4120 * address space location
4122 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4126 if (reg_base == 0xffffffff)
4129 rte_write32(reg_base, (uint8_t *)bp->bar0 +
4130 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4135 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4137 struct bnxt_error_recovery_info *info = bp->recovery_info;
4138 uint32_t delay = info->delay_after_reset[index];
4139 uint32_t val = info->reset_reg_val[index];
4140 uint32_t reg = info->reset_reg[index];
4141 uint32_t type, offset;
4144 type = BNXT_FW_STATUS_REG_TYPE(reg);
4145 offset = BNXT_FW_STATUS_REG_OFF(reg);
4148 case BNXT_FW_STATUS_REG_TYPE_CFG:
4149 ret = rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4151 PMD_DRV_LOG(ERR, "Failed to write %#x at PCI offset %#x",
4156 case BNXT_FW_STATUS_REG_TYPE_GRC:
4157 offset = bnxt_map_reset_regs(bp, offset);
4158 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4160 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4161 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4164 /* wait on a specific interval of time until core reset is complete */
4166 rte_delay_ms(delay);
4169 static void bnxt_dev_cleanup(struct bnxt *bp)
4171 bp->eth_dev->data->dev_link.link_status = 0;
4172 bp->link_info->link_up = 0;
4173 if (bp->eth_dev->data->dev_started)
4174 bnxt_dev_stop(bp->eth_dev);
4176 bnxt_uninit_resources(bp, true);
4180 bnxt_check_fw_reset_done(struct bnxt *bp)
4182 int timeout = bp->fw_reset_max_msecs;
4187 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4189 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4195 } while (timeout--);
4197 if (val == 0xffff) {
4198 PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n");
4205 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4207 struct rte_eth_dev *dev = bp->eth_dev;
4208 struct rte_vlan_filter_conf *vfc;
4212 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4213 vfc = &dev->data->vlan_filter_conf;
4214 vidx = vlan_id / 64;
4215 vbit = vlan_id % 64;
4217 /* Each bit corresponds to a VLAN id */
4218 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4219 rc = bnxt_add_vlan_filter(bp, vlan_id);
4228 static int bnxt_restore_mac_filters(struct bnxt *bp)
4230 struct rte_eth_dev *dev = bp->eth_dev;
4231 struct rte_eth_dev_info dev_info;
4232 struct rte_ether_addr *addr;
4238 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4241 rc = bnxt_dev_info_get_op(dev, &dev_info);
4245 /* replay MAC address configuration */
4246 for (i = 1; i < dev_info.max_mac_addrs; i++) {
4247 addr = &dev->data->mac_addrs[i];
4249 /* skip zero address */
4250 if (rte_is_zero_ether_addr(addr))
4254 pool_mask = dev->data->mac_pool_sel[i];
4257 if (pool_mask & 1ULL) {
4258 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4264 } while (pool_mask);
4270 static int bnxt_restore_filters(struct bnxt *bp)
4272 struct rte_eth_dev *dev = bp->eth_dev;
4275 if (dev->data->all_multicast) {
4276 ret = bnxt_allmulticast_enable_op(dev);
4280 if (dev->data->promiscuous) {
4281 ret = bnxt_promiscuous_enable_op(dev);
4286 ret = bnxt_restore_mac_filters(bp);
4290 ret = bnxt_restore_vlan_filters(bp);
4291 /* TODO restore other filters as well */
4295 static int bnxt_check_fw_ready(struct bnxt *bp)
4297 int timeout = bp->fw_reset_max_msecs;
4301 rc = bnxt_hwrm_poll_ver_get(bp);
4304 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4305 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4306 } while (rc && timeout > 0);
4309 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4314 static void bnxt_dev_recover(void *arg)
4316 struct bnxt *bp = arg;
4319 pthread_mutex_lock(&bp->err_recovery_lock);
4321 if (!bp->fw_reset_min_msecs) {
4322 rc = bnxt_check_fw_reset_done(bp);
4327 /* Clear Error flag so that device re-init should happen */
4328 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4330 rc = bnxt_check_fw_ready(bp);
4334 rc = bnxt_init_resources(bp, true);
4337 "Failed to initialize resources after reset\n");
4340 /* clear reset flag as the device is initialized now */
4341 bp->flags &= ~BNXT_FLAG_FW_RESET;
4343 rc = bnxt_dev_start_op(bp->eth_dev);
4345 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4349 rc = bnxt_restore_filters(bp);
4353 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4354 pthread_mutex_unlock(&bp->err_recovery_lock);
4358 bnxt_dev_stop(bp->eth_dev);
4360 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4361 bnxt_uninit_resources(bp, false);
4362 if (bp->eth_dev->data->dev_conf.intr_conf.rmv)
4363 rte_eth_dev_callback_process(bp->eth_dev,
4364 RTE_ETH_EVENT_INTR_RMV,
4366 pthread_mutex_unlock(&bp->err_recovery_lock);
4367 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4370 void bnxt_dev_reset_and_resume(void *arg)
4372 struct bnxt *bp = arg;
4373 uint32_t us = US_PER_MS * bp->fw_reset_min_msecs;
4377 bnxt_dev_cleanup(bp);
4379 bnxt_wait_for_device_shutdown(bp);
4381 /* During some fatal firmware error conditions, the PCI config space
4382 * register 0x2e which normally contains the subsystem ID will become
4383 * 0xffff. This register will revert back to the normal value after
4384 * the chip has completed core reset. If we detect this condition,
4385 * we can poll this config register immediately for the value to revert.
4387 if (bp->flags & BNXT_FLAG_FATAL_ERROR) {
4388 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4390 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4393 if (val == 0xffff) {
4394 bp->fw_reset_min_msecs = 0;
4399 rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp);
4401 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4404 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4406 struct bnxt_error_recovery_info *info = bp->recovery_info;
4407 uint32_t reg = info->status_regs[index];
4408 uint32_t type, offset, val = 0;
4411 type = BNXT_FW_STATUS_REG_TYPE(reg);
4412 offset = BNXT_FW_STATUS_REG_OFF(reg);
4415 case BNXT_FW_STATUS_REG_TYPE_CFG:
4416 ret = rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4418 PMD_DRV_LOG(ERR, "Failed to read PCI offset %#x",
4421 case BNXT_FW_STATUS_REG_TYPE_GRC:
4422 offset = info->mapped_status_regs[index];
4424 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4425 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4433 static int bnxt_fw_reset_all(struct bnxt *bp)
4435 struct bnxt_error_recovery_info *info = bp->recovery_info;
4439 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4440 /* Reset through master function driver */
4441 for (i = 0; i < info->reg_array_cnt; i++)
4442 bnxt_write_fw_reset_reg(bp, i);
4443 /* Wait for time specified by FW after triggering reset */
4444 rte_delay_ms(info->master_func_wait_period_after_reset);
4445 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4446 /* Reset with the help of Kong processor */
4447 rc = bnxt_hwrm_fw_reset(bp);
4449 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4455 static void bnxt_fw_reset_cb(void *arg)
4457 struct bnxt *bp = arg;
4458 struct bnxt_error_recovery_info *info = bp->recovery_info;
4461 /* Only Master function can do FW reset */
4462 if (bnxt_is_master_func(bp) &&
4463 bnxt_is_recovery_enabled(bp)) {
4464 rc = bnxt_fw_reset_all(bp);
4466 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4471 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4472 * EXCEPTION_FATAL_ASYNC event to all the functions
4473 * (including MASTER FUNC). After receiving this Async, all the active
4474 * drivers should treat this case as FW initiated recovery
4476 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4477 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4478 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4480 /* To recover from error */
4481 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4486 /* Driver should poll FW heartbeat, reset_counter with the frequency
4487 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4488 * When the driver detects heartbeat stop or change in reset_counter,
4489 * it has to trigger a reset to recover from the error condition.
4490 * A “master PF” is the function who will have the privilege to
4491 * initiate the chimp reset. The master PF will be elected by the
4492 * firmware and will be notified through async message.
4494 static void bnxt_check_fw_health(void *arg)
4496 struct bnxt *bp = arg;
4497 struct bnxt_error_recovery_info *info = bp->recovery_info;
4498 uint32_t val = 0, wait_msec;
4500 if (!info || !bnxt_is_recovery_enabled(bp) ||
4501 is_bnxt_in_error(bp))
4504 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4505 if (val == info->last_heart_beat)
4508 info->last_heart_beat = val;
4510 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4511 if (val != info->last_reset_counter)
4514 info->last_reset_counter = val;
4516 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4517 bnxt_check_fw_health, (void *)bp);
4521 /* Stop DMA to/from device */
4522 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4523 bp->flags |= BNXT_FLAG_FW_RESET;
4527 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4529 if (bnxt_is_master_func(bp))
4530 wait_msec = info->master_func_wait_period;
4532 wait_msec = info->normal_func_wait_period;
4534 rte_eal_alarm_set(US_PER_MS * wait_msec,
4535 bnxt_fw_reset_cb, (void *)bp);
4538 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4540 uint32_t polling_freq;
4542 pthread_mutex_lock(&bp->health_check_lock);
4544 if (!bnxt_is_recovery_enabled(bp))
4547 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4550 polling_freq = bp->recovery_info->driver_polling_freq;
4552 rte_eal_alarm_set(US_PER_MS * polling_freq,
4553 bnxt_check_fw_health, (void *)bp);
4554 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4557 pthread_mutex_unlock(&bp->health_check_lock);
4560 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4562 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4563 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4566 static bool bnxt_vf_pciid(uint16_t device_id)
4568 switch (device_id) {
4569 case BROADCOM_DEV_ID_57304_VF:
4570 case BROADCOM_DEV_ID_57406_VF:
4571 case BROADCOM_DEV_ID_5731X_VF:
4572 case BROADCOM_DEV_ID_5741X_VF:
4573 case BROADCOM_DEV_ID_57414_VF:
4574 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4575 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4576 case BROADCOM_DEV_ID_58802_VF:
4577 case BROADCOM_DEV_ID_57500_VF1:
4578 case BROADCOM_DEV_ID_57500_VF2:
4579 case BROADCOM_DEV_ID_58818_VF:
4587 /* Phase 5 device */
4588 static bool bnxt_p5_device(uint16_t device_id)
4590 switch (device_id) {
4591 case BROADCOM_DEV_ID_57508:
4592 case BROADCOM_DEV_ID_57504:
4593 case BROADCOM_DEV_ID_57502:
4594 case BROADCOM_DEV_ID_57508_MF1:
4595 case BROADCOM_DEV_ID_57504_MF1:
4596 case BROADCOM_DEV_ID_57502_MF1:
4597 case BROADCOM_DEV_ID_57508_MF2:
4598 case BROADCOM_DEV_ID_57504_MF2:
4599 case BROADCOM_DEV_ID_57502_MF2:
4600 case BROADCOM_DEV_ID_57500_VF1:
4601 case BROADCOM_DEV_ID_57500_VF2:
4602 case BROADCOM_DEV_ID_58812:
4603 case BROADCOM_DEV_ID_58814:
4604 case BROADCOM_DEV_ID_58818:
4605 case BROADCOM_DEV_ID_58818_VF:
4613 bool bnxt_stratus_device(struct bnxt *bp)
4615 uint16_t device_id = bp->pdev->id.device_id;
4617 switch (device_id) {
4618 case BROADCOM_DEV_ID_STRATUS_NIC:
4619 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4620 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4628 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev)
4630 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4631 struct bnxt *bp = eth_dev->data->dev_private;
4633 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4634 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4635 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4636 if (!bp->bar0 || !bp->doorbell_base) {
4637 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4641 bp->eth_dev = eth_dev;
4647 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4648 struct bnxt_ctx_pg_info *ctx_pg,
4653 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4654 const struct rte_memzone *mz = NULL;
4655 char mz_name[RTE_MEMZONE_NAMESIZE];
4656 rte_iova_t mz_phys_addr;
4657 uint64_t valid_bits = 0;
4664 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4666 rmem->page_size = BNXT_PAGE_SIZE;
4667 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4668 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4669 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4671 valid_bits = PTU_PTE_VALID;
4673 if (rmem->nr_pages > 1) {
4674 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4675 "bnxt_ctx_pg_tbl%s_%x_%d",
4676 suffix, idx, bp->eth_dev->data->port_id);
4677 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4678 mz = rte_memzone_lookup(mz_name);
4680 mz = rte_memzone_reserve_aligned(mz_name,
4682 bp->eth_dev->device->numa_node,
4684 RTE_MEMZONE_SIZE_HINT_ONLY |
4685 RTE_MEMZONE_IOVA_CONTIG,
4691 memset(mz->addr, 0, mz->len);
4692 mz_phys_addr = mz->iova;
4694 rmem->pg_tbl = mz->addr;
4695 rmem->pg_tbl_map = mz_phys_addr;
4696 rmem->pg_tbl_mz = mz;
4699 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4700 suffix, idx, bp->eth_dev->data->port_id);
4701 mz = rte_memzone_lookup(mz_name);
4703 mz = rte_memzone_reserve_aligned(mz_name,
4705 bp->eth_dev->device->numa_node,
4707 RTE_MEMZONE_SIZE_HINT_ONLY |
4708 RTE_MEMZONE_IOVA_CONTIG,
4714 memset(mz->addr, 0, mz->len);
4715 mz_phys_addr = mz->iova;
4717 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4718 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4719 rmem->dma_arr[i] = mz_phys_addr + sz;
4721 if (rmem->nr_pages > 1) {
4722 if (i == rmem->nr_pages - 2 &&
4723 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4724 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4725 else if (i == rmem->nr_pages - 1 &&
4726 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4727 valid_bits |= PTU_PTE_LAST;
4729 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4735 if (rmem->vmem_size)
4736 rmem->vmem = (void **)mz->addr;
4737 rmem->dma_arr[0] = mz_phys_addr;
4741 static void bnxt_free_ctx_mem(struct bnxt *bp)
4745 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4748 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4749 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4750 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4751 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4752 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4753 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4754 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4755 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4756 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4757 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4758 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4760 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4761 if (bp->ctx->tqm_mem[i])
4762 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4769 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4771 #define min_t(type, x, y) ({ \
4772 type __min1 = (x); \
4773 type __min2 = (y); \
4774 __min1 < __min2 ? __min1 : __min2; })
4776 #define max_t(type, x, y) ({ \
4777 type __max1 = (x); \
4778 type __max2 = (y); \
4779 __max1 > __max2 ? __max1 : __max2; })
4781 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4783 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4785 struct bnxt_ctx_pg_info *ctx_pg;
4786 struct bnxt_ctx_mem_info *ctx;
4787 uint32_t mem_size, ena, entries;
4788 uint32_t entries_sp, min;
4791 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4793 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4797 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4800 ctx_pg = &ctx->qp_mem;
4801 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4802 if (ctx->qp_entry_size) {
4803 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4804 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4809 ctx_pg = &ctx->srq_mem;
4810 ctx_pg->entries = ctx->srq_max_l2_entries;
4811 if (ctx->srq_entry_size) {
4812 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4813 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4818 ctx_pg = &ctx->cq_mem;
4819 ctx_pg->entries = ctx->cq_max_l2_entries;
4820 if (ctx->cq_entry_size) {
4821 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4822 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4827 ctx_pg = &ctx->vnic_mem;
4828 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4829 ctx->vnic_max_ring_table_entries;
4830 if (ctx->vnic_entry_size) {
4831 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4832 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4837 ctx_pg = &ctx->stat_mem;
4838 ctx_pg->entries = ctx->stat_max_entries;
4839 if (ctx->stat_entry_size) {
4840 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4841 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4846 min = ctx->tqm_min_entries_per_ring;
4848 entries_sp = ctx->qp_max_l2_entries +
4849 ctx->vnic_max_vnic_entries +
4850 2 * ctx->qp_min_qp1_entries + min;
4851 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4853 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4854 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4855 entries = clamp_t(uint32_t, entries, min,
4856 ctx->tqm_max_entries_per_ring);
4857 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4858 /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7.
4859 * i > 8 is other ext rings.
4861 ctx_pg = ctx->tqm_mem[i];
4862 ctx_pg->entries = i ? entries : entries_sp;
4863 if (ctx->tqm_entry_size) {
4864 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4865 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size,
4870 if (i < BNXT_MAX_TQM_LEGACY_RINGS)
4871 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4873 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8;
4876 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4877 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4880 "Failed to configure context mem: rc = %d\n", rc);
4882 ctx->flags |= BNXT_CTX_FLAG_INITED;
4887 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4889 struct rte_pci_device *pci_dev = bp->pdev;
4890 char mz_name[RTE_MEMZONE_NAMESIZE];
4891 const struct rte_memzone *mz = NULL;
4892 uint32_t total_alloc_len;
4893 rte_iova_t mz_phys_addr;
4895 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4898 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4899 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4900 pci_dev->addr.bus, pci_dev->addr.devid,
4901 pci_dev->addr.function, "rx_port_stats");
4902 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4903 mz = rte_memzone_lookup(mz_name);
4905 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4906 sizeof(struct rx_port_stats_ext) + 512);
4908 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4911 RTE_MEMZONE_SIZE_HINT_ONLY |
4912 RTE_MEMZONE_IOVA_CONTIG);
4916 memset(mz->addr, 0, mz->len);
4917 mz_phys_addr = mz->iova;
4919 bp->rx_mem_zone = (const void *)mz;
4920 bp->hw_rx_port_stats = mz->addr;
4921 bp->hw_rx_port_stats_map = mz_phys_addr;
4923 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4924 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4925 pci_dev->addr.bus, pci_dev->addr.devid,
4926 pci_dev->addr.function, "tx_port_stats");
4927 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4928 mz = rte_memzone_lookup(mz_name);
4930 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4931 sizeof(struct tx_port_stats_ext) + 512);
4933 mz = rte_memzone_reserve(mz_name,
4937 RTE_MEMZONE_SIZE_HINT_ONLY |
4938 RTE_MEMZONE_IOVA_CONTIG);
4942 memset(mz->addr, 0, mz->len);
4943 mz_phys_addr = mz->iova;
4945 bp->tx_mem_zone = (const void *)mz;
4946 bp->hw_tx_port_stats = mz->addr;
4947 bp->hw_tx_port_stats_map = mz_phys_addr;
4948 bp->flags |= BNXT_FLAG_PORT_STATS;
4950 /* Display extended statistics if FW supports it */
4951 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4952 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4953 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4956 bp->hw_rx_port_stats_ext = (void *)
4957 ((uint8_t *)bp->hw_rx_port_stats +
4958 sizeof(struct rx_port_stats));
4959 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4960 sizeof(struct rx_port_stats);
4961 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4963 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4964 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4965 bp->hw_tx_port_stats_ext = (void *)
4966 ((uint8_t *)bp->hw_tx_port_stats +
4967 sizeof(struct tx_port_stats));
4968 bp->hw_tx_port_stats_ext_map =
4969 bp->hw_tx_port_stats_map +
4970 sizeof(struct tx_port_stats);
4971 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4977 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4979 struct bnxt *bp = eth_dev->data->dev_private;
4982 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4983 RTE_ETHER_ADDR_LEN *
4986 if (eth_dev->data->mac_addrs == NULL) {
4987 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4991 if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4995 /* Generate a random MAC address, if none was assigned by PF */
4996 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4997 bnxt_eth_hw_addr_random(bp->mac_addr);
4999 "Assign random MAC:" RTE_ETHER_ADDR_PRT_FMT "\n",
5000 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5001 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5003 rc = bnxt_hwrm_set_mac(bp);
5008 /* Copy the permanent MAC from the FUNC_QCAPS response */
5009 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5014 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5018 /* MAC is already configured in FW */
5019 if (BNXT_HAS_DFLT_MAC_SET(bp))
5022 /* Restore the old MAC configured */
5023 rc = bnxt_hwrm_set_mac(bp);
5025 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5030 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5035 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5037 if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
5038 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
5039 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
5040 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
5041 BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
5042 BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
5046 bnxt_get_bp(uint16_t port)
5049 struct rte_eth_dev *dev;
5051 if (!rte_eth_dev_is_valid_port(port)) {
5052 PMD_DRV_LOG(ERR, "Invalid port %d\n", port);
5056 dev = &rte_eth_devices[port];
5057 if (!is_bnxt_supported(dev)) {
5058 PMD_DRV_LOG(ERR, "Device %d not supported\n", port);
5062 bp = (struct bnxt *)dev->data->dev_private;
5063 if (!BNXT_TRUFLOW_EN(bp)) {
5064 PMD_DRV_LOG(ERR, "TRUFLOW not enabled\n");
5072 bnxt_get_svif(uint16_t port_id, bool func_svif,
5073 enum bnxt_ulp_intf_type type)
5075 struct rte_eth_dev *eth_dev;
5078 eth_dev = &rte_eth_devices[port_id];
5079 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5080 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5084 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5087 eth_dev = vfr->parent_dev;
5090 bp = eth_dev->data->dev_private;
5092 return func_svif ? bp->func_svif : bp->port_svif;
5096 bnxt_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type,
5097 uint8_t *mac, uint8_t *parent_mac)
5099 struct rte_eth_dev *eth_dev;
5102 if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF &&
5103 type != BNXT_ULP_INTF_TYPE_PF)
5106 eth_dev = &rte_eth_devices[port];
5107 bp = eth_dev->data->dev_private;
5108 memcpy(mac, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5110 if (type == BNXT_ULP_INTF_TYPE_TRUSTED_VF)
5111 memcpy(parent_mac, bp->parent->mac_addr, RTE_ETHER_ADDR_LEN);
5115 bnxt_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5117 struct rte_eth_dev *eth_dev;
5120 if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF)
5123 eth_dev = &rte_eth_devices[port];
5124 bp = eth_dev->data->dev_private;
5126 return bp->parent->vnic;
5129 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5131 struct rte_eth_dev *eth_dev;
5132 struct bnxt_vnic_info *vnic;
5135 eth_dev = &rte_eth_devices[port];
5136 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5137 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5141 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5142 return vfr->dflt_vnic_id;
5144 eth_dev = vfr->parent_dev;
5147 bp = eth_dev->data->dev_private;
5149 vnic = BNXT_GET_DEFAULT_VNIC(bp);
5151 return vnic->fw_vnic_id;
5155 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5157 struct rte_eth_dev *eth_dev;
5160 eth_dev = &rte_eth_devices[port];
5161 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5162 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5166 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5169 eth_dev = vfr->parent_dev;
5172 bp = eth_dev->data->dev_private;
5177 enum bnxt_ulp_intf_type
5178 bnxt_get_interface_type(uint16_t port)
5180 struct rte_eth_dev *eth_dev;
5183 eth_dev = &rte_eth_devices[port];
5184 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5185 return BNXT_ULP_INTF_TYPE_VF_REP;
5187 bp = eth_dev->data->dev_private;
5189 return BNXT_ULP_INTF_TYPE_PF;
5190 else if (BNXT_VF_IS_TRUSTED(bp))
5191 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5192 else if (BNXT_VF(bp))
5193 return BNXT_ULP_INTF_TYPE_VF;
5195 return BNXT_ULP_INTF_TYPE_INVALID;
5199 bnxt_get_phy_port_id(uint16_t port_id)
5201 struct bnxt_representor *vfr;
5202 struct rte_eth_dev *eth_dev;
5205 eth_dev = &rte_eth_devices[port_id];
5206 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5207 vfr = eth_dev->data->dev_private;
5211 eth_dev = vfr->parent_dev;
5214 bp = eth_dev->data->dev_private;
5216 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5220 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5222 struct rte_eth_dev *eth_dev;
5225 eth_dev = &rte_eth_devices[port_id];
5226 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5227 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5231 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5232 return vfr->fw_fid - 1;
5234 eth_dev = vfr->parent_dev;
5237 bp = eth_dev->data->dev_private;
5239 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5243 bnxt_get_vport(uint16_t port_id)
5245 return (1 << bnxt_get_phy_port_id(port_id));
5248 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5250 struct bnxt_error_recovery_info *info = bp->recovery_info;
5253 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5254 memset(info, 0, sizeof(*info));
5258 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5261 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5264 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5266 bp->recovery_info = info;
5269 static void bnxt_check_fw_status(struct bnxt *bp)
5273 if (!(bp->recovery_info &&
5274 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5277 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5278 if (fw_status != BNXT_FW_STATUS_HEALTHY)
5279 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5283 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5285 struct bnxt_error_recovery_info *info = bp->recovery_info;
5286 uint32_t status_loc;
5289 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5290 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5291 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5292 BNXT_GRCP_WINDOW_2_BASE +
5293 offsetof(struct hcomm_status,
5295 /* If the signature is absent, then FW does not support this feature */
5296 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5297 HCOMM_STATUS_SIGNATURE_VAL)
5301 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5305 bp->recovery_info = info;
5307 memset(info, 0, sizeof(*info));
5310 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5311 BNXT_GRCP_WINDOW_2_BASE +
5312 offsetof(struct hcomm_status,
5315 /* Only pre-map the FW health status GRC register */
5316 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5319 info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5320 info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5321 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5323 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5324 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5326 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5331 /* This function gets the FW version along with the
5332 * capabilities(MAX and current) of the function, vnic,
5333 * error recovery, phy and other chip related info
5335 static int bnxt_get_config(struct bnxt *bp)
5342 rc = bnxt_map_hcomm_fw_status_reg(bp);
5346 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5348 bnxt_check_fw_status(bp);
5352 rc = bnxt_hwrm_func_reset(bp);
5356 rc = bnxt_hwrm_vnic_qcaps(bp);
5360 rc = bnxt_hwrm_queue_qportcfg(bp);
5364 /* Get the MAX capabilities for this function.
5365 * This function also allocates context memory for TQM rings and
5366 * informs the firmware about this allocated backing store memory.
5368 rc = bnxt_hwrm_func_qcaps(bp);
5372 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5376 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5380 bnxt_hwrm_port_mac_qcfg(bp);
5382 bnxt_hwrm_parent_pf_qcfg(bp);
5384 bnxt_hwrm_port_phy_qcaps(bp);
5386 bnxt_alloc_error_recovery_info(bp);
5387 /* Get the adapter error recovery support info */
5388 rc = bnxt_hwrm_error_recovery_qcfg(bp);
5390 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5392 bnxt_hwrm_port_led_qcaps(bp);
5398 bnxt_init_locks(struct bnxt *bp)
5402 err = pthread_mutex_init(&bp->flow_lock, NULL);
5404 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5408 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5410 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5414 err = pthread_mutex_init(&bp->health_check_lock, NULL);
5416 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5420 err = pthread_mutex_init(&bp->err_recovery_lock, NULL);
5422 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n");
5427 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5431 rc = bnxt_get_config(bp);
5435 if (!reconfig_dev) {
5436 rc = bnxt_setup_mac_addr(bp->eth_dev);
5440 rc = bnxt_restore_dflt_mac(bp);
5445 bnxt_config_vf_req_fwd(bp);
5447 rc = bnxt_hwrm_func_driver_register(bp);
5449 PMD_DRV_LOG(ERR, "Failed to register driver");
5454 if (bp->pdev->max_vfs) {
5455 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5457 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5461 rc = bnxt_hwrm_allocate_pf_only(bp);
5464 "Failed to allocate PF resources");
5470 rc = bnxt_alloc_mem(bp, reconfig_dev);
5474 rc = bnxt_setup_int(bp);
5478 rc = bnxt_request_int(bp);
5482 rc = bnxt_init_ctx_mem(bp);
5484 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5492 bnxt_parse_devarg_accum_stats(__rte_unused const char *key,
5493 const char *value, void *opaque_arg)
5495 struct bnxt *bp = opaque_arg;
5496 unsigned long accum_stats;
5499 if (!value || !opaque_arg) {
5501 "Invalid parameter passed to accum-stats devargs.\n");
5505 accum_stats = strtoul(value, &end, 10);
5506 if (end == NULL || *end != '\0' ||
5507 (accum_stats == ULONG_MAX && errno == ERANGE)) {
5509 "Invalid parameter passed to accum-stats devargs.\n");
5513 if (BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats)) {
5515 "Invalid value passed to accum-stats devargs.\n");
5520 bp->flags2 |= BNXT_FLAGS2_ACCUM_STATS_EN;
5521 PMD_DRV_LOG(INFO, "Host-based accum-stats feature enabled.\n");
5523 bp->flags2 &= ~BNXT_FLAGS2_ACCUM_STATS_EN;
5524 PMD_DRV_LOG(INFO, "Host-based accum-stats feature disabled.\n");
5531 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5532 const char *value, void *opaque_arg)
5534 struct bnxt *bp = opaque_arg;
5535 unsigned long flow_xstat;
5538 if (!value || !opaque_arg) {
5540 "Invalid parameter passed to flow_xstat devarg.\n");
5544 flow_xstat = strtoul(value, &end, 10);
5545 if (end == NULL || *end != '\0' ||
5546 (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5548 "Invalid parameter passed to flow_xstat devarg.\n");
5552 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5554 "Invalid value passed to flow_xstat devarg.\n");
5558 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5559 if (BNXT_FLOW_XSTATS_EN(bp))
5560 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5566 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5567 const char *value, void *opaque_arg)
5569 struct bnxt *bp = opaque_arg;
5570 unsigned long max_num_kflows;
5573 if (!value || !opaque_arg) {
5575 "Invalid parameter passed to max_num_kflows devarg.\n");
5579 max_num_kflows = strtoul(value, &end, 10);
5580 if (end == NULL || *end != '\0' ||
5581 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5583 "Invalid parameter passed to max_num_kflows devarg.\n");
5587 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5589 "Invalid value passed to max_num_kflows devarg.\n");
5593 bp->max_num_kflows = max_num_kflows;
5594 if (bp->max_num_kflows)
5595 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5602 bnxt_parse_devarg_app_id(__rte_unused const char *key,
5603 const char *value, void *opaque_arg)
5605 struct bnxt *bp = opaque_arg;
5606 unsigned long app_id;
5609 if (!value || !opaque_arg) {
5611 "Invalid parameter passed to app-id "
5616 app_id = strtoul(value, &end, 10);
5617 if (end == NULL || *end != '\0' ||
5618 (app_id == ULONG_MAX && errno == ERANGE)) {
5620 "Invalid parameter passed to app_id "
5625 if (BNXT_DEVARG_APP_ID_INVALID(app_id)) {
5626 PMD_DRV_LOG(ERR, "Invalid app-id(%d) devargs.\n",
5631 bp->app_id = app_id;
5632 PMD_DRV_LOG(INFO, "app-id=%d feature enabled.\n", (uint16_t)app_id);
5638 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5639 const char *value, void *opaque_arg)
5641 struct bnxt_representor *vfr_bp = opaque_arg;
5642 unsigned long rep_is_pf;
5645 if (!value || !opaque_arg) {
5647 "Invalid parameter passed to rep_is_pf devargs.\n");
5651 rep_is_pf = strtoul(value, &end, 10);
5652 if (end == NULL || *end != '\0' ||
5653 (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5655 "Invalid parameter passed to rep_is_pf devargs.\n");
5659 if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5661 "Invalid value passed to rep_is_pf devargs.\n");
5665 vfr_bp->flags |= rep_is_pf;
5666 if (BNXT_REP_PF(vfr_bp))
5667 PMD_DRV_LOG(INFO, "PF representor\n");
5669 PMD_DRV_LOG(INFO, "VF representor\n");
5675 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5676 const char *value, void *opaque_arg)
5678 struct bnxt_representor *vfr_bp = opaque_arg;
5679 unsigned long rep_based_pf;
5682 if (!value || !opaque_arg) {
5684 "Invalid parameter passed to rep_based_pf "
5689 rep_based_pf = strtoul(value, &end, 10);
5690 if (end == NULL || *end != '\0' ||
5691 (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5693 "Invalid parameter passed to rep_based_pf "
5698 if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5700 "Invalid value passed to rep_based_pf devargs.\n");
5704 vfr_bp->rep_based_pf = rep_based_pf;
5705 vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
5707 PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5713 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5714 const char *value, void *opaque_arg)
5716 struct bnxt_representor *vfr_bp = opaque_arg;
5717 unsigned long rep_q_r2f;
5720 if (!value || !opaque_arg) {
5722 "Invalid parameter passed to rep_q_r2f "
5727 rep_q_r2f = strtoul(value, &end, 10);
5728 if (end == NULL || *end != '\0' ||
5729 (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5731 "Invalid parameter passed to rep_q_r2f "
5736 if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5738 "Invalid value passed to rep_q_r2f devargs.\n");
5742 vfr_bp->rep_q_r2f = rep_q_r2f;
5743 vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5744 PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5750 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5751 const char *value, void *opaque_arg)
5753 struct bnxt_representor *vfr_bp = opaque_arg;
5754 unsigned long rep_q_f2r;
5757 if (!value || !opaque_arg) {
5759 "Invalid parameter passed to rep_q_f2r "
5764 rep_q_f2r = strtoul(value, &end, 10);
5765 if (end == NULL || *end != '\0' ||
5766 (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5768 "Invalid parameter passed to rep_q_f2r "
5773 if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5775 "Invalid value passed to rep_q_f2r devargs.\n");
5779 vfr_bp->rep_q_f2r = rep_q_f2r;
5780 vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5781 PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5787 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5788 const char *value, void *opaque_arg)
5790 struct bnxt_representor *vfr_bp = opaque_arg;
5791 unsigned long rep_fc_r2f;
5794 if (!value || !opaque_arg) {
5796 "Invalid parameter passed to rep_fc_r2f "
5801 rep_fc_r2f = strtoul(value, &end, 10);
5802 if (end == NULL || *end != '\0' ||
5803 (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5805 "Invalid parameter passed to rep_fc_r2f "
5810 if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5812 "Invalid value passed to rep_fc_r2f devargs.\n");
5816 vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5817 vfr_bp->rep_fc_r2f = rep_fc_r2f;
5818 PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5824 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5825 const char *value, void *opaque_arg)
5827 struct bnxt_representor *vfr_bp = opaque_arg;
5828 unsigned long rep_fc_f2r;
5831 if (!value || !opaque_arg) {
5833 "Invalid parameter passed to rep_fc_f2r "
5838 rep_fc_f2r = strtoul(value, &end, 10);
5839 if (end == NULL || *end != '\0' ||
5840 (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5842 "Invalid parameter passed to rep_fc_f2r "
5847 if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5849 "Invalid value passed to rep_fc_f2r devargs.\n");
5853 vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5854 vfr_bp->rep_fc_f2r = rep_fc_f2r;
5855 PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5861 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5863 struct rte_kvargs *kvlist;
5866 if (devargs == NULL)
5869 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5874 * Handler for "flow_xstat" devarg.
5875 * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5877 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5878 bnxt_parse_devarg_flow_xstat, bp);
5883 * Handler for "accum-stats" devarg.
5884 * Invoked as for ex: "-a 0000:00:0d.0,accum-stats=1"
5886 rte_kvargs_process(kvlist, BNXT_DEVARG_ACCUM_STATS,
5887 bnxt_parse_devarg_accum_stats, bp);
5889 * Handler for "max_num_kflows" devarg.
5890 * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5892 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5893 bnxt_parse_devarg_max_num_kflows, bp);
5899 * Handler for "app-id" devarg.
5900 * Invoked as for ex: "-a 000:00:0d.0,app-id=1"
5902 rte_kvargs_process(kvlist, BNXT_DEVARG_APP_ID,
5903 bnxt_parse_devarg_app_id, bp);
5905 rte_kvargs_free(kvlist);
5909 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5913 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5914 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5917 "Failed to alloc switch domain: %d\n", rc);
5920 "Switch domain allocated %d\n",
5921 bp->switch_domain_id);
5927 /* Allocate and initialize various fields in bnxt struct that
5928 * need to be allocated/destroyed only once in the lifetime of the driver
5930 static int bnxt_drv_init(struct rte_eth_dev *eth_dev)
5932 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5933 struct bnxt *bp = eth_dev->data->dev_private;
5936 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5938 if (bnxt_vf_pciid(pci_dev->id.device_id))
5939 bp->flags |= BNXT_FLAG_VF;
5941 if (bnxt_p5_device(pci_dev->id.device_id))
5942 bp->flags |= BNXT_FLAG_CHIP_P5;
5944 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5945 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5946 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5947 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5948 bp->flags |= BNXT_FLAG_STINGRAY;
5950 if (BNXT_TRUFLOW_EN(bp)) {
5951 /* extra mbuf field is required to store CFA code from mark */
5952 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5953 .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5954 .size = sizeof(bnxt_cfa_code_dynfield_t),
5955 .align = __alignof__(bnxt_cfa_code_dynfield_t),
5957 bnxt_cfa_code_dynfield_offset =
5958 rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5959 if (bnxt_cfa_code_dynfield_offset < 0) {
5961 "Failed to register mbuf field for TruFlow mark\n");
5966 rc = bnxt_map_pci_bars(eth_dev);
5969 "Failed to initialize board rc: %x\n", rc);
5973 rc = bnxt_alloc_pf_info(bp);
5977 rc = bnxt_alloc_link_info(bp);
5981 rc = bnxt_alloc_parent_info(bp);
5985 rc = bnxt_alloc_hwrm_resources(bp);
5988 "Failed to allocate response buffer rc: %x\n", rc);
5991 rc = bnxt_alloc_leds_info(bp);
5995 rc = bnxt_alloc_cos_queues(bp);
5999 rc = bnxt_init_locks(bp);
6003 rc = bnxt_alloc_switch_domain(bp);
6011 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
6013 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
6014 static int version_printed;
6018 if (version_printed++ == 0)
6019 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
6021 eth_dev->dev_ops = &bnxt_dev_ops;
6022 eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
6023 eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
6024 eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
6025 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
6026 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
6029 * For secondary processes, we don't initialise any further
6030 * as primary has already done this work.
6032 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6035 rte_eth_copy_pci_info(eth_dev, pci_dev);
6036 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
6038 bp = eth_dev->data->dev_private;
6040 /* Parse dev arguments passed on when starting the DPDK application. */
6041 rc = bnxt_parse_dev_args(bp, pci_dev->device.devargs);
6045 rc = bnxt_drv_init(eth_dev);
6049 rc = bnxt_init_resources(bp, false);
6053 rc = bnxt_alloc_stats_mem(bp);
6058 "Found %s device at mem %" PRIX64 ", node addr %pM\n",
6060 pci_dev->mem_resource[0].phys_addr,
6061 pci_dev->mem_resource[0].addr);
6066 bnxt_dev_uninit(eth_dev);
6071 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
6080 ctx->dma = RTE_BAD_IOVA;
6081 ctx->ctx_id = BNXT_CTX_VAL_INVAL;
6084 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
6086 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
6087 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6088 bp->flow_stat->rx_fc_out_tbl.ctx_id,
6089 bp->flow_stat->max_fc,
6092 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
6093 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6094 bp->flow_stat->tx_fc_out_tbl.ctx_id,
6095 bp->flow_stat->max_fc,
6098 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6099 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
6100 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6102 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6103 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
6104 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6106 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6107 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
6108 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6110 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6111 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
6112 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6115 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
6117 bnxt_unregister_fc_ctx_mem(bp);
6119 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
6120 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
6121 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
6122 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
6125 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
6127 if (BNXT_FLOW_XSTATS_EN(bp))
6128 bnxt_uninit_fc_ctx_mem(bp);
6132 bnxt_free_error_recovery_info(struct bnxt *bp)
6134 rte_free(bp->recovery_info);
6135 bp->recovery_info = NULL;
6136 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
6140 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
6145 bnxt_free_mem(bp, reconfig_dev);
6147 bnxt_hwrm_func_buf_unrgtr(bp);
6148 if (bp->pf != NULL) {
6149 rte_free(bp->pf->vf_req_buf);
6150 bp->pf->vf_req_buf = NULL;
6153 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
6154 bp->flags &= ~BNXT_FLAG_REGISTERED;
6155 bnxt_free_ctx_mem(bp);
6156 if (!reconfig_dev) {
6157 bnxt_free_hwrm_resources(bp);
6158 bnxt_free_error_recovery_info(bp);
6161 bnxt_uninit_ctx_mem(bp);
6163 bnxt_free_flow_stats_info(bp);
6164 if (bp->rep_info != NULL)
6165 bnxt_free_switch_domain(bp);
6166 bnxt_free_rep_info(bp);
6167 rte_free(bp->ptp_cfg);
6173 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
6175 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6178 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
6180 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
6181 bnxt_dev_close_op(eth_dev);
6186 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
6188 struct bnxt *bp = eth_dev->data->dev_private;
6189 struct rte_eth_dev *vf_rep_eth_dev;
6195 for (i = 0; i < bp->num_reps; i++) {
6196 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
6197 if (!vf_rep_eth_dev)
6199 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
6200 vf_rep_eth_dev->data->port_id);
6201 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
6203 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
6204 eth_dev->data->port_id);
6205 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
6210 static void bnxt_free_rep_info(struct bnxt *bp)
6212 rte_free(bp->rep_info);
6213 bp->rep_info = NULL;
6214 rte_free(bp->cfa_code_map);
6215 bp->cfa_code_map = NULL;
6218 static int bnxt_init_rep_info(struct bnxt *bp)
6225 bp->rep_info = rte_zmalloc("bnxt_rep_info",
6226 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
6228 if (!bp->rep_info) {
6229 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
6232 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
6233 sizeof(*bp->cfa_code_map) *
6234 BNXT_MAX_CFA_CODE, 0);
6235 if (!bp->cfa_code_map) {
6236 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
6237 bnxt_free_rep_info(bp);
6241 for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
6242 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
6244 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
6246 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
6247 bnxt_free_rep_info(bp);
6251 rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
6253 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
6254 bnxt_free_rep_info(bp);
6261 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
6262 struct rte_eth_devargs *eth_da,
6263 struct rte_eth_dev *backing_eth_dev,
6264 const char *dev_args)
6266 struct rte_eth_dev *vf_rep_eth_dev;
6267 char name[RTE_ETH_NAME_MAX_LEN];
6268 struct bnxt *backing_bp;
6271 struct rte_kvargs *kvlist = NULL;
6273 if (eth_da->type == RTE_ETH_REPRESENTOR_NONE)
6275 if (eth_da->type != RTE_ETH_REPRESENTOR_VF) {
6276 PMD_DRV_LOG(ERR, "unsupported representor type %d\n",
6280 num_rep = eth_da->nb_representor_ports;
6281 if (num_rep > BNXT_MAX_VF_REPS) {
6282 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
6283 num_rep, BNXT_MAX_VF_REPS);
6287 if (num_rep >= RTE_MAX_ETHPORTS) {
6289 "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6290 num_rep, RTE_MAX_ETHPORTS);
6294 backing_bp = backing_eth_dev->data->dev_private;
6296 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6298 "Not a PF or trusted VF. No Representor support\n");
6299 /* Returning an error is not an option.
6300 * Applications are not handling this correctly
6305 if (bnxt_init_rep_info(backing_bp))
6308 for (i = 0; i < num_rep; i++) {
6309 struct bnxt_representor representor = {
6310 .vf_id = eth_da->representor_ports[i],
6311 .switch_domain_id = backing_bp->switch_domain_id,
6312 .parent_dev = backing_eth_dev
6315 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6316 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6317 representor.vf_id, BNXT_MAX_VF_REPS);
6321 /* representor port net_bdf_port */
6322 snprintf(name, sizeof(name), "net_%s_representor_%d",
6323 pci_dev->device.name, eth_da->representor_ports[i]);
6325 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
6328 * Handler for "rep_is_pf" devarg.
6329 * Invoked as for ex: "-a 000:00:0d.0,
6330 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6332 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
6333 bnxt_parse_devarg_rep_is_pf,
6334 (void *)&representor);
6340 * Handler for "rep_based_pf" devarg.
6341 * Invoked as for ex: "-a 000:00:0d.0,
6342 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6344 ret = rte_kvargs_process(kvlist,
6345 BNXT_DEVARG_REP_BASED_PF,
6346 bnxt_parse_devarg_rep_based_pf,
6347 (void *)&representor);
6353 * Handler for "rep_based_pf" devarg.
6354 * Invoked as for ex: "-a 000:00:0d.0,
6355 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6357 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
6358 bnxt_parse_devarg_rep_q_r2f,
6359 (void *)&representor);
6365 * Handler for "rep_based_pf" devarg.
6366 * Invoked as for ex: "-a 000:00:0d.0,
6367 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6369 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
6370 bnxt_parse_devarg_rep_q_f2r,
6371 (void *)&representor);
6377 * Handler for "rep_based_pf" devarg.
6378 * Invoked as for ex: "-a 000:00:0d.0,
6379 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6381 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
6382 bnxt_parse_devarg_rep_fc_r2f,
6383 (void *)&representor);
6389 * Handler for "rep_based_pf" devarg.
6390 * Invoked as for ex: "-a 000:00:0d.0,
6391 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6393 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
6394 bnxt_parse_devarg_rep_fc_f2r,
6395 (void *)&representor);
6402 ret = rte_eth_dev_create(&pci_dev->device, name,
6403 sizeof(struct bnxt_representor),
6405 bnxt_representor_init,
6408 PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6409 "representor %s.", name);
6413 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6414 if (!vf_rep_eth_dev) {
6415 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6416 " for VF-Rep: %s.", name);
6421 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6422 backing_eth_dev->data->port_id);
6423 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6425 backing_bp->num_reps++;
6429 rte_kvargs_free(kvlist);
6433 /* If num_rep > 1, then rollback already created
6434 * ports, since we'll be failing the probe anyway
6437 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6439 rte_kvargs_free(kvlist);
6444 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6445 struct rte_pci_device *pci_dev)
6447 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6448 struct rte_eth_dev *backing_eth_dev;
6452 if (pci_dev->device.devargs) {
6453 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6459 num_rep = eth_da.nb_representor_ports;
6460 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6463 /* We could come here after first level of probe is already invoked
6464 * as part of an application bringup(OVS-DPDK vswitchd), so first check
6465 * for already allocated eth_dev for the backing device (PF/Trusted VF)
6467 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6468 if (backing_eth_dev == NULL) {
6469 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6470 sizeof(struct bnxt),
6471 eth_dev_pci_specific_init, pci_dev,
6472 bnxt_dev_init, NULL);
6474 if (ret || !num_rep)
6477 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6479 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6480 backing_eth_dev->data->port_id);
6485 /* probe representor ports now */
6486 ret = bnxt_rep_port_probe(pci_dev, ð_da, backing_eth_dev,
6487 pci_dev->device.devargs->args);
6492 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6494 struct rte_eth_dev *eth_dev;
6496 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6498 return 0; /* Invoked typically only by OVS-DPDK, by the
6499 * time it comes here the eth_dev is already
6500 * deleted by rte_eth_dev_close(), so returning
6501 * +ve value will at least help in proper cleanup
6504 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6505 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6506 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6507 return rte_eth_dev_destroy(eth_dev,
6508 bnxt_representor_uninit);
6510 return rte_eth_dev_destroy(eth_dev,
6513 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6517 static struct rte_pci_driver bnxt_rte_pmd = {
6518 .id_table = bnxt_pci_id_map,
6519 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6520 RTE_PCI_DRV_INTR_RMV |
6521 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6524 .probe = bnxt_pci_probe,
6525 .remove = bnxt_pci_remove,
6529 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6531 if (strcmp(dev->device->driver->name, drv->driver.name))
6537 bool is_bnxt_supported(struct rte_eth_dev *dev)
6539 return is_device_supported(dev, &bnxt_rte_pmd);
6542 RTE_LOG_REGISTER_SUFFIX(bnxt_logtype_driver, driver, NOTICE);
6543 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6544 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6545 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");