drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16
  17 #include "bnxt.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_reps.h"
  22 #include "bnxt_ring.h"
  23 #include "bnxt_rxq.h"
  24 #include "bnxt_rxr.h"
  25 #include "bnxt_stats.h"
  26 #include "bnxt_txq.h"
  27 #include "bnxt_txr.h"
  28 #include "bnxt_vnic.h"
  29 #include "hsi_struct_def_dpdk.h"
  30 #include "bnxt_nvm_defs.h"
  31 #include "bnxt_tf_common.h"
  32 #include "ulp_flow_db.h"
  33
  34 #define DRV_MODULE_NAME         "bnxt"
  35 static const char bnxt_version[] =
  36         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  37
  38 /*
  39  * The set of PCI devices this driver supports
  40  */
  41 static const struct rte_pci_id bnxt_pci_id_map[] = {
  42         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  43                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  95         { .vendor_id = 0, /* sentinel */ },
  96 };
  97
  98 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
  99 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
 100 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
 101 #define BNXT_DEVARG_REPRESENTOR "representor"
 102 #define BNXT_DEVARG_REP_BASED_PF  "rep-based-pf"
 103 #define BNXT_DEVARG_REP_IS_PF  "rep-is-pf"
 104 #define BNXT_DEVARG_REP_Q_R2F  "rep-q-r2f"
 105 #define BNXT_DEVARG_REP_Q_F2R  "rep-q-f2r"
 106 #define BNXT_DEVARG_REP_FC_R2F  "rep-fc-r2f"
 107 #define BNXT_DEVARG_REP_FC_F2R  "rep-fc-f2r"
 108
 109 static const char *const bnxt_dev_args[] = {
 110         BNXT_DEVARG_REPRESENTOR,
 111         BNXT_DEVARG_TRUFLOW,
 112         BNXT_DEVARG_FLOW_XSTAT,
 113         BNXT_DEVARG_MAX_NUM_KFLOWS,
 114         BNXT_DEVARG_REP_BASED_PF,
 115         BNXT_DEVARG_REP_IS_PF,
 116         BNXT_DEVARG_REP_Q_R2F,
 117         BNXT_DEVARG_REP_Q_F2R,
 118         BNXT_DEVARG_REP_FC_R2F,
 119         BNXT_DEVARG_REP_FC_F2R,
 120         NULL
 121 };
 122
 123 /*
 124  * truflow == false to disable the feature
 125  * truflow == true to enable the feature
 126  */
 127 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 128
 129 /*
 130  * flow_xstat == false to disable the feature
 131  * flow_xstat == true to enable the feature
 132  */
 133 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 134
 135 /*
 136  * rep_is_pf == false to indicate VF representor
 137  * rep_is_pf == true to indicate PF representor
 138  */
 139 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)        ((rep_is_pf) > 1)
 140
 141 /*
 142  * rep_based_pf == Physical index of the PF
 143  */
 144 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)  ((rep_based_pf) > 15)
 145 /*
 146  * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
 147  */
 148 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)        ((rep_q_r2f) > 3)
 149
 150 /*
 151  * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
 152  */
 153 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)        ((rep_q_f2r) > 3)
 154
 155 /*
 156  * rep_fc_r2f == Flow control for the representor to endpoint direction
 157  */
 158 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)      ((rep_fc_r2f) > 1)
 159
 160 /*
 161  * rep_fc_f2r == Flow control for the endpoint to representor direction
 162  */
 163 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)      ((rep_fc_f2r) > 1)
 164
 165 /*
 166  * max_num_kflows must be >= 32
 167  * and must be a power-of-2 supported value
 168  * return: 1 -> invalid
 169  *         0 -> valid
 170  */
 171 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 172 {
 173         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 174                 return 1;
 175         return 0;
 176 }
 177
 178 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 179 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 180 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 181 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 182 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 183 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 184 static void bnxt_dev_recover(void *arg);
 185 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 186 static void bnxt_free_rep_info(struct bnxt *bp);
 187
 188 int is_bnxt_in_error(struct bnxt *bp)
 189 {
 190         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 191                 return -EIO;
 192         if (bp->flags & BNXT_FLAG_FW_RESET)
 193                 return -EBUSY;
 194
 195         return 0;
 196 }
 197
 198 /***********************/
 199
 200 /*
 201  * High level utility functions
 202  */
 203
 204 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 205 {
 206         if (!BNXT_CHIP_THOR(bp))
 207                 return 1;
 208
 209         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 210                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 211                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 212 }
 213
 214 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 215 {
 216         if (!BNXT_CHIP_THOR(bp))
 217                 return HW_HASH_INDEX_SIZE;
 218
 219         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 220 }
 221
 222 static void bnxt_free_parent_info(struct bnxt *bp)
 223 {
 224         rte_free(bp->parent);
 225 }
 226
 227 static void bnxt_free_pf_info(struct bnxt *bp)
 228 {
 229         rte_free(bp->pf);
 230 }
 231
 232 static void bnxt_free_link_info(struct bnxt *bp)
 233 {
 234         rte_free(bp->link_info);
 235 }
 236
 237 static void bnxt_free_leds_info(struct bnxt *bp)
 238 {
 239         if (BNXT_VF(bp))
 240                 return;
 241
 242         rte_free(bp->leds);
 243         bp->leds = NULL;
 244 }
 245
 246 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 247 {
 248         rte_free(bp->flow_stat);
 249         bp->flow_stat = NULL;
 250 }
 251
 252 static void bnxt_free_cos_queues(struct bnxt *bp)
 253 {
 254         rte_free(bp->rx_cos_queue);
 255         rte_free(bp->tx_cos_queue);
 256 }
 257
 258 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 259 {
 260         bnxt_free_filter_mem(bp);
 261         bnxt_free_vnic_attributes(bp);
 262         bnxt_free_vnic_mem(bp);
 263
 264         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 265          * If the number of rings change across fw update,
 266          * we don't have much choice except to warn the user.
 267          */
 268         if (!reconfig) {
 269                 bnxt_free_stats(bp);
 270                 bnxt_free_tx_rings(bp);
 271                 bnxt_free_rx_rings(bp);
 272         }
 273         bnxt_free_async_cp_ring(bp);
 274         bnxt_free_rxtx_nq_ring(bp);
 275
 276         rte_free(bp->grp_info);
 277         bp->grp_info = NULL;
 278 }
 279
 280 static int bnxt_alloc_parent_info(struct bnxt *bp)
 281 {
 282         bp->parent = rte_zmalloc("bnxt_parent_info",
 283                                  sizeof(struct bnxt_parent_info), 0);
 284         if (bp->parent == NULL)
 285                 return -ENOMEM;
 286
 287         return 0;
 288 }
 289
 290 static int bnxt_alloc_pf_info(struct bnxt *bp)
 291 {
 292         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 293         if (bp->pf == NULL)
 294                 return -ENOMEM;
 295
 296         return 0;
 297 }
 298
 299 static int bnxt_alloc_link_info(struct bnxt *bp)
 300 {
 301         bp->link_info =
 302                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 303         if (bp->link_info == NULL)
 304                 return -ENOMEM;
 305
 306         return 0;
 307 }
 308
 309 static int bnxt_alloc_leds_info(struct bnxt *bp)
 310 {
 311         if (BNXT_VF(bp))
 312                 return 0;
 313
 314         bp->leds = rte_zmalloc("bnxt_leds",
 315                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 316                                0);
 317         if (bp->leds == NULL)
 318                 return -ENOMEM;
 319
 320         return 0;
 321 }
 322
 323 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 324 {
 325         bp->rx_cos_queue =
 326                 rte_zmalloc("bnxt_rx_cosq",
 327                             BNXT_COS_QUEUE_COUNT *
 328                             sizeof(struct bnxt_cos_queue_info),
 329                             0);
 330         if (bp->rx_cos_queue == NULL)
 331                 return -ENOMEM;
 332
 333         bp->tx_cos_queue =
 334                 rte_zmalloc("bnxt_tx_cosq",
 335                             BNXT_COS_QUEUE_COUNT *
 336                             sizeof(struct bnxt_cos_queue_info),
 337                             0);
 338         if (bp->tx_cos_queue == NULL)
 339                 return -ENOMEM;
 340
 341         return 0;
 342 }
 343
 344 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 345 {
 346         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 347                                     sizeof(struct bnxt_flow_stat_info), 0);
 348         if (bp->flow_stat == NULL)
 349                 return -ENOMEM;
 350
 351         return 0;
 352 }
 353
 354 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 355 {
 356         int rc;
 357
 358         rc = bnxt_alloc_ring_grps(bp);
 359         if (rc)
 360                 goto alloc_mem_err;
 361
 362         rc = bnxt_alloc_async_ring_struct(bp);
 363         if (rc)
 364                 goto alloc_mem_err;
 365
 366         rc = bnxt_alloc_vnic_mem(bp);
 367         if (rc)
 368                 goto alloc_mem_err;
 369
 370         rc = bnxt_alloc_vnic_attributes(bp);
 371         if (rc)
 372                 goto alloc_mem_err;
 373
 374         rc = bnxt_alloc_filter_mem(bp);
 375         if (rc)
 376                 goto alloc_mem_err;
 377
 378         rc = bnxt_alloc_async_cp_ring(bp);
 379         if (rc)
 380                 goto alloc_mem_err;
 381
 382         rc = bnxt_alloc_rxtx_nq_ring(bp);
 383         if (rc)
 384                 goto alloc_mem_err;
 385
 386         if (BNXT_FLOW_XSTATS_EN(bp)) {
 387                 rc = bnxt_alloc_flow_stats_info(bp);
 388                 if (rc)
 389                         goto alloc_mem_err;
 390         }
 391
 392         return 0;
 393
 394 alloc_mem_err:
 395         bnxt_free_mem(bp, reconfig);
 396         return rc;
 397 }
 398
 399 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 400 {
 401         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 402         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 403         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 404         struct bnxt_rx_queue *rxq;
 405         unsigned int j;
 406         int rc;
 407
 408         rc = bnxt_vnic_grp_alloc(bp, vnic);
 409         if (rc)
 410                 goto err_out;
 411
 412         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 413                     vnic_id, vnic, vnic->fw_grp_ids);
 414
 415         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 416         if (rc)
 417                 goto err_out;
 418
 419         /* Alloc RSS context only if RSS mode is enabled */
 420         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 421                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 422
 423                 rc = 0;
 424                 for (j = 0; j < nr_ctxs; j++) {
 425                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 426                         if (rc)
 427                                 break;
 428                 }
 429                 if (rc) {
 430                         PMD_DRV_LOG(ERR,
 431                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 432                                     vnic_id, j, rc);
 433                         goto err_out;
 434                 }
 435                 vnic->num_lb_ctxts = nr_ctxs;
 436         }
 437
 438         /*
 439          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 440          * setting is not available at this time, it will not be
 441          * configured correctly in the CFA.
 442          */
 443         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 444                 vnic->vlan_strip = true;
 445         else
 446                 vnic->vlan_strip = false;
 447
 448         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 449         if (rc)
 450                 goto err_out;
 451
 452         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 453         if (rc)
 454                 goto err_out;
 455
 456         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 457                 rxq = bp->eth_dev->data->rx_queues[j];
 458
 459                 PMD_DRV_LOG(DEBUG,
 460                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 461                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 462
 463                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 464                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 465                 else
 466                         vnic->rx_queue_cnt++;
 467         }
 468
 469         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 470
 471         rc = bnxt_vnic_rss_configure(bp, vnic);
 472         if (rc)
 473                 goto err_out;
 474
 475         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 476
 477         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 478                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 479         else
 480                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 481
 482         return 0;
 483 err_out:
 484         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 485                     vnic_id, rc);
 486         return rc;
 487 }
 488
 489 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 490 {
 491         int rc = 0;
 492
 493         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 494                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 495         if (rc)
 496                 return rc;
 497
 498         PMD_DRV_LOG(DEBUG,
 499                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 500                     " rx_fc_in_tbl.ctx_id = %d\n",
 501                     bp->flow_stat->rx_fc_in_tbl.va,
 502                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 503                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 504
 505         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 506                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 507         if (rc)
 508                 return rc;
 509
 510         PMD_DRV_LOG(DEBUG,
 511                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 512                     " rx_fc_out_tbl.ctx_id = %d\n",
 513                     bp->flow_stat->rx_fc_out_tbl.va,
 514                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 515                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 516
 517         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 518                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 519         if (rc)
 520                 return rc;
 521
 522         PMD_DRV_LOG(DEBUG,
 523                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 524                     " tx_fc_in_tbl.ctx_id = %d\n",
 525                     bp->flow_stat->tx_fc_in_tbl.va,
 526                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 527                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 528
 529         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 530                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 531         if (rc)
 532                 return rc;
 533
 534         PMD_DRV_LOG(DEBUG,
 535                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 536                     " tx_fc_out_tbl.ctx_id = %d\n",
 537                     bp->flow_stat->tx_fc_out_tbl.va,
 538                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 539                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 540
 541         memset(bp->flow_stat->rx_fc_out_tbl.va,
 542                0,
 543                bp->flow_stat->rx_fc_out_tbl.size);
 544         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 545                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 546                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 547                                        bp->flow_stat->max_fc,
 548                                        true);
 549         if (rc)
 550                 return rc;
 551
 552         memset(bp->flow_stat->tx_fc_out_tbl.va,
 553                0,
 554                bp->flow_stat->tx_fc_out_tbl.size);
 555         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 556                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 557                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 558                                        bp->flow_stat->max_fc,
 559                                        true);
 560
 561         return rc;
 562 }
 563
 564 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 565                                   struct bnxt_ctx_mem_buf_info *ctx)
 566 {
 567         if (!ctx)
 568                 return -EINVAL;
 569
 570         ctx->va = rte_zmalloc(type, size, 0);
 571         if (ctx->va == NULL)
 572                 return -ENOMEM;
 573         rte_mem_lock_page(ctx->va);
 574         ctx->size = size;
 575         ctx->dma = rte_mem_virt2iova(ctx->va);
 576         if (ctx->dma == RTE_BAD_IOVA)
 577                 return -ENOMEM;
 578
 579         return 0;
 580 }
 581
 582 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 583 {
 584         struct rte_pci_device *pdev = bp->pdev;
 585         char type[RTE_MEMZONE_NAMESIZE];
 586         uint16_t max_fc;
 587         int rc = 0;
 588
 589         max_fc = bp->flow_stat->max_fc;
 590
 591         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 592                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 593         /* 4 bytes for each counter-id */
 594         rc = bnxt_alloc_ctx_mem_buf(type,
 595                                     max_fc * 4,
 596                                     &bp->flow_stat->rx_fc_in_tbl);
 597         if (rc)
 598                 return rc;
 599
 600         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 601                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 602         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 603         rc = bnxt_alloc_ctx_mem_buf(type,
 604                                     max_fc * 16,
 605                                     &bp->flow_stat->rx_fc_out_tbl);
 606         if (rc)
 607                 return rc;
 608
 609         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 610                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 611         /* 4 bytes for each counter-id */
 612         rc = bnxt_alloc_ctx_mem_buf(type,
 613                                     max_fc * 4,
 614                                     &bp->flow_stat->tx_fc_in_tbl);
 615         if (rc)
 616                 return rc;
 617
 618         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 619                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 620         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 621         rc = bnxt_alloc_ctx_mem_buf(type,
 622                                     max_fc * 16,
 623                                     &bp->flow_stat->tx_fc_out_tbl);
 624         if (rc)
 625                 return rc;
 626
 627         rc = bnxt_register_fc_ctx_mem(bp);
 628
 629         return rc;
 630 }
 631
 632 static int bnxt_init_ctx_mem(struct bnxt *bp)
 633 {
 634         int rc = 0;
 635
 636         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 637             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 638             !BNXT_FLOW_XSTATS_EN(bp))
 639                 return 0;
 640
 641         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 642         if (rc)
 643                 return rc;
 644
 645         rc = bnxt_init_fc_ctx_mem(bp);
 646
 647         return rc;
 648 }
 649
 650 static int bnxt_update_phy_setting(struct bnxt *bp)
 651 {
 652         struct rte_eth_link new;
 653         int rc;
 654
 655         rc = bnxt_get_hwrm_link_config(bp, &new);
 656         if (rc) {
 657                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 658                 return rc;
 659         }
 660
 661         /*
 662          * On BCM957508-N2100 adapters, FW will not allow any user other
 663          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 664          * always returns link up. Force phy update always in that case.
 665          */
 666         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 667                 rc = bnxt_set_hwrm_link_config(bp, true);
 668                 if (rc) {
 669                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 670                         return rc;
 671                 }
 672         }
 673
 674         return rc;
 675 }
 676
 677 static int bnxt_init_chip(struct bnxt *bp)
 678 {
 679         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 680         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 681         uint32_t intr_vector = 0;
 682         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 683         uint32_t vec = BNXT_MISC_VEC_ID;
 684         unsigned int i, j;
 685         int rc;
 686
 687         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 688                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 689                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 690                 bp->flags |= BNXT_FLAG_JUMBO;
 691         } else {
 692                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 693                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 694                 bp->flags &= ~BNXT_FLAG_JUMBO;
 695         }
 696
 697         /* THOR does not support ring groups.
 698          * But we will use the array to save RSS context IDs.
 699          */
 700         if (BNXT_CHIP_THOR(bp))
 701                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 702
 703         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 704         if (rc) {
 705                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 706                 goto err_out;
 707         }
 708
 709         rc = bnxt_alloc_hwrm_rings(bp);
 710         if (rc) {
 711                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 712                 goto err_out;
 713         }
 714
 715         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 716         if (rc) {
 717                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 718                 goto err_out;
 719         }
 720
 721         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 722                 goto skip_cosq_cfg;
 723
 724         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 725                 if (bp->rx_cos_queue[i].id != 0xff) {
 726                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 727
 728                         if (!vnic) {
 729                                 PMD_DRV_LOG(ERR,
 730                                             "Num pools more than FW profile\n");
 731                                 rc = -EINVAL;
 732                                 goto err_out;
 733                         }
 734                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 735                         bp->rx_cosq_cnt++;
 736                 }
 737         }
 738
 739 skip_cosq_cfg:
 740         rc = bnxt_mq_rx_configure(bp);
 741         if (rc) {
 742                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 743                 goto err_out;
 744         }
 745
 746         /* VNIC configuration */
 747         for (i = 0; i < bp->nr_vnics; i++) {
 748                 rc = bnxt_setup_one_vnic(bp, i);
 749                 if (rc)
 750                         goto err_out;
 751         }
 752
 753         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 754         if (rc) {
 755                 PMD_DRV_LOG(ERR,
 756                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 757                 goto err_out;
 758         }
 759
 760         /* check and configure queue intr-vector mapping */
 761         if ((rte_intr_cap_multiple(intr_handle) ||
 762              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 763             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 764                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 765                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 766                 if (intr_vector > bp->rx_cp_nr_rings) {
 767                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 768                                         bp->rx_cp_nr_rings);
 769                         return -ENOTSUP;
 770                 }
 771                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 772                 if (rc)
 773                         return rc;
 774         }
 775
 776         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 777                 intr_handle->intr_vec =
 778                         rte_zmalloc("intr_vec",
 779                                     bp->eth_dev->data->nb_rx_queues *
 780                                     sizeof(int), 0);
 781                 if (intr_handle->intr_vec == NULL) {
 782                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 783                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 784                         rc = -ENOMEM;
 785                         goto err_disable;
 786                 }
 787                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 788                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 789                          intr_handle->intr_vec, intr_handle->nb_efd,
 790                         intr_handle->max_intr);
 791                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 792                      queue_id++) {
 793                         intr_handle->intr_vec[queue_id] =
 794                                                         vec + BNXT_RX_VEC_START;
 795                         if (vec < base + intr_handle->nb_efd - 1)
 796                                 vec++;
 797                 }
 798         }
 799
 800         /* enable uio/vfio intr/eventfd mapping */
 801         rc = rte_intr_enable(intr_handle);
 802 #ifndef RTE_EXEC_ENV_FREEBSD
 803         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 804         if (rc)
 805                 goto err_free;
 806 #endif
 807
 808         rc = bnxt_update_phy_setting(bp);
 809         if (rc)
 810                 goto err_free;
 811
 812         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 813         if (!bp->mark_table)
 814                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 815
 816         return 0;
 817
 818 err_free:
 819         rte_free(intr_handle->intr_vec);
 820 err_disable:
 821         rte_intr_efd_disable(intr_handle);
 822 err_out:
 823         /* Some of the error status returned by FW may not be from errno.h */
 824         if (rc > 0)
 825                 rc = -EIO;
 826
 827         return rc;
 828 }
 829
 830 static int bnxt_shutdown_nic(struct bnxt *bp)
 831 {
 832         bnxt_free_all_hwrm_resources(bp);
 833         bnxt_free_all_filters(bp);
 834         bnxt_free_all_vnics(bp);
 835         return 0;
 836 }
 837
 838 /*
 839  * Device configuration and status function
 840  */
 841
 842 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 843 {
 844         uint32_t link_speed = bp->link_info->support_speeds;
 845         uint32_t speed_capa = 0;
 846
 847         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 848                 speed_capa |= ETH_LINK_SPEED_100M;
 849         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 850                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 851         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 852                 speed_capa |= ETH_LINK_SPEED_1G;
 853         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 854                 speed_capa |= ETH_LINK_SPEED_2_5G;
 855         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 856                 speed_capa |= ETH_LINK_SPEED_10G;
 857         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 858                 speed_capa |= ETH_LINK_SPEED_20G;
 859         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 860                 speed_capa |= ETH_LINK_SPEED_25G;
 861         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 862                 speed_capa |= ETH_LINK_SPEED_40G;
 863         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 864                 speed_capa |= ETH_LINK_SPEED_50G;
 865         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 866                 speed_capa |= ETH_LINK_SPEED_100G;
 867         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
 868                 speed_capa |= ETH_LINK_SPEED_50G;
 869         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
 870                 speed_capa |= ETH_LINK_SPEED_100G;
 871         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
 872                 speed_capa |= ETH_LINK_SPEED_200G;
 873
 874         if (bp->link_info->auto_mode ==
 875             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 876                 speed_capa |= ETH_LINK_SPEED_FIXED;
 877         else
 878                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 879
 880         return speed_capa;
 881 }
 882
 883 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 884                                 struct rte_eth_dev_info *dev_info)
 885 {
 886         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 887         struct bnxt *bp = eth_dev->data->dev_private;
 888         uint16_t max_vnics, i, j, vpool, vrxq;
 889         unsigned int max_rx_rings;
 890         int rc;
 891
 892         rc = is_bnxt_in_error(bp);
 893         if (rc)
 894                 return rc;
 895
 896         /* MAC Specifics */
 897         dev_info->max_mac_addrs = bp->max_l2_ctx;
 898         dev_info->max_hash_mac_addrs = 0;
 899
 900         /* PF/VF specifics */
 901         if (BNXT_PF(bp))
 902                 dev_info->max_vfs = pdev->max_vfs;
 903
 904         max_rx_rings = BNXT_MAX_RINGS(bp);
 905         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 906         dev_info->max_rx_queues = max_rx_rings;
 907         dev_info->max_tx_queues = max_rx_rings;
 908         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 909         dev_info->hash_key_size = 40;
 910         max_vnics = bp->max_vnics;
 911
 912         /* MTU specifics */
 913         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 914         dev_info->max_mtu = BNXT_MAX_MTU;
 915
 916         /* Fast path specifics */
 917         dev_info->min_rx_bufsize = 1;
 918         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 919
 920         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 921         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 922                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 923         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 924         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
 925                                     dev_info->tx_queue_offload_capa;
 926         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 927
 928         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 929
 930         /* *INDENT-OFF* */
 931         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 932                 .rx_thresh = {
 933                         .pthresh = 8,
 934                         .hthresh = 8,
 935                         .wthresh = 0,
 936                 },
 937                 .rx_free_thresh = 32,
 938                 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
 939         };
 940
 941         dev_info->default_txconf = (struct rte_eth_txconf) {
 942                 .tx_thresh = {
 943                         .pthresh = 32,
 944                         .hthresh = 0,
 945                         .wthresh = 0,
 946                 },
 947                 .tx_free_thresh = 32,
 948                 .tx_rs_thresh = 32,
 949         };
 950         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 951
 952         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 953         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 954         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 955         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 956         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 957
 958         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
 959                 dev_info->switch_info.name = eth_dev->device->name;
 960                 dev_info->switch_info.domain_id = bp->switch_domain_id;
 961                 dev_info->switch_info.port_id =
 962                                 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
 963                                     BNXT_SWITCH_PORT_ID_TRUSTED_VF;
 964         }
 965
 966         /* *INDENT-ON* */
 967
 968         /*
 969          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 970          *       need further investigation.
 971          */
 972
 973         /* VMDq resources */
 974         vpool = 64; /* ETH_64_POOLS */
 975         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 976         for (i = 0; i < 4; vpool >>= 1, i++) {
 977                 if (max_vnics > vpool) {
 978                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 979                                 if (dev_info->max_rx_queues > vrxq) {
 980                                         if (vpool > vrxq)
 981                                                 vpool = vrxq;
 982                                         goto found;
 983                                 }
 984                         }
 985                         /* Not enough resources to support VMDq */
 986                         break;
 987                 }
 988         }
 989         /* Not enough resources to support VMDq */
 990         vpool = 0;
 991         vrxq = 0;
 992 found:
 993         dev_info->max_vmdq_pools = vpool;
 994         dev_info->vmdq_queue_num = vrxq;
 995
 996         dev_info->vmdq_pool_base = 0;
 997         dev_info->vmdq_queue_base = 0;
 998
 999         return 0;
1000 }
1001
1002 /* Configure the device based on the configuration provided */
1003 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1004 {
1005         struct bnxt *bp = eth_dev->data->dev_private;
1006         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1007         int rc;
1008
1009         bp->rx_queues = (void *)eth_dev->data->rx_queues;
1010         bp->tx_queues = (void *)eth_dev->data->tx_queues;
1011         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1012         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1013
1014         rc = is_bnxt_in_error(bp);
1015         if (rc)
1016                 return rc;
1017
1018         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1019                 rc = bnxt_hwrm_check_vf_rings(bp);
1020                 if (rc) {
1021                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1022                         return -ENOSPC;
1023                 }
1024
1025                 /* If a resource has already been allocated - in this case
1026                  * it is the async completion ring, free it. Reallocate it after
1027                  * resource reservation. This will ensure the resource counts
1028                  * are calculated correctly.
1029                  */
1030
1031                 pthread_mutex_lock(&bp->def_cp_lock);
1032
1033                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1034                         bnxt_disable_int(bp);
1035                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
1036                 }
1037
1038                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1039                 if (rc) {
1040                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1041                         pthread_mutex_unlock(&bp->def_cp_lock);
1042                         return -ENOSPC;
1043                 }
1044
1045                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1046                         rc = bnxt_alloc_async_cp_ring(bp);
1047                         if (rc) {
1048                                 pthread_mutex_unlock(&bp->def_cp_lock);
1049                                 return rc;
1050                         }
1051                         bnxt_enable_int(bp);
1052                 }
1053
1054                 pthread_mutex_unlock(&bp->def_cp_lock);
1055         } else {
1056                 /* legacy driver needs to get updated values */
1057                 rc = bnxt_hwrm_func_qcaps(bp);
1058                 if (rc) {
1059                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
1060                         return rc;
1061                 }
1062         }
1063
1064         /* Inherit new configurations */
1065         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1066             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1067             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1068                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1069             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1070             bp->max_stat_ctx)
1071                 goto resource_error;
1072
1073         if (BNXT_HAS_RING_GRPS(bp) &&
1074             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1075                 goto resource_error;
1076
1077         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1078             bp->max_vnics < eth_dev->data->nb_rx_queues)
1079                 goto resource_error;
1080
1081         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1082         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1083
1084         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1085                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1086         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1087
1088         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1089                 eth_dev->data->mtu =
1090                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1091                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1092                         BNXT_NUM_VLANS;
1093                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1094         }
1095         return 0;
1096
1097 resource_error:
1098         PMD_DRV_LOG(ERR,
1099                     "Insufficient resources to support requested config\n");
1100         PMD_DRV_LOG(ERR,
1101                     "Num Queues Requested: Tx %d, Rx %d\n",
1102                     eth_dev->data->nb_tx_queues,
1103                     eth_dev->data->nb_rx_queues);
1104         PMD_DRV_LOG(ERR,
1105                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1106                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1107                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1108         return -ENOSPC;
1109 }
1110
1111 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1112 {
1113         struct rte_eth_link *link = &eth_dev->data->dev_link;
1114
1115         if (link->link_status)
1116                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1117                         eth_dev->data->port_id,
1118                         (uint32_t)link->link_speed,
1119                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1120                         ("full-duplex") : ("half-duplex\n"));
1121         else
1122                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1123                         eth_dev->data->port_id);
1124 }
1125
1126 /*
1127  * Determine whether the current configuration requires support for scattered
1128  * receive; return 1 if scattered receive is required and 0 if not.
1129  */
1130 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1131 {
1132         uint16_t buf_size;
1133         int i;
1134
1135         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1136                 return 1;
1137
1138         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1139                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1140
1141                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1142                                       RTE_PKTMBUF_HEADROOM);
1143                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1144                         return 1;
1145         }
1146         return 0;
1147 }
1148
1149 static eth_rx_burst_t
1150 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1151 {
1152         struct bnxt *bp = eth_dev->data->dev_private;
1153
1154 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1155 #ifndef RTE_LIBRTE_IEEE1588
1156         /*
1157          * Vector mode receive can be enabled only if scatter rx is not
1158          * in use and rx offloads are limited to VLAN stripping and
1159          * CRC stripping.
1160          */
1161         if (!eth_dev->data->scattered_rx &&
1162             !(eth_dev->data->dev_conf.rxmode.offloads &
1163               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1164                 DEV_RX_OFFLOAD_KEEP_CRC |
1165                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1166                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1167                 DEV_RX_OFFLOAD_UDP_CKSUM |
1168                 DEV_RX_OFFLOAD_TCP_CKSUM |
1169                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1170                 DEV_RX_OFFLOAD_RSS_HASH |
1171                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1172             !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp)) {
1173                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1174                             eth_dev->data->port_id);
1175                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1176                 return bnxt_recv_pkts_vec;
1177         }
1178         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1179                     eth_dev->data->port_id);
1180         PMD_DRV_LOG(INFO,
1181                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1182                     eth_dev->data->port_id,
1183                     eth_dev->data->scattered_rx,
1184                     eth_dev->data->dev_conf.rxmode.offloads);
1185 #endif
1186 #endif
1187         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1188         return bnxt_recv_pkts;
1189 }
1190
1191 static eth_tx_burst_t
1192 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1193 {
1194 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1195 #ifndef RTE_LIBRTE_IEEE1588
1196         uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1197         struct bnxt *bp = eth_dev->data->dev_private;
1198
1199         /*
1200          * Vector mode transmit can be enabled only if not using scatter rx
1201          * or tx offloads.
1202          */
1203         if (!eth_dev->data->scattered_rx &&
1204             !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
1205             !BNXT_TRUFLOW_EN(bp)) {
1206                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1207                             eth_dev->data->port_id);
1208                 return bnxt_xmit_pkts_vec;
1209         }
1210         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1211                     eth_dev->data->port_id);
1212         PMD_DRV_LOG(INFO,
1213                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1214                     eth_dev->data->port_id,
1215                     eth_dev->data->scattered_rx,
1216                     offloads);
1217 #endif
1218 #endif
1219         return bnxt_xmit_pkts;
1220 }
1221
1222 static int bnxt_handle_if_change_status(struct bnxt *bp)
1223 {
1224         int rc;
1225
1226         /* Since fw has undergone a reset and lost all contexts,
1227          * set fatal flag to not issue hwrm during cleanup
1228          */
1229         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1230         bnxt_uninit_resources(bp, true);
1231
1232         /* clear fatal flag so that re-init happens */
1233         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1234         rc = bnxt_init_resources(bp, true);
1235
1236         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1237
1238         return rc;
1239 }
1240
1241 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1242 {
1243         struct bnxt *bp = eth_dev->data->dev_private;
1244         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1245         int vlan_mask = 0;
1246         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1247
1248         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1249                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1250                 return -EINVAL;
1251         }
1252
1253         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1254                 PMD_DRV_LOG(ERR,
1255                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1256                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1257         }
1258
1259         do {
1260                 rc = bnxt_hwrm_if_change(bp, true);
1261                 if (rc == 0 || rc != -EAGAIN)
1262                         break;
1263
1264                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1265         } while (retry_cnt--);
1266
1267         if (rc)
1268                 return rc;
1269
1270         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1271                 rc = bnxt_handle_if_change_status(bp);
1272                 if (rc)
1273                         return rc;
1274         }
1275
1276         bnxt_enable_int(bp);
1277
1278         rc = bnxt_init_chip(bp);
1279         if (rc)
1280                 goto error;
1281
1282         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1283         eth_dev->data->dev_started = 1;
1284
1285         bnxt_link_update_op(eth_dev, 1);
1286
1287         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1288                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1289         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1290                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1291         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1292         if (rc)
1293                 goto error;
1294
1295         /* Initialize bnxt ULP port details */
1296         rc = bnxt_ulp_port_init(bp);
1297         if (rc)
1298                 goto error;
1299
1300         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1301         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1302
1303         bnxt_schedule_fw_health_check(bp);
1304
1305         return 0;
1306
1307 error:
1308         bnxt_shutdown_nic(bp);
1309         bnxt_free_tx_mbufs(bp);
1310         bnxt_free_rx_mbufs(bp);
1311         bnxt_hwrm_if_change(bp, false);
1312         eth_dev->data->dev_started = 0;
1313         return rc;
1314 }
1315
1316 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1317 {
1318         struct bnxt *bp = eth_dev->data->dev_private;
1319         int rc = 0;
1320
1321         if (!bp->link_info->link_up)
1322                 rc = bnxt_set_hwrm_link_config(bp, true);
1323         if (!rc)
1324                 eth_dev->data->dev_link.link_status = 1;
1325
1326         bnxt_print_link_info(eth_dev);
1327         return rc;
1328 }
1329
1330 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1331 {
1332         struct bnxt *bp = eth_dev->data->dev_private;
1333
1334         eth_dev->data->dev_link.link_status = 0;
1335         bnxt_set_hwrm_link_config(bp, false);
1336         bp->link_info->link_up = 0;
1337
1338         return 0;
1339 }
1340
1341 static void bnxt_free_switch_domain(struct bnxt *bp)
1342 {
1343         if (bp->switch_domain_id)
1344                 rte_eth_switch_domain_free(bp->switch_domain_id);
1345 }
1346
1347 /* Unload the driver, release resources */
1348 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1349 {
1350         struct bnxt *bp = eth_dev->data->dev_private;
1351         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1352         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1353         struct rte_eth_link link;
1354
1355         eth_dev->data->dev_started = 0;
1356         eth_dev->data->scattered_rx = 0;
1357
1358         /* Prevent crashes when queues are still in use */
1359         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1360         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1361
1362         bnxt_disable_int(bp);
1363
1364         /* disable uio/vfio intr/eventfd mapping */
1365         rte_intr_disable(intr_handle);
1366
1367         /* Stop the child representors for this device */
1368         bnxt_rep_stop_all(bp);
1369
1370         /* delete the bnxt ULP port details */
1371         bnxt_ulp_port_deinit(bp);
1372
1373         bnxt_cancel_fw_health_check(bp);
1374
1375         /* Do not bring link down during reset recovery */
1376         if (!is_bnxt_in_error(bp)) {
1377                 bnxt_dev_set_link_down_op(eth_dev);
1378                 /* Wait for link to be reset */
1379                 if (BNXT_SINGLE_PF(bp))
1380                         rte_delay_ms(500);
1381                 /* clear the recorded link status */
1382                 memset(&link, 0, sizeof(link));
1383                 rte_eth_linkstatus_set(eth_dev, &link);
1384         }
1385
1386         /* Clean queue intr-vector mapping */
1387         rte_intr_efd_disable(intr_handle);
1388         if (intr_handle->intr_vec != NULL) {
1389                 rte_free(intr_handle->intr_vec);
1390                 intr_handle->intr_vec = NULL;
1391         }
1392
1393         bnxt_hwrm_port_clr_stats(bp);
1394         bnxt_free_tx_mbufs(bp);
1395         bnxt_free_rx_mbufs(bp);
1396         /* Process any remaining notifications in default completion queue */
1397         bnxt_int_handler(eth_dev);
1398         bnxt_shutdown_nic(bp);
1399         bnxt_hwrm_if_change(bp, false);
1400
1401         rte_free(bp->mark_table);
1402         bp->mark_table = NULL;
1403
1404         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1405         bp->rx_cosq_cnt = 0;
1406         /* All filters are deleted on a port stop. */
1407         if (BNXT_FLOW_XSTATS_EN(bp))
1408                 bp->flow_stat->flow_count = 0;
1409 }
1410
1411 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1412 {
1413         struct bnxt *bp = eth_dev->data->dev_private;
1414
1415         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1416                 return 0;
1417
1418         /* cancel the recovery handler before remove dev */
1419         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1420         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1421         bnxt_cancel_fc_thread(bp);
1422
1423         if (eth_dev->data->dev_started)
1424                 bnxt_dev_stop_op(eth_dev);
1425
1426         bnxt_free_switch_domain(bp);
1427
1428         bnxt_uninit_resources(bp, false);
1429
1430         bnxt_free_leds_info(bp);
1431         bnxt_free_cos_queues(bp);
1432         bnxt_free_link_info(bp);
1433         bnxt_free_pf_info(bp);
1434         bnxt_free_parent_info(bp);
1435
1436         eth_dev->dev_ops = NULL;
1437         eth_dev->rx_pkt_burst = NULL;
1438         eth_dev->tx_pkt_burst = NULL;
1439
1440         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1441         bp->tx_mem_zone = NULL;
1442         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1443         bp->rx_mem_zone = NULL;
1444
1445         bnxt_hwrm_free_vf_info(bp);
1446
1447         rte_free(bp->grp_info);
1448         bp->grp_info = NULL;
1449
1450         return 0;
1451 }
1452
1453 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1454                                     uint32_t index)
1455 {
1456         struct bnxt *bp = eth_dev->data->dev_private;
1457         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1458         struct bnxt_vnic_info *vnic;
1459         struct bnxt_filter_info *filter, *temp_filter;
1460         uint32_t i;
1461
1462         if (is_bnxt_in_error(bp))
1463                 return;
1464
1465         /*
1466          * Loop through all VNICs from the specified filter flow pools to
1467          * remove the corresponding MAC addr filter
1468          */
1469         for (i = 0; i < bp->nr_vnics; i++) {
1470                 if (!(pool_mask & (1ULL << i)))
1471                         continue;
1472
1473                 vnic = &bp->vnic_info[i];
1474                 filter = STAILQ_FIRST(&vnic->filter);
1475                 while (filter) {
1476                         temp_filter = STAILQ_NEXT(filter, next);
1477                         if (filter->mac_index == index) {
1478                                 STAILQ_REMOVE(&vnic->filter, filter,
1479                                                 bnxt_filter_info, next);
1480                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1481                                 bnxt_free_filter(bp, filter);
1482                         }
1483                         filter = temp_filter;
1484                 }
1485         }
1486 }
1487
1488 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1489                                struct rte_ether_addr *mac_addr, uint32_t index,
1490                                uint32_t pool)
1491 {
1492         struct bnxt_filter_info *filter;
1493         int rc = 0;
1494
1495         /* Attach requested MAC address to the new l2_filter */
1496         STAILQ_FOREACH(filter, &vnic->filter, next) {
1497                 if (filter->mac_index == index) {
1498                         PMD_DRV_LOG(DEBUG,
1499                                     "MAC addr already existed for pool %d\n",
1500                                     pool);
1501                         return 0;
1502                 }
1503         }
1504
1505         filter = bnxt_alloc_filter(bp);
1506         if (!filter) {
1507                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1508                 return -ENODEV;
1509         }
1510
1511         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1512          * if the MAC that's been programmed now is a different one, then,
1513          * copy that addr to filter->l2_addr
1514          */
1515         if (mac_addr)
1516                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1517         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1518
1519         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1520         if (!rc) {
1521                 filter->mac_index = index;
1522                 if (filter->mac_index == 0)
1523                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1524                 else
1525                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1526         } else {
1527                 bnxt_free_filter(bp, filter);
1528         }
1529
1530         return rc;
1531 }
1532
1533 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1534                                 struct rte_ether_addr *mac_addr,
1535                                 uint32_t index, uint32_t pool)
1536 {
1537         struct bnxt *bp = eth_dev->data->dev_private;
1538         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1539         int rc = 0;
1540
1541         rc = is_bnxt_in_error(bp);
1542         if (rc)
1543                 return rc;
1544
1545         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1546                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1547                 return -ENOTSUP;
1548         }
1549
1550         if (!vnic) {
1551                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1552                 return -EINVAL;
1553         }
1554
1555         /* Filter settings will get applied when port is started */
1556         if (!eth_dev->data->dev_started)
1557                 return 0;
1558
1559         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1560
1561         return rc;
1562 }
1563
1564 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1565 {
1566         int rc = 0;
1567         struct bnxt *bp = eth_dev->data->dev_private;
1568         struct rte_eth_link new;
1569         int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1570                         BNXT_MIN_LINK_WAIT_CNT;
1571
1572         rc = is_bnxt_in_error(bp);
1573         if (rc)
1574                 return rc;
1575
1576         memset(&new, 0, sizeof(new));
1577         do {
1578                 /* Retrieve link info from hardware */
1579                 rc = bnxt_get_hwrm_link_config(bp, &new);
1580                 if (rc) {
1581                         new.link_speed = ETH_LINK_SPEED_100M;
1582                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1583                         PMD_DRV_LOG(ERR,
1584                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1585                         goto out;
1586                 }
1587
1588                 if (!wait_to_complete || new.link_status)
1589                         break;
1590
1591                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1592         } while (cnt--);
1593
1594         /* Only single function PF can bring phy down.
1595          * When port is stopped, report link down for VF/MH/NPAR functions.
1596          */
1597         if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1598                 memset(&new, 0, sizeof(new));
1599
1600 out:
1601         /* Timed out or success */
1602         if (new.link_status != eth_dev->data->dev_link.link_status ||
1603         new.link_speed != eth_dev->data->dev_link.link_speed) {
1604                 rte_eth_linkstatus_set(eth_dev, &new);
1605
1606                 rte_eth_dev_callback_process(eth_dev,
1607                                              RTE_ETH_EVENT_INTR_LSC,
1608                                              NULL);
1609
1610                 bnxt_print_link_info(eth_dev);
1611         }
1612
1613         return rc;
1614 }
1615
1616 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1617 {
1618         struct bnxt *bp = eth_dev->data->dev_private;
1619         struct bnxt_vnic_info *vnic;
1620         uint32_t old_flags;
1621         int rc;
1622
1623         rc = is_bnxt_in_error(bp);
1624         if (rc)
1625                 return rc;
1626
1627         /* Filter settings will get applied when port is started */
1628         if (!eth_dev->data->dev_started)
1629                 return 0;
1630
1631         if (bp->vnic_info == NULL)
1632                 return 0;
1633
1634         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1635
1636         old_flags = vnic->flags;
1637         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1638         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1639         if (rc != 0)
1640                 vnic->flags = old_flags;
1641
1642         return rc;
1643 }
1644
1645 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1646 {
1647         struct bnxt *bp = eth_dev->data->dev_private;
1648         struct bnxt_vnic_info *vnic;
1649         uint32_t old_flags;
1650         int rc;
1651
1652         rc = is_bnxt_in_error(bp);
1653         if (rc)
1654                 return rc;
1655
1656         /* Filter settings will get applied when port is started */
1657         if (!eth_dev->data->dev_started)
1658                 return 0;
1659
1660         if (bp->vnic_info == NULL)
1661                 return 0;
1662
1663         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1664
1665         old_flags = vnic->flags;
1666         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1667         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1668         if (rc != 0)
1669                 vnic->flags = old_flags;
1670
1671         return rc;
1672 }
1673
1674 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1675 {
1676         struct bnxt *bp = eth_dev->data->dev_private;
1677         struct bnxt_vnic_info *vnic;
1678         uint32_t old_flags;
1679         int rc;
1680
1681         rc = is_bnxt_in_error(bp);
1682         if (rc)
1683                 return rc;
1684
1685         /* Filter settings will get applied when port is started */
1686         if (!eth_dev->data->dev_started)
1687                 return 0;
1688
1689         if (bp->vnic_info == NULL)
1690                 return 0;
1691
1692         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1693
1694         old_flags = vnic->flags;
1695         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1696         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1697         if (rc != 0)
1698                 vnic->flags = old_flags;
1699
1700         return rc;
1701 }
1702
1703 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1704 {
1705         struct bnxt *bp = eth_dev->data->dev_private;
1706         struct bnxt_vnic_info *vnic;
1707         uint32_t old_flags;
1708         int rc;
1709
1710         rc = is_bnxt_in_error(bp);
1711         if (rc)
1712                 return rc;
1713
1714         /* Filter settings will get applied when port is started */
1715         if (!eth_dev->data->dev_started)
1716                 return 0;
1717
1718         if (bp->vnic_info == NULL)
1719                 return 0;
1720
1721         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1722
1723         old_flags = vnic->flags;
1724         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1725         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1726         if (rc != 0)
1727                 vnic->flags = old_flags;
1728
1729         return rc;
1730 }
1731
1732 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1733 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1734 {
1735         if (qid >= bp->rx_nr_rings)
1736                 return NULL;
1737
1738         return bp->eth_dev->data->rx_queues[qid];
1739 }
1740
1741 /* Return rxq corresponding to a given rss table ring/group ID. */
1742 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1743 {
1744         struct bnxt_rx_queue *rxq;
1745         unsigned int i;
1746
1747         if (!BNXT_HAS_RING_GRPS(bp)) {
1748                 for (i = 0; i < bp->rx_nr_rings; i++) {
1749                         rxq = bp->eth_dev->data->rx_queues[i];
1750                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1751                                 return rxq->index;
1752                 }
1753         } else {
1754                 for (i = 0; i < bp->rx_nr_rings; i++) {
1755                         if (bp->grp_info[i].fw_grp_id == fwr)
1756                                 return i;
1757                 }
1758         }
1759
1760         return INVALID_HW_RING_ID;
1761 }
1762
1763 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1764                             struct rte_eth_rss_reta_entry64 *reta_conf,
1765                             uint16_t reta_size)
1766 {
1767         struct bnxt *bp = eth_dev->data->dev_private;
1768         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1769         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1770         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1771         uint16_t idx, sft;
1772         int i, rc;
1773
1774         rc = is_bnxt_in_error(bp);
1775         if (rc)
1776                 return rc;
1777
1778         if (!vnic->rss_table)
1779                 return -EINVAL;
1780
1781         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1782                 return -EINVAL;
1783
1784         if (reta_size != tbl_size) {
1785                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1786                         "(%d) must equal the size supported by the hardware "
1787                         "(%d)\n", reta_size, tbl_size);
1788                 return -EINVAL;
1789         }
1790
1791         for (i = 0; i < reta_size; i++) {
1792                 struct bnxt_rx_queue *rxq;
1793
1794                 idx = i / RTE_RETA_GROUP_SIZE;
1795                 sft = i % RTE_RETA_GROUP_SIZE;
1796
1797                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1798                         continue;
1799
1800                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1801                 if (!rxq) {
1802                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1803                         return -EINVAL;
1804                 }
1805
1806                 if (BNXT_CHIP_THOR(bp)) {
1807                         vnic->rss_table[i * 2] =
1808                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1809                         vnic->rss_table[i * 2 + 1] =
1810                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1811                 } else {
1812                         vnic->rss_table[i] =
1813                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1814                 }
1815         }
1816
1817         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1818         return 0;
1819 }
1820
1821 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1822                               struct rte_eth_rss_reta_entry64 *reta_conf,
1823                               uint16_t reta_size)
1824 {
1825         struct bnxt *bp = eth_dev->data->dev_private;
1826         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1827         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1828         uint16_t idx, sft, i;
1829         int rc;
1830
1831         rc = is_bnxt_in_error(bp);
1832         if (rc)
1833                 return rc;
1834
1835         /* Retrieve from the default VNIC */
1836         if (!vnic)
1837                 return -EINVAL;
1838         if (!vnic->rss_table)
1839                 return -EINVAL;
1840
1841         if (reta_size != tbl_size) {
1842                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1843                         "(%d) must equal the size supported by the hardware "
1844                         "(%d)\n", reta_size, tbl_size);
1845                 return -EINVAL;
1846         }
1847
1848         for (idx = 0, i = 0; i < reta_size; i++) {
1849                 idx = i / RTE_RETA_GROUP_SIZE;
1850                 sft = i % RTE_RETA_GROUP_SIZE;
1851
1852                 if (reta_conf[idx].mask & (1ULL << sft)) {
1853                         uint16_t qid;
1854
1855                         if (BNXT_CHIP_THOR(bp))
1856                                 qid = bnxt_rss_to_qid(bp,
1857                                                       vnic->rss_table[i * 2]);
1858                         else
1859                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1860
1861                         if (qid == INVALID_HW_RING_ID) {
1862                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1863                                 return -EINVAL;
1864                         }
1865                         reta_conf[idx].reta[sft] = qid;
1866                 }
1867         }
1868
1869         return 0;
1870 }
1871
1872 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1873                                    struct rte_eth_rss_conf *rss_conf)
1874 {
1875         struct bnxt *bp = eth_dev->data->dev_private;
1876         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1877         struct bnxt_vnic_info *vnic;
1878         int rc;
1879
1880         rc = is_bnxt_in_error(bp);
1881         if (rc)
1882                 return rc;
1883
1884         /*
1885          * If RSS enablement were different than dev_configure,
1886          * then return -EINVAL
1887          */
1888         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1889                 if (!rss_conf->rss_hf)
1890                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1891         } else {
1892                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1893                         return -EINVAL;
1894         }
1895
1896         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1897         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
1898                rss_conf,
1899                sizeof(*rss_conf));
1900
1901         /* Update the default RSS VNIC(s) */
1902         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1903         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1904         vnic->hash_mode =
1905                 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
1906                                             ETH_RSS_LEVEL(rss_conf->rss_hf));
1907
1908         /*
1909          * If hashkey is not specified, use the previously configured
1910          * hashkey
1911          */
1912         if (!rss_conf->rss_key)
1913                 goto rss_config;
1914
1915         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1916                 PMD_DRV_LOG(ERR,
1917                             "Invalid hashkey length, should be 16 bytes\n");
1918                 return -EINVAL;
1919         }
1920         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1921
1922 rss_config:
1923         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1924         return 0;
1925 }
1926
1927 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1928                                      struct rte_eth_rss_conf *rss_conf)
1929 {
1930         struct bnxt *bp = eth_dev->data->dev_private;
1931         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1932         int len, rc;
1933         uint32_t hash_types;
1934
1935         rc = is_bnxt_in_error(bp);
1936         if (rc)
1937                 return rc;
1938
1939         /* RSS configuration is the same for all VNICs */
1940         if (vnic && vnic->rss_hash_key) {
1941                 if (rss_conf->rss_key) {
1942                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1943                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1944                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1945                 }
1946
1947                 hash_types = vnic->hash_type;
1948                 rss_conf->rss_hf = 0;
1949                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1950                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1951                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1952                 }
1953                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1954                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1955                         hash_types &=
1956                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1957                 }
1958                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1959                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1960                         hash_types &=
1961                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1962                 }
1963                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1964                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1965                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1966                 }
1967                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1968                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1969                         hash_types &=
1970                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1971                 }
1972                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1973                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1974                         hash_types &=
1975                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1976                 }
1977
1978                 rss_conf->rss_hf |=
1979                         bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
1980
1981                 if (hash_types) {
1982                         PMD_DRV_LOG(ERR,
1983                                 "Unknown RSS config from firmware (%08x), RSS disabled",
1984                                 vnic->hash_type);
1985                         return -ENOTSUP;
1986                 }
1987         } else {
1988                 rss_conf->rss_hf = 0;
1989         }
1990         return 0;
1991 }
1992
1993 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1994                                struct rte_eth_fc_conf *fc_conf)
1995 {
1996         struct bnxt *bp = dev->data->dev_private;
1997         struct rte_eth_link link_info;
1998         int rc;
1999
2000         rc = is_bnxt_in_error(bp);
2001         if (rc)
2002                 return rc;
2003
2004         rc = bnxt_get_hwrm_link_config(bp, &link_info);
2005         if (rc)
2006                 return rc;
2007
2008         memset(fc_conf, 0, sizeof(*fc_conf));
2009         if (bp->link_info->auto_pause)
2010                 fc_conf->autoneg = 1;
2011         switch (bp->link_info->pause) {
2012         case 0:
2013                 fc_conf->mode = RTE_FC_NONE;
2014                 break;
2015         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2016                 fc_conf->mode = RTE_FC_TX_PAUSE;
2017                 break;
2018         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2019                 fc_conf->mode = RTE_FC_RX_PAUSE;
2020                 break;
2021         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2022                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2023                 fc_conf->mode = RTE_FC_FULL;
2024                 break;
2025         }
2026         return 0;
2027 }
2028
2029 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2030                                struct rte_eth_fc_conf *fc_conf)
2031 {
2032         struct bnxt *bp = dev->data->dev_private;
2033         int rc;
2034
2035         rc = is_bnxt_in_error(bp);
2036         if (rc)
2037                 return rc;
2038
2039         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2040                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2041                 return -ENOTSUP;
2042         }
2043
2044         switch (fc_conf->mode) {
2045         case RTE_FC_NONE:
2046                 bp->link_info->auto_pause = 0;
2047                 bp->link_info->force_pause = 0;
2048                 break;
2049         case RTE_FC_RX_PAUSE:
2050                 if (fc_conf->autoneg) {
2051                         bp->link_info->auto_pause =
2052                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2053                         bp->link_info->force_pause = 0;
2054                 } else {
2055                         bp->link_info->auto_pause = 0;
2056                         bp->link_info->force_pause =
2057                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2058                 }
2059                 break;
2060         case RTE_FC_TX_PAUSE:
2061                 if (fc_conf->autoneg) {
2062                         bp->link_info->auto_pause =
2063                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2064                         bp->link_info->force_pause = 0;
2065                 } else {
2066                         bp->link_info->auto_pause = 0;
2067                         bp->link_info->force_pause =
2068                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2069                 }
2070                 break;
2071         case RTE_FC_FULL:
2072                 if (fc_conf->autoneg) {
2073                         bp->link_info->auto_pause =
2074                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2075                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2076                         bp->link_info->force_pause = 0;
2077                 } else {
2078                         bp->link_info->auto_pause = 0;
2079                         bp->link_info->force_pause =
2080                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2081                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2082                 }
2083                 break;
2084         }
2085         return bnxt_set_hwrm_link_config(bp, true);
2086 }
2087
2088 /* Add UDP tunneling port */
2089 static int
2090 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2091                          struct rte_eth_udp_tunnel *udp_tunnel)
2092 {
2093         struct bnxt *bp = eth_dev->data->dev_private;
2094         uint16_t tunnel_type = 0;
2095         int rc = 0;
2096
2097         rc = is_bnxt_in_error(bp);
2098         if (rc)
2099                 return rc;
2100
2101         switch (udp_tunnel->prot_type) {
2102         case RTE_TUNNEL_TYPE_VXLAN:
2103                 if (bp->vxlan_port_cnt) {
2104                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2105                                 udp_tunnel->udp_port);
2106                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2107                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2108                                 return -ENOSPC;
2109                         }
2110                         bp->vxlan_port_cnt++;
2111                         return 0;
2112                 }
2113                 tunnel_type =
2114                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2115                 bp->vxlan_port_cnt++;
2116                 break;
2117         case RTE_TUNNEL_TYPE_GENEVE:
2118                 if (bp->geneve_port_cnt) {
2119                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2120                                 udp_tunnel->udp_port);
2121                         if (bp->geneve_port != udp_tunnel->udp_port) {
2122                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2123                                 return -ENOSPC;
2124                         }
2125                         bp->geneve_port_cnt++;
2126                         return 0;
2127                 }
2128                 tunnel_type =
2129                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2130                 bp->geneve_port_cnt++;
2131                 break;
2132         default:
2133                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2134                 return -ENOTSUP;
2135         }
2136         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2137                                              tunnel_type);
2138         return rc;
2139 }
2140
2141 static int
2142 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2143                          struct rte_eth_udp_tunnel *udp_tunnel)
2144 {
2145         struct bnxt *bp = eth_dev->data->dev_private;
2146         uint16_t tunnel_type = 0;
2147         uint16_t port = 0;
2148         int rc = 0;
2149
2150         rc = is_bnxt_in_error(bp);
2151         if (rc)
2152                 return rc;
2153
2154         switch (udp_tunnel->prot_type) {
2155         case RTE_TUNNEL_TYPE_VXLAN:
2156                 if (!bp->vxlan_port_cnt) {
2157                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2158                         return -EINVAL;
2159                 }
2160                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2161                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2162                                 udp_tunnel->udp_port, bp->vxlan_port);
2163                         return -EINVAL;
2164                 }
2165                 if (--bp->vxlan_port_cnt)
2166                         return 0;
2167
2168                 tunnel_type =
2169                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2170                 port = bp->vxlan_fw_dst_port_id;
2171                 break;
2172         case RTE_TUNNEL_TYPE_GENEVE:
2173                 if (!bp->geneve_port_cnt) {
2174                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2175                         return -EINVAL;
2176                 }
2177                 if (bp->geneve_port != udp_tunnel->udp_port) {
2178                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2179                                 udp_tunnel->udp_port, bp->geneve_port);
2180                         return -EINVAL;
2181                 }
2182                 if (--bp->geneve_port_cnt)
2183                         return 0;
2184
2185                 tunnel_type =
2186                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2187                 port = bp->geneve_fw_dst_port_id;
2188                 break;
2189         default:
2190                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2191                 return -ENOTSUP;
2192         }
2193
2194         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2195         return rc;
2196 }
2197
2198 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2199 {
2200         struct bnxt_filter_info *filter;
2201         struct bnxt_vnic_info *vnic;
2202         int rc = 0;
2203         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2204
2205         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2206         filter = STAILQ_FIRST(&vnic->filter);
2207         while (filter) {
2208                 /* Search for this matching MAC+VLAN filter */
2209                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2210                         /* Delete the filter */
2211                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2212                         if (rc)
2213                                 return rc;
2214                         STAILQ_REMOVE(&vnic->filter, filter,
2215                                       bnxt_filter_info, next);
2216                         bnxt_free_filter(bp, filter);
2217                         PMD_DRV_LOG(INFO,
2218                                     "Deleted vlan filter for %d\n",
2219                                     vlan_id);
2220                         return 0;
2221                 }
2222                 filter = STAILQ_NEXT(filter, next);
2223         }
2224         return -ENOENT;
2225 }
2226
2227 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2228 {
2229         struct bnxt_filter_info *filter;
2230         struct bnxt_vnic_info *vnic;
2231         int rc = 0;
2232         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2233                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2234         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2235
2236         /* Implementation notes on the use of VNIC in this command:
2237          *
2238          * By default, these filters belong to default vnic for the function.
2239          * Once these filters are set up, only destination VNIC can be modified.
2240          * If the destination VNIC is not specified in this command,
2241          * then the HWRM shall only create an l2 context id.
2242          */
2243
2244         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2245         filter = STAILQ_FIRST(&vnic->filter);
2246         /* Check if the VLAN has already been added */
2247         while (filter) {
2248                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2249                         return -EEXIST;
2250
2251                 filter = STAILQ_NEXT(filter, next);
2252         }
2253
2254         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2255          * command to create MAC+VLAN filter with the right flags, enables set.
2256          */
2257         filter = bnxt_alloc_filter(bp);
2258         if (!filter) {
2259                 PMD_DRV_LOG(ERR,
2260                             "MAC/VLAN filter alloc failed\n");
2261                 return -ENOMEM;
2262         }
2263         /* MAC + VLAN ID filter */
2264         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2265          * untagged packets are received
2266          *
2267          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2268          * packets and only the programmed vlan's packets are received
2269          */
2270         filter->l2_ivlan = vlan_id;
2271         filter->l2_ivlan_mask = 0x0FFF;
2272         filter->enables |= en;
2273         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2274
2275         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2276         if (rc) {
2277                 /* Free the newly allocated filter as we were
2278                  * not able to create the filter in hardware.
2279                  */
2280                 bnxt_free_filter(bp, filter);
2281                 return rc;
2282         }
2283
2284         filter->mac_index = 0;
2285         /* Add this new filter to the list */
2286         if (vlan_id == 0)
2287                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2288         else
2289                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2290
2291         PMD_DRV_LOG(INFO,
2292                     "Added Vlan filter for %d\n", vlan_id);
2293         return rc;
2294 }
2295
2296 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2297                 uint16_t vlan_id, int on)
2298 {
2299         struct bnxt *bp = eth_dev->data->dev_private;
2300         int rc;
2301
2302         rc = is_bnxt_in_error(bp);
2303         if (rc)
2304                 return rc;
2305
2306         if (!eth_dev->data->dev_started) {
2307                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2308                 return -EINVAL;
2309         }
2310
2311         /* These operations apply to ALL existing MAC/VLAN filters */
2312         if (on)
2313                 return bnxt_add_vlan_filter(bp, vlan_id);
2314         else
2315                 return bnxt_del_vlan_filter(bp, vlan_id);
2316 }
2317
2318 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2319                                     struct bnxt_vnic_info *vnic)
2320 {
2321         struct bnxt_filter_info *filter;
2322         int rc;
2323
2324         filter = STAILQ_FIRST(&vnic->filter);
2325         while (filter) {
2326                 if (filter->mac_index == 0 &&
2327                     !memcmp(filter->l2_addr, bp->mac_addr,
2328                             RTE_ETHER_ADDR_LEN)) {
2329                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2330                         if (!rc) {
2331                                 STAILQ_REMOVE(&vnic->filter, filter,
2332                                               bnxt_filter_info, next);
2333                                 bnxt_free_filter(bp, filter);
2334                         }
2335                         return rc;
2336                 }
2337                 filter = STAILQ_NEXT(filter, next);
2338         }
2339         return 0;
2340 }
2341
2342 static int
2343 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2344 {
2345         struct bnxt_vnic_info *vnic;
2346         unsigned int i;
2347         int rc;
2348
2349         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2350         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2351                 /* Remove any VLAN filters programmed */
2352                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2353                         bnxt_del_vlan_filter(bp, i);
2354
2355                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2356                 if (rc)
2357                         return rc;
2358         } else {
2359                 /* Default filter will allow packets that match the
2360                  * dest mac. So, it has to be deleted, otherwise, we
2361                  * will endup receiving vlan packets for which the
2362                  * filter is not programmed, when hw-vlan-filter
2363                  * configuration is ON
2364                  */
2365                 bnxt_del_dflt_mac_filter(bp, vnic);
2366                 /* This filter will allow only untagged packets */
2367                 bnxt_add_vlan_filter(bp, 0);
2368         }
2369         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2370                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2371
2372         return 0;
2373 }
2374
2375 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2376 {
2377         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2378         unsigned int i;
2379         int rc;
2380
2381         /* Destroy vnic filters and vnic */
2382         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2383             DEV_RX_OFFLOAD_VLAN_FILTER) {
2384                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2385                         bnxt_del_vlan_filter(bp, i);
2386         }
2387         bnxt_del_dflt_mac_filter(bp, vnic);
2388
2389         rc = bnxt_hwrm_vnic_free(bp, vnic);
2390         if (rc)
2391                 return rc;
2392
2393         rte_free(vnic->fw_grp_ids);
2394         vnic->fw_grp_ids = NULL;
2395
2396         vnic->rx_queue_cnt = 0;
2397
2398         return 0;
2399 }
2400
2401 static int
2402 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2403 {
2404         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2405         int rc;
2406
2407         /* Destroy, recreate and reconfigure the default vnic */
2408         rc = bnxt_free_one_vnic(bp, 0);
2409         if (rc)
2410                 return rc;
2411
2412         /* default vnic 0 */
2413         rc = bnxt_setup_one_vnic(bp, 0);
2414         if (rc)
2415                 return rc;
2416
2417         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2418             DEV_RX_OFFLOAD_VLAN_FILTER) {
2419                 rc = bnxt_add_vlan_filter(bp, 0);
2420                 if (rc)
2421                         return rc;
2422                 rc = bnxt_restore_vlan_filters(bp);
2423                 if (rc)
2424                         return rc;
2425         } else {
2426                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2427                 if (rc)
2428                         return rc;
2429         }
2430
2431         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2432         if (rc)
2433                 return rc;
2434
2435         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2436                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2437
2438         return rc;
2439 }
2440
2441 static int
2442 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2443 {
2444         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2445         struct bnxt *bp = dev->data->dev_private;
2446         int rc;
2447
2448         rc = is_bnxt_in_error(bp);
2449         if (rc)
2450                 return rc;
2451
2452         /* Filter settings will get applied when port is started */
2453         if (!dev->data->dev_started)
2454                 return 0;
2455
2456         if (mask & ETH_VLAN_FILTER_MASK) {
2457                 /* Enable or disable VLAN filtering */
2458                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2459                 if (rc)
2460                         return rc;
2461         }
2462
2463         if (mask & ETH_VLAN_STRIP_MASK) {
2464                 /* Enable or disable VLAN stripping */
2465                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2466                 if (rc)
2467                         return rc;
2468         }
2469
2470         if (mask & ETH_VLAN_EXTEND_MASK) {
2471                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2472                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2473                 else
2474                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2475         }
2476
2477         return 0;
2478 }
2479
2480 static int
2481 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2482                       uint16_t tpid)
2483 {
2484         struct bnxt *bp = dev->data->dev_private;
2485         int qinq = dev->data->dev_conf.rxmode.offloads &
2486                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2487
2488         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2489             vlan_type != ETH_VLAN_TYPE_OUTER) {
2490                 PMD_DRV_LOG(ERR,
2491                             "Unsupported vlan type.");
2492                 return -EINVAL;
2493         }
2494         if (!qinq) {
2495                 PMD_DRV_LOG(ERR,
2496                             "QinQ not enabled. Needs to be ON as we can "
2497                             "accelerate only outer vlan\n");
2498                 return -EINVAL;
2499         }
2500
2501         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2502                 switch (tpid) {
2503                 case RTE_ETHER_TYPE_QINQ:
2504                         bp->outer_tpid_bd =
2505                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2506                                 break;
2507                 case RTE_ETHER_TYPE_VLAN:
2508                         bp->outer_tpid_bd =
2509                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2510                                 break;
2511                 case RTE_ETHER_TYPE_QINQ1:
2512                         bp->outer_tpid_bd =
2513                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2514                                 break;
2515                 case RTE_ETHER_TYPE_QINQ2:
2516                         bp->outer_tpid_bd =
2517                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2518                                 break;
2519                 case RTE_ETHER_TYPE_QINQ3:
2520                         bp->outer_tpid_bd =
2521                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2522                                 break;
2523                 default:
2524                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2525                         return -EINVAL;
2526                 }
2527                 bp->outer_tpid_bd |= tpid;
2528                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2529         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2530                 PMD_DRV_LOG(ERR,
2531                             "Can accelerate only outer vlan in QinQ\n");
2532                 return -EINVAL;
2533         }
2534
2535         return 0;
2536 }
2537
2538 static int
2539 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2540                              struct rte_ether_addr *addr)
2541 {
2542         struct bnxt *bp = dev->data->dev_private;
2543         /* Default Filter is tied to VNIC 0 */
2544         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2545         int rc;
2546
2547         rc = is_bnxt_in_error(bp);
2548         if (rc)
2549                 return rc;
2550
2551         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2552                 return -EPERM;
2553
2554         if (rte_is_zero_ether_addr(addr))
2555                 return -EINVAL;
2556
2557         /* Filter settings will get applied when port is started */
2558         if (!dev->data->dev_started)
2559                 return 0;
2560
2561         /* Check if the requested MAC is already added */
2562         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2563                 return 0;
2564
2565         /* Destroy filter and re-create it */
2566         bnxt_del_dflt_mac_filter(bp, vnic);
2567
2568         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2569         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2570                 /* This filter will allow only untagged packets */
2571                 rc = bnxt_add_vlan_filter(bp, 0);
2572         } else {
2573                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2574         }
2575
2576         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2577         return rc;
2578 }
2579
2580 static int
2581 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2582                           struct rte_ether_addr *mc_addr_set,
2583                           uint32_t nb_mc_addr)
2584 {
2585         struct bnxt *bp = eth_dev->data->dev_private;
2586         char *mc_addr_list = (char *)mc_addr_set;
2587         struct bnxt_vnic_info *vnic;
2588         uint32_t off = 0, i = 0;
2589         int rc;
2590
2591         rc = is_bnxt_in_error(bp);
2592         if (rc)
2593                 return rc;
2594
2595         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2596
2597         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2598                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2599                 goto allmulti;
2600         }
2601
2602         /* TODO Check for Duplicate mcast addresses */
2603         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2604         for (i = 0; i < nb_mc_addr; i++) {
2605                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2606                         RTE_ETHER_ADDR_LEN);
2607                 off += RTE_ETHER_ADDR_LEN;
2608         }
2609
2610         vnic->mc_addr_cnt = i;
2611         if (vnic->mc_addr_cnt)
2612                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2613         else
2614                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2615
2616 allmulti:
2617         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2618 }
2619
2620 static int
2621 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2622 {
2623         struct bnxt *bp = dev->data->dev_private;
2624         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2625         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2626         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2627         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2628         int ret;
2629
2630         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2631                         fw_major, fw_minor, fw_updt, fw_rsvd);
2632
2633         ret += 1; /* add the size of '\0' */
2634         if (fw_size < (uint32_t)ret)
2635                 return ret;
2636         else
2637                 return 0;
2638 }
2639
2640 static void
2641 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2642         struct rte_eth_rxq_info *qinfo)
2643 {
2644         struct bnxt *bp = dev->data->dev_private;
2645         struct bnxt_rx_queue *rxq;
2646
2647         if (is_bnxt_in_error(bp))
2648                 return;
2649
2650         rxq = dev->data->rx_queues[queue_id];
2651
2652         qinfo->mp = rxq->mb_pool;
2653         qinfo->scattered_rx = dev->data->scattered_rx;
2654         qinfo->nb_desc = rxq->nb_rx_desc;
2655
2656         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2657         qinfo->conf.rx_drop_en = rxq->drop_en;
2658         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2659         qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2660 }
2661
2662 static void
2663 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2664         struct rte_eth_txq_info *qinfo)
2665 {
2666         struct bnxt *bp = dev->data->dev_private;
2667         struct bnxt_tx_queue *txq;
2668
2669         if (is_bnxt_in_error(bp))
2670                 return;
2671
2672         txq = dev->data->tx_queues[queue_id];
2673
2674         qinfo->nb_desc = txq->nb_tx_desc;
2675
2676         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2677         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2678         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2679
2680         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2681         qinfo->conf.tx_rs_thresh = 0;
2682         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2683         qinfo->conf.offloads = txq->offloads;
2684 }
2685
2686 static const struct {
2687         eth_rx_burst_t pkt_burst;
2688         const char *info;
2689 } bnxt_rx_burst_info[] = {
2690         {bnxt_recv_pkts,        "Scalar"},
2691 #if defined(RTE_ARCH_X86)
2692         {bnxt_recv_pkts_vec,    "Vector SSE"},
2693 #elif defined(RTE_ARCH_ARM64)
2694         {bnxt_recv_pkts_vec,    "Vector Neon"},
2695 #endif
2696 };
2697
2698 static int
2699 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2700                        struct rte_eth_burst_mode *mode)
2701 {
2702         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2703         size_t i;
2704
2705         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2706                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2707                         snprintf(mode->info, sizeof(mode->info), "%s",
2708                                  bnxt_rx_burst_info[i].info);
2709                         return 0;
2710                 }
2711         }
2712
2713         return -EINVAL;
2714 }
2715
2716 static const struct {
2717         eth_tx_burst_t pkt_burst;
2718         const char *info;
2719 } bnxt_tx_burst_info[] = {
2720         {bnxt_xmit_pkts,        "Scalar"},
2721 #if defined(RTE_ARCH_X86)
2722         {bnxt_xmit_pkts_vec,    "Vector SSE"},
2723 #elif defined(RTE_ARCH_ARM64)
2724         {bnxt_xmit_pkts_vec,    "Vector Neon"},
2725 #endif
2726 };
2727
2728 static int
2729 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2730                        struct rte_eth_burst_mode *mode)
2731 {
2732         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2733         size_t i;
2734
2735         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2736                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2737                         snprintf(mode->info, sizeof(mode->info), "%s",
2738                                  bnxt_tx_burst_info[i].info);
2739                         return 0;
2740                 }
2741         }
2742
2743         return -EINVAL;
2744 }
2745
2746 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2747 {
2748         struct bnxt *bp = eth_dev->data->dev_private;
2749         uint32_t new_pkt_size;
2750         uint32_t rc = 0;
2751         uint32_t i;
2752
2753         rc = is_bnxt_in_error(bp);
2754         if (rc)
2755                 return rc;
2756
2757         /* Exit if receive queues are not configured yet */
2758         if (!eth_dev->data->nb_rx_queues)
2759                 return rc;
2760
2761         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2762                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2763
2764         /*
2765          * Disallow any MTU change that would require scattered receive support
2766          * if it is not already enabled.
2767          */
2768         if (eth_dev->data->dev_started &&
2769             !eth_dev->data->scattered_rx &&
2770             (new_pkt_size >
2771              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2772                 PMD_DRV_LOG(ERR,
2773                             "MTU change would require scattered rx support. ");
2774                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2775                 return -EINVAL;
2776         }
2777
2778         if (new_mtu > RTE_ETHER_MTU) {
2779                 bp->flags |= BNXT_FLAG_JUMBO;
2780                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2781                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2782         } else {
2783                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2784                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2785                 bp->flags &= ~BNXT_FLAG_JUMBO;
2786         }
2787
2788         /* Is there a change in mtu setting? */
2789         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2790                 return rc;
2791
2792         for (i = 0; i < bp->nr_vnics; i++) {
2793                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2794                 uint16_t size = 0;
2795
2796                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2797                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2798                 if (rc)
2799                         break;
2800
2801                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2802                 size -= RTE_PKTMBUF_HEADROOM;
2803
2804                 if (size < new_mtu) {
2805                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2806                         if (rc)
2807                                 return rc;
2808                 }
2809         }
2810
2811         if (!rc)
2812                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2813
2814         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2815
2816         return rc;
2817 }
2818
2819 static int
2820 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2821 {
2822         struct bnxt *bp = dev->data->dev_private;
2823         uint16_t vlan = bp->vlan;
2824         int rc;
2825
2826         rc = is_bnxt_in_error(bp);
2827         if (rc)
2828                 return rc;
2829
2830         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2831                 PMD_DRV_LOG(ERR,
2832                         "PVID cannot be modified for this function\n");
2833                 return -ENOTSUP;
2834         }
2835         bp->vlan = on ? pvid : 0;
2836
2837         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2838         if (rc)
2839                 bp->vlan = vlan;
2840         return rc;
2841 }
2842
2843 static int
2844 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2845 {
2846         struct bnxt *bp = dev->data->dev_private;
2847         int rc;
2848
2849         rc = is_bnxt_in_error(bp);
2850         if (rc)
2851                 return rc;
2852
2853         return bnxt_hwrm_port_led_cfg(bp, true);
2854 }
2855
2856 static int
2857 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2858 {
2859         struct bnxt *bp = dev->data->dev_private;
2860         int rc;
2861
2862         rc = is_bnxt_in_error(bp);
2863         if (rc)
2864                 return rc;
2865
2866         return bnxt_hwrm_port_led_cfg(bp, false);
2867 }
2868
2869 static uint32_t
2870 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2871 {
2872         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2873         uint32_t desc = 0, raw_cons = 0, cons;
2874         struct bnxt_cp_ring_info *cpr;
2875         struct bnxt_rx_queue *rxq;
2876         struct rx_pkt_cmpl *rxcmp;
2877         int rc;
2878
2879         rc = is_bnxt_in_error(bp);
2880         if (rc)
2881                 return rc;
2882
2883         rxq = dev->data->rx_queues[rx_queue_id];
2884         cpr = rxq->cp_ring;
2885         raw_cons = cpr->cp_raw_cons;
2886
2887         while (1) {
2888                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2889                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2890                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2891
2892                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2893                         break;
2894                 } else {
2895                         raw_cons++;
2896                         desc++;
2897                 }
2898         }
2899
2900         return desc;
2901 }
2902
2903 static int
2904 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2905 {
2906         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2907         struct bnxt_rx_ring_info *rxr;
2908         struct bnxt_cp_ring_info *cpr;
2909         struct rte_mbuf *rx_buf;
2910         struct rx_pkt_cmpl *rxcmp;
2911         uint32_t cons, cp_cons;
2912         int rc;
2913
2914         if (!rxq)
2915                 return -EINVAL;
2916
2917         rc = is_bnxt_in_error(rxq->bp);
2918         if (rc)
2919                 return rc;
2920
2921         cpr = rxq->cp_ring;
2922         rxr = rxq->rx_ring;
2923
2924         if (offset >= rxq->nb_rx_desc)
2925                 return -EINVAL;
2926
2927         cons = RING_CMP(cpr->cp_ring_struct, offset);
2928         cp_cons = cpr->cp_raw_cons;
2929         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2930
2931         if (cons > cp_cons) {
2932                 if (CMPL_VALID(rxcmp, cpr->valid))
2933                         return RTE_ETH_RX_DESC_DONE;
2934         } else {
2935                 if (CMPL_VALID(rxcmp, !cpr->valid))
2936                         return RTE_ETH_RX_DESC_DONE;
2937         }
2938         rx_buf = rxr->rx_buf_ring[cons];
2939         if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf)
2940                 return RTE_ETH_RX_DESC_UNAVAIL;
2941
2942
2943         return RTE_ETH_RX_DESC_AVAIL;
2944 }
2945
2946 static int
2947 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2948 {
2949         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2950         struct bnxt_tx_ring_info *txr;
2951         struct bnxt_cp_ring_info *cpr;
2952         struct bnxt_sw_tx_bd *tx_buf;
2953         struct tx_pkt_cmpl *txcmp;
2954         uint32_t cons, cp_cons;
2955         int rc;
2956
2957         if (!txq)
2958                 return -EINVAL;
2959
2960         rc = is_bnxt_in_error(txq->bp);
2961         if (rc)
2962                 return rc;
2963
2964         cpr = txq->cp_ring;
2965         txr = txq->tx_ring;
2966
2967         if (offset >= txq->nb_tx_desc)
2968                 return -EINVAL;
2969
2970         cons = RING_CMP(cpr->cp_ring_struct, offset);
2971         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2972         cp_cons = cpr->cp_raw_cons;
2973
2974         if (cons > cp_cons) {
2975                 if (CMPL_VALID(txcmp, cpr->valid))
2976                         return RTE_ETH_TX_DESC_UNAVAIL;
2977         } else {
2978                 if (CMPL_VALID(txcmp, !cpr->valid))
2979                         return RTE_ETH_TX_DESC_UNAVAIL;
2980         }
2981         tx_buf = &txr->tx_buf_ring[cons];
2982         if (tx_buf->mbuf == NULL)
2983                 return RTE_ETH_TX_DESC_DONE;
2984
2985         return RTE_ETH_TX_DESC_FULL;
2986 }
2987
2988 static struct bnxt_filter_info *
2989 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2990                                 struct rte_eth_ethertype_filter *efilter,
2991                                 struct bnxt_vnic_info *vnic0,
2992                                 struct bnxt_vnic_info *vnic,
2993                                 int *ret)
2994 {
2995         struct bnxt_filter_info *mfilter = NULL;
2996         int match = 0;
2997         *ret = 0;
2998
2999         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
3000                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
3001                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
3002                         " ethertype filter.", efilter->ether_type);
3003                 *ret = -EINVAL;
3004                 goto exit;
3005         }
3006         if (efilter->queue >= bp->rx_nr_rings) {
3007                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
3008                 *ret = -EINVAL;
3009                 goto exit;
3010         }
3011
3012         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3013         vnic = &bp->vnic_info[efilter->queue];
3014         if (vnic == NULL) {
3015                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
3016                 *ret = -EINVAL;
3017                 goto exit;
3018         }
3019
3020         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3021                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
3022                         if ((!memcmp(efilter->mac_addr.addr_bytes,
3023                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
3024                              mfilter->flags ==
3025                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
3026                              mfilter->ethertype == efilter->ether_type)) {
3027                                 match = 1;
3028                                 break;
3029                         }
3030                 }
3031         } else {
3032                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
3033                         if ((!memcmp(efilter->mac_addr.addr_bytes,
3034                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
3035                              mfilter->ethertype == efilter->ether_type &&
3036                              mfilter->flags ==
3037                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
3038                                 match = 1;
3039                                 break;
3040                         }
3041         }
3042
3043         if (match)
3044                 *ret = -EEXIST;
3045
3046 exit:
3047         return mfilter;
3048 }
3049
3050 static int
3051 bnxt_ethertype_filter(struct rte_eth_dev *dev,
3052                         enum rte_filter_op filter_op,
3053                         void *arg)
3054 {
3055         struct bnxt *bp = dev->data->dev_private;
3056         struct rte_eth_ethertype_filter *efilter =
3057                         (struct rte_eth_ethertype_filter *)arg;
3058         struct bnxt_filter_info *bfilter, *filter1;
3059         struct bnxt_vnic_info *vnic, *vnic0;
3060         int ret;
3061
3062         if (filter_op == RTE_ETH_FILTER_NOP)
3063                 return 0;
3064
3065         if (arg == NULL) {
3066                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3067                             filter_op);
3068                 return -EINVAL;
3069         }
3070
3071         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3072         vnic = &bp->vnic_info[efilter->queue];
3073
3074         switch (filter_op) {
3075         case RTE_ETH_FILTER_ADD:
3076                 bnxt_match_and_validate_ether_filter(bp, efilter,
3077                                                         vnic0, vnic, &ret);
3078                 if (ret < 0)
3079                         return ret;
3080
3081                 bfilter = bnxt_get_unused_filter(bp);
3082                 if (bfilter == NULL) {
3083                         PMD_DRV_LOG(ERR,
3084                                 "Not enough resources for a new filter.\n");
3085                         return -ENOMEM;
3086                 }
3087                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3088                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
3089                        RTE_ETHER_ADDR_LEN);
3090                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
3091                        RTE_ETHER_ADDR_LEN);
3092                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3093                 bfilter->ethertype = efilter->ether_type;
3094                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3095
3096                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
3097                 if (filter1 == NULL) {
3098                         ret = -EINVAL;
3099                         goto cleanup;
3100                 }
3101                 bfilter->enables |=
3102                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3103                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3104
3105                 bfilter->dst_id = vnic->fw_vnic_id;
3106
3107                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3108                         bfilter->flags =
3109                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3110                 }
3111
3112                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3113                 if (ret)
3114                         goto cleanup;
3115                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3116                 break;
3117         case RTE_ETH_FILTER_DELETE:
3118                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
3119                                                         vnic0, vnic, &ret);
3120                 if (ret == -EEXIST) {
3121                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
3122
3123                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
3124                                       next);
3125                         bnxt_free_filter(bp, filter1);
3126                 } else if (ret == 0) {
3127                         PMD_DRV_LOG(ERR, "No matching filter found\n");
3128                 }
3129                 break;
3130         default:
3131                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3132                 ret = -EINVAL;
3133                 goto error;
3134         }
3135         return ret;
3136 cleanup:
3137         bnxt_free_filter(bp, bfilter);
3138 error:
3139         return ret;
3140 }
3141
3142 static inline int
3143 parse_ntuple_filter(struct bnxt *bp,
3144                     struct rte_eth_ntuple_filter *nfilter,
3145                     struct bnxt_filter_info *bfilter)
3146 {
3147         uint32_t en = 0;
3148
3149         if (nfilter->queue >= bp->rx_nr_rings) {
3150                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
3151                 return -EINVAL;
3152         }
3153
3154         switch (nfilter->dst_port_mask) {
3155         case UINT16_MAX:
3156                 bfilter->dst_port_mask = -1;
3157                 bfilter->dst_port = nfilter->dst_port;
3158                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
3159                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3160                 break;
3161         default:
3162                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3163                 return -EINVAL;
3164         }
3165
3166         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3167         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3168
3169         switch (nfilter->proto_mask) {
3170         case UINT8_MAX:
3171                 if (nfilter->proto == 17) /* IPPROTO_UDP */
3172                         bfilter->ip_protocol = 17;
3173                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
3174                         bfilter->ip_protocol = 6;
3175                 else
3176                         return -EINVAL;
3177                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3178                 break;
3179         default:
3180                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3181                 return -EINVAL;
3182         }
3183
3184         switch (nfilter->dst_ip_mask) {
3185         case UINT32_MAX:
3186                 bfilter->dst_ipaddr_mask[0] = -1;
3187                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
3188                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
3189                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3190                 break;
3191         default:
3192                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3193                 return -EINVAL;
3194         }
3195
3196         switch (nfilter->src_ip_mask) {
3197         case UINT32_MAX:
3198                 bfilter->src_ipaddr_mask[0] = -1;
3199                 bfilter->src_ipaddr[0] = nfilter->src_ip;
3200                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
3201                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3202                 break;
3203         default:
3204                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3205                 return -EINVAL;
3206         }
3207
3208         switch (nfilter->src_port_mask) {
3209         case UINT16_MAX:
3210                 bfilter->src_port_mask = -1;
3211                 bfilter->src_port = nfilter->src_port;
3212                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
3213                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3214                 break;
3215         default:
3216                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3217                 return -EINVAL;
3218         }
3219
3220         bfilter->enables = en;
3221         return 0;
3222 }
3223
3224 static struct bnxt_filter_info*
3225 bnxt_match_ntuple_filter(struct bnxt *bp,
3226                          struct bnxt_filter_info *bfilter,
3227                          struct bnxt_vnic_info **mvnic)
3228 {
3229         struct bnxt_filter_info *mfilter = NULL;
3230         int i;
3231
3232         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3233                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3234                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
3235                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
3236                             bfilter->src_ipaddr_mask[0] ==
3237                             mfilter->src_ipaddr_mask[0] &&
3238                             bfilter->src_port == mfilter->src_port &&
3239                             bfilter->src_port_mask == mfilter->src_port_mask &&
3240                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
3241                             bfilter->dst_ipaddr_mask[0] ==
3242                             mfilter->dst_ipaddr_mask[0] &&
3243                             bfilter->dst_port == mfilter->dst_port &&
3244                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
3245                             bfilter->flags == mfilter->flags &&
3246                             bfilter->enables == mfilter->enables) {
3247                                 if (mvnic)
3248                                         *mvnic = vnic;
3249                                 return mfilter;
3250                         }
3251                 }
3252         }
3253         return NULL;
3254 }
3255
3256 static int
3257 bnxt_cfg_ntuple_filter(struct bnxt *bp,
3258                        struct rte_eth_ntuple_filter *nfilter,
3259                        enum rte_filter_op filter_op)
3260 {
3261         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
3262         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
3263         int ret;
3264
3265         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
3266                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3267                 return -EINVAL;
3268         }
3269
3270         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
3271                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
3272                 return -EINVAL;
3273         }
3274
3275         bfilter = bnxt_get_unused_filter(bp);
3276         if (bfilter == NULL) {
3277                 PMD_DRV_LOG(ERR,
3278                         "Not enough resources for a new filter.\n");
3279                 return -ENOMEM;
3280         }
3281         ret = parse_ntuple_filter(bp, nfilter, bfilter);
3282         if (ret < 0)
3283                 goto free_filter;
3284
3285         vnic = &bp->vnic_info[nfilter->queue];
3286         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3287         filter1 = STAILQ_FIRST(&vnic0->filter);
3288         if (filter1 == NULL) {
3289                 ret = -EINVAL;
3290                 goto free_filter;
3291         }
3292
3293         bfilter->dst_id = vnic->fw_vnic_id;
3294         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3295         bfilter->enables |=
3296                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3297         bfilter->ethertype = 0x800;
3298         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3299
3300         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3301
3302         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3303             bfilter->dst_id == mfilter->dst_id) {
3304                 PMD_DRV_LOG(ERR, "filter exists.\n");
3305                 ret = -EEXIST;
3306                 goto free_filter;
3307         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3308                    bfilter->dst_id != mfilter->dst_id) {
3309                 mfilter->dst_id = vnic->fw_vnic_id;
3310                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3311                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3312                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3313                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3314                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3315                 goto free_filter;
3316         }
3317         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3318                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3319                 ret = -ENOENT;
3320                 goto free_filter;
3321         }
3322
3323         if (filter_op == RTE_ETH_FILTER_ADD) {
3324                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3325                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3326                 if (ret)
3327                         goto free_filter;
3328                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3329         } else {
3330                 if (mfilter == NULL) {
3331                         /* This should not happen. But for Coverity! */
3332                         ret = -ENOENT;
3333                         goto free_filter;
3334                 }
3335                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3336
3337                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3338                 bnxt_free_filter(bp, mfilter);
3339                 bnxt_free_filter(bp, bfilter);
3340         }
3341
3342         return 0;
3343 free_filter:
3344         bnxt_free_filter(bp, bfilter);
3345         return ret;
3346 }
3347
3348 static int
3349 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3350                         enum rte_filter_op filter_op,
3351                         void *arg)
3352 {
3353         struct bnxt *bp = dev->data->dev_private;
3354         int ret;
3355
3356         if (filter_op == RTE_ETH_FILTER_NOP)
3357                 return 0;
3358
3359         if (arg == NULL) {
3360                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3361                             filter_op);
3362                 return -EINVAL;
3363         }
3364
3365         switch (filter_op) {
3366         case RTE_ETH_FILTER_ADD:
3367                 ret = bnxt_cfg_ntuple_filter(bp,
3368                         (struct rte_eth_ntuple_filter *)arg,
3369                         filter_op);
3370                 break;
3371         case RTE_ETH_FILTER_DELETE:
3372                 ret = bnxt_cfg_ntuple_filter(bp,
3373                         (struct rte_eth_ntuple_filter *)arg,
3374                         filter_op);
3375                 break;
3376         default:
3377                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3378                 ret = -EINVAL;
3379                 break;
3380         }
3381         return ret;
3382 }
3383
3384 static int
3385 bnxt_parse_fdir_filter(struct bnxt *bp,
3386                        struct rte_eth_fdir_filter *fdir,
3387                        struct bnxt_filter_info *filter)
3388 {
3389         enum rte_fdir_mode fdir_mode =
3390                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3391         struct bnxt_vnic_info *vnic0, *vnic;
3392         struct bnxt_filter_info *filter1;
3393         uint32_t en = 0;
3394         int i;
3395
3396         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3397                 return -EINVAL;
3398
3399         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3400         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3401
3402         switch (fdir->input.flow_type) {
3403         case RTE_ETH_FLOW_IPV4:
3404         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3405                 /* FALLTHROUGH */
3406                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3407                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3408                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3409                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3410                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3411                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3412                 filter->ip_addr_type =
3413                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3414                 filter->src_ipaddr_mask[0] = 0xffffffff;
3415                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3416                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3417                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3418                 filter->ethertype = 0x800;
3419                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3420                 break;
3421         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3422                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3423                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3424                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3425                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3426                 filter->dst_port_mask = 0xffff;
3427                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3428                 filter->src_port_mask = 0xffff;
3429                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3430                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3431                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3432                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3433                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3434                 filter->ip_protocol = 6;
3435                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3436                 filter->ip_addr_type =
3437                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3438                 filter->src_ipaddr_mask[0] = 0xffffffff;
3439                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3440                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3441                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3442                 filter->ethertype = 0x800;
3443                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3444                 break;
3445         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3446                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3447                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3448                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3449                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3450                 filter->dst_port_mask = 0xffff;
3451                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3452                 filter->src_port_mask = 0xffff;
3453                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3454                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3455                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3456                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3457                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3458                 filter->ip_protocol = 17;
3459                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3460                 filter->ip_addr_type =
3461                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3462                 filter->src_ipaddr_mask[0] = 0xffffffff;
3463                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3464                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3465                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3466                 filter->ethertype = 0x800;
3467                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3468                 break;
3469         case RTE_ETH_FLOW_IPV6:
3470         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3471                 /* FALLTHROUGH */
3472                 filter->ip_addr_type =
3473                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3474                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3475                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3476                 rte_memcpy(filter->src_ipaddr,
3477                            fdir->input.flow.ipv6_flow.src_ip, 16);
3478                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3479                 rte_memcpy(filter->dst_ipaddr,
3480                            fdir->input.flow.ipv6_flow.dst_ip, 16);
3481                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3482                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3483                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3484                 memset(filter->src_ipaddr_mask, 0xff, 16);
3485                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3486                 filter->ethertype = 0x86dd;
3487                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3488                 break;
3489         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3490                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3491                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3492                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3493                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3494                 filter->dst_port_mask = 0xffff;
3495                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3496                 filter->src_port_mask = 0xffff;
3497                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3498                 filter->ip_addr_type =
3499                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3500                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3501                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3502                 rte_memcpy(filter->src_ipaddr,
3503                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3504                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3505                 rte_memcpy(filter->dst_ipaddr,
3506                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3507                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3508                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3509                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3510                 memset(filter->src_ipaddr_mask, 0xff, 16);
3511                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3512                 filter->ethertype = 0x86dd;
3513                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3514                 break;
3515         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3516                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3517                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3518                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3519                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3520                 filter->dst_port_mask = 0xffff;
3521                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3522                 filter->src_port_mask = 0xffff;
3523                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3524                 filter->ip_addr_type =
3525                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3526                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3527                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3528                 rte_memcpy(filter->src_ipaddr,
3529                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3530                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3531                 rte_memcpy(filter->dst_ipaddr,
3532                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3533                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3534                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3535                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3536                 memset(filter->src_ipaddr_mask, 0xff, 16);
3537                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3538                 filter->ethertype = 0x86dd;
3539                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3540                 break;
3541         case RTE_ETH_FLOW_L2_PAYLOAD:
3542                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3543                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3544                 break;
3545         case RTE_ETH_FLOW_VXLAN:
3546                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3547                         return -EINVAL;
3548                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3549                 filter->tunnel_type =
3550                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3551                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3552                 break;
3553         case RTE_ETH_FLOW_NVGRE:
3554                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3555                         return -EINVAL;
3556                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3557                 filter->tunnel_type =
3558                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3559                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3560                 break;
3561         case RTE_ETH_FLOW_UNKNOWN:
3562         case RTE_ETH_FLOW_RAW:
3563         case RTE_ETH_FLOW_FRAG_IPV4:
3564         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3565         case RTE_ETH_FLOW_FRAG_IPV6:
3566         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3567         case RTE_ETH_FLOW_IPV6_EX:
3568         case RTE_ETH_FLOW_IPV6_TCP_EX:
3569         case RTE_ETH_FLOW_IPV6_UDP_EX:
3570         case RTE_ETH_FLOW_GENEVE:
3571                 /* FALLTHROUGH */
3572         default:
3573                 return -EINVAL;
3574         }
3575
3576         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3577         vnic = &bp->vnic_info[fdir->action.rx_queue];
3578         if (vnic == NULL) {
3579                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3580                 return -EINVAL;
3581         }
3582
3583         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3584                 rte_memcpy(filter->dst_macaddr,
3585                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3586                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3587         }
3588
3589         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3590                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3591                 filter1 = STAILQ_FIRST(&vnic0->filter);
3592                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3593         } else {
3594                 filter->dst_id = vnic->fw_vnic_id;
3595                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3596                         if (filter->dst_macaddr[i] == 0x00)
3597                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3598                         else
3599                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3600         }
3601
3602         if (filter1 == NULL)
3603                 return -EINVAL;
3604
3605         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3606         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3607
3608         filter->enables = en;
3609
3610         return 0;
3611 }
3612
3613 static struct bnxt_filter_info *
3614 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3615                 struct bnxt_vnic_info **mvnic)
3616 {
3617         struct bnxt_filter_info *mf = NULL;
3618         int i;
3619
3620         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3621                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3622
3623                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3624                         if (mf->filter_type == nf->filter_type &&
3625                             mf->flags == nf->flags &&
3626                             mf->src_port == nf->src_port &&
3627                             mf->src_port_mask == nf->src_port_mask &&
3628                             mf->dst_port == nf->dst_port &&
3629                             mf->dst_port_mask == nf->dst_port_mask &&
3630                             mf->ip_protocol == nf->ip_protocol &&
3631                             mf->ip_addr_type == nf->ip_addr_type &&
3632                             mf->ethertype == nf->ethertype &&
3633                             mf->vni == nf->vni &&
3634                             mf->tunnel_type == nf->tunnel_type &&
3635                             mf->l2_ovlan == nf->l2_ovlan &&
3636                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3637                             mf->l2_ivlan == nf->l2_ivlan &&
3638                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3639                             !memcmp(mf->l2_addr, nf->l2_addr,
3640                                     RTE_ETHER_ADDR_LEN) &&
3641                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3642                                     RTE_ETHER_ADDR_LEN) &&
3643                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3644                                     RTE_ETHER_ADDR_LEN) &&
3645                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3646                                     RTE_ETHER_ADDR_LEN) &&
3647                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3648                                     sizeof(nf->src_ipaddr)) &&
3649                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3650                                     sizeof(nf->src_ipaddr_mask)) &&
3651                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3652                                     sizeof(nf->dst_ipaddr)) &&
3653                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3654                                     sizeof(nf->dst_ipaddr_mask))) {
3655                                 if (mvnic)
3656                                         *mvnic = vnic;
3657                                 return mf;
3658                         }
3659                 }
3660         }
3661         return NULL;
3662 }
3663
3664 static int
3665 bnxt_fdir_filter(struct rte_eth_dev *dev,
3666                  enum rte_filter_op filter_op,
3667                  void *arg)
3668 {
3669         struct bnxt *bp = dev->data->dev_private;
3670         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3671         struct bnxt_filter_info *filter, *match;
3672         struct bnxt_vnic_info *vnic, *mvnic;
3673         int ret = 0, i;
3674
3675         if (filter_op == RTE_ETH_FILTER_NOP)
3676                 return 0;
3677
3678         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3679                 return -EINVAL;
3680
3681         switch (filter_op) {
3682         case RTE_ETH_FILTER_ADD:
3683         case RTE_ETH_FILTER_DELETE:
3684                 /* FALLTHROUGH */
3685                 filter = bnxt_get_unused_filter(bp);
3686                 if (filter == NULL) {
3687                         PMD_DRV_LOG(ERR,
3688                                 "Not enough resources for a new flow.\n");
3689                         return -ENOMEM;
3690                 }
3691
3692                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3693                 if (ret != 0)
3694                         goto free_filter;
3695                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3696
3697                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3698                         vnic = &bp->vnic_info[0];
3699                 else
3700                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3701
3702                 match = bnxt_match_fdir(bp, filter, &mvnic);
3703                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3704                         if (match->dst_id == vnic->fw_vnic_id) {
3705                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3706                                 ret = -EEXIST;
3707                                 goto free_filter;
3708                         } else {
3709                                 match->dst_id = vnic->fw_vnic_id;
3710                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3711                                                                   match->dst_id,
3712                                                                   match);
3713                                 STAILQ_REMOVE(&mvnic->filter, match,
3714                                               bnxt_filter_info, next);
3715                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3716                                 PMD_DRV_LOG(ERR,
3717                                         "Filter with matching pattern exist\n");
3718                                 PMD_DRV_LOG(ERR,
3719                                         "Updated it to new destination q\n");
3720                                 goto free_filter;
3721                         }
3722                 }
3723                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3724                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3725                         ret = -ENOENT;
3726                         goto free_filter;
3727                 }
3728
3729                 if (filter_op == RTE_ETH_FILTER_ADD) {
3730                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3731                                                           filter->dst_id,
3732                                                           filter);
3733                         if (ret)
3734                                 goto free_filter;
3735                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3736                 } else {
3737                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3738                         STAILQ_REMOVE(&vnic->filter, match,
3739                                       bnxt_filter_info, next);
3740                         bnxt_free_filter(bp, match);
3741                         bnxt_free_filter(bp, filter);
3742                 }
3743                 break;
3744         case RTE_ETH_FILTER_FLUSH:
3745                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3746                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3747
3748                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3749                                 if (filter->filter_type ==
3750                                     HWRM_CFA_NTUPLE_FILTER) {
3751                                         ret =
3752                                         bnxt_hwrm_clear_ntuple_filter(bp,
3753                                                                       filter);
3754                                         STAILQ_REMOVE(&vnic->filter, filter,
3755                                                       bnxt_filter_info, next);
3756                                 }
3757                         }
3758                 }
3759                 return ret;
3760         case RTE_ETH_FILTER_UPDATE:
3761         case RTE_ETH_FILTER_STATS:
3762         case RTE_ETH_FILTER_INFO:
3763                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3764                 break;
3765         default:
3766                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3767                 ret = -EINVAL;
3768                 break;
3769         }
3770         return ret;
3771
3772 free_filter:
3773         bnxt_free_filter(bp, filter);
3774         return ret;
3775 }
3776
3777 int
3778 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3779                     enum rte_filter_type filter_type,
3780                     enum rte_filter_op filter_op, void *arg)
3781 {
3782         struct bnxt *bp = dev->data->dev_private;
3783         int ret = 0;
3784
3785         if (!bp)
3786                 return -EIO;
3787
3788         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3789                 struct bnxt_representor *vfr = dev->data->dev_private;
3790                 bp = vfr->parent_dev->data->dev_private;
3791                 /* parent is deleted while children are still valid */
3792                 if (!bp) {
3793                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n",
3794                                     dev->data->port_id,
3795                                     filter_type,
3796                                     filter_op);
3797                         return -EIO;
3798                 }
3799         }
3800
3801         ret = is_bnxt_in_error(bp);
3802         if (ret)
3803                 return ret;
3804
3805         switch (filter_type) {
3806         case RTE_ETH_FILTER_TUNNEL:
3807                 PMD_DRV_LOG(ERR,
3808                         "filter type: %d: To be implemented\n", filter_type);
3809                 break;
3810         case RTE_ETH_FILTER_FDIR:
3811                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3812                 break;
3813         case RTE_ETH_FILTER_NTUPLE:
3814                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3815                 break;
3816         case RTE_ETH_FILTER_ETHERTYPE:
3817                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3818                 break;
3819         case RTE_ETH_FILTER_GENERIC:
3820                 if (filter_op != RTE_ETH_FILTER_GET)
3821                         return -EINVAL;
3822                 if (BNXT_TRUFLOW_EN(bp))
3823                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3824                 else
3825                         *(const void **)arg = &bnxt_flow_ops;
3826                 break;
3827         default:
3828                 PMD_DRV_LOG(ERR,
3829                         "Filter type (%d) not supported", filter_type);
3830                 ret = -EINVAL;
3831                 break;
3832         }
3833         return ret;
3834 }
3835
3836 static const uint32_t *
3837 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3838 {
3839         static const uint32_t ptypes[] = {
3840                 RTE_PTYPE_L2_ETHER_VLAN,
3841                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3842                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3843                 RTE_PTYPE_L4_ICMP,
3844                 RTE_PTYPE_L4_TCP,
3845                 RTE_PTYPE_L4_UDP,
3846                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3847                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3848                 RTE_PTYPE_INNER_L4_ICMP,
3849                 RTE_PTYPE_INNER_L4_TCP,
3850                 RTE_PTYPE_INNER_L4_UDP,
3851                 RTE_PTYPE_UNKNOWN
3852         };
3853
3854         if (!dev->rx_pkt_burst)
3855                 return NULL;
3856
3857         return ptypes;
3858 }
3859
3860 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3861                          int reg_win)
3862 {
3863         uint32_t reg_base = *reg_arr & 0xfffff000;
3864         uint32_t win_off;
3865         int i;
3866
3867         for (i = 0; i < count; i++) {
3868                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3869                         return -ERANGE;
3870         }
3871         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3872         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3873         return 0;
3874 }
3875
3876 static int bnxt_map_ptp_regs(struct bnxt *bp)
3877 {
3878         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3879         uint32_t *reg_arr;
3880         int rc, i;
3881
3882         reg_arr = ptp->rx_regs;
3883         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3884         if (rc)
3885                 return rc;
3886
3887         reg_arr = ptp->tx_regs;
3888         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3889         if (rc)
3890                 return rc;
3891
3892         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3893                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3894
3895         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3896                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3897
3898         return 0;
3899 }
3900
3901 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3902 {
3903         rte_write32(0, (uint8_t *)bp->bar0 +
3904                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3905         rte_write32(0, (uint8_t *)bp->bar0 +
3906                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3907 }
3908
3909 static uint64_t bnxt_cc_read(struct bnxt *bp)
3910 {
3911         uint64_t ns;
3912
3913         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3914                               BNXT_GRCPF_REG_SYNC_TIME));
3915         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3916                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3917         return ns;
3918 }
3919
3920 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3921 {
3922         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3923         uint32_t fifo;
3924
3925         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3926                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3927         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3928                 return -EAGAIN;
3929
3930         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3931                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3932         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3933                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3934         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3935                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3936
3937         return 0;
3938 }
3939
3940 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3941 {
3942         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3943         struct bnxt_pf_info *pf = bp->pf;
3944         uint16_t port_id;
3945         uint32_t fifo;
3946
3947         if (!ptp)
3948                 return -ENODEV;
3949
3950         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3951                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3952         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3953                 return -EAGAIN;
3954
3955         port_id = pf->port_id;
3956         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3957                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3958
3959         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3960                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3961         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3962 /*              bnxt_clr_rx_ts(bp);       TBD  */
3963                 return -EBUSY;
3964         }
3965
3966         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3967                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3968         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3969                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3970
3971         return 0;
3972 }
3973
3974 static int
3975 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3976 {
3977         uint64_t ns;
3978         struct bnxt *bp = dev->data->dev_private;
3979         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3980
3981         if (!ptp)
3982                 return 0;
3983
3984         ns = rte_timespec_to_ns(ts);
3985         /* Set the timecounters to a new value. */
3986         ptp->tc.nsec = ns;
3987
3988         return 0;
3989 }
3990
3991 static int
3992 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3993 {
3994         struct bnxt *bp = dev->data->dev_private;
3995         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3996         uint64_t ns, systime_cycles = 0;
3997         int rc = 0;
3998
3999         if (!ptp)
4000                 return 0;
4001
4002         if (BNXT_CHIP_THOR(bp))
4003                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
4004                                              &systime_cycles);
4005         else
4006                 systime_cycles = bnxt_cc_read(bp);
4007
4008         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
4009         *ts = rte_ns_to_timespec(ns);
4010
4011         return rc;
4012 }
4013 static int
4014 bnxt_timesync_enable(struct rte_eth_dev *dev)
4015 {
4016         struct bnxt *bp = dev->data->dev_private;
4017         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4018         uint32_t shift = 0;
4019         int rc;
4020
4021         if (!ptp)
4022                 return 0;
4023
4024         ptp->rx_filter = 1;
4025         ptp->tx_tstamp_en = 1;
4026         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
4027
4028         rc = bnxt_hwrm_ptp_cfg(bp);
4029         if (rc)
4030                 return rc;
4031
4032         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
4033         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4034         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4035
4036         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4037         ptp->tc.cc_shift = shift;
4038         ptp->tc.nsec_mask = (1ULL << shift) - 1;
4039
4040         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4041         ptp->rx_tstamp_tc.cc_shift = shift;
4042         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4043
4044         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4045         ptp->tx_tstamp_tc.cc_shift = shift;
4046         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4047
4048         if (!BNXT_CHIP_THOR(bp))
4049                 bnxt_map_ptp_regs(bp);
4050
4051         return 0;
4052 }
4053
4054 static int
4055 bnxt_timesync_disable(struct rte_eth_dev *dev)
4056 {
4057         struct bnxt *bp = dev->data->dev_private;
4058         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4059
4060         if (!ptp)
4061                 return 0;
4062
4063         ptp->rx_filter = 0;
4064         ptp->tx_tstamp_en = 0;
4065         ptp->rxctl = 0;
4066
4067         bnxt_hwrm_ptp_cfg(bp);
4068
4069         if (!BNXT_CHIP_THOR(bp))
4070                 bnxt_unmap_ptp_regs(bp);
4071
4072         return 0;
4073 }
4074
4075 static int
4076 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4077                                  struct timespec *timestamp,
4078                                  uint32_t flags __rte_unused)
4079 {
4080         struct bnxt *bp = dev->data->dev_private;
4081         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4082         uint64_t rx_tstamp_cycles = 0;
4083         uint64_t ns;
4084
4085         if (!ptp)
4086                 return 0;
4087
4088         if (BNXT_CHIP_THOR(bp))
4089                 rx_tstamp_cycles = ptp->rx_timestamp;
4090         else
4091                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
4092
4093         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
4094         *timestamp = rte_ns_to_timespec(ns);
4095         return  0;
4096 }
4097
4098 static int
4099 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4100                                  struct timespec *timestamp)
4101 {
4102         struct bnxt *bp = dev->data->dev_private;
4103         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4104         uint64_t tx_tstamp_cycles = 0;
4105         uint64_t ns;
4106         int rc = 0;
4107
4108         if (!ptp)
4109                 return 0;
4110
4111         if (BNXT_CHIP_THOR(bp))
4112                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
4113                                              &tx_tstamp_cycles);
4114         else
4115                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
4116
4117         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
4118         *timestamp = rte_ns_to_timespec(ns);
4119
4120         return rc;
4121 }
4122
4123 static int
4124 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4125 {
4126         struct bnxt *bp = dev->data->dev_private;
4127         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4128
4129         if (!ptp)
4130                 return 0;
4131
4132         ptp->tc.nsec += delta;
4133
4134         return 0;
4135 }
4136
4137 static int
4138 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
4139 {
4140         struct bnxt *bp = dev->data->dev_private;
4141         int rc;
4142         uint32_t dir_entries;
4143         uint32_t entry_length;
4144
4145         rc = is_bnxt_in_error(bp);
4146         if (rc)
4147                 return rc;
4148
4149         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
4150                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4151                     bp->pdev->addr.devid, bp->pdev->addr.function);
4152
4153         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4154         if (rc != 0)
4155                 return rc;
4156
4157         return dir_entries * entry_length;
4158 }
4159
4160 static int
4161 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
4162                 struct rte_dev_eeprom_info *in_eeprom)
4163 {
4164         struct bnxt *bp = dev->data->dev_private;
4165         uint32_t index;
4166         uint32_t offset;
4167         int rc;
4168
4169         rc = is_bnxt_in_error(bp);
4170         if (rc)
4171                 return rc;
4172
4173         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4174                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4175                     bp->pdev->addr.devid, bp->pdev->addr.function,
4176                     in_eeprom->offset, in_eeprom->length);
4177
4178         if (in_eeprom->offset == 0) /* special offset value to get directory */
4179                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
4180                                                 in_eeprom->data);
4181
4182         index = in_eeprom->offset >> 24;
4183         offset = in_eeprom->offset & 0xffffff;
4184
4185         if (index != 0)
4186                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
4187                                            in_eeprom->length, in_eeprom->data);
4188
4189         return 0;
4190 }
4191
4192 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
4193 {
4194         switch (dir_type) {
4195         case BNX_DIR_TYPE_CHIMP_PATCH:
4196         case BNX_DIR_TYPE_BOOTCODE:
4197         case BNX_DIR_TYPE_BOOTCODE_2:
4198         case BNX_DIR_TYPE_APE_FW:
4199         case BNX_DIR_TYPE_APE_PATCH:
4200         case BNX_DIR_TYPE_KONG_FW:
4201         case BNX_DIR_TYPE_KONG_PATCH:
4202         case BNX_DIR_TYPE_BONO_FW:
4203         case BNX_DIR_TYPE_BONO_PATCH:
4204                 /* FALLTHROUGH */
4205                 return true;
4206         }
4207
4208         return false;
4209 }
4210
4211 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
4212 {
4213         switch (dir_type) {
4214         case BNX_DIR_TYPE_AVS:
4215         case BNX_DIR_TYPE_EXP_ROM_MBA:
4216         case BNX_DIR_TYPE_PCIE:
4217         case BNX_DIR_TYPE_TSCF_UCODE:
4218         case BNX_DIR_TYPE_EXT_PHY:
4219         case BNX_DIR_TYPE_CCM:
4220         case BNX_DIR_TYPE_ISCSI_BOOT:
4221         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
4222         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
4223                 /* FALLTHROUGH */
4224                 return true;
4225         }
4226
4227         return false;
4228 }
4229
4230 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
4231 {
4232         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
4233                 bnxt_dir_type_is_other_exec_format(dir_type);
4234 }
4235
4236 static int
4237 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
4238                 struct rte_dev_eeprom_info *in_eeprom)
4239 {
4240         struct bnxt *bp = dev->data->dev_private;
4241         uint8_t index, dir_op;
4242         uint16_t type, ext, ordinal, attr;
4243         int rc;
4244
4245         rc = is_bnxt_in_error(bp);
4246         if (rc)
4247                 return rc;
4248
4249         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4250                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4251                     bp->pdev->addr.devid, bp->pdev->addr.function,
4252                     in_eeprom->offset, in_eeprom->length);
4253
4254         if (!BNXT_PF(bp)) {
4255                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
4256                 return -EINVAL;
4257         }
4258
4259         type = in_eeprom->magic >> 16;
4260
4261         if (type == 0xffff) { /* special value for directory operations */
4262                 index = in_eeprom->magic & 0xff;
4263                 dir_op = in_eeprom->magic >> 8;
4264                 if (index == 0)
4265                         return -EINVAL;
4266                 switch (dir_op) {
4267                 case 0x0e: /* erase */
4268                         if (in_eeprom->offset != ~in_eeprom->magic)
4269                                 return -EINVAL;
4270                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
4271                 default:
4272                         return -EINVAL;
4273                 }
4274         }
4275
4276         /* Create or re-write an NVM item: */
4277         if (bnxt_dir_type_is_executable(type) == true)
4278                 return -EOPNOTSUPP;
4279         ext = in_eeprom->magic & 0xffff;
4280         ordinal = in_eeprom->offset >> 16;
4281         attr = in_eeprom->offset & 0xffff;
4282
4283         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
4284                                      in_eeprom->data, in_eeprom->length);
4285 }
4286
4287 /*
4288  * Initialization
4289  */
4290
4291 static const struct eth_dev_ops bnxt_dev_ops = {
4292         .dev_infos_get = bnxt_dev_info_get_op,
4293         .dev_close = bnxt_dev_close_op,
4294         .dev_configure = bnxt_dev_configure_op,
4295         .dev_start = bnxt_dev_start_op,
4296         .dev_stop = bnxt_dev_stop_op,
4297         .dev_set_link_up = bnxt_dev_set_link_up_op,
4298         .dev_set_link_down = bnxt_dev_set_link_down_op,
4299         .stats_get = bnxt_stats_get_op,
4300         .stats_reset = bnxt_stats_reset_op,
4301         .rx_queue_setup = bnxt_rx_queue_setup_op,
4302         .rx_queue_release = bnxt_rx_queue_release_op,
4303         .tx_queue_setup = bnxt_tx_queue_setup_op,
4304         .tx_queue_release = bnxt_tx_queue_release_op,
4305         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4306         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4307         .reta_update = bnxt_reta_update_op,
4308         .reta_query = bnxt_reta_query_op,
4309         .rss_hash_update = bnxt_rss_hash_update_op,
4310         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4311         .link_update = bnxt_link_update_op,
4312         .promiscuous_enable = bnxt_promiscuous_enable_op,
4313         .promiscuous_disable = bnxt_promiscuous_disable_op,
4314         .allmulticast_enable = bnxt_allmulticast_enable_op,
4315         .allmulticast_disable = bnxt_allmulticast_disable_op,
4316         .mac_addr_add = bnxt_mac_addr_add_op,
4317         .mac_addr_remove = bnxt_mac_addr_remove_op,
4318         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4319         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4320         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4321         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4322         .vlan_filter_set = bnxt_vlan_filter_set_op,
4323         .vlan_offload_set = bnxt_vlan_offload_set_op,
4324         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4325         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4326         .mtu_set = bnxt_mtu_set_op,
4327         .mac_addr_set = bnxt_set_default_mac_addr_op,
4328         .xstats_get = bnxt_dev_xstats_get_op,
4329         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4330         .xstats_reset = bnxt_dev_xstats_reset_op,
4331         .fw_version_get = bnxt_fw_version_get,
4332         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4333         .rxq_info_get = bnxt_rxq_info_get_op,
4334         .txq_info_get = bnxt_txq_info_get_op,
4335         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4336         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4337         .dev_led_on = bnxt_dev_led_on_op,
4338         .dev_led_off = bnxt_dev_led_off_op,
4339         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4340         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4341         .rx_queue_start = bnxt_rx_queue_start,
4342         .rx_queue_stop = bnxt_rx_queue_stop,
4343         .tx_queue_start = bnxt_tx_queue_start,
4344         .tx_queue_stop = bnxt_tx_queue_stop,
4345         .filter_ctrl = bnxt_filter_ctrl_op,
4346         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4347         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4348         .get_eeprom           = bnxt_get_eeprom_op,
4349         .set_eeprom           = bnxt_set_eeprom_op,
4350         .timesync_enable      = bnxt_timesync_enable,
4351         .timesync_disable     = bnxt_timesync_disable,
4352         .timesync_read_time   = bnxt_timesync_read_time,
4353         .timesync_write_time   = bnxt_timesync_write_time,
4354         .timesync_adjust_time = bnxt_timesync_adjust_time,
4355         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4356         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4357 };
4358
4359 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4360 {
4361         uint32_t offset;
4362
4363         /* Only pre-map the reset GRC registers using window 3 */
4364         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4365                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4366
4367         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4368
4369         return offset;
4370 }
4371
4372 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4373 {
4374         struct bnxt_error_recovery_info *info = bp->recovery_info;
4375         uint32_t reg_base = 0xffffffff;
4376         int i;
4377
4378         /* Only pre-map the monitoring GRC registers using window 2 */
4379         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4380                 uint32_t reg = info->status_regs[i];
4381
4382                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4383                         continue;
4384
4385                 if (reg_base == 0xffffffff)
4386                         reg_base = reg & 0xfffff000;
4387                 if ((reg & 0xfffff000) != reg_base)
4388                         return -ERANGE;
4389
4390                 /* Use mask 0xffc as the Lower 2 bits indicates
4391                  * address space location
4392                  */
4393                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4394                                                 (reg & 0xffc);
4395         }
4396
4397         if (reg_base == 0xffffffff)
4398                 return 0;
4399
4400         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4401                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4402
4403         return 0;
4404 }
4405
4406 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4407 {
4408         struct bnxt_error_recovery_info *info = bp->recovery_info;
4409         uint32_t delay = info->delay_after_reset[index];
4410         uint32_t val = info->reset_reg_val[index];
4411         uint32_t reg = info->reset_reg[index];
4412         uint32_t type, offset;
4413
4414         type = BNXT_FW_STATUS_REG_TYPE(reg);
4415         offset = BNXT_FW_STATUS_REG_OFF(reg);
4416
4417         switch (type) {
4418         case BNXT_FW_STATUS_REG_TYPE_CFG:
4419                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4420                 break;
4421         case BNXT_FW_STATUS_REG_TYPE_GRC:
4422                 offset = bnxt_map_reset_regs(bp, offset);
4423                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4424                 break;
4425         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4426                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4427                 break;
4428         }
4429         /* wait on a specific interval of time until core reset is complete */
4430         if (delay)
4431                 rte_delay_ms(delay);
4432 }
4433
4434 static void bnxt_dev_cleanup(struct bnxt *bp)
4435 {
4436         bp->eth_dev->data->dev_link.link_status = 0;
4437         bp->link_info->link_up = 0;
4438         if (bp->eth_dev->data->dev_started)
4439                 bnxt_dev_stop_op(bp->eth_dev);
4440
4441         bnxt_uninit_resources(bp, true);
4442 }
4443
4444 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4445 {
4446         struct rte_eth_dev *dev = bp->eth_dev;
4447         struct rte_vlan_filter_conf *vfc;
4448         int vidx, vbit, rc;
4449         uint16_t vlan_id;
4450
4451         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4452                 vfc = &dev->data->vlan_filter_conf;
4453                 vidx = vlan_id / 64;
4454                 vbit = vlan_id % 64;
4455
4456                 /* Each bit corresponds to a VLAN id */
4457                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4458                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4459                         if (rc)
4460                                 return rc;
4461                 }
4462         }
4463
4464         return 0;
4465 }
4466
4467 static int bnxt_restore_mac_filters(struct bnxt *bp)
4468 {
4469         struct rte_eth_dev *dev = bp->eth_dev;
4470         struct rte_eth_dev_info dev_info;
4471         struct rte_ether_addr *addr;
4472         uint64_t pool_mask;
4473         uint32_t pool = 0;
4474         uint16_t i;
4475         int rc;
4476
4477         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4478                 return 0;
4479
4480         rc = bnxt_dev_info_get_op(dev, &dev_info);
4481         if (rc)
4482                 return rc;
4483
4484         /* replay MAC address configuration */
4485         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4486                 addr = &dev->data->mac_addrs[i];
4487
4488                 /* skip zero address */
4489                 if (rte_is_zero_ether_addr(addr))
4490                         continue;
4491
4492                 pool = 0;
4493                 pool_mask = dev->data->mac_pool_sel[i];
4494
4495                 do {
4496                         if (pool_mask & 1ULL) {
4497                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4498                                 if (rc)
4499                                         return rc;
4500                         }
4501                         pool_mask >>= 1;
4502                         pool++;
4503                 } while (pool_mask);
4504         }
4505
4506         return 0;
4507 }
4508
4509 static int bnxt_restore_filters(struct bnxt *bp)
4510 {
4511         struct rte_eth_dev *dev = bp->eth_dev;
4512         int ret = 0;
4513
4514         if (dev->data->all_multicast) {
4515                 ret = bnxt_allmulticast_enable_op(dev);
4516                 if (ret)
4517                         return ret;
4518         }
4519         if (dev->data->promiscuous) {
4520                 ret = bnxt_promiscuous_enable_op(dev);
4521                 if (ret)
4522                         return ret;
4523         }
4524
4525         ret = bnxt_restore_mac_filters(bp);
4526         if (ret)
4527                 return ret;
4528
4529         ret = bnxt_restore_vlan_filters(bp);
4530         /* TODO restore other filters as well */
4531         return ret;
4532 }
4533
4534 static void bnxt_dev_recover(void *arg)
4535 {
4536         struct bnxt *bp = arg;
4537         int timeout = bp->fw_reset_max_msecs;
4538         int rc = 0;
4539
4540         /* Clear Error flag so that device re-init should happen */
4541         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4542
4543         do {
4544                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4545                 if (rc == 0)
4546                         break;
4547                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4548                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4549         } while (rc && timeout);
4550
4551         if (rc) {
4552                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4553                 goto err;
4554         }
4555
4556         rc = bnxt_init_resources(bp, true);
4557         if (rc) {
4558                 PMD_DRV_LOG(ERR,
4559                             "Failed to initialize resources after reset\n");
4560                 goto err;
4561         }
4562         /* clear reset flag as the device is initialized now */
4563         bp->flags &= ~BNXT_FLAG_FW_RESET;
4564
4565         rc = bnxt_dev_start_op(bp->eth_dev);
4566         if (rc) {
4567                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4568                 goto err_start;
4569         }
4570
4571         rc = bnxt_restore_filters(bp);
4572         if (rc)
4573                 goto err_start;
4574
4575         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4576         return;
4577 err_start:
4578         bnxt_dev_stop_op(bp->eth_dev);
4579 err:
4580         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4581         bnxt_uninit_resources(bp, false);
4582         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4583 }
4584
4585 void bnxt_dev_reset_and_resume(void *arg)
4586 {
4587         struct bnxt *bp = arg;
4588         int rc;
4589
4590         bnxt_dev_cleanup(bp);
4591
4592         bnxt_wait_for_device_shutdown(bp);
4593
4594         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4595                                bnxt_dev_recover, (void *)bp);
4596         if (rc)
4597                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4598 }
4599
4600 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4601 {
4602         struct bnxt_error_recovery_info *info = bp->recovery_info;
4603         uint32_t reg = info->status_regs[index];
4604         uint32_t type, offset, val = 0;
4605
4606         type = BNXT_FW_STATUS_REG_TYPE(reg);
4607         offset = BNXT_FW_STATUS_REG_OFF(reg);
4608
4609         switch (type) {
4610         case BNXT_FW_STATUS_REG_TYPE_CFG:
4611                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4612                 break;
4613         case BNXT_FW_STATUS_REG_TYPE_GRC:
4614                 offset = info->mapped_status_regs[index];
4615                 /* FALLTHROUGH */
4616         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4617                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4618                                        offset));
4619                 break;
4620         }
4621
4622         return val;
4623 }
4624
4625 static int bnxt_fw_reset_all(struct bnxt *bp)
4626 {
4627         struct bnxt_error_recovery_info *info = bp->recovery_info;
4628         uint32_t i;
4629         int rc = 0;
4630
4631         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4632                 /* Reset through master function driver */
4633                 for (i = 0; i < info->reg_array_cnt; i++)
4634                         bnxt_write_fw_reset_reg(bp, i);
4635                 /* Wait for time specified by FW after triggering reset */
4636                 rte_delay_ms(info->master_func_wait_period_after_reset);
4637         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4638                 /* Reset with the help of Kong processor */
4639                 rc = bnxt_hwrm_fw_reset(bp);
4640                 if (rc)
4641                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4642         }
4643
4644         return rc;
4645 }
4646
4647 static void bnxt_fw_reset_cb(void *arg)
4648 {
4649         struct bnxt *bp = arg;
4650         struct bnxt_error_recovery_info *info = bp->recovery_info;
4651         int rc = 0;
4652
4653         /* Only Master function can do FW reset */
4654         if (bnxt_is_master_func(bp) &&
4655             bnxt_is_recovery_enabled(bp)) {
4656                 rc = bnxt_fw_reset_all(bp);
4657                 if (rc) {
4658                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4659                         return;
4660                 }
4661         }
4662
4663         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4664          * EXCEPTION_FATAL_ASYNC event to all the functions
4665          * (including MASTER FUNC). After receiving this Async, all the active
4666          * drivers should treat this case as FW initiated recovery
4667          */
4668         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4669                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4670                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4671
4672                 /* To recover from error */
4673                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4674                                   (void *)bp);
4675         }
4676 }
4677
4678 /* Driver should poll FW heartbeat, reset_counter with the frequency
4679  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4680  * When the driver detects heartbeat stop or change in reset_counter,
4681  * it has to trigger a reset to recover from the error condition.
4682  * A “master PF” is the function who will have the privilege to
4683  * initiate the chimp reset. The master PF will be elected by the
4684  * firmware and will be notified through async message.
4685  */
4686 static void bnxt_check_fw_health(void *arg)
4687 {
4688         struct bnxt *bp = arg;
4689         struct bnxt_error_recovery_info *info = bp->recovery_info;
4690         uint32_t val = 0, wait_msec;
4691
4692         if (!info || !bnxt_is_recovery_enabled(bp) ||
4693             is_bnxt_in_error(bp))
4694                 return;
4695
4696         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4697         if (val == info->last_heart_beat)
4698                 goto reset;
4699
4700         info->last_heart_beat = val;
4701
4702         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4703         if (val != info->last_reset_counter)
4704                 goto reset;
4705
4706         info->last_reset_counter = val;
4707
4708         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4709                           bnxt_check_fw_health, (void *)bp);
4710
4711         return;
4712 reset:
4713         /* Stop DMA to/from device */
4714         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4715         bp->flags |= BNXT_FLAG_FW_RESET;
4716
4717         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4718
4719         if (bnxt_is_master_func(bp))
4720                 wait_msec = info->master_func_wait_period;
4721         else
4722                 wait_msec = info->normal_func_wait_period;
4723
4724         rte_eal_alarm_set(US_PER_MS * wait_msec,
4725                           bnxt_fw_reset_cb, (void *)bp);
4726 }
4727
4728 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4729 {
4730         uint32_t polling_freq;
4731
4732         pthread_mutex_lock(&bp->health_check_lock);
4733
4734         if (!bnxt_is_recovery_enabled(bp))
4735                 goto done;
4736
4737         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4738                 goto done;
4739
4740         polling_freq = bp->recovery_info->driver_polling_freq;
4741
4742         rte_eal_alarm_set(US_PER_MS * polling_freq,
4743                           bnxt_check_fw_health, (void *)bp);
4744         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4745
4746 done:
4747         pthread_mutex_unlock(&bp->health_check_lock);
4748 }
4749
4750 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4751 {
4752         if (!bnxt_is_recovery_enabled(bp))
4753                 return;
4754
4755         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4756         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4757 }
4758
4759 static bool bnxt_vf_pciid(uint16_t device_id)
4760 {
4761         switch (device_id) {
4762         case BROADCOM_DEV_ID_57304_VF:
4763         case BROADCOM_DEV_ID_57406_VF:
4764         case BROADCOM_DEV_ID_5731X_VF:
4765         case BROADCOM_DEV_ID_5741X_VF:
4766         case BROADCOM_DEV_ID_57414_VF:
4767         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4768         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4769         case BROADCOM_DEV_ID_58802_VF:
4770         case BROADCOM_DEV_ID_57500_VF1:
4771         case BROADCOM_DEV_ID_57500_VF2:
4772                 /* FALLTHROUGH */
4773                 return true;
4774         default:
4775                 return false;
4776         }
4777 }
4778
4779 static bool bnxt_thor_device(uint16_t device_id)
4780 {
4781         switch (device_id) {
4782         case BROADCOM_DEV_ID_57508:
4783         case BROADCOM_DEV_ID_57504:
4784         case BROADCOM_DEV_ID_57502:
4785         case BROADCOM_DEV_ID_57508_MF1:
4786         case BROADCOM_DEV_ID_57504_MF1:
4787         case BROADCOM_DEV_ID_57502_MF1:
4788         case BROADCOM_DEV_ID_57508_MF2:
4789         case BROADCOM_DEV_ID_57504_MF2:
4790         case BROADCOM_DEV_ID_57502_MF2:
4791         case BROADCOM_DEV_ID_57500_VF1:
4792         case BROADCOM_DEV_ID_57500_VF2:
4793                 /* FALLTHROUGH */
4794                 return true;
4795         default:
4796                 return false;
4797         }
4798 }
4799
4800 bool bnxt_stratus_device(struct bnxt *bp)
4801 {
4802         uint16_t device_id = bp->pdev->id.device_id;
4803
4804         switch (device_id) {
4805         case BROADCOM_DEV_ID_STRATUS_NIC:
4806         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4807         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4808                 /* FALLTHROUGH */
4809                 return true;
4810         default:
4811                 return false;
4812         }
4813 }
4814
4815 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4816 {
4817         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4818         struct bnxt *bp = eth_dev->data->dev_private;
4819
4820         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4821         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4822         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4823         if (!bp->bar0 || !bp->doorbell_base) {
4824                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4825                 return -ENODEV;
4826         }
4827
4828         bp->eth_dev = eth_dev;
4829         bp->pdev = pci_dev;
4830
4831         return 0;
4832 }
4833
4834 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4835                                   struct bnxt_ctx_pg_info *ctx_pg,
4836                                   uint32_t mem_size,
4837                                   const char *suffix,
4838                                   uint16_t idx)
4839 {
4840         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4841         const struct rte_memzone *mz = NULL;
4842         char mz_name[RTE_MEMZONE_NAMESIZE];
4843         rte_iova_t mz_phys_addr;
4844         uint64_t valid_bits = 0;
4845         uint32_t sz;
4846         int i;
4847
4848         if (!mem_size)
4849                 return 0;
4850
4851         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4852                          BNXT_PAGE_SIZE;
4853         rmem->page_size = BNXT_PAGE_SIZE;
4854         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4855         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4856         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4857
4858         valid_bits = PTU_PTE_VALID;
4859
4860         if (rmem->nr_pages > 1) {
4861                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4862                          "bnxt_ctx_pg_tbl%s_%x_%d",
4863                          suffix, idx, bp->eth_dev->data->port_id);
4864                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4865                 mz = rte_memzone_lookup(mz_name);
4866                 if (!mz) {
4867                         mz = rte_memzone_reserve_aligned(mz_name,
4868                                                 rmem->nr_pages * 8,
4869                                                 SOCKET_ID_ANY,
4870                                                 RTE_MEMZONE_2MB |
4871                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4872                                                 RTE_MEMZONE_IOVA_CONTIG,
4873                                                 BNXT_PAGE_SIZE);
4874                         if (mz == NULL)
4875                                 return -ENOMEM;
4876                 }
4877
4878                 memset(mz->addr, 0, mz->len);
4879                 mz_phys_addr = mz->iova;
4880
4881                 rmem->pg_tbl = mz->addr;
4882                 rmem->pg_tbl_map = mz_phys_addr;
4883                 rmem->pg_tbl_mz = mz;
4884         }
4885
4886         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4887                  suffix, idx, bp->eth_dev->data->port_id);
4888         mz = rte_memzone_lookup(mz_name);
4889         if (!mz) {
4890                 mz = rte_memzone_reserve_aligned(mz_name,
4891                                                  mem_size,
4892                                                  SOCKET_ID_ANY,
4893                                                  RTE_MEMZONE_1GB |
4894                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4895                                                  RTE_MEMZONE_IOVA_CONTIG,
4896                                                  BNXT_PAGE_SIZE);
4897                 if (mz == NULL)
4898                         return -ENOMEM;
4899         }
4900
4901         memset(mz->addr, 0, mz->len);
4902         mz_phys_addr = mz->iova;
4903
4904         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4905                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4906                 rmem->dma_arr[i] = mz_phys_addr + sz;
4907
4908                 if (rmem->nr_pages > 1) {
4909                         if (i == rmem->nr_pages - 2 &&
4910                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4911                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4912                         else if (i == rmem->nr_pages - 1 &&
4913                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4914                                 valid_bits |= PTU_PTE_LAST;
4915
4916                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4917                                                            valid_bits);
4918                 }
4919         }
4920
4921         rmem->mz = mz;
4922         if (rmem->vmem_size)
4923                 rmem->vmem = (void **)mz->addr;
4924         rmem->dma_arr[0] = mz_phys_addr;
4925         return 0;
4926 }
4927
4928 static void bnxt_free_ctx_mem(struct bnxt *bp)
4929 {
4930         int i;
4931
4932         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4933                 return;
4934
4935         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4936         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4937         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4938         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4939         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4940         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4941         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4942         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4943         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4944         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4945         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4946
4947         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4948                 if (bp->ctx->tqm_mem[i])
4949                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4950         }
4951
4952         rte_free(bp->ctx);
4953         bp->ctx = NULL;
4954 }
4955
4956 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4957
4958 #define min_t(type, x, y) ({                    \
4959         type __min1 = (x);                      \
4960         type __min2 = (y);                      \
4961         __min1 < __min2 ? __min1 : __min2; })
4962
4963 #define max_t(type, x, y) ({                    \
4964         type __max1 = (x);                      \
4965         type __max2 = (y);                      \
4966         __max1 > __max2 ? __max1 : __max2; })
4967
4968 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4969
4970 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4971 {
4972         struct bnxt_ctx_pg_info *ctx_pg;
4973         struct bnxt_ctx_mem_info *ctx;
4974         uint32_t mem_size, ena, entries;
4975         uint32_t entries_sp, min;
4976         int i, rc;
4977
4978         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4979         if (rc) {
4980                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4981                 return rc;
4982         }
4983         ctx = bp->ctx;
4984         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4985                 return 0;
4986
4987         ctx_pg = &ctx->qp_mem;
4988         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4989         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4990         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4991         if (rc)
4992                 return rc;
4993
4994         ctx_pg = &ctx->srq_mem;
4995         ctx_pg->entries = ctx->srq_max_l2_entries;
4996         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4997         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4998         if (rc)
4999                 return rc;
5000
5001         ctx_pg = &ctx->cq_mem;
5002         ctx_pg->entries = ctx->cq_max_l2_entries;
5003         mem_size = ctx->cq_entry_size * ctx_pg->entries;
5004         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
5005         if (rc)
5006                 return rc;
5007
5008         ctx_pg = &ctx->vnic_mem;
5009         ctx_pg->entries = ctx->vnic_max_vnic_entries +
5010                 ctx->vnic_max_ring_table_entries;
5011         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
5012         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
5013         if (rc)
5014                 return rc;
5015
5016         ctx_pg = &ctx->stat_mem;
5017         ctx_pg->entries = ctx->stat_max_entries;
5018         mem_size = ctx->stat_entry_size * ctx_pg->entries;
5019         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
5020         if (rc)
5021                 return rc;
5022
5023         min = ctx->tqm_min_entries_per_ring;
5024
5025         entries_sp = ctx->qp_max_l2_entries +
5026                      ctx->vnic_max_vnic_entries +
5027                      2 * ctx->qp_min_qp1_entries + min;
5028         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
5029
5030         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
5031         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
5032         entries = clamp_t(uint32_t, entries, min,
5033                           ctx->tqm_max_entries_per_ring);
5034         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
5035                 ctx_pg = ctx->tqm_mem[i];
5036                 ctx_pg->entries = i ? entries : entries_sp;
5037                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
5038                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
5039                 if (rc)
5040                         return rc;
5041                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
5042         }
5043
5044         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
5045         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
5046         if (rc)
5047                 PMD_DRV_LOG(ERR,
5048                             "Failed to configure context mem: rc = %d\n", rc);
5049         else
5050                 ctx->flags |= BNXT_CTX_FLAG_INITED;
5051
5052         return rc;
5053 }
5054
5055 static int bnxt_alloc_stats_mem(struct bnxt *bp)
5056 {
5057         struct rte_pci_device *pci_dev = bp->pdev;
5058         char mz_name[RTE_MEMZONE_NAMESIZE];
5059         const struct rte_memzone *mz = NULL;
5060         uint32_t total_alloc_len;
5061         rte_iova_t mz_phys_addr;
5062
5063         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
5064                 return 0;
5065
5066         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5067                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5068                  pci_dev->addr.bus, pci_dev->addr.devid,
5069                  pci_dev->addr.function, "rx_port_stats");
5070         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5071         mz = rte_memzone_lookup(mz_name);
5072         total_alloc_len =
5073                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
5074                                        sizeof(struct rx_port_stats_ext) + 512);
5075         if (!mz) {
5076                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
5077                                          SOCKET_ID_ANY,
5078                                          RTE_MEMZONE_2MB |
5079                                          RTE_MEMZONE_SIZE_HINT_ONLY |
5080                                          RTE_MEMZONE_IOVA_CONTIG);
5081                 if (mz == NULL)
5082                         return -ENOMEM;
5083         }
5084         memset(mz->addr, 0, mz->len);
5085         mz_phys_addr = mz->iova;
5086
5087         bp->rx_mem_zone = (const void *)mz;
5088         bp->hw_rx_port_stats = mz->addr;
5089         bp->hw_rx_port_stats_map = mz_phys_addr;
5090
5091         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5092                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5093                  pci_dev->addr.bus, pci_dev->addr.devid,
5094                  pci_dev->addr.function, "tx_port_stats");
5095         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5096         mz = rte_memzone_lookup(mz_name);
5097         total_alloc_len =
5098                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
5099                                        sizeof(struct tx_port_stats_ext) + 512);
5100         if (!mz) {
5101                 mz = rte_memzone_reserve(mz_name,
5102                                          total_alloc_len,
5103                                          SOCKET_ID_ANY,
5104                                          RTE_MEMZONE_2MB |
5105                                          RTE_MEMZONE_SIZE_HINT_ONLY |
5106                                          RTE_MEMZONE_IOVA_CONTIG);
5107                 if (mz == NULL)
5108                         return -ENOMEM;
5109         }
5110         memset(mz->addr, 0, mz->len);
5111         mz_phys_addr = mz->iova;
5112
5113         bp->tx_mem_zone = (const void *)mz;
5114         bp->hw_tx_port_stats = mz->addr;
5115         bp->hw_tx_port_stats_map = mz_phys_addr;
5116         bp->flags |= BNXT_FLAG_PORT_STATS;
5117
5118         /* Display extended statistics if FW supports it */
5119         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
5120             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
5121             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
5122                 return 0;
5123
5124         bp->hw_rx_port_stats_ext = (void *)
5125                 ((uint8_t *)bp->hw_rx_port_stats +
5126                  sizeof(struct rx_port_stats));
5127         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
5128                 sizeof(struct rx_port_stats);
5129         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
5130
5131         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
5132             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
5133                 bp->hw_tx_port_stats_ext = (void *)
5134                         ((uint8_t *)bp->hw_tx_port_stats +
5135                          sizeof(struct tx_port_stats));
5136                 bp->hw_tx_port_stats_ext_map =
5137                         bp->hw_tx_port_stats_map +
5138                         sizeof(struct tx_port_stats);
5139                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
5140         }
5141
5142         return 0;
5143 }
5144
5145 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
5146 {
5147         struct bnxt *bp = eth_dev->data->dev_private;
5148         int rc = 0;
5149
5150         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
5151                                                RTE_ETHER_ADDR_LEN *
5152                                                bp->max_l2_ctx,
5153                                                0);
5154         if (eth_dev->data->mac_addrs == NULL) {
5155                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
5156                 return -ENOMEM;
5157         }
5158
5159         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
5160                 if (BNXT_PF(bp))
5161                         return -EINVAL;
5162
5163                 /* Generate a random MAC address, if none was assigned by PF */
5164                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5165                 bnxt_eth_hw_addr_random(bp->mac_addr);
5166                 PMD_DRV_LOG(INFO,
5167                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
5168                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5169                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5170
5171                 rc = bnxt_hwrm_set_mac(bp);
5172                 if (rc)
5173                         return rc;
5174         }
5175
5176         /* Copy the permanent MAC from the FUNC_QCAPS response */
5177         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5178
5179         return rc;
5180 }
5181
5182 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5183 {
5184         int rc = 0;
5185
5186         /* MAC is already configured in FW */
5187         if (BNXT_HAS_DFLT_MAC_SET(bp))
5188                 return 0;
5189
5190         /* Restore the old MAC configured */
5191         rc = bnxt_hwrm_set_mac(bp);
5192         if (rc)
5193                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5194
5195         return rc;
5196 }
5197
5198 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5199 {
5200         if (!BNXT_PF(bp))
5201                 return;
5202
5203         memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5204
5205         if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
5206                 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
5207         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
5208         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
5209         BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
5210         BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
5211 }
5212
5213 uint16_t
5214 bnxt_get_svif(uint16_t port_id, bool func_svif,
5215               enum bnxt_ulp_intf_type type)
5216 {
5217         struct rte_eth_dev *eth_dev;
5218         struct bnxt *bp;
5219
5220         eth_dev = &rte_eth_devices[port_id];
5221         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5222                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5223                 if (!vfr)
5224                         return 0;
5225
5226                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5227                         return vfr->svif;
5228
5229                 eth_dev = vfr->parent_dev;
5230         }
5231
5232         bp = eth_dev->data->dev_private;
5233
5234         return func_svif ? bp->func_svif : bp->port_svif;
5235 }
5236
5237 uint16_t
5238 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5239 {
5240         struct rte_eth_dev *eth_dev;
5241         struct bnxt_vnic_info *vnic;
5242         struct bnxt *bp;
5243
5244         eth_dev = &rte_eth_devices[port];
5245         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5246                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5247                 if (!vfr)
5248                         return 0;
5249
5250                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5251                         return vfr->dflt_vnic_id;
5252
5253                 eth_dev = vfr->parent_dev;
5254         }
5255
5256         bp = eth_dev->data->dev_private;
5257
5258         vnic = BNXT_GET_DEFAULT_VNIC(bp);
5259
5260         return vnic->fw_vnic_id;
5261 }
5262
5263 uint16_t
5264 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5265 {
5266         struct rte_eth_dev *eth_dev;
5267         struct bnxt *bp;
5268
5269         eth_dev = &rte_eth_devices[port];
5270         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5271                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5272                 if (!vfr)
5273                         return 0;
5274
5275                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5276                         return vfr->fw_fid;
5277
5278                 eth_dev = vfr->parent_dev;
5279         }
5280
5281         bp = eth_dev->data->dev_private;
5282
5283         return bp->fw_fid;
5284 }
5285
5286 enum bnxt_ulp_intf_type
5287 bnxt_get_interface_type(uint16_t port)
5288 {
5289         struct rte_eth_dev *eth_dev;
5290         struct bnxt *bp;
5291
5292         eth_dev = &rte_eth_devices[port];
5293         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5294                 return BNXT_ULP_INTF_TYPE_VF_REP;
5295
5296         bp = eth_dev->data->dev_private;
5297         if (BNXT_PF(bp))
5298                 return BNXT_ULP_INTF_TYPE_PF;
5299         else if (BNXT_VF_IS_TRUSTED(bp))
5300                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5301         else if (BNXT_VF(bp))
5302                 return BNXT_ULP_INTF_TYPE_VF;
5303
5304         return BNXT_ULP_INTF_TYPE_INVALID;
5305 }
5306
5307 uint16_t
5308 bnxt_get_phy_port_id(uint16_t port_id)
5309 {
5310         struct bnxt_representor *vfr;
5311         struct rte_eth_dev *eth_dev;
5312         struct bnxt *bp;
5313
5314         eth_dev = &rte_eth_devices[port_id];
5315         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5316                 vfr = eth_dev->data->dev_private;
5317                 if (!vfr)
5318                         return 0;
5319
5320                 eth_dev = vfr->parent_dev;
5321         }
5322
5323         bp = eth_dev->data->dev_private;
5324
5325         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5326 }
5327
5328 uint16_t
5329 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5330 {
5331         struct rte_eth_dev *eth_dev;
5332         struct bnxt *bp;
5333
5334         eth_dev = &rte_eth_devices[port_id];
5335         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5336                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5337                 if (!vfr)
5338                         return 0;
5339
5340                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5341                         return vfr->fw_fid - 1;
5342
5343                 eth_dev = vfr->parent_dev;
5344         }
5345
5346         bp = eth_dev->data->dev_private;
5347
5348         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5349 }
5350
5351 uint16_t
5352 bnxt_get_vport(uint16_t port_id)
5353 {
5354         return (1 << bnxt_get_phy_port_id(port_id));
5355 }
5356
5357 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5358 {
5359         struct bnxt_error_recovery_info *info = bp->recovery_info;
5360
5361         if (info) {
5362                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5363                         memset(info, 0, sizeof(*info));
5364                 return;
5365         }
5366
5367         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5368                 return;
5369
5370         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5371                            sizeof(*info), 0);
5372         if (!info)
5373                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5374
5375         bp->recovery_info = info;
5376 }
5377
5378 static void bnxt_check_fw_status(struct bnxt *bp)
5379 {
5380         uint32_t fw_status;
5381
5382         if (!(bp->recovery_info &&
5383               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5384                 return;
5385
5386         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5387         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5388                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5389                             fw_status);
5390 }
5391
5392 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5393 {
5394         struct bnxt_error_recovery_info *info = bp->recovery_info;
5395         uint32_t status_loc;
5396         uint32_t sig_ver;
5397
5398         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5399                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5400         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5401                                    BNXT_GRCP_WINDOW_2_BASE +
5402                                    offsetof(struct hcomm_status,
5403                                             sig_ver)));
5404         /* If the signature is absent, then FW does not support this feature */
5405         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5406             HCOMM_STATUS_SIGNATURE_VAL)
5407                 return 0;
5408
5409         if (!info) {
5410                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5411                                    sizeof(*info), 0);
5412                 if (!info)
5413                         return -ENOMEM;
5414                 bp->recovery_info = info;
5415         } else {
5416                 memset(info, 0, sizeof(*info));
5417         }
5418
5419         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5420                                       BNXT_GRCP_WINDOW_2_BASE +
5421                                       offsetof(struct hcomm_status,
5422                                                fw_status_loc)));
5423
5424         /* Only pre-map the FW health status GRC register */
5425         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5426                 return 0;
5427
5428         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5429         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5430                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5431
5432         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5433                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5434
5435         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5436
5437         return 0;
5438 }
5439
5440 static int bnxt_init_fw(struct bnxt *bp)
5441 {
5442         uint16_t mtu;
5443         int rc = 0;
5444
5445         bp->fw_cap = 0;
5446
5447         rc = bnxt_map_hcomm_fw_status_reg(bp);
5448         if (rc)
5449                 return rc;
5450
5451         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5452         if (rc) {
5453                 bnxt_check_fw_status(bp);
5454                 return rc;
5455         }
5456
5457         rc = bnxt_hwrm_func_reset(bp);
5458         if (rc)
5459                 return -EIO;
5460
5461         rc = bnxt_hwrm_vnic_qcaps(bp);
5462         if (rc)
5463                 return rc;
5464
5465         rc = bnxt_hwrm_queue_qportcfg(bp);
5466         if (rc)
5467                 return rc;
5468
5469         /* Get the MAX capabilities for this function.
5470          * This function also allocates context memory for TQM rings and
5471          * informs the firmware about this allocated backing store memory.
5472          */
5473         rc = bnxt_hwrm_func_qcaps(bp);
5474         if (rc)
5475                 return rc;
5476
5477         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5478         if (rc)
5479                 return rc;
5480
5481         bnxt_hwrm_port_mac_qcfg(bp);
5482
5483         bnxt_hwrm_parent_pf_qcfg(bp);
5484
5485         bnxt_hwrm_port_phy_qcaps(bp);
5486
5487         bnxt_alloc_error_recovery_info(bp);
5488         /* Get the adapter error recovery support info */
5489         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5490         if (rc)
5491                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5492
5493         bnxt_hwrm_port_led_qcaps(bp);
5494
5495         return 0;
5496 }
5497
5498 static int
5499 bnxt_init_locks(struct bnxt *bp)
5500 {
5501         int err;
5502
5503         err = pthread_mutex_init(&bp->flow_lock, NULL);
5504         if (err) {
5505                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5506                 return err;
5507         }
5508
5509         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5510         if (err)
5511                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5512
5513         err = pthread_mutex_init(&bp->health_check_lock, NULL);
5514         if (err)
5515                 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5516         return err;
5517 }
5518
5519 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5520 {
5521         int rc = 0;
5522
5523         rc = bnxt_init_fw(bp);
5524         if (rc)
5525                 return rc;
5526
5527         if (!reconfig_dev) {
5528                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5529                 if (rc)
5530                         return rc;
5531         } else {
5532                 rc = bnxt_restore_dflt_mac(bp);
5533                 if (rc)
5534                         return rc;
5535         }
5536
5537         bnxt_config_vf_req_fwd(bp);
5538
5539         rc = bnxt_hwrm_func_driver_register(bp);
5540         if (rc) {
5541                 PMD_DRV_LOG(ERR, "Failed to register driver");
5542                 return -EBUSY;
5543         }
5544
5545         if (BNXT_PF(bp)) {
5546                 if (bp->pdev->max_vfs) {
5547                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5548                         if (rc) {
5549                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5550                                 return rc;
5551                         }
5552                 } else {
5553                         rc = bnxt_hwrm_allocate_pf_only(bp);
5554                         if (rc) {
5555                                 PMD_DRV_LOG(ERR,
5556                                             "Failed to allocate PF resources");
5557                                 return rc;
5558                         }
5559                 }
5560         }
5561
5562         rc = bnxt_alloc_mem(bp, reconfig_dev);
5563         if (rc)
5564                 return rc;
5565
5566         rc = bnxt_setup_int(bp);
5567         if (rc)
5568                 return rc;
5569
5570         rc = bnxt_request_int(bp);
5571         if (rc)
5572                 return rc;
5573
5574         rc = bnxt_init_ctx_mem(bp);
5575         if (rc) {
5576                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5577                 return rc;
5578         }
5579
5580         rc = bnxt_init_locks(bp);
5581         if (rc)
5582                 return rc;
5583
5584         return 0;
5585 }
5586
5587 static int
5588 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5589                           const char *value, void *opaque_arg)
5590 {
5591         struct bnxt *bp = opaque_arg;
5592         unsigned long truflow;
5593         char *end = NULL;
5594
5595         if (!value || !opaque_arg) {
5596                 PMD_DRV_LOG(ERR,
5597                             "Invalid parameter passed to truflow devargs.\n");
5598                 return -EINVAL;
5599         }
5600
5601         truflow = strtoul(value, &end, 10);
5602         if (end == NULL || *end != '\0' ||
5603             (truflow == ULONG_MAX && errno == ERANGE)) {
5604                 PMD_DRV_LOG(ERR,
5605                             "Invalid parameter passed to truflow devargs.\n");
5606                 return -EINVAL;
5607         }
5608
5609         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5610                 PMD_DRV_LOG(ERR,
5611                             "Invalid value passed to truflow devargs.\n");
5612                 return -EINVAL;
5613         }
5614
5615         if (truflow) {
5616                 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5617                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5618         } else {
5619                 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
5620                 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
5621         }
5622
5623         return 0;
5624 }
5625
5626 static int
5627 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5628                              const char *value, void *opaque_arg)
5629 {
5630         struct bnxt *bp = opaque_arg;
5631         unsigned long flow_xstat;
5632         char *end = NULL;
5633
5634         if (!value || !opaque_arg) {
5635                 PMD_DRV_LOG(ERR,
5636                             "Invalid parameter passed to flow_xstat devarg.\n");
5637                 return -EINVAL;
5638         }
5639
5640         flow_xstat = strtoul(value, &end, 10);
5641         if (end == NULL || *end != '\0' ||
5642             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5643                 PMD_DRV_LOG(ERR,
5644                             "Invalid parameter passed to flow_xstat devarg.\n");
5645                 return -EINVAL;
5646         }
5647
5648         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5649                 PMD_DRV_LOG(ERR,
5650                             "Invalid value passed to flow_xstat devarg.\n");
5651                 return -EINVAL;
5652         }
5653
5654         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5655         if (BNXT_FLOW_XSTATS_EN(bp))
5656                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5657
5658         return 0;
5659 }
5660
5661 static int
5662 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5663                                         const char *value, void *opaque_arg)
5664 {
5665         struct bnxt *bp = opaque_arg;
5666         unsigned long max_num_kflows;
5667         char *end = NULL;
5668
5669         if (!value || !opaque_arg) {
5670                 PMD_DRV_LOG(ERR,
5671                         "Invalid parameter passed to max_num_kflows devarg.\n");
5672                 return -EINVAL;
5673         }
5674
5675         max_num_kflows = strtoul(value, &end, 10);
5676         if (end == NULL || *end != '\0' ||
5677                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5678                 PMD_DRV_LOG(ERR,
5679                         "Invalid parameter passed to max_num_kflows devarg.\n");
5680                 return -EINVAL;
5681         }
5682
5683         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5684                 PMD_DRV_LOG(ERR,
5685                         "Invalid value passed to max_num_kflows devarg.\n");
5686                 return -EINVAL;
5687         }
5688
5689         bp->max_num_kflows = max_num_kflows;
5690         if (bp->max_num_kflows)
5691                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5692                                 max_num_kflows);
5693
5694         return 0;
5695 }
5696
5697 static int
5698 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5699                             const char *value, void *opaque_arg)
5700 {
5701         struct bnxt_representor *vfr_bp = opaque_arg;
5702         unsigned long rep_is_pf;
5703         char *end = NULL;
5704
5705         if (!value || !opaque_arg) {
5706                 PMD_DRV_LOG(ERR,
5707                             "Invalid parameter passed to rep_is_pf devargs.\n");
5708                 return -EINVAL;
5709         }
5710
5711         rep_is_pf = strtoul(value, &end, 10);
5712         if (end == NULL || *end != '\0' ||
5713             (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5714                 PMD_DRV_LOG(ERR,
5715                             "Invalid parameter passed to rep_is_pf devargs.\n");
5716                 return -EINVAL;
5717         }
5718
5719         if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5720                 PMD_DRV_LOG(ERR,
5721                             "Invalid value passed to rep_is_pf devargs.\n");
5722                 return -EINVAL;
5723         }
5724
5725         vfr_bp->flags |= rep_is_pf;
5726         if (BNXT_REP_PF(vfr_bp))
5727                 PMD_DRV_LOG(INFO, "PF representor\n");
5728         else
5729                 PMD_DRV_LOG(INFO, "VF representor\n");
5730
5731         return 0;
5732 }
5733
5734 static int
5735 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5736                                const char *value, void *opaque_arg)
5737 {
5738         struct bnxt_representor *vfr_bp = opaque_arg;
5739         unsigned long rep_based_pf;
5740         char *end = NULL;
5741
5742         if (!value || !opaque_arg) {
5743                 PMD_DRV_LOG(ERR,
5744                             "Invalid parameter passed to rep_based_pf "
5745                             "devargs.\n");
5746                 return -EINVAL;
5747         }
5748
5749         rep_based_pf = strtoul(value, &end, 10);
5750         if (end == NULL || *end != '\0' ||
5751             (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5752                 PMD_DRV_LOG(ERR,
5753                             "Invalid parameter passed to rep_based_pf "
5754                             "devargs.\n");
5755                 return -EINVAL;
5756         }
5757
5758         if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5759                 PMD_DRV_LOG(ERR,
5760                             "Invalid value passed to rep_based_pf devargs.\n");
5761                 return -EINVAL;
5762         }
5763
5764         vfr_bp->rep_based_pf = rep_based_pf;
5765         PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5766
5767         return 0;
5768 }
5769
5770 static int
5771 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5772                             const char *value, void *opaque_arg)
5773 {
5774         struct bnxt_representor *vfr_bp = opaque_arg;
5775         unsigned long rep_q_r2f;
5776         char *end = NULL;
5777
5778         if (!value || !opaque_arg) {
5779                 PMD_DRV_LOG(ERR,
5780                             "Invalid parameter passed to rep_q_r2f "
5781                             "devargs.\n");
5782                 return -EINVAL;
5783         }
5784
5785         rep_q_r2f = strtoul(value, &end, 10);
5786         if (end == NULL || *end != '\0' ||
5787             (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5788                 PMD_DRV_LOG(ERR,
5789                             "Invalid parameter passed to rep_q_r2f "
5790                             "devargs.\n");
5791                 return -EINVAL;
5792         }
5793
5794         if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5795                 PMD_DRV_LOG(ERR,
5796                             "Invalid value passed to rep_q_r2f devargs.\n");
5797                 return -EINVAL;
5798         }
5799
5800         vfr_bp->rep_q_r2f = rep_q_r2f;
5801         vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5802         PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5803
5804         return 0;
5805 }
5806
5807 static int
5808 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5809                             const char *value, void *opaque_arg)
5810 {
5811         struct bnxt_representor *vfr_bp = opaque_arg;
5812         unsigned long rep_q_f2r;
5813         char *end = NULL;
5814
5815         if (!value || !opaque_arg) {
5816                 PMD_DRV_LOG(ERR,
5817                             "Invalid parameter passed to rep_q_f2r "
5818                             "devargs.\n");
5819                 return -EINVAL;
5820         }
5821
5822         rep_q_f2r = strtoul(value, &end, 10);
5823         if (end == NULL || *end != '\0' ||
5824             (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5825                 PMD_DRV_LOG(ERR,
5826                             "Invalid parameter passed to rep_q_f2r "
5827                             "devargs.\n");
5828                 return -EINVAL;
5829         }
5830
5831         if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5832                 PMD_DRV_LOG(ERR,
5833                             "Invalid value passed to rep_q_f2r devargs.\n");
5834                 return -EINVAL;
5835         }
5836
5837         vfr_bp->rep_q_f2r = rep_q_f2r;
5838         vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5839         PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5840
5841         return 0;
5842 }
5843
5844 static int
5845 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5846                              const char *value, void *opaque_arg)
5847 {
5848         struct bnxt_representor *vfr_bp = opaque_arg;
5849         unsigned long rep_fc_r2f;
5850         char *end = NULL;
5851
5852         if (!value || !opaque_arg) {
5853                 PMD_DRV_LOG(ERR,
5854                             "Invalid parameter passed to rep_fc_r2f "
5855                             "devargs.\n");
5856                 return -EINVAL;
5857         }
5858
5859         rep_fc_r2f = strtoul(value, &end, 10);
5860         if (end == NULL || *end != '\0' ||
5861             (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5862                 PMD_DRV_LOG(ERR,
5863                             "Invalid parameter passed to rep_fc_r2f "
5864                             "devargs.\n");
5865                 return -EINVAL;
5866         }
5867
5868         if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5869                 PMD_DRV_LOG(ERR,
5870                             "Invalid value passed to rep_fc_r2f devargs.\n");
5871                 return -EINVAL;
5872         }
5873
5874         vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5875         vfr_bp->rep_fc_r2f = rep_fc_r2f;
5876         PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5877
5878         return 0;
5879 }
5880
5881 static int
5882 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5883                              const char *value, void *opaque_arg)
5884 {
5885         struct bnxt_representor *vfr_bp = opaque_arg;
5886         unsigned long rep_fc_f2r;
5887         char *end = NULL;
5888
5889         if (!value || !opaque_arg) {
5890                 PMD_DRV_LOG(ERR,
5891                             "Invalid parameter passed to rep_fc_f2r "
5892                             "devargs.\n");
5893                 return -EINVAL;
5894         }
5895
5896         rep_fc_f2r = strtoul(value, &end, 10);
5897         if (end == NULL || *end != '\0' ||
5898             (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5899                 PMD_DRV_LOG(ERR,
5900                             "Invalid parameter passed to rep_fc_f2r "
5901                             "devargs.\n");
5902                 return -EINVAL;
5903         }
5904
5905         if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5906                 PMD_DRV_LOG(ERR,
5907                             "Invalid value passed to rep_fc_f2r devargs.\n");
5908                 return -EINVAL;
5909         }
5910
5911         vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5912         vfr_bp->rep_fc_f2r = rep_fc_f2r;
5913         PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5914
5915         return 0;
5916 }
5917
5918 static void
5919 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5920 {
5921         struct rte_kvargs *kvlist;
5922
5923         if (devargs == NULL)
5924                 return;
5925
5926         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5927         if (kvlist == NULL)
5928                 return;
5929
5930         /*
5931          * Handler for "truflow" devarg.
5932          * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1"
5933          */
5934         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5935                            bnxt_parse_devarg_truflow, bp);
5936
5937         /*
5938          * Handler for "flow_xstat" devarg.
5939          * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1"
5940          */
5941         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5942                            bnxt_parse_devarg_flow_xstat, bp);
5943
5944         /*
5945          * Handler for "max_num_kflows" devarg.
5946          * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32"
5947          */
5948         rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5949                            bnxt_parse_devarg_max_num_kflows, bp);
5950
5951         rte_kvargs_free(kvlist);
5952 }
5953
5954 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5955 {
5956         int rc = 0;
5957
5958         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5959                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5960                 if (rc)
5961                         PMD_DRV_LOG(ERR,
5962                                     "Failed to alloc switch domain: %d\n", rc);
5963                 else
5964                         PMD_DRV_LOG(INFO,
5965                                     "Switch domain allocated %d\n",
5966                                     bp->switch_domain_id);
5967         }
5968
5969         return rc;
5970 }
5971
5972 static int
5973 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5974 {
5975         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5976         static int version_printed;
5977         struct bnxt *bp;
5978         int rc;
5979
5980         if (version_printed++ == 0)
5981                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5982
5983         eth_dev->dev_ops = &bnxt_dev_ops;
5984         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5985         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5986         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5987         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5988         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5989
5990         /*
5991          * For secondary processes, we don't initialise any further
5992          * as primary has already done this work.
5993          */
5994         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5995                 return 0;
5996
5997         rte_eth_copy_pci_info(eth_dev, pci_dev);
5998
5999         bp = eth_dev->data->dev_private;
6000
6001         /* Parse dev arguments passed on when starting the DPDK application. */
6002         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
6003
6004         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
6005
6006         if (bnxt_vf_pciid(pci_dev->id.device_id))
6007                 bp->flags |= BNXT_FLAG_VF;
6008
6009         if (bnxt_thor_device(pci_dev->id.device_id))
6010                 bp->flags |= BNXT_FLAG_THOR_CHIP;
6011
6012         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
6013             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
6014             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
6015             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
6016                 bp->flags |= BNXT_FLAG_STINGRAY;
6017
6018         rc = bnxt_init_board(eth_dev);
6019         if (rc) {
6020                 PMD_DRV_LOG(ERR,
6021                             "Failed to initialize board rc: %x\n", rc);
6022                 return rc;
6023         }
6024
6025         rc = bnxt_alloc_pf_info(bp);
6026         if (rc)
6027                 goto error_free;
6028
6029         rc = bnxt_alloc_link_info(bp);
6030         if (rc)
6031                 goto error_free;
6032
6033         rc = bnxt_alloc_parent_info(bp);
6034         if (rc)
6035                 goto error_free;
6036
6037         rc = bnxt_alloc_hwrm_resources(bp);
6038         if (rc) {
6039                 PMD_DRV_LOG(ERR,
6040                             "Failed to allocate hwrm resource rc: %x\n", rc);
6041                 goto error_free;
6042         }
6043         rc = bnxt_alloc_leds_info(bp);
6044         if (rc)
6045                 goto error_free;
6046
6047         rc = bnxt_alloc_cos_queues(bp);
6048         if (rc)
6049                 goto error_free;
6050
6051         rc = bnxt_init_resources(bp, false);
6052         if (rc)
6053                 goto error_free;
6054
6055         rc = bnxt_alloc_stats_mem(bp);
6056         if (rc)
6057                 goto error_free;
6058
6059         bnxt_alloc_switch_domain(bp);
6060
6061         PMD_DRV_LOG(INFO,
6062                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
6063                     pci_dev->mem_resource[0].phys_addr,
6064                     pci_dev->mem_resource[0].addr);
6065
6066         return 0;
6067
6068 error_free:
6069         bnxt_dev_uninit(eth_dev);
6070         return rc;
6071 }
6072
6073
6074 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
6075 {
6076         if (!ctx)
6077                 return;
6078
6079         if (ctx->va)
6080                 rte_free(ctx->va);
6081
6082         ctx->va = NULL;
6083         ctx->dma = RTE_BAD_IOVA;
6084         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
6085 }
6086
6087 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
6088 {
6089         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
6090                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6091                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
6092                                   bp->flow_stat->max_fc,
6093                                   false);
6094
6095         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
6096                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6097                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
6098                                   bp->flow_stat->max_fc,
6099                                   false);
6100
6101         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6102                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
6103         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6104
6105         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6106                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
6107         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6108
6109         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6110                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
6111         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6112
6113         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6114                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
6115         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6116 }
6117
6118 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
6119 {
6120         bnxt_unregister_fc_ctx_mem(bp);
6121
6122         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
6123         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
6124         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
6125         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
6126 }
6127
6128 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
6129 {
6130         if (BNXT_FLOW_XSTATS_EN(bp))
6131                 bnxt_uninit_fc_ctx_mem(bp);
6132 }
6133
6134 static void
6135 bnxt_free_error_recovery_info(struct bnxt *bp)
6136 {
6137         rte_free(bp->recovery_info);
6138         bp->recovery_info = NULL;
6139         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
6140 }
6141
6142 static void
6143 bnxt_uninit_locks(struct bnxt *bp)
6144 {
6145         pthread_mutex_destroy(&bp->flow_lock);
6146         pthread_mutex_destroy(&bp->def_cp_lock);
6147         pthread_mutex_destroy(&bp->health_check_lock);
6148         if (bp->rep_info) {
6149                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
6150                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
6151         }
6152 }
6153
6154 static int
6155 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
6156 {
6157         int rc;
6158
6159         bnxt_free_int(bp);
6160         bnxt_free_mem(bp, reconfig_dev);
6161
6162         bnxt_hwrm_func_buf_unrgtr(bp);
6163         rte_free(bp->pf->vf_req_buf);
6164
6165         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
6166         bp->flags &= ~BNXT_FLAG_REGISTERED;
6167         bnxt_free_ctx_mem(bp);
6168         if (!reconfig_dev) {
6169                 bnxt_free_hwrm_resources(bp);
6170                 bnxt_free_error_recovery_info(bp);
6171         }
6172
6173         bnxt_uninit_ctx_mem(bp);
6174
6175         bnxt_uninit_locks(bp);
6176         bnxt_free_flow_stats_info(bp);
6177         bnxt_free_rep_info(bp);
6178         rte_free(bp->ptp_cfg);
6179         bp->ptp_cfg = NULL;
6180         return rc;
6181 }
6182
6183 static int
6184 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
6185 {
6186         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6187                 return -EPERM;
6188
6189         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
6190
6191         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
6192                 bnxt_dev_close_op(eth_dev);
6193
6194         return 0;
6195 }
6196
6197 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
6198 {
6199         struct bnxt *bp = eth_dev->data->dev_private;
6200         struct rte_eth_dev *vf_rep_eth_dev;
6201         int ret = 0, i;
6202
6203         if (!bp)
6204                 return -EINVAL;
6205
6206         for (i = 0; i < bp->num_reps; i++) {
6207                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
6208                 if (!vf_rep_eth_dev)
6209                         continue;
6210                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
6211                             vf_rep_eth_dev->data->port_id);
6212                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
6213         }
6214         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
6215                     eth_dev->data->port_id);
6216         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
6217
6218         return ret;
6219 }
6220
6221 static void bnxt_free_rep_info(struct bnxt *bp)
6222 {
6223         rte_free(bp->rep_info);
6224         bp->rep_info = NULL;
6225         rte_free(bp->cfa_code_map);
6226         bp->cfa_code_map = NULL;
6227 }
6228
6229 static int bnxt_init_rep_info(struct bnxt *bp)
6230 {
6231         int i = 0, rc;
6232
6233         if (bp->rep_info)
6234                 return 0;
6235
6236         bp->rep_info = rte_zmalloc("bnxt_rep_info",
6237                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
6238                                    0);
6239         if (!bp->rep_info) {
6240                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
6241                 return -ENOMEM;
6242         }
6243         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
6244                                        sizeof(*bp->cfa_code_map) *
6245                                        BNXT_MAX_CFA_CODE, 0);
6246         if (!bp->cfa_code_map) {
6247                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
6248                 bnxt_free_rep_info(bp);
6249                 return -ENOMEM;
6250         }
6251
6252         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
6253                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
6254
6255         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
6256         if (rc) {
6257                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
6258                 bnxt_free_rep_info(bp);
6259                 return rc;
6260         }
6261
6262         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
6263         if (rc) {
6264                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
6265                 bnxt_free_rep_info(bp);
6266                 return rc;
6267         }
6268
6269         return rc;
6270 }
6271
6272 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
6273                                struct rte_eth_devargs eth_da,
6274                                struct rte_eth_dev *backing_eth_dev,
6275                                const char *dev_args)
6276 {
6277         struct rte_eth_dev *vf_rep_eth_dev;
6278         char name[RTE_ETH_NAME_MAX_LEN];
6279         struct bnxt *backing_bp;
6280         uint16_t num_rep;
6281         int i, ret = 0;
6282         struct rte_kvargs *kvlist;
6283
6284         num_rep = eth_da.nb_representor_ports;
6285         if (num_rep > BNXT_MAX_VF_REPS) {
6286                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
6287                             num_rep, BNXT_MAX_VF_REPS);
6288                 return -EINVAL;
6289         }
6290
6291         if (num_rep >= RTE_MAX_ETHPORTS) {
6292                 PMD_DRV_LOG(ERR,
6293                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6294                             num_rep, RTE_MAX_ETHPORTS);
6295                 return -EINVAL;
6296         }
6297
6298         backing_bp = backing_eth_dev->data->dev_private;
6299
6300         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6301                 PMD_DRV_LOG(ERR,
6302                             "Not a PF or trusted VF. No Representor support\n");
6303                 /* Returning an error is not an option.
6304                  * Applications are not handling this correctly
6305                  */
6306                 return 0;
6307         }
6308
6309         if (bnxt_init_rep_info(backing_bp))
6310                 return 0;
6311
6312         for (i = 0; i < num_rep; i++) {
6313                 struct bnxt_representor representor = {
6314                         .vf_id = eth_da.representor_ports[i],
6315                         .switch_domain_id = backing_bp->switch_domain_id,
6316                         .parent_dev = backing_eth_dev
6317                 };
6318
6319                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6320                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6321                                     representor.vf_id, BNXT_MAX_VF_REPS);
6322                         continue;
6323                 }
6324
6325                 /* representor port net_bdf_port */
6326                 snprintf(name, sizeof(name), "net_%s_representor_%d",
6327                          pci_dev->device.name, eth_da.representor_ports[i]);
6328
6329                 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
6330                 if (kvlist) {
6331                         /*
6332                          * Handler for "rep_is_pf" devarg.
6333                          * Invoked as for ex: "-w 000:00:0d.0,
6334                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6335                          */
6336                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
6337                                            bnxt_parse_devarg_rep_is_pf,
6338                                            (void *)&representor);
6339                         /*
6340                          * Handler for "rep_based_pf" devarg.
6341                          * Invoked as for ex: "-w 000:00:0d.0,
6342                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6343                          */
6344                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_BASED_PF,
6345                                            bnxt_parse_devarg_rep_based_pf,
6346                                            (void *)&representor);
6347                         /*
6348                          * Handler for "rep_based_pf" devarg.
6349                          * Invoked as for ex: "-w 000:00:0d.0,
6350                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6351                          */
6352                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
6353                                            bnxt_parse_devarg_rep_q_r2f,
6354                                            (void *)&representor);
6355                         /*
6356                          * Handler for "rep_based_pf" devarg.
6357                          * Invoked as for ex: "-w 000:00:0d.0,
6358                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6359                          */
6360                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
6361                                            bnxt_parse_devarg_rep_q_f2r,
6362                                            (void *)&representor);
6363                         /*
6364                          * Handler for "rep_based_pf" devarg.
6365                          * Invoked as for ex: "-w 000:00:0d.0,
6366                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6367                          */
6368                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
6369                                            bnxt_parse_devarg_rep_fc_r2f,
6370                                            (void *)&representor);
6371                         /*
6372                          * Handler for "rep_based_pf" devarg.
6373                          * Invoked as for ex: "-w 000:00:0d.0,
6374                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6375                          */
6376                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
6377                                            bnxt_parse_devarg_rep_fc_f2r,
6378                                            (void *)&representor);
6379                 }
6380
6381                 ret = rte_eth_dev_create(&pci_dev->device, name,
6382                                          sizeof(struct bnxt_representor),
6383                                          NULL, NULL,
6384                                          bnxt_representor_init,
6385                                          &representor);
6386                 if (ret) {
6387                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6388                                     "representor %s.", name);
6389                         goto err;
6390                 }
6391
6392                 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6393                 if (!vf_rep_eth_dev) {
6394                         PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6395                                     " for VF-Rep: %s.", name);
6396                         ret = -ENODEV;
6397                         goto err;
6398                 }
6399
6400                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6401                             backing_eth_dev->data->port_id);
6402                 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6403                                                          vf_rep_eth_dev;
6404                 backing_bp->num_reps++;
6405
6406         }
6407
6408         return 0;
6409
6410 err:
6411         /* If num_rep > 1, then rollback already created
6412          * ports, since we'll be failing the probe anyway
6413          */
6414         if (num_rep > 1)
6415                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6416
6417         return ret;
6418 }
6419
6420 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6421                           struct rte_pci_device *pci_dev)
6422 {
6423         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6424         struct rte_eth_dev *backing_eth_dev;
6425         uint16_t num_rep;
6426         int ret = 0;
6427
6428         if (pci_dev->device.devargs) {
6429                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6430                                             &eth_da);
6431                 if (ret)
6432                         return ret;
6433         }
6434
6435         num_rep = eth_da.nb_representor_ports;
6436         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6437                     num_rep);
6438
6439         /* We could come here after first level of probe is already invoked
6440          * as part of an application bringup(OVS-DPDK vswitchd), so first check
6441          * for already allocated eth_dev for the backing device (PF/Trusted VF)
6442          */
6443         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6444         if (backing_eth_dev == NULL) {
6445                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6446                                          sizeof(struct bnxt),
6447                                          eth_dev_pci_specific_init, pci_dev,
6448                                          bnxt_dev_init, NULL);
6449
6450                 if (ret || !num_rep)
6451                         return ret;
6452
6453                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6454         }
6455         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6456                     backing_eth_dev->data->port_id);
6457
6458         if (!num_rep)
6459                 return ret;
6460
6461         /* probe representor ports now */
6462         ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev,
6463                                   pci_dev->device.devargs->args);
6464
6465         return ret;
6466 }
6467
6468 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6469 {
6470         struct rte_eth_dev *eth_dev;
6471
6472         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6473         if (!eth_dev)
6474                 return 0; /* Invoked typically only by OVS-DPDK, by the
6475                            * time it comes here the eth_dev is already
6476                            * deleted by rte_eth_dev_close(), so returning
6477                            * +ve value will at least help in proper cleanup
6478                            */
6479
6480         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6481         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6482                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6483                         return rte_eth_dev_destroy(eth_dev,
6484                                                    bnxt_representor_uninit);
6485                 else
6486                         return rte_eth_dev_destroy(eth_dev,
6487                                                    bnxt_dev_uninit);
6488         } else {
6489                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6490         }
6491 }
6492
6493 static struct rte_pci_driver bnxt_rte_pmd = {
6494         .id_table = bnxt_pci_id_map,
6495         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6496                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6497                                                   * and OVS-DPDK
6498                                                   */
6499         .probe = bnxt_pci_probe,
6500         .remove = bnxt_pci_remove,
6501 };
6502
6503 static bool
6504 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6505 {
6506         if (strcmp(dev->device->driver->name, drv->driver.name))
6507                 return false;
6508
6509         return true;
6510 }
6511
6512 bool is_bnxt_supported(struct rte_eth_dev *dev)
6513 {
6514         return is_device_supported(dev, &bnxt_rte_pmd);
6515 }
6516
6517 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
6518 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6519 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6520 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");