drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <ethdev_driver.h>
  11 #include <ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16 #include <rte_vect.h>
  17
  18 #include "bnxt.h"
  19 #include "bnxt_filter.h"
  20 #include "bnxt_hwrm.h"
  21 #include "bnxt_irq.h"
  22 #include "bnxt_reps.h"
  23 #include "bnxt_ring.h"
  24 #include "bnxt_rxq.h"
  25 #include "bnxt_rxr.h"
  26 #include "bnxt_stats.h"
  27 #include "bnxt_txq.h"
  28 #include "bnxt_txr.h"
  29 #include "bnxt_vnic.h"
  30 #include "hsi_struct_def_dpdk.h"
  31 #include "bnxt_nvm_defs.h"
  32 #include "bnxt_tf_common.h"
  33 #include "ulp_flow_db.h"
  34 #include "rte_pmd_bnxt.h"
  35
  36 #define DRV_MODULE_NAME         "bnxt"
  37 static const char bnxt_version[] =
  38         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  39
  40 /*
  41  * The set of PCI devices this driver supports
  42  */
  43 static const struct rte_pci_id bnxt_pci_id_map[] = {
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  47                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
  87         { .vendor_id = 0, /* sentinel */ },
  88 };
  89
  90 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
  91 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
  92 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
  93 #define BNXT_DEVARG_REPRESENTOR "representor"
  94 #define BNXT_DEVARG_REP_BASED_PF  "rep-based-pf"
  95 #define BNXT_DEVARG_REP_IS_PF  "rep-is-pf"
  96 #define BNXT_DEVARG_REP_Q_R2F  "rep-q-r2f"
  97 #define BNXT_DEVARG_REP_Q_F2R  "rep-q-f2r"
  98 #define BNXT_DEVARG_REP_FC_R2F  "rep-fc-r2f"
  99 #define BNXT_DEVARG_REP_FC_F2R  "rep-fc-f2r"
 100
 101 static const char *const bnxt_dev_args[] = {
 102         BNXT_DEVARG_REPRESENTOR,
 103         BNXT_DEVARG_TRUFLOW,
 104         BNXT_DEVARG_FLOW_XSTAT,
 105         BNXT_DEVARG_MAX_NUM_KFLOWS,
 106         BNXT_DEVARG_REP_BASED_PF,
 107         BNXT_DEVARG_REP_IS_PF,
 108         BNXT_DEVARG_REP_Q_R2F,
 109         BNXT_DEVARG_REP_Q_F2R,
 110         BNXT_DEVARG_REP_FC_R2F,
 111         BNXT_DEVARG_REP_FC_F2R,
 112         NULL
 113 };
 114
 115 /*
 116  * truflow == false to disable the feature
 117  * truflow == true to enable the feature
 118  */
 119 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 120
 121 /*
 122  * flow_xstat == false to disable the feature
 123  * flow_xstat == true to enable the feature
 124  */
 125 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 126
 127 /*
 128  * rep_is_pf == false to indicate VF representor
 129  * rep_is_pf == true to indicate PF representor
 130  */
 131 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)        ((rep_is_pf) > 1)
 132
 133 /*
 134  * rep_based_pf == Physical index of the PF
 135  */
 136 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)  ((rep_based_pf) > 15)
 137 /*
 138  * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
 139  */
 140 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)        ((rep_q_r2f) > 3)
 141
 142 /*
 143  * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
 144  */
 145 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)        ((rep_q_f2r) > 3)
 146
 147 /*
 148  * rep_fc_r2f == Flow control for the representor to endpoint direction
 149  */
 150 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)      ((rep_fc_r2f) > 1)
 151
 152 /*
 153  * rep_fc_f2r == Flow control for the endpoint to representor direction
 154  */
 155 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)      ((rep_fc_f2r) > 1)
 156
 157 int bnxt_cfa_code_dynfield_offset = -1;
 158
 159 /*
 160  * max_num_kflows must be >= 32
 161  * and must be a power-of-2 supported value
 162  * return: 1 -> invalid
 163  *         0 -> valid
 164  */
 165 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 166 {
 167         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 168                 return 1;
 169         return 0;
 170 }
 171
 172 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 173 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 174 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 175 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 176 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 177 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 178 static void bnxt_dev_recover(void *arg);
 179 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 180 static void bnxt_free_rep_info(struct bnxt *bp);
 181
 182 int is_bnxt_in_error(struct bnxt *bp)
 183 {
 184         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 185                 return -EIO;
 186         if (bp->flags & BNXT_FLAG_FW_RESET)
 187                 return -EBUSY;
 188
 189         return 0;
 190 }
 191
 192 /***********************/
 193
 194 /*
 195  * High level utility functions
 196  */
 197
 198 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 199 {
 200         unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
 201                                              BNXT_RSS_TBL_SIZE_P5);
 202
 203         if (!BNXT_CHIP_P5(bp))
 204                 return 1;
 205
 206         return RTE_ALIGN_MUL_CEIL(num_rss_rings,
 207                                   BNXT_RSS_ENTRIES_PER_CTX_P5) /
 208                                   BNXT_RSS_ENTRIES_PER_CTX_P5;
 209 }
 210
 211 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 212 {
 213         if (!BNXT_CHIP_P5(bp))
 214                 return HW_HASH_INDEX_SIZE;
 215
 216         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
 217 }
 218
 219 static void bnxt_free_parent_info(struct bnxt *bp)
 220 {
 221         rte_free(bp->parent);
 222         bp->parent = NULL;
 223 }
 224
 225 static void bnxt_free_pf_info(struct bnxt *bp)
 226 {
 227         rte_free(bp->pf);
 228         bp->pf = NULL;
 229 }
 230
 231 static void bnxt_free_link_info(struct bnxt *bp)
 232 {
 233         rte_free(bp->link_info);
 234         bp->link_info = NULL;
 235 }
 236
 237 static void bnxt_free_leds_info(struct bnxt *bp)
 238 {
 239         if (BNXT_VF(bp))
 240                 return;
 241
 242         rte_free(bp->leds);
 243         bp->leds = NULL;
 244 }
 245
 246 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 247 {
 248         rte_free(bp->flow_stat);
 249         bp->flow_stat = NULL;
 250 }
 251
 252 static void bnxt_free_cos_queues(struct bnxt *bp)
 253 {
 254         rte_free(bp->rx_cos_queue);
 255         bp->rx_cos_queue = NULL;
 256         rte_free(bp->tx_cos_queue);
 257         bp->tx_cos_queue = NULL;
 258 }
 259
 260 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 261 {
 262         bnxt_free_filter_mem(bp);
 263         bnxt_free_vnic_attributes(bp);
 264         bnxt_free_vnic_mem(bp);
 265
 266         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 267          * If the number of rings change across fw update,
 268          * we don't have much choice except to warn the user.
 269          */
 270         if (!reconfig) {
 271                 bnxt_free_stats(bp);
 272                 bnxt_free_tx_rings(bp);
 273                 bnxt_free_rx_rings(bp);
 274         }
 275         bnxt_free_async_cp_ring(bp);
 276         bnxt_free_rxtx_nq_ring(bp);
 277
 278         rte_free(bp->grp_info);
 279         bp->grp_info = NULL;
 280 }
 281
 282 static int bnxt_alloc_parent_info(struct bnxt *bp)
 283 {
 284         bp->parent = rte_zmalloc("bnxt_parent_info",
 285                                  sizeof(struct bnxt_parent_info), 0);
 286         if (bp->parent == NULL)
 287                 return -ENOMEM;
 288
 289         return 0;
 290 }
 291
 292 static int bnxt_alloc_pf_info(struct bnxt *bp)
 293 {
 294         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 295         if (bp->pf == NULL)
 296                 return -ENOMEM;
 297
 298         return 0;
 299 }
 300
 301 static int bnxt_alloc_link_info(struct bnxt *bp)
 302 {
 303         bp->link_info =
 304                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 305         if (bp->link_info == NULL)
 306                 return -ENOMEM;
 307
 308         return 0;
 309 }
 310
 311 static int bnxt_alloc_leds_info(struct bnxt *bp)
 312 {
 313         if (BNXT_VF(bp))
 314                 return 0;
 315
 316         bp->leds = rte_zmalloc("bnxt_leds",
 317                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 318                                0);
 319         if (bp->leds == NULL)
 320                 return -ENOMEM;
 321
 322         return 0;
 323 }
 324
 325 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 326 {
 327         bp->rx_cos_queue =
 328                 rte_zmalloc("bnxt_rx_cosq",
 329                             BNXT_COS_QUEUE_COUNT *
 330                             sizeof(struct bnxt_cos_queue_info),
 331                             0);
 332         if (bp->rx_cos_queue == NULL)
 333                 return -ENOMEM;
 334
 335         bp->tx_cos_queue =
 336                 rte_zmalloc("bnxt_tx_cosq",
 337                             BNXT_COS_QUEUE_COUNT *
 338                             sizeof(struct bnxt_cos_queue_info),
 339                             0);
 340         if (bp->tx_cos_queue == NULL)
 341                 return -ENOMEM;
 342
 343         return 0;
 344 }
 345
 346 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 347 {
 348         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 349                                     sizeof(struct bnxt_flow_stat_info), 0);
 350         if (bp->flow_stat == NULL)
 351                 return -ENOMEM;
 352
 353         return 0;
 354 }
 355
 356 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 357 {
 358         int rc;
 359
 360         rc = bnxt_alloc_ring_grps(bp);
 361         if (rc)
 362                 goto alloc_mem_err;
 363
 364         rc = bnxt_alloc_async_ring_struct(bp);
 365         if (rc)
 366                 goto alloc_mem_err;
 367
 368         rc = bnxt_alloc_vnic_mem(bp);
 369         if (rc)
 370                 goto alloc_mem_err;
 371
 372         rc = bnxt_alloc_vnic_attributes(bp);
 373         if (rc)
 374                 goto alloc_mem_err;
 375
 376         rc = bnxt_alloc_filter_mem(bp);
 377         if (rc)
 378                 goto alloc_mem_err;
 379
 380         rc = bnxt_alloc_async_cp_ring(bp);
 381         if (rc)
 382                 goto alloc_mem_err;
 383
 384         rc = bnxt_alloc_rxtx_nq_ring(bp);
 385         if (rc)
 386                 goto alloc_mem_err;
 387
 388         if (BNXT_FLOW_XSTATS_EN(bp)) {
 389                 rc = bnxt_alloc_flow_stats_info(bp);
 390                 if (rc)
 391                         goto alloc_mem_err;
 392         }
 393
 394         return 0;
 395
 396 alloc_mem_err:
 397         bnxt_free_mem(bp, reconfig);
 398         return rc;
 399 }
 400
 401 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 402 {
 403         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 404         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 405         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 406         struct bnxt_rx_queue *rxq;
 407         unsigned int j;
 408         int rc;
 409
 410         rc = bnxt_vnic_grp_alloc(bp, vnic);
 411         if (rc)
 412                 goto err_out;
 413
 414         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 415                     vnic_id, vnic, vnic->fw_grp_ids);
 416
 417         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 418         if (rc)
 419                 goto err_out;
 420
 421         /* Alloc RSS context only if RSS mode is enabled */
 422         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 423                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 424
 425                 /* RSS table size in Thor is 512.
 426                  * Cap max Rx rings to same value
 427                  */
 428                 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
 429                         PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
 430                                     bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
 431                         goto err_out;
 432                 }
 433
 434                 rc = 0;
 435                 for (j = 0; j < nr_ctxs; j++) {
 436                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 437                         if (rc)
 438                                 break;
 439                 }
 440                 if (rc) {
 441                         PMD_DRV_LOG(ERR,
 442                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 443                                     vnic_id, j, rc);
 444                         goto err_out;
 445                 }
 446                 vnic->num_lb_ctxts = nr_ctxs;
 447         }
 448
 449         /*
 450          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 451          * setting is not available at this time, it will not be
 452          * configured correctly in the CFA.
 453          */
 454         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 455                 vnic->vlan_strip = true;
 456         else
 457                 vnic->vlan_strip = false;
 458
 459         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 460         if (rc)
 461                 goto err_out;
 462
 463         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 464         if (rc)
 465                 goto err_out;
 466
 467         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 468                 rxq = bp->eth_dev->data->rx_queues[j];
 469
 470                 PMD_DRV_LOG(DEBUG,
 471                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 472                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 473
 474                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 475                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 476                 else
 477                         vnic->rx_queue_cnt++;
 478         }
 479
 480         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 481
 482         rc = bnxt_vnic_rss_configure(bp, vnic);
 483         if (rc)
 484                 goto err_out;
 485
 486         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 487
 488         rc = bnxt_hwrm_vnic_tpa_cfg(bp, vnic,
 489                                     (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) ?
 490                                     true : false);
 491         if (rc)
 492                 goto err_out;
 493
 494         return 0;
 495 err_out:
 496         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 497                     vnic_id, rc);
 498         return rc;
 499 }
 500
 501 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 502 {
 503         int rc = 0;
 504
 505         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 506                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 507         if (rc)
 508                 return rc;
 509
 510         PMD_DRV_LOG(DEBUG,
 511                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 512                     " rx_fc_in_tbl.ctx_id = %d\n",
 513                     bp->flow_stat->rx_fc_in_tbl.va,
 514                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 515                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 516
 517         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 518                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 519         if (rc)
 520                 return rc;
 521
 522         PMD_DRV_LOG(DEBUG,
 523                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 524                     " rx_fc_out_tbl.ctx_id = %d\n",
 525                     bp->flow_stat->rx_fc_out_tbl.va,
 526                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 527                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 528
 529         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 530                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 531         if (rc)
 532                 return rc;
 533
 534         PMD_DRV_LOG(DEBUG,
 535                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 536                     " tx_fc_in_tbl.ctx_id = %d\n",
 537                     bp->flow_stat->tx_fc_in_tbl.va,
 538                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 539                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 540
 541         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 542                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 543         if (rc)
 544                 return rc;
 545
 546         PMD_DRV_LOG(DEBUG,
 547                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 548                     " tx_fc_out_tbl.ctx_id = %d\n",
 549                     bp->flow_stat->tx_fc_out_tbl.va,
 550                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 551                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 552
 553         memset(bp->flow_stat->rx_fc_out_tbl.va,
 554                0,
 555                bp->flow_stat->rx_fc_out_tbl.size);
 556         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 557                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 558                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 559                                        bp->flow_stat->max_fc,
 560                                        true);
 561         if (rc)
 562                 return rc;
 563
 564         memset(bp->flow_stat->tx_fc_out_tbl.va,
 565                0,
 566                bp->flow_stat->tx_fc_out_tbl.size);
 567         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 568                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 569                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 570                                        bp->flow_stat->max_fc,
 571                                        true);
 572
 573         return rc;
 574 }
 575
 576 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 577                                   struct bnxt_ctx_mem_buf_info *ctx)
 578 {
 579         if (!ctx)
 580                 return -EINVAL;
 581
 582         ctx->va = rte_zmalloc(type, size, 0);
 583         if (ctx->va == NULL)
 584                 return -ENOMEM;
 585         rte_mem_lock_page(ctx->va);
 586         ctx->size = size;
 587         ctx->dma = rte_mem_virt2iova(ctx->va);
 588         if (ctx->dma == RTE_BAD_IOVA)
 589                 return -ENOMEM;
 590
 591         return 0;
 592 }
 593
 594 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 595 {
 596         struct rte_pci_device *pdev = bp->pdev;
 597         char type[RTE_MEMZONE_NAMESIZE];
 598         uint16_t max_fc;
 599         int rc = 0;
 600
 601         max_fc = bp->flow_stat->max_fc;
 602
 603         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 604                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 605         /* 4 bytes for each counter-id */
 606         rc = bnxt_alloc_ctx_mem_buf(type,
 607                                     max_fc * 4,
 608                                     &bp->flow_stat->rx_fc_in_tbl);
 609         if (rc)
 610                 return rc;
 611
 612         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 613                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 614         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 615         rc = bnxt_alloc_ctx_mem_buf(type,
 616                                     max_fc * 16,
 617                                     &bp->flow_stat->rx_fc_out_tbl);
 618         if (rc)
 619                 return rc;
 620
 621         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 622                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 623         /* 4 bytes for each counter-id */
 624         rc = bnxt_alloc_ctx_mem_buf(type,
 625                                     max_fc * 4,
 626                                     &bp->flow_stat->tx_fc_in_tbl);
 627         if (rc)
 628                 return rc;
 629
 630         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 631                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 632         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 633         rc = bnxt_alloc_ctx_mem_buf(type,
 634                                     max_fc * 16,
 635                                     &bp->flow_stat->tx_fc_out_tbl);
 636         if (rc)
 637                 return rc;
 638
 639         rc = bnxt_register_fc_ctx_mem(bp);
 640
 641         return rc;
 642 }
 643
 644 static int bnxt_init_ctx_mem(struct bnxt *bp)
 645 {
 646         int rc = 0;
 647
 648         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 649             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 650             !BNXT_FLOW_XSTATS_EN(bp))
 651                 return 0;
 652
 653         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 654         if (rc)
 655                 return rc;
 656
 657         rc = bnxt_init_fc_ctx_mem(bp);
 658
 659         return rc;
 660 }
 661
 662 static int bnxt_update_phy_setting(struct bnxt *bp)
 663 {
 664         struct rte_eth_link new;
 665         int rc;
 666
 667         rc = bnxt_get_hwrm_link_config(bp, &new);
 668         if (rc) {
 669                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 670                 return rc;
 671         }
 672
 673         /*
 674          * On BCM957508-N2100 adapters, FW will not allow any user other
 675          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 676          * always returns link up. Force phy update always in that case.
 677          */
 678         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 679                 rc = bnxt_set_hwrm_link_config(bp, true);
 680                 if (rc) {
 681                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 682                         return rc;
 683                 }
 684         }
 685
 686         return rc;
 687 }
 688
 689 static int bnxt_start_nic(struct bnxt *bp)
 690 {
 691         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 692         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 693         uint32_t intr_vector = 0;
 694         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 695         uint32_t vec = BNXT_MISC_VEC_ID;
 696         unsigned int i, j;
 697         int rc;
 698
 699         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 700                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 701                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 702                 bp->flags |= BNXT_FLAG_JUMBO;
 703         } else {
 704                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 705                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 706                 bp->flags &= ~BNXT_FLAG_JUMBO;
 707         }
 708
 709         /* THOR does not support ring groups.
 710          * But we will use the array to save RSS context IDs.
 711          */
 712         if (BNXT_CHIP_P5(bp))
 713                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
 714
 715         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 716         if (rc) {
 717                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 718                 goto err_out;
 719         }
 720
 721         rc = bnxt_alloc_hwrm_rings(bp);
 722         if (rc) {
 723                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 724                 goto err_out;
 725         }
 726
 727         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 728         if (rc) {
 729                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 730                 goto err_out;
 731         }
 732
 733         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 734                 goto skip_cosq_cfg;
 735
 736         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 737                 if (bp->rx_cos_queue[i].id != 0xff) {
 738                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 739
 740                         if (!vnic) {
 741                                 PMD_DRV_LOG(ERR,
 742                                             "Num pools more than FW profile\n");
 743                                 rc = -EINVAL;
 744                                 goto err_out;
 745                         }
 746                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 747                         bp->rx_cosq_cnt++;
 748                 }
 749         }
 750
 751 skip_cosq_cfg:
 752         rc = bnxt_mq_rx_configure(bp);
 753         if (rc) {
 754                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 755                 goto err_out;
 756         }
 757
 758         /* default vnic 0 */
 759         rc = bnxt_setup_one_vnic(bp, 0);
 760         if (rc)
 761                 goto err_out;
 762         /* VNIC configuration */
 763         if (BNXT_RFS_NEEDS_VNIC(bp)) {
 764                 for (i = 1; i < bp->nr_vnics; i++) {
 765                         rc = bnxt_setup_one_vnic(bp, i);
 766                         if (rc)
 767                                 goto err_out;
 768                 }
 769         }
 770
 771         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 772         if (rc) {
 773                 PMD_DRV_LOG(ERR,
 774                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 775                 goto err_out;
 776         }
 777
 778         /* check and configure queue intr-vector mapping */
 779         if ((rte_intr_cap_multiple(intr_handle) ||
 780              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 781             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 782                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 783                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 784                 if (intr_vector > bp->rx_cp_nr_rings) {
 785                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 786                                         bp->rx_cp_nr_rings);
 787                         return -ENOTSUP;
 788                 }
 789                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 790                 if (rc)
 791                         return rc;
 792         }
 793
 794         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 795                 intr_handle->intr_vec =
 796                         rte_zmalloc("intr_vec",
 797                                     bp->eth_dev->data->nb_rx_queues *
 798                                     sizeof(int), 0);
 799                 if (intr_handle->intr_vec == NULL) {
 800                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 801                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 802                         rc = -ENOMEM;
 803                         goto err_out;
 804                 }
 805                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 806                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 807                          intr_handle->intr_vec, intr_handle->nb_efd,
 808                         intr_handle->max_intr);
 809                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 810                      queue_id++) {
 811                         intr_handle->intr_vec[queue_id] =
 812                                                         vec + BNXT_RX_VEC_START;
 813                         if (vec < base + intr_handle->nb_efd - 1)
 814                                 vec++;
 815                 }
 816         }
 817
 818         /* enable uio/vfio intr/eventfd mapping */
 819         rc = rte_intr_enable(intr_handle);
 820 #ifndef RTE_EXEC_ENV_FREEBSD
 821         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 822         if (rc)
 823                 goto err_out;
 824 #endif
 825
 826         rc = bnxt_update_phy_setting(bp);
 827         if (rc)
 828                 goto err_out;
 829
 830         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 831         if (!bp->mark_table)
 832                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 833
 834         return 0;
 835
 836 err_out:
 837         /* Some of the error status returned by FW may not be from errno.h */
 838         if (rc > 0)
 839                 rc = -EIO;
 840
 841         return rc;
 842 }
 843
 844 static int bnxt_shutdown_nic(struct bnxt *bp)
 845 {
 846         bnxt_free_all_hwrm_resources(bp);
 847         bnxt_free_all_filters(bp);
 848         bnxt_free_all_vnics(bp);
 849         return 0;
 850 }
 851
 852 /*
 853  * Device configuration and status function
 854  */
 855
 856 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 857 {
 858         uint32_t link_speed = 0;
 859         uint32_t speed_capa = 0;
 860
 861         if (bp->link_info == NULL)
 862                 return 0;
 863
 864         link_speed = bp->link_info->support_speeds;
 865
 866         /* If PAM4 is configured, use PAM4 supported speed */
 867         if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
 868                 link_speed = bp->link_info->support_pam4_speeds;
 869
 870         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 871                 speed_capa |= ETH_LINK_SPEED_100M;
 872         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 873                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 874         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 875                 speed_capa |= ETH_LINK_SPEED_1G;
 876         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 877                 speed_capa |= ETH_LINK_SPEED_2_5G;
 878         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 879                 speed_capa |= ETH_LINK_SPEED_10G;
 880         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 881                 speed_capa |= ETH_LINK_SPEED_20G;
 882         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 883                 speed_capa |= ETH_LINK_SPEED_25G;
 884         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 885                 speed_capa |= ETH_LINK_SPEED_40G;
 886         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 887                 speed_capa |= ETH_LINK_SPEED_50G;
 888         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 889                 speed_capa |= ETH_LINK_SPEED_100G;
 890         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
 891                 speed_capa |= ETH_LINK_SPEED_50G;
 892         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
 893                 speed_capa |= ETH_LINK_SPEED_100G;
 894         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
 895                 speed_capa |= ETH_LINK_SPEED_200G;
 896
 897         if (bp->link_info->auto_mode ==
 898             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 899                 speed_capa |= ETH_LINK_SPEED_FIXED;
 900
 901         return speed_capa;
 902 }
 903
 904 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 905                                 struct rte_eth_dev_info *dev_info)
 906 {
 907         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 908         struct bnxt *bp = eth_dev->data->dev_private;
 909         uint16_t max_vnics, i, j, vpool, vrxq;
 910         unsigned int max_rx_rings;
 911         int rc;
 912
 913         rc = is_bnxt_in_error(bp);
 914         if (rc)
 915                 return rc;
 916
 917         /* MAC Specifics */
 918         dev_info->max_mac_addrs = bp->max_l2_ctx;
 919         dev_info->max_hash_mac_addrs = 0;
 920
 921         /* PF/VF specifics */
 922         if (BNXT_PF(bp))
 923                 dev_info->max_vfs = pdev->max_vfs;
 924
 925         max_rx_rings = bnxt_max_rings(bp);
 926         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 927         dev_info->max_rx_queues = max_rx_rings;
 928         dev_info->max_tx_queues = max_rx_rings;
 929         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 930         dev_info->hash_key_size = 40;
 931         max_vnics = bp->max_vnics;
 932
 933         /* MTU specifics */
 934         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 935         dev_info->max_mtu = BNXT_MAX_MTU;
 936
 937         /* Fast path specifics */
 938         dev_info->min_rx_bufsize = 1;
 939         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 940
 941         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 942         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 943                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 944         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 945         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
 946                                     dev_info->tx_queue_offload_capa;
 947         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 948
 949         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 950
 951         /* *INDENT-OFF* */
 952         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 953                 .rx_thresh = {
 954                         .pthresh = 8,
 955                         .hthresh = 8,
 956                         .wthresh = 0,
 957                 },
 958                 .rx_free_thresh = 32,
 959                 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
 960         };
 961
 962         dev_info->default_txconf = (struct rte_eth_txconf) {
 963                 .tx_thresh = {
 964                         .pthresh = 32,
 965                         .hthresh = 0,
 966                         .wthresh = 0,
 967                 },
 968                 .tx_free_thresh = 32,
 969                 .tx_rs_thresh = 32,
 970         };
 971         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 972
 973         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 974         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 975         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 976         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 977         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 978
 979         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
 980                 dev_info->switch_info.name = eth_dev->device->name;
 981                 dev_info->switch_info.domain_id = bp->switch_domain_id;
 982                 dev_info->switch_info.port_id =
 983                                 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
 984                                     BNXT_SWITCH_PORT_ID_TRUSTED_VF;
 985         }
 986
 987         /* *INDENT-ON* */
 988
 989         /*
 990          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 991          *       need further investigation.
 992          */
 993
 994         /* VMDq resources */
 995         vpool = 64; /* ETH_64_POOLS */
 996         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 997         for (i = 0; i < 4; vpool >>= 1, i++) {
 998                 if (max_vnics > vpool) {
 999                         for (j = 0; j < 5; vrxq >>= 1, j++) {
1000                                 if (dev_info->max_rx_queues > vrxq) {
1001                                         if (vpool > vrxq)
1002                                                 vpool = vrxq;
1003                                         goto found;
1004                                 }
1005                         }
1006                         /* Not enough resources to support VMDq */
1007                         break;
1008                 }
1009         }
1010         /* Not enough resources to support VMDq */
1011         vpool = 0;
1012         vrxq = 0;
1013 found:
1014         dev_info->max_vmdq_pools = vpool;
1015         dev_info->vmdq_queue_num = vrxq;
1016
1017         dev_info->vmdq_pool_base = 0;
1018         dev_info->vmdq_queue_base = 0;
1019
1020         return 0;
1021 }
1022
1023 /* Configure the device based on the configuration provided */
1024 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1025 {
1026         struct bnxt *bp = eth_dev->data->dev_private;
1027         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1028         int rc;
1029
1030         bp->rx_queues = (void *)eth_dev->data->rx_queues;
1031         bp->tx_queues = (void *)eth_dev->data->tx_queues;
1032         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1033         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1034
1035         rc = is_bnxt_in_error(bp);
1036         if (rc)
1037                 return rc;
1038
1039         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1040                 rc = bnxt_hwrm_check_vf_rings(bp);
1041                 if (rc) {
1042                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1043                         return -ENOSPC;
1044                 }
1045
1046                 /* If a resource has already been allocated - in this case
1047                  * it is the async completion ring, free it. Reallocate it after
1048                  * resource reservation. This will ensure the resource counts
1049                  * are calculated correctly.
1050                  */
1051
1052                 pthread_mutex_lock(&bp->def_cp_lock);
1053
1054                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1055                         bnxt_disable_int(bp);
1056                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
1057                 }
1058
1059                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1060                 if (rc) {
1061                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1062                         pthread_mutex_unlock(&bp->def_cp_lock);
1063                         return -ENOSPC;
1064                 }
1065
1066                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1067                         rc = bnxt_alloc_async_cp_ring(bp);
1068                         if (rc) {
1069                                 pthread_mutex_unlock(&bp->def_cp_lock);
1070                                 return rc;
1071                         }
1072                         bnxt_enable_int(bp);
1073                 }
1074
1075                 pthread_mutex_unlock(&bp->def_cp_lock);
1076         }
1077
1078         /* Inherit new configurations */
1079         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1080             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1081             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1082                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1083             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1084             bp->max_stat_ctx)
1085                 goto resource_error;
1086
1087         if (BNXT_HAS_RING_GRPS(bp) &&
1088             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1089                 goto resource_error;
1090
1091         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1092             bp->max_vnics < eth_dev->data->nb_rx_queues)
1093                 goto resource_error;
1094
1095         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1096         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1097
1098         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1099                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1100         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1101
1102         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1103                 eth_dev->data->mtu =
1104                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1105                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1106                         BNXT_NUM_VLANS;
1107                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1108         }
1109         return 0;
1110
1111 resource_error:
1112         PMD_DRV_LOG(ERR,
1113                     "Insufficient resources to support requested config\n");
1114         PMD_DRV_LOG(ERR,
1115                     "Num Queues Requested: Tx %d, Rx %d\n",
1116                     eth_dev->data->nb_tx_queues,
1117                     eth_dev->data->nb_rx_queues);
1118         PMD_DRV_LOG(ERR,
1119                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1120                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1121                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1122         return -ENOSPC;
1123 }
1124
1125 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1126 {
1127         struct rte_eth_link *link = &eth_dev->data->dev_link;
1128
1129         if (link->link_status)
1130                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1131                         eth_dev->data->port_id,
1132                         (uint32_t)link->link_speed,
1133                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1134                         ("full-duplex") : ("half-duplex\n"));
1135         else
1136                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1137                         eth_dev->data->port_id);
1138 }
1139
1140 /*
1141  * Determine whether the current configuration requires support for scattered
1142  * receive; return 1 if scattered receive is required and 0 if not.
1143  */
1144 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1145 {
1146         uint16_t buf_size;
1147         int i;
1148
1149         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1150                 return 1;
1151
1152         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO)
1153                 return 1;
1154
1155         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1156                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1157
1158                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1159                                       RTE_PKTMBUF_HEADROOM);
1160                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1161                         return 1;
1162         }
1163         return 0;
1164 }
1165
1166 static eth_rx_burst_t
1167 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1168 {
1169         struct bnxt *bp = eth_dev->data->dev_private;
1170
1171         /* Disable vector mode RX for Stingray2 for now */
1172         if (BNXT_CHIP_SR2(bp)) {
1173                 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1174                 return bnxt_recv_pkts;
1175         }
1176
1177 #if (defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)) && \
1178         !defined(RTE_LIBRTE_IEEE1588)
1179
1180         /* Vector mode receive cannot be enabled if scattered rx is in use. */
1181         if (eth_dev->data->scattered_rx)
1182                 goto use_scalar_rx;
1183
1184         /*
1185          * Vector mode receive cannot be enabled if Truflow is enabled or if
1186          * asynchronous completions and receive completions can be placed in
1187          * the same completion ring.
1188          */
1189         if (BNXT_TRUFLOW_EN(bp) || !BNXT_NUM_ASYNC_CPR(bp))
1190                 goto use_scalar_rx;
1191
1192         /*
1193          * Vector mode receive cannot be enabled if any receive offloads outside
1194          * a limited subset have been enabled.
1195          */
1196         if (eth_dev->data->dev_conf.rxmode.offloads &
1197                 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1198                   DEV_RX_OFFLOAD_KEEP_CRC |
1199                   DEV_RX_OFFLOAD_JUMBO_FRAME |
1200                   DEV_RX_OFFLOAD_IPV4_CKSUM |
1201                   DEV_RX_OFFLOAD_UDP_CKSUM |
1202                   DEV_RX_OFFLOAD_TCP_CKSUM |
1203                   DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1204                   DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1205                   DEV_RX_OFFLOAD_RSS_HASH |
1206                   DEV_RX_OFFLOAD_VLAN_FILTER))
1207                 goto use_scalar_rx;
1208
1209 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1210         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1211             rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1212                 PMD_DRV_LOG(INFO,
1213                             "Using AVX2 vector mode receive for port %d\n",
1214                             eth_dev->data->port_id);
1215                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1216                 return bnxt_recv_pkts_vec_avx2;
1217         }
1218  #endif
1219         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1220                 PMD_DRV_LOG(INFO,
1221                             "Using SSE vector mode receive for port %d\n",
1222                             eth_dev->data->port_id);
1223                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1224                 return bnxt_recv_pkts_vec;
1225         }
1226
1227 use_scalar_rx:
1228         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1229                     eth_dev->data->port_id);
1230         PMD_DRV_LOG(INFO,
1231                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1232                     eth_dev->data->port_id,
1233                     eth_dev->data->scattered_rx,
1234                     eth_dev->data->dev_conf.rxmode.offloads);
1235 #endif
1236         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1237         return bnxt_recv_pkts;
1238 }
1239
1240 static eth_tx_burst_t
1241 bnxt_transmit_function(struct rte_eth_dev *eth_dev)
1242 {
1243         struct bnxt *bp = eth_dev->data->dev_private;
1244
1245         /* Disable vector mode TX for Stingray2 for now */
1246         if (BNXT_CHIP_SR2(bp))
1247                 return bnxt_xmit_pkts;
1248
1249 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) && \
1250         !defined(RTE_LIBRTE_IEEE1588)
1251         uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1252
1253         /*
1254          * Vector mode transmit can be enabled only if not using scatter rx
1255          * or tx offloads.
1256          */
1257         if (eth_dev->data->scattered_rx ||
1258             (offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) ||
1259             BNXT_TRUFLOW_EN(bp))
1260                 goto use_scalar_tx;
1261
1262 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1263         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1264             rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1265                 PMD_DRV_LOG(INFO,
1266                             "Using AVX2 vector mode transmit for port %d\n",
1267                             eth_dev->data->port_id);
1268                 return bnxt_xmit_pkts_vec_avx2;
1269         }
1270 #endif
1271         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1272                 PMD_DRV_LOG(INFO,
1273                             "Using SSE vector mode transmit for port %d\n",
1274                             eth_dev->data->port_id);
1275                 return bnxt_xmit_pkts_vec;
1276         }
1277
1278 use_scalar_tx:
1279         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1280                     eth_dev->data->port_id);
1281         PMD_DRV_LOG(INFO,
1282                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1283                     eth_dev->data->port_id,
1284                     eth_dev->data->scattered_rx,
1285                     offloads);
1286 #endif
1287         return bnxt_xmit_pkts;
1288 }
1289
1290 static int bnxt_handle_if_change_status(struct bnxt *bp)
1291 {
1292         int rc;
1293
1294         /* Since fw has undergone a reset and lost all contexts,
1295          * set fatal flag to not issue hwrm during cleanup
1296          */
1297         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1298         bnxt_uninit_resources(bp, true);
1299
1300         /* clear fatal flag so that re-init happens */
1301         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1302         rc = bnxt_init_resources(bp, true);
1303
1304         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1305
1306         return rc;
1307 }
1308
1309 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1310 {
1311         struct bnxt *bp = eth_dev->data->dev_private;
1312         int rc = 0;
1313
1314         if (!BNXT_SINGLE_PF(bp))
1315                 return -ENOTSUP;
1316
1317         if (!bp->link_info->link_up)
1318                 rc = bnxt_set_hwrm_link_config(bp, true);
1319         if (!rc)
1320                 eth_dev->data->dev_link.link_status = 1;
1321
1322         bnxt_print_link_info(eth_dev);
1323         return rc;
1324 }
1325
1326 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1327 {
1328         struct bnxt *bp = eth_dev->data->dev_private;
1329
1330         if (!BNXT_SINGLE_PF(bp))
1331                 return -ENOTSUP;
1332
1333         eth_dev->data->dev_link.link_status = 0;
1334         bnxt_set_hwrm_link_config(bp, false);
1335         bp->link_info->link_up = 0;
1336
1337         return 0;
1338 }
1339
1340 static void bnxt_free_switch_domain(struct bnxt *bp)
1341 {
1342         int rc = 0;
1343
1344         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)))
1345                 return;
1346
1347         rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1348         if (rc)
1349                 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1350                             bp->switch_domain_id, rc);
1351 }
1352
1353 static void bnxt_ptp_get_current_time(void *arg)
1354 {
1355         struct bnxt *bp = arg;
1356         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1357         int rc;
1358
1359         rc = is_bnxt_in_error(bp);
1360         if (rc)
1361                 return;
1362
1363         if (!ptp)
1364                 return;
1365
1366         bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1367                                 &ptp->current_time);
1368
1369         rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1370         if (rc != 0) {
1371                 PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n");
1372                 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1373         }
1374 }
1375
1376 static int bnxt_schedule_ptp_alarm(struct bnxt *bp)
1377 {
1378         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1379         int rc;
1380
1381         if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED)
1382                 return 0;
1383
1384         bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1385                                 &ptp->current_time);
1386
1387         rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1388         return rc;
1389 }
1390
1391 static void bnxt_cancel_ptp_alarm(struct bnxt *bp)
1392 {
1393         if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) {
1394                 rte_eal_alarm_cancel(bnxt_ptp_get_current_time, (void *)bp);
1395                 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1396         }
1397 }
1398
1399 static void bnxt_ptp_stop(struct bnxt *bp)
1400 {
1401         bnxt_cancel_ptp_alarm(bp);
1402         bp->flags2 &= ~BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1403 }
1404
1405 static int bnxt_ptp_start(struct bnxt *bp)
1406 {
1407         int rc;
1408
1409         rc = bnxt_schedule_ptp_alarm(bp);
1410         if (rc != 0) {
1411                 PMD_DRV_LOG(ERR, "Failed to schedule PTP alarm\n");
1412         } else {
1413                 bp->flags2 |= BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1414                 bp->flags2 |= BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1415         }
1416
1417         return rc;
1418 }
1419
1420 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev)
1421 {
1422         struct bnxt *bp = eth_dev->data->dev_private;
1423         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1424         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1425         struct rte_eth_link link;
1426         int ret;
1427
1428         eth_dev->data->dev_started = 0;
1429         eth_dev->data->scattered_rx = 0;
1430
1431         /* Prevent crashes when queues are still in use */
1432         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1433         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1434
1435         bnxt_disable_int(bp);
1436
1437         /* disable uio/vfio intr/eventfd mapping */
1438         rte_intr_disable(intr_handle);
1439
1440         /* Stop the child representors for this device */
1441         ret = bnxt_rep_stop_all(bp);
1442         if (ret != 0)
1443                 return ret;
1444
1445         /* delete the bnxt ULP port details */
1446         bnxt_ulp_port_deinit(bp);
1447
1448         bnxt_cancel_fw_health_check(bp);
1449
1450         if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1451                 bnxt_cancel_ptp_alarm(bp);
1452
1453         /* Do not bring link down during reset recovery */
1454         if (!is_bnxt_in_error(bp)) {
1455                 bnxt_dev_set_link_down_op(eth_dev);
1456                 /* Wait for link to be reset */
1457                 if (BNXT_SINGLE_PF(bp))
1458                         rte_delay_ms(500);
1459                 /* clear the recorded link status */
1460                 memset(&link, 0, sizeof(link));
1461                 rte_eth_linkstatus_set(eth_dev, &link);
1462         }
1463
1464         /* Clean queue intr-vector mapping */
1465         rte_intr_efd_disable(intr_handle);
1466         if (intr_handle->intr_vec != NULL) {
1467                 rte_free(intr_handle->intr_vec);
1468                 intr_handle->intr_vec = NULL;
1469         }
1470
1471         bnxt_hwrm_port_clr_stats(bp);
1472         bnxt_free_tx_mbufs(bp);
1473         bnxt_free_rx_mbufs(bp);
1474         /* Process any remaining notifications in default completion queue */
1475         bnxt_int_handler(eth_dev);
1476         bnxt_shutdown_nic(bp);
1477         bnxt_hwrm_if_change(bp, false);
1478
1479         rte_free(bp->mark_table);
1480         bp->mark_table = NULL;
1481
1482         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1483         bp->rx_cosq_cnt = 0;
1484         /* All filters are deleted on a port stop. */
1485         if (BNXT_FLOW_XSTATS_EN(bp))
1486                 bp->flow_stat->flow_count = 0;
1487
1488         return 0;
1489 }
1490
1491 /* Unload the driver, release resources */
1492 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1493 {
1494         struct bnxt *bp = eth_dev->data->dev_private;
1495
1496         pthread_mutex_lock(&bp->err_recovery_lock);
1497         if (bp->flags & BNXT_FLAG_FW_RESET) {
1498                 PMD_DRV_LOG(ERR,
1499                             "Adapter recovering from error..Please retry\n");
1500                 pthread_mutex_unlock(&bp->err_recovery_lock);
1501                 return -EAGAIN;
1502         }
1503         pthread_mutex_unlock(&bp->err_recovery_lock);
1504
1505         return bnxt_dev_stop(eth_dev);
1506 }
1507
1508 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1509 {
1510         struct bnxt *bp = eth_dev->data->dev_private;
1511         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1512         int vlan_mask = 0;
1513         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1514
1515         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1516                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1517                 return -EINVAL;
1518         }
1519
1520         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1521                 PMD_DRV_LOG(ERR,
1522                             "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1523                             bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1524
1525         do {
1526                 rc = bnxt_hwrm_if_change(bp, true);
1527                 if (rc == 0 || rc != -EAGAIN)
1528                         break;
1529
1530                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1531         } while (retry_cnt--);
1532
1533         if (rc)
1534                 return rc;
1535
1536         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1537                 rc = bnxt_handle_if_change_status(bp);
1538                 if (rc)
1539                         return rc;
1540         }
1541
1542         bnxt_enable_int(bp);
1543
1544         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1545
1546         rc = bnxt_start_nic(bp);
1547         if (rc)
1548                 goto error;
1549
1550         eth_dev->data->dev_started = 1;
1551
1552         bnxt_link_update_op(eth_dev, 1);
1553
1554         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1555                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1556         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1557                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1558         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1559         if (rc)
1560                 goto error;
1561
1562         /* Initialize bnxt ULP port details */
1563         rc = bnxt_ulp_port_init(bp);
1564         if (rc)
1565                 goto error;
1566
1567         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1568         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1569
1570         bnxt_schedule_fw_health_check(bp);
1571
1572         if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1573                 bnxt_schedule_ptp_alarm(bp);
1574
1575         return 0;
1576
1577 error:
1578         bnxt_dev_stop(eth_dev);
1579         return rc;
1580 }
1581
1582 static void
1583 bnxt_uninit_locks(struct bnxt *bp)
1584 {
1585         pthread_mutex_destroy(&bp->flow_lock);
1586         pthread_mutex_destroy(&bp->def_cp_lock);
1587         pthread_mutex_destroy(&bp->health_check_lock);
1588         pthread_mutex_destroy(&bp->err_recovery_lock);
1589         if (bp->rep_info) {
1590                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
1591                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
1592         }
1593 }
1594
1595 static void bnxt_drv_uninit(struct bnxt *bp)
1596 {
1597         bnxt_free_leds_info(bp);
1598         bnxt_free_cos_queues(bp);
1599         bnxt_free_link_info(bp);
1600         bnxt_free_parent_info(bp);
1601         bnxt_uninit_locks(bp);
1602
1603         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1604         bp->tx_mem_zone = NULL;
1605         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1606         bp->rx_mem_zone = NULL;
1607
1608         bnxt_free_vf_info(bp);
1609         bnxt_free_pf_info(bp);
1610
1611         rte_free(bp->grp_info);
1612         bp->grp_info = NULL;
1613 }
1614
1615 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1616 {
1617         struct bnxt *bp = eth_dev->data->dev_private;
1618         int ret = 0;
1619
1620         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1621                 return 0;
1622
1623         pthread_mutex_lock(&bp->err_recovery_lock);
1624         if (bp->flags & BNXT_FLAG_FW_RESET) {
1625                 PMD_DRV_LOG(ERR,
1626                             "Adapter recovering from error...Please retry\n");
1627                 pthread_mutex_unlock(&bp->err_recovery_lock);
1628                 return -EAGAIN;
1629         }
1630         pthread_mutex_unlock(&bp->err_recovery_lock);
1631
1632         /* cancel the recovery handler before remove dev */
1633         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1634         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1635         bnxt_cancel_fc_thread(bp);
1636
1637         if (eth_dev->data->dev_started)
1638                 ret = bnxt_dev_stop(eth_dev);
1639
1640         bnxt_uninit_resources(bp, false);
1641
1642         bnxt_drv_uninit(bp);
1643
1644         return ret;
1645 }
1646
1647 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1648                                     uint32_t index)
1649 {
1650         struct bnxt *bp = eth_dev->data->dev_private;
1651         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1652         struct bnxt_vnic_info *vnic;
1653         struct bnxt_filter_info *filter, *temp_filter;
1654         uint32_t i;
1655
1656         if (is_bnxt_in_error(bp))
1657                 return;
1658
1659         /*
1660          * Loop through all VNICs from the specified filter flow pools to
1661          * remove the corresponding MAC addr filter
1662          */
1663         for (i = 0; i < bp->nr_vnics; i++) {
1664                 if (!(pool_mask & (1ULL << i)))
1665                         continue;
1666
1667                 vnic = &bp->vnic_info[i];
1668                 filter = STAILQ_FIRST(&vnic->filter);
1669                 while (filter) {
1670                         temp_filter = STAILQ_NEXT(filter, next);
1671                         if (filter->mac_index == index) {
1672                                 STAILQ_REMOVE(&vnic->filter, filter,
1673                                                 bnxt_filter_info, next);
1674                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1675                                 bnxt_free_filter(bp, filter);
1676                         }
1677                         filter = temp_filter;
1678                 }
1679         }
1680 }
1681
1682 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1683                                struct rte_ether_addr *mac_addr, uint32_t index,
1684                                uint32_t pool)
1685 {
1686         struct bnxt_filter_info *filter;
1687         int rc = 0;
1688
1689         /* Attach requested MAC address to the new l2_filter */
1690         STAILQ_FOREACH(filter, &vnic->filter, next) {
1691                 if (filter->mac_index == index) {
1692                         PMD_DRV_LOG(DEBUG,
1693                                     "MAC addr already existed for pool %d\n",
1694                                     pool);
1695                         return 0;
1696                 }
1697         }
1698
1699         filter = bnxt_alloc_filter(bp);
1700         if (!filter) {
1701                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1702                 return -ENODEV;
1703         }
1704
1705         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1706          * if the MAC that's been programmed now is a different one, then,
1707          * copy that addr to filter->l2_addr
1708          */
1709         if (mac_addr)
1710                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1711         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1712
1713         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1714         if (!rc) {
1715                 filter->mac_index = index;
1716                 if (filter->mac_index == 0)
1717                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1718                 else
1719                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1720         } else {
1721                 bnxt_free_filter(bp, filter);
1722         }
1723
1724         return rc;
1725 }
1726
1727 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1728                                 struct rte_ether_addr *mac_addr,
1729                                 uint32_t index, uint32_t pool)
1730 {
1731         struct bnxt *bp = eth_dev->data->dev_private;
1732         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1733         int rc = 0;
1734
1735         rc = is_bnxt_in_error(bp);
1736         if (rc)
1737                 return rc;
1738
1739         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1740                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1741                 return -ENOTSUP;
1742         }
1743
1744         if (!vnic) {
1745                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1746                 return -EINVAL;
1747         }
1748
1749         /* Filter settings will get applied when port is started */
1750         if (!eth_dev->data->dev_started)
1751                 return 0;
1752
1753         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1754
1755         return rc;
1756 }
1757
1758 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1759 {
1760         int rc = 0;
1761         struct bnxt *bp = eth_dev->data->dev_private;
1762         struct rte_eth_link new;
1763         int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1764                         BNXT_MIN_LINK_WAIT_CNT;
1765
1766         rc = is_bnxt_in_error(bp);
1767         if (rc)
1768                 return rc;
1769
1770         memset(&new, 0, sizeof(new));
1771
1772         if (bp->link_info == NULL)
1773                 goto out;
1774
1775         do {
1776                 /* Retrieve link info from hardware */
1777                 rc = bnxt_get_hwrm_link_config(bp, &new);
1778                 if (rc) {
1779                         new.link_speed = ETH_LINK_SPEED_100M;
1780                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1781                         PMD_DRV_LOG(ERR,
1782                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1783                         goto out;
1784                 }
1785
1786                 if (!wait_to_complete || new.link_status)
1787                         break;
1788
1789                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1790         } while (cnt--);
1791
1792         /* Only single function PF can bring phy down.
1793          * When port is stopped, report link down for VF/MH/NPAR functions.
1794          */
1795         if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1796                 memset(&new, 0, sizeof(new));
1797
1798 out:
1799         /* Timed out or success */
1800         if (new.link_status != eth_dev->data->dev_link.link_status ||
1801             new.link_speed != eth_dev->data->dev_link.link_speed) {
1802                 rte_eth_linkstatus_set(eth_dev, &new);
1803
1804                 rte_eth_dev_callback_process(eth_dev,
1805                                              RTE_ETH_EVENT_INTR_LSC,
1806                                              NULL);
1807
1808                 bnxt_print_link_info(eth_dev);
1809         }
1810
1811         return rc;
1812 }
1813
1814 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1815 {
1816         struct bnxt *bp = eth_dev->data->dev_private;
1817         struct bnxt_vnic_info *vnic;
1818         uint32_t old_flags;
1819         int rc;
1820
1821         rc = is_bnxt_in_error(bp);
1822         if (rc)
1823                 return rc;
1824
1825         /* Filter settings will get applied when port is started */
1826         if (!eth_dev->data->dev_started)
1827                 return 0;
1828
1829         if (bp->vnic_info == NULL)
1830                 return 0;
1831
1832         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1833
1834         old_flags = vnic->flags;
1835         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1836         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1837         if (rc != 0)
1838                 vnic->flags = old_flags;
1839
1840         return rc;
1841 }
1842
1843 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1844 {
1845         struct bnxt *bp = eth_dev->data->dev_private;
1846         struct bnxt_vnic_info *vnic;
1847         uint32_t old_flags;
1848         int rc;
1849
1850         rc = is_bnxt_in_error(bp);
1851         if (rc)
1852                 return rc;
1853
1854         /* Filter settings will get applied when port is started */
1855         if (!eth_dev->data->dev_started)
1856                 return 0;
1857
1858         if (bp->vnic_info == NULL)
1859                 return 0;
1860
1861         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1862
1863         old_flags = vnic->flags;
1864         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1865         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1866         if (rc != 0)
1867                 vnic->flags = old_flags;
1868
1869         return rc;
1870 }
1871
1872 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1873 {
1874         struct bnxt *bp = eth_dev->data->dev_private;
1875         struct bnxt_vnic_info *vnic;
1876         uint32_t old_flags;
1877         int rc;
1878
1879         rc = is_bnxt_in_error(bp);
1880         if (rc)
1881                 return rc;
1882
1883         /* Filter settings will get applied when port is started */
1884         if (!eth_dev->data->dev_started)
1885                 return 0;
1886
1887         if (bp->vnic_info == NULL)
1888                 return 0;
1889
1890         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1891
1892         old_flags = vnic->flags;
1893         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1894         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1895         if (rc != 0)
1896                 vnic->flags = old_flags;
1897
1898         return rc;
1899 }
1900
1901 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1902 {
1903         struct bnxt *bp = eth_dev->data->dev_private;
1904         struct bnxt_vnic_info *vnic;
1905         uint32_t old_flags;
1906         int rc;
1907
1908         rc = is_bnxt_in_error(bp);
1909         if (rc)
1910                 return rc;
1911
1912         /* Filter settings will get applied when port is started */
1913         if (!eth_dev->data->dev_started)
1914                 return 0;
1915
1916         if (bp->vnic_info == NULL)
1917                 return 0;
1918
1919         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1920
1921         old_flags = vnic->flags;
1922         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1923         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1924         if (rc != 0)
1925                 vnic->flags = old_flags;
1926
1927         return rc;
1928 }
1929
1930 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1931 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1932 {
1933         if (qid >= bp->rx_nr_rings)
1934                 return NULL;
1935
1936         return bp->eth_dev->data->rx_queues[qid];
1937 }
1938
1939 /* Return rxq corresponding to a given rss table ring/group ID. */
1940 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1941 {
1942         struct bnxt_rx_queue *rxq;
1943         unsigned int i;
1944
1945         if (!BNXT_HAS_RING_GRPS(bp)) {
1946                 for (i = 0; i < bp->rx_nr_rings; i++) {
1947                         rxq = bp->eth_dev->data->rx_queues[i];
1948                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1949                                 return rxq->index;
1950                 }
1951         } else {
1952                 for (i = 0; i < bp->rx_nr_rings; i++) {
1953                         if (bp->grp_info[i].fw_grp_id == fwr)
1954                                 return i;
1955                 }
1956         }
1957
1958         return INVALID_HW_RING_ID;
1959 }
1960
1961 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1962                             struct rte_eth_rss_reta_entry64 *reta_conf,
1963                             uint16_t reta_size)
1964 {
1965         struct bnxt *bp = eth_dev->data->dev_private;
1966         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1967         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1968         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1969         uint16_t idx, sft;
1970         int i, rc;
1971
1972         rc = is_bnxt_in_error(bp);
1973         if (rc)
1974                 return rc;
1975
1976         if (!vnic->rss_table)
1977                 return -EINVAL;
1978
1979         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1980                 return -EINVAL;
1981
1982         if (reta_size != tbl_size) {
1983                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1984                         "(%d) must equal the size supported by the hardware "
1985                         "(%d)\n", reta_size, tbl_size);
1986                 return -EINVAL;
1987         }
1988
1989         for (i = 0; i < reta_size; i++) {
1990                 struct bnxt_rx_queue *rxq;
1991
1992                 idx = i / RTE_RETA_GROUP_SIZE;
1993                 sft = i % RTE_RETA_GROUP_SIZE;
1994
1995                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1996                         continue;
1997
1998                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1999                 if (!rxq) {
2000                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
2001                         return -EINVAL;
2002                 }
2003
2004                 if (BNXT_CHIP_P5(bp)) {
2005                         vnic->rss_table[i * 2] =
2006                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
2007                         vnic->rss_table[i * 2 + 1] =
2008                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
2009                 } else {
2010                         vnic->rss_table[i] =
2011                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
2012                 }
2013         }
2014
2015         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2016         return rc;
2017 }
2018
2019 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
2020                               struct rte_eth_rss_reta_entry64 *reta_conf,
2021                               uint16_t reta_size)
2022 {
2023         struct bnxt *bp = eth_dev->data->dev_private;
2024         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2025         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
2026         uint16_t idx, sft, i;
2027         int rc;
2028
2029         rc = is_bnxt_in_error(bp);
2030         if (rc)
2031                 return rc;
2032
2033         /* Retrieve from the default VNIC */
2034         if (!vnic)
2035                 return -EINVAL;
2036         if (!vnic->rss_table)
2037                 return -EINVAL;
2038
2039         if (reta_size != tbl_size) {
2040                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2041                         "(%d) must equal the size supported by the hardware "
2042                         "(%d)\n", reta_size, tbl_size);
2043                 return -EINVAL;
2044         }
2045
2046         for (idx = 0, i = 0; i < reta_size; i++) {
2047                 idx = i / RTE_RETA_GROUP_SIZE;
2048                 sft = i % RTE_RETA_GROUP_SIZE;
2049
2050                 if (reta_conf[idx].mask & (1ULL << sft)) {
2051                         uint16_t qid;
2052
2053                         if (BNXT_CHIP_P5(bp))
2054                                 qid = bnxt_rss_to_qid(bp,
2055                                                       vnic->rss_table[i * 2]);
2056                         else
2057                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
2058
2059                         if (qid == INVALID_HW_RING_ID) {
2060                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
2061                                 return -EINVAL;
2062                         }
2063                         reta_conf[idx].reta[sft] = qid;
2064                 }
2065         }
2066
2067         return 0;
2068 }
2069
2070 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
2071                                    struct rte_eth_rss_conf *rss_conf)
2072 {
2073         struct bnxt *bp = eth_dev->data->dev_private;
2074         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2075         struct bnxt_vnic_info *vnic;
2076         int rc;
2077
2078         rc = is_bnxt_in_error(bp);
2079         if (rc)
2080                 return rc;
2081
2082         /*
2083          * If RSS enablement were different than dev_configure,
2084          * then return -EINVAL
2085          */
2086         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
2087                 if (!rss_conf->rss_hf)
2088                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
2089         } else {
2090                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
2091                         return -EINVAL;
2092         }
2093
2094         bp->flags |= BNXT_FLAG_UPDATE_HASH;
2095         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
2096                rss_conf,
2097                sizeof(*rss_conf));
2098
2099         /* Update the default RSS VNIC(s) */
2100         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2101         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
2102         vnic->hash_mode =
2103                 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
2104                                             ETH_RSS_LEVEL(rss_conf->rss_hf));
2105
2106         /*
2107          * If hashkey is not specified, use the previously configured
2108          * hashkey
2109          */
2110         if (!rss_conf->rss_key)
2111                 goto rss_config;
2112
2113         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
2114                 PMD_DRV_LOG(ERR,
2115                             "Invalid hashkey length, should be 16 bytes\n");
2116                 return -EINVAL;
2117         }
2118         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
2119
2120 rss_config:
2121         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2122         return rc;
2123 }
2124
2125 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
2126                                      struct rte_eth_rss_conf *rss_conf)
2127 {
2128         struct bnxt *bp = eth_dev->data->dev_private;
2129         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2130         int len, rc;
2131         uint32_t hash_types;
2132
2133         rc = is_bnxt_in_error(bp);
2134         if (rc)
2135                 return rc;
2136
2137         /* RSS configuration is the same for all VNICs */
2138         if (vnic && vnic->rss_hash_key) {
2139                 if (rss_conf->rss_key) {
2140                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
2141                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
2142                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
2143                 }
2144
2145                 hash_types = vnic->hash_type;
2146                 rss_conf->rss_hf = 0;
2147                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
2148                         rss_conf->rss_hf |= ETH_RSS_IPV4;
2149                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
2150                 }
2151                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
2152                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2153                         hash_types &=
2154                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
2155                 }
2156                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
2157                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2158                         hash_types &=
2159                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
2160                 }
2161                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
2162                         rss_conf->rss_hf |= ETH_RSS_IPV6;
2163                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
2164                 }
2165                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
2166                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2167                         hash_types &=
2168                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
2169                 }
2170                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
2171                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2172                         hash_types &=
2173                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2174                 }
2175
2176                 rss_conf->rss_hf |=
2177                         bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2178
2179                 if (hash_types) {
2180                         PMD_DRV_LOG(ERR,
2181                                 "Unknown RSS config from firmware (%08x), RSS disabled",
2182                                 vnic->hash_type);
2183                         return -ENOTSUP;
2184                 }
2185         } else {
2186                 rss_conf->rss_hf = 0;
2187         }
2188         return 0;
2189 }
2190
2191 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2192                                struct rte_eth_fc_conf *fc_conf)
2193 {
2194         struct bnxt *bp = dev->data->dev_private;
2195         struct rte_eth_link link_info;
2196         int rc;
2197
2198         rc = is_bnxt_in_error(bp);
2199         if (rc)
2200                 return rc;
2201
2202         rc = bnxt_get_hwrm_link_config(bp, &link_info);
2203         if (rc)
2204                 return rc;
2205
2206         memset(fc_conf, 0, sizeof(*fc_conf));
2207         if (bp->link_info->auto_pause)
2208                 fc_conf->autoneg = 1;
2209         switch (bp->link_info->pause) {
2210         case 0:
2211                 fc_conf->mode = RTE_FC_NONE;
2212                 break;
2213         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2214                 fc_conf->mode = RTE_FC_TX_PAUSE;
2215                 break;
2216         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2217                 fc_conf->mode = RTE_FC_RX_PAUSE;
2218                 break;
2219         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2220                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2221                 fc_conf->mode = RTE_FC_FULL;
2222                 break;
2223         }
2224         return 0;
2225 }
2226
2227 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2228                                struct rte_eth_fc_conf *fc_conf)
2229 {
2230         struct bnxt *bp = dev->data->dev_private;
2231         int rc;
2232
2233         rc = is_bnxt_in_error(bp);
2234         if (rc)
2235                 return rc;
2236
2237         if (!BNXT_SINGLE_PF(bp)) {
2238                 PMD_DRV_LOG(ERR,
2239                             "Flow Control Settings cannot be modified on VF or on shared PF\n");
2240                 return -ENOTSUP;
2241         }
2242
2243         switch (fc_conf->mode) {
2244         case RTE_FC_NONE:
2245                 bp->link_info->auto_pause = 0;
2246                 bp->link_info->force_pause = 0;
2247                 break;
2248         case RTE_FC_RX_PAUSE:
2249                 if (fc_conf->autoneg) {
2250                         bp->link_info->auto_pause =
2251                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2252                         bp->link_info->force_pause = 0;
2253                 } else {
2254                         bp->link_info->auto_pause = 0;
2255                         bp->link_info->force_pause =
2256                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2257                 }
2258                 break;
2259         case RTE_FC_TX_PAUSE:
2260                 if (fc_conf->autoneg) {
2261                         bp->link_info->auto_pause =
2262                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2263                         bp->link_info->force_pause = 0;
2264                 } else {
2265                         bp->link_info->auto_pause = 0;
2266                         bp->link_info->force_pause =
2267                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2268                 }
2269                 break;
2270         case RTE_FC_FULL:
2271                 if (fc_conf->autoneg) {
2272                         bp->link_info->auto_pause =
2273                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2274                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2275                         bp->link_info->force_pause = 0;
2276                 } else {
2277                         bp->link_info->auto_pause = 0;
2278                         bp->link_info->force_pause =
2279                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2280                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2281                 }
2282                 break;
2283         }
2284         return bnxt_set_hwrm_link_config(bp, true);
2285 }
2286
2287 /* Add UDP tunneling port */
2288 static int
2289 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2290                          struct rte_eth_udp_tunnel *udp_tunnel)
2291 {
2292         struct bnxt *bp = eth_dev->data->dev_private;
2293         uint16_t tunnel_type = 0;
2294         int rc = 0;
2295
2296         rc = is_bnxt_in_error(bp);
2297         if (rc)
2298                 return rc;
2299
2300         switch (udp_tunnel->prot_type) {
2301         case RTE_TUNNEL_TYPE_VXLAN:
2302                 if (bp->vxlan_port_cnt) {
2303                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2304                                 udp_tunnel->udp_port);
2305                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2306                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2307                                 return -ENOSPC;
2308                         }
2309                         bp->vxlan_port_cnt++;
2310                         return 0;
2311                 }
2312                 tunnel_type =
2313                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2314                 bp->vxlan_port_cnt++;
2315                 break;
2316         case RTE_TUNNEL_TYPE_GENEVE:
2317                 if (bp->geneve_port_cnt) {
2318                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2319                                 udp_tunnel->udp_port);
2320                         if (bp->geneve_port != udp_tunnel->udp_port) {
2321                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2322                                 return -ENOSPC;
2323                         }
2324                         bp->geneve_port_cnt++;
2325                         return 0;
2326                 }
2327                 tunnel_type =
2328                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2329                 bp->geneve_port_cnt++;
2330                 break;
2331         default:
2332                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2333                 return -ENOTSUP;
2334         }
2335         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2336                                              tunnel_type);
2337         return rc;
2338 }
2339
2340 static int
2341 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2342                          struct rte_eth_udp_tunnel *udp_tunnel)
2343 {
2344         struct bnxt *bp = eth_dev->data->dev_private;
2345         uint16_t tunnel_type = 0;
2346         uint16_t port = 0;
2347         int rc = 0;
2348
2349         rc = is_bnxt_in_error(bp);
2350         if (rc)
2351                 return rc;
2352
2353         switch (udp_tunnel->prot_type) {
2354         case RTE_TUNNEL_TYPE_VXLAN:
2355                 if (!bp->vxlan_port_cnt) {
2356                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2357                         return -EINVAL;
2358                 }
2359                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2360                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2361                                 udp_tunnel->udp_port, bp->vxlan_port);
2362                         return -EINVAL;
2363                 }
2364                 if (--bp->vxlan_port_cnt)
2365                         return 0;
2366
2367                 tunnel_type =
2368                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2369                 port = bp->vxlan_fw_dst_port_id;
2370                 break;
2371         case RTE_TUNNEL_TYPE_GENEVE:
2372                 if (!bp->geneve_port_cnt) {
2373                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2374                         return -EINVAL;
2375                 }
2376                 if (bp->geneve_port != udp_tunnel->udp_port) {
2377                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2378                                 udp_tunnel->udp_port, bp->geneve_port);
2379                         return -EINVAL;
2380                 }
2381                 if (--bp->geneve_port_cnt)
2382                         return 0;
2383
2384                 tunnel_type =
2385                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2386                 port = bp->geneve_fw_dst_port_id;
2387                 break;
2388         default:
2389                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2390                 return -ENOTSUP;
2391         }
2392
2393         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2394         return rc;
2395 }
2396
2397 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2398 {
2399         struct bnxt_filter_info *filter;
2400         struct bnxt_vnic_info *vnic;
2401         int rc = 0;
2402         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2403
2404         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2405         filter = STAILQ_FIRST(&vnic->filter);
2406         while (filter) {
2407                 /* Search for this matching MAC+VLAN filter */
2408                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2409                         /* Delete the filter */
2410                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2411                         if (rc)
2412                                 return rc;
2413                         STAILQ_REMOVE(&vnic->filter, filter,
2414                                       bnxt_filter_info, next);
2415                         bnxt_free_filter(bp, filter);
2416                         PMD_DRV_LOG(INFO,
2417                                     "Deleted vlan filter for %d\n",
2418                                     vlan_id);
2419                         return 0;
2420                 }
2421                 filter = STAILQ_NEXT(filter, next);
2422         }
2423         return -ENOENT;
2424 }
2425
2426 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2427 {
2428         struct bnxt_filter_info *filter;
2429         struct bnxt_vnic_info *vnic;
2430         int rc = 0;
2431         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2432                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2433         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2434
2435         /* Implementation notes on the use of VNIC in this command:
2436          *
2437          * By default, these filters belong to default vnic for the function.
2438          * Once these filters are set up, only destination VNIC can be modified.
2439          * If the destination VNIC is not specified in this command,
2440          * then the HWRM shall only create an l2 context id.
2441          */
2442
2443         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2444         filter = STAILQ_FIRST(&vnic->filter);
2445         /* Check if the VLAN has already been added */
2446         while (filter) {
2447                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2448                         return -EEXIST;
2449
2450                 filter = STAILQ_NEXT(filter, next);
2451         }
2452
2453         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2454          * command to create MAC+VLAN filter with the right flags, enables set.
2455          */
2456         filter = bnxt_alloc_filter(bp);
2457         if (!filter) {
2458                 PMD_DRV_LOG(ERR,
2459                             "MAC/VLAN filter alloc failed\n");
2460                 return -ENOMEM;
2461         }
2462         /* MAC + VLAN ID filter */
2463         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2464          * untagged packets are received
2465          *
2466          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2467          * packets and only the programmed vlan's packets are received
2468          */
2469         filter->l2_ivlan = vlan_id;
2470         filter->l2_ivlan_mask = 0x0FFF;
2471         filter->enables |= en;
2472         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2473
2474         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2475         if (rc) {
2476                 /* Free the newly allocated filter as we were
2477                  * not able to create the filter in hardware.
2478                  */
2479                 bnxt_free_filter(bp, filter);
2480                 return rc;
2481         }
2482
2483         filter->mac_index = 0;
2484         /* Add this new filter to the list */
2485         if (vlan_id == 0)
2486                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2487         else
2488                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2489
2490         PMD_DRV_LOG(INFO,
2491                     "Added Vlan filter for %d\n", vlan_id);
2492         return rc;
2493 }
2494
2495 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2496                 uint16_t vlan_id, int on)
2497 {
2498         struct bnxt *bp = eth_dev->data->dev_private;
2499         int rc;
2500
2501         rc = is_bnxt_in_error(bp);
2502         if (rc)
2503                 return rc;
2504
2505         if (!eth_dev->data->dev_started) {
2506                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2507                 return -EINVAL;
2508         }
2509
2510         /* These operations apply to ALL existing MAC/VLAN filters */
2511         if (on)
2512                 return bnxt_add_vlan_filter(bp, vlan_id);
2513         else
2514                 return bnxt_del_vlan_filter(bp, vlan_id);
2515 }
2516
2517 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2518                                     struct bnxt_vnic_info *vnic)
2519 {
2520         struct bnxt_filter_info *filter;
2521         int rc;
2522
2523         filter = STAILQ_FIRST(&vnic->filter);
2524         while (filter) {
2525                 if (filter->mac_index == 0 &&
2526                     !memcmp(filter->l2_addr, bp->mac_addr,
2527                             RTE_ETHER_ADDR_LEN)) {
2528                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2529                         if (!rc) {
2530                                 STAILQ_REMOVE(&vnic->filter, filter,
2531                                               bnxt_filter_info, next);
2532                                 bnxt_free_filter(bp, filter);
2533                         }
2534                         return rc;
2535                 }
2536                 filter = STAILQ_NEXT(filter, next);
2537         }
2538         return 0;
2539 }
2540
2541 static int
2542 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2543 {
2544         struct bnxt_vnic_info *vnic;
2545         unsigned int i;
2546         int rc;
2547
2548         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2549         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2550                 /* Remove any VLAN filters programmed */
2551                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2552                         bnxt_del_vlan_filter(bp, i);
2553
2554                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2555                 if (rc)
2556                         return rc;
2557         } else {
2558                 /* Default filter will allow packets that match the
2559                  * dest mac. So, it has to be deleted, otherwise, we
2560                  * will endup receiving vlan packets for which the
2561                  * filter is not programmed, when hw-vlan-filter
2562                  * configuration is ON
2563                  */
2564                 bnxt_del_dflt_mac_filter(bp, vnic);
2565                 /* This filter will allow only untagged packets */
2566                 bnxt_add_vlan_filter(bp, 0);
2567         }
2568         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2569                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2570
2571         return 0;
2572 }
2573
2574 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2575 {
2576         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2577         unsigned int i;
2578         int rc;
2579
2580         /* Destroy vnic filters and vnic */
2581         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2582             DEV_RX_OFFLOAD_VLAN_FILTER) {
2583                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2584                         bnxt_del_vlan_filter(bp, i);
2585         }
2586         bnxt_del_dflt_mac_filter(bp, vnic);
2587
2588         rc = bnxt_hwrm_vnic_ctx_free(bp, vnic);
2589         if (rc)
2590                 return rc;
2591
2592         rc = bnxt_hwrm_vnic_free(bp, vnic);
2593         if (rc)
2594                 return rc;
2595
2596         rte_free(vnic->fw_grp_ids);
2597         vnic->fw_grp_ids = NULL;
2598
2599         vnic->rx_queue_cnt = 0;
2600
2601         return 0;
2602 }
2603
2604 static int
2605 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2606 {
2607         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2608         int rc;
2609
2610         /* Destroy, recreate and reconfigure the default vnic */
2611         rc = bnxt_free_one_vnic(bp, 0);
2612         if (rc)
2613                 return rc;
2614
2615         /* default vnic 0 */
2616         rc = bnxt_setup_one_vnic(bp, 0);
2617         if (rc)
2618                 return rc;
2619
2620         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2621             DEV_RX_OFFLOAD_VLAN_FILTER) {
2622                 rc = bnxt_add_vlan_filter(bp, 0);
2623                 if (rc)
2624                         return rc;
2625                 rc = bnxt_restore_vlan_filters(bp);
2626                 if (rc)
2627                         return rc;
2628         } else {
2629                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2630                 if (rc)
2631                         return rc;
2632         }
2633
2634         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2635         if (rc)
2636                 return rc;
2637
2638         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2639                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2640
2641         return rc;
2642 }
2643
2644 static int
2645 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2646 {
2647         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2648         struct bnxt *bp = dev->data->dev_private;
2649         int rc;
2650
2651         rc = is_bnxt_in_error(bp);
2652         if (rc)
2653                 return rc;
2654
2655         /* Filter settings will get applied when port is started */
2656         if (!dev->data->dev_started)
2657                 return 0;
2658
2659         if (mask & ETH_VLAN_FILTER_MASK) {
2660                 /* Enable or disable VLAN filtering */
2661                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2662                 if (rc)
2663                         return rc;
2664         }
2665
2666         if (mask & ETH_VLAN_STRIP_MASK) {
2667                 /* Enable or disable VLAN stripping */
2668                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2669                 if (rc)
2670                         return rc;
2671         }
2672
2673         if (mask & ETH_VLAN_EXTEND_MASK) {
2674                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2675                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2676                 else
2677                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2678         }
2679
2680         return 0;
2681 }
2682
2683 static int
2684 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2685                       uint16_t tpid)
2686 {
2687         struct bnxt *bp = dev->data->dev_private;
2688         int qinq = dev->data->dev_conf.rxmode.offloads &
2689                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2690
2691         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2692             vlan_type != ETH_VLAN_TYPE_OUTER) {
2693                 PMD_DRV_LOG(ERR,
2694                             "Unsupported vlan type.");
2695                 return -EINVAL;
2696         }
2697         if (!qinq) {
2698                 PMD_DRV_LOG(ERR,
2699                             "QinQ not enabled. Needs to be ON as we can "
2700                             "accelerate only outer vlan\n");
2701                 return -EINVAL;
2702         }
2703
2704         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2705                 switch (tpid) {
2706                 case RTE_ETHER_TYPE_QINQ:
2707                         bp->outer_tpid_bd =
2708                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2709                                 break;
2710                 case RTE_ETHER_TYPE_VLAN:
2711                         bp->outer_tpid_bd =
2712                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2713                                 break;
2714                 case RTE_ETHER_TYPE_QINQ1:
2715                         bp->outer_tpid_bd =
2716                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2717                                 break;
2718                 case RTE_ETHER_TYPE_QINQ2:
2719                         bp->outer_tpid_bd =
2720                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2721                                 break;
2722                 case RTE_ETHER_TYPE_QINQ3:
2723                         bp->outer_tpid_bd =
2724                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2725                                 break;
2726                 default:
2727                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2728                         return -EINVAL;
2729                 }
2730                 bp->outer_tpid_bd |= tpid;
2731                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2732         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2733                 PMD_DRV_LOG(ERR,
2734                             "Can accelerate only outer vlan in QinQ\n");
2735                 return -EINVAL;
2736         }
2737
2738         return 0;
2739 }
2740
2741 static int
2742 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2743                              struct rte_ether_addr *addr)
2744 {
2745         struct bnxt *bp = dev->data->dev_private;
2746         /* Default Filter is tied to VNIC 0 */
2747         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2748         int rc;
2749
2750         rc = is_bnxt_in_error(bp);
2751         if (rc)
2752                 return rc;
2753
2754         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2755                 return -EPERM;
2756
2757         if (rte_is_zero_ether_addr(addr))
2758                 return -EINVAL;
2759
2760         /* Filter settings will get applied when port is started */
2761         if (!dev->data->dev_started)
2762                 return 0;
2763
2764         /* Check if the requested MAC is already added */
2765         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2766                 return 0;
2767
2768         /* Destroy filter and re-create it */
2769         bnxt_del_dflt_mac_filter(bp, vnic);
2770
2771         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2772         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2773                 /* This filter will allow only untagged packets */
2774                 rc = bnxt_add_vlan_filter(bp, 0);
2775         } else {
2776                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2777         }
2778
2779         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2780         return rc;
2781 }
2782
2783 static int
2784 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2785                           struct rte_ether_addr *mc_addr_set,
2786                           uint32_t nb_mc_addr)
2787 {
2788         struct bnxt *bp = eth_dev->data->dev_private;
2789         char *mc_addr_list = (char *)mc_addr_set;
2790         struct bnxt_vnic_info *vnic;
2791         uint32_t off = 0, i = 0;
2792         int rc;
2793
2794         rc = is_bnxt_in_error(bp);
2795         if (rc)
2796                 return rc;
2797
2798         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2799
2800         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2801                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2802                 goto allmulti;
2803         }
2804
2805         /* TODO Check for Duplicate mcast addresses */
2806         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2807         for (i = 0; i < nb_mc_addr; i++) {
2808                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2809                         RTE_ETHER_ADDR_LEN);
2810                 off += RTE_ETHER_ADDR_LEN;
2811         }
2812
2813         vnic->mc_addr_cnt = i;
2814         if (vnic->mc_addr_cnt)
2815                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2816         else
2817                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2818
2819 allmulti:
2820         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2821 }
2822
2823 static int
2824 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2825 {
2826         struct bnxt *bp = dev->data->dev_private;
2827         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2828         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2829         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2830         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2831         int ret;
2832
2833         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2834                         fw_major, fw_minor, fw_updt, fw_rsvd);
2835         if (ret < 0)
2836                 return -EINVAL;
2837
2838         ret += 1; /* add the size of '\0' */
2839         if (fw_size < (size_t)ret)
2840                 return ret;
2841         else
2842                 return 0;
2843 }
2844
2845 static void
2846 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2847         struct rte_eth_rxq_info *qinfo)
2848 {
2849         struct bnxt *bp = dev->data->dev_private;
2850         struct bnxt_rx_queue *rxq;
2851
2852         if (is_bnxt_in_error(bp))
2853                 return;
2854
2855         rxq = dev->data->rx_queues[queue_id];
2856
2857         qinfo->mp = rxq->mb_pool;
2858         qinfo->scattered_rx = dev->data->scattered_rx;
2859         qinfo->nb_desc = rxq->nb_rx_desc;
2860
2861         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2862         qinfo->conf.rx_drop_en = rxq->drop_en;
2863         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2864         qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2865 }
2866
2867 static void
2868 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2869         struct rte_eth_txq_info *qinfo)
2870 {
2871         struct bnxt *bp = dev->data->dev_private;
2872         struct bnxt_tx_queue *txq;
2873
2874         if (is_bnxt_in_error(bp))
2875                 return;
2876
2877         txq = dev->data->tx_queues[queue_id];
2878
2879         qinfo->nb_desc = txq->nb_tx_desc;
2880
2881         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2882         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2883         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2884
2885         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2886         qinfo->conf.tx_rs_thresh = 0;
2887         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2888         qinfo->conf.offloads = txq->offloads;
2889 }
2890
2891 static const struct {
2892         eth_rx_burst_t pkt_burst;
2893         const char *info;
2894 } bnxt_rx_burst_info[] = {
2895         {bnxt_recv_pkts,                "Scalar"},
2896 #if defined(RTE_ARCH_X86)
2897         {bnxt_recv_pkts_vec,            "Vector SSE"},
2898 #endif
2899 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2900         {bnxt_recv_pkts_vec_avx2,       "Vector AVX2"},
2901 #endif
2902 #if defined(RTE_ARCH_ARM64)
2903         {bnxt_recv_pkts_vec,            "Vector Neon"},
2904 #endif
2905 };
2906
2907 static int
2908 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2909                        struct rte_eth_burst_mode *mode)
2910 {
2911         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2912         size_t i;
2913
2914         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2915                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2916                         snprintf(mode->info, sizeof(mode->info), "%s",
2917                                  bnxt_rx_burst_info[i].info);
2918                         return 0;
2919                 }
2920         }
2921
2922         return -EINVAL;
2923 }
2924
2925 static const struct {
2926         eth_tx_burst_t pkt_burst;
2927         const char *info;
2928 } bnxt_tx_burst_info[] = {
2929         {bnxt_xmit_pkts,                "Scalar"},
2930 #if defined(RTE_ARCH_X86)
2931         {bnxt_xmit_pkts_vec,            "Vector SSE"},
2932 #endif
2933 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2934         {bnxt_xmit_pkts_vec_avx2,       "Vector AVX2"},
2935 #endif
2936 #if defined(RTE_ARCH_ARM64)
2937         {bnxt_xmit_pkts_vec,            "Vector Neon"},
2938 #endif
2939 };
2940
2941 static int
2942 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2943                        struct rte_eth_burst_mode *mode)
2944 {
2945         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2946         size_t i;
2947
2948         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2949                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2950                         snprintf(mode->info, sizeof(mode->info), "%s",
2951                                  bnxt_tx_burst_info[i].info);
2952                         return 0;
2953                 }
2954         }
2955
2956         return -EINVAL;
2957 }
2958
2959 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2960 {
2961         struct bnxt *bp = eth_dev->data->dev_private;
2962         uint32_t new_pkt_size;
2963         uint32_t rc = 0;
2964         uint32_t i;
2965
2966         rc = is_bnxt_in_error(bp);
2967         if (rc)
2968                 return rc;
2969
2970         /* Exit if receive queues are not configured yet */
2971         if (!eth_dev->data->nb_rx_queues)
2972                 return rc;
2973
2974         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2975                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2976
2977         /*
2978          * Disallow any MTU change that would require scattered receive support
2979          * if it is not already enabled.
2980          */
2981         if (eth_dev->data->dev_started &&
2982             !eth_dev->data->scattered_rx &&
2983             (new_pkt_size >
2984              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2985                 PMD_DRV_LOG(ERR,
2986                             "MTU change would require scattered rx support. ");
2987                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2988                 return -EINVAL;
2989         }
2990
2991         if (new_mtu > RTE_ETHER_MTU) {
2992                 bp->flags |= BNXT_FLAG_JUMBO;
2993                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2994                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2995         } else {
2996                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2997                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2998                 bp->flags &= ~BNXT_FLAG_JUMBO;
2999         }
3000
3001         /* Is there a change in mtu setting? */
3002         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
3003                 return rc;
3004
3005         for (i = 0; i < bp->nr_vnics; i++) {
3006                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3007                 uint16_t size = 0;
3008
3009                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
3010                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
3011                 if (rc)
3012                         break;
3013
3014                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
3015                 size -= RTE_PKTMBUF_HEADROOM;
3016
3017                 if (size < new_mtu) {
3018                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
3019                         if (rc)
3020                                 return rc;
3021                 }
3022         }
3023
3024         if (!rc)
3025                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
3026
3027         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
3028
3029         return rc;
3030 }
3031
3032 static int
3033 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
3034 {
3035         struct bnxt *bp = dev->data->dev_private;
3036         uint16_t vlan = bp->vlan;
3037         int rc;
3038
3039         rc = is_bnxt_in_error(bp);
3040         if (rc)
3041                 return rc;
3042
3043         if (!BNXT_SINGLE_PF(bp)) {
3044                 PMD_DRV_LOG(ERR, "PVID cannot be modified on VF or on shared PF\n");
3045                 return -ENOTSUP;
3046         }
3047         bp->vlan = on ? pvid : 0;
3048
3049         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
3050         if (rc)
3051                 bp->vlan = vlan;
3052         return rc;
3053 }
3054
3055 static int
3056 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
3057 {
3058         struct bnxt *bp = dev->data->dev_private;
3059         int rc;
3060
3061         rc = is_bnxt_in_error(bp);
3062         if (rc)
3063                 return rc;
3064
3065         return bnxt_hwrm_port_led_cfg(bp, true);
3066 }
3067
3068 static int
3069 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
3070 {
3071         struct bnxt *bp = dev->data->dev_private;
3072         int rc;
3073
3074         rc = is_bnxt_in_error(bp);
3075         if (rc)
3076                 return rc;
3077
3078         return bnxt_hwrm_port_led_cfg(bp, false);
3079 }
3080
3081 static uint32_t
3082 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3083 {
3084         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
3085         struct bnxt_cp_ring_info *cpr;
3086         uint32_t desc = 0, raw_cons;
3087         struct bnxt_rx_queue *rxq;
3088         struct rx_pkt_cmpl *rxcmp;
3089         int rc;
3090
3091         rc = is_bnxt_in_error(bp);
3092         if (rc)
3093                 return rc;
3094
3095         rxq = dev->data->rx_queues[rx_queue_id];
3096         cpr = rxq->cp_ring;
3097         raw_cons = cpr->cp_raw_cons;
3098
3099         while (1) {
3100                 uint32_t agg_cnt, cons, cmpl_type;
3101
3102                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3103                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3104
3105                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3106                         break;
3107
3108                 cmpl_type = CMP_TYPE(rxcmp);
3109
3110                 switch (cmpl_type) {
3111                 case CMPL_BASE_TYPE_RX_L2:
3112                 case CMPL_BASE_TYPE_RX_L2_V2:
3113                         agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3114                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3115                         desc++;
3116                         break;
3117
3118                 case CMPL_BASE_TYPE_RX_TPA_END:
3119                         if (BNXT_CHIP_P5(rxq->bp)) {
3120                                 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3121
3122                                 p5_tpa_end = (void *)rxcmp;
3123                                 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3124                         } else {
3125                                 struct rx_tpa_end_cmpl *tpa_end;
3126
3127                                 tpa_end = (void *)rxcmp;
3128                                 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3129                         }
3130
3131                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3132                         desc++;
3133                         break;
3134
3135                 default:
3136                         raw_cons += CMP_LEN(cmpl_type);
3137                 }
3138         }
3139
3140         return desc;
3141 }
3142
3143 static int
3144 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
3145 {
3146         struct bnxt_rx_queue *rxq = rx_queue;
3147         struct bnxt_cp_ring_info *cpr;
3148         struct bnxt_rx_ring_info *rxr;
3149         uint32_t desc, raw_cons;
3150         struct bnxt *bp = rxq->bp;
3151         struct rx_pkt_cmpl *rxcmp;
3152         int rc;
3153
3154         rc = is_bnxt_in_error(bp);
3155         if (rc)
3156                 return rc;
3157
3158         if (offset >= rxq->nb_rx_desc)
3159                 return -EINVAL;
3160
3161         rxr = rxq->rx_ring;
3162         cpr = rxq->cp_ring;
3163
3164         /*
3165          * For the vector receive case, the completion at the requested
3166          * offset can be indexed directly.
3167          */
3168 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
3169         if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) {
3170                 struct rx_pkt_cmpl *rxcmp;
3171                 uint32_t cons;
3172
3173                 /* Check status of completion descriptor. */
3174                 raw_cons = cpr->cp_raw_cons +
3175                            offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2);
3176                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3177                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3178
3179                 if (CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3180                         return RTE_ETH_RX_DESC_DONE;
3181
3182                 /* Check whether rx desc has an mbuf attached. */
3183                 cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2);
3184                 if (cons >= rxq->rxrearm_start &&
3185                     cons < rxq->rxrearm_start + rxq->rxrearm_nb) {
3186                         return RTE_ETH_RX_DESC_UNAVAIL;
3187                 }
3188
3189                 return RTE_ETH_RX_DESC_AVAIL;
3190         }
3191 #endif
3192
3193         /*
3194          * For the non-vector receive case, scan the completion ring to
3195          * locate the completion descriptor for the requested offset.
3196          */
3197         raw_cons = cpr->cp_raw_cons;
3198         desc = 0;
3199         while (1) {
3200                 uint32_t agg_cnt, cons, cmpl_type;
3201
3202                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3203                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3204
3205                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3206                         break;
3207
3208                 cmpl_type = CMP_TYPE(rxcmp);
3209
3210                 switch (cmpl_type) {
3211                 case CMPL_BASE_TYPE_RX_L2:
3212                 case CMPL_BASE_TYPE_RX_L2_V2:
3213                         if (desc == offset) {
3214                                 cons = rxcmp->opaque;
3215                                 if (rxr->rx_buf_ring[cons])
3216                                         return RTE_ETH_RX_DESC_DONE;
3217                                 else
3218                                         return RTE_ETH_RX_DESC_UNAVAIL;
3219                         }
3220                         agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3221                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3222                         desc++;
3223                         break;
3224
3225                 case CMPL_BASE_TYPE_RX_TPA_END:
3226                         if (desc == offset)
3227                                 return RTE_ETH_RX_DESC_DONE;
3228
3229                         if (BNXT_CHIP_P5(rxq->bp)) {
3230                                 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3231
3232                                 p5_tpa_end = (void *)rxcmp;
3233                                 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3234                         } else {
3235                                 struct rx_tpa_end_cmpl *tpa_end;
3236
3237                                 tpa_end = (void *)rxcmp;
3238                                 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3239                         }
3240
3241                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3242                         desc++;
3243                         break;
3244
3245                 default:
3246                         raw_cons += CMP_LEN(cmpl_type);
3247                 }
3248         }
3249
3250         return RTE_ETH_RX_DESC_AVAIL;
3251 }
3252
3253 static int
3254 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
3255 {
3256         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
3257         struct bnxt_tx_ring_info *txr;
3258         struct bnxt_cp_ring_info *cpr;
3259         struct rte_mbuf **tx_buf;
3260         struct tx_pkt_cmpl *txcmp;
3261         uint32_t cons, cp_cons;
3262         int rc;
3263
3264         if (!txq)
3265                 return -EINVAL;
3266
3267         rc = is_bnxt_in_error(txq->bp);
3268         if (rc)
3269                 return rc;
3270
3271         cpr = txq->cp_ring;
3272         txr = txq->tx_ring;
3273
3274         if (offset >= txq->nb_tx_desc)
3275                 return -EINVAL;
3276
3277         cons = RING_CMP(cpr->cp_ring_struct, offset);
3278         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3279         cp_cons = cpr->cp_raw_cons;
3280
3281         if (cons > cp_cons) {
3282                 if (CMPL_VALID(txcmp, cpr->valid))
3283                         return RTE_ETH_TX_DESC_UNAVAIL;
3284         } else {
3285                 if (CMPL_VALID(txcmp, !cpr->valid))
3286                         return RTE_ETH_TX_DESC_UNAVAIL;
3287         }
3288         tx_buf = &txr->tx_buf_ring[cons];
3289         if (*tx_buf == NULL)
3290                 return RTE_ETH_TX_DESC_DONE;
3291
3292         return RTE_ETH_TX_DESC_FULL;
3293 }
3294
3295 int
3296 bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
3297                      const struct rte_flow_ops **ops)
3298 {
3299         struct bnxt *bp = dev->data->dev_private;
3300         int ret = 0;
3301
3302         if (!bp)
3303                 return -EIO;
3304
3305         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3306                 struct bnxt_representor *vfr = dev->data->dev_private;
3307                 bp = vfr->parent_dev->data->dev_private;
3308                 /* parent is deleted while children are still valid */
3309                 if (!bp) {
3310                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error\n",
3311                                     dev->data->port_id);
3312                         return -EIO;
3313                 }
3314         }
3315
3316         ret = is_bnxt_in_error(bp);
3317         if (ret)
3318                 return ret;
3319
3320         /* PMD supports thread-safe flow operations.  rte_flow API
3321          * functions can avoid mutex for multi-thread safety.
3322          */
3323         dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3324
3325         if (BNXT_TRUFLOW_EN(bp))
3326                 *ops = &bnxt_ulp_rte_flow_ops;
3327         else
3328                 *ops = &bnxt_flow_ops;
3329
3330         return ret;
3331 }
3332
3333 static const uint32_t *
3334 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3335 {
3336         static const uint32_t ptypes[] = {
3337                 RTE_PTYPE_L2_ETHER_VLAN,
3338                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3339                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3340                 RTE_PTYPE_L4_ICMP,
3341                 RTE_PTYPE_L4_TCP,
3342                 RTE_PTYPE_L4_UDP,
3343                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3344                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3345                 RTE_PTYPE_INNER_L4_ICMP,
3346                 RTE_PTYPE_INNER_L4_TCP,
3347                 RTE_PTYPE_INNER_L4_UDP,
3348                 RTE_PTYPE_UNKNOWN
3349         };
3350
3351         if (!dev->rx_pkt_burst)
3352                 return NULL;
3353
3354         return ptypes;
3355 }
3356
3357 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3358                          int reg_win)
3359 {
3360         uint32_t reg_base = *reg_arr & 0xfffff000;
3361         uint32_t win_off;
3362         int i;
3363
3364         for (i = 0; i < count; i++) {
3365                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3366                         return -ERANGE;
3367         }
3368         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3369         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3370         return 0;
3371 }
3372
3373 static int bnxt_map_ptp_regs(struct bnxt *bp)
3374 {
3375         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3376         uint32_t *reg_arr;
3377         int rc, i;
3378
3379         reg_arr = ptp->rx_regs;
3380         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3381         if (rc)
3382                 return rc;
3383
3384         reg_arr = ptp->tx_regs;
3385         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3386         if (rc)
3387                 return rc;
3388
3389         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3390                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3391
3392         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3393                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3394
3395         return 0;
3396 }
3397
3398 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3399 {
3400         rte_write32(0, (uint8_t *)bp->bar0 +
3401                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3402         rte_write32(0, (uint8_t *)bp->bar0 +
3403                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3404 }
3405
3406 static uint64_t bnxt_cc_read(struct bnxt *bp)
3407 {
3408         uint64_t ns;
3409
3410         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3411                               BNXT_GRCPF_REG_SYNC_TIME));
3412         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3413                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3414         return ns;
3415 }
3416
3417 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3418 {
3419         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3420         uint32_t fifo;
3421
3422         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3423                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3424         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3425                 return -EAGAIN;
3426
3427         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3428                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3429         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3430                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3431         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3432                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3433         rte_read32((uint8_t *)bp->bar0 + ptp->tx_mapped_regs[BNXT_PTP_TX_SEQ]);
3434
3435         return 0;
3436 }
3437
3438 static int bnxt_clr_rx_ts(struct bnxt *bp, uint64_t *last_ts)
3439 {
3440         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3441         struct bnxt_pf_info *pf = bp->pf;
3442         uint16_t port_id;
3443         int i = 0;
3444         uint32_t fifo;
3445
3446         if (!ptp || (bp->flags & BNXT_FLAG_CHIP_P5))
3447                 return -EINVAL;
3448
3449         port_id = pf->port_id;
3450         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3451                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3452         while ((fifo & BNXT_PTP_RX_FIFO_PENDING) && (i < BNXT_PTP_RX_PND_CNT)) {
3453                 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3454                             ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3455                 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3456                                         ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3457                 *last_ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3458                                         ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3459                 *last_ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3460                                         ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3461                 i++;
3462         }
3463
3464         if (i >= BNXT_PTP_RX_PND_CNT)
3465                 return -EBUSY;
3466
3467         return 0;
3468 }
3469
3470 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3471 {
3472         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3473         struct bnxt_pf_info *pf = bp->pf;
3474         uint16_t port_id;
3475         uint32_t fifo;
3476
3477         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3478                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3479         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3480                 return -EAGAIN;
3481
3482         port_id = pf->port_id;
3483         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3484                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3485
3486         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3487                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3488         if (fifo & BNXT_PTP_RX_FIFO_PENDING)
3489                 return bnxt_clr_rx_ts(bp, ts);
3490
3491         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3492                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3493         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3494                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3495
3496         return 0;
3497 }
3498
3499 static int
3500 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3501 {
3502         uint64_t ns;
3503         struct bnxt *bp = dev->data->dev_private;
3504         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3505
3506         if (!ptp)
3507                 return -ENOTSUP;
3508
3509         ns = rte_timespec_to_ns(ts);
3510         /* Set the timecounters to a new value. */
3511         ptp->tc.nsec = ns;
3512         ptp->tx_tstamp_tc.nsec = ns;
3513         ptp->rx_tstamp_tc.nsec = ns;
3514
3515         return 0;
3516 }
3517
3518 static int
3519 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3520 {
3521         struct bnxt *bp = dev->data->dev_private;
3522         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3523         uint64_t ns, systime_cycles = 0;
3524         int rc = 0;
3525
3526         if (!ptp)
3527                 return -ENOTSUP;
3528
3529         if (BNXT_CHIP_P5(bp))
3530                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3531                                              &systime_cycles);
3532         else
3533                 systime_cycles = bnxt_cc_read(bp);
3534
3535         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3536         *ts = rte_ns_to_timespec(ns);
3537
3538         return rc;
3539 }
3540 static int
3541 bnxt_timesync_enable(struct rte_eth_dev *dev)
3542 {
3543         struct bnxt *bp = dev->data->dev_private;
3544         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3545         uint32_t shift = 0;
3546         int rc;
3547
3548         if (!ptp)
3549                 return -ENOTSUP;
3550
3551         ptp->rx_filter = 1;
3552         ptp->tx_tstamp_en = 1;
3553         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3554
3555         rc = bnxt_hwrm_ptp_cfg(bp);
3556         if (rc)
3557                 return rc;
3558
3559         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3560         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3561         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3562
3563         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3564         ptp->tc.cc_shift = shift;
3565         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3566
3567         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3568         ptp->rx_tstamp_tc.cc_shift = shift;
3569         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3570
3571         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3572         ptp->tx_tstamp_tc.cc_shift = shift;
3573         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3574
3575         if (!BNXT_CHIP_P5(bp))
3576                 bnxt_map_ptp_regs(bp);
3577         else
3578                 rc = bnxt_ptp_start(bp);
3579
3580         return rc;
3581 }
3582
3583 static int
3584 bnxt_timesync_disable(struct rte_eth_dev *dev)
3585 {
3586         struct bnxt *bp = dev->data->dev_private;
3587         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3588
3589         if (!ptp)
3590                 return -ENOTSUP;
3591
3592         ptp->rx_filter = 0;
3593         ptp->tx_tstamp_en = 0;
3594         ptp->rxctl = 0;
3595
3596         bnxt_hwrm_ptp_cfg(bp);
3597
3598         if (!BNXT_CHIP_P5(bp))
3599                 bnxt_unmap_ptp_regs(bp);
3600         else
3601                 bnxt_ptp_stop(bp);
3602
3603         return 0;
3604 }
3605
3606 static int
3607 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3608                                  struct timespec *timestamp,
3609                                  uint32_t flags __rte_unused)
3610 {
3611         struct bnxt *bp = dev->data->dev_private;
3612         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3613         uint64_t rx_tstamp_cycles = 0;
3614         uint64_t ns;
3615
3616         if (!ptp)
3617                 return -ENOTSUP;
3618
3619         if (BNXT_CHIP_P5(bp))
3620                 rx_tstamp_cycles = ptp->rx_timestamp;
3621         else
3622                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3623
3624         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3625         *timestamp = rte_ns_to_timespec(ns);
3626         return  0;
3627 }
3628
3629 static int
3630 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3631                                  struct timespec *timestamp)
3632 {
3633         struct bnxt *bp = dev->data->dev_private;
3634         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3635         uint64_t tx_tstamp_cycles = 0;
3636         uint64_t ns;
3637         int rc = 0;
3638
3639         if (!ptp)
3640                 return -ENOTSUP;
3641
3642         if (BNXT_CHIP_P5(bp))
3643                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3644                                              &tx_tstamp_cycles);
3645         else
3646                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3647
3648         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3649         *timestamp = rte_ns_to_timespec(ns);
3650
3651         return rc;
3652 }
3653
3654 static int
3655 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3656 {
3657         struct bnxt *bp = dev->data->dev_private;
3658         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3659
3660         if (!ptp)
3661                 return -ENOTSUP;
3662
3663         ptp->tc.nsec += delta;
3664         ptp->tx_tstamp_tc.nsec += delta;
3665         ptp->rx_tstamp_tc.nsec += delta;
3666
3667         return 0;
3668 }
3669
3670 static int
3671 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3672 {
3673         struct bnxt *bp = dev->data->dev_private;
3674         int rc;
3675         uint32_t dir_entries;
3676         uint32_t entry_length;
3677
3678         rc = is_bnxt_in_error(bp);
3679         if (rc)
3680                 return rc;
3681
3682         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3683                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3684                     bp->pdev->addr.devid, bp->pdev->addr.function);
3685
3686         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3687         if (rc != 0)
3688                 return rc;
3689
3690         return dir_entries * entry_length;
3691 }
3692
3693 static int
3694 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3695                 struct rte_dev_eeprom_info *in_eeprom)
3696 {
3697         struct bnxt *bp = dev->data->dev_private;
3698         uint32_t index;
3699         uint32_t offset;
3700         int rc;
3701
3702         rc = is_bnxt_in_error(bp);
3703         if (rc)
3704                 return rc;
3705
3706         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3707                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3708                     bp->pdev->addr.devid, bp->pdev->addr.function,
3709                     in_eeprom->offset, in_eeprom->length);
3710
3711         if (in_eeprom->offset == 0) /* special offset value to get directory */
3712                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3713                                                 in_eeprom->data);
3714
3715         index = in_eeprom->offset >> 24;
3716         offset = in_eeprom->offset & 0xffffff;
3717
3718         if (index != 0)
3719                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3720                                            in_eeprom->length, in_eeprom->data);
3721
3722         return 0;
3723 }
3724
3725 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3726 {
3727         switch (dir_type) {
3728         case BNX_DIR_TYPE_CHIMP_PATCH:
3729         case BNX_DIR_TYPE_BOOTCODE:
3730         case BNX_DIR_TYPE_BOOTCODE_2:
3731         case BNX_DIR_TYPE_APE_FW:
3732         case BNX_DIR_TYPE_APE_PATCH:
3733         case BNX_DIR_TYPE_KONG_FW:
3734         case BNX_DIR_TYPE_KONG_PATCH:
3735         case BNX_DIR_TYPE_BONO_FW:
3736         case BNX_DIR_TYPE_BONO_PATCH:
3737                 /* FALLTHROUGH */
3738                 return true;
3739         }
3740
3741         return false;
3742 }
3743
3744 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3745 {
3746         switch (dir_type) {
3747         case BNX_DIR_TYPE_AVS:
3748         case BNX_DIR_TYPE_EXP_ROM_MBA:
3749         case BNX_DIR_TYPE_PCIE:
3750         case BNX_DIR_TYPE_TSCF_UCODE:
3751         case BNX_DIR_TYPE_EXT_PHY:
3752         case BNX_DIR_TYPE_CCM:
3753         case BNX_DIR_TYPE_ISCSI_BOOT:
3754         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3755         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3756                 /* FALLTHROUGH */
3757                 return true;
3758         }
3759
3760         return false;
3761 }
3762
3763 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3764 {
3765         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3766                 bnxt_dir_type_is_other_exec_format(dir_type);
3767 }
3768
3769 static int
3770 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3771                 struct rte_dev_eeprom_info *in_eeprom)
3772 {
3773         struct bnxt *bp = dev->data->dev_private;
3774         uint8_t index, dir_op;
3775         uint16_t type, ext, ordinal, attr;
3776         int rc;
3777
3778         rc = is_bnxt_in_error(bp);
3779         if (rc)
3780                 return rc;
3781
3782         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3783                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3784                     bp->pdev->addr.devid, bp->pdev->addr.function,
3785                     in_eeprom->offset, in_eeprom->length);
3786
3787         if (!BNXT_PF(bp)) {
3788                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3789                 return -EINVAL;
3790         }
3791
3792         type = in_eeprom->magic >> 16;
3793
3794         if (type == 0xffff) { /* special value for directory operations */
3795                 index = in_eeprom->magic & 0xff;
3796                 dir_op = in_eeprom->magic >> 8;
3797                 if (index == 0)
3798                         return -EINVAL;
3799                 switch (dir_op) {
3800                 case 0x0e: /* erase */
3801                         if (in_eeprom->offset != ~in_eeprom->magic)
3802                                 return -EINVAL;
3803                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3804                 default:
3805                         return -EINVAL;
3806                 }
3807         }
3808
3809         /* Create or re-write an NVM item: */
3810         if (bnxt_dir_type_is_executable(type) == true)
3811                 return -EOPNOTSUPP;
3812         ext = in_eeprom->magic & 0xffff;
3813         ordinal = in_eeprom->offset >> 16;
3814         attr = in_eeprom->offset & 0xffff;
3815
3816         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3817                                      in_eeprom->data, in_eeprom->length);
3818 }
3819
3820 /*
3821  * Initialization
3822  */
3823
3824 static const struct eth_dev_ops bnxt_dev_ops = {
3825         .dev_infos_get = bnxt_dev_info_get_op,
3826         .dev_close = bnxt_dev_close_op,
3827         .dev_configure = bnxt_dev_configure_op,
3828         .dev_start = bnxt_dev_start_op,
3829         .dev_stop = bnxt_dev_stop_op,
3830         .dev_set_link_up = bnxt_dev_set_link_up_op,
3831         .dev_set_link_down = bnxt_dev_set_link_down_op,
3832         .stats_get = bnxt_stats_get_op,
3833         .stats_reset = bnxt_stats_reset_op,
3834         .rx_queue_setup = bnxt_rx_queue_setup_op,
3835         .rx_queue_release = bnxt_rx_queue_release_op,
3836         .tx_queue_setup = bnxt_tx_queue_setup_op,
3837         .tx_queue_release = bnxt_tx_queue_release_op,
3838         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3839         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3840         .reta_update = bnxt_reta_update_op,
3841         .reta_query = bnxt_reta_query_op,
3842         .rss_hash_update = bnxt_rss_hash_update_op,
3843         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3844         .link_update = bnxt_link_update_op,
3845         .promiscuous_enable = bnxt_promiscuous_enable_op,
3846         .promiscuous_disable = bnxt_promiscuous_disable_op,
3847         .allmulticast_enable = bnxt_allmulticast_enable_op,
3848         .allmulticast_disable = bnxt_allmulticast_disable_op,
3849         .mac_addr_add = bnxt_mac_addr_add_op,
3850         .mac_addr_remove = bnxt_mac_addr_remove_op,
3851         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3852         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3853         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3854         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3855         .vlan_filter_set = bnxt_vlan_filter_set_op,
3856         .vlan_offload_set = bnxt_vlan_offload_set_op,
3857         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3858         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3859         .mtu_set = bnxt_mtu_set_op,
3860         .mac_addr_set = bnxt_set_default_mac_addr_op,
3861         .xstats_get = bnxt_dev_xstats_get_op,
3862         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3863         .xstats_reset = bnxt_dev_xstats_reset_op,
3864         .fw_version_get = bnxt_fw_version_get,
3865         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3866         .rxq_info_get = bnxt_rxq_info_get_op,
3867         .txq_info_get = bnxt_txq_info_get_op,
3868         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
3869         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
3870         .dev_led_on = bnxt_dev_led_on_op,
3871         .dev_led_off = bnxt_dev_led_off_op,
3872         .rx_queue_start = bnxt_rx_queue_start,
3873         .rx_queue_stop = bnxt_rx_queue_stop,
3874         .tx_queue_start = bnxt_tx_queue_start,
3875         .tx_queue_stop = bnxt_tx_queue_stop,
3876         .flow_ops_get = bnxt_flow_ops_get_op,
3877         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3878         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3879         .get_eeprom           = bnxt_get_eeprom_op,
3880         .set_eeprom           = bnxt_set_eeprom_op,
3881         .timesync_enable      = bnxt_timesync_enable,
3882         .timesync_disable     = bnxt_timesync_disable,
3883         .timesync_read_time   = bnxt_timesync_read_time,
3884         .timesync_write_time   = bnxt_timesync_write_time,
3885         .timesync_adjust_time = bnxt_timesync_adjust_time,
3886         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3887         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3888 };
3889
3890 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3891 {
3892         uint32_t offset;
3893
3894         /* Only pre-map the reset GRC registers using window 3 */
3895         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3896                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3897
3898         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3899
3900         return offset;
3901 }
3902
3903 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3904 {
3905         struct bnxt_error_recovery_info *info = bp->recovery_info;
3906         uint32_t reg_base = 0xffffffff;
3907         int i;
3908
3909         /* Only pre-map the monitoring GRC registers using window 2 */
3910         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3911                 uint32_t reg = info->status_regs[i];
3912
3913                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3914                         continue;
3915
3916                 if (reg_base == 0xffffffff)
3917                         reg_base = reg & 0xfffff000;
3918                 if ((reg & 0xfffff000) != reg_base)
3919                         return -ERANGE;
3920
3921                 /* Use mask 0xffc as the Lower 2 bits indicates
3922                  * address space location
3923                  */
3924                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3925                                                 (reg & 0xffc);
3926         }
3927
3928         if (reg_base == 0xffffffff)
3929                 return 0;
3930
3931         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3932                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3933
3934         return 0;
3935 }
3936
3937 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3938 {
3939         struct bnxt_error_recovery_info *info = bp->recovery_info;
3940         uint32_t delay = info->delay_after_reset[index];
3941         uint32_t val = info->reset_reg_val[index];
3942         uint32_t reg = info->reset_reg[index];
3943         uint32_t type, offset;
3944         int ret;
3945
3946         type = BNXT_FW_STATUS_REG_TYPE(reg);
3947         offset = BNXT_FW_STATUS_REG_OFF(reg);
3948
3949         switch (type) {
3950         case BNXT_FW_STATUS_REG_TYPE_CFG:
3951                 ret = rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3952                 if (ret < 0) {
3953                         PMD_DRV_LOG(ERR, "Failed to write %#x at PCI offset %#x",
3954                                     val, offset);
3955                         return;
3956                 }
3957                 break;
3958         case BNXT_FW_STATUS_REG_TYPE_GRC:
3959                 offset = bnxt_map_reset_regs(bp, offset);
3960                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3961                 break;
3962         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3963                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3964                 break;
3965         }
3966         /* wait on a specific interval of time until core reset is complete */
3967         if (delay)
3968                 rte_delay_ms(delay);
3969 }
3970
3971 static void bnxt_dev_cleanup(struct bnxt *bp)
3972 {
3973         bp->eth_dev->data->dev_link.link_status = 0;
3974         bp->link_info->link_up = 0;
3975         if (bp->eth_dev->data->dev_started)
3976                 bnxt_dev_stop(bp->eth_dev);
3977
3978         bnxt_uninit_resources(bp, true);
3979 }
3980
3981 static int
3982 bnxt_check_fw_reset_done(struct bnxt *bp)
3983 {
3984         int timeout = bp->fw_reset_max_msecs;
3985         uint16_t val = 0;
3986         int rc;
3987
3988         do {
3989                 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
3990                 if (rc < 0) {
3991                         PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
3992                         return rc;
3993                 }
3994                 if (val != 0xffff)
3995                         break;
3996                 rte_delay_ms(1);
3997         } while (timeout--);
3998
3999         if (val == 0xffff) {
4000                 PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n");
4001                 return -1;
4002         }
4003
4004         return 0;
4005 }
4006
4007 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4008 {
4009         struct rte_eth_dev *dev = bp->eth_dev;
4010         struct rte_vlan_filter_conf *vfc;
4011         int vidx, vbit, rc;
4012         uint16_t vlan_id;
4013
4014         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4015                 vfc = &dev->data->vlan_filter_conf;
4016                 vidx = vlan_id / 64;
4017                 vbit = vlan_id % 64;
4018
4019                 /* Each bit corresponds to a VLAN id */
4020                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4021                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4022                         if (rc)
4023                                 return rc;
4024                 }
4025         }
4026
4027         return 0;
4028 }
4029
4030 static int bnxt_restore_mac_filters(struct bnxt *bp)
4031 {
4032         struct rte_eth_dev *dev = bp->eth_dev;
4033         struct rte_eth_dev_info dev_info;
4034         struct rte_ether_addr *addr;
4035         uint64_t pool_mask;
4036         uint32_t pool = 0;
4037         uint32_t i;
4038         int rc;
4039
4040         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4041                 return 0;
4042
4043         rc = bnxt_dev_info_get_op(dev, &dev_info);
4044         if (rc)
4045                 return rc;
4046
4047         /* replay MAC address configuration */
4048         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4049                 addr = &dev->data->mac_addrs[i];
4050
4051                 /* skip zero address */
4052                 if (rte_is_zero_ether_addr(addr))
4053                         continue;
4054
4055                 pool = 0;
4056                 pool_mask = dev->data->mac_pool_sel[i];
4057
4058                 do {
4059                         if (pool_mask & 1ULL) {
4060                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4061                                 if (rc)
4062                                         return rc;
4063                         }
4064                         pool_mask >>= 1;
4065                         pool++;
4066                 } while (pool_mask);
4067         }
4068
4069         return 0;
4070 }
4071
4072 static int bnxt_restore_filters(struct bnxt *bp)
4073 {
4074         struct rte_eth_dev *dev = bp->eth_dev;
4075         int ret = 0;
4076
4077         if (dev->data->all_multicast) {
4078                 ret = bnxt_allmulticast_enable_op(dev);
4079                 if (ret)
4080                         return ret;
4081         }
4082         if (dev->data->promiscuous) {
4083                 ret = bnxt_promiscuous_enable_op(dev);
4084                 if (ret)
4085                         return ret;
4086         }
4087
4088         ret = bnxt_restore_mac_filters(bp);
4089         if (ret)
4090                 return ret;
4091
4092         ret = bnxt_restore_vlan_filters(bp);
4093         /* TODO restore other filters as well */
4094         return ret;
4095 }
4096
4097 static int bnxt_check_fw_ready(struct bnxt *bp)
4098 {
4099         int timeout = bp->fw_reset_max_msecs;
4100         int rc = 0;
4101
4102         do {
4103                 rc = bnxt_hwrm_poll_ver_get(bp);
4104                 if (rc == 0)
4105                         break;
4106                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4107                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4108         } while (rc && timeout > 0);
4109
4110         if (rc)
4111                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4112
4113         return rc;
4114 }
4115
4116 static void bnxt_dev_recover(void *arg)
4117 {
4118         struct bnxt *bp = arg;
4119         int rc = 0;
4120
4121         pthread_mutex_lock(&bp->err_recovery_lock);
4122
4123         if (!bp->fw_reset_min_msecs) {
4124                 rc = bnxt_check_fw_reset_done(bp);
4125                 if (rc)
4126                         goto err;
4127         }
4128
4129         /* Clear Error flag so that device re-init should happen */
4130         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4131
4132         rc = bnxt_check_fw_ready(bp);
4133         if (rc)
4134                 goto err;
4135
4136         rc = bnxt_init_resources(bp, true);
4137         if (rc) {
4138                 PMD_DRV_LOG(ERR,
4139                             "Failed to initialize resources after reset\n");
4140                 goto err;
4141         }
4142         /* clear reset flag as the device is initialized now */
4143         bp->flags &= ~BNXT_FLAG_FW_RESET;
4144
4145         rc = bnxt_dev_start_op(bp->eth_dev);
4146         if (rc) {
4147                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4148                 goto err_start;
4149         }
4150
4151         rc = bnxt_restore_filters(bp);
4152         if (rc)
4153                 goto err_start;
4154
4155         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4156         pthread_mutex_unlock(&bp->err_recovery_lock);
4157
4158         return;
4159 err_start:
4160         bnxt_dev_stop(bp->eth_dev);
4161 err:
4162         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4163         bnxt_uninit_resources(bp, false);
4164         pthread_mutex_unlock(&bp->err_recovery_lock);
4165         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4166 }
4167
4168 void bnxt_dev_reset_and_resume(void *arg)
4169 {
4170         struct bnxt *bp = arg;
4171         uint32_t us = US_PER_MS * bp->fw_reset_min_msecs;
4172         uint16_t val = 0;
4173         int rc;
4174
4175         bnxt_dev_cleanup(bp);
4176
4177         bnxt_wait_for_device_shutdown(bp);
4178
4179         /* During some fatal firmware error conditions, the PCI config space
4180          * register 0x2e which normally contains the subsystem ID will become
4181          * 0xffff. This register will revert back to the normal value after
4182          * the chip has completed core reset. If we detect this condition,
4183          * we can poll this config register immediately for the value to revert.
4184          */
4185         if (bp->flags & BNXT_FLAG_FATAL_ERROR) {
4186                 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4187                 if (rc < 0) {
4188                         PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4189                         return;
4190                 }
4191                 if (val == 0xffff) {
4192                         bp->fw_reset_min_msecs = 0;
4193                         us = 1;
4194                 }
4195         }
4196
4197         rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp);
4198         if (rc)
4199                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4200 }
4201
4202 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4203 {
4204         struct bnxt_error_recovery_info *info = bp->recovery_info;
4205         uint32_t reg = info->status_regs[index];
4206         uint32_t type, offset, val = 0;
4207         int ret = 0;
4208
4209         type = BNXT_FW_STATUS_REG_TYPE(reg);
4210         offset = BNXT_FW_STATUS_REG_OFF(reg);
4211
4212         switch (type) {
4213         case BNXT_FW_STATUS_REG_TYPE_CFG:
4214                 ret = rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4215                 if (ret < 0)
4216                         PMD_DRV_LOG(ERR, "Failed to read PCI offset %#x",
4217                                     offset);
4218                 break;
4219         case BNXT_FW_STATUS_REG_TYPE_GRC:
4220                 offset = info->mapped_status_regs[index];
4221                 /* FALLTHROUGH */
4222         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4223                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4224                                        offset));
4225                 break;
4226         }
4227
4228         return val;
4229 }
4230
4231 static int bnxt_fw_reset_all(struct bnxt *bp)
4232 {
4233         struct bnxt_error_recovery_info *info = bp->recovery_info;
4234         uint32_t i;
4235         int rc = 0;
4236
4237         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4238                 /* Reset through master function driver */
4239                 for (i = 0; i < info->reg_array_cnt; i++)
4240                         bnxt_write_fw_reset_reg(bp, i);
4241                 /* Wait for time specified by FW after triggering reset */
4242                 rte_delay_ms(info->master_func_wait_period_after_reset);
4243         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4244                 /* Reset with the help of Kong processor */
4245                 rc = bnxt_hwrm_fw_reset(bp);
4246                 if (rc)
4247                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4248         }
4249
4250         return rc;
4251 }
4252
4253 static void bnxt_fw_reset_cb(void *arg)
4254 {
4255         struct bnxt *bp = arg;
4256         struct bnxt_error_recovery_info *info = bp->recovery_info;
4257         int rc = 0;
4258
4259         /* Only Master function can do FW reset */
4260         if (bnxt_is_master_func(bp) &&
4261             bnxt_is_recovery_enabled(bp)) {
4262                 rc = bnxt_fw_reset_all(bp);
4263                 if (rc) {
4264                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4265                         return;
4266                 }
4267         }
4268
4269         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4270          * EXCEPTION_FATAL_ASYNC event to all the functions
4271          * (including MASTER FUNC). After receiving this Async, all the active
4272          * drivers should treat this case as FW initiated recovery
4273          */
4274         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4275                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4276                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4277
4278                 /* To recover from error */
4279                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4280                                   (void *)bp);
4281         }
4282 }
4283
4284 /* Driver should poll FW heartbeat, reset_counter with the frequency
4285  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4286  * When the driver detects heartbeat stop or change in reset_counter,
4287  * it has to trigger a reset to recover from the error condition.
4288  * A “master PF” is the function who will have the privilege to
4289  * initiate the chimp reset. The master PF will be elected by the
4290  * firmware and will be notified through async message.
4291  */
4292 static void bnxt_check_fw_health(void *arg)
4293 {
4294         struct bnxt *bp = arg;
4295         struct bnxt_error_recovery_info *info = bp->recovery_info;
4296         uint32_t val = 0, wait_msec;
4297
4298         if (!info || !bnxt_is_recovery_enabled(bp) ||
4299             is_bnxt_in_error(bp))
4300                 return;
4301
4302         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4303         if (val == info->last_heart_beat)
4304                 goto reset;
4305
4306         info->last_heart_beat = val;
4307
4308         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4309         if (val != info->last_reset_counter)
4310                 goto reset;
4311
4312         info->last_reset_counter = val;
4313
4314         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4315                           bnxt_check_fw_health, (void *)bp);
4316
4317         return;
4318 reset:
4319         /* Stop DMA to/from device */
4320         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4321         bp->flags |= BNXT_FLAG_FW_RESET;
4322
4323         bnxt_stop_rxtx(bp);
4324
4325         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4326
4327         if (bnxt_is_master_func(bp))
4328                 wait_msec = info->master_func_wait_period;
4329         else
4330                 wait_msec = info->normal_func_wait_period;
4331
4332         rte_eal_alarm_set(US_PER_MS * wait_msec,
4333                           bnxt_fw_reset_cb, (void *)bp);
4334 }
4335
4336 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4337 {
4338         uint32_t polling_freq;
4339
4340         pthread_mutex_lock(&bp->health_check_lock);
4341
4342         if (!bnxt_is_recovery_enabled(bp))
4343                 goto done;
4344
4345         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4346                 goto done;
4347
4348         polling_freq = bp->recovery_info->driver_polling_freq;
4349
4350         rte_eal_alarm_set(US_PER_MS * polling_freq,
4351                           bnxt_check_fw_health, (void *)bp);
4352         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4353
4354 done:
4355         pthread_mutex_unlock(&bp->health_check_lock);
4356 }
4357
4358 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4359 {
4360         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4361         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4362 }
4363
4364 static bool bnxt_vf_pciid(uint16_t device_id)
4365 {
4366         switch (device_id) {
4367         case BROADCOM_DEV_ID_57304_VF:
4368         case BROADCOM_DEV_ID_57406_VF:
4369         case BROADCOM_DEV_ID_5731X_VF:
4370         case BROADCOM_DEV_ID_5741X_VF:
4371         case BROADCOM_DEV_ID_57414_VF:
4372         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4373         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4374         case BROADCOM_DEV_ID_58802_VF:
4375         case BROADCOM_DEV_ID_57500_VF1:
4376         case BROADCOM_DEV_ID_57500_VF2:
4377         case BROADCOM_DEV_ID_58818_VF:
4378                 /* FALLTHROUGH */
4379                 return true;
4380         default:
4381                 return false;
4382         }
4383 }
4384
4385 /* Phase 5 device */
4386 static bool bnxt_p5_device(uint16_t device_id)
4387 {
4388         switch (device_id) {
4389         case BROADCOM_DEV_ID_57508:
4390         case BROADCOM_DEV_ID_57504:
4391         case BROADCOM_DEV_ID_57502:
4392         case BROADCOM_DEV_ID_57508_MF1:
4393         case BROADCOM_DEV_ID_57504_MF1:
4394         case BROADCOM_DEV_ID_57502_MF1:
4395         case BROADCOM_DEV_ID_57508_MF2:
4396         case BROADCOM_DEV_ID_57504_MF2:
4397         case BROADCOM_DEV_ID_57502_MF2:
4398         case BROADCOM_DEV_ID_57500_VF1:
4399         case BROADCOM_DEV_ID_57500_VF2:
4400         case BROADCOM_DEV_ID_58812:
4401         case BROADCOM_DEV_ID_58814:
4402         case BROADCOM_DEV_ID_58818:
4403         case BROADCOM_DEV_ID_58818_VF:
4404                 /* FALLTHROUGH */
4405                 return true;
4406         default:
4407                 return false;
4408         }
4409 }
4410
4411 bool bnxt_stratus_device(struct bnxt *bp)
4412 {
4413         uint16_t device_id = bp->pdev->id.device_id;
4414
4415         switch (device_id) {
4416         case BROADCOM_DEV_ID_STRATUS_NIC:
4417         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4418         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4419                 /* FALLTHROUGH */
4420                 return true;
4421         default:
4422                 return false;
4423         }
4424 }
4425
4426 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev)
4427 {
4428         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4429         struct bnxt *bp = eth_dev->data->dev_private;
4430
4431         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4432         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4433         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4434         if (!bp->bar0 || !bp->doorbell_base) {
4435                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4436                 return -ENODEV;
4437         }
4438
4439         bp->eth_dev = eth_dev;
4440         bp->pdev = pci_dev;
4441
4442         return 0;
4443 }
4444
4445 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4446                                   struct bnxt_ctx_pg_info *ctx_pg,
4447                                   uint32_t mem_size,
4448                                   const char *suffix,
4449                                   uint16_t idx)
4450 {
4451         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4452         const struct rte_memzone *mz = NULL;
4453         char mz_name[RTE_MEMZONE_NAMESIZE];
4454         rte_iova_t mz_phys_addr;
4455         uint64_t valid_bits = 0;
4456         uint32_t sz;
4457         int i;
4458
4459         if (!mem_size)
4460                 return 0;
4461
4462         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4463                          BNXT_PAGE_SIZE;
4464         rmem->page_size = BNXT_PAGE_SIZE;
4465         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4466         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4467         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4468
4469         valid_bits = PTU_PTE_VALID;
4470
4471         if (rmem->nr_pages > 1) {
4472                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4473                          "bnxt_ctx_pg_tbl%s_%x_%d",
4474                          suffix, idx, bp->eth_dev->data->port_id);
4475                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4476                 mz = rte_memzone_lookup(mz_name);
4477                 if (!mz) {
4478                         mz = rte_memzone_reserve_aligned(mz_name,
4479                                                 rmem->nr_pages * 8,
4480                                                 SOCKET_ID_ANY,
4481                                                 RTE_MEMZONE_2MB |
4482                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4483                                                 RTE_MEMZONE_IOVA_CONTIG,
4484                                                 BNXT_PAGE_SIZE);
4485                         if (mz == NULL)
4486                                 return -ENOMEM;
4487                 }
4488
4489                 memset(mz->addr, 0, mz->len);
4490                 mz_phys_addr = mz->iova;
4491
4492                 rmem->pg_tbl = mz->addr;
4493                 rmem->pg_tbl_map = mz_phys_addr;
4494                 rmem->pg_tbl_mz = mz;
4495         }
4496
4497         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4498                  suffix, idx, bp->eth_dev->data->port_id);
4499         mz = rte_memzone_lookup(mz_name);
4500         if (!mz) {
4501                 mz = rte_memzone_reserve_aligned(mz_name,
4502                                                  mem_size,
4503                                                  SOCKET_ID_ANY,
4504                                                  RTE_MEMZONE_1GB |
4505                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4506                                                  RTE_MEMZONE_IOVA_CONTIG,
4507                                                  BNXT_PAGE_SIZE);
4508                 if (mz == NULL)
4509                         return -ENOMEM;
4510         }
4511
4512         memset(mz->addr, 0, mz->len);
4513         mz_phys_addr = mz->iova;
4514
4515         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4516                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4517                 rmem->dma_arr[i] = mz_phys_addr + sz;
4518
4519                 if (rmem->nr_pages > 1) {
4520                         if (i == rmem->nr_pages - 2 &&
4521                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4522                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4523                         else if (i == rmem->nr_pages - 1 &&
4524                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4525                                 valid_bits |= PTU_PTE_LAST;
4526
4527                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4528                                                            valid_bits);
4529                 }
4530         }
4531
4532         rmem->mz = mz;
4533         if (rmem->vmem_size)
4534                 rmem->vmem = (void **)mz->addr;
4535         rmem->dma_arr[0] = mz_phys_addr;
4536         return 0;
4537 }
4538
4539 static void bnxt_free_ctx_mem(struct bnxt *bp)
4540 {
4541         int i;
4542
4543         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4544                 return;
4545
4546         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4547         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4548         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4549         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4550         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4551         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4552         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4553         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4554         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4555         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4556         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4557
4558         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4559                 if (bp->ctx->tqm_mem[i])
4560                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4561         }
4562
4563         rte_free(bp->ctx);
4564         bp->ctx = NULL;
4565 }
4566
4567 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4568
4569 #define min_t(type, x, y) ({                    \
4570         type __min1 = (x);                      \
4571         type __min2 = (y);                      \
4572         __min1 < __min2 ? __min1 : __min2; })
4573
4574 #define max_t(type, x, y) ({                    \
4575         type __max1 = (x);                      \
4576         type __max2 = (y);                      \
4577         __max1 > __max2 ? __max1 : __max2; })
4578
4579 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4580
4581 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4582 {
4583         struct bnxt_ctx_pg_info *ctx_pg;
4584         struct bnxt_ctx_mem_info *ctx;
4585         uint32_t mem_size, ena, entries;
4586         uint32_t entries_sp, min;
4587         int i, rc;
4588
4589         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4590         if (rc) {
4591                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4592                 return rc;
4593         }
4594         ctx = bp->ctx;
4595         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4596                 return 0;
4597
4598         ctx_pg = &ctx->qp_mem;
4599         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4600         if (ctx->qp_entry_size) {
4601                 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4602                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4603                 if (rc)
4604                         return rc;
4605         }
4606
4607         ctx_pg = &ctx->srq_mem;
4608         ctx_pg->entries = ctx->srq_max_l2_entries;
4609         if (ctx->srq_entry_size) {
4610                 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4611                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4612                 if (rc)
4613                         return rc;
4614         }
4615
4616         ctx_pg = &ctx->cq_mem;
4617         ctx_pg->entries = ctx->cq_max_l2_entries;
4618         if (ctx->cq_entry_size) {
4619                 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4620                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4621                 if (rc)
4622                         return rc;
4623         }
4624
4625         ctx_pg = &ctx->vnic_mem;
4626         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4627                 ctx->vnic_max_ring_table_entries;
4628         if (ctx->vnic_entry_size) {
4629                 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4630                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4631                 if (rc)
4632                         return rc;
4633         }
4634
4635         ctx_pg = &ctx->stat_mem;
4636         ctx_pg->entries = ctx->stat_max_entries;
4637         if (ctx->stat_entry_size) {
4638                 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4639                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4640                 if (rc)
4641                         return rc;
4642         }
4643
4644         min = ctx->tqm_min_entries_per_ring;
4645
4646         entries_sp = ctx->qp_max_l2_entries +
4647                      ctx->vnic_max_vnic_entries +
4648                      2 * ctx->qp_min_qp1_entries + min;
4649         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4650
4651         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4652         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4653         entries = clamp_t(uint32_t, entries, min,
4654                           ctx->tqm_max_entries_per_ring);
4655         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4656                 /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7.
4657                  * i > 8 is other ext rings.
4658                  */
4659                 ctx_pg = ctx->tqm_mem[i];
4660                 ctx_pg->entries = i ? entries : entries_sp;
4661                 if (ctx->tqm_entry_size) {
4662                         mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4663                         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size,
4664                                                     "tqm_mem", i);
4665                         if (rc)
4666                                 return rc;
4667                 }
4668                 if (i < BNXT_MAX_TQM_LEGACY_RINGS)
4669                         ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4670                 else
4671                         ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8;
4672         }
4673
4674         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4675         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4676         if (rc)
4677                 PMD_DRV_LOG(ERR,
4678                             "Failed to configure context mem: rc = %d\n", rc);
4679         else
4680                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4681
4682         return rc;
4683 }
4684
4685 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4686 {
4687         struct rte_pci_device *pci_dev = bp->pdev;
4688         char mz_name[RTE_MEMZONE_NAMESIZE];
4689         const struct rte_memzone *mz = NULL;
4690         uint32_t total_alloc_len;
4691         rte_iova_t mz_phys_addr;
4692
4693         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4694                 return 0;
4695
4696         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4697                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4698                  pci_dev->addr.bus, pci_dev->addr.devid,
4699                  pci_dev->addr.function, "rx_port_stats");
4700         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4701         mz = rte_memzone_lookup(mz_name);
4702         total_alloc_len =
4703                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4704                                        sizeof(struct rx_port_stats_ext) + 512);
4705         if (!mz) {
4706                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4707                                          SOCKET_ID_ANY,
4708                                          RTE_MEMZONE_2MB |
4709                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4710                                          RTE_MEMZONE_IOVA_CONTIG);
4711                 if (mz == NULL)
4712                         return -ENOMEM;
4713         }
4714         memset(mz->addr, 0, mz->len);
4715         mz_phys_addr = mz->iova;
4716
4717         bp->rx_mem_zone = (const void *)mz;
4718         bp->hw_rx_port_stats = mz->addr;
4719         bp->hw_rx_port_stats_map = mz_phys_addr;
4720
4721         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4722                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4723                  pci_dev->addr.bus, pci_dev->addr.devid,
4724                  pci_dev->addr.function, "tx_port_stats");
4725         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4726         mz = rte_memzone_lookup(mz_name);
4727         total_alloc_len =
4728                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4729                                        sizeof(struct tx_port_stats_ext) + 512);
4730         if (!mz) {
4731                 mz = rte_memzone_reserve(mz_name,
4732                                          total_alloc_len,
4733                                          SOCKET_ID_ANY,
4734                                          RTE_MEMZONE_2MB |
4735                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4736                                          RTE_MEMZONE_IOVA_CONTIG);
4737                 if (mz == NULL)
4738                         return -ENOMEM;
4739         }
4740         memset(mz->addr, 0, mz->len);
4741         mz_phys_addr = mz->iova;
4742
4743         bp->tx_mem_zone = (const void *)mz;
4744         bp->hw_tx_port_stats = mz->addr;
4745         bp->hw_tx_port_stats_map = mz_phys_addr;
4746         bp->flags |= BNXT_FLAG_PORT_STATS;
4747
4748         /* Display extended statistics if FW supports it */
4749         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4750             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4751             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4752                 return 0;
4753
4754         bp->hw_rx_port_stats_ext = (void *)
4755                 ((uint8_t *)bp->hw_rx_port_stats +
4756                  sizeof(struct rx_port_stats));
4757         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4758                 sizeof(struct rx_port_stats);
4759         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4760
4761         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4762             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4763                 bp->hw_tx_port_stats_ext = (void *)
4764                         ((uint8_t *)bp->hw_tx_port_stats +
4765                          sizeof(struct tx_port_stats));
4766                 bp->hw_tx_port_stats_ext_map =
4767                         bp->hw_tx_port_stats_map +
4768                         sizeof(struct tx_port_stats);
4769                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4770         }
4771
4772         return 0;
4773 }
4774
4775 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4776 {
4777         struct bnxt *bp = eth_dev->data->dev_private;
4778         int rc = 0;
4779
4780         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4781                                                RTE_ETHER_ADDR_LEN *
4782                                                bp->max_l2_ctx,
4783                                                0);
4784         if (eth_dev->data->mac_addrs == NULL) {
4785                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4786                 return -ENOMEM;
4787         }
4788
4789         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4790                 if (BNXT_PF(bp))
4791                         return -EINVAL;
4792
4793                 /* Generate a random MAC address, if none was assigned by PF */
4794                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4795                 bnxt_eth_hw_addr_random(bp->mac_addr);
4796                 PMD_DRV_LOG(INFO,
4797                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4798                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4799                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4800
4801                 rc = bnxt_hwrm_set_mac(bp);
4802                 if (rc)
4803                         return rc;
4804         }
4805
4806         /* Copy the permanent MAC from the FUNC_QCAPS response */
4807         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4808
4809         return rc;
4810 }
4811
4812 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4813 {
4814         int rc = 0;
4815
4816         /* MAC is already configured in FW */
4817         if (BNXT_HAS_DFLT_MAC_SET(bp))
4818                 return 0;
4819
4820         /* Restore the old MAC configured */
4821         rc = bnxt_hwrm_set_mac(bp);
4822         if (rc)
4823                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4824
4825         return rc;
4826 }
4827
4828 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4829 {
4830         if (!BNXT_PF(bp))
4831                 return;
4832
4833         memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
4834
4835         if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
4836                 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
4837         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
4838         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
4839         BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
4840         BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
4841 }
4842
4843 uint16_t
4844 bnxt_get_svif(uint16_t port_id, bool func_svif,
4845               enum bnxt_ulp_intf_type type)
4846 {
4847         struct rte_eth_dev *eth_dev;
4848         struct bnxt *bp;
4849
4850         eth_dev = &rte_eth_devices[port_id];
4851         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4852                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4853                 if (!vfr)
4854                         return 0;
4855
4856                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4857                         return vfr->svif;
4858
4859                 eth_dev = vfr->parent_dev;
4860         }
4861
4862         bp = eth_dev->data->dev_private;
4863
4864         return func_svif ? bp->func_svif : bp->port_svif;
4865 }
4866
4867 uint16_t
4868 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
4869 {
4870         struct rte_eth_dev *eth_dev;
4871         struct bnxt_vnic_info *vnic;
4872         struct bnxt *bp;
4873
4874         eth_dev = &rte_eth_devices[port];
4875         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4876                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4877                 if (!vfr)
4878                         return 0;
4879
4880                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4881                         return vfr->dflt_vnic_id;
4882
4883                 eth_dev = vfr->parent_dev;
4884         }
4885
4886         bp = eth_dev->data->dev_private;
4887
4888         vnic = BNXT_GET_DEFAULT_VNIC(bp);
4889
4890         return vnic->fw_vnic_id;
4891 }
4892
4893 uint16_t
4894 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
4895 {
4896         struct rte_eth_dev *eth_dev;
4897         struct bnxt *bp;
4898
4899         eth_dev = &rte_eth_devices[port];
4900         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4901                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4902                 if (!vfr)
4903                         return 0;
4904
4905                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4906                         return vfr->fw_fid;
4907
4908                 eth_dev = vfr->parent_dev;
4909         }
4910
4911         bp = eth_dev->data->dev_private;
4912
4913         return bp->fw_fid;
4914 }
4915
4916 enum bnxt_ulp_intf_type
4917 bnxt_get_interface_type(uint16_t port)
4918 {
4919         struct rte_eth_dev *eth_dev;
4920         struct bnxt *bp;
4921
4922         eth_dev = &rte_eth_devices[port];
4923         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
4924                 return BNXT_ULP_INTF_TYPE_VF_REP;
4925
4926         bp = eth_dev->data->dev_private;
4927         if (BNXT_PF(bp))
4928                 return BNXT_ULP_INTF_TYPE_PF;
4929         else if (BNXT_VF_IS_TRUSTED(bp))
4930                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
4931         else if (BNXT_VF(bp))
4932                 return BNXT_ULP_INTF_TYPE_VF;
4933
4934         return BNXT_ULP_INTF_TYPE_INVALID;
4935 }
4936
4937 uint16_t
4938 bnxt_get_phy_port_id(uint16_t port_id)
4939 {
4940         struct bnxt_representor *vfr;
4941         struct rte_eth_dev *eth_dev;
4942         struct bnxt *bp;
4943
4944         eth_dev = &rte_eth_devices[port_id];
4945         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4946                 vfr = eth_dev->data->dev_private;
4947                 if (!vfr)
4948                         return 0;
4949
4950                 eth_dev = vfr->parent_dev;
4951         }
4952
4953         bp = eth_dev->data->dev_private;
4954
4955         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
4956 }
4957
4958 uint16_t
4959 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
4960 {
4961         struct rte_eth_dev *eth_dev;
4962         struct bnxt *bp;
4963
4964         eth_dev = &rte_eth_devices[port_id];
4965         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4966                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4967                 if (!vfr)
4968                         return 0;
4969
4970                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4971                         return vfr->fw_fid - 1;
4972
4973                 eth_dev = vfr->parent_dev;
4974         }
4975
4976         bp = eth_dev->data->dev_private;
4977
4978         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
4979 }
4980
4981 uint16_t
4982 bnxt_get_vport(uint16_t port_id)
4983 {
4984         return (1 << bnxt_get_phy_port_id(port_id));
4985 }
4986
4987 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
4988 {
4989         struct bnxt_error_recovery_info *info = bp->recovery_info;
4990
4991         if (info) {
4992                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
4993                         memset(info, 0, sizeof(*info));
4994                 return;
4995         }
4996
4997         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4998                 return;
4999
5000         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5001                            sizeof(*info), 0);
5002         if (!info)
5003                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5004
5005         bp->recovery_info = info;
5006 }
5007
5008 static void bnxt_check_fw_status(struct bnxt *bp)
5009 {
5010         uint32_t fw_status;
5011
5012         if (!(bp->recovery_info &&
5013               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5014                 return;
5015
5016         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5017         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5018                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5019                             fw_status);
5020 }
5021
5022 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5023 {
5024         struct bnxt_error_recovery_info *info = bp->recovery_info;
5025         uint32_t status_loc;
5026         uint32_t sig_ver;
5027
5028         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5029                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5030         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5031                                    BNXT_GRCP_WINDOW_2_BASE +
5032                                    offsetof(struct hcomm_status,
5033                                             sig_ver)));
5034         /* If the signature is absent, then FW does not support this feature */
5035         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5036             HCOMM_STATUS_SIGNATURE_VAL)
5037                 return 0;
5038
5039         if (!info) {
5040                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5041                                    sizeof(*info), 0);
5042                 if (!info)
5043                         return -ENOMEM;
5044                 bp->recovery_info = info;
5045         } else {
5046                 memset(info, 0, sizeof(*info));
5047         }
5048
5049         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5050                                       BNXT_GRCP_WINDOW_2_BASE +
5051                                       offsetof(struct hcomm_status,
5052                                                fw_status_loc)));
5053
5054         /* Only pre-map the FW health status GRC register */
5055         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5056                 return 0;
5057
5058         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5059         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5060                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5061
5062         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5063                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5064
5065         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5066
5067         return 0;
5068 }
5069
5070 /* This function gets the FW version along with the
5071  * capabilities(MAX and current) of the function, vnic,
5072  * error recovery, phy and other chip related info
5073  */
5074 static int bnxt_get_config(struct bnxt *bp)
5075 {
5076         uint16_t mtu;
5077         int rc = 0;
5078
5079         bp->fw_cap = 0;
5080
5081         rc = bnxt_map_hcomm_fw_status_reg(bp);
5082         if (rc)
5083                 return rc;
5084
5085         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5086         if (rc) {
5087                 bnxt_check_fw_status(bp);
5088                 return rc;
5089         }
5090
5091         rc = bnxt_hwrm_func_reset(bp);
5092         if (rc)
5093                 return -EIO;
5094
5095         rc = bnxt_hwrm_vnic_qcaps(bp);
5096         if (rc)
5097                 return rc;
5098
5099         rc = bnxt_hwrm_queue_qportcfg(bp);
5100         if (rc)
5101                 return rc;
5102
5103         /* Get the MAX capabilities for this function.
5104          * This function also allocates context memory for TQM rings and
5105          * informs the firmware about this allocated backing store memory.
5106          */
5107         rc = bnxt_hwrm_func_qcaps(bp);
5108         if (rc)
5109                 return rc;
5110
5111         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5112         if (rc)
5113                 return rc;
5114
5115         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5116         if (rc)
5117                 return rc;
5118
5119         bnxt_hwrm_port_mac_qcfg(bp);
5120
5121         bnxt_hwrm_parent_pf_qcfg(bp);
5122
5123         bnxt_hwrm_port_phy_qcaps(bp);
5124
5125         bnxt_alloc_error_recovery_info(bp);
5126         /* Get the adapter error recovery support info */
5127         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5128         if (rc)
5129                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5130
5131         bnxt_hwrm_port_led_qcaps(bp);
5132
5133         return 0;
5134 }
5135
5136 static int
5137 bnxt_init_locks(struct bnxt *bp)
5138 {
5139         int err;
5140
5141         err = pthread_mutex_init(&bp->flow_lock, NULL);
5142         if (err) {
5143                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5144                 return err;
5145         }
5146
5147         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5148         if (err) {
5149                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5150                 return err;
5151         }
5152
5153         err = pthread_mutex_init(&bp->health_check_lock, NULL);
5154         if (err) {
5155                 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5156                 return err;
5157         }
5158
5159         err = pthread_mutex_init(&bp->err_recovery_lock, NULL);
5160         if (err)
5161                 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n");
5162
5163         return err;
5164 }
5165
5166 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5167 {
5168         int rc = 0;
5169
5170         rc = bnxt_get_config(bp);
5171         if (rc)
5172                 return rc;
5173
5174         if (!reconfig_dev) {
5175                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5176                 if (rc)
5177                         return rc;
5178         } else {
5179                 rc = bnxt_restore_dflt_mac(bp);
5180                 if (rc)
5181                         return rc;
5182         }
5183
5184         bnxt_config_vf_req_fwd(bp);
5185
5186         rc = bnxt_hwrm_func_driver_register(bp);
5187         if (rc) {
5188                 PMD_DRV_LOG(ERR, "Failed to register driver");
5189                 return -EBUSY;
5190         }
5191
5192         if (BNXT_PF(bp)) {
5193                 if (bp->pdev->max_vfs) {
5194                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5195                         if (rc) {
5196                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5197                                 return rc;
5198                         }
5199                 } else {
5200                         rc = bnxt_hwrm_allocate_pf_only(bp);
5201                         if (rc) {
5202                                 PMD_DRV_LOG(ERR,
5203                                             "Failed to allocate PF resources");
5204                                 return rc;
5205                         }
5206                 }
5207         }
5208
5209         rc = bnxt_alloc_mem(bp, reconfig_dev);
5210         if (rc)
5211                 return rc;
5212
5213         rc = bnxt_setup_int(bp);
5214         if (rc)
5215                 return rc;
5216
5217         rc = bnxt_request_int(bp);
5218         if (rc)
5219                 return rc;
5220
5221         rc = bnxt_init_ctx_mem(bp);
5222         if (rc) {
5223                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5224                 return rc;
5225         }
5226
5227         return 0;
5228 }
5229
5230 static int
5231 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5232                           const char *value, void *opaque_arg)
5233 {
5234         struct bnxt *bp = opaque_arg;
5235         unsigned long truflow;
5236         char *end = NULL;
5237
5238         if (!value || !opaque_arg) {
5239                 PMD_DRV_LOG(ERR,
5240                             "Invalid parameter passed to truflow devargs.\n");
5241                 return -EINVAL;
5242         }
5243
5244         truflow = strtoul(value, &end, 10);
5245         if (end == NULL || *end != '\0' ||
5246             (truflow == ULONG_MAX && errno == ERANGE)) {
5247                 PMD_DRV_LOG(ERR,
5248                             "Invalid parameter passed to truflow devargs.\n");
5249                 return -EINVAL;
5250         }
5251
5252         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5253                 PMD_DRV_LOG(ERR,
5254                             "Invalid value passed to truflow devargs.\n");
5255                 return -EINVAL;
5256         }
5257
5258         if (truflow) {
5259                 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5260                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5261         } else {
5262                 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
5263                 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
5264         }
5265
5266         return 0;
5267 }
5268
5269 static int
5270 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5271                              const char *value, void *opaque_arg)
5272 {
5273         struct bnxt *bp = opaque_arg;
5274         unsigned long flow_xstat;
5275         char *end = NULL;
5276
5277         if (!value || !opaque_arg) {
5278                 PMD_DRV_LOG(ERR,
5279                             "Invalid parameter passed to flow_xstat devarg.\n");
5280                 return -EINVAL;
5281         }
5282
5283         flow_xstat = strtoul(value, &end, 10);
5284         if (end == NULL || *end != '\0' ||
5285             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5286                 PMD_DRV_LOG(ERR,
5287                             "Invalid parameter passed to flow_xstat devarg.\n");
5288                 return -EINVAL;
5289         }
5290
5291         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5292                 PMD_DRV_LOG(ERR,
5293                             "Invalid value passed to flow_xstat devarg.\n");
5294                 return -EINVAL;
5295         }
5296
5297         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5298         if (BNXT_FLOW_XSTATS_EN(bp))
5299                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5300
5301         return 0;
5302 }
5303
5304 static int
5305 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5306                                         const char *value, void *opaque_arg)
5307 {
5308         struct bnxt *bp = opaque_arg;
5309         unsigned long max_num_kflows;
5310         char *end = NULL;
5311
5312         if (!value || !opaque_arg) {
5313                 PMD_DRV_LOG(ERR,
5314                         "Invalid parameter passed to max_num_kflows devarg.\n");
5315                 return -EINVAL;
5316         }
5317
5318         max_num_kflows = strtoul(value, &end, 10);
5319         if (end == NULL || *end != '\0' ||
5320                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5321                 PMD_DRV_LOG(ERR,
5322                         "Invalid parameter passed to max_num_kflows devarg.\n");
5323                 return -EINVAL;
5324         }
5325
5326         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5327                 PMD_DRV_LOG(ERR,
5328                         "Invalid value passed to max_num_kflows devarg.\n");
5329                 return -EINVAL;
5330         }
5331
5332         bp->max_num_kflows = max_num_kflows;
5333         if (bp->max_num_kflows)
5334                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5335                                 max_num_kflows);
5336
5337         return 0;
5338 }
5339
5340 static int
5341 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5342                             const char *value, void *opaque_arg)
5343 {
5344         struct bnxt_representor *vfr_bp = opaque_arg;
5345         unsigned long rep_is_pf;
5346         char *end = NULL;
5347
5348         if (!value || !opaque_arg) {
5349                 PMD_DRV_LOG(ERR,
5350                             "Invalid parameter passed to rep_is_pf devargs.\n");
5351                 return -EINVAL;
5352         }
5353
5354         rep_is_pf = strtoul(value, &end, 10);
5355         if (end == NULL || *end != '\0' ||
5356             (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5357                 PMD_DRV_LOG(ERR,
5358                             "Invalid parameter passed to rep_is_pf devargs.\n");
5359                 return -EINVAL;
5360         }
5361
5362         if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5363                 PMD_DRV_LOG(ERR,
5364                             "Invalid value passed to rep_is_pf devargs.\n");
5365                 return -EINVAL;
5366         }
5367
5368         vfr_bp->flags |= rep_is_pf;
5369         if (BNXT_REP_PF(vfr_bp))
5370                 PMD_DRV_LOG(INFO, "PF representor\n");
5371         else
5372                 PMD_DRV_LOG(INFO, "VF representor\n");
5373
5374         return 0;
5375 }
5376
5377 static int
5378 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5379                                const char *value, void *opaque_arg)
5380 {
5381         struct bnxt_representor *vfr_bp = opaque_arg;
5382         unsigned long rep_based_pf;
5383         char *end = NULL;
5384
5385         if (!value || !opaque_arg) {
5386                 PMD_DRV_LOG(ERR,
5387                             "Invalid parameter passed to rep_based_pf "
5388                             "devargs.\n");
5389                 return -EINVAL;
5390         }
5391
5392         rep_based_pf = strtoul(value, &end, 10);
5393         if (end == NULL || *end != '\0' ||
5394             (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5395                 PMD_DRV_LOG(ERR,
5396                             "Invalid parameter passed to rep_based_pf "
5397                             "devargs.\n");
5398                 return -EINVAL;
5399         }
5400
5401         if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5402                 PMD_DRV_LOG(ERR,
5403                             "Invalid value passed to rep_based_pf devargs.\n");
5404                 return -EINVAL;
5405         }
5406
5407         vfr_bp->rep_based_pf = rep_based_pf;
5408         vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
5409
5410         PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5411
5412         return 0;
5413 }
5414
5415 static int
5416 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5417                             const char *value, void *opaque_arg)
5418 {
5419         struct bnxt_representor *vfr_bp = opaque_arg;
5420         unsigned long rep_q_r2f;
5421         char *end = NULL;
5422
5423         if (!value || !opaque_arg) {
5424                 PMD_DRV_LOG(ERR,
5425                             "Invalid parameter passed to rep_q_r2f "
5426                             "devargs.\n");
5427                 return -EINVAL;
5428         }
5429
5430         rep_q_r2f = strtoul(value, &end, 10);
5431         if (end == NULL || *end != '\0' ||
5432             (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5433                 PMD_DRV_LOG(ERR,
5434                             "Invalid parameter passed to rep_q_r2f "
5435                             "devargs.\n");
5436                 return -EINVAL;
5437         }
5438
5439         if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5440                 PMD_DRV_LOG(ERR,
5441                             "Invalid value passed to rep_q_r2f devargs.\n");
5442                 return -EINVAL;
5443         }
5444
5445         vfr_bp->rep_q_r2f = rep_q_r2f;
5446         vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5447         PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5448
5449         return 0;
5450 }
5451
5452 static int
5453 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5454                             const char *value, void *opaque_arg)
5455 {
5456         struct bnxt_representor *vfr_bp = opaque_arg;
5457         unsigned long rep_q_f2r;
5458         char *end = NULL;
5459
5460         if (!value || !opaque_arg) {
5461                 PMD_DRV_LOG(ERR,
5462                             "Invalid parameter passed to rep_q_f2r "
5463                             "devargs.\n");
5464                 return -EINVAL;
5465         }
5466
5467         rep_q_f2r = strtoul(value, &end, 10);
5468         if (end == NULL || *end != '\0' ||
5469             (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5470                 PMD_DRV_LOG(ERR,
5471                             "Invalid parameter passed to rep_q_f2r "
5472                             "devargs.\n");
5473                 return -EINVAL;
5474         }
5475
5476         if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5477                 PMD_DRV_LOG(ERR,
5478                             "Invalid value passed to rep_q_f2r devargs.\n");
5479                 return -EINVAL;
5480         }
5481
5482         vfr_bp->rep_q_f2r = rep_q_f2r;
5483         vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5484         PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5485
5486         return 0;
5487 }
5488
5489 static int
5490 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5491                              const char *value, void *opaque_arg)
5492 {
5493         struct bnxt_representor *vfr_bp = opaque_arg;
5494         unsigned long rep_fc_r2f;
5495         char *end = NULL;
5496
5497         if (!value || !opaque_arg) {
5498                 PMD_DRV_LOG(ERR,
5499                             "Invalid parameter passed to rep_fc_r2f "
5500                             "devargs.\n");
5501                 return -EINVAL;
5502         }
5503
5504         rep_fc_r2f = strtoul(value, &end, 10);
5505         if (end == NULL || *end != '\0' ||
5506             (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5507                 PMD_DRV_LOG(ERR,
5508                             "Invalid parameter passed to rep_fc_r2f "
5509                             "devargs.\n");
5510                 return -EINVAL;
5511         }
5512
5513         if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5514                 PMD_DRV_LOG(ERR,
5515                             "Invalid value passed to rep_fc_r2f devargs.\n");
5516                 return -EINVAL;
5517         }
5518
5519         vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5520         vfr_bp->rep_fc_r2f = rep_fc_r2f;
5521         PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5522
5523         return 0;
5524 }
5525
5526 static int
5527 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5528                              const char *value, void *opaque_arg)
5529 {
5530         struct bnxt_representor *vfr_bp = opaque_arg;
5531         unsigned long rep_fc_f2r;
5532         char *end = NULL;
5533
5534         if (!value || !opaque_arg) {
5535                 PMD_DRV_LOG(ERR,
5536                             "Invalid parameter passed to rep_fc_f2r "
5537                             "devargs.\n");
5538                 return -EINVAL;
5539         }
5540
5541         rep_fc_f2r = strtoul(value, &end, 10);
5542         if (end == NULL || *end != '\0' ||
5543             (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5544                 PMD_DRV_LOG(ERR,
5545                             "Invalid parameter passed to rep_fc_f2r "
5546                             "devargs.\n");
5547                 return -EINVAL;
5548         }
5549
5550         if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5551                 PMD_DRV_LOG(ERR,
5552                             "Invalid value passed to rep_fc_f2r devargs.\n");
5553                 return -EINVAL;
5554         }
5555
5556         vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5557         vfr_bp->rep_fc_f2r = rep_fc_f2r;
5558         PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5559
5560         return 0;
5561 }
5562
5563 static int
5564 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5565 {
5566         struct rte_kvargs *kvlist;
5567         int ret;
5568
5569         if (devargs == NULL)
5570                 return 0;
5571
5572         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5573         if (kvlist == NULL)
5574                 return -EINVAL;
5575
5576         /*
5577          * Handler for "truflow" devarg.
5578          * Invoked as for ex: "-a 0000:00:0d.0,host-based-truflow=1"
5579          */
5580         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5581                                  bnxt_parse_devarg_truflow, bp);
5582         if (ret)
5583                 goto err;
5584
5585         /*
5586          * Handler for "flow_xstat" devarg.
5587          * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5588          */
5589         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5590                                  bnxt_parse_devarg_flow_xstat, bp);
5591         if (ret)
5592                 goto err;
5593
5594         /*
5595          * Handler for "max_num_kflows" devarg.
5596          * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5597          */
5598         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5599                                  bnxt_parse_devarg_max_num_kflows, bp);
5600         if (ret)
5601                 goto err;
5602
5603 err:
5604         rte_kvargs_free(kvlist);
5605         return ret;
5606 }
5607
5608 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5609 {
5610         int rc = 0;
5611
5612         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5613                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5614                 if (rc)
5615                         PMD_DRV_LOG(ERR,
5616                                     "Failed to alloc switch domain: %d\n", rc);
5617                 else
5618                         PMD_DRV_LOG(INFO,
5619                                     "Switch domain allocated %d\n",
5620                                     bp->switch_domain_id);
5621         }
5622
5623         return rc;
5624 }
5625
5626 /* Allocate and initialize various fields in bnxt struct that
5627  * need to be allocated/destroyed only once in the lifetime of the driver
5628  */
5629 static int bnxt_drv_init(struct rte_eth_dev *eth_dev)
5630 {
5631         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5632         struct bnxt *bp = eth_dev->data->dev_private;
5633         int rc = 0;
5634
5635         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5636
5637         if (bnxt_vf_pciid(pci_dev->id.device_id))
5638                 bp->flags |= BNXT_FLAG_VF;
5639
5640         if (bnxt_p5_device(pci_dev->id.device_id))
5641                 bp->flags |= BNXT_FLAG_CHIP_P5;
5642
5643         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5644             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5645             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5646             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5647                 bp->flags |= BNXT_FLAG_STINGRAY;
5648
5649         if (BNXT_TRUFLOW_EN(bp)) {
5650                 /* extra mbuf field is required to store CFA code from mark */
5651                 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5652                         .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5653                         .size = sizeof(bnxt_cfa_code_dynfield_t),
5654                         .align = __alignof__(bnxt_cfa_code_dynfield_t),
5655                 };
5656                 bnxt_cfa_code_dynfield_offset =
5657                         rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5658                 if (bnxt_cfa_code_dynfield_offset < 0) {
5659                         PMD_DRV_LOG(ERR,
5660                             "Failed to register mbuf field for TruFlow mark\n");
5661                         return -rte_errno;
5662                 }
5663         }
5664
5665         rc = bnxt_map_pci_bars(eth_dev);
5666         if (rc) {
5667                 PMD_DRV_LOG(ERR,
5668                             "Failed to initialize board rc: %x\n", rc);
5669                 return rc;
5670         }
5671
5672         rc = bnxt_alloc_pf_info(bp);
5673         if (rc)
5674                 return rc;
5675
5676         rc = bnxt_alloc_link_info(bp);
5677         if (rc)
5678                 return rc;
5679
5680         rc = bnxt_alloc_parent_info(bp);
5681         if (rc)
5682                 return rc;
5683
5684         rc = bnxt_alloc_hwrm_resources(bp);
5685         if (rc) {
5686                 PMD_DRV_LOG(ERR,
5687                             "Failed to allocate response buffer rc: %x\n", rc);
5688                 return rc;
5689         }
5690         rc = bnxt_alloc_leds_info(bp);
5691         if (rc)
5692                 return rc;
5693
5694         rc = bnxt_alloc_cos_queues(bp);
5695         if (rc)
5696                 return rc;
5697
5698         rc = bnxt_init_locks(bp);
5699         if (rc)
5700                 return rc;
5701
5702         rc = bnxt_alloc_switch_domain(bp);
5703         if (rc)
5704                 return rc;
5705
5706         return rc;
5707 }
5708
5709 static int
5710 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5711 {
5712         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5713         static int version_printed;
5714         struct bnxt *bp;
5715         int rc;
5716
5717         if (version_printed++ == 0)
5718                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5719
5720         eth_dev->dev_ops = &bnxt_dev_ops;
5721         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5722         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5723         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5724         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5725         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5726
5727         /*
5728          * For secondary processes, we don't initialise any further
5729          * as primary has already done this work.
5730          */
5731         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5732                 return 0;
5733
5734         rte_eth_copy_pci_info(eth_dev, pci_dev);
5735         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
5736
5737         bp = eth_dev->data->dev_private;
5738
5739         /* Parse dev arguments passed on when starting the DPDK application. */
5740         rc = bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5741         if (rc)
5742                 goto error_free;
5743
5744         rc = bnxt_drv_init(eth_dev);
5745         if (rc)
5746                 goto error_free;
5747
5748         rc = bnxt_init_resources(bp, false);
5749         if (rc)
5750                 goto error_free;
5751
5752         rc = bnxt_alloc_stats_mem(bp);
5753         if (rc)
5754                 goto error_free;
5755
5756         PMD_DRV_LOG(INFO,
5757                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5758                     pci_dev->mem_resource[0].phys_addr,
5759                     pci_dev->mem_resource[0].addr);
5760
5761         return 0;
5762
5763 error_free:
5764         bnxt_dev_uninit(eth_dev);
5765         return rc;
5766 }
5767
5768
5769 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5770 {
5771         if (!ctx)
5772                 return;
5773
5774         if (ctx->va)
5775                 rte_free(ctx->va);
5776
5777         ctx->va = NULL;
5778         ctx->dma = RTE_BAD_IOVA;
5779         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5780 }
5781
5782 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5783 {
5784         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5785                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5786                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
5787                                   bp->flow_stat->max_fc,
5788                                   false);
5789
5790         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5791                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5792                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
5793                                   bp->flow_stat->max_fc,
5794                                   false);
5795
5796         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5797                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5798         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5799
5800         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5801                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5802         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5803
5804         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5805                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5806         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5807
5808         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5809                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5810         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5811 }
5812
5813 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5814 {
5815         bnxt_unregister_fc_ctx_mem(bp);
5816
5817         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5818         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5819         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5820         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5821 }
5822
5823 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5824 {
5825         if (BNXT_FLOW_XSTATS_EN(bp))
5826                 bnxt_uninit_fc_ctx_mem(bp);
5827 }
5828
5829 static void
5830 bnxt_free_error_recovery_info(struct bnxt *bp)
5831 {
5832         rte_free(bp->recovery_info);
5833         bp->recovery_info = NULL;
5834         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5835 }
5836
5837 static int
5838 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5839 {
5840         int rc;
5841
5842         bnxt_free_int(bp);
5843         bnxt_free_mem(bp, reconfig_dev);
5844
5845         bnxt_hwrm_func_buf_unrgtr(bp);
5846         if (bp->pf != NULL) {
5847                 rte_free(bp->pf->vf_req_buf);
5848                 bp->pf->vf_req_buf = NULL;
5849         }
5850
5851         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5852         bp->flags &= ~BNXT_FLAG_REGISTERED;
5853         bnxt_free_ctx_mem(bp);
5854         if (!reconfig_dev) {
5855                 bnxt_free_hwrm_resources(bp);
5856                 bnxt_free_error_recovery_info(bp);
5857         }
5858
5859         bnxt_uninit_ctx_mem(bp);
5860
5861         bnxt_free_flow_stats_info(bp);
5862         if (bp->rep_info != NULL)
5863                 bnxt_free_switch_domain(bp);
5864         bnxt_free_rep_info(bp);
5865         rte_free(bp->ptp_cfg);
5866         bp->ptp_cfg = NULL;
5867         return rc;
5868 }
5869
5870 static int
5871 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5872 {
5873         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5874                 return -EPERM;
5875
5876         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5877
5878         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5879                 bnxt_dev_close_op(eth_dev);
5880
5881         return 0;
5882 }
5883
5884 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5885 {
5886         struct bnxt *bp = eth_dev->data->dev_private;
5887         struct rte_eth_dev *vf_rep_eth_dev;
5888         int ret = 0, i;
5889
5890         if (!bp)
5891                 return -EINVAL;
5892
5893         for (i = 0; i < bp->num_reps; i++) {
5894                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5895                 if (!vf_rep_eth_dev)
5896                         continue;
5897                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
5898                             vf_rep_eth_dev->data->port_id);
5899                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
5900         }
5901         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
5902                     eth_dev->data->port_id);
5903         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5904
5905         return ret;
5906 }
5907
5908 static void bnxt_free_rep_info(struct bnxt *bp)
5909 {
5910         rte_free(bp->rep_info);
5911         bp->rep_info = NULL;
5912         rte_free(bp->cfa_code_map);
5913         bp->cfa_code_map = NULL;
5914 }
5915
5916 static int bnxt_init_rep_info(struct bnxt *bp)
5917 {
5918         int i = 0, rc;
5919
5920         if (bp->rep_info)
5921                 return 0;
5922
5923         bp->rep_info = rte_zmalloc("bnxt_rep_info",
5924                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5925                                    0);
5926         if (!bp->rep_info) {
5927                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5928                 return -ENOMEM;
5929         }
5930         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5931                                        sizeof(*bp->cfa_code_map) *
5932                                        BNXT_MAX_CFA_CODE, 0);
5933         if (!bp->cfa_code_map) {
5934                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5935                 bnxt_free_rep_info(bp);
5936                 return -ENOMEM;
5937         }
5938
5939         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5940                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5941
5942         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5943         if (rc) {
5944                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5945                 bnxt_free_rep_info(bp);
5946                 return rc;
5947         }
5948
5949         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
5950         if (rc) {
5951                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
5952                 bnxt_free_rep_info(bp);
5953                 return rc;
5954         }
5955
5956         return rc;
5957 }
5958
5959 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5960                                struct rte_eth_devargs *eth_da,
5961                                struct rte_eth_dev *backing_eth_dev,
5962                                const char *dev_args)
5963 {
5964         struct rte_eth_dev *vf_rep_eth_dev;
5965         char name[RTE_ETH_NAME_MAX_LEN];
5966         struct bnxt *backing_bp;
5967         uint16_t num_rep;
5968         int i, ret = 0;
5969         struct rte_kvargs *kvlist = NULL;
5970
5971         if (eth_da->type == RTE_ETH_REPRESENTOR_NONE)
5972                 return 0;
5973         if (eth_da->type != RTE_ETH_REPRESENTOR_VF) {
5974                 PMD_DRV_LOG(ERR, "unsupported representor type %d\n",
5975                             eth_da->type);
5976                 return -ENOTSUP;
5977         }
5978         num_rep = eth_da->nb_representor_ports;
5979         if (num_rep > BNXT_MAX_VF_REPS) {
5980                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5981                             num_rep, BNXT_MAX_VF_REPS);
5982                 return -EINVAL;
5983         }
5984
5985         if (num_rep >= RTE_MAX_ETHPORTS) {
5986                 PMD_DRV_LOG(ERR,
5987                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
5988                             num_rep, RTE_MAX_ETHPORTS);
5989                 return -EINVAL;
5990         }
5991
5992         backing_bp = backing_eth_dev->data->dev_private;
5993
5994         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
5995                 PMD_DRV_LOG(ERR,
5996                             "Not a PF or trusted VF. No Representor support\n");
5997                 /* Returning an error is not an option.
5998                  * Applications are not handling this correctly
5999                  */
6000                 return 0;
6001         }
6002
6003         if (bnxt_init_rep_info(backing_bp))
6004                 return 0;
6005
6006         for (i = 0; i < num_rep; i++) {
6007                 struct bnxt_representor representor = {
6008                         .vf_id = eth_da->representor_ports[i],
6009                         .switch_domain_id = backing_bp->switch_domain_id,
6010                         .parent_dev = backing_eth_dev
6011                 };
6012
6013                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6014                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6015                                     representor.vf_id, BNXT_MAX_VF_REPS);
6016                         continue;
6017                 }
6018
6019                 /* representor port net_bdf_port */
6020                 snprintf(name, sizeof(name), "net_%s_representor_%d",
6021                          pci_dev->device.name, eth_da->representor_ports[i]);
6022
6023                 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
6024                 if (kvlist) {
6025                         /*
6026                          * Handler for "rep_is_pf" devarg.
6027                          * Invoked as for ex: "-a 000:00:0d.0,
6028                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6029                          */
6030                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
6031                                                  bnxt_parse_devarg_rep_is_pf,
6032                                                  (void *)&representor);
6033                         if (ret) {
6034                                 ret = -EINVAL;
6035                                 goto err;
6036                         }
6037                         /*
6038                          * Handler for "rep_based_pf" devarg.
6039                          * Invoked as for ex: "-a 000:00:0d.0,
6040                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6041                          */
6042                         ret = rte_kvargs_process(kvlist,
6043                                                  BNXT_DEVARG_REP_BASED_PF,
6044                                                  bnxt_parse_devarg_rep_based_pf,
6045                                                  (void *)&representor);
6046                         if (ret) {
6047                                 ret = -EINVAL;
6048                                 goto err;
6049                         }
6050                         /*
6051                          * Handler for "rep_based_pf" devarg.
6052                          * Invoked as for ex: "-a 000:00:0d.0,
6053                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6054                          */
6055                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
6056                                                  bnxt_parse_devarg_rep_q_r2f,
6057                                                  (void *)&representor);
6058                         if (ret) {
6059                                 ret = -EINVAL;
6060                                 goto err;
6061                         }
6062                         /*
6063                          * Handler for "rep_based_pf" devarg.
6064                          * Invoked as for ex: "-a 000:00:0d.0,
6065                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6066                          */
6067                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
6068                                                  bnxt_parse_devarg_rep_q_f2r,
6069                                                  (void *)&representor);
6070                         if (ret) {
6071                                 ret = -EINVAL;
6072                                 goto err;
6073                         }
6074                         /*
6075                          * Handler for "rep_based_pf" devarg.
6076                          * Invoked as for ex: "-a 000:00:0d.0,
6077                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6078                          */
6079                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
6080                                                  bnxt_parse_devarg_rep_fc_r2f,
6081                                                  (void *)&representor);
6082                         if (ret) {
6083                                 ret = -EINVAL;
6084                                 goto err;
6085                         }
6086                         /*
6087                          * Handler for "rep_based_pf" devarg.
6088                          * Invoked as for ex: "-a 000:00:0d.0,
6089                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6090                          */
6091                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
6092                                                  bnxt_parse_devarg_rep_fc_f2r,
6093                                                  (void *)&representor);
6094                         if (ret) {
6095                                 ret = -EINVAL;
6096                                 goto err;
6097                         }
6098                 }
6099
6100                 ret = rte_eth_dev_create(&pci_dev->device, name,
6101                                          sizeof(struct bnxt_representor),
6102                                          NULL, NULL,
6103                                          bnxt_representor_init,
6104                                          &representor);
6105                 if (ret) {
6106                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6107                                     "representor %s.", name);
6108                         goto err;
6109                 }
6110
6111                 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6112                 if (!vf_rep_eth_dev) {
6113                         PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6114                                     " for VF-Rep: %s.", name);
6115                         ret = -ENODEV;
6116                         goto err;
6117                 }
6118
6119                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6120                             backing_eth_dev->data->port_id);
6121                 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6122                                                          vf_rep_eth_dev;
6123                 backing_bp->num_reps++;
6124
6125         }
6126
6127         rte_kvargs_free(kvlist);
6128         return 0;
6129
6130 err:
6131         /* If num_rep > 1, then rollback already created
6132          * ports, since we'll be failing the probe anyway
6133          */
6134         if (num_rep > 1)
6135                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6136         rte_errno = -ret;
6137         rte_kvargs_free(kvlist);
6138
6139         return ret;
6140 }
6141
6142 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6143                           struct rte_pci_device *pci_dev)
6144 {
6145         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6146         struct rte_eth_dev *backing_eth_dev;
6147         uint16_t num_rep;
6148         int ret = 0;
6149
6150         if (pci_dev->device.devargs) {
6151                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6152                                             &eth_da);
6153                 if (ret)
6154                         return ret;
6155         }
6156
6157         num_rep = eth_da.nb_representor_ports;
6158         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6159                     num_rep);
6160
6161         /* We could come here after first level of probe is already invoked
6162          * as part of an application bringup(OVS-DPDK vswitchd), so first check
6163          * for already allocated eth_dev for the backing device (PF/Trusted VF)
6164          */
6165         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6166         if (backing_eth_dev == NULL) {
6167                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6168                                          sizeof(struct bnxt),
6169                                          eth_dev_pci_specific_init, pci_dev,
6170                                          bnxt_dev_init, NULL);
6171
6172                 if (ret || !num_rep)
6173                         return ret;
6174
6175                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6176         }
6177         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6178                     backing_eth_dev->data->port_id);
6179
6180         if (!num_rep)
6181                 return ret;
6182
6183         /* probe representor ports now */
6184         ret = bnxt_rep_port_probe(pci_dev, &eth_da, backing_eth_dev,
6185                                   pci_dev->device.devargs->args);
6186
6187         return ret;
6188 }
6189
6190 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6191 {
6192         struct rte_eth_dev *eth_dev;
6193
6194         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6195         if (!eth_dev)
6196                 return 0; /* Invoked typically only by OVS-DPDK, by the
6197                            * time it comes here the eth_dev is already
6198                            * deleted by rte_eth_dev_close(), so returning
6199                            * +ve value will at least help in proper cleanup
6200                            */
6201
6202         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6203         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6204                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6205                         return rte_eth_dev_destroy(eth_dev,
6206                                                    bnxt_representor_uninit);
6207                 else
6208                         return rte_eth_dev_destroy(eth_dev,
6209                                                    bnxt_dev_uninit);
6210         } else {
6211                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6212         }
6213 }
6214
6215 static struct rte_pci_driver bnxt_rte_pmd = {
6216         .id_table = bnxt_pci_id_map,
6217         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6218                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6219                                                   * and OVS-DPDK
6220                                                   */
6221         .probe = bnxt_pci_probe,
6222         .remove = bnxt_pci_remove,
6223 };
6224
6225 static bool
6226 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6227 {
6228         if (strcmp(dev->device->driver->name, drv->driver.name))
6229                 return false;
6230
6231         return true;
6232 }
6233
6234 bool is_bnxt_supported(struct rte_eth_dev *dev)
6235 {
6236         return is_device_supported(dev, &bnxt_rte_pmd);
6237 }
6238
6239 RTE_LOG_REGISTER_SUFFIX(bnxt_logtype_driver, driver, NOTICE);
6240 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6241 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6242 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");